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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM71-10159-2E
FR Family
32-BIT MICROCONTROLLER
MB91461
HARDWARE MANUAL
FR Family
32-BIT MICROCONTROLLER
MB91461
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
CONTENTS
■ Objectives and intended reader
MB91461 is Fujitsu Microelectronics general-purpose 32-bit RISC microcontrollers designed for
embedded control applications on consumer devices and other equipment that require high-speed real-time
processing. These microcontrollers use FR60, which is compatible with the FR family, as their CPU.
This series incorporates a built-in LIN-UART and CAN controller.
Low-power consumption implementation by providing shut-down mode as a one of low-power
consumption mode.
Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU MICRO
ELECTRONICS Limited.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Organization of this manual
This manual consists of the following 24 chapters and appendix.
CHAPTER 1 OVERVIEW
This chapter explains the basic information such as features, block diagram and overview of MB91461.
CHAPTER 2 HANDLING DEVICES
This chapter describes precautions on handling FR family devices.
CHAPTER 3 CPU
This chapter describes FR family CPU core architecture, specifications and instructions.
CHAPTER 4 CONTROL BLOCK
This chapter describes the Control Block.
CHAPTER 5 INSTRUCTION CACHE
This chapter describes the instruction cache.
CHAPTER 6 LOW-POWER CONSUMPTION MODE
This chapter describes functions and operations of the low-power consumption modes.
CHAPTER 7 HARDWARE WATCHDOG TIMER
This chapter explains the functions of hardware watchdog timer.
CHAPTER 8 EXTERNAL BUS INTERFACE
This chapter explains each function of the external bus interface.
CHAPTER 9 I/O PORT
This chapter describes I/O ports and the configuration and functions of the registers.
CHAPTER 10 INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt controller, configuration and functions of the
registers, and interrupt controller operation.
CHAPTER 11 EXTERNAL INTERRUPT CONTROLLER
This chapter describes the overview of the external interrupt controller, configuration and functions of the
registers and external interrupt controller operation.
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CHAPTER 12 REALOS RELATED HARDWARE
This chapter describes overview, configurations/functions of registers, and operations of REALOS.
CHAPTER 13 DMAC (DMA CONTROLLER)
This chapter describes the overview of the DMAC, configuration and functions of the registers, and
DMAC operation.
CHAPTER 14 CAN CONTROLLER
This chapter describes the functions and operations of the CAN controller.
CHAPTER 15 LIN-UART
This chapter describes functions and operations of the LIN-compatible LIN-UART.
CHAPTER 16 I2C INTERFACE
This chapter describes overview, register configuration/function, and operation of the I2C interface.
CHAPTER 17 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit
reload timer operation.
CHAPTER 18 16-BIT FREE-RUN TIMER
This chapter describes the functions and operation of the 16-bit free-run timer.
CHAPTER 19 INPUT CAPTURE
This chapter describes the functions and operation of the input capture.
CHAPTER 20 OUTPUT COMPARE UNIT
This chapter describes the functions and operation of the output compare unit.
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
This chapter describes the registers, function, and operation of the PPG.
CHAPTER 22 REAL TIME CLOCK
This chapter describes the register structure and functions, and the operation of RTC module for the real
time clock.
CHAPTER 23 A/D CONVERTER
This chapter describes the overview, register configuration and function, and operation of the A/D
converter.
CHAPTER 24 FLASH MEMORY SUPPORT
This chapter describes the support of the on-board flash memory serial programming.
APPENDIX
The appendix describes pin states in each CPU state, notes on using the little-endian areas, a list of FR
family instructions, and notes on using MB91461.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for
the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out
of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use
of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is
secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,
submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2007-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
CHAPTER 2
2.1
2.2
HANDLING DEVICES ................................................................................ 19
Precautions on Handling Devices ..................................................................................................... 20
Precautions for Use .......................................................................................................................... 24
CHAPTER 3
3.1
3.2
3.2.1
3.3
3.3.1
3.3.2
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
OVERVIEW ................................................................................................... 1
Overview ............................................................................................................................................. 2
Block Diagram .................................................................................................................................... 5
Package Dimensions .......................................................................................................................... 6
Pin Assignment Diagram .................................................................................................................... 7
Pin Descriptions .................................................................................................................................. 9
I/O Circuit Types ............................................................................................................................... 15
CPU ............................................................................................................ 27
Memory Space ..................................................................................................................................
Internal Architecture ..........................................................................................................................
Overview of Instructions ..............................................................................................................
Programming Model .........................................................................................................................
General-purpose Registers .........................................................................................................
Dedicated Registers ....................................................................................................................
Data Structure ...................................................................................................................................
Memory Map .....................................................................................................................................
Branch Instructions ...........................................................................................................................
Branch Instructions with a Delay Slot ..........................................................................................
Branch Instructions without a Delay Slot .....................................................................................
EIT (Exception, Interrupt, and Trap) .................................................................................................
EIT Interrupt Levels .....................................................................................................................
Interrupt Control Register (ICR) ...................................................................................................
System Stack Pointer (SSP) ........................................................................................................
Table Base Register (TBR) .........................................................................................................
Multiple EIT Processing ...............................................................................................................
EIT Operation ..............................................................................................................................
CHAPTER 4
28
29
33
35
36
37
44
46
47
48
50
51
52
54
55
56
57
59
CONTROL BLOCK .................................................................................... 63
4.1
Operating Modes ..............................................................................................................................
4.1.1
Bus Mode ....................................................................................................................................
4.1.2
Mode Setting ...............................................................................................................................
4.2
Reset (Device Initialization) ..............................................................................................................
4.2.1
Reset Level ..................................................................................................................................
4.2.2
Reset Source ...............................................................................................................................
4.2.3
Reset Sequence ..........................................................................................................................
4.2.4
Oscillation Stabilization Wait Time ..............................................................................................
4.2.5
Reset Operation Modes ...............................................................................................................
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64
65
66
69
70
71
73
74
76
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.4
4.4.1
4.4.2
4.5
4.5.1
4.6
Clock Generation Control ................................................................................................................. 77
PLL Control .................................................................................................................................. 78
Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 79
Clock Distribution ......................................................................................................................... 81
Clock Division .............................................................................................................................. 83
Block Diagram of Clock Generation Control Block ...................................................................... 84
Registers in the Clock Generation Control Block ........................................................................ 85
Peripheral Circuits in the Clock Control Block ........................................................................... 104
PLL Interface .................................................................................................................................. 107
Registers for the PLL Interface .................................................................................................. 108
Examples of PLL Multiply Rate Setting ..................................................................................... 115
Device State Control ....................................................................................................................... 119
Device States and Transitions ................................................................................................... 120
Interval Timer .................................................................................................................................. 124
CHAPTER 5
5.1
5.2
5.3
5.4
CHAPTER 6
6.1
6.2
6.3
6.4
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.3
8.4
8.4.1
144
145
147
149
HARDWARE WATCHDOG TIMER .......................................................... 155
Overview of Hardware Watchdog Timer .........................................................................................
Configuration of Hardware Watchdog Timer ..................................................................................
Hardware Watchdog Timer Register ..............................................................................................
Function of Hardware Watchdog Timer ..........................................................................................
Notes on Using Hardware Watchdog Timer ...................................................................................
CHAPTER 8
132
135
139
141
LOW-POWER CONSUMPTION MODE ................................................... 143
Overview of Low-Power Consumption Mode ..................................................................................
Sleep Mode .....................................................................................................................................
Stop Mode ......................................................................................................................................
Shut-down Mode .............................................................................................................................
CHAPTER 7
7.1
7.2
7.3
7.4
7.5
INSTRUCTION CACHE ............................................................................ 131
Overview .........................................................................................................................................
Control Register ..............................................................................................................................
Cache State And Various Operating Modes ...................................................................................
Setting Up the Instruction Cache before Use .................................................................................
156
157
158
160
162
EXTERNAL BUS INTERFACE ................................................................ 163
Features of External Bus Interface .................................................................................................
External Bus Interface Registers ....................................................................................................
Area Select Register (ASR0 to ASR4) ......................................................................................
Area Configuration Register (ACR0 to ACR4) ...........................................................................
Area Wait Register (AWR0 to AWR4) .......................................................................................
I/O Wait Register for DMAC (IOWR0 to IOWR2) ......................................................................
Chip Select Enable Register (CSER) ........................................................................................
CacHe Enable Register (CHER) ...............................................................................................
Terminal and Timing Control Register (TCR) ............................................................................
Chip Select Area .............................................................................................................................
Endian and Bus Access ..................................................................................................................
Big Endian Bus Access .............................................................................................................
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164
167
168
169
175
181
184
185
186
188
190
191
8.4.2
8.4.3
8.5
8.6
8.7
8.8
Little Endian Bus Access ...........................................................................................................
Comparison Of External Accesses In Big Endian and Little Endian ..........................................
Normal Bus Interface ......................................................................................................................
Address/Data Multiplex Interface ....................................................................................................
DMA Access ...................................................................................................................................
Procedure for Setting Registers ......................................................................................................
CHAPTER 9
9.1
9.2
9.3
9.4
9.5
196
201
205
213
217
220
I/O PORT .................................................................................................. 221
Overview of I/O Ports ......................................................................................................................
I/O Port Data Register ....................................................................................................................
Setting of Port Function Register ....................................................................................................
Selection of Pin Input Level ............................................................................................................
Pull-up and Pull-down Control Register ..........................................................................................
222
226
228
242
243
CHAPTER 10 INTERRUPT CONTROLLER ................................................................... 245
10.1 Overview of the Interrupt Controller ................................................................................................
10.2 Interrupt Controller Registers ..........................................................................................................
10.2.1 Interrupt Control Register (ICR) .................................................................................................
10.2.2 HRCL (Hold Request Cancellation Request Register) ..............................................................
10.3 Interrupt Controller Operation .........................................................................................................
246
250
251
252
253
CHAPTER 11 EXTERNAL INTERRUPT CONTROLLER ............................................... 263
11.1 Overview of the External Interrupt Controller ..................................................................................
11.2 External Interrupt Controller Registers ...........................................................................................
11.2.1 External Interrupt Enable Register (ENIR) ................................................................................
11.2.2 External Interrupt Factor Register (EIRR) .................................................................................
11.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................
11.3 Operation of the External Interrupt Controller .................................................................................
264
266
267
268
269
270
CHAPTER 12 REALOS RELATED HARDWARE ........................................................... 275
12.1 Delayed Interrupt Module ...............................................................................................................
12.1.1 Overview of Delayed Interrupt Module ......................................................................................
12.1.2 Delayed Interrupt Module Register ............................................................................................
12.1.3 Operation of the Delayed Interrupt Module ...............................................................................
12.2 Bit Search Module ..........................................................................................................................
12.2.1 Overview of Bit Search Module .................................................................................................
12.2.2 Bit Search Module Registers .....................................................................................................
12.2.3 Operation of the Bit Search Module ..........................................................................................
276
277
278
279
280
281
282
284
CHAPTER 13 DMAC (DMA CONTROLLER) .................................................................. 287
13.1 Overview of DMAC (DMA Controller) ............................................................................................. 288
13.2 Detailed Explanation of the DMAC (DMA Controller) Registers ..................................................... 291
13.2.1 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers A ................................................. 292
13.2.2 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers B ................................................. 296
13.2.3 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Transfer Destination Address Setting Registers
.................................................................................................................................................... 302
13.2.4 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC All-Channel Control Register ................................... 304
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13.3 Explanation of the DMAC (DMA Controller) Operation ...................................................................
13.3.1 Operational Overview of DMAC (DMA Controller) ....................................................................
13.3.2 Transfer Request Setting ...........................................................................................................
13.3.3 Transfer Sequence ....................................................................................................................
13.3.4 DMA Transfer in General ...........................................................................................................
13.3.5 Addressing Mode .......................................................................................................................
13.3.6 Data Types ................................................................................................................................
13.3.7 Transfer Number Control ...........................................................................................................
13.3.8 CPU Control ..............................................................................................................................
13.3.9 Starting Operation .....................................................................................................................
13.3.10 Transfer Request Acceptance and Transfer ..............................................................................
13.3.11 Clearing Peripheral Interrupts by DMA ......................................................................................
13.3.12 Temporary Stop .........................................................................................................................
13.3.13 Operation End/Stop ...................................................................................................................
13.3.14 Error Stop ..................................................................................................................................
13.3.15 DMAC Interrupt Control .............................................................................................................
13.3.16 DMA Transfer during Sleep Mode .............................................................................................
13.3.17 Channel Selection and Control ..................................................................................................
13.4 Operational Flow of DMAC (DMA Controller) .................................................................................
13.5 Data Path of DMAC (DMA Controller) ............................................................................................
306
307
309
310
312
314
315
316
317
318
319
320
321
322
323
324
325
326
328
330
CHAPTER 14 CAN CONTROLLER ................................................................................ 333
14.1 Features of CAN .............................................................................................................................
14.2 CAN Block Diagram ........................................................................................................................
14.3 CAN Registers ................................................................................................................................
14.4 CAN Register Functions .................................................................................................................
14.4.1 General Control Register ...........................................................................................................
14.4.1.1 CAN Control Register (CTRLR) ..............................................................................................
14.4.1.2 CAN Status Register (STATR) ...............................................................................................
14.4.1.3 CAN Error Counter (ERRCNT) ...............................................................................................
14.4.1.4 CAN Bit Timing Register (BTR) ..............................................................................................
14.4.1.5 CAN Interrupt Register (INTR) ...............................................................................................
14.4.1.6 CAN Test Register (TESTR) ..................................................................................................
14.4.1.7 CAN Prescaler Expansion Register (BRPER) ........................................................................
14.4.2 Message Interface Register .......................................................................................................
14.4.2.1 IFx Command Request Register (IFxCREQ) .........................................................................
14.4.2.2 IFx Command Mask Register (IFxCMSK) ..............................................................................
14.4.2.3 IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) .......................................................................
14.4.2.4 IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2) ................................................................
14.4.2.5 IFx Message Control Register (IFxMCTR) .............................................................................
14.4.2.6 IFx Data Registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) .......................
14.4.3 Message Object .........................................................................................................................
14.4.4 Message Handler Register ........................................................................................................
14.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2) ..................................................
14.4.4.2 CAN Data Update Register (NEWDT1, NEWDT2) .................................................................
14.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2) .........................................................
14.4.4.4 CAN Message Validation Register (MSGVAL1, MSGVAL2) ..................................................
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334
335
336
342
343
344
347
350
351
353
355
357
358
359
362
367
368
369
370
371
377
378
380
382
384
14.4.5 CAN Prescaler Register (CANPRE) ..........................................................................................
14.5 CAN Controller Functions ...............................................................................................................
14.5.1 Message Object .........................................................................................................................
14.5.2 Message Transmission Operation .............................................................................................
14.5.3 Message Reception Operation ..................................................................................................
14.5.4 FIFO Buffer Function .................................................................................................................
14.5.5 Interrupt Function ......................................................................................................................
14.5.6 Bit Timing ...................................................................................................................................
14.5.7 Test Mode ..................................................................................................................................
14.5.8 Software Initialization .................................................................................................................
14.5.9 CAN Clock Prescaler .................................................................................................................
386
388
389
391
393
397
399
401
404
409
410
CHAPTER 15 LIN-UART ................................................................................................. 413
15.1 Overview of LIN-UART ...................................................................................................................
15.2 Configuration of LIN-UART .............................................................................................................
15.3 LIN-UART Registers .......................................................................................................................
15.3.1 Serial Control Register (SCR) ...................................................................................................
15.3.2 Serial Mode Register (SMR) ......................................................................................................
15.3.3 Serial Status Register (SSR) .....................................................................................................
15.3.4 Transmission/Reception Data Registers (RDR/TDR) ................................................................
15.3.5 Extended Status/Control Register (ESCR) ................................................................................
15.3.6 Extended Communication Control Register (ECCR) .................................................................
15.3.7 Baud Rate/Reload Counter Register (BGR) ..............................................................................
15.4 LIN-UART Interrupts .......................................................................................................................
15.4.1 Reception Interrupt Generation and Flag Set Timing ................................................................
15.4.2 Transmission Interrupt Generation and Flag Timing .................................................................
15.5 LIN-UART Baud Rate Setting .........................................................................................................
15.5.1 Baud Rate Setting .....................................................................................................................
15.5.2 Restarting Reload Counter ........................................................................................................
15.6 LIN-UART Operations .....................................................................................................................
15.6.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................
15.6.2 Operation in Synchronous Mode (Operation Mode 2) ...............................................................
15.6.3 Operation with LIN Function (Operation Mode 3) ......................................................................
15.6.4 Direct Access to Serial Pins ......................................................................................................
15.6.5 Bidirectional Communication Function (Normal Mode) .............................................................
15.6.6 Master/Slave Communication Function (Multiprocessor Mode) ................................................
15.6.7 LIN Communication Function ....................................................................................................
15.6.8 Sample Flowchart for LIN-UART in LIN Communication Mode (Operation Mode 3) .................
15.7 Notes on Using LIN-UART ..............................................................................................................
414
417
422
424
427
430
433
435
438
441
443
447
449
451
453
456
458
460
462
465
469
470
471
474
475
478
CHAPTER 16 I2C INTERFACE ....................................................................................... 481
16.1 I2C Interface Overview ....................................................................................................................
16.2 I2C Interface Register .....................................................................................................................
16.2.1 Bus Status Register (IBSR) .......................................................................................................
16.2.2 Bus Control Register (IBCR) .....................................................................................................
16.2.3 Clock Control Register (ICCR) ..................................................................................................
16.2.4 10-bit Slave Address Register (ITBA) ........................................................................................
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482
487
488
492
500
502
16.2.5 10-bit Slave Address Mask Register (ITMK) .............................................................................
16.2.6 7-bit Slave Address Register (ISBA) .........................................................................................
16.2.7 7-bit Slave Address Mask Register (ISMK) ...............................................................................
16.2.8 Data Register (IDAR) .................................................................................................................
16.3 Explanation of I2C Interface Operation ...........................................................................................
16.4 Operation Flowchart .......................................................................................................................
503
505
506
507
508
513
CHAPTER 17 16-BIT RELOAD TIMER ........................................................................... 517
17.1 Overview of the 16-bit Reload Timer ..............................................................................................
17.2 16-bit Reload Timer Registers ........................................................................................................
17.2.1 Control Status Register (TMCSR) .............................................................................................
17.2.2 16-bit Timer Register (TMR) ......................................................................................................
17.2.3 16-bit Reload Register (TMRLR) ...............................................................................................
17.3 16-bit Reload Timer Operation .......................................................................................................
518
519
520
525
526
527
CHAPTER 18 16-BIT FREE-RUN TIMER ....................................................................... 531
18.1 Overview of 16-bit Free-run Timer ..................................................................................................
18.2 16-bit Free-run Timer Registers ......................................................................................................
18.2.1 Timer Data Register (TCDT) .....................................................................................................
18.2.2 Timer Control Status Register (TCCS) ......................................................................................
18.3 16-bit Free-run Timer Operation .....................................................................................................
18.4 Notes on Using the 16-bit Free-run Timer ......................................................................................
532
533
534
535
538
540
CHAPTER 19 INPUT CAPTURE ..................................................................................... 541
19.1 Overview of the Input Capture ........................................................................................................
19.2 Input Capture Registers ..................................................................................................................
19.2.1 Input Capture Register (IPCP0 to IPCP3) .................................................................................
19.2.2 Input Capture Control Register (ICS01,ICS23) .........................................................................
19.3 Input Capture Operation .................................................................................................................
542
543
544
545
547
CHAPTER 20 OUTPUT COMPARE UNIT ...................................................................... 549
20.1 Overview of the Output Compare Unit ............................................................................................
20.2 Output Compare Unit Registers ......................................................................................................
20.2.1 Compare Register (OCCP0 to OCCP3) ....................................................................................
20.2.2 Control Register (OCS01,OCS23) .............................................................................................
20.3 Output Compare Unit Operation .....................................................................................................
550
551
552
553
556
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR) .................................. 561
21.1 Overview of PPG ............................................................................................................................
21.2 PPG Registers ................................................................................................................................
21.2.1 Control Status Registers (PCNH, PCNL) ..................................................................................
21.2.2 PPG Cycle Setting Register (PCSR) .........................................................................................
21.2.3 PPG Duty Setting Register (PDUT) ...........................................................................................
21.2.4 PPG Timer Register (PTMR) .....................................................................................................
21.2.5 General Control Register 10 (GCN10) ......................................................................................
21.2.6 General Control Register 11 (GCN11) ......................................................................................
21.2.7 General Control Register 2 (GCN20,GCN21) ...........................................................................
x
562
565
568
572
573
574
575
578
581
21.3 PPG Operation ...............................................................................................................................
21.3.1 PWM Operation .........................................................................................................................
21.3.2 One-Shot Operation ..................................................................................................................
21.3.3 Interrupts ...................................................................................................................................
21.3.4 All "L" and All "H" PPG Outputs .................................................................................................
21.3.5 Activation of Multiple Channels .................................................................................................
582
583
585
587
588
589
CHAPTER 22 REAL TIME CLOCK ................................................................................. 591
22.1
22.2
22.3
Register Configuration of Real Time Clock ..................................................................................... 592
Block Diagram of Real Time Clock ................................................................................................. 594
Register Details of Real Time Clock ............................................................................................... 595
CHAPTER 23 A/D CONVERTER .................................................................................... 601
23.1 Overview of A/D Converter .............................................................................................................
23.2 Block Diagram of A/D Converter .....................................................................................................
23.3 Registers of A/D Converter .............................................................................................................
23.3.1 Analog Input Enable Register (ADER) ......................................................................................
23.3.2 A/D Control Status Register (ADCS) .........................................................................................
23.3.3 Data Register (ADCR1, ADCR0) ...............................................................................................
23.3.4 Conversion Time Setting Register (ADCT) ................................................................................
23.3.5 Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH) ..................
23.4 Operation of A/D Converter ............................................................................................................
602
603
604
606
607
612
613
615
617
CHAPTER 24 FLASH MEMORY SUPPORT .................................................................. 619
24.1
Flash Memory Serial Programming ................................................................................................ 620
APPENDIX ......................................................................................................................... 621
APPENDIX A Instruction Lists ....................................................................................................................
A.1 Meaning of Symbols .......................................................................................................................
A.2 Instruction Lists ..............................................................................................................................
A.3 Instruction Maps .............................................................................................................................
A.4 Instruction Maps of Instruction Format TYPE-E .............................................................................
APPENDIX B I/O Map ................................................................................................................................
APPENDIX C Interrupt Vector ....................................................................................................................
APPENDIX D DMA Transfer Request Source ............................................................................................
APPENDIX E Pin State at Serial Programming Mode ................................................................................
622
623
630
639
640
641
662
668
669
INDEX................................................................................................................................... 675
xi
xii
Main changes in this edition
Page
Changes (For details, refer to main body.)
Changed the document code.
CM44-10133-1E → CM71-10159-2E
-
2
-
CHAPTER 1 OVERVIEW
1.1 Overview
■ Features
Changed the document name.
MB91461 MB91F467R HARDWARE MANUAL
→
MB91461 HARDWARE MANUAL
Corrected the comments in "● FR60 CPU".
• Source oscillation 20MHz/4MHz → Source oscillation 4 MHz
• multiply by 4/20 → multiply by 20
Corrected the comments in "● Built-in Peripheral Functions".
F-bus RAM → ID-RAM
4
6
22
■ Product Lineup
Corrected the comments in Table 1.1-1.
F-bus RAM → ID-RAM
1.3 Package Dimensions
Corrected Figure 1.3-1.
120-pin plastic LQFP → 176-pin plastic LQFP
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling Devices
Corrected the comments in "■ External Bus Setting".
400 MHz → 40 MHz
Added "■ Serial communication".
CHAPTER 3 CPU
Corrected the chapter title.
CHAPTER 3 CPU AND CONTROL BLOCK → CPU
28
CHAPTER 3 CPU
3.1 Memory Space
■ Memory Map
Corrected the Figure 3.1-1.
F-bus RAM → ID-RAM
60
CHAPTER 3 CPU
3.7.6 EIT Operation
■ Operation of User Interrupts and NMI
Corrected an explanation.
OR CCR, ST ILM, MOV Ri, or PS → "OR CCR", "ST ILM", or
"MOV Ri, PS"
CHAPTER 4 CONTROL BLOCK
Changed the composition of the chapter.
"3.9 Operating Modes" to "3.14 Interval Timer".
→
CHAPTER 4 CONTROL BLOCK
CHAPTER 4 CONTROL BLOCK
4.1.1 Bus Mode
■ Bus Mode 0 (Single Chip Mode)
Corrected the comments.
F-bus RAM → ID-RAM
4.1.2 Mode Setting
■ Mode Register (MODR)
Corrected the comments of "[bit2] ROMA (built-in ROM enable
bit)".
F-bus RAM → ID-RAM
CHAPTER 5 CLOCK MODULATOR
Corrected "CHAPTER 5 CLOCK MODULATOR".
27
63
65
67
-
xiii
Page
Changes (For details, refer to main body.)
CHAPTER 5 INSTRUCTION CACHE
Changed the composition of the chapter.
3.3 Instruction Cache
→
CHAPTER 5 INSTRUCTION CACHE
CHAPTER 6 LOW-POWER
CONSUMPTION MODE
6.4 Shut-down Mode
Corrected the comments.
F-bus RAM → ID-RAM
152
● Transition to Shut-down Mode
Corrected the coments.
F-bus RAM → ID-RAM
154
● Return from Shut-down Mode
Added the comments in "Note".
-
CHAPTER 6 SUB OSCILLATION
STABILIZATION WAIT TIMER
Deleted "CHAPTER 6 SUB OSCILLATION STABILIZATION
WAIT TIMER".
-
CHAPTER 8 MEMORY
CONTROLLER
Deleted "CHAPTER 8 MEMORY CONTROLLER".
CHAPTER 8 EXTERNAL BUS
INTERFACE
8.4.1 Endian and Bus Access
Changed the comments in "■ External Bus Access".
and are "10B" if "00B" or "01B"
→
and are 10B if 10B or 11B
CHAPTER 9 I/O PORT
9.1 Overview of I/O Ports
■ General Specification of Ports
Corrected an explanation.
On MB91461, → On MB91V460,
228
CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
Deleted "■ Port 00", "■ Port 01", "■ Port 05", "■ Port 06",
"■ Port 07", "■ Port 08", "■ Port 09", "■ Port 10", "■ Port 11",
and "■ Port 13".
233
CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
■ Port 19
Corrected the Figure 9.3-6.
• EPFR19_1 → −
• EPFR19_0 → −
131
149
193
224
Corrected the Table 9.3-6.
X0B → 0XB
262
CHAPTER 10 INTERRUPT
CONTROLLER
10.3 Interrupt Controller Operation
Corrected the title of Figure 10.3-3.
INTC-3 Interrupt Level → Interrupt Level
290
CHAPTER 13 DMAC
(DMA CONTROLLER)
13.1 Overview of DMAC
(DMA Controller)
Corrected the Figure 13.1-2.
DSS[3:0] → DSS[2:0]
CHAPTER 15 LIN-UART
15.3.1 Serial Control Register (SCR)
■ Serial Control Register (SCR)
Added "Note" under "[bit10] CRE: Reception error flag clear bit".
426
CHAPTER 18 I2C INTERFACE
16.2.2 Bus Control Register (IBCR)
■ Bus Control Register (IBCR)
Corrected the comments under the Figure 18.2-4.
3-bit data transmission time = {1 / (100 ¥ 103)} ¥ 3 = 30 ms
→
3-bit data transmission time = {1 / (100 ✕ 103)} ✕ 3 = 30 ms
498
xiv
Page
-
619
Changes (For details, refer to main body.)
CHAPTER 26 SUB CLOCK
CALIBRATION UNIT
Deleted "CHAPTER 26 SUB CLOCK CALIBRATION UNIT".
CHAPTER 24 FLASH MEMORY
SUPPORT
Changed the chapter title.
FLASH MEMOEY
→
FLASH MEMORY SUPPORT
24.1 Flash Memory Serial Programming
Changed the content.
27.4 Notes on Using Flash Memory
→
24.1 Flash Memory Serial Programming
CHAPTER 28 FLASH SECURITY
Deleted "CHAPTER 28 FLASH SECURITY".
620
-
The vertical lines marked in the left side of the page show the changes.
xv
xvi
CHAPTER 1
OVERVIEW
This chapter explains the basic information such as
features, block diagram and overview of MB91461.
1.1 Overview
1.2 Block Diagram
1.3 Package Dimensions
1.4 Pin Assignment Diagram
1.5 Pin Descriptions
1.6 I/O Circuit Types
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
1
CHAPTER 1 OVERVIEW
1.1 Overview
1.1
MB91461
Overview
MB91461 is Fujitsu’s general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed real-time processing of
consumer appliances. This microcontroller uses FR60 as its CPU, compatible with other
products in the FR family.
MB91461 incorporate a built-in LIN-UART and CAN controller.
■ Features
● FR60 CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operation frequency: 80 MHz (Source oscillation 4 MHz, multiply by 20 (PLL clock
multiplication method))
• 16-bit fixed length instructions (basic instructions)
• Instruction execution speed: One instruction per cycle
• Memory-to-memory transfer instructions, bit processing instructions, barrel shift instructions, etc.:
Instructions adapted for embedded applications
• Function entry/exit instructions, multiple-register load/store instructions:
Instructions supporting C language
• Register interlock function: Easier assembler coding enabled
• Built-in multiplier supported at the instruction level
1. Signed 32-bit multiplication: 5 cycles
2. Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS save): 6 cycles (16 levels)
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction compatibility with the FR family
● Built-in Peripheral Functions
• Built-in ROM capacity
Instruction cache 4 Kbytes
ID-RAM (Used as both instruction and data RAM) 64 Kbytes
• General-purpose ports: up to 72 ports
• DMAC (DMA Controller)
Capable of simultaneous operation of up to 5 channels (one channel for external-to-external operation)
Three transfer sources (external pins, internal peripheral, software)
Activation sources are selectable by software.
Addressing using 32-bit full addressing mode (increment, decrement, fixed)
Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
Supporting flyby transfers (between external I/O and memories)
Selectable transfer data size: 8, 16, or 32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (sequential comparison type)
10-bit resolution: 13 channels
Conversion time: 1 μs (when peripheral macro operation clock is operated at 16.67 MHz)
2
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.1 Overview
MB91461
• External interrupt input: 16 channels
Shared with the RX pins of CAN0 and CAN1
• Bit search module (for REALOS)
Search function to locate the position of the first bit that changes from "1" to "0" in one word, from the
MSB (high-order bit)
• LIN-UART (full duplex double buffer type): 7 channels
Synchronous/asynchronous clock operations selectable
Sync-break detection
Dedicated built-in baud-rate generator
• I2C bus interface (supporting 400 kbps): 3 channels
3ch master/slave sending and receiving
Arbitration and clock synchronization
• CAN controller (C-CAN): 2 channels
Transfer speed: up to 1 Mbps
32 send/receive message buffer
• 16-bit PPG timer: 8 channels
• 16-bit reload timer: 5 channels
• 16-bit free-run timer: 4 channels (one channel each for ICU and OCU)
• Input capture: 4 channels (linked to the free-run timer)
• Output compare: 4 channels (linked to the free-run timer)
• Watchdog timer
Watchdog reset output pins available
• Real time clock
• Power saving modes: sleep mode, stop mode, shutdown mode
● Package: LQFP-176 (FPT-176P-M07)
● CMOS 0.18μm technology
● Power supply voltage: 3.3V/5V
(Internal logic by a step-down circuit: 1.8V, partially 5.0V pressure-resistant)
● Operating temperatures: −40°C to +85°C
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
3
CHAPTER 1 OVERVIEW
1.1 Overview
MB91461
■ Product Lineup
Table 1.1-1 shows the MB91461 product lineup.
Table 1.1-1 Configuration List for MB91461
Item
4
MB91461
Installed channel
ROM/Flash capacity
⎯
⎯
Instruction cache
4 Kbytes
⎯
Direct Map Cache
⎯
⎯
D-bus RAM capacity
(for data only)
⎯
⎯
ID-RAM capacity
(for both instruction and data)
64 Kbytes
⎯
External interrupt
16ch
INT0 to INT15
DMAC
5ch
ch.0 to ch.4
A/D Converter
13ch
ch.0 to ch.12
LIN-UART
7ch
ch.0 to ch.6
I2C
3ch
ch.0 to ch.2
CAN
2ch(32msg)
ch.0,ch.1
16-bit Programmable Pulse Generator
8ch
ch.0 to ch.7
16-bit Reload Timer
5ch
ch.0 to ch.3,ch.7
16-bit Free-run Timer
4ch
ch.0 to ch.3
Input Capture Unit
4ch
ch.0 to ch.3
Output Compare Unit
4ch
ch.0 to ch.3
Real Time Clock
Yes
⎯
32 kHz Sub clock
⎯
⎯
External bus
Address 24-bit
Data 16-bit
⎯
Others
ROM less device
⎯
Debug Support Unit
DSU4
⎯
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.2 Block Diagram
MB91461
1.2
Block Diagram
Figure 1.2-1 shows the block diagram of the MB91461.
■ Block Diagram
Figure 1.2-1 Block Diagram of the MB91461
TRSTX
BREAK
ICS0 to ICS2
ICD0 to ICD3
DSU
FR60 CPU Core
(Debug Support)
Bit Search
I-Cache
CAN
(2ch)
I-bus
32
RAM
D-bus
32
RX0, RX1
TX0, TX1
32 to 16
Bus Adapter
Bus
Converter
SYSCLK
ASX
RDX
WR0X
WR1X
Ext.bus-IF
BRQ
BGRNTX
CS0X to CS4X
A23 to A00
D31 to D16
DREQ0
DACK0X
DEOP0
IOWRX
IORDX
DMAC (5ch)
R-bus
16
Interrupt
Controller
Clock Control
External
Interrupt 16ch
TRG0 to TRG3
PPG0 to PPG7
PPG
(8ch)
TIN0 to TIN3
TOT0 to TOT3
Reload
Timer (5ch)
FRCK0 to FRCK3
ICU0 to ICU3
Free-run
Timer (4ch)
PORT
interface
NMIX
INT0 to INT15
PORT
LIN-UART(7ch)
(including BRG)
SIN0 to SIN6
SOT0 to SOT6
SCK0 to SCK6
I2C
(3ch)
SDA0 to SDA2
SCL0 to SCL2
Input
Capture (4ch)
RTC
OCU0 to OCU3
CM71-10159-2E
Output
Compare (4ch)
A/D Converter
(13ch)
FUJITSU MICROELECTRONICS LIMITED
AN0 to AN12
ATGX
5
CHAPTER 1 OVERVIEW
1.3 Package Dimensions
1.3
MB91461
Package Dimensions
Figure 1.3-1 shows the package dimensions of MB91461.
Figure 1.3-1 Package Dimensions of FPT-176P-M07
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0˚~8˚
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
45
"A"
LEAD No.
1
44
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.25(.010)
M
©2004-2008
FUJITSU MICROELECTRONICS LIMITED F176013S-c-1-2
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
6
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.4 Pin Assignment Diagram
MB91461
1.4
Pin Assignment Diagram
Figure 1.4-1 shows the pin assignment diagram of the MB91461.
■ Pin Assignment Diagram of the MB91461
Figure 1.4-1 shows the pin assignment diagram of the MB91461.
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VCC5
P17_3 PPG3
P17_2/ PPG2
P17_1/ PPG1
P17_0/ PPG0
P14_3/ ICU3/TTN3/TRG3
P14_2/ ICU2/TIN2/TRG2
P14_1/ ICU1/TIN1/TRG1
P14_0/ ICU0/TIN0/TRG0
P22_3
P22_2/ INT13
P22_0/ INT12
P23_6/ INT11
P23_4/ INT10
VCC5
VSS
P15_3/ OCU3/TOT3
P15_2/ OCU2/TOT2
P15_1/ OCU1/TOT1
P15_0/ OCU0/TOT0
P18_2/ SCK6
P18_1/ SOT6
P18_0/ SIN6
P19_6/ SCK5
P19_5/ SOT5
P19_4/ SIN5
P19_2/ SCK4
P19_1/ SOT4
P19_0/ SIN4
VCC5
VSS
P20_6/ SCK3/FRCK3
P20_5/ SOT3
P20_4/ SIN3
P20_2/ SCK2/FRCK2
P20_1/ SOT2
P20_0/ SIN2
P21_6/ SCK1/FRCK1
P21_5/ SOT1
P21_4/ SIN1
P21_2/ SCK0/FRCK0
P21_1/ SOT0
P21_0/ SIN0
VCC5
Figure 1.4-1 Pin Assignment Diagram of the MB91461
VSS
INT2 / P24_2
lNT3 / P24_3
SDA1/lNT15 / P22_6
SCL1 /P22_7
SDA2/INT4 / P24_4
SCL2/lNT5 / P24_5
DREQ0
DACK0X
DEOP0
VCC3
VCC3
VSS
C_1
CS4X
CS3X
CS2X
CS1X
CS0X
IORDX
IOWRX
RDY
BRQ
BGRNTX
RDX
WR0X
WR1X
SYSCLK
ASX
VCC3
C_2
VSS
X0
X1
VSS
D16
D17
D18
D19
D20
D21
D22
D23
VCC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
TOP View
MB91461 Pin Assignment
(LQFP-176)
2 power supply products
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
INITX
TRSTX
MD0
MD1
MD2
MD3
P23_3 / TX1
P23_2 / RX1/INT9
P23_1 / TX0
P23_0 / RX0/lNT8
P24_7 / INT7
P24_6 / INT6
p22_5 / SCL0
P22_4 / SDA0/INT14
P24_1 / lNT1
P24_0 / INT0
AVRH
AVCC3
AVSS/AVRL
P28_4 / AN12
P28_3 / AN11
P28_2 / AN10
P28_1 / AN9
P28_0 / AN8
P29_7 / AN7
P29_6 / AN6
P29_5 / AN5
P29_4 / AN4
P29_3 / AN3
P29_2 / AN2
P29_1 / AN1
P29_0 / AN0
WDRESETX
BREAK
ICLK
ICS2
ICS1
lCS0
ICD3
lCD2
lCD1
lCD0
VCC3
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VSS
P17_7 / PPG7
P17_6 / PPG6
P17_5 / PPG5
P17_4 / PPG4
P16_7 / ATGX
NMIX
A23
A22
A21
A20
A19
A18
A17
VSS
VCC3
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
VSS
VCC3
A02
A01
A00
D31
D30
D29
D28
D27
D26
D25
D24
VSS
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
7
CHAPTER 1 OVERVIEW
1.4 Pin Assignment Diagram
MB91461
Note:
Three I/O blocks (Blocks 1, 2 & 3) are each 176 pins, 162 pins, 133 pins (147 pins), and power
supply level (3.3V/5V) to each pin can be set. However, please supply 5V power supply when there
is a pin that operates as much as one each block by 5V.
Only when the pin for I2C of Block 1 supplies 5V to the power supply, the input of 5V amplitude
becomes possible. Moreover, the input threshold of I2C reaches the value based on 3.3V regardless
of the power-supply voltage.
When I/O Block 1 or 3 is used with 5V pins, the INITX pin requires 5V input. Consequently, I/O Block
3 also requires 5V to be supplied.
8
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
1.5
Pin Descriptions
Table 1.5-1 shows the pin descriptions of the MB91461.
■ Pin Descriptions
Table 1.5-1 Pin Descriptions (1 / 5)
Pin no.
Pin name
I/O
I/O circuit type
I/O
D
P24_2
2
General purpose I/O port
INT2
External interrupt input pin
P24_3
3
General purpose I/O port
I/O
D
INT3
External interrupt input pin
P22_6
4
SDA1
General purpose I/O port
I/O
Open Drain
C
INT15
P22_7
5
SCL1
SDA2
I/O
Open Drain
General purpose I/O port
C
C
I2C bus DATA I/O pin
External interrupt input pin
P24_5
SCL2
I2C bus Clock I/O pin
General purpose I/O port
I/O
Open Drain
INT4
7
I2C bus DATA I/O pin
External interrupt input pin
P24_4
6
Function
General purpose I/O port
I/O
Open Drain
C
INT5
I2C bus Clock I/O pin
External interrupt input pin
8
DREQ0
I
H
DMA external transfer request input
9
DACK0X
O
H
DMA external transfer acknowledge output
10
DEOP0
O
H
DMA external transfer EOP (End of Process) output
15 to 19
CS4X to CS0X
O
H
Chip select outputs
20
IORDX
O
H
Read strobe output for DMA flyby transfer
21
IOWRX
O
H
Write strobe output for DMA flyby transfer
22
RDY
I
H
External ready input
23
BRQ
I
H
External bus release request input
24
BGRNTX
O
H
External bus release acceptance output
25
RDX
O
H
External read strobe output
26
WR0X
O
H
External write strobe output
27
WR1X
O
H
External write strobe output
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
9
CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
Table 1.5-1 Pin Descriptions (2 / 5)
Pin no.
Pin name
I/O
I/O circuit type
28
SYSCLK
O
H
System clock output
29
ASX
O
H
Address strobe output
33
X0
−
H
Clock (oscillation) input
34
X1
−
H
Clock (oscillation) output
36 to 43
46 to 53
D16 to D31
I/O
H
External data bus signals
54 to 56
59 to 72
75 to 81
A00 to A23
O
H
External address bus signals
82
NMIX
I
H
NMI (Non Maskable Interrupt) input
H
General purpose I/O port
H
A/D converter external trigger input
H
General purpose I/O port
H
PPG timer output pins
P16_7
83
Function
I/O
ATGX
P17_4 to P17_7
84 to 87
I/O
PPG4 to PPG7
90 to 93
ICD0 to ICD3
I/O
H
Data I/O pins for a development tool
94 to 96
ICS0 to ICS2
O
H
Status output pins for a development tool
97
ICLK
O
I
Clock output pin for a development tool
98
BREAK
I
H
Break input pin for a development tool
99
WDRESETX
O
J
Watchdog reset output pin
I/O
F
P29_0 to P29_7
100 to 107
General purpose I/O port
AN0 to AN7
Analog input pins for the A/D converter
P28_0 to P28_4
108 to 112
General purpose I/O port
I/O
F
AN8 to AN12
Analog input pins for the A/D converter
P24_0, P24_1
General purpose I/O port
116, 117
I/O
D
INT0, INT1
P22_4
118
SDA0
General purpose I/O port
I/O
Open Drain
C
INT14
P22_5
119
SCL0
I/O
Open Drain
General purpose I/O port
C
10
I2C bus clock I/O pin
General purpose I/O port
I/O
INT6
I2C bus DATA I/O pin
External interrupt input pin
P24_6
120
External interrupt input pin
Can be used as a shutdown recovery source
D
External interrupt input pin
Can be used as a shutdown recovery source
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
Table 1.5-1 Pin Descriptions (3 / 5)
Pin no.
Pin name
I/O
I/O circuit type
P24_7
121
122
General purpose I/O port
I/O
D
INT7
External interrupt input pin
Can be used as a shutdown recovery source
P23_0
General purpose I/O port
RX0
I/O
D
P23_1
123
RX input pin for CAN0
External interrupt input pin
Can be used as a shutdown recovery source
INT8
124
Function
General purpose I/O port
I/O
D
TX0
TX output pin for CAN0
P23_2
General purpose I/O port
RX1
I/O
D
External interrupt input pin
Can be used as a shutdown recovery source
INT9
P23_3
125
RX input pin for CAN1
General purpose I/O port
I/O
D
TX1
TX output pin for CAN0
126
MD3
I
A
127
MD2
I
A
128
MD1
I
A
129
MD0
I
B
130
TRSTX
I
E
Reset input pin for a development tool
131
INITX
I
B
External reset input
I/O
D
P21_0
134
General purpose I/O port
SIN0
Data input pin for UART0
P21_1
135
136
General purpose I/O port
I/O
D
SOT0
Data output pin for UART0
P21_2
General purpose I/O port
SCK0
I/O
D
FRCK0
General purpose I/O port
I/O
D
SIN1
Data input pin for UART1
P21_5
138
General purpose I/O port
I/O
SOT1
Clock I/O pin for UART0
External clock input pin for the free-run timer 0
P21_4
137
CM71-10159-2E
Mode setup pin
MD3 is fixed to "0"
D
Data output pin for UART1
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
Table 1.5-1 Pin Descriptions (4 / 5)
Pin no.
Pin name
I/O
I/O circuit type
P21_6
139
SCK1
General purpose I/O port
I/O
D
FRCK1
General purpose I/O port
I/O
D
SIN2
Data input pin for UART2
P20_1
141
142
General purpose I/O port
I/O
D
SOT2
Data output pin for UART2
P20_2
General purpose I/O port
SCK2
I/O
D
FRCK2
General purpose I/O port
I/O
D
SIN3
Data input pin for UART3
P20_5
144
General purpose I/O port
I/O
D
SOT3
Data output pin for UART3
P20_6
General purpose I/O port
SCK3
I/O
D
FRCK3
General purpose I/O port
I/O
D
SIN4
Data input pin for UART4
P19_1
149
General purpose I/O port
I/O
D
SOT4
Data output pin for UART4
P19_2
150
General purpose I/O port
I/O
D
SCK4
Clock I/O pin for UART4
P19_4
151
General purpose I/O port
I/O
D
SIN5
Data input pin for UART5
P19_5
152
General purpose I/O port
I/O
D
SOT5
Data output pin for UART5
P19_6
153
General purpose I/O port
I/O
D
SCK5
Clock I/O pin for UART5
P18_0
154
General purpose I/O port
I/O
D
SIN6
Data input pin for UART6
P18_1
155
General purpose I/O port
I/O
SOT6
Clock I/O pin for UART3
External clock input pin for the free-run timer 3
P19_0
148
12
Clock I/O pin for UART2
External clock input pin for the free-run timer 2
P20_4
143
145
Clock I/O pin for UART1
External clock input pin for the free-run timer 1
P20_0
140
Function
D
Data output pin for UART6
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
Table 1.5-1 Pin Descriptions (5 / 5)
Pin no.
Pin name
I/O
I/O circuit type
I/O
D
P18_2
156
157 to 160
Function
General purpose I/O port
SCK6
Clock I/O pin for UART6
P15_0 to P15_3
General purpose I/O port
OCU0 to OCU3
I/O
D
TOT0 to TOT3
Reload timer output pins
P23_4
163
General purpose I/O port
I/O
D
INT10
External interrupt input pin
P23_6
164
General purpose I/O port
I/O
D
INT11
External interrupt input pin
P22_0
165
General purpose I/O port
I/O
D
INT12
External interrupt input pin
P22_2
166
General purpose I/O port
I/O
D
INT13
167
P22_3
External interrupt input pin
I/O
D
P14_0 to P14_3
Input capture input pins
I/O
D
TIN0 to TIN3
External trigger input pin for the reload timers
TRG0 to TRG3
External trigger input pins for PPG
P17_0 to P17_3
172 to 175
General purpose I/O port
I/O
PPG0 to PPG3
CM71-10159-2E
General purpose I/O port
General purpose I/O port
ICU0 to ICU3
168 to 171
Output compare output pins
D
PPG timer output pins
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 1 OVERVIEW
1.5 Pin Descriptions
MB91461
Table 1.5-2 Pin Descriptions [Power Supply and GND Pins]
Pin no.
Pin name
I/O circuit type
1, 13, 32, 35
45, 58, 74, 88
132, 146, 161
VSS
(VSS)
11, 12, 30, 44
57, 73, 89
VCC3
(VCC3)
3.3V power supply pins
14
Function
GND pins
133
147
VCC5
(VCC5)
5V power supply pins, used as I/O power supply pins supporting pins
116 to 145. When 3.3V is supplied, I/O performs 3.3V operations.
When 5V is used in another I/O power supply block, the I/O block
which this pin belongs to must also be set to 5V.
162
VCC5
(VCC5)
5V power supply pins, used as I/O power supply pins supporting pins
148 to 160. When 3.3V is supplied, I/O performs 3.3V operations.
176
VCC5
(VCC5)
5V power supply pins, used as I/O power supply pins supporting pins 2
to 7 and 163 to 175. If there is at least one 5V pin, 5V must be supplied.
113
AVSS/AVRL
(AVSS)
Analog GND pin for the A/D converter
114
AVCC3
(AVCC3)
3.3V power supply pin for the A/D converter
115
AVRH
(AVRH)
Reference power supply pin for the A/D converter
14
C_1
−
Capacitor connection pin for the internal regulator. 4.7 μF must be
connected.
31
C_2
−
Capacitor connection pin for the internal regulator. 4.7 μF must be
connected.
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.6 I/O Circuit Types
MB91461
1.6
I/O Circuit Types
This section describes the I/O circuit types.
■ I/O Circuit Types
Table 1.6-1 I/O Circuit Types (1 / 4)
Type
Circuit
Remarks
5V CMOS hysteresis input with pull-down
5V level
Input
A
N-ch
Pull-down
5V CMOS hysteresis input with pull-up
Pull-up
P-ch
B
Input
5V level
I/O pin for I2C
IOL= 3mA
N-ch
Output drive N-ch
5V resisting pressure (With standby control)
C
Input
Standby control
CM71-10159-2E
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CHAPTER 1 OVERVIEW
1.6 I/O Circuit Types
MB91461
Table 1.6-1 I/O Circuit Types (2 / 4)
Type
Circuit
Remarks
5V CMOS level output
IOL= 4mA
Pull-up control
5V CMOS level input
P-ch
Output drive P-ch
5V CMOS hysteresis input with pull-up/pull-down
control
(With standby control)
N-ch
Output drive N-ch
P-ch
5V level
D
Pull-down control
N-ch
Input
Standby control
Input
Standby control
3.3V CMOS hysteresis input
3.3V level
E
5V resisting pressure (With standby control)
Input
3.3V CMOS level output
IOL= 4mA
3.3V level
P-ch
N-ch
Output drive P-ch
Output drive N-ch
3.3V CMOS level input
3.3V CMOS hysteresis input
Analog input (With standby control)
F
Input
Standby control
Input
Standby control
Analog input
16
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 1 OVERVIEW
1.6 I/O Circuit Types
MB91461
Table 1.6-1 I/O Circuit Types (3 / 4)
Type
Circuit
Remarks
3.3V oscillation cell
3.3V level
Input
(feedback resistor 1 MΩ)
G
Standby control
3.3V CMOS level output
IOL= 4mA
Pull-up control
3.3V CMOS level input
P-ch
Output drive P-ch
3.3V CMOS hysteresis input with pull-up/pulldown control
(With standby control)
N-ch
Output drive N-ch
P-ch
3.3V level
H
N-ch
Pull-down control
Input
Standby control
Input
Standby control
3.3V CMOS level output
I: IOL= 8mA
3.3V level
P-ch
Output drive P-ch
N-ch
Output drive N-ch
J: IOL= 4mA
I, J
CM71-10159-2E
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CHAPTER 1 OVERVIEW
1.6 I/O Circuit Types
MB91461
Table 1.6-1 I/O Circuit Types (4 / 4)
Type
Circuit
Remarks
5V CMOS level input
5V level
K
18
Input
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 2
HANDLING DEVICES
This chapter describes precautions on handling FR
family devices.
2.1 Precautions on Handling Devices
2.2 Precautions for Use
CM71-10159-2E
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CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling Devices
2.1
MB91461
Precautions on Handling Devices
This section explains how to prevent latch-up, perform pin processing, handle circuits
and input at power-up.
■ Preventing Latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC or less than VSS is applied to an input or
output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may
significantly increase the power supply current, resulting in thermal destruction of an element. Therefore,
utmost care should be taken that the maximum rating is not exceeded in use.
■ Treatment of Unused Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by using a pull-up or pulldown resistor.
■ Power Supply Pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the
device to avoid abnormal operations including latch-up. However, you must connect all the pins to external
power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current
rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low
impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS
near this device.
MB91461 incorporates a built-in step-down regulator. Connect a 4.7 μF bypass capacitor to C_1 and C_2
pins for the regulator.
■ Crystal Oscillator Circuit
Noise near the X0 and X1 (X0A, X1A) pins may cause the device to malfunction. Design the printed
circuit board so that X0 (X0A) and X1 (X1A), the crystal oscillator, and the bypass capacitor to ground are
located as close to the device as possible. It is strongly recommended to design the PC board artwork with
the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a
layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
20
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling Devices
MB91461
■ Notes on Using External Clock
When an external clock is used, supply it to X0 (X0A) pin generally, and simultaneously the opposite phase
clock to X0 (X0A) must be supplied to X1 (X1A) pin. However, in this case the stop mode (oscillator stop
mode) must not be used (This is because the X1 (X1A) pin stops at "H" output in the STOP mode).
Figure 2.1-1 Example Application of External Clock (Normal)
X0 (X0A)
X1 (X1A)
Note: STOP mode (oscillation stop mode) cannot be used.
■ Mode Pins (MD0 to MD3)
These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to
test mode due to noise, design the printed circuit board such that the distance between the mode pins and
VCC or VSS is as short as possible and the connection impedance is low.
■ Power-up Sequence for 3.3V and 5V Power Supplies
• Immediately after the power supply is turned on, hold the Low level input to the INITX pin for the
settling time required for the oscillator circuit to take the oscillation stabilization wait time (8ms) for the
oscillator circuit.
• There is no particular start-up sequence for power supply
• When canceling a reset (by changing the INITX pin from the Low level to the High level), ensure that
3.3V and 5V power supplies are stable.
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling Devices
MB91461
■ Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
■ External Bus Setting
MB91461 guarantee an external bus clock (SYSCLK) frequency of 40 MHz.
Setting the base clock frequency to 40 MHz with DIVR1 (external bus base clock division setting register)
initialized sets the external bus frequency also to 80 MHz. Before changing the base clock frequency, set
SYSCLK not exceeding 80 MHz.
■ Pull-up Control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC
specifications.
■ Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an
error. If an error is detected, retransmit the data.
■ Notes on the PS Register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS
register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning
from such an EIT event, it performs operations before and after the EIT as specified in either case.
(1) The following operations are performed when the instruction followed by a DIV0U/DIV0S
instruction results in acceptance of a user interrupt or NMI, single-stepping, or a break at a data
event or emulator menu.
- The D0 and D1 flags are updated in advance.
- An EIT handling routine (user interrupt, NMI, or emulator) is executed.
- Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags
are updated to the same values as in (1).
(2) The following operations are performed when the OR CCR/ST ILM/MOV Ri, PS instructions are
executed during a user interrupt or NMI.
- The PS register is updated in advance.
- An EIT handling routine (user interrupt, NMI, or emulator) is executed.
- Upon returning from the EIT, the above instructions are executed and the PS register is updated to
the same value as in (1).
■ Software Reset on the Synchronous Mode
Be sure to meet the following two conditions before setting "0" to the SRST bit of STCR (standby
control register) when the software reset is used on the synchronous mode.
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CM71-10159-2E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions on Handling Devices
MB91461
• Set the interrupt enable flag (I) to interrupt disabled (I = 0).
• Not used NMI.
■ Note on Debugger
● Step execution of RETI command
If an interrupt occurs frequently during stepping, only the corresponding interrupt handling routine is
executed repeatedly. This will prevent the main routine and low-interrupt-level programs from being
executed (For example, whenever RETI is stepped with interrupts by the time-base timer enabled, the timebase timer routine causes a break at the beginning).
Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs
debugging.
● Break function
If the address at which to cause a hardware break (including an event break) is set to the address currently
contained in the system stack pointer or in the area containing the stack pointer, the user program causes a
break after the execution of one instruction, despite no actual data access command in the program.
To prevent a break, do not set (word) access to the area containing the address in the system stack pointer
as the target of a hardware break (including an event break).
● Operand breaks
A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 2 HANDLING DEVICES
2.2 Precautions for Use
2.2
MB91461
Precautions for Use
This section shows the precautions when using dedicated DSU4 (ICE) connection pin.
■ Dedicated DSU4 (ICE) Connection Pin
The DSU4 (ICE) connection pin for MB91461 is shown below.
Table 2.2-1 DSU4 (ICE) Connection Pin for MB91461
Pin no.
Pin name
Function
93 to 90
ICD3 to ICD0
Data I/O pins for a development tool
96 to 94
ICS2 to ICS0
Status output pins for a development tool
97
ICLK
Clock pin for a development tool
98
BREAK
Break pin for a development tool
130
TRSTX
Reset pin for a development tool
(3.3V/5V input pin)
● Connector for the user target board and MB91461 connection
A recommended connector for the user target board is shown below.
Manufacturer: Yamaichi Electronics Co., Ltd.
Part number: FAP-20-08#*
Note: The symbol "*" shown in the part number is a single-digit number that indicates a pin shape.
• 1: Right-angled/wrapping
• 2: Right-angled/solder dip
• 4: Straight/solder dip
Figure 2.2-1 Connector for the User Target Board and MB91461 Connection
24
19pin
1pin
20pin
2pin
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 2 HANDLING DEVICES
2.2 Precautions for Use
MB91461
Table 2.2-2 Pin Function List of Target Side Connector
Pin no.
Signal line
name
Input/
output
1
EVCC2
Input
OPEN
2
EVCC3
Input
OPEN
3
DSUIO
I/O
OPEN
4
UVCC
Output
User Vcc output
6
XRSTIN
Output
Connected to the INITX signal in the user circuit
8
PLVL
Input
5
XTRST
Input
Connected to TRSTX (Pin no. 130)
7
XINIT
Input
Connected to INITX (Pin no. 131)
9
GND
−
10
BREAK
Input
11
ICD[3]
12
ICD[2]
Pin handling
OPEN
Connected to VSS
Connected to BREAK (Pin no. 98)
Connected to ICD3 (Pin no. 93)
Connected to ICD2 (Pin no. 92)
I/O
13
ICD[1]
Connected to ICD1 (Pin no. 91)
MB91461
CM71-10159-2E
14
ICD[0]
Connected to ICD0 (Pin no. 90)
15
GND
16
ICS[2]
17
ICS[1]
18
ICS[0]
19
GND
−
20
ICLK
Output
−
Connected to VSS
Connected to ICS2 (Pin no. 96)
Output
Connected to ICS1 (Pin no. 95)
Connected to ICS0 (Pin no. 94)
Connected to VSS
Connected to ICLK (Pin no. 97)
FUJITSU MICROELECTRONICS LIMITED
25
CHAPTER 2 HANDLING DEVICES
2.2 Precautions for Use
MB91461
● Handling of DSU4 (ICE) pins in mass production
Table 2.2-3 Handling of DSU4 (ICE) Pins in Mass Production
Pin no.
Pin name
Pin handling
93 to 90
ICD3 to ICD0
OPEN
96 to 94
ICS2 to ICS0
OPEN
97
ICLK
OPEN
98
BREAK
OPEN
130
TRSTX
Connected to INITX (Pin no. 131: External reset input pin)
Figure 2.2-2 Connection Handling of the Reset Pin (TRSTX) for the Development Tool (DSU) in Mass
Production
INITX
Reset input
TRSTX
As the reset pin (TRSTX) for the development tool supports both 3.3V and 5V power supplies, it can be
connected directly to the INITX pin.
26
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 3
CPU
This chapter describes FR family CPU core architecture,
specifications and instructions.
3.1 Memory Space
3.2 Internal Architecture
3.3 Programming Model
3.4 Data Structure
3.5 Memory Map
3.6 Branch Instructions
3.7 EIT (Exception, Interrupt, and Trap)
CM71-10159-2E
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CHAPTER 3 CPU
3.1 Memory Space
3.1
MB91461
Memory Space
The FR family has a logical address space of 4Gbytes (232 addresses) and the CPU
linearly accesses the memory space.
■ Direct Addressing Area
The following areas on the address space are used for I/O.
In these areas, called "direct addressing areas", operand addresses can be specified directly in instructions.
There are different direct addressing areas as shown below, depending on the size of the accessed data.
Byte data access
: 000H to 0FFH
Halfword data access
: 000H to 1FFH
Word data access
: 000H to 3FFH
■ Memory Map
Figure 3.1-1 shows the memory map.
Figure 3.1-1 Memory Map
MB91461
External ROM
external bus mode
0000 0000H
I/O
0000 0400H
Direct addressing
area
(See I/O map)
I/O
0000 1000H
0000 8000H
0000 BFFFH
BI-ROM
0001 0000H
0002 0000H
I-cache
0003 0000H
0004 0000H
ID-RAM
External area
0010 0000H
Reset /
mode vector
External area
FFFF FFFFH
Note:
RAM installed in MB91V460 is all "0" weight.
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FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 3 CPU
MB91461
3.2
Internal Architecture
3.2 Internal Architecture
The CPU of the FR family is a high performance core that adopts highly functional
instructions for embedded applications as well as a RISC architecture.
■ Features of the Internal Architecture
• Adoption of RISC architecture
Basic instruction: one instruction per cycle
• 32-bit architecture
General-purpose registers: 32 bits × 16
• Linear memory space of 4 Gbytes
• Multipliers installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
High response speed (6 cycles)
Multiple interrupts supported
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instructions
Bit processing instructions
• High code efficiency
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode, stop mode, shutdown mode
CM71-10159-2E
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29
CHAPTER 3 CPU
3.2 Internal Architecture
MB91461
■ Structure of the Internal Architecture
The CPU of the FR family is based on the Harvard architecture in which the instruction bus and data bus
are separated.
The 32-bit ←→ 16-bit bus converter is connected to a 32-bit bus (D-bus), providing an interface between
the CPU and the peripheral resources.
The Harvard ←→ Princeton bus converter is connected to both of the I-bus and D-bus, providing an
interface between the CPU and the bus controller.
Figure 3.2-1 shows the structure of the internal architecture.
Figure 3.2-1 Structure of the Internal Architecture
DSU
(debug support)
FR60CPU
Core
D-bus
I-bus
Bit search
I-cache
RAM
32
32
CAN (2ch)
32
16
Bus adapter
RAM
Bus converter
16
R-bus
External
bus
interface
DMAC
5ch
Peripheral
resources
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FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 3 CPU
3.2 Internal Architecture
MB91461
■ CPU
The 32-bit RISC FR architecture is compactly implemented on the CPU. A five-level instruction pipeline
method is adopted to execute one instruction per cycle. The pipeline is composed of the following stages.
Figure 3.2-2 shows the instruction pipeline.
Instruction fetch (IF):
Outputs the instruction address and fetches the instruction.
Instruction decode (ID):
Decodes the fetched instruction and also reads registers.
Execution (EX):
Executes the operation.
Memory access (MA):
Performs memory load or store accesses.
Write back (WB):
Writes the operation results (or loaded memory data) back to the registers.
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead of
instruction B, instruction A always reaches the writeback stage before instruction B.
The standard execution speed is one instruction per cycle. However, load and store instructions that involve
a memory wait, branch instructions without a delay slot, and multi-cycle instructions require more than one
cycle to execute. The instruction execution speed also drops if delivery of instruction is slow.
■ Instruction Cache
The on-chip instruction cache enables a high-performance system to be implemented without the added
cost of external high-speed memory and related control logic. Even if the external bus speed is slow,
instructions can be supplied to the CPU at high speed.
Refer to "CHAPTER 5 INSTRUCTION CACHE" for details of instruction cache.
CM71-10159-2E
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CHAPTER 3 CPU
3.2 Internal Architecture
MB91461
■ 32-bit ←→ 16-bit Bus Converter
This converter provides an interface between the 32-bit F-bus that is accessed at high speed and the 16-bit
R-bus and enables the CPU to access data in the internal peripheral circuits.
When a 32-bit access from the CPU occurs, the bus converter converts the access into two 16-bit accesses
on the R-bus. Note that the access width of some internal peripheral circuits is restricted.
■ Harvard ←→ Princeton Bus Converter
This bus converter coordinates CPU instruction and data accesses and provides a smooth interface to the
external bus.
The CPU has a Harvard architecture in which the instruction and data buses are separated. However, the
bus controller that controls the external bus has a single-bus Princeton architecture. The bus converter
prioritizes CPU instruction and data accesses and controls access to the bus controller. This function
continuously optimizes the order of external bus accesses.
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3.2.1
Overview of Instructions
3.2 Internal Architecture
In addition to standard RISC instructions, the FR family supports logical operations
optimized for embedded applications, bit manipulation instructions, and direct
addressing instructions.
As each instruction is 16 bits in length (some instructions are 32-bit or 48-bit long), the
FR provides superior memory utilization efficiency.
The instruction set can be divided into the following functional groups.
• Arithmetic operations
• Load and store
• Branch
• Logical operations and bit manipulation
• Direct addressing
• Others
■ Arithmetic Operations
The standard arithmetic operation instructions (add, subtract, compare) and shift instructions (logical shift,
arithmetic operation shift) are provided. Addition and subtraction include operations with carry for use in
multi-word operations and operations that do not change the flags, a convenience in address calculations.
Also, 32-bit × 32-bit multiplication, 16-bit × 16-bit multiplication, and 32-bit / 32-bit step division
instructions are provided. In addition, immediate value transfer instructions which set immediate values to
registers are provided. Register-to-register transfer instructions are also enabled. The arithmetic operation
instructions all perform operations using the general-purpose register and multiplication and division
registers in the CPU.
■ Load and Store
Load and store instructions read data from or write data to external memory. The instructions are also used
to read from and write to the internal peripheral circuits (I/O).
Load and store instructions are provided for byte (8 bits), halfword (16 bits), and word length (32 bits)
access. In addition to standard register indirect memory addressing, some instructions support register
indirect with displacement memory addressing and register indirect with register increment or decrement
memory addressing.
■ Branch
This includes the branch, call, interrupt, and return instructions. Branch instructions are divided into those
that have a delay slot and those that do not. This enables optimization depending on applications. Refer to
"3.6 Branch Instructions" for details of branch instructions.
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CHAPTER 3 CPU
3.2 Internal Architecture
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■ Logical Operations and Bit Manipulation
Logical operation instructions can perform AND, OR, or EOR logical operations between general-purpose
registers or between general-purpose registers and memory (and I/O). The bit manipulation instructions can
manipulate the contents of memory (and I/O) directly.
These instructions use standard register indirect memory addressing.
■ Direct Addressing
Direct addressing instructions are instructions used for access between I/O and general-purpose register or
between I/O and memory. Specifying an I/O address directly in an instruction rather than by register
indirect addressing provides high-speed, high-efficiency access. Some instructions support register indirect
memory addressing with register increment or decrement.
■ Other Instructions
These include instructions to set the flags in the PS register and instructions to perform stack operations as
well as sign-extend and zero-extend instructions. Function entry and exit processing instructions for highlevel languages and multi-register load/store instructions are also provided.
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CHAPTER 3 CPU
3.3 Programming Model
MB91461
3.3
Programming Model
This section describes the programming model, general-purpose registers, and
dedicated registers of the FR family.
■ Basic Programming Model
Figure 3.3-1 shows the basic programming model.
Figure 3.3-1 Basic Programming Model
32 bits
[Initial value]
XXXX XXXXH
R0
···
R1
···
···
General-purpose
registers
···
···
···
AC
···
R12
R13
R14
R15
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication and
division result registers
MDH
MDL
CM71-10159-2E
···
···
ILM
FP
XXXX XXXXH
SP
0000 0000H
SCR
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CCR
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CHAPTER 3 CPU
3.3 Programming Model
3.3.1
MB91461
General-purpose Registers
Registers R0 to R15 are general-purpose registers.
These registers are used as an accumulator for operations or as a pointer for memory
access.
■ General-purpose Registers
Figure 3.3-2 shows the structure of the general-purpose registers.
Figure 3.3-2 Structure of the General-purpose Registers
32 bits
[Initial value]
R0
XXXX XXXXH
R1
···
···
···
···
···
···
···
···
···
R12
R13
R14
AC
FP
XXXX XXXXH
R15
SP
0000 0000H
Of the 16 general-purpose registers, the following registers are expected to be used in special applications.
Therefore, some of the instructions used are enhanced.
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)
The initial value of R0 to R14 after a reset is indeterminate. The initial value of R15 is 00000000H (SSP
value).
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CHAPTER 3 CPU
3.3 Programming Model
MB91461
3.3.2
Dedicated Registers
Each of the dedicated registers is used for a specific purpose.
The FR family has the following dedicated registers:
• Program Status (PS)
• Condition Code Register (CCR)
• System Condition code Register (SCR)
• Interrupt Level Mask Register (ILM)
• Program Counter (PC)
• Table Base Register (TBR)
• Return Pointer (RP)
• System Stack Pointer (SSP)
• User Stack Pointer (USP)
• Multiply & Divide register
■ Program Status (PS)
Stores the program status (PS) and consists of the ILM, SCR, and CCR sections.
All undefined bits are reserved bits and always read as "0".
Writing is invalid.
Figure 3.3-3 shows the structure of the program status (PS).
Figure 3.3-3 The Structure of the Program Status (PS)
bit
31
20
16
ILM
CM71-10159-2E
10 8 7
SCR
0
CCR
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CHAPTER 3 CPU
3.3 Programming Model
MB91461
■ Condition Code Register (CCR)
Figure 3.3-4 shows the structure of the condition code register (CCR).
Figure 3.3-4 The Structure of the Condition Code Register (CCR)
bit
7
6
5
4
3
2
1
0
Initial value
−
−
S
I
N
Z
V
C
--00XXXXB
[bit5] S: Stack flag
Specifies the stack pointer used as R15.
Table 3.3-1 Stack Flag
Value
Function
0
SSP is used as R15.
Automatically changes to "0" when an EIT occurs
(Note that the value saved on the stack is the value before the bit is cleared).
1
USP is used as R15.
This bit is cleared to "0" at reset.
Set it to "0" when executing a RETI instruction.
[bit4] I: Interrupt enable flag
Controls the enabling and disabling of user interrupt requests.
Table 3.3-2 Interrupt Enable Flag
Value
Function
0
User interrupts disabled.
Cleared to "0" when an INT instruction is executed
(Note that the value saved on the stack is the value before the bit is cleared).
1
User interrupts enabled.
The ILM value controls the masking of user interrupt requests.
This bit is cleared to "0" at reset.
[bit3] N: Negative flag
Indicates the sign of the operation result interpreted as an integer that is expressed in the complement of
2.
Table 3.3-3 Negative Flag
Value
Function
0
Indicates that the operation has resulted in a positive value.
1
Indicates that the operation has resulted in a negative value.
The initial value after a reset is indeterminate.
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[bit2] Z: Zero flag
Specifies whether the operation result was zero.
Table 3.3-4 Zero Flag
Value
Function
0
Indicates that the operation has resulted in a value other than zero.
1
Indicates that the operation has resulted in zero.
The initial value after a reset is indeterminate.
[bit1] O: Overflow flag
Interprets the operand used in the operation as the integer that is expressed in the complement of 2 and
specifies whether or not the operation has caused an overflow.
Table 3.3-5 Overflow Flag
Value
Function
0
Indicates that the operation has not caused an overflow.
1
Indicates that the operation has caused an overflow.
The initial value after a reset is indeterminate.
[bit0] C: Carry flag
Specifies whether the operation has caused a carry or borrow from the MSB.
Table 3.3-6 Carry Flag
Value
Function
0
Indicates that neither a carry nor borrow has occurred.
1
Indicates that a carry or borrow has occurred.
The initial value after a reset is indeterminate.
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CHAPTER 3 CPU
3.3 Programming Model
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■ System Condition Code Register (SCR)
Figure 3.3-5 shows the structure of the system condition code register (SCR).
Figure 3.3-5 The Structure of the System Condition Code Register (SCR)
bit
10
9
8
[Initial value]
D1
D0
T
XX0B
[bit10, bit9] Step division flags
These bits store intermediate data during the execution of step divisions.
Do not modify the bits during a division operation. If performing other operations during a step
division, restarting of the division is assured if the value of the PS register is saved and restored.
The initial value after a reset is indeterminate.
Executing the DIV0S instruction references the dividend and divisor and sets the bits.
Executing the DIV0U instruction forcibly clears the bits.
Do not perform any operation in expectation of the D0/D1 bits of the PS register before EIT branching
in the EIT processing routine for a DIV0S/DIV0U instruction, user interrupt, and NMI simultaneous
acceptance.
If the bits are stopped by a break or step immediately before a DIV0S/DIV0U instruction, the D0/D1
bits of the PS register may not display the correct value. However, the operation result shows the
correct value once it is restored.
[bit8] Step trace trap flag
This flag specifies whether the step trace trap is enabled or disabled.
Table 3.3-7 Step Trace Trap Flag
Value
Function
0
Disables the step trace trap.
1
Enables the step trace trap.
This disables the user NMI and all the user interrupts.
Initialized to "0" at reset.
The step trace trap function is used by the emulator. The function cannot be used by the user program
when the emulator is in use.
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CHAPTER 3 CPU
3.3 Programming Model
MB91461
■ Interrupt Level Mask Register (ILM)
Figure 3.3-6 shows the structure of the interrupt level mask register (ILM).
Figure 3.3-6 The Structure of the Interrupt Level Mask Register (ILM)
bit
20
19
18
17
16
[Initial value]
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
The interrupt level mask register (ILM) stores the interrupt level mask value. The value stored in the
interrupt level mask register (ILM) is used for the level mask.
Only interrupt requests to the CPU with an interrupt level that has a higher priority than the level in the
interrupt level mask register (ILM) are accepted.
Level 0 (00000B) has the highest priority and level 31 (11111B) has the lowest priority.
Restrictions apply to the values that can be set by the program.
When the original value is between 16 and 31:
A new value can be set to only 16 to 31. Executing an instruction to set a value to 0 to 15 transfers the
"specified value + 16".
When the original value is between 0 and 15:
When the original value is between 0 and 15, any value between 0 and 31 can be set.
It is initialized to 15 (01111B) at reset.
■ Program Counter (PC)
Figure 3.3-7 shows the structure of the program counter (PC).
Figure 3.3-7 The Structure of the Program Counter (PC)
bit 31
0
PC
[Initial value]
XXXXXXXXH
[bit31 to bit0]
This register functions as a program counter and points to the address of the currently executing
instruction.
Bit0 is set to "0" when updating the PC as part of instruction execution. Bit0 can have the value "1"
only when an odd-numbered address is specified as a branch destination address.
However, even if bit0 is "1", the bit0 value is ignored and instructions must be located at addresses that
are multiples of two.
The initial value after a reset is indeterminate.
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CHAPTER 3 CPU
3.3 Programming Model
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■ Table Base Register (TBR)
Figure 3.3-8 shows the structure of the table base register (TBR).
Figure 3.3-8 The Structure of the Table Base Register (TBR)
bit 31
0
TBR
[Initial value]
000FFC00H
This register stores the top address of the vector table used for EIT processing.
It is initialized to 000FFC00H at reset.
■ Return Pointer (RP)
Figure 3.3-9 shows the structure of the return pointer (RP).
Figure 3.3-9 The Structure of the Return Pointer (RP)
bit 31
0
RP
[Initial value]
XXXXXXXXH
This pointer stores the return address from subroutines.
Executing the CALL instruction transfers the value of the PC to the RP.
Executing the RET instruction transfers the contents of the RP to the PC.
The initial value after a reset is indeterminate.
■ System Stack Pointer (SSP)
Figure 3.3-10 shows the structure of the system stack pointer (SSP).
Figure 3.3-10 The Structure of the System Stack Pointer (SSP)
bit 31
0
SSP
[Initial value]
00000000H
The SSP is a system stack pointer.
It functions as R15 when the S flag is "0".
The SSP can also be specified explicitly. The SSP can also be used as the stack pointer that specifies the
stack on which to save the PS and PC when an EIT occurs.
It is initialized to 00000000H at reset.
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■ User Stack Pointer (USP)
Figure 3.3-11 shows the structure of the user stack pointer (USP).
Figure 3.3-11 The Structure of the User Stack Pointer (USP)
bit 31
0
USP
[Initial value]
XXXXXXXXH
The USP is a user stack pointer.
It functions as R15 when the S flag is "1".
The USP can also be specified explicitly.
The initial value after a reset is indeterminate.
It cannot be used in the RETI instruction.
■ Multiply & Divide Registers
Figure 3.3-12 shows the structure of the multiply & divide registers.
Figure 3.3-12 The Structure of the Multiply & Divide Registers
bit 31
0
MDH
MDL
These registers are used for multiplication and division and are 32 bits in length.
The initial value after a reset is indeterminate.
When a multiplication is executed:
For a 32-bit × 32-bit multiplication, the 64-bit operation result is stored in the multiplication and
division result registers as shown below.
MDH: Upper 32 bits
MDL: Lower 32 bits
For a 16-bit × 16-bit multiplication, the result is stored as follows.
MDH: Indeterminate
MDL: 32-bit result
When a division is executed:
The dividend is stored in MDL when the calculation is started.
When the division is performed by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, DIV4S instructions,
the result is stored in MDH and MDL.
MDH: Remainder
MDL: Quotient
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CHAPTER 3 CPU
3.4 Data Structure
3.4
MB91461
Data Structure
This section describes the data structure of the FR family.
■ Bit Ordering
The FR family uses little endian bit ordering. Figure 3.4-1 shows the data assignment of the bit ordering.
Figure 3.4-1 Data Assignment of Little Endian Bit Ordering
bit
31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
0
MSB
LSB
■ Byte Ordering
The FR family uses big endian byte ordering.
Figure 3.4-2 shows the data assignment of the byte ordering.
Figure 3.4-2 Data Assignment of Big Endian Byte Ordering
Memory
MSB
bit 31
23
15
7
LSB
0
10101010B 11001100B 11111111B 00010001B
bit
7
0
n Address 10101010B
(n+1) Address 11001100B
(n+2) Address 11111111B
(n+3) Address 00010001B
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CHAPTER 3 CPU
3.4 Data Structure
MB91461
■ Word Alignment
● Program access
Programs used for the FR family must be located at addresses that are multiples of two.
Bit0 of the PC is set to "0" when the PC is updated as part of instruction execution.
Bit0 can become "1" only when an odd-numbered address is specified as a branch destination address.
However, even if bit0 is "1", the bit0 value is ignored and instructions must be located at addresses that are
multiples of two.
There is no odd-numbered address exception.
● Data access
The address for data access in the FR family is forcibly aligned as shown below, depending on the data
access size.
Word access:
Address is a multiple of 4. (The lowest two bits are forcibly set to 00B.)
Halfword access:
Address is a multiple of 2. (The lowest bit is forcibly set to "0").
Byte access:
————
In word or halfword data access, it is the effective address that may have bits forcibly set to "0".
For example, in the @(R13, Ri) addressing mode, the register values prior to the addition are used without
change (even if the LSB is "1") and the lower bit of the addition result is masked. The register values
before the calculation are not masked.
[Example] LD @(R13, R2), R0
R13
00002222H
R2
00000003H
+)
Result of addition
Address pin
CM71-10159-2E
00002225H
Lower two bits forcibly masked
00002224H
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CHAPTER 3 CPU
3.5 Memory Map
3.5
MB91461
Memory Map
This section describes the memory map of the FR family.
■ Memory Map
The address space is 32-bit long and linear.
Figure 3.5-1 shows the memory map.
Figure 3.5-1 Memory Map
0000 0000H
Byte data
0000 0100H
Halfword data
Direct addressing area
0000 0200H
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
Initial area
FFFF FFFFH
Direct addressing area
The following areas of the address space are I/O areas that can be accessed by direct addressing.
Address operands can be specified directly in instructions.
The size of directly addressable address areas depends on the length of the data being accessed.
Byte data (8 bits):
000H to 0FFH
Halfword data (16 bits):
000H to 1FFH
Word data (32 bits):
000H to 3FFH
Initial vector table area
The area between 000FFC00H and 000FFFFFH is the initial EIT vector table area.
The vector table used in EIT processing can be set to a user-specified address by changing the time base
register (TBR). However, after initialization at reset, the vector table is located in this area.
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CHAPTER 3 CPU
MB91461
3.6
Branch Instructions
3.6 Branch Instructions
This section describes the branch instructions of the FR family.
■ Overview of the Branch Instructions
In the FR family, you can specify whether branch instructions operate with or without a delay slot.
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CHAPTER 3 CPU
3.6 Branch Instructions
3.6.1
MB91461
Branch Instructions with a Delay Slot
This section describes branch instructions with a delay slot.
■ Branch Instructions with a Delay Slot
The instructions with the notation listed below perform the branch operation with a delay slot.
JMP:D
@Ri
CALL:D label12
CALL:D
@Ri
RET:D
BRA:D
label9
BNO:D
label9
BEQ:D
label9
BNE:D
label9
BC:D
label9
BNC:D
label9
BN:D
label9
BP:D
label9
BV:D
label9
BNV:D
label9
BLT:D
label9
BGE:D
label9
BLE:D
label9
BGT:D
label9
BLS:D
label9
BHI:D
label9
■ Description of the Branch Operation with a Delay Slot
Branching with a delay slot means that the branch operation occurs after executing the instruction placed
immediately after the branch instruction (in what is called the delay slot).
As the instruction in the delay slot is executed before the branch operations, the apparent execution speed is
one cycle. However, if no useful instruction can be placed in the delay slot, a NOP instruction must be
placed instead.
[Example]
; Instruction sequence
ADD
R1, R2
;
BRA:D
LABEL
; Branch instruction
MOV
R2, R3
; Delay slot: Executed before branching
···
LABEL:ST R3, @R4
; Branch destination
For conditional branch instructions, the instruction in the delay slot is executed whether or not the branch
condition is satisfied.
Although delayed branch instructions appear to reverse the execution order of some instructions, this only
applies to the updating of the program counter (PC). Other operations (such as updating or referencing
registers) are executed in the order they appear in the program.
The following describes some specific examples.
1) The value of Ri referenced by the JMP:D @Ri or CALL:D @Ri instruction is not changed by any
update of Ri by the instruction in the delay slot.
[Example]
LDI:32 #Label, R0
JMP:D @R0
LDI:8
#0,
; Branch to Label
R0 ; Does not change the branch destination address.
···
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CHAPTER 3 CPU
3.6 Branch Instructions
MB91461
2) The value of RP referenced by the RET:D instruction is not changed by any update of RP by the
instruction in the delay slot.
[Example]
RET:D
MOV
; Branch to the address previously set in RP.
R8,
RP ; Does not affect the return operation.
···
3) The flags referenced by the Bcc:D rel instruction are not affected by the instruction in the delay slot.
[Example]
ADD
#1,
R0 ; Flag change
BC:D
Overflow ; Branch depending on the result of the previous instruction
AND CCR #0
; This flag update does not reference the above branch instruction.
···
4) Referencing the RP by the instruction in the CALL:D instruction’s delay slot reads the RP value
updated by the CALL:D instruction.
[Example]
CALL:D Label
MOV
RP,
; Update RP and branch.
R0 ; Transfers the RP value resulting from the execution of the above CALL:D.
···
■ Restrictions on the Operation with a Delay Slot
Instructions that can be placed in the delay slot
Only instructions that meet the following criteria can be executed in the delay slot.
1-cycle instruction
Not a branch instruction
Instruction not affected by the order in which it is executed
"One-cycle instructions" are instructions with "1", "a", "b", "c", or "d" listed in the number of cycles
column of the instruction list.
Step trace trap
Step trace traps do not occur between execution of branch instructions with a delay slot and the delay
slot.
Interrupts/NMI
Interrupts and NMI are not accepted between execution of branch instructions with a delay slot and the
delay slot.
Undefined instruction exception
If the delay slot contains an undefined instruction, the undefined instruction exception is not generated.
In this case, the undefined instruction is executed as a NOP instruction.
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CHAPTER 3 CPU
3.6 Branch Instructions
3.6.2
MB91461
Branch Instructions without a Delay Slot
This section describes the branch instructions without a delay slot.
■ Instructions without a Delay Slot
The instructions with the notation listed below perform the branch operation without a delay slot.
JMP
@Ri
CALL
label12
CALL
@Ri
RET
BRA
label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE
label9
BGT
label9
BLS
label9
BHI
label9
■ Description of Operation without a Delay Slot
Branching without a delay slot means that instructions are always executed in the order they appear in the
program.
The instruction following the branch instruction is never executed before branching.
[Example]
; Instruction sequence
ADD
R1, R2
;
BRA
LABEL
; Branch instruction (without a delay slot)
MOV
R2, R3
; Not executed
R3, @R4
; Branch destination
···
LABEL: ST
The number of cycles required to execute a branch instruction without a delay slot is two cycles if the
branch occurs and one cycle if the branch does not occur.
As no instruction can be placed in the delay slot for a branch instruction without a delay slot, instruction
code efficiency is increased compared with a branch instruction with a delay slot containing a NOP
instruction.
Use operation with a delay slot when there is a useful instruction to place in the delay slot and do not use
operation with a delay slot otherwise. This satisfies both execution speed and code efficiency.
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CHAPTER 3 CPU
3.7
MB91461
3.7
EIT (Exception, Interrupt, and Trap)
EIT (Exception, Interrupt, and Trap)
The term EIT is a generic term for exceptions, interrupts and traps. EITs interrupt
execution of the current program when an event occurs and pass control to another
program.
Exceptions are generated based on the execution context. Execution restarts from the
instruction that caused the exception.
Interrupts are generated independently of the execution context. The event is caused by
hardware.
Traps are generated based on the execution context. These include traps generated by
an operation within the program like a system call. Execution restarts from the
instruction following the instruction that caused the trap.
■ EIT Features
• Multiple interrupt support
• Level mask function for interrupts (15 levels are available to the user.)
• Trap instruction (INT)
• EITs for activating the emulator (hardware/software)
■ EIT Triggers
The following items can generate an EIT.
• Reset
• User interrupt (internal resources, external interrupts)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absent trap
• Coprocessor error trap
Note:
There are restrictions on the delay slot of branch instructions regarding EITs. For more details, see
"3.6 Branch Instructions".
■ Returning from EIT
To recover from EIT, issue RETI instruction.
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CHAPTER 3 CPU
3.7 EIT (Exception, Interrupt, and Trap)
3.7.1
MB91461
EIT Interrupt Levels
Interrupt levels have the range 0 to 31 and are managed as a 5-bit value.
■ EIT Interrupt Levels
Table 3.7-1 lists the interrupt levels.
Table 3.7-1 Interrupt Levels
Level
Interrupt source
Binary
Decimal
00000B
0
(System reserved)
···
···
···
···
···
···
00011B
3
(System reserved)
00100B
4
00101B
5
(System reserved)
···
···
···
···
···
···
01110B
14
(System reserved)
01111B
15
NMI (for the user)
10000B
16
Interrupt
10001B
17
Interrupt
···
···
···
···
···
···
11110B
30
Interrupt
11111B
31
—
{
Remarks
If the original value of the ILM is between 16
and 31, values in this range cannot be set to the
ILM by the program.
INTE instruction
Step trace trap
When set to the ILM, user interrupts are
disabled.
When set to the ICR, the interrupt is disabled.
Levels 16 to 31 are available for the user.
The undefined instruction exception, coprocessor absent trap, coprocessor error trap, and INT instruction
are not affected by the interrupt level. Similarly, they do not change the ILM.
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3.7 EIT (Exception, Interrupt, and Trap)
MB91461
■ I Flag
This flag enables or disables interrupts. It is located in bit4 of the CCR in the PS.
Table 3.7-2 I Flag
Value
Function
0
Interrupts disabled
Cleared to "0" by the INT instruction
(However, the value saved on the stack is the value before the bit is cleared).
1
Interrupts enabled
Masking of interrupt requests is controlled by the value in ILM.
■ ILM
The ILM register is located in the PS register (bit20 to bit16) and stores the interrupt level mask value.
Only interrupt requests to the CPU with an interrupt level that has a higher priority than the level in the
ILM are accepted.
Level 0 (00000B) has the highest priority and level 31 (11111B) has the lowest priority.
Restrictions apply to the values that can be set by the program. When the original value is between 16 and
31, only new values between 16 and 31 can be set. Executing an instruction to set a value between 0 and 15
transfers the value "specified value + 16".
If the original value is between 0 and 15, any value between 0 and 31 can be set. The ST ILM instruction is
used to set any value.
■ Level Mask for Interrupts/NMI
When an NMI or interrupt request occurs, the interrupt level of that interrupt source (Refer to Table 3.7-1)
is compared with the level mask value held in the ILM. If the following condition is satisfied, the interrupt
is masked and the request not accepted:
Interrupt level of interrupt source ≥ Level mask value
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CHAPTER 3 CPU
3.7 EIT (Exception, Interrupt, and Trap)
3.7.2
MB91461
Interrupt Control Register (ICR)
These are registers located in the interrupt controller and set the level for each interrupt
request. The Interrupt Control Register (ICR) registers are provided for each interrupt
request input. The Interrupt Control Register (ICR) registers are mapped in the I/O
memory space and are accessed by the CPU via the bus.
■ Interrupt Control Register (ICR) Bit Structure
Figure 3.7-1 shows the bit structure of the interrupt control register (ICR).
Figure 3.7-1 The Bit Structure of the Interrupt Control Register (ICR)
bit
7
6
5
4
3
2
1
0
−
−
−
−
−
−
ICR4
R
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
Initial value
---111111B
[bit4] ICR4
Always "1".
[bit3 to bit0] ICR3 to ICR0
These are the lower 4 bits of the interrupt level for the interrupt request. They are readable and writable.
Including bit4, an Interrupt Control Register (ICR) can have values in the range 16 to 31.
■ ICR Mapping
Table 3.7-3 lists the interrupt source, interrupt control register and interrupt vector.
Table 3.7-3 Interrupt Source, Interrupt Control Register and Interrupt Vector
Interrupt Control Register
Interrupt
Source
IRQ00
IRQ01
IRQ02
IRQ03
···
···
IRQ126
IRQ127
Corresponding Interrupt Vector
No.
No.
Address
ICR00
00000440H
ICR01
00000441H
···
···
ICR63
0000047FH
Address
Hexadecimal
Decimal
10H
16
TBR+3BCH
11H
17
TBR+3B8H
12H
18
TBR+3B4H
13H
19
TBR+3B0H
···
···
···
···
···
···
3DH
142
TBR+1C4H
8FH
143
TBR+1C0H
• TBR initial value: 000FFC00H
• For more details, see "CHAPTER 10 INTERRUPT CONTROLLER".
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CHAPTER 3 CPU
3.7 EIT (Exception, Interrupt, and Trap)
MB91461
3.7.3
System Stack Pointer (SSP)
The System Stack Pointer (SSP) is used as the pointer to the stack used to save and
restore data on receiving or returning from an EIT.
■ System Stack Pointer (SSP)
Figure 3.7-2 shows the structure of the system stack pointer (SSP).
Figure 3.7-2 The Structure of the System Stack Pointer (SSP)
bit 31
0
Initial value
00000000H
SSP
The value of the System Stack Pointer (SSP) is decremented by 8 by EIT processing and incremented by 8
on returning from the EIT by the RETI instruction.
It is initialized to 00000000H at reset.
When the S flag in the CCR is "0", the System Stack Pointer (SSP) can also function as R15 generalpurpose register.
■ Interrupt Stack
This is the area pointed to by the SSP and used to save and restore the PC and PS values.
After an interrupt occurs, the PC is placed at the address pointed to by SSP and the PS at the address
"SSP+4".
Figure 3.7-3 shows the interrupt stack.
Figure 3.7-3 Interrupt Stack
[Before interrupt]
SSP
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
CM71-10159-2E
80000000H
7FFFFFFCH
7FFFFFF8H
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PS
PC
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3.7 EIT (Exception, Interrupt, and Trap)
3.7.4
MB91461
Table Base Register (TBR)
This register indicates the top address of the EIT vector table.
■ Table Base Register (TBR)
Figure 3.7-4 shows the structure of the table base register (TBR).
Figure 3.7-4 The Structure of the Table Base Register (TBR)
bit 31
0
Initial value
000FFC00H
TBR
The vector address for each EIT is calculated by adding the offset value for that EIT to the Table Base
Register (TBR).
It is initialized to 000FFC00H at reset.
■ EIT Vector Table
The 1 Kbyte area starting from the address pointed to by TBR is the EIT vector area.
Each vector consists of four bytes. The following formula shows the relationship between the vector
number and vector address.
vctadr = TBR + vctofs
= TBR + (3FCH − 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct:
Vector number
The lower 2 bits of the addition result are always treated as 00B.
The initial vector table area after a reset is the area between 000FFC00H and 000FFFFFH.
Special functions are assigned to some vectors. 000FFFFCH and 000FFFF8H are always assigned to the
reset vector and mode vector respectively, even if the TBR value is modified.
Maskable factors are determined by each model. For the vector table designed, see the interrupt vector table
shown in "Table C-1".
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MB91461
3.7.5
Multiple EIT Processing
3.7 EIT (Exception, Interrupt, and Trap)
When more than one EIT occurs at the same time, the CPU repetitively performs the
following operations: select one EIT to accept, execute the EIT sequence, and then
detect the next EIT.
The CPU executes the handler instructions for the last EIT to be accepted when EIT
detection finds no more EITs that can be accepted.
Therefore, the sequence for executing the handlers for multiple EITs that occur at the
same time is determined by the following two factors:
• The priority of the accepting EITs
• How other EITs are masked when an EIT is accepted
■ Priority of Accepting EITs
The EIT acceptance priority is the priority order for selecting which EIT to execute. The EIT sequence
consists of saving the PS and PC, updating the PC (as required), and performing masking of other EITs.
Consequently, the handler of the first EIT to be accepted is not necessarily executed first.
Table 3.7-4 lists the priority order for accepting EITs and masking of other EITs.
Table 3.7-4 Priority Order for Accepting EITs and Masking of Other EITs
Priority for
accepting EITs
CM71-10159-2E
EIT
Masking of other EITs
1
Reset
Other EITs are cleared.
2
Instruction break
Other EITs are canceled. (ILM = 4)
3
INTE instruction
Other EITs are canceled. (ILM = 4)
4
Undefined instruction exception
Other EITs are canceled. (I flag = 0)
5
INT instruction/Coprocessor exception
I flag = 0
6
User interrupt
ILM = Level of accepted EIT
7
NMI (for the user)
ILM = 15
8
NMI (for the emulator)
Other EITs are canceled. (ILM = 4)
9
Step trace trap
Other EITs are canceled. (ILM = 4)
10
Operand break
Other EITs are canceled. (ILM = 4)
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3.7 EIT (Exception, Interrupt, and Trap)
MB91461
After accepting an EIT and performing masking of other EITs, the priority for executing the handlers of
EITs that occur at the same time is as shown in Table 3.7-5.
Table 3.7-5 Execution Priority for EIT Handlers
Handler Execution
Priority
EIT
1
Reset
2
Undefined instruction exception
3
Instruction break
4
INTE instruction
5
NMI (for the emulator)
6
Step trace trap
7
Operand break
8
NMI (for the user)
9
INT instruction/Coprocessor exception
10
User interrupt
Figure 3.7-5 shows the multiple EIT processing.
Figure 3.7-5 Multiple EIT Processing
Main routine
NMI handler
INT instruction
handler
Priority
(High) NMI occurrence
(1) Execute first
(Low) INT instruction execution
(2) Execute next
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MB91461
3.7.6
EIT Operation
3.7 EIT (Exception, Interrupt, and Trap)
This section describes EIT operations.
■ EIT Operation
In the following explanation, the transfer source "PC" contains the address of the instruction at which the
EIT was detected. Also, in the operation description, the "address of the next instruction" means that the
instruction that detected the EIT was as follows.
• For LDI:32.......PC + 6
• For LDI:20, COPOP, COPLD, COPST, COPSV.......PC + 4
• For all other instructions.......PC + 2
■ Operation of User Interrupts and NMI
When a user interrupt or user NMI interrupt request is generated, the following sequence determines
whether or not the request can be accepted.
[Determining whether an interrupt request can be accepted]
1) Compare the interrupt levels of any simultaneously occurring requests and select the interrupt with
the highest priority level (smallest level value).
As for maskable interruption, the value that corresponding ICR maintains is used as a comparison
level. Moreover, the constant is decided beforehand in NMI.
2) If more than one interrupt request with the same level is generated, select the interrupt request with
the lowest interrupt number.
3) If the interrupt level ≥ the level mask value, the interrupt request is masked and not accepted.
If the interrupt level < the level mask value, proceed to 4).
4) If the selected interrupt request is a maskable interrupt and the I flag is "0", the interrupt request is
masked and not accepted. If the I flag is "1", proceed to 5).
If the selected interrupt request is an NMI, proceed to 5) regardless of the I flag value.
5) If the above conditions are satisfied, the interrupt request is accepted at the end of the current
instruction processing.
If a user interrupt or NMI request is accepted when an EIT request is detected, the CPU operates as follows,
using the interrupt number corresponding to the accepted interrupt request.
Note: ( ) represents the address that the register points to in the operation sequence below.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) Address of the next instruction → (SSP)
5) Interrupt level of the accepted request → ILM
6) "0" → S flag
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3.7 EIT (Exception, Interrupt, and Trap)
MB91461
7) (TBR + vector offset of the received interrupt request) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
After the interrupt sequence is completed, the system checks whether any new EITs are present before
executing the first instruction of the handler. If an EIT that can be accepted is present, the CPU enters the
EIT processing sequence.
If the "OR CCR", "ST ILM", or "MOV Ri, PS" instruction is executed to enable an interrupt while a user
interrupt or NMI is being generated, the above instruction may be executed twice before and after the
interrupt handler. However, this does not affect the operation, as it only set the same value twice to the
registers in the CPU.
Do not perform any operation in expectation of the contents of the PS register before EIT branching in the
EIT processing routine.
■ Operation of the INT Instruction
INT #u8 instruction operates as follows:
Branches to the interrupt handler at the vector indicated by u8.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) PC + 2 → (SSP)
5) "0" → I flag
6) "0" → S flag
7) (TBR + 3FCH-4 × u8) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
■ Operation of the INTE Instruction
INTE instruction operates as follows:
Branches to the interrupt handler pointed to by vector #9.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) PC + 2 → (SSP)
5) 00100B → ILM
6) "0" → S flag
7) (TBR + 3D8H) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
Do not use the INTE instruction during a processing routine for the INTE instruction or step trace trap.
The INTE does not generate an EIT during step execution.
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3.7 EIT (Exception, Interrupt, and Trap)
MB91461
■ Operation of the Step Trace Trap
If the T flag in the SCR of the PS is set to enable the step trace function, a trap occurs after execution of
each instruction. The trap causes execution to break.
[Conditions for detecting a step trace trap]
• T flag = 1
• Not a delayed branch instruction
• Executing anything other than the processing routine for the INTE instruction and step trace trap
If the above conditions are satisfied, a break occurs at the end of the current instruction.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) Address of the next instruction → (SSP)
5) 00100B → ILM
6) "0" → S flag
7) (TBR + 3CCH) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
The user NMI and user interrupts are disabled when the step trace trap is enabled by the T flag. Similarly,
the INTE instruction does not generate EITs.
In the FR family, a trap is generated from the instruction following the instruction in which the T flag was
set.
■ Operation of the Undefined Instruction Exception
The undefined instruction exception is generated if an undefined instruction is detected at instruction
decoding.
[Conditions for detecting an undefined instruction exception]
• An undefined instruction is detected at instruction decoding.
• The instruction is not in a delay slot (not located immediately after a delayed branch instruction).
If the above conditions are satisfied, an undefined instruction exception is generated and execution
breaks.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) PC → (SSP)
5) "0" → S flag
6) (TBR + 3C4H) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
The saved PC value is the address of the instruction that caused the undefined instruction exception.
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3.7 EIT (Exception, Interrupt, and Trap)
MB91461
■ Coprocessor Absent Trap
When a coprocessor instruction is executed to use an unmounted coprocessor, a coprocessor absent trap is
generated.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) Address of the next instruction → (SSP)
5) "0" → S Flag
6) (TBR + 3E0H) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
■ Coprocessor Error Trap
If an error occurs while using a coprocessor and then the coprocessor instruction that operates the
coprocessor is executed, a coprocessor error trap is generated.
[Operation]
1) SSP − 4 → SSP
2) PS → (SSP)
3) SSP − 4 → SSP
4) Address of the next instruction (SSP)
5) "0" → S Flag
6)(TBR + 3DCH) → PC
Note: ( ) represents the address that the register points to in the operation sequence below.
■ Operation of the RETI Instruction
The RETI instruction returns from an EIT processing routine.
[Operation]
1) (R15) → PC
2) R15 + 4 → R15
3) (R15) → PS
4) R15 + 4 → R15
Note: ( ) represents the address that the register points to in the operation sequence below.
The RETI instruction must be executed when the S flag is "0".
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CHAPTER 4
CONTROL BLOCK
This chapter describes the Control Block.
4.1 Operating Modes
4.2 Reset (Device Initialization)
4.3 Clock Generation Control
4.4 PLL Interface
4.5 Device State Control
4.6 Interval Timer
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CHAPTER 4 CONTROL BLOCK
4.1 Operating Modes
4.1
MB91461
Operating Modes
This section describes the operating modes of the FR family.
■ Overview of the Operating Modes
The FR family uses the bus mode and the access mode as its operating modes.
■ Bus Mode
The bus mode controls operations of the built-in ROM and external access function. It is set by the values
of the mode setup pins (MD2, MD1, MD0) and ROMA bit in the mode data.
■ Access Mode
This mode controls the external data bus width. It is set by the values of the WTH1 and WTH0 bits in the
mode register as well as the DBW0 bit in ACR0 to ACR3 (Area Configuration Register).
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4.1 Operating Modes
MB91461
4.1.1
Bus Mode
The following three bus modes are available to the FR family.
For more details, see "3.1 Memory Space".
■ Bus Mode 0 (Single Chip Mode)
In this mode, access to the internal I/O, ID-RAM and F-bus ROM (FLASH) is valid, but not to other areas.
The external pins function as peripheral resources or general-purpose ports. They do not function as bus
pins.
Note: This mode cannot be used for MB91461.
■ Bus Mode 1 (Built-in ROM & External Bus Mode)
In this mode, the internal I/O, ID-RAM and F-bus ROM (FLASH) are valid. Access to an externally
accessible area becomes access to external space. Some external pins function as bus pins.
Note: This mode cannot be used in MB91461.
■ Bus Mode 2 (External ROM & External Bus Mode)
In this mode, access to the internal I/O and ID-RAM is enabled but access to F-bus ROM (FLASH) is
disabled. As a result, all access can be provided for external space. Some external pins function as bus pins.
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CHAPTER 4 CONTROL BLOCK
4.1 Operating Modes
4.1.2
MB91461
Mode Setting
The operating modes of the FR family are set by the mode pins (MD2, MD1, MD0) and
mode register (MODR).
■ Mode Pins
There are three mode pins - MD2, MD1 and MD0. These pins specify how the mode vector fetch is
performed.
Table 4.1-1 shows setting for the mode vector fetch.
Table 4.1-1 Setting for the Mode Vector Fetch
Mode Pins
Mode Name
Reset Vector
Access Area
Remark
MD3
MD2
MD1
MD0
0
0
0
0
Built-in ROM mode vector
Internal
* Setting prohibited in MB91461
0
0
0
1
External ROM mode vector
External
Bus width specified by the mode register
*: Always set MD3 at "0". However, settings that are not listed in the table are prohibited.
Note:
The FR family does not support the external mode vector fetch by a multiplexed bus.
■ Mode Register (MODR)
The data to be written to the mode register by the mode vector fetch is called mode data. For the mode
vector fetch, see "4.2.3 Reset Sequence".
After an operating mode has been set in the mode register (MODR), the device operates in this operating
mode.
MODR is set by all types of reset. User programs cannot write data to MODR.
Reference:
Traditionally, no data is present at the addresses 000007FFH of the mode register when using in the
FR family.
Rewriting is enabled in the emulator mode. Use 8-bit data transfer instructions in this mode.
16-bit and 32-bit transfer instructions cannot write data.
Figure 4.1-1 shows the details of the mode register.
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CHAPTER 4 CONTROL BLOCK
4.1 Operating Modes
MB91461
[Details of the mode register]
Figure 4.1-1 Details of the Mode Register
MODR
Address: bit
000FFFF8H
7
6
5
4
3
0
0
0
0
0
2
1
0
ROMA WTH1 WTH0
Initial value
XXXXXXXXB
[bit7 to bit3] Reserved bits
Always set these bits to 00000B.
Operation is not guaranteed when other values are set.
[bit2] ROMA (built-in ROM enable bit)
This bit specifies whether to validate the internal ID-RAM and F-bus ROM (FLASH) areas.
ROMA
Function
Remark
0
External
ROM mode
Validates the Internal ID-RAM. The built-in ROM area
(40000H to FFFFFH) becomes an external area.
1
Built-in
ROM mode
Validates the Internal ID-RAM and F-bus ROM (FLASH).
Note: Set "0" in MB91461.
[bit1, bit0] WTH1 and WTH0 (bus width setting bits)
These bits set the bus width that is valid when the external bus mode is selected.
When the external bus mode is in use, the values are set at BW1 and BW0 bits of AMD0 (CS0 area).
Table 4.1-2 Function
WTH1
WTH0
Function
Remark
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
-
Setting disabled
1
1
Single chip mode
Single chip mode
Note: The single chip mode cannot be used in MB91461.
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CHAPTER 4 CONTROL BLOCK
4.1 Operating Modes
MB91461
Note:
It is necessary to store the mode data to set it to the mode vector into 000FFFF8H as byte data.
Because the big endian is used as byte endian in the FR family, please store the mode data into
MSB of bit31 to bit24 as shown in Figure 4.1-2 .
Figure 4.1-2 Notes of Mode Data
Error
bit 31
24 23
16 15
8 7
000FFFF8H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
bit 31
Correct 000FFFF8H
000FFFFCH
68
0
MODR
24 23
16 15
8 7
0
XXXXXXXX
XXXXXXXX
XXXXXXXX
MODR
B
B
B
Reset Vector
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CM71-10159-2E
CHAPTER 4 CONTROL BLOCK
MB91461
4.2
Reset (Device Initialization)
4.2 Reset (Device Initialization)
This section describes reset operations that initialize the devices of MB91461.
■ Overview of Reset (Device Initialization)
When a reset source occurs, the device stops operations of all programs and hardware and performs
initialization. This state is called reset state.
When the reset source is released, the device restarts the program and hardware operations from the initial
state. The series of operations from this reset state through the start of program and hardware operations is
called reset sequence.
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CHAPTER 4 CONTROL BLOCK
4.2 Reset (Device Initialization)
4.2.1
MB91461
Reset Level
The reset operation is divided into two levels. The occurrence factor and initialization
type of each reset differ.
This section describes these two reset levels.
■ Setting Initialization Reset (INIT)
The most powerful reset level, which initializes all settings, is called setting initialization reset (INIT).
The following items are initialized by INIT.
[Items that are initialized by INIT]
Device operating mode (bus mode and external bus width settings)
All settings related to internal clocks (clock source selection, PLL control, division ratio settings)
All settings related to the CS0 area of the external bus
All settings related to the status of other pins
All settings to be initialized by operation initialization reset (RST)
For details, see the description of each function.
After power-on, always execute INIT at the INITX pin.
■ Operation Initialization Reset (RST)
The normal reset level, which initializes program operation, is called operation initialization reset (RST).
RST occurs at the same time as INIT.
The following items are initialized by RST.
[Items that are initialized by RST]
Program operation
CPU and internal bus
Register settings of peripheral circuits
I/O port settings
All settings related to the CS0 area of the external bus
For details, see the description of each function.
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4.2 Reset (Device Initialization)
MB91461
4.2.2
Reset Source
This section describes the reset sources and the reset levels to be generated.
Past reset sources can be obtained by reading the reset source register (RSRR). (For
details of the registers and flags appearing in each description, see "4.3.5 Block
Diagram of Clock Generation Control Block" and "4.3.6 Registers in the Clock
Generation Control Block").
■ INITX Pin Input (Setting Initialization Reset Pin)
The INITX pin is an external pin that functions as a setting initialization reset pin.
A setting initialization reset (INIT) request is generated when a "L" level signal is input to the INITX pin.
The INIT request is released by inputting a "H" level signal to the INITX pin.
When INIT is generated by a request from this pin, the INIT bit (bit15) in RSRR (reset source register) is
set. INIT generated by this request is the most powerful reset of all reset sources and takes priority over all
inputs, operations, and status.
Always execute INIT at the INITX pin immediately after power-on. Also retain a "L" level input to the
INITX pin to secure the oscillation stabilization wait time of the requested oscillation circuit. (Executing
INIT at the INITX pin initializes the set oscillation stabilization wait time to the minimum value.)
Occurrence source:
"L" level input to the external INITX pin
Release source:
"H" level input to the external INITX pin
Occurrence level:
Setting initialization reset (INIT)
Corresponding flag: INIT bit (bit15)
■ Writing to the SRST Bit in STCR (Software Reset)
A software reset request occurs when "0" is written to the SRST bit (bit4) of the standby control register
(STCR).
The software reset request is an operation initialization reset (RST) request.
The software reset request is released when that request is accepted and RST is generated.
When the software reset request generates RST, the SRST bit (bit11) in RSRR is set.
When the SYNCR bit (bit9) in the time-base counter control register (TBCR) is set, RST is not generated
by the software reset request until all bus access stops.
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For this reason, it may take a long time until RST is generated, depending on the bus usage status.
Occurrence source:
Writing "0" to the SRST bit (bit4) in STCR
Release source:
Operation initialization reset (RST) generated
Occurrence level:
Operation initialization reset (RST)
Corresponding flag: SRST bit (bit11)
■ Watchdog Reset
Writing data to the watchdog timer control register (RSRR) starts the watchdog timer. If A5H and 5AH are
not written subsequently to the watchdog reset occurrence delay register (WPR) within the cycle set by the
WT1 and WT0 bits (bit9 and bit8) in the RSRR, a watchdog reset request occurs.
The watchdog reset request is the setting initialization reset (INIT) request. When INIT or RST occurs, the
accepted watchdog reset request is released.
If INIT is generated by the watchdog reset request, the WDOG bit (bit13) in the reset source register
(RSRR) is set.
If INIT is generated by the watchdog reset request, the set oscillation stabilization wait time is not
initialized.
Occurrence source:
Elapse of set watchdog timer cycle
Release source:
Generation of setting initialization reset (INIT) or operation initialization reset
(RST)
Occurrence level:
Setting initialization reset (INIT)
Corresponding flag: WDOG bit (bit13)
■ Hardware Watchdog Reset
The hardware watchdog timer starts immediately after INITX is released. INIT is issued when the counter
overflows after the timer remains uncleared for a certain amount of time.
Occurrence source:
Elapse of set hardware watchdog timer cycle
Release source:
Generation of setting initialization reset (INIT) or operation initialization reset
(RST)
Occurrence level:
Setting initialization reset (INIT)
Corresponding flag: HWDCS bit (bit10)
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4.2.3
Reset Sequence
4.2 Reset (Device Initialization)
When the reset source is released, the device starts execution of the reset sequence.
The reset sequence operation differs for each reset level.
This section describes such operation at the different levels.
■ Setting Initialization Reset (INIT) Release Sequence
When the setting initialization reset (INIT) request is released, the device executes the following operations
in sequence:
1) Releases INIT and switches the oscillation stabilization waiting state
2) Retains operation initialization reset (RST) state during oscillation stabilization wait time (bit3 and
bit2: OS1 and OS0 in STCR) and stops the internal clock
3) Sets RST and starts internal clock operation
4) Releases RST and switches to the normal operation state
5) Reads mode vector from address 000FFFF8H
6) Writes the mode vector to the mode register (MODR) at address 000007FDH
7) Reads reset vector from address 000FFFFCH
8) Writes the reset vector to the program counter (PC)
9) Starts program operation at the address indicated by PC
■ Operation Initialization Reset (RST) Release Sequence
When the RST request is released, the device executes the following operations in sequence:
1) Releases RST and switches to the normal operation state
2) Reads mode vector from address 000FFFF8H
3) Writes the mode vector to the mode register (MODR) at address 000007FDH
4) Reads reset vector from address 000FFFFCH
5) Writes the reset vector to the program counter (PC)
6) Starts program operation at the address indicated by PC
Note:
As for the reset generated at a time other than stop and shutdown, some RAM contents may be
destroyed.
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4.2.4
MB91461
Oscillation Stabilization Wait Time
The device automatically switches to the oscillation stabilization wait state when it
returns from a state in which the original oscillation stopped, or may have stopped.
This function disables use of unstable oscillator output after oscillation has started.
During the oscillation stabilization wait time, supply of internal and external clock stops
and only the built-in time-base counter operates. The device waits for the elapse of the
stabilization wait time set by the standby control register (STCR).
This section details the oscillation stabilization wait operation.
■ Oscillation Stabilization Wait Factors
The oscillation stabilization wait factors are shown below.
● When setting initialization reset (INIT) is released
Immediately after INIT has been released by various factors, the device switches to the oscillation
stabilization wait state.
After the oscillation stabilization wait time has elapsed, the device switches to operation initialization
reset (RST) state.
● At return from the stop mode
Immediately after the stop mode has been released, the device switches to the oscillation stabilization
wait state. However, if the stop mode is released by the setting initialization reset (INT) request, the
device switches to the INIT state. It switches to the oscillation stabilization wait state after INIT has
been released.
After the oscillation stabilization wait time has elapsed, the device switches to the state corresponding
to the stop mode release factor.
At return due to input of valid external interrupt request (including NMI): The device switches to the
normal operation state.
At return due to the INIT request: The device switches to RST state.
● At return due to error state occurrence when PLL is selected
If a PLL control error (*) occurs when the PLL is operating as a source clock, the device automatically
switches to the oscillation stabilization wait time to secure the PLL lock time.
After the oscillation stabilization wait time has elapsed, the device switches to the normal operation
state.
(*): Change of multiply rate during use of PLL and PLL operation enable bit error, etc.
● When a hardware watchdog reset occurs
When a hardware watchdog reset occurs, internal reset is issued during 1024 cycles of the original
oscillation clock. As the internal reset sets the OS1 and OS0 bits of the STCR to "0" (initial value),
oscillation stabilization wait is not performed.
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● At return from the shutdown mode
Immediately after the shutdown mode has been released, the device switches to the oscillation
stabilization wait state. However, if the shutdown mode is released by the setting initialization reset
(INIT) request, the device switches to the INIT state. It switches to the oscillation stabilization wait
state after INIT has been released.
A signal from the external oscillator or the internal oscillation circuit that is divided by 218 is used as
the oscillation stabilization wait time.
■ Selection of Oscillation Stabilization Wait Time
The built-in time-base counter is used to count the oscillation stabilization wait time.
When the device switches to the oscillation stabilization wait state because an oscillation stabilization wait
factor occurs, the built-in time-base counter starts counting the oscillation stabilization wait time after it has
been initialized once.
The OS1 and OS0 bits (bit3 and bit2) in the standby control register (STCR) can be used to select and set
one of the four oscillation stabilization wait times.
The set oscillation stabilization wait time can be initialized by setting initialization reset (INIT) at the
external INITX pin, return from the shutdown mode, or hardware watchdog reset. At other resets such as
the INIT by watchdog reset and the operation initialization reset (RST), the oscillation stabilization wait
time that was set before the reset is held.
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4.2.5
MB91461
Reset Operation Modes
Operation initialization reset (RST) usually supports two modes: ordinary
(asynchronous) reset mode, and synchronous reset mode. Use the SYNCR bit (bit9) in
the time-base counter control register (TBCR) to select the mode.
The set reset mode can be initialized only by the setting initialization reset (INIT).
INIT is always executed asynchronously.
This section describes operations of these reset modes.
■ Ordinary Reset Operation
Immediate switching to the RST state when the RST request occurs is called ordinary reset.
When the RST request is accepted in the ordinary reset mode, the device immediately switches to the RST
state, regardless of the internal bus access state.
The result of bus access being performed when this mode switches to another mode is not guaranteed.
However, the bus access request is always accepted.
When the SYNCR bit (bit9) in the TBCR is "0", the device operates in the ordinary reset mode.
The initial value after INIT has occurred is the ordinary reset mode.
■ Synchronous Reset Operation
Switching to the RST state after all bus accesses have stopped when the RST request occurs is called
synchronous reset.
Even if the RST request is accepted in the synchronous reset mode, the device does not switch to the RST
state if the internal bus is being accessed.
When the above request is accepted, a sleep request is issued to the internal buses. When each bus stops
operation and switches to the sleep state, the device switches to the RST state.
All bus accesses stop when the synchronous reset mode switches to another mode and the results of all bus
accesses are guaranteed.
However, if bus access does not stop for some reason, each request cannot be accepted. (Even in this case,
INIT becomes valid immediately.)
Bus access does not stop in the following cases:
Reference:
• The DMA controller does not delay device switching to each state because it stops transfer when
it receives a request.
• When the SYNCR bit (bit9) in the TBCR is "1", it indicates the synchronous reset mode.
• For using software reset on the synchronous mode, see the limitations of the bit9:SYNCR bit of
TBCR (time-base timer counter control register).
After INIT has occurred, the initial value returns to the ordinary reset mode.
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4.3
Clock Generation Control
4.3 Clock Generation Control
This section describes clock generation control.
■ Internal Clock Generation
The internal clocks are generated as shown below.
Source clock:
This clock is generated by dividing a signal from the X0 or X1 pin, or a signal from the internal
oscillation circuit by two.
Base clock generation:
The base clock is generated by selecting either the source clock divided by 2 or the PLL oscillation
clock.
Generation of each internal clock:
Dividing the base clock generates four different types of operating clocks to be supplied to different
parts of the device.
Generation and control of each clock is described below.
For details of the registers and flags in the following descriptions, see "4.3.5 Block Diagram of Clock
Generation Control Block" and "4.3.6 Registers in the Clock Generation Control Block".
■ Selection of Clock
This section describes selection of the source clock.
The source clock is generated by connecting the resonator to pins X0 and X1 (external oscillation pins),
oscillating using the internal oscillation circuit, and then dividing this signal by two.
All clocks including the external bus clock are supplied by MB91461 itself.
An internal base clock is generated by selecting one of the following clocks:
• Source clock divided by two
• Clock generated by using PLL to multiply the clock that is directly input from the internal oscillation
circuit or pins X0 and X1.
Clock selection is controlled by the setting of the clock source control register (CLKR).
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4.3.1
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PLL Control
Operation (oscillation) enable/disable and multiply rate settings can be controlled for
PLL oscillation circuits corresponding to the main clock.
Such settings are controlled by setting the clock source control register (CLKR),
PLLDIVM and PLLDIVN (multiply rate setting registers). This section describes control
of these PLL settings.
■ Enabling PLL Operation
Oscillation enable/disable for the main PLL is controlled according to the setting of the PLL1EN bit (bit10)
in the CLKR.
PLL1EN is initialized to "0" after setting initialization reset (INIT) has been executed and PLL oscillation
is stopped. When PLL oscillation is stopped, PLL output cannot be selected as the source clock.
When program operation is started, fist, set the multiply rate for the PLL and enable PLL oscillation. Then,
switch the clock after the PLL lock wait time has elapsed. In this case, the time-base timer interrupt should
be used to indicate the end of the PLL lock wait time.
When PLL output is selected as the base clock, the PLL operation cannot be stopped (write operations to
the corresponding register is ignored). Before stopping the PLL e.g. when the device switches to the stop
mode, reselect the source clock divided by two as the base clock.
When the OSCD1 and OSCD2 bits (bit0 and bit1) in the standby control register (STCR) are set so that
oscillation stops in the stop mode, the PLLs also automatically stop when the device switches to the stop
mode. When the device subsequently returns from the stop mode, the PLLs automatically start oscillation.
When these bits are set so that oscillation does not stop in the stop mode, the PLLs do not stop
automatically. In this case, if required, set operation to stop before the device switches to the stop mode.
■ PLL Multiply Rate
The PLL multiply rate is set by the PLLDIVM and PLLDIVN registers.
All bits of both registers are initialized to "0" after setting initialization reset (INIT) has been executed.
[PLL multiply rate setting]
To change the PLL multiply rate setting to its initial value, set the rate after starting program operation
or before enabling PLL operation. After modifying the multiply rate, switch the source clock to PLL
clock when the lock wait time has elapsed. In this case, the time-base timer interrupt should be used to
indicate that the PLL lock wait time is over.
When changing the PLL multiply rate setting during operation, first, switch the source clock to a clock
other than the appropriate PLL. After changing the multiply rate, switch the source clock back to PLL
clock, as described above, when the lock wait time has elapsed.
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4.3.2
Oscillation Stabilization Wait Time and PLL Lock Wait
Time
When a clock selected as the source clock is not in a stable operating state, oscillation
stabilization wait time is required. (See "4.2.4 Oscillation Stabilization Wait Time".)
After PLLs start operation, lock wait time is required until the output stabilizes to the set
frequency level.
This section describes wait time in each case.
■ Wait Time after Power-on
After power-on, it is necessary to input a "L" level signal to the INITX pin (setting initialization reset pin).
In this state, the lock wait time need not be considered because no PLL operation is enabled.
■ Wait Time after Setting Initialization
When setting initialization reset (INIT) is released, the device switches to the oscillation stabilization wait
state. In this state, the oscillation stabilization wait time is generated internally.
In this state, the lock wait time need not be considered because no PLL operation is enabled.
■ Wait Time after PLL Operation is Enabled
When operation of the inactive PLL is enabled after program operation has started, PLL output cannot be
used before the lock wait time has elapsed.
If the PLL is not selected as the source clock, program operation can be executed even during the lock wait
time.
In this case, the time-base timer interrupt should be used to indicate that the PLL lock wait time is over.
■ Wait Time after the PLL Multiply Rate is Changed
When the multiply rate setting of the operating PLL is changed after program operation has been started,
PLL output cannot be used unless the lock wait time has elapsed.
If the PLL is not selected as the source clock, program operation can be executed even during the lock wait
time.
In this case, the time-base timer interrupt should be used to indicate that the PLL lock wait time is over.
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■ Wait Time after Return from the Stop Mode
When the device switches to the stop mode after program operation had been started, the oscillation
stabilization wait time set by the program is internally generated at cancellation of that mode.
If the oscillation circuit for the clock of the clock source is set to stop in the stop mode, the oscillation
stabilization wait time of the oscillation circuit or the lock wait time of the PLL being used, whichever is
longer, becomes necessary. Set the oscillation stabilization wait time before switching the device to the stop
mode.
When the oscillation circuit for the clock of the clock source is set not to stop in the stop mode, PLLs are
not stopped automatically. Therefore, oscillation stabilization wait time is not required unless PLLs are
stopped. Set the oscillation stabilization wait time to the minimum value before entering the stop mode.
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4.3.3
Clock Distribution
4.3 Clock Generation Control
Operating clocks for each function are created from the base clock generated from the
selected clock.
The device has three internal operating clocks. The division ratio of each of these
clocks can be set independently.
This section describes such operating clocks.
■ CPU Clock (CLKB)
The CPU clock is used by the CPU, internal memory, and internal buses.
The following circuits use the CPU clock.
• CPU
• Built-in RAM
• Bit search module
• I-bus, D-bus, X-bus, F-bus
• DMA controller
• DSU
The operable upper frequency limit is 80 MHz. Do not set combinations of multiply rate and division ratio
that exceed this upper frequency limit.
■ Peripheral Clock (CLKP)
The peripheral clock is used by peripheral circuits and peripheral buses.
The following circuits use this clock.
• Peripheral bus
• Clock control block (bus interface block only)
• Interrupt controller
• Peripheral I/O ports
• I/O port bus
• External interrupt input
• LIN-UART
• 16-bit timer
• A/D converter
• Free-run timer
• Reload timer
• Up/down counter
• Input capture
• Output compare
• I2C interface
• PPG
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The operable upper frequency limit is 20 MHz. Do not set combinations of multiply rate and division ratio
that exceed this upper frequency limit.
■ External Bus Clock (CLKT)
The external bus clock is used by the external extension bus interface.
The following circuits use the external bus clock.
• External extension bus interface
• External Clock output
The operable upper frequency limit is 40 MHz. Do not set combinations of multiply rate and division ratio
that exceed this upper frequency limit.
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4.3.4
Clock Division
4.3 Clock Generation Control
The division ratio of each internal operating clock can be set independently from the
base clock. This function enables setting of the optimum operating frequency for each
circuit.
■ Setting the Division Ratio
The division ratio is set by the basic clock division setting register 0 (DIVR0) and basic clock division
setting register 1 (DIVR1).
DIVR0 and DIVR1 each have 4 setting bits corresponding to each clock. "Register setting value + 1" is the
division ratio for the base clock. Even if the set division ratio is an odd number, the duty is always 50%.
When the register setting value is changed, the new division ratio becomes valid from the rising edge of the
next clock after setting.
■ Initializing the Division Ratio Setting
Division ratio setting is not initialized if an operation initialization reset (RST) occurs, and the division
ratio setting before RST occurs is held. The division ratio setting is initialized only when the setting
initialization reset (INIT) occurs. In the initial state, the division ratios of all clocks other than the
peripheral clock (CLKP) are "1". For this reason, always set a division ratio before changing the clock
source to a faster one.
Note:
The operable upper frequency limit is specified for each clock. Operation is not guaranteed if the
operable upper frequency limit is exceeded as a result of the combined source clock selection, PLL
multiply rate setting, and division ratio setting. Take care not to make a mistake in the change setting
sequence for source clock selection.
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4.3.5
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Block Diagram of Clock Generation Control Block
Figure 4.3-1 shows the block diagram of the clock generation control block.
For details of the registers in the diagram, see "4.3.6 Registers in the Clock Generation
Control Block".
■ Block Diagram of Clock Generation Control Block
Figure 4.3-1 Block Diagram of Clock Generation Control Block
X0
X1
Oscillation
circuit
Peripheral
clock division
Selector
External bus
clock division
Selector
CPU clock division
Stop control
Selector
DIVR0, DIVR1
Registers
CPU clock
Peripheral clock
External bus clock
CLKR Register
1/2
Source clock
Selector
R-bus
[Clock generation block]
PLL
1/2
Base clock
Hardware
Watchdog
[Stop/sleep control block]
Internal interrupt
STGR
Register
Internal reset
Stop state
State
transition
control
circuit
Sleep state
Reset
occurrence F/F
Reset
occurrence F/F
Internal reset (RST)
Internal reset (INIT)
[Reset source circuit]
INITX pin
RSRR Register
[Watchdog control block]
WPR Register
Watchdog F/F
Time-base counter
Counter clock
CTBR Register
Selector
TBCR Register
Overflow
detection F/F
Interrupt enabled
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4.3.6
Registers in the Clock Generation Control Block
This section describes the registers in the clock generation control block.
■ RSRR: Reset Source Register and Watchdog Timer Control Register
Figure 4.3-2 shows the structure of the reset source register and watchdog timer control register.
Figure 4.3-2 The Structure of the Reset Source Register and Watchdog Timer Control Register
RSRR
bit
Address: 000480H
Read/Write
Initial value (INITX pin)
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
9
8
INIT
R
1
*
X
Reserved
WDOG
R
0
*
X
Reserved
SRST
R
0
X
*
Reserved
WT1
R/W
0
0
0
WT0
R/W
0
0
0
R
X
X
X
R
X
X
X
R
X
X
X
* : Initialized depending on the reset source
X: Not initialized
RSRR is used to retain the preceding reset source, set the cycle of the watchdog timer and control the
watchdog timer start.
When this register is read, the held reset source is cleared. If a reset occurs several times before the register
is read, several reset resource flags are accumulated and set.
The watchdog timer is started when this register is written to. Watchdog timer operation continues until
RST occurs.
[bit15] INIT: External reset occurrence flag
This bit indicates whether reset (INIT) was caused by input to the INITX pin.
Table 4.3-1 External Reset Occurrence Flag
Value
Function
0
INIT not caused by input to INITX pin
1
INIT caused by input to INITX pin
This bit is cleared to "0" immediately after being read.
The bit is read only. Write does not affect other bit values.
Upon power-on, supply the "L" level to the INITX pin which is 8ms or greater. Otherwise, the flag may
not be set.
[bit14] Reserved bit
This bit is reserved.
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[bit13] WDOG: Watchdog reset occurrence flag
This bit indicates whether reset (INIT) was caused by the watchdog timer.
Table 4.3-2 Watchdog Reset Occurrence Flag
Value
Function
0
INIT not caused by watchdog timer
1
INIT caused by watchdog timer
This bit is cleared to "0" when reset (INIT) is caused by input to the INITX pin upon power-on or
immediately after it is read.
The bit is read only. Write does not affect other bit values.
[bit12] Reserved bit
This bit is reserved.
[bit11] SRST: Software reset occurrence flag
This bit indicates whether reset (RST) is caused by data write (software reset) to the SRST bit of the
STCR register.
Table 4.3-3 Software Reset Occurrence Flag
Value
Function
0
RST not caused by software reset
1
RST caused by software reset
This bit is cleared to "0" when reset (INIT) is caused by input to the INITX pin upon power-on or
immediately after it is read.
The bit is read only. Write does not affect other bit values.
[bit10] Reserved bit
This bit is reserved.
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[bit9, bit8] WT1 and WT0: Watchdog timer interval select bits
These bits are used to set the watchdog timer cycle.
Select one of the four watchdog timer cycles from the table below by writing the values to these bits.
Table 4.3-4 Watchdog Timer Interval Select Bits
Minimum writing interval to
WPR required to control
watchdog reset occurrence
Duration between last 5AH
writing to WPR and occurrence
of watchdog reset
WT1
WT0
0
0
φ × 216 [Initial value]
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
("φ" represents the base clock cycle.)
These bits are initialized to 00B at reset (RST).
They are read only. Only the first write after reset (RST) is valid and subsequent writes are invalid.
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■ STCR: Standby Control Register
Figure 4.3-3 shows the structure of the standby control register.
Figure 4.3-3 The Structure of the Standby Control Register
STCR
bit
Address: 000481H
7
6
STOP SLEEP
5
4
3
2
1
0
HIZ
SRST
OS1
OS0
Reserved
OSCD1
Read/Write
Initial value (INITX pin)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
1
Initial value (INIT)
0
0
1
1
X
X
1
1
Initial value (RST)
0
0
X
1
X
X
X
X
This register is used to control the device operating mode.
It switches toe device to the stop or sleep mode (standby mode) and controls the pins in the stop mode and
oscillation stop. It also sets the oscillation stabilization wait time and issues a software reset instruction.
Note:
When selecting a standby mode, always use the following sequence while the synchronous standby
mode is in use. The synchronous standby mode is set by the bit8: SYNCS of the time-base counter
control register (TBCR).
(LDI#value_of_standby,R0) ; "value_of_standby" represents write data to STCR
(LDI#_STCR,R12)
; "_STCR" is the STCR address (481H)
STB
; Writing to STCR
R0,@R12
LDUB @R12,R0
; Reading from STCR for synchronous standby
LDUB @R12,R0
; Dummy reading from STCR again
NOP
; NOP × 5 to adjust the timing
NOP
NOP
NOP
NOP
[bit7] STOP: STOP mode bit
This bit is used to instruct the device to switch to the stop mode. It has priority over bit6 (SLEEP bit)
when "1" is written to both bits. Therefore, the device switches to the STOP mode.
Table 4.3-5 STOP Mode Bit
Value
Function
0
The device does not switch to the stop mode [Initial value]
1
The device switches to the stop mode
This bit is initialized to "0" when reset (RST) or a stop return factor occurs.
This bit is readable and writable.
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[bit6] SLEEP: SLEEP mode bit
This bit is used to instruct the device to switch to the sleep mode. Bit7 (STOP bit) has priority over this
bit when both bits are "1". Therefore, the device switches to the stop mode.
Table 4.3-6 SLEEP Mode Bit
Value
Function
0
The device does not switch to the sleep mode [Initial value]
1
The device switches to the sleep mode
This bit is initialized to "0" when reset (RST) or a sleep return factor occurs.
This bit is readable and writable.
[bit5] HIZ: Hi-Z mode bit
This bit is used to control the pin state when the device is in the stop mode.
Table 4.3-7 Hi-Z Mode Bit
Value
Function
0
Holds the pin state before the device switches to the stop mode.
1
Sets pin output to the high-impedance state when the device is in the stop
mode [Initial value]
This bit is initialized to "1" at reset (INIT).
This bit is readable and writable.
[bit4] SRST: Software reset bit
This bit is used to issue the software reset (RST) instruction.
Table 4.3-8 Software Reset Bit
Value
Function
0
Issues the software reset instruction
1
Does not issue the software reset instruction [Initial value]
This bit is initialized to "1" at reset (RST).
This bit is readable and writable and the read value is always "1".
Note:
For using software reset on the synchronous mode, see the limitations of the bit9:SYNCR bit of
TBCR (time-base timer counter control register).
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[bit3, bit2] OS1 and OS0: Oscillation stabilization wait time select bits
These bits set the oscillation stabilization wait time after a reset (INIT) or after a return to the stop
mode.
The table below shows the combination of values written to these bits and the four associated oscillation
stabilization wait times.
Table 4.3-9 Oscillation Stabilization Wait Time Select Bits
OS1
OS0
Oscillation stabilization
wait time
When the original
oscillation is 18 MHz
0
0
φ × 21
[Initial value]
0.44 μs
0
1
φ × 211
0.46 ms
1
0
φ × 216
14.6 ms
1
1
φ × 222
0.93 s
"φ" represents the base clock cycle.
These bits are initialized to 00B at reset (INIT) caused by input to the INITX pin.
These bits are readable and writable.
[bit1] Reserved bit
This bit is reserved.
[bit0] OSCD1: Oscillation stop bit
This bit controls stop operation of the oscillation circuits in the stop mode
Table 4.3-10 Oscillation Stop Bit
Value
Function
0
Oscillation does not stop in the stop mode
1
Oscillation stops in the stop mode [Initial value]
This bit is initialized to "1" at reset (INIT).
This bit is readable and writable.
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■ TBCR: Time-base Counter Control Register
Figure 4.3-4 shows the structure of the time-base counter control register.
Figure 4.3-4 The Structure of the Time-base Counter Control Register
TBCR
bit
Address: 000482H
Read/Write
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
TBIF
R/W
0
TBIE
R/W
0
TBC2
R/W
X
TBC1
R/W
X
TBC0
R/W
X
Reserved
0
0
X
X
X
X
R/W
X
9
8
SYNCR SYNCS
R/W
R/W
0
0
X
X
This register controls time-base timer interrupts.
The register enables time-base timer interrupts and selects the interrupt interval time.
[bit15] TBIF: Time-base timer interrupt flag
This bit serves as the time-base timer interrupt flag.
The bit indicates that the interval time set by the time-base counter (set at bit13 to bit11: TBC2 to
TBC0) has passed.
When this bit is set to "1" while interrupt occurrence is enabled by the TBIE bit (bit14: TBIE = 1), a
time-base timer interrupt request is generated.
Table 4.3-11 Time-base Timer Interrupt Flag
Clearing factor
"0" written by instruction
Setting factor
Elapse of the set interval time
(falling edge of time-base counter output detected)
This bit is initialized to "0" at reset (RST).
This bit is readable and writable. However, only "0" can be written. Writing "1" does not change the bit
value.
The read value of read-modify-write (RMW) instructions is always "1".
[bit14] TBIE: Time-base timer interrupt enable bit
This bit enables output of the time-base timer interrupt request.
The bit controls the interrupt request output caused by the elapse of the interval time to which the timebase counter was set. When this bit is set to "1", a time-base timer interrupt request is generated when
bit15 (TBIF bit) is set to "1".
Table 4.3-12 Time-base Timer Interrupt Enable Bit
Value
Function
0
Disables time-base timer interrupt request output [Initial value]
1
Enables time-base timer interrupt request output
This bit is initialized to "0" at reset (RST).
This bit is readable and writable.
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[bit13 to bit11] TBC2, TBC1, TBC0: Time-base timer counter select bits
These bits set the interval time of the time-base counter used for the time-base timer.
The table below shows the combination of values written to these bits and their associated 8 intervals.
Table 4.3-13 Time-base Timer Counter Select Bits
TBC2
TBC1
TBC0
Timer interval time
When the original
oscillation is 18 MHz and
PLL is multiplied by 4
0
0
0
φ × 211
28.4 μs
0
0
1
φ × 212
56.9 μs
0
1
0
φ × 213
114 μs
0
1
1
φ × 222
58.3 ms
1
0
0
φ × 223
117 ms
1
0
1
φ × 224
233 ms
1
1
0
φ × 225
466 ms
1
1
1
φ × 226
932 ms
"φ" represents the base clock cycle.
The initial values of these bits are undefined. Always set a value before enabling an interrupt.
These bits are readable and writable.
[bit10] Reserved bit
This bit is reserved. The read value is undefined and write has no effect.
[bit9] SYNCR: Synchronous reset enable bit
This bit is a synchronous reset enable bit.
When an operation initialization reset (RST) request is generated, this bit selects an ordinary reset
operation that immediately causes a RST, or a synchronous reset operation that causes RST after all bus
access has stopped.
Table 4.3-14 Synchronous Reset Enable Bit
Value
Function
0
Causes ordinary reset operation [Initial value]
1
Causes synchronous reset operation
This bit is initialized to "0" at reset (INIT).
This bit is readable and writable. As MB91461 only supports the synchronous reset, set the bit to "1"
when writing to this register.
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Note:
Be sure to meet the following two conditions before setting "0" to the SRST bit of STCR (standby
control register) when the software reset is used on the synchronous mode.
• Set the interrupt enable flag (I) to interrupt disabled (I = 0).
• Not used NMI.
[bit8] SYNCS: Synchronous standby enable bit
This bit enables synchronous standby operation.
When generating a standby request (sleep mode request or stop mode request), this bit selects either the
ordinary standby operation in which a transition to the standby state is only caused by a write to the
control bit of the STCR register, or the synchronous standby operation in which a transition to the
standby state is caused by reading the STCR register after writing to the control bit of the STCR
register.
Table 4.3-15 Synchronous Standby Enable Bit
Value
Function
0
Performs ordinary standby operation [Initial value]
1
Performs synchronous standby operation
This bit is initialized to "0" at reset (INIT).
Note:
Always set "1" to set synchronous standby operation when transition to the standby mode.
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■ CTBR: Time-base Counter Clear Register
Figure 4.3-5 shows the structure of the time-base counter clear register.
Figure 4.3-5 The Structure of the Time-base Counter Clear Register
CTBR
bit
Address: 000483H
Read/Write
Initial value
7
6
5
4
3
2
1
0
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
X
D0
W
X
This register initializes the time-base counter.
When A5H and 5AH are written consecutively to this register, all bits of the time-base counter are cleared
to "0" immediately after a write to 5AH. There is no time restriction between the A5H write and 5AH write.
However, when data other than 5AH is written after the A5H write, the time-base counter is not cleared
even when 5AH is written unless A5H is written again.
The read value from this register is undefined.
Note:
When the time-base counter is cleared using this register, the oscillation stabilization wait interval,
watchdog timer cycle, and time-base timer cycle change temporarily.
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■ CLKR: Clock Source Control Register
Figure 4.3-6 shows the structure of the clock source control register.
Figure 4.3-6 The Structure of the Clock Source Control Register
CLKR
bit
Address: 000484H
Read/Write
Initial value (INIT)
Initial value (RST)
15
14
13
12
Reserved
Reserved
Reserved
Reserved
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
11
10
9
8
SCKEN PLL1EN CLKS1 CLKS0
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
This register selects the clock source used as the base clock for the system and controls the PLL.
This register selects one of two types of clock sources.
[bit15 to bit12] Reserved bits
These bits are reserved. Always set them to "0".
[bit11] SCKEN: Sub clock selection enable bit
This bit enables sub clock selection. Modifying the sub clock selection enable bit (SCKEN) while the
sub clock is selected as the clock source (CLKS[1:0]=11B) is prohibited (the result is not guaranteed).
Modify the setting only when the main clock is selected. (See the explanation for the clock source
selection bits (CLKS[1:0]) for details of how to change the clock source.) This bit is not installed on
MB91461. Bit 11 is a reserved bit on MB91461.
Table 4.3-16 Sub Clock Selection Enable Bit
Value
Function
0
Disables sub clock selection [Initial value]
1
Enables sub clock selection
[bit10] PLL1EN: PLL enable bit
This bit enables PLL operation.
Do not rewrite this bit when PLL is selected as the clock source. Also, do not select PLL as the clock
source when this bit is set to "0" (due to the settings of bit9 and bit8: CLKS1 and CLKS0).
If bit0:OSCD1 of the STCR is "1", PLLs stop even when this bit is set to "1" during the stop mode. The
PLL operation is enabled after returning from the stop mode.
Table 4.3-17 PLL Enable Bit
Value
Function
0
Stops PLLs [Initial value]
1
Enables PLL operation
This bit is initialized to "0" at reset (INIT). This bit is readable and writable.
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[bit9, bit8] CLKS1 and CLKS0: Clock source select bits
These bits set the clock source to be used for the device.
Two clock sources are available for selection and the values to be written to these bits are as shown in
the table below.
While CLKS1 (bit9) is "1", the value of CLKS0 (bit8) cannot be changed.
Table 4.3-18 Changing Example of Clock Source Select Bits
Unmodifiable Combination
Modifiable Combination
00B → 01B or 10B
00B → 11B
01B → 11B or 00B
01B → 10B
10B → 00B
10B → 01B or 11B
11B → 01B
11B → 00B or 10B
CLKS1
CLKS0
Clock Source Setting
0
0
Original oscillation input from X0/X1, divided by 4 [Initial value]
0
1
Original oscillation input from X0/X1, divided by 4
1
0
PLL (Main Clock)
1
1
Sub Clock (Setting disabled)
These bits are initialized to 00B at reset (INIT).
These bits are readable and writable.
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■ WPR:Watchdog Reset Generation Postponement Register
Figure 4.3-7 shows the structure of the watchdog reset generation postponement register.
Figure 4.3-7 The Structure of the Watchdog Reset Generation Postponement Register
WPR
bit
Address: 000485H
Read/Write
Initial value
7
6
5
4
3
2
1
0
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
X
D0
W
X
This register postpones generation of the watchdog reset.
When A5H and 5AH are written consecutively to this register, the detection FF of the watchdog timer is
cleared immediately after the 5AH write to postpone generation of the watchdog reset.
There is no minimum time restriction between the A5H write and the 5AH write. However, when data other
than 5AH is written after the A5H write, the detection FF of the watchdog timer is not cleared even when
5AH is written unless A5H is written again.
Table 4.3-19 shows a correlation between the watchdog reset generation interval and the RSRR register
values.
The watchdog reset is generated if writing of both data is not completed within the specified period. The
duration until watchdog reset generation and the write interval required to postpone the generation depend
on the state of WT1 (bit9) and WT0 (bit8) of the RSRR register.
Table 4.3-19 Interval of Watchdog Reset Generation
Minimum writing interval to WPR,
required for control of RSRR
watchdog reset generation
Time between last 5AH writing to
WPR and watchdog reset generation
WT1
WT0
0
0
φ × 216 [Initial value]
φ × 216 to φ × 217
0
1
φ × 218
φ × 218 to φ × 219
1
0
φ × 220
φ × 220 to φ × 221
1
1
φ × 222
φ × 222 to φ × 223
"φ" represents the base clock cycle. WT1 (bit9) and WT0 (bit8) of the RSRR register are used to set the
watchdog timer cycle.
During a time when the CPU is not operating, such as stop, sleep, and DMA transfer, clearing is performed
automatically. Therefore, when these conditions occur, the watchdog reset is postponed automatically.
However, when a hold request for the external bus (BRQ) is accepted, the watchdog reset is not postponed.
For this reason, to hold the external bus for a long period, switch to the sleep mode before inputting the
BRQ.
The read value of this register is undefined.
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■ DIVR0: Base Clock Division Setting Register 0
Figure 4.3-8 shows the structure of the base clock division setting register 0.
Figure 4.3-8 The Structure of the Base Clock Division Setting Register 0
DIVR0
bit
Address: 000486H
Read/Write
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
9
8
B3
R/W
0
X
B2
R/W
0
X
B1
R/W
0
X
B0
R/W
0
X
P3
R/W
0
X
P2
R/W
0
X
P1
R/W
1
X
P0
R/W
1
X
This register controls the base clock division ratio of each internal clock.
It sets the division ratio of the clock for the CPU and internal buses (CLKB), and the clock for peripheral
circuits and peripheral buses (CLKP).
Note:
The upper operation frequency limit is defined for each clock. Note that operation is not guaranteed if
the upper frequency limit is exceeded by a combination of the source clock selection, PLL multiply
rate setting, and division ratio setting. Take care not to make any mistakes in the setting order of
change of the source clock selection.
When this register setting is modified, the new division ratio becomes valid from the next clock rate.
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[bit15 to bit12] B3, B2, B1, B0: CLKB division select bits
These bits set the division ratio for the CPU clock (CLKB), internal memory, and internal buses.
In accordance with the combination of values written to these bits, one base clock division ratio (clock
frequency) is selected from the 16 shown in the table below for the CPU and internal bus clocks.
The operable upper frequency limit is 75 MHz. Do not set a division ratio causing a frequency that
exceeds this limit.
Clock division ratio
Clock frequency: When the original
oscillation is 18 MHz and
the PLL multiply rate is 4
B3
B2
B1
B0
0
0
0
0
φ
72.0 MHz [Initial value]
0
0
0
1
φ × 2 (2 divisions)
36.0 MHz
0
0
1
0
φ × 3 (3 divisions)
24.0 MHz
0
0
1
1
φ × 4 (4 divisions)
18.0 MHz
0
1
0
0
φ × 5 (5 divisions)
14.4 MHz
0
1
0
1
φ × 6 (6 divisions)
12.0 MHz
0
1
1
0
φ × 7 (7 divisions)
10.3 MHz
0
1
1
1
φ × 8 (8 divisions)
9.0 MHz
···
···
···
···
1
1
1
1
···
φ × 16 (16 divisions)
···
4.5 MHz
"φ" represents the base clock cycle.
These bits are initialized to 0000B at reset (INIT).
These bits are readable and writable.
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[bit11 to bit8] P3, P2, P1, P0: CLKP division select bits
These bits set the division ratio for the peripheral clock (CLKP).
They set the division ratio for the peripheral circuit and peripheral bus clocks (CLKP).
In accordance with the combination of values written to these bits, one base clock division ratio (clock
frequency) is selected from the 16 shown in the table below for the peripheral circuit and peripheral bus
clocks.
The operable upper frequency limit is 20 MHz. Do not set a division ratio causing a frequency that
exceeds this limit.
Clock division ratio
Clock frequency: When the original
oscillation is 18 MHz and
the PLL multiply rate is 4
P3
P2
P1
P0
0
0
0
0
φ
72.0 MHz
0
0
0
1
φ × 2 (2 divisions)
36.0 MHz
0
0
1
0
φ × 3 (3 divisions)
24.0 MHz
0
0
1
1
φ × 4 (4 divisions)
18.0 MHz [Initial value]
0
1
0
0
φ × 5 (5 divisions)
14.4 MHz
0
1
0
1
φ × 6 (6 divisions)
12.0 MHz
0
1
1
0
φ × 7 (7 divisions)
10.3 MHz
0
1
1
1
φ × 8 (8 divisions)
9.0 MHz
···
···
···
···
1
1
1
1
···
φ × 16 (16 divisions)
···
4.5 MHz
"φ" represents the base clock cycle.
These bits are initialized to 0011B at reset (INIT).
These bits are readable and writable.
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■ DIVR1: Base Clock Division Setting Register 1
Figure 4.3-9 shows the structure of the base clock division setting register 1.
Figure 4.3-9 The Structure of the Base Clock Division Setting Register 1
DIVR1
bit
Address: 000487H
Read/Write
Initial value (INIT)
Initial value (RST)
7
6
5
4
3
2
1
0
T3
R/W
0
X
T2
R/W
0
X
T1
R/W
0
X
T0
R/W
0
X
Reserved
Reserved
Reserved
Reserved
R/W
0
X
R/W
0
X
R/W
0
X
R/W
0
X
This register controls the base clock division ratio of each internal clock.
It sets the division ratio of the clock for the external extension bus interface (CLKT).
Note:
The upper operation frequency limit is defined for each clock. Note that operation is not guaranteed if
the upper frequency limit is exceeded by a combination of the source clock selection, PLL multiply
rate setting, and division ratio setting. Take care not to make any mistakes in the setting order of
change of the source clock selection.
When this register setting is modified, the new division ratio becomes valid from the next clock rate.
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[bit7 to bit4] T3, T2, T1, T0: CLKT division select bits
These bits set the division ratio for the external bus clock (CLKT).
They set the division ratio for the clock of the external extension bus interface (CLKT).
In accordance with the combination of values written to these bits, one base clock division ratio (clock
frequency) is selected from the 16 shown in the table below for the clock of the external extension bus
interface.
The operable upper frequency limit is 40 MHz. Do not set a division ratio causing a frequency that
exceeds this limit.
Clock division ratio
Clock frequency: When the original
oscillation is 18 MHz and
the PLL multiply rate is 4
T3
T2
T1
T0
0
0
0
0
φ
72.0 MHz [Initial value]
0
0
0
1
φ × 2 (2 divisions)
36.0 MHz
0
0
1
0
φ × 3 (3 divisions)
24.0 MHz
0
0
1
1
φ × 4 (4 divisions)
18.0 MHz
0
1
0
0
φ × 5 (5 divisions)
14.4 MHz
0
1
0
1
φ × 6 (6 divisions)
12.0 MHz
0
1
1
0
φ × 7 (7 divisions)
10.3 MHz
0
1
1
1
φ × 8 (8 divisions)
9.0 MHz
···
···
···
···
1
1
1
1
···
φ × 16 (16 divisions)
···
4.5 MHz
"φ" represents the base clock cycle.
These bits are initialized to 0000B at reset (INIT).
These bits are readable and writable.
[bit3 to bit0] Reserved bits
These bits are reserved.
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CSC3 to CSC0
Function
--00B
Real-time clock source is main clock oscillation
--01B
Real-time clock source is subclock oscillation
--10B
Real-time clock source is CR oscillation
--11B
Setting disabled
-0--B
Subclock calibration source is subclock oscillation
-1--B
Subclock calibration source is CR oscillation
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4.3.7
MB91461
Peripheral Circuits in the Clock Control Block
This section describes the peripheral circuit functions in the clock control block.
■ Time-base Counter
The clock control block has a 26-bit time-base counter that operates using base clocks.
The time-base counter is used to count the oscillation stabilization wait time (see "4.2.4 Oscillation
Stabilization Wait Time") as well as for the following uses.
Watchdog timer:
The watchdog timer for detecting malfunction of the system uses bit output of the time-base counter
for counting.
Time-base timer:
The time-base counter output is used to generate interval interrupts.
● Watchdog timer
The watchdog timer detects the system malfunction by using a time-base counter output. When the
watchdog reset generation delay is no longer caused during the set interval due to the program
malfunction, the watchdog timer generates the setting initialization reset (INIT) request as a watchdog
reset. The watchdog timer explained here is different from the hardware watchdog timer explained in
Chapter 7. It enters a stop state immediately after reset.
[Watchdog timer activation]
The watchdog timer is started by a write to the 1st RSRR (reset factor register / watchdog timer control
register) after a reset (RST).
At this point, the watchdog timer interval time is set using bit9 and bit8 (WT1 and WT0). Only the
interval time set by the first write is valid and all intervals set by succeeding writes are ignored.
[Watchdog reset generation delay]
After the watchdog timer is started, the program must write data to WPP (watchdog reset generation
delay register) regularly in the order of A5H, 5AH.
This operation initializes the watchdog reset generation flag.
[Watchdog reset generation]
The watchdog reset generation flag is set by the falling edge of the time-base counter output at the set
interval. When the flag is still set at detection of the second falling edge, the watchdog timer generates a
setting initialization reset (INIT) request as a watchdog reset.
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[Watchdog timer stop]
After the watchdog timer is started, it cannot be stopped until the operation initialization reset (RST) is
generated.
In the following conditions, where RST is generated, the watchdog timer stops and does not function
until it is restarted by the program:
- Operation initialization reset (RST) state
- Setting initialization reset (INIT) state
- Oscillation stabilization wait reset (RST) state
[Watchdog timer temporary stop (delay of automatic generation)]
When the CPU program operation is stopped, the watchdog timer initializes the watchdog reset
generation flag, delaying generation of the watchdog reset. Stop of the program operation means that
the program is in one of the following states:
- Sleep state
- Stop state
- Oscillation stabilization wait run state
- Breaking the program by using the emulator debugger or the monitor debugger
- Period from execution of INTE instruction to execution of RETI instruction
- Step trace trap
(Break per instruction with the T flag of the PS register being 1)
- Instruction cache control registers (ISIZE and ICHCR)
Data to cache memory in the RAM mode
When the time-base counter is cleared, the watchdog reset generation flag is also initialized at the same
time, delaying generation of a watchdog reset.
If the state listed above is caused by system malfunction, a watchdog reset may not be generated. In this
case, perform a reset (INIT) by using the external INITX pin.
● Time-base timer
The time-base timer is an interval interrupt generation timer that uses the output of the time-base
counter. The timer is suitable for counting a relatively long duration of up to {base clock × 226} cycles,
such as PLL lock wait time.
When the falling edge of output of the time-base counter for the set interval is detected, the time-base
timer generates a time-base timer interrupt request.
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[Time-base timer start and interval setting]
The time-base timer sets an interval time by using bit13 to bit11 (TBC2, TBC1, TBC0) of TBCR (timebase counter control register).
The falling edge of output of the time-base counter for the set interval is always detected. Therefore,
after setting an interval time, clear bit15 (TBIF bit), and then set bit14 (TBIE bit) to "1" to enable the
interrupt request output.
When changing the interval time, set bit14 (TBIE bit) to "0" in advance to disable the interrupt request
output.
The time-base counter is always counting and is not affected by these settings. To obtain an accurate
interval interrupt time, clear the time-base counter before enabling an interrupt. When not clearing, an
interrupt request might occur immediately after an interrupt is enabled.
[Clearing time-base counter by program]
When data is written to CTBR, in the order of A5H, 5AH, all bits of the time-base counter are cleared to 0
immediately after 5AH is written. There are no restrictions on the time between A5H and 5AH. However,
if data other than 5AH is written after A5H is written, the counter is not cleared even when 5AH is written
unless A5H is written again.
When the time-base counter is cleared, the watchdog reset generation flag is initialized at the same time,
delaying generation of the watchdog reset.
[Clearing the time-base counter at the device state]
All bits of the time-base counter are simultaneously cleared to "0" in transition to the following device
state:
- Stop state
- Setting initialization reset (INIT) state
In the stop state, particularly, the time-base counter is used for counting the oscillation stabilization wait
time, so the time-base timer interval interrupt may be generated unintentionally.
Therefore, before setting the stop mode, disable the time-base timer interrupt, and do not use the timebase timer.
In other states, the operation initialization reset (RST) is generated, so the time-base timer interrupts are
automatically disabled.
● Interval timer
This is a 23-bit timer that is not affected by clock source selection or division setting. The interval timer
is synchronized with the source clock to count up.
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4.4
PLL Interface
This section describes PLL multiply settings.
Figure 4.4-1 shows the block diagram of PLL.
Figure 4.4-1 Block Diagram of PLL
Clock Unit
XIN1
PLL Interface
PLL
Crystal
or clock input
PLLIN
X
1/G
1/M
CK
Phase correction
M
U
X
FB
1/N
Clock Tree
CLKB
CLKP
CLKT
M
U
X
FB1 delay
■ Features
The multiply rate is determined by two dividers that are enabled to set any value ranging from 1 to 64.
Clock automatic gear up-down function preventing voltage drops and voltage surges
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4.4.1
MB91461
Registers for the PLL Interface
This section describes the registers for the PLL interface.
■ PLLDIVM: PLL Divider M
Figure 4.4-2 shows the structure of the PLL divider M.
Figure 4.4-2 The Structure of the PLL Divider M
PLLDIVM
bit
Address: 00048CH
Read/Write
Initial value
7
6
5
4
3
2
1
0
Reserved
Reserved
DVM5
DVM4
DVM3
DVM2
DVM1
DVM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PLLDIVM is one of the dividers included in the PLL feedback loop. This divider determines the PLL
multiply rate along with PLLDIVN. PLLDIVM also divides PLL oscillation output. It is used as divider
that generates a clock affecting the following clock unit.
[bit7, bit6] Reserved bits
These bits are reserved. Their read value is "0".
[bit5 to bit0] DVM5 to DVM0: PLLDIVM division setting value
The division number varies as shown below, depending on the value set to DVM5 to DVM0.
Table 4.4-1 PLLDIVM Division Setting Value
108
DVM5 to DVM0
Division No.
000000B
1 (No division)
000001B
2
000010B
3
000011B
4
000100B
5
000101B
6
000110B
7
000111B
8
······
······
111111B
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Notes:
• Although the division number can be set to "1" (no division), it is recommended to set it to "2" or
greater.
Please select an even number for the division number to ensure the duty ratio of PLL output is
50%.
• When PLL is selected as the clock source (CLKS[1:0] = 10B), the PLLDIVM value cannot be
changed.
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■ PLLDIVN: PLL Divider N
Figure 4.4-3 shows the structure of the PLL divider N.
Figure 4.4-3 The Structure of the PLL Divider N
PLLDIVN
bit
Address: 00048DH
Read/Write
Initial value
7
6
5
4
3
2
1
0
Reserved
Reserved
DVN5
DVN4
DVN3
DVN2
DVN1
DVN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PLLDIVN is one of the dividers included in the PLL feedback loop. This divider determines the PLL
multiply rate along with PLLDIVM.
[bit7, bit6] Reserved bits
These bits are reserved. Their read value is "0".
[bit5 to bit0] DVN5 to DVN0: PLLDIVN division setting value
The division number varies as shown below, depending on the value set to DVN5 to DVN0.
Table 4.4-2 PLLDIVN Division Setting Value
DVN5 to DVN0
Division No.
000000B
1 (No division)
000001B
2
000010B
3
000011B
4
000100B
5
000101B
6
000110B
7
000111B
8
······
······
111111B
64
Note:
When PLL is selected as the clock source (CLKS[1:0] = 10B), the PLLDIVN value cannot be
changed.
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■ PLLDIVG
PLLDIVG
bit
7
Address: 00048EH
Reserved
Read/Write
R/W
Initial value
(INITX pin input,
0
watchdog reset)
Initial value
0
(Software reset)
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
R/W
R/W
R/W
DVG3
R/W
DVG2
R/W
DVG1
R/W
DVG0
R/W
0
0
0
0
0
0
0
0
0
0
X
X
X
X
[bit7 to bit4] Reserved bits
Always write "0" to these bits.
[bit3 to bit0] DVG3 to DVG0: Select divide-by-G for PLL automatic gear start/stop
DVG3 to DVG0
Start/Stop frequency for dividing PLL output by G (Generationf: Base clock)
0000B
Automatic gear disabled (Initial value)
0001B
Source (FCL-PLL): 2 (divide by 2)
0010B
Source (FCL-PLL): 3 (divide by 3)
0011B
Source (FCL-PLL): 4 (divide by 4)
0100B
Source (FCL-PLL): 5 (divide by 5)
0101B
Source (FCL-PLL): 6 (divide by 6)
0110B
Source (FCL-PLL): 7 (divide by 7)
0111B
Source (FCL-PLL): 8 (divide by 8)
......
.....
1111B
Source (FCL-PLL): 16 (divide by 16)
Notes: • Although an odd division ratio (3, 5, 7, etc.) can be selected for divide-by-G counter, such value
is not a recommended value. Always select an even division ratio (2, 4, 6, etc.).
• The register value cannot be changed (CLKS[1:0]=10B) if PLL is selected as a clock source.
• Please set to 0000B (initial value) when not use the automatic gear function.
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■ PLLMULG
PLLMULG
bit
Address: 00048FH
Read/Write
Initial value
(INITX pin input,
watchdog reset)
Initial value
(Software reset)
7
6
5
4
3
2
1
0
MLG7
R/W
MLG6
R/W
MLG5
R/W
MLG4
R/W
MLG3
R/W
MLG2
R/W
MLG1
R/W
MLG0
R/W
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
[bit7 to bit0] MLG7 to MLG0: Select step multiplication factor for dividing PLL automatic gear by G
MLG7 to MLG0
Step multiplication factor for dividing by G
00000000B
Divide-by-G step x 1 (multiply by 1)
00000001B
Divide-by-G step x 2 (multiply by 2)
00000010B
Divide-by-G step x 3 (multiply by 3)
00000011B
Divide-by-G step x 4 (multiply by 4)
00000100B
Divide-by-G step x 5 (multiply by 5)
00000101B
Divide-by-G step x 6 (multiply by 6)
00000110B
Divide-by-G step x 7 (multiply by 7)
00000111B
Divide-by-G step x 8 (multiply by 8)
......
.....
11111111B
Divide-by-G step x 256 (multiply by 256)
Notes: • The register value cannot be changed (CLKS[1:0]=10B) if PLL is selected as a clock source.
• When the automatic gear function is not used, this register is not used.
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■ PLLCTRL
PLLCTRL
bit
7
Address: 000490H
Reserved
Read/Write
R/W
Initial value
(INITX pin input,
0
watchdog reset)
Initial value
0
(Software reset)
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
R/W
R/W
R/W
IEDN
R/W
GRDN
R/W
IEUP
R/W
GRUP
R/W
0
0
0
0
0
0
0
0
0
0
X
X
X
X
[bit7 to bit4] Reserved bits
The read value is always "0".
[bit3] IEDN: Interrupt enable gear down bit
IEDN
Function
0
Disables gear down interrupt (Initial value)
1
Enables gear down interrupt
[bit2] GRDN: Interrupt flag gear down bit
GRDN
Function
0
Gear down interrupt is inactive (Initial value)
1
Gear down interrupt is active
• If the divide-by-G counter reaches to a programmed end value, this flag is set when a clock source is
switched from PLL to clock source oscillation.
• "1" is read from this bit when a read-modify-write (RMW) instruction is used. Writing "1" to this bit
does not affect the operation.
[bit1] IEUP: Interrupt enable gear up bit
IEUP
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Function
0
Disables gear up interrupt (Initial value)
1
Enables gear up interrupt
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[bit0] GRUP: Interrupt flag gear up bit
GRUP
Function
0
Gear up interrupt is inactive (Initial value)
1
Gear up interrupt is active
• If the divide-by-G counter reaches to an end value defined in the divide-by-M counter, this flag is set
when a clock source is switched from oscillation to clock source PLL.
• "1" is read from this bit when a read-modify-write (RMW) instruction is used. Writing "1" to this bit
does not affect the operation.
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4.4.2
Examples of PLL Multiply Rate Setting
This section shows examples of PLL setting
The table below shows setting examples for PLLDIVM and PLLDIVN.
The output of the PLL oscillator should be set within a range from 80 MHz to 170 MHz.
Table 4.4-3 Examples of PLL Multiply Rate Setting (1 / 2)
PLL input clock
[MHz]
PLLDIVM Setting PLLDIVN Setting
Output of PLL
Oscillator [MHz]
PLL Output
(Output to Clock Unit) [MHz]
4
20
2
160
8
4
14
3
168
12
4
10
4
160
16
4
8
5
160
20
4
8
6
192
24
4
6
7
168
28
4
6
8
192
32
4
6
9
192
36
4
4
10
160
40
4
4
11
176
44
4
4
12
192
48
4
2
19
152
76
4
2
20
160
80
10
2
8
160
80
10
3
5
150
50
10
3
6
180
60
10
4
4
160
40
10
4
5
200
50
10
5
3
150
30
10
5
4
200
40
10
6
3
180
30
10
8
2
160
20
10
9
2
180
20
10
10
2
200
20
12
3
5
180
60
12
4
4
192
48
12
5
3
180
36
12
7
2
168
24
12
8
2
192
24
14
3
4
168
56
14
4
3
168
42
14
6
2
168
28
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Table 4.4-3 Examples of PLL Multiply Rate Setting (2 / 2)
PLL input clock
[MHz]
116
PLLDIVM Setting PLLDIVN Setting
Output of PLL
Oscillator [MHz]
PLL Output
(Output to Clock Unit) [MHz]
14
7
2
196
28
16
2
5
160
80
16
3
4
192
64
16
4
3
192
48
16
5
2
160
32
16
6
2
192
32
18
3
3
162
54
18
5
2
180
36
20
2
4
160
80
20
3
3
180
60
20
4
2
160
40
20
5
2
200
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MB91461
■ Clock Automatic Gear Up-Down
In the PLL interface, a circuit that allows the clock to gear up and gear down smoothly is implemented to
prevent voltage drops and surges when a clock source is switched from oscillation to high-frequency PLL
output (or vice versa).
The main function is implemented using two division counters (divide-by-M counter and divide-by-G
counter). A target frequency is specified for PLL feedback in the divide-by-M counter. In another counter,
the divide-by-G counter, a frequency is increased from a programmable division specified in the Divide-byG setting (DIVG) to a target frequency specified in the M division setting (DIVM) and then the frequency
is decreased from the M division setting (DIVM) to a programmable end frequency (DIVG).
If the system clock is modified from a low-frequency to a high-frequency (gear up) or from a highfrequency to a low-frequency (gear down), only the setting with DIVG > DIVM becomes valid clock gear
specification.
Frequency steps are executed at PLL output frequency multiplier as follows. Oscillator = 4 MHz, M = 2,
and N = 20. (This means that if PLL output = 160 MHz and frequency output to C unit = 80 MHz, the
frequency multiplier becomes M × N = 40.)
The gear divider can be set to any even-numbered divider. In this example, G = 20 and a gear up is
performed when the clock source is switched from oscillation to PLL.
1. Step: 1-cycle 8.0 MHz (8.0 MHz is a 20-cycle PLL output.)
2. Step: 2-cycle 8.4 MHz (8.4 MHz is a 19-cycle PLL output.)
3. Step: 3-cycle 8.8 MHz (8.8 MHz is an 18-cycle PLL output.)
:
17. Step: 17-cycle 40.0 MHz (40.0 MHz is a 4-cycle PLL output.)
18. Step: 18-cycle 53.3 MHz (53.3 MHz is a 3-cycle PLL output.)
19. Step: 19-cycle 80.0 MHz (80.0 MHz is a 2-cycle PLL output.)
→ Target frequency reached by the transition to the last step (from 18. to 19. in this example)
If a multiplication value is set in the gear multiplication factor register, each step is multiplied. The time
from when a start frequency is generated to the time when a target frequency is reached can be calculated
using the following formula.
i
 i


duration = mul Þ t Þ  k Þ ( i – k + 1 ) –  k Þ ( i – k + 1 )


k = 1

k = j+1
This formula is the same as the one below (the finite arithmetic series of the first addition term result to the
below).
i


i
Þ
(
i
+
1
)
Þ
(
i
+
2
)

duration = mul Þ t Þ  ---------------------------------------------- –  k Þ ( i – k + 1 )
6


k = j+1
i = G, j = G - M, mul = MULG, t = 1/f(pllout)
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The above setting is equivalent to 1483 PLL output clock cycles. With this 1483 PLL output clock cycles,
the time from the start frequency to the target frequency is 9262500 ps (about 9.3 s).
Note:
Before using the clock automatic gear function, it is recommended to use the gear up and gear down
flags (PLLCTRL:GRUP and PLLCTRL:GRDN) to evaluate the current status of this function. This can
prevent error operations that are caused by changing the setting before the completion from occurring in
the clock system.
Procedure example:
1. Set PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the
selected frequency and gear time.
2. Set PLL to ON (CLKR:PLL1EN=1).
3. Enable the corresponding interrupts (PLLCTRL:IEUP, PLLCTRL:IEDN) if an interrupt is received
after a gear up or gear down switching.
4. Wait until PLL stabilization wait time.
5. Set base clock division registers (DIV0, DIV1).
6. Switch the clock source to PLL (CLKR:CLKS 00B → 10B).
7. Wait for until PLLCTRL.GRUP gear up flag (polling or interrupt) before switching the clock
source back to oscillation, or confirm the PLLCTRL:GRUP=1 setting before changing bits in the
CLKR register.
8. Switch the clock source to oscillation (CLKR:CLKS 10B → 00B).
9. Wait for until PLLCTRL:GRDN gear down flag (polling or interrupt) before switching the clock
source back to PLL, or confirm the PLLCTRL:GRDN=1 setting before changing bits in the CLKR
register.
10. Set PLL to OFF (CLKR:PLL1EN=0).
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4.5
Device State Control
4.5 Device State Control
This section describes the states and control of the MB91461.
■ Overview of the Device State Control
The following device states are available.
• Run state (normal operation)
• Sleep state
• Stop state
• Shutdown state
• Oscillation stabilization wait run state
• Oscillation wait reset (RST) state
• Operation initialization reset (RST) state
• Setting initialization reset (INIT) state
The above device states as well as the sleep and stop modes designed for low-power consumption mode are
detailed below.
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4.5.1
MB91461
Device States and Transitions
Figure 4.5-1 shows the device states and transitions.
■ Device States
Figure 4.5-1 Device States
Priority levels of
transition requests
1 INITX pin = 0 (INIT)
2 INITX pin = 1 (INIT released)
3 Oscillation stabilization wait completed
4 Reset (RST) released
5 Software reset (RST)
6 Sleep (interrupt written)
7 Stop (interrupt written)
8 Shutdown (interrupt written)
9 Interrupt
10 External interrupt requiring no clock
11 Watchdog reset (INIT)
(Including hardware watchdog)
Power-on
Highest
1
Lowest
Setting initialization reset (INT)
Oscillation stabilization wait end
Operation initialization reset (RST)
Interrupt request
Stop (shutdown)
Sleep
Setting initialization
(INT)
2
1
Shutdown
10
1
Oscillation stabilization
wait reset
Stop
1
8
10
1
Oscillation
stabilization wait run
3
Program reset
(RST)
3
7
5
1
6
Sleep
RUN
1
4
11
1
9
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■ Operation States of the Device
The MB91461 has the following operation states.
● Run state (normal operation)
This is the state in which the program runs.
In the run state, all the internal clocks are supplied and all the circuits are operable. However, the bus clock
for the 16-bit peripheral bus is stopped when the peripheral bus is not accessed.
Transition requests for each state are accepted. However, if the synchronous reset mode is selected, state
transitions responding to some requests operate differently from the normal reset mode.
For more details, see "4.2.5 Reset Operation Modes" - "■ Synchronous Reset Operation".
● Sleep state
In this state, the program is stopped. Program operation causes state transition.
In the sleep state, only CPU program execution is stopped and the peripheral circuits are operable. The
internal memory and internal/external buses are stopped unless requested by the DMA controller. When a
valid interrupt request is generated, this state is cleared and the device transits to the run state (normal
operation).
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
When an operation initialization reset (RST) request is generated, the device transits to the operation
initialization reset (RST) state.
● Stop state
In this state, the device is stopped. Program operation causes state transition.
In the stop state, all internal circuits are stopped. All the internal clocks are stopped and oscillation circuits
and PLLs can be set to stop. The stop state can also set external pins (except some pins) to operate at high
impedance.
When a particular valid interrupt request (requiring no clock) is generated, or an interval timer interrupt
request is generated during oscillation, the device transits to the oscillation stabilization wait run state.
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
When an operation initialization reset (RST) request is generated, the device transits to the oscillation
stabilization wait reset (RST) state.
● Shutdown state
In this state, the device is stopped in all components except RAM. Program operation causes state
transition.
Power supply is cut off in all components except RAM (64 Kbytes) and circuits surrounding it. This
function allows a significant decrease in leakage currents in the shutdown state. All output except the
output to hold the external bus control signal is at high impedance.
When a particular valid interrupt request (requiring no clock) is generated, the device transits to the
oscillation stabilization wait run state.
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
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● Oscillation stabilization wait run state
In this state, the device is stopped. The device transits to this state after returning from the stop state.
All internal circuits except the circuits in the clock generation control block (time-base counter and device
state control sections) are stopped. Although all the internal clocks are stopped, the oscillation circuit and
PLLs that are enabled to operate are active.
Control of the external pins at high impedance in the stop state is cleared.
When the set oscillation stabilization wait time has elapsed, the device transits to the run state (normal
operation).
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
When an operation initialization reset (RST) request is generated, the device transits to the operation
initialization reset (RST) state.
● Oscillation stabilization wait reset (RST) state
In this state, the device is stopped. The device transits to this state after returning from the stop state or
setting initialization reset (INIT) state.
All internal circuits except the circuits in the clock generation control block (time-base counter and device
state control sections) are stopped. Although all the internal clocks are stopped, the oscillation circuit and
PLLs that are enabled to operate are active.
Control of the external pins at high impedance in the stop state is cleared.
Operation initialization reset (RST) is output to the internal circuits.
When the set oscillation stabilization wait time has elapsed, the device transits to the oscillation
stabilization wait reset (RST) state.
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
● Operation initialization reset (RST) state
In this state, the program is initialized. When an operation initialization reset (RST) request is accepted, or
the oscillation stabilization wait reset (RST) state is terminated, transition occurs.
Program execution is stopped in the CPU and the program counter is initialized. Most peripheral circuits
are also initialized. All internal clocks, oscillation circuit, and PLLs that are enabled to operate are active.
Operation initialization reset (RST) is output to the internal circuits.
When an operation initialization reset (RST) request is released, the device transits to the run state (normal
operation state) and the operation initialization reset sequence is executed. If this occurs after returning
from the setting initialization reset (INIT) state, the setting initialization reset sequence is executed.
When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization
reset (INIT) state.
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● Setting initialization reset (INIT) state
In this state, all settings are initialized. When a setting initialization reset (INIT) request is accepted, or the
hardware standby state is terminated, transition occurs.
In the CPU, program execution is stopped and the program counter is initialized. All peripheral circuits are
initialized. While the oscillation circuit operates, PLLs stop operation. All the internal clocks operate
except during "L" level input into the external INITX pin.
Setting initialization reset (INIT) and operation initialization reset (RST) are output to the internal circuits.
When the setting initialization reset (INIT) request is released, the device transits from this state to the
oscillation stabilization wait reset (RST) state. After the RST state, the setting initialization reset sequence
is executed.
● Priority of each state transition request
In any state, every state transition request follows the priority order shown below. However, some requests
are only generated in a particular state and only valid in that state.
[Highest]
↓
Setting initialization reset (INIT) request
Termination of oscillation stabilization wait time
(Only the oscillation stabilization wait reset state and the oscillation stabilization wait run
state occur.)
↓
Operation initialization reset (RST) request
↓
Valid interrupt request
(Only the run state, sleep state, stop state, and shutdown state occur.)
↓
Stop mode request (shutdown)
(Writing to register) (Only the run state occurs.)
[Lowest]
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Sleep mode request (Writing to register) (Only the run state occurs.)
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4.6 Interval Timer
4.6
MB91461
Interval Timer
The interval timer is a 23-bit counter synchronized with the source clock to count up.
This timer incorporates a function to continuously generate interrupts at a regular
interval.
■ Interval Duration of the Interval Timer
Table 4.6-1 lists the interval duration of the interval timer.
Table 4.6-1 Interval Duration of the Interval Timer
Main clock cycle
Interval Timer
214/FXTL
219/FXTL
1/FXTL
225/FXTL
Note: FXTL is the clock from the X0 and X1 pins or the oscillation circuit.
■ Block Diagram of the Interval Timer
Figure 4.6-1 shows the block diagram of the interval timer.
Figure 4.6-1 Block Diagram of the Interval Timer
Counter for the
interval timer
FXTL
22
0
1
2
3
4
5
6
7
8
23 24 25 26 27 28 29 210 211
11
16
22
214
219
225
Source clock
Interval
timer
selector
Reset
(INIT)
Counter clear
circuit
Interval timer
interrupt
Interval timer control
register (OSCR)
WIF
WIE
WEN
Reserved Reserved
WS1
WS0
WCL
FXTL: Clock from the X0 and X1 pins or the oscillation circuit
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4.6 Interval Timer
MB91461
● Interval timer
This is a 23-bit up-counter that uses the clock either from the X0 and X1 pins or the oscillation circuit that
is divided by 4 as its count clock.
● Counter clear circuit
This circuit clears the counter at reset (INIT) as well as OSCR register settings (WCL = 0).
● Interval timer selector
Among three types of division output for the interval timer counter, this circuit selects one for the interval
timer. The falling edge of the selected division output becomes an interrupt factor.
● Interval timer control register (OSCR)
This register selects the interval duration, clears the counter, controls interrupts, and confirms their state.
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4.6 Interval Timer
MB91461
■ Registers in the Interval Timer
Figure 4.6-2 shows the structure of registers in the interval timer.
Figure 4.6-2 The Structure of Registers in the Interval Timer
OSCR
bit
Address: 0004C8H
Read/Write
Initial value (INIT)
Initial value (RST)
15
14
13
12
11
10
9
8
WIF
R/W
0
X
WIE
R/W
0
X
WEN
R/W
0
X
Reserved
Reserved
R/W
−
X
R/W
−
X
WS1
R/W
0
X
WS0
R/W
0
X
WCL
R/W
1
X
[bit15] WIF: Timer interrupt flag
This is an interval interrupt request flag.
This flag is set to "1" by the falling edge of division output of the selected interval timer.
When this bit and the interrupt request enable bit are both set to "1", an interval timer interrupt request
is generated.
Table 4.6-2 Timer Interrupt Flag
Value
Function
0
Generates no interval timer interrupt request. [Initial value]
1
Generates an interval timer interrupt request.
This bit is initialized to "0" at reset (INIT).
This bit is readable and writable. However, only "0" can be written. Writing "1" does not change the bit
value.
The read value of read-modify-write (RMW) instructions is always "1".
[bit14] WIE: Timer interrupt enable bit
This bit enables and disables output of interrupt request to the CPU. When this bit and the interval timer
interrupt request flag bit are set to "1", an interval timer interrupt request is generated.
Table 4.6-3 Timer Interrupt Enable Bit
Value
Function
0
Disables output of an interval timer interrupt request. [Initial value]
1
Enables output of an interval timer interrupt request.
This bit is initialized to "1" at reset (INIT).
It is readable and writable.
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4.6 Interval Timer
MB91461
[bit13] WEN: Timer operation enable bit
This bit enables the timer operation.
When this bit is set to "1", the timer counts.
Table 4.6-4 Timer Operation Enable Bit
Value
Function
0
Stops the timer operation. [Initial value]
1
Operates the timer.
This bit is initialized to "0" at reset (INIT).
It is readable and writable.
[bit12, bit11] Reserved bits
These bits are reserved. "0" should be written. (Writing "1" is prohibited.)
The read value is undefined.
[bit10, bit9] WS1 and WS0: Timer interval select bits
These bits select the interval timer cycle.
The cycle is selected from the following three combinations of output bits of the interval timer counter.
Table 4.6-5 Timer Interval Select Bits
WS1
WS0
Interval timer cycle
0
0
Setting disabled [Initial value]
0
1
214/FXTL
1
0
219/FXTL
1
1
225/FXTL
FXTL is the clock from the X0 and X1 pins or the oscillation circuit.
These bits are initialized to 00B at reset (INIT).
They are readable and writable.
When using the interval timer, write data to this register.
[bit8] WCL: Timer clear bit
Writing "0" clears the interval timer to "0".
Only "0" can be written. Writing "1" has no effect.
The read value is always "1".
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4.6 Interval Timer
MB91461
■ Interval Interrupt
The interval timer counter counts by using the clock (source clock) either from the X0 pin and X1 pin or
the oscillation circuit that is divided by 2. When the set interval has elapsed, the interval interrupt request
flag (WIF) is set to "1". At this point, if the interrupt request enable bit is enabled (WIE = 1), an interrupt
request is generated to the CPU. However, when the oscillation circuit is stopped (see section "■ Operation
of the interval timer function"), counting is also stopped. Consequently, no interval interrupt is generated.
Write "0" to the WIF flag in an interrupt routine to clear the interrupt request.
Note that when the specified division output falls, the WIF bit is set regardless of the value of the WIE bit.
Notes:
• When enabling output of an interrupt request after reset is canceled, or when modifying the WS1
bit (bit0), always clear the WIF and WCL bits at the same time (WIF = WCL = 0).
This timer cannot be used to automatically retain the stabilization wait time of the oscillation
circuit.
• When the WIF bit is set to "1", changing the WIE bit from the disabled state to the enabled state
(0 → 1) immediately generates an interrupt request.
• When the counter is cleared (OSCR: WCL = 1) at the same time as the selected bit overflows, the
WIF bit is not set.
■ Operation of the Interval Timer Function
The interval timer counter uses the source clock to count up. In the following state, however, counting is
stopped as oscillation from the oscillation circuit is stopped.
When the WEN bit is set to "0":
When the oscillation circuit is set to stop in the stop mode (the OSCD1 (bit0) of the standby control
register (STCR) is set to "1"), and the device enters that mode, counting is stopped during the stop
mode. The OSCD1 bit is initialized to "1" at reset (INIT). Therefore, to operate the interval timer in the
stop mode, set the OSCD2 bit to "0" before the device enters the standby state.
Clearing the counter (WCL = 0) allows the counter to count from 000000H. When the counter has reached
7FFFFFH, it goes back to 000000H to continue to count. The interval interrupt request bit (WIF) is set to
"1" by the falling edge of division output of the interval timer that was selected during the counting-up
operation. In other words, interval timer interrupt requests are generated at each selected interval, based on
the cleared time.
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4.6 Interval Timer
MB91461
■ Interval Timer Operation
Figure 4.6-3 shows the counter state during interval timer operation.
Figure 4.6-3 Counter State During Interval Timer Operation
7FFFFFH
Counter value
000000H
TIME
Set time
· Timer clearing (WCL = 1) * when not "0"
· Interval setting (WS1, WS0 = 11B)
Clearing in interrupt routine
WIF (Interrupt request)
WIE (Interrupt mask)
■ Precautions for Use of the Interval Timer
The set time is reference only, because the oscillation cycle is unstable immediately after oscillation starts.
While the oscillation circuit is stopped, the counter is also stopped. Consequently, no interval timer
interrupts are generated. Therefore, when executing processing using an interval timer interrupt, the
oscillation circuit should not be stopped.
When a WIF flag set request is generated at the same time as "0" clearing is requested by the CPU, the flag
set request has priority and the "0" clearing request becomes invalid.
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4.6 Interval Timer
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MB91461
CM71-10159-2E
CHAPTER 5
INSTRUCTION CACHE
This chapter describes the instruction cache.
5.1 Overview
5.2 Control Register
5.3 Cache State And Various Operating Modes
5.4 Setting Up the Instruction Cache before Use
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CHAPTER 5 INSTRUCTION CACHE
5.1 Overview
5.1
MB91461
Overview
The instruction cache is temporary memory. When an external low-speed memory
accesses an instruction code, the instruction cache stores the single-accessed code to
increase the second and subsequent access speeds.
■ Overview
Setting this memory to the RAM mode enables software to directly read and write instruction cache data
RAM and tag RAM.
■ Main Frame Structure
• FR basic instruction length: 2 bytes
• Block arrangement system: 2-way set associative system
• Block:
One way consists of 128 blocks
One block consists of 16 bytes (= 4 sub-blocks)
One sub-block consists of 4 bytes (= 1 bus access unit)
Figure 5.1-1 Instruction Cache Structure
I3
I2
I1
I0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 127
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 127
128 Blocks
···
Way-1
4 bytes
4 bytes
4 bytes
···
4 bytes
···
4 bytes
Cache tag
132
···
···
128 Blocks
···
Way-2
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CHAPTER 5 INSTRUCTION CACHE
5.1 Overview
MB91461
Figure 5.1-2 Instruction Cache Tag
Way-1
bit31
9
Address tag
8
Reserved
7
SBV3
6
SBV2
5
SBV1
Sub-block valid
LRU
Entry lock
4
SBV0
3
2
TAGV Reserved
1
LRU
0
ETLK
1
0
ETLK
TAG valid
Way-2
bit31
9
Address tag
8
Reserved
7
SBV3
6
SBV2
Sub-block valid
5
SBV1
4
SBV0
3
TAGV
2
Reserved
TAG valid
Entry lock
[bit31 to bit9] Address tag
The upper 23 bits of the memory address of the instruction cached in the corresponding block are
stored.
The memory address IA of the instruction data stored in sub-block k on block i is as follows:
IA = Address tag × 211 + i × 24 + k × 22
These bits are used to perform coincidence checkout of instruction address that the CPU requests access
to.
• When the requested instruction data is in the cache (hit), the cache transfers the data to the CPU
within one cycle.
• When the requested instruction data is not in the cache (miss), the CPU and cache simultaneously
acquire the data by external access.
[bit7 to bit4] SBV3 to SBV0: Sub-block valid
When the sub-block valid* is set to "1", the current instruction data at the tagged address is entered in
the corresponding sub-block. Normally, two instructions are stored in a sub-block (except for the
immediate value transfer instruction).
[bit3] TAGV: TAG valid
This bit indicates whether address tag value is valid. When this bit is "0", this block is invalid regardless
of the sub-valid bit (flushed state).
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5.1 Overview
MB91461
[bit1] LRU bit (way 1 only)
This bit is present only for way-1 instruction cache tag. Regarding the selected set, the bit indicates
whether a way-1 or way-2 entry was accessed in the cache last. When LRU = 1, a way-1 set entry was
accessed last. Conversely, when LRU = 0, a way-2 set entry was accessed last.
[bit0] ETLK: Entry lock bit
This bit locks all tagged entries within a block in the cache. When ETLK = 1, the locked state prevails
so entries are not updated when they are not found in the cache. However, invalid sub-blocks are
updated. If the data is not found in the cache when way 1 and way 2 are both entry-locked, the external
memory is accessed after the loss of one cycle of "cache miss" evaluation.
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5.2 Control Register
MB91461
5.2
Control Register
Control register consists of Cache size register (ISIZE) and Instruction Cache control
register. This section explains the functions of these registers.
■ Cache Size Register (ISIZE)
Figure 5.2-1 The Structure of Cache Size Register (ISIZE)
ISIZE (8 bits)
bit
000003C7H
7
6
5
4
3
2
−
−
−
−
−
−
−
−
−
−
−
−
1
0
SIZE1 SIZE0
R/W
R/W
Initial value
------10B
[bit1, bit0] SIZE1 and SIZE0
These bits are used to set the cache size. As shown in Figure 5.2-3 , the cache size, IRAM size, and
address map in the RAM mode change according to setting of these bits. When the cache size is
changed, always turn on cache after unlocking flush and entry lock.
Table 5.2-1 Cache Size Register
SIZE1
SIZE0
Size
0
0
1 Kbyte
0
1
2 Kbytes
1
0
4 Kbytes [Initial value]
1
1
Setting disabled
■ Instruction Cache Control Register (ICHCR)
Instruction Cache Control Register (ICHCR) controls the instruction cache operations.
Writing to the ICHCR does not affect caching of instructions fetched within subsequent three cycles.
Figure 5.2-2 The Structure of Instruction Cache Control Register (ICHCR)
ICHCR (8 bits)
bit
000003E7H
CM71-10159-2E
7
6
5
4
3
2
1
0
Initial value
RAM
−
GBLK
ALFL
EOLK
ELKR
FLSH
ENAB
0-000000B
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
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5.2 Control Register
MB91461
[bit7] RAM: RAM Mode
Setting the RAM bit to "1" enables instruction cache to operate in the RAM mode. If the ENAB bit is
"1" with cache on when the RAM mode is selected, cache RAM will be mapped as shown in Figure 5.23.
[bit5] GBLK: Global lock bit
This bit locks all current entries in cache. When GBLK = 1, valid entries in the cache are not updated at
a "cache miss". However, invalid sub-blocks are updated. The resulting instruction data fetch operation
is the same as for unlocked entries.
[bit4] ALFL: Auto lock fail bit
When a locked entry is attempted to be locked for the second time, the ALFL is set to "1". When entryauto-locked entry is updated for a locked entry, the new entry is not locked in the cache. Referencing is
done for program debugging. This is cleared by writing "0".
[bit3] EOLK: Entry auto lock bit
This bit specifies whether auto locking feature is enabled or disabled for individual entries in instruction
cache. Entries accessed (only at miss) while EOLK = 1 are locked when the entry lock bit in the cache
tag is set to "1" by hardware. Locked entries are not subsequently updated at a cache miss. However,
invalid sub-blocks are updated. To assure proper locking, first flush and then set this bit.
[bit2] ELKR: Entry lock release bit
This bit is used to clear entry lock bits at all cache tags. When ELKR is set to "1", entry lock bits at all
cache tags are cleared to "0" at the next cycle. However, the value of this bit is held only for one clock
cycle. It is cleared to "0" at the second and subsequent clock cycles.
[bit1] FLSH: Flush bit
This bit specifies flushing of instruction cache. When FLSH = 1, the cache data is flushed. However,
the value of this bit is held only for 1 clock cycle. It is cleared to "0" at the second and subsequent clock
cycles.
[bit0] ENAB: Enable bit
This bit enables or disables instruction cache. When ENAB = 0, the instruction cache is disabled so
instruction accessing from the CPU is performed directly to the outside, without using the cache. When
the instruction cache is disabled, instructions in the cache are saved.
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5.2 Control Register
MB91461
Figure 5.2-3 RAM Address Map
Address
00010000H
00010200H
00010400H
00010600H
00010800H
···
00014000H
00014200H
00014400H
00014600H
00014800H
···
00018000H
00018200H
00018400H
00018600H
00018800H
···
Cache OFF
RAM OFF
Cache OFF
RAM ON
TAG
(way1)
Cache ON 4K Cache ON 4K Cache ON 2K Cache ON 2K Cache ON 1K Cache ON 1K
RAM OFF
RAM ON
RAM OFF
RAM ON
RAM OFF
RAM ON
TAG
TAG
TAG(way1)
(way1)
(way1)
[TAG way1]
[TAG way1]
[TAG way1]
[TAG way1]
[TAG way1]
[TAG way1]
[TAG way1]
[TAG way1]
···
···
···
···
[TAG way1]
TAG
TAG
TAG
TAG(way2)
(way2)
(way2)
(way2)
[TAG way2]
[TAG way2]
[TAG way2]
[TAG way2]
[TAG way2]
[TAG way2]
[TAG way2]
[TAG way2]
···
···
···
[TAG way2]
IRAM
$RAM(IRAM)
$RAM
$RAM
$RAM(way1)
(way1)
(way1)
(way1)
(way1)
IRAM
IRAM
*1
IRAM
IRAM
(way1)
(way1)
(way1)
(way1)
[IRAM way1] [$RAM way1]
[$RAM way1] [IRAM way1]*2 [ $/I way1 ]
[IRAM way]
[ $/I way1 ]
···
···
···
···
···
···
···
0001C000H
IRAM
$RAM(IRAM)
(way2)
(way2)
0001C200H
0001C400H
*1
0001C600H
0001C800H [IRAM way2] [$RAM way2]
···
···
···
$RAM
(way2)
IRAM
(way2)
[$RAM way2] [IRAM way2]*2
···
···
$RAM
(way2)
IRAM
(way2)
[ $/I way2 ]
···
IRAM
(way2)
$RAM(way2)
IRAM
(way2)
[IRAM way2]
···
[ $/I way2 ]
···
00020000H
[ ] refers to a mirror area
*1 Same as the map when cache is on, in accordance with the value of the ISIZE register.
*2 A mirror area is generated in the upper 2 Kbytes of every 4 Kbytes.
Note: "$" represents cache.
TAGRAM
00010000H
00010004H
00010008H
0001000CH
00010010H
00010014H
00010018H
0001001CH
00010020H
CM71-10159-2E
$RAM
<- Entry at 00x address 00018000H
<- Mirror at 00x
00018004H
00018008H
0001800CH
<- Entry at 01x address 00018010H
<- Mirror at 01x
00018014H
00018018H
0001801CH
00018020H
FUJITSU MICROELECTRONICS LIMITED
Instruction at 000 address (SBV0)
Instruction at 004 address (SBV1)
Instruction at 008 address (SBV2)
Instruction at 00C address (SBV3)
Instruction at 000 address (SBV0)
Instruction at 004 address (SBV1)
Instruction at 008 address (SBV2)
Instruction at 00C address (SBV3)
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5.2 Control Register
MB91461
Figure 5.2-4 Memory Assignment for Each Cache Size
Address
000H
200H
400H
600H
···
000H
200H
400H
600H
Cache 4K
$RAM
(WAY1)
Cache 2K
$RAM
Cache 1K
$RAM
IRAM
Cache off
IRAM
IRAM
$RAM
(WAY2)
···
$RAM
···
$RAM
IRAM
IRAM
IRAM
Note: "$" represents cache.
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5.3 Cache State And Various Operating Modes
MB91461
5.3
Cache State And Various Operating Modes
This section explains the cache states in Various operating modes and setting method
of instruction cache.
■ Cache State in Various Operating Modes
The table below indicates the prevailing state for disable and flush when the associated bit is changed by bit
manipulation instruction or other instructions.
Table 5.3-1 Cache State in Various Operating Modes
Immediately
after Reset
Tag
Cache Memory
Address Tag
The contents are
undefined.
Sub-block Valid Bit
The contents are
undefined.
LRU
The contents are
undefined.
Entry Lock Bit
The contents are
undefined.
TAG Valid Bit
The contents are
undefined.
RAM
Control Register
The contents are
undefined.
Normal Mode
Global Lock
Unlock
Auto Lock Fail
No fail
Entry Auto Lock
Unlock
Entry Lock Release No release
Enable
Disabled
Flush
Not flushed
CM71-10159-2E
Disable (ENAB = 0)
The preceding state is held.
Rewriting is impossible while the
cache is disabled.
The preceding state is held.
Rewriting is impossible while the
cache is disabled.
The preceding state is held.
Rewriting is impossible while the
cache is disabled.
The preceding state is held.
Rewriting is impossible while the
cache is disabled.
The preceding state is held.
Rewriting is impossible while the
cache is disabled.
The preceding state is held.
Flushing is possible while the cache is
disabled.
The preceding state is held.
Flushing is possible while the cache is
disabled.
The preceding state is held.
Rewriting is possible while the cache
is disabled.
The preceding state is held.
Rewriting is possible while the cache
is disabled.
The preceding state is held.
Rewriting is possible while the cache
is disabled.
The preceding state is held.
Rewriting is possible while the cache
is disabled.
Disabled
The preceding state is held.
Rewriting is possible while the cache
is disabled.
FUJITSU MICROELECTRONICS LIMITED
Flush
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
(Entry lock release is required.)
All entries are invalid.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
Flushed in cycle following
memory accessing.
Reverts to "0" subsequently.
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5.3 Cache State And Various Operating Modes
MB91461
■ Cache Entry Update
Cache entries are updated as shown in the following table.
Table 5.3-2 Cache Entry Update
Unlock
Lock
Hit
Not updated.
Not updated.
Miss
The memory data is loaded and the cache
entry data is updated.
Not updated at tag miss.
Updated when sub-block is invalid.
■ Instruction Cache Area for Caching
• Regarding instruction cache, data is cached only in external bus space.
• Even if the external memory data is updated by DMA transfer, coherency with cached instructions will
not be maintained.
In this case, flush the cache to maintain the coherency.
• Instruction cache space can be set as non-cacheable area by chip select area. Even in this setting, a
penalty of one cycle is incurred compared with the time when the cache is off. (Refer to "8.3 Chip
Select Area".)
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5.4 Setting Up the Instruction Cache before Use
MB91461
5.4
Setting Up the Instruction Cache before Use
This section explains the setting method for using instruction cache.
■ Setting Procedures
Perform the following procedures to made the settings for using instruction cache.
● Initializing
Before instruction cache is used, its content must be cleared.
Set both the FLSH and ELKR bits of the register to "1" to delete the old data.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000110,r1
// Set "1" to FLSH bit (bit1)
// Set "1" to ELKR bit (bit2)
stb
r1,@r0
// Writing to register
The cache is now initialized.
● Enabling (turning on) the cache
To enable the instruction cache, set the ENAB bit to "1".
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000001,r1
// Set "1" to ENAB bit (bit0)
stb
r1,@r0
// Writing to register
Subsequently-accessed instructions will be cached.
Cache can be initialized and validated simultaneously.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000111,r1
// Set "1" to ENAB bit (bit0)
// Set "1" to FLSH bit (bit1)
// Set "1" to ELKR bit (bit2)
stb
r1,@r0
// Writing to register
● Disabling (turning off) the cache
To disable the instruction cache, set the ENAB bit to "0".
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000000,r1
// Set "0" to ENAB bit (bit0)
stb
r1,@r0
// Writing to register
In this state (same as the state after a reset), no cache appears to be present and no action is taken.
The cache can be turned off if the processing may experience problems due to cache overhead.
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5.4 Setting Up the Instruction Cache before Use
MB91461
● Locking all cached instructions
To lock all the currently-cached instructions in the cache to prevent any from disappearing, set the
GBLK bit of the register to "1". Unless the ENAB bit is also set to "1", the cache will be turned off and
any instructions locked in the cache cannot be used.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00100001,r1
// Set "1" to ENAB bit (bit0)
// Set "1" to GBLK bit (bit5)
stb
r1,@r0
// Writing to register
● Locking specific instructions in cache
To lock a specific group of instructions (e.g. subroutines) in cache, set the EOLK bit to "1" before
executing these instructions.
Instructions locked in this manner allow high-speed access as if using a fast built-in ROM.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00001001,r1
// Set "1" to ENAB bit (bit0)
// Set "1" to EOLK bit (bit3)
stb
r1,@r0
// Writing to register
Instructions succeeding the stb instruction become valid, although this depends on the memory wait
count. Set the EOLK bit to "0" when the desired group of instructions has been locked.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000001,r1
// Set "1" to ENAB bit (bit0)
// Set "0" to EOLK bit (bit3)
stb
r1,@r0
// Writing to register
● Unlocking the cached instructions
To unlock the data which is locked in (5) above, proceed as follows.
ldi
#0x000003e7,r0
// Instruction cache control register address
ldi
#0B00000000,r1
// Cache disabled
stb
r1,@r0
// Writing to register
ldi
#0B00000100,r1
// Set "1" to ELKR bit (bit2)
stb
r1,@r0
// Writing to register
As only locked information is unlocked, locked instructions are sequentially replaced with new ones
according to the state of the LRU bit.
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CHAPTER 6
LOW-POWER
CONSUMPTION MODE
This chapter describes functions and operations of the
low-power consumption modes.
6.1 Overview of Low-Power Consumption Mode
6.2 Sleep Mode
6.3 Stop Mode
6.4 Shut-down Mode
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1 Overview of Low-Power Consumption Mode
6.1
MB91461
Overview of Low-Power Consumption Mode
This section explains three low-power consumption modes supported with MB91461.
■ Low-Power Consumption Mode
● Sleep mode (Program is stopped)
Clock provision for the CPU core is stopped. Operation of the peripheral functions is continued.
Writing to the register causes the device to transition to the sleep state.
● Stop mode (Device is stopped)
Clock provision for the CPU core and the peripheral function is stopped.
The selection of stopping or continuing the main oscillation can be made.
● Shut-down mode (Power is shut)
Power supply for entire device except RAM and some control logics is shut internally.
Both the oscillation and the clock provision are stopped.
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6.2 Sleep Mode
MB91461
6.2
Sleep Mode
CPU keeps stopping with sleep mode in the mode that stops only the clock supplied to
CPU core, and the function in the surrounding operating.
■ Overview of Sleep Mode
The sleep mode is the state in which the program is stopped. A transition is made to this state depending on
the register setting of a software.
In the sleep state, only the CPU program execution is stopped and the peripheral circuits can operate.
Various internal memories and the internal/external buses are stopped unless requested by the DMA
controller. When an enabled interrupt request is generated, the sleep state is cancelled, causing a transition
to the RUN state (normal operation).
● Transition to Sleep Mode
When "1" is written to bit6 (SLEEP bit) of STCR (standby control register), the sleep mode is established,
causing a transition to the sleep state.
The sleep state continues until a factor causing a return from the sleep state occurs. When "1" is written to
both bit6 and bit7 (STOP bit) of STCR, bit7 is prior to bit6, causing a transition to the stopped state.
When establishing the sleep mode, set the synchronous standby mode (set by bit8 (SYNCS bit) of TBCR
(time base counter control register)) and always use the following sequence:
(LDI
#value_of_sleep,R0) ; value_of_sleep is write data to STCR
(LDI
#_STCR,R12)
; _STCR is STCR address (481H)
STB
R0,@R12
; Writing to standby control register (STCR)
LDUB @R12,R0
; Reading STCR for synchronous standby
LDUB @R12,R0
; Once more dummy reading of STCR
NOP
; Five NOPs for coordinate the timing
NOP
NOP
NOP
NOP
[Circuits stopped in sleep state]
• CPU program execution
• Bit search module (operates when DMA transfer performed)
• Various built-in memories (These memories operate when DMA transfer is performed.)
• Internal/external buses (These buses operate when DMA transfer is performed.)
[Circuits not stopped in sleep state]
• Oscillator circuit
• Enabled PLL
• Clock generation control unit
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2 Sleep Mode
MB91461
• Interrupt controller
• Peripheral circuits
• DMA controller
• DSU
• Interval timer
[Factors causing return from sleep state]
• Occurrence of enabled interrupt requests
When an interrupt request with an interrupt level other than interrupt disable (1FH) occurs, the sleep
mode is cancelled, performing a transition to the RUN state (normal state).
In order not to cancel the sleep mode even if an interrupt request occurs, set interrupt disable (1FH)
to the appropriate ICR as an interrupt level.
• Occurrence of setting initialization reset (INIT) request
When a setting initialization reset (INIT) request occurs, a transition is always made to the INIT
state.
• Occurrence of operation initialization reset (RST) request
When an operation initialization reset (RST) request occurs, a transition is unconditionally made to
the RST state.
See Section "4.5.1 Device States and Transitions" for the priority of each factor.
[Synchronous-standby operation]
When bit8 (SYNCS bit) of TBCR (time-base counter control register) is "1", the synchronous-standby
operation is enabled. In this case, just writing to the SLEEP bit does not cause a transition to the sleep
state. A transition is made to the sleep state by reading the STCR register after this writing.
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6.3 Stop Mode
MB91461
6.3
Stop Mode
The stop mode is a mode that stops the clock supplied to CPU core part and the
function in the surrounding.
When "1" is written to bit7 (STOP bit) of STCR (standby control register), the stop mode is established,
causing a transition to the stopped state. The stopped state continues until a factor causing a return from the
stopped state occurs.
When "1" is written to both bit6 (SLEEP bit) and bit7 of STCR, bit7 is prior to bit6, causing a transition to
the stopped state.
[Circuits stopped in stopped state]
Oscillator circuit set to be stopped:
When bit0 (OSCD1 bit) of STCR (standby control register) is "1", the oscillator circuit for the main
clock in the stopped state is placed in the stopped state. In this case, also the interval timer is
stopped.
PLL with disabled operation or connected to oscillator circuit set to be stopped:
When bit0 (OSCD1 bit) of STCR (standby control register) is "1", the PLL for the main clock in the
stopped state is placed in the stopped state even if bit10 (PLL1EN bit) of CLKR (clock source
control register) is "1".
All other internal circuits except the circuits not stopped in stopped state
[Circuits not stopped in stopped state]
Oscillator circuit not set to be stopped:
When bit0 (OSCD1 bit) of STCR (standby control register) is "0", the oscillator circuit for the
stopped main clock is not stopped. In this case, also the interval timer is not stopped.
PLL with enabled operation and connected to oscillator circuit not set to be stopped:
When bit0 (OSCD1 bit) of STCR (standby control register) is "0", the PLL for the main clock in the
stopped state is not stopped when bit10 (PLL1EN bit) of CLKR (clock source control register) is
"1".
[Pin high-impedance control in stopped state]
When bit5 (HIZ bit) of STCR (standby control register) is "1", the pin output in the stopped state is
placed in the high-impedance state.
When bit5 (HIZ bit) of STCR (standby control register) is "0", the pin output in the stopped state holds
the value before the transition to the stopped state. For details, see "4.3.6 Registers in the Clock
Generation Control Block".
[Input to peripheral resource in stopped state]
In the stopped state, an input to each peripheral resource is "0". Regarding the external interrupt (INTn)
pin and the CAN receiving (RXn) pin, when appropriate PFR is "0", an input of each resource is "0."
On the other hand, when the PFR is "1", signal from the pin is transmitted to the resource.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3 Stop Mode
MB91461
[Factors causing return from stopped state]
Occurrence of particular effective interrupt requests requiring no clock:
Only the following is enabled: external interrupt input pin (INTn pin) and interval timer interrupt
during main oscillation.
When an interrupt request with an interrupt level other than interrupt disable (1FH) occurs, the stop
mode is cancelled, performing a transition to the RUN state (normal state).
In order not to cancel the stop mode even if an interrupt request occurs, set interrupt disable (1FH) to
the appropriate ICR as an interrupt level. Do not set edge detection on an interrupt request level
(ELVR register).
Occurrence of interval timer interrupt:
With bit0 (OSCD1 bit) of STCR (standby control register) set to "0", when an interrupt request of
the interval timer occurs, the stop mode is cancelled, performing a transition to the RUN state
(normal state).
In order not to cancel the stop mode even if an interrupt request occurs, stop the interval timer, or set
interrupt disable to the interrupt enabling bit of the interval timer.
Occurrence of setting initialization reset (INIT) request:
When a setting initialization reset (INIT) request occurs, a transition is unconditionally made to the
INIT state.
Occurrence of operation initialization reset (RST) request:
When an operation initialization reset (RST) request occurs, a transition is unconditionally made to
the RST state.
[Clock source selection when stop mode enabled]
Before setting the stop mode, set the clock source selection so that PLL output is not selected. The
restrictions on the frequency division rate setting are the same as in the normal operation.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4 Shut-down Mode
MB91461
6.4
Shut-down Mode
The Leake current at the standby can be greatly decreased with the shutdown mode in
the mode that stops the power supplies other than RAM and a part of control logic.
All register settings except RAM* and the returning factor flag of shut-down state are not held. The
necessary information need to be stored in RAM before performing a transition to the shut-down mode. In
the shut-down mode, all output is placed in the high-impedance state except keeping output of the external
bus control signal. Returning from the shut-down mode is performed when a previously specified external
interrupt signal is asserted or INITX (external reset pin) is asserted. Returning from the shut-down mode
cannot be performed by NMI input.
*: 64 Kbytes RAM (ID-RAM) for instruction/data use (0003:0000H to 0003:FFFFH).
● SHDE: Shut-down control register
Figure 6.4-1 The Structure of Shut-down Control Register
Address: 0004D4H
bit
Read/Write
Initial value
7
6
5
4
3
2
1
0
SDENB
R/W
0
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
−
−
X
X
X
X
X
X
X
(INITX pin, restart from shut-down mode)
Initial value
Held
X
(Software reset, watchdog reset)
This register is used to enable the shut-down mode.
SDENB (bit7): Shut-down enable
"1": Shut-down mode enabled.
"2": Shut-down mode disabled.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4 Shut-down Mode
MB91461
● EXTE: External interrupt enable register
Figure 6.4-2 The Structure of External Interrupt Enable Register
Address: 0004D6H
bit
Read/Write
Initial value
7
6
5
4
3
2
1
0
RX1
R/W
0
RX0
R/W
0
INT7
R/W
0
INT6
R/W
0
INT3
R/W
0
INT2
R/W
0
INT1
R/W
0
INT0
R/W
0
Held
Held
Held
Held
Held
(INITX pin, restart from shut-down mode)
Initial value
Held
Held
Held
(Software reset, watchdog reset)
This register is used to select a factor causing return from the shut-down mode.
To set this register to the enabled factor causing return, set the bit of this register corresponding to interrupt
or CAN receive signal (RX) to "1". Each bit is cleared when returning from the shut-down mode (restart).
Therefore this register need to be set every time before performing a transition to the shut-down mode.
● EXTF: External interrupt factor flag
Figure 6.4-3 The Structure of External Interrupt Factor Flag
Address: 0004D7H
bit
Read/Write
Initial value
7
6
5
4
3
2
1
0
RX1
R/W
0
RX0
R/W
0
INT7
R/W
0
INT6
R/W
0
INT3
R/W
0
INT2
R/W
0
INT1
R/W
0
INT0
R/W
0
Held
Held
Held
Held
Held
Held
Held
Held
(INITX pin)
Initial value
(Software reset, restart from shut-down, watchdog reset)
This register is a factor causing return from the shut-down mode.
When there is an input of enable factor causing return, the corresponding flag is set to "1". This register can
be written "0". To clear these flags, set to "0" by the CPU instruction or reset through INITX pin.
When the first factor is received after transition to the shut-down mode, the information is held in flag and
the reset sequence to return starts immediately (approximately 100 μs later). Therefore even if there are
several factors causing return, the subsequent factors are not received and the flag is not held.
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4 Shut-down Mode
MB91461
● EXTLV1: External interrupt level register
Figure 6.4-4 The Structure of External Interrupt Level Register
Address: 0004D8H
bit
Read/Write
Initial value
7
6
5
4
3
2
1
0
LB7
R/W
0
LA7
R/W
0
LB6
R/W
0
LA6
R/W
0
LB5
R/W
0
LA5
R/W
0
LB4
R/W
0
LA4
R/W
0
Held
Held
Held
Held
Held
(INITX pin, restart from shut-down mode)
Initial value
Held
Held
Held
(Software reset, watchdog reset)
● EXTLV2: External interrupt level register
Figure 6.4-5 The Structure of External Interrupt Level Register
Address: 0004D9H
bit
Read/Write
Initial value
7
6
5
4
3
2
1
0
LB3
R/W
0
LA3
R/W
0
LB2
R/W
0
LA2
R/W
0
LB1
R/W
0
LA1
R/W
0
LB0
R/W
0
LA0
R/W
0
Held
Held
Held
Held
Held
(INITX pin, restart from shut-down mode)
Initial value
Held
Held
Held
(Software reset, watchdog reset)
This register is used to specify the interrupt level of the factor causing return from the shut-down mode.
Table 6.4-1 External Interrupt Level Register
LBx
LAx
Interrupt Level
0
0
"L" Level (Initial value)
0
1
"H" Level
1
0
Setting disabled
1
1
Setting disabled
Note: For an interrupt level from the shut-down mode, only L level or H level can be set.
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6.4 Shut-down Mode
MB91461
● Transition to Shut-down Mode
The following procedures are required for transition to the shut-down mode.
1) Set an interrupt signal level to be used for returning from the shut-down mode in EXTLV1 and
EXTLV2 (external interrupt level registers).
2) Set SHDE bit in the SHDE (shut-down control register) to "1" to enable shut-down mode.
3) Set an external interrupt channel to be used for returning in EXTE (external interrupt enable
register). If the SDENB bit is not set to "1" in advance, the return channel cannot be set to "1".
4) Execute the same instructions as those for transition to the stop mode. By executing 1) to 3)
beforehand, it will shift to the shut-down mode after executing the next instruction sequence.
(LDI
#value_of_stop, R0)
; value_of_sleep is write data to STCR
(LDI
#_STCR, R12)
; _STCR is STCR address (481H)
STB
R0, @R12
; Writing to standby control register (STCR)
LDUB @R12, R0
; Reading STCR for synchronous standby
LDUB @R12, R0
; Once more dummy reading of STCR
NOP
; Five NOPs for coordinate the timing
NOP
NOP
NOP
NOP
During the shut-down mode, though the external bus control signal keeps the last value before the transition
to the shut-down mode, all other output is placed in Hi-Z. Input of the pin for return from the shut-down
mode keeps input threshold and pull-up/pull-down setting until a factor causing return is received. During
the shut-down mode, oscillation is stopped and also power supply to the internal logics is stopped except
RAM* to and the shut-down control logic.
*
152
64 Kbytes RAM (ID-RAM) for instruction/data use (0003:0000H to 0003:FFFFH).
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4 Shut-down Mode
MB91461
[Pin state during shut-down mode]
Table 6.4-2 Pin State During Shut-down Mode
Pin name
Pin state
WDRESETX
ASX
CS0X, CS1X, CS2X, CS3X,
CS4X
IORDX
IOWRX
RDX
WR0X, WR1X
BGRNTX
Keeps the last state before the transition to the shut-down
mode.
INT0, INT1, INT2, INT3,
INT6, INT7,
RX0/INT8, RX1/INT9
Keeps the input threshold setting and the pull-up/pulldown setting during the shut-down mode.
Returns to the initial value when performing a transition to
reset after the first factor causing return.
SYSCLK
Is placed in Hi-Z state.
Other pins
Are placed in Hi-Z state.
The pull-up/pull-down setting returns to the initial value.
● Return from Shut-down Mode
When an enable level is input to the external interrupt pin set by the external interrupt enable register, reset
is performed and the device restarts after starting power supply to the internal logics and waiting
stabilization of oscillation. In this case, the factor causing return from the shut-down mode is held in the
external interrupt factor flag register (EXTF). A software can determine whether the initial start-up process
or the return process from the shut-down mode by detecting the flag register value in the initial setting
routine. During the return process, a factor of the subsequent interrupt input after the first factor causing
return is not held.
[Return by interrupt pin]
Regarding the factor causing return from the shut-down mode, when the first factor is received, the
information is held in the flag and the reset sequence begins. Even if there are several factors causing
return, the subsequent factors are not received and the flag is not held.
When a factor causing return from the shut-down mode is received, all pins return to the reset state.
Therefore the input threshold setting and the pull-up/pull-down setting of the pins for returning return to
the initial state.
When a factor causing return is received, the device restarts through the following process.
1) Reactivating power supply from the internal regulator.
2) Waiting for stabilization of the oscillation.
3) Reset cancellation, mode vector fetch, and reset vector fetch.
During the shut-down mode, the input threshold setting of the pin for returning keeps the last value
before the transition to the shut-down mode.
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6.4 Shut-down Mode
MB91461
When a return is performed by an interrupt, the interrupt request level setting register (ELVR) cannot be
used for edge detection.
[Return by INITX pin]
When the "L" level is input to INITX pin, the reset is performed. In this case, all interrupt factor flags
are cleared.
Unlike the return by the interrupt pin, there is no time for waiting for stabilization of the oscillation.
Always keep INITX input more than 8 ms to make time for stabilization of the oscillation.
Note:
NMI cannot be used for return from the shut-down mode.
RTC operation stops during the shut-down mode.
• When using the level as the interrupt factor, input a 500μs or higher level. When this specification
is not satisfied, the MCU malfunctions. It is recommended that the edge is used for recovery from
the shutdown state.
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CHAPTER 7
HARDWARE WATCHDOG
TIMER
This chapter explains the functions of hardware
watchdog timer.
7.1 Overview of Hardware Watchdog Timer
7.2 Configuration of Hardware Watchdog Timer
7.3 Hardware Watchdog Timer Register
7.4 Function of Hardware Watchdog Timer
7.5 Notes on Using Hardware Watchdog Timer
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.1 Overview of Hardware Watchdog Timer
7.1
MB91461
Overview of Hardware Watchdog Timer
Hardware watchdog timer issues the reset signal (setting initialization reset) when
internal counter is not cleared for a specified period.
■ Hardware Watchdog Timer
Hardware watchdog timer is a module for CPU operation monitoring. This timer immediately starts count
up after the setting initialization reset (INIT). This timer must periodically be cleared within a specified
period to continue the program execution. When the counter is not cleared over a specified period, such as
entering to infinite loop, the reset signal is issued.
The width of "L" pulse which is outputted to the external pin WDRESETX is 128 cycles of source
oscillation clock, and the width of internal reset is 1024 cycles of the clock.
Note:
When CPU transfers to the mode which stops operations (standby mode) as follows, the operation of
this module is also stopped.
• SLEEP mode:
CPU stop, peripheral circuit operation
• STOP mode:
CPU and peripheral circuit operation are stopped.
• SHUT-DOWN mode: CPU and peripheral circuit operation are stopped.
• RTC mode:
CPU and peripheral circuits except for RTC module are stopped. Oscillator
operation
• Debug mode:
When a break is generated by DSU (Debug Support Unit) and debug
routine is running.
If one of the following conditions is met, hardware watchdog timer is cleared.
• "0" writing to CL bit of HWDCS register
• Reset
• Oscillation stops
• Transfer to SLEEP/STOP/SHUT-DOWN, RTC, or Debug mode
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.2 Configuration of Hardware Watchdog Timer
MB91461
7.2
Configuration of Hardware Watchdog Timer
Hardware watchdog timer consists of the following two circuits.
• Watchdog timer
• Hardware watchdog timer control register
■ Block Diagram of Hardware Watchdog Timer
Figure 7.2-1 Block Diagram of Hardware Watchdog Timer
X0/X1 input or
oscillation circuit
1/2
Counter
FF
Reset signal
Clear
Reserved Reserved Reserved Reserved
CL
Reserved Reserved
CPUF
Internal bus
● Watchdog timer
This is a timer for monitoring CPU operation. Clear it periodically after reset releasing.
● Hardware watchdog timer control register
This register has a reset flag and clear bit of timer.
● Reset issuance
If the timer is not cleared over a specified period, the hardware watchdog timer module issues the setting
initialization reset (INIT). The width of internal reset signal is 1024 cycles of source oscillation clock.
● Operating clock for watchdog timer
The operating clock for the watchdog timer is a clock derived from X0 (external input or crystal oscillator).
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.3 Hardware Watchdog Timer Register
7.3
MB91461
Hardware Watchdog Timer Register
Hardware watchdog timer control register has a reset flag and a watchdog timer clear
bit.
■ Hardware Watchdog Timer Register
Figure 7.3-1 The Structure of Hardware Watchdog Timer Register
HWDCS
bit
7
6
5
4
Address: 0004C7H
Reserved Reserved Reserved Reserved
Read/Write R/W
R/W
R/W
R/W
Initial value
0
0
0
1
3
CL
W
1
2
1
Reserved Reserved
R/W
0
R/W
0
0
CPUF
R/W
0
[bit7 to bit4] Reserved: Reserved bits
These are reserved bits.
Be sure to set these bits to 0001B.
[bit3] CL: Timer clear bit
This bit is a watchdog timer clear bit.
Writing "0" to this bit clears the watchdog timer.
Reading value is always "1". Writing "1" is invalid.
[bit2, bit1] Reserved: Reserved bits
These are reserved bits.
Be sure to set these bits to 00B.
[bit0] CPUF: CPU reset flag
When overflow is generated in watchdog timer, this bit is set to "1".
Writing "0" clears this bit. Writing "1" is invalid.
This bit is initialized by external reset input (INITX) but not by internal reset (software reset).
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.3 Hardware Watchdog Timer Register
MB91461
■ Hardware Watchdog Timer Period Register
Figure 7.3-2 Hardware Watchdog Timer Period Register
HWWDE
bit
7
6
5
4
3
2
Address: 0004C6H
Reserved Reserved Reserved Reserved Reserved Reserved
Read/write
Initial value
-
1
0
ED1
R/W
0
ED0
R/W
0
[bit7 to bit2] Reserved: Reserved bit
These are reserved bits.
[bit1, bit0] ED1, ED0: Watchdog period setting
This bit sets a watchdog period.
ED1
ED0
Function
0
0
Watchdog period is 216*CR clock cycles (Initial value)
0
1
Watchdog period is 217*CR clock cycles
1
0
Watchdog period is 218*CR clock cycles
1
1
Watchdog period is 219*CR clock cycles
Notes:
• This function cannot be used with MB91461.
• This function is not revokable from an initial value at the cycle though operates by the CR
oscillation in MB91V460 (It is not revokable from 216 × CR).
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7.4 Function of Hardware Watchdog Timer
7.4
MB91461
Function of Hardware Watchdog Timer
If the watchdog timer is not cleared over a specified period, the setting initialization
reset (INIT) is issued. In this case, the register value of CPU is not guaranteed.
■ Function of Hardware Watchdog Timer
After a reset is released, the hardware watchdog timer starts counting up without waiting the stabilization
time. If the timer is not cleared for a specified time and the counter overflows, the setting initialization reset
(INIT) is issued.
■ Cycle of Hardware Watchdog Timer
The bit length of the hardware watchdog timer is 23 bits and the overflow period is 932.1 ms (when source
oscillation is 18 MHz).
Table 7.4-1 Hardware Watchdog Timer Period
9 MHz
18 MHz
Watchdog timer
operation clock cycle
0.22 μs
0.11 μs
Watchdog timer cycle
1864.1 ms
932.1 ms
WDRESETX output pulse width
14.22 μs
7.11 μs
Time required for starting external bus cycle after
WDRESETX is asserted
113.78 μs
56.89 μs
■ Reset Timing for Watchdog Timer Overflow
Figure 7.4-1 Reset Timing for Watchdog Timer Overflow
(at 18 MHz oscillation)
7.11µs
WDRESETX
Internal reset
160
56.89µs
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.4 Function of Hardware Watchdog Timer
MB91461
■ About WDRESETX Pin Output
"L" level by the external reset input (INITX) as well as "L" pulse when the hardware watchdog timer
overflows is outputted to the WDRESETX pin.
When a watchdog reset is generated, the flash memory returns to the read mode even if the flash memory is
in the write/erase mode by connecting the WDRESETX pin and a RESET pin of the external flash
memory.
Pulses of resets generated by the watchdog timer that is activated by CPU core internal software and pulses
of software resets are not outputted to the WDRESETX pin. Therefore, these resets cannot be used as a
factor that triggers the return of the flash memory from the write/erase mode.
Note:
There is no WDRESETX output in MB91V460. Please note that the WDRESETX output cannot be
used when ICE is used and operated.
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CHAPTER 7 HARDWARE WATCHDOG TIMER
7.5 Notes on Using Hardware Watchdog Timer
7.5
MB91461
Notes on Using Hardware Watchdog Timer
This section explains the notes on using hardware watchdog timer.
■ Notes on Using Hardware Watchdog Timer
● Stop disabled in software
Watchdog timer immediately starts operation after releasing reset. The counting cannot be stopped by
software.
● Reset control
Clearing of the timer is required to control hardware watchdog reset. When "0" is written to CL bit of the
hardware watchdog timer control register, the timer is once cleared and the reset issuance is controlled.
● Stop and clear of timer
In the mode which CPU is not operating (SLEEP mode, STOP mode, SHUT-DOWN mode and RTC
mode), the timer is cleared before transferring to such mode and the count is stopped. Also, when a debug
routine is running via DSU, the watchdog timer is cleared and the count is stopped.
● Operation during DMA transfer
Writing "0" to CL bit is disabled since DMAC is occupying the bus during the DMA transfer to peripheral
resources that are connected to internal D-bus. Therefore, in the case that DMA transfer time is longer than
watchdog cycle, a reset is issued.
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CHAPTER 8
EXTERNAL BUS INTERFACE
This chapter explains each function of the external bus
interface.
8.1 Features of External Bus Interface
8.2 External Bus Interface Registers
8.3 Chip Select Area
8.4 Endian and Bus Access
8.5 Normal Bus Interface
8.6 Address/Data Multiplex Interface
8.7 DMA Access
8.8 Procedure for Setting Registers
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.1 Features of External Bus Interface
8.1
MB91461
Features of External Bus Interface
This section explains the features of the external bus interface.
■ Features of External Bus Interface
• Addresses of up to 24-bit length can be outputted.
• Various types of external memory (8-bit/16-bit) can be directly connected and multiple access timings
can be mixed and controlled.
- Asynchronous SRAM and asynchronous ROM/FLASH memory
(Multiple write strobe method)
- Address/data multiplex bus (8-bit/16-bit width only)
• Five independent banks (chip select areas) can be set, and chip select corresponding to each bank can be
outputted.
- CS0 to CS4 can be set to the space between 00040000H and 00FFFFFFH in units of 64 Kbytes to
2048 Mbytes.
- Boundaries may be limited depending on the size of the area.
• In each chip select area, the following functions can be set independently:
- Enabling and disabling of the chip select area
(Disabled areas cannot be accessed)
- Setting of the access timing type such as support for various types of memory
- Detailed access timing setting
(Individual setting of the access type such as the wait cycle)
- Setting of the data bus width (8-bit/16-bit)
• A different detailed timing can be set for each access timing type.
- For the same type of access timing, a different setting can be made in each chip select area.
- Auto-wait can be set to up to 7 cycles.
(Asynchronous SRAM, ROM, Flash and I/O area)
- The bus cycle can be extended by external RDY input.
(Asynchronous SRAM, ROM, Flash and I/O area)
- Various types of idle/recovery cycles and setup delays can be inserted.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.1 Features of External Bus Interface
MB91461
■ Block Diagram of External Bus Interface
Figure 8.1-1 shows the block diagram of external bus interface.
Figure 8.1-1 Block Diagram of External Bus Interface
Internal
Address Bus
32
Internal
Data Bus
32
A-Out
Write
Buffer
Switch
Read
Buffer
Switch
M
U
X
External
Data Bus
Data Block
Address Block
+1 or +2
External
Address Bus
Address
Buffer
Comparator
ASR
ASZ
External Pin Control
All Block Control
Register
&
Control
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
CS0X to CS4X
ASX, RDX
WR0X, WR1X
BRQ
BGRNTX
RDY
SYSCLK
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8.1 Features of External Bus Interface
MB91461
■ I/O Pins
I/O pins are external bus interface pins.
[Normal bus interface]
A23 to A00, D31 to D16 (AD15 to AD00)
CS0X, CS1X, CS2X, CS3X, CS4X
ASX, SYSCLK, RDX, WR0X, WR1X, WEX
RDY, BRQ, BGRNTX
Note:
There is MCLKE, MCLKI or neither MCLKO nor BAAX in MB91461.
■ Register List of External Bus Interface
Figure 8.1-2 lists the register list of external bus interface.
Figure 8.1-2 Register List of External Bus Interface
Address
bit
31
24
23
16
15
8
7
0
000640H
ASR0
ACR0
000644H
ASR1
ACR1
000648H
ASR2
ACR2
00064CH
ASR3
ACR3
000650H
ASR4
ACR4
000660H
AWR0
AWR1
000664H
AWR2
AWR3
000668H
AWR4
Reserved
000678H
IOWR0
IOWR1
IOWR2
Reserved
000680H
CSER
CHER
Reserved
TCR
0007FCH
Reserved
MODR*
Reserved
Reserved
Reserved: Reserved register. Be sure to set "0" at rewrite.
*: MODR cannot be accessed from user programs.
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CHAPTER 8 EXTERNAL BUS INTERFACE
MB91461
8.2
External Bus Interface Registers
8.2 External Bus Interface Registers
This section explains the registers used in the external bus interface.
■ Overview of External Bus Interface Registers
The following seven types of registers are used by the external bus interface:
• Area Select Register (ASR0 to ASR4)
• Area Configuration Register (ACR0 to ACR4)
• Area Wait Register (AWR0 to AWR4)
• I/O Wait Register for DMAC (IOWR0 to IOWR2)
• Chip Select Enable Register (CSER)
• CacHe Enable Register (CHER)
• Terminal and Timing Control Register (TCR)
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8.2 External Bus Interface Registers
8.2.1
MB91461
Area Select Register (ASR0 to ASR4)
This section explains the details of area select registers.
■ Register Configuration of ASR0 to ASR4 (Area Select Register)
Figure 8.2-1 shows the register configuration of ASR0 to ASR4 (area select register).
Figure 8.2-1 Register Configuration of ASR0 to ASR4 (Area Select Register)
ASR0
bit15
...
8
7
6
...
1
0
000640H
A31
...
A24
A23
A22
...
A17
A16
ASR1
bit15
...
8
7
6
1
0
000644H
A31
...
A24
A23
A22
A17
A16
ASR2
bit15
...
8
7
6
1
0
000648H
A31
...
A24
A23
A22
A17
A16
ASR3
bit15
...
8
7
6
1
0
00064CH
A31
...
A24
A23
A22
A17
A16
ASR4
bit15
...
8
7
6
1
0
00064CH
A31
...
A24
A23
A22
A17
A16
...
...
...
...
Initial value
At INIT At RST
Access
0000H
0000H
R/W
XXXXH
XXXXH
R/W
XXXXH
XXXXH
R/W
XXXXH
XXXXH
R/W
XXXXH
XXXXH
R/W
[bit15 to bit0] A31 to A16: Area start address
ASR0 to ASR4 (Area Select Registers 0 to 4) specify the start address of each chip select area for CS0X
to CS4X.
The start address can be set in the high-order 16 bits A[31:16]. Each chip select area starts with the
address set in this register and covers the range set by ASZ[3:0] bits of the ACR0 to ACR4 registers.
The boundary of each chip select area is specified by the setting of ASZ[3:0] bits of the ACR0 to ACR4
registers. For example, if an area of 1Mbyte is set by ASZ[3:0] bits, the low-order 4 bits of the ASR0 to
ASR4 registers are ignored and only A[23:20] bits are valid.
The ASR0 register is initialized to 0000H by INIT or RST. ASR1 to ASR4 are not initialized by INIT or
RST but become undefined. After starting LSI operation, be sure to set the corresponding ASR register
by CSER register before enabling each chip select area.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.2 External Bus Interface Registers
MB91461
8.2.2
Area Configuration Register (ACR0 to ACR4)
This section explains the details of area configuration registers.
■ Register Configuration of Area Configuration Register (ACR0 to ACR4)
Register configuration of ACR0 to ACR4 is as follows.
Figure 8.2-2 Register Configuration of ACR0 to ACR4 (Area Configuration Register)
ACR0 Higher
000642H
ACR0 Lower
000643H
ACR1 Higher
000646H
ACR1 Lower
000647H
ACR2 Higher
00064AH
ACR2 Lower
00064BH
ACR3 Higher
00064EH
ACR3 Lower
00064FH
ACR4 Higher
000652H
ACR4 Lower
000653H
bit15
14
13
12
11
10
9
8
6
5
SREN PFEN WREN
bit15
14
13
4
0
12
R/W
TYP3 TYP2 TYP1 TYP0 00000000B 00000000B
R/W
3
11
2
10
1
9
6
5
4
3
2
1
8
14
13
12
11
10
9
6
5
4
3
2
1
14
13
12
11
10
9
6
5
4
3
2
1
14
13
12
11
10
9
6
5
4
3
2
1
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
8
ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0
bit7
xxxxxxxxB
0
SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0
bit15
xxxxxxxxB
8
ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0
bit7
R/W
0
SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0
bit15
xxxxxxxxB
8
ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0
bit7
xxxxxxxxB
0
SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0
bit15
1111**00B
0
ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0
bit7
Access
1111**00B
ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0
bit7
Initial value
At INIT
At RST
0
SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0
ACR0 to ACR4 (Area Configuration Registers 0 to 4) set the functions of each chip select area.
The same value of the WTH bit of mode vector is written to the initial value of DBW1, DBW0 bit of ACR0.
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8.2 External Bus Interface Registers
MB91461
[bit15 to bit12] ASZ3 to ASZ0 = Area Size bits [3:0]
Table 8.2-1 lists the size of each chip select area by area size bits.
Table 8.2-1 Size of Each Chip Select Area by Area Size Bits
ASZ3
ASZ2
ASZ1
ASZ0
Size of each chip select area
0
0
0
0
64 Kbytes
(00010000H byte, ASR A[31:16] bit specification is valid)
0
0
0
1
128 Kbytes
(00020000H byte, ASR A[31:17] bit specification is valid)
0
0
1
0
256 Kbytes
(00040000H byte, ASR A[31:18] bit specification is valid)
0
0
1
1
512 Kbytes
(00080000H byte, ASR A[31:19] bit specification is valid)
0
1
0
0
1 Mbyte
(00100000H byte, ASR A[31:20] bit specification is valid)
0
1
0
1
2 Mbytes
(00200000H byte, ASR A[31:21] bit specification is valid)
0
1
1
0
4 Mbytes
(00400000H byte, ASR A[31:22] bit specification is valid)
0
1
1
1
8 Mbytes
(00800000H byte, ASR A[31:23] bit specification is valid)
1
0
0
0
16 Mbytes
(01000000H byte, ASR A[31:24] bit specification is valid)
1
0
0
1
32 Mbytes
(02000000H byte, ASR A[31:25] bit specification is valid)
1
0
1
0
64 Mbytes
(04000000H byte, ASR A[31:26] bit specification is valid)
1
0
1
1
128 Mbytes
(08000000H byte, ASR A[31:27] bit specification is valid)
1
1
0
0
256 Mbytes
(10000000H byte, ASR A[31:28] bit specification is valid)
1
1
0
1
512 Mbytes
(20000000H byte, ASR A[31:29] bit specification is valid)
1
1
1
0
1024 Mbytes
(40000000H byte, ASR A[31:30] bit specification is valid)
1
1
1
1
2048 Mbytes
(80000000H byte, ASR A[31] bit specification is valid)
ASZ[3:0] are used to set the size of each area by changing the number of bits for address comparison
with ASR. Thus, an ASR contains bits that are not compared.
ASZ[3:0] bits of ACR0 are initialized to 1111B by RST. Despite this setting, however, the CS0 area just
after RST is exceptionally set from 00000000H to FFFFFFFFH (setting of entire area). The entire area
setting is cancelled after the first writing to ACR0 and an appropriate size is set as indicated in the
above table.
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8.2 External Bus Interface Registers
MB91461
[bit11, bit10] DBW1, DBW0: Data Bus Width 1, 0
Table 8.2-2 lists the data bus width of each chip select area.
Table 8.2-2 Data Bus Width of Each Chip Select Area
DBW1
DBW0
Data bus width
0
0
8-bit
0
1
16-bit (halfwordaccess)
1
0
Reserved, Setting disabled
1
1
Reserved, Setting disabled
(byteaccess)
The same values as those of the WTH bits of the mode vector are written automatically to bits DBW1
and DBW0 of ACR0 during the reset sequence.
[bit9, bit8] BST1, BST0: Burst Size 1, 0
Table 8.2-3 lists the burst size of each chip select area.
Table 8.2-3 Burst Size of Each Chip Select Area
BST1
BST0
Maximum burst size
0
0
1 (Single access)
0
1
2 bursts
1
0
4 bursts
1
1
8 bursts
Areas with the burst size setting other than single access execute continuous burst access within the
address boundary defined by the burst size only when prefetch access is executed or data with size over
bus width is read.
The maximum burst size shall not exceed 2 bursts in 16-bit bus width area.
[bit7] SREN: ShaRed ENable
Table 8.2-4 lists the enabling and disabling of BRQ/BGRNTX sharing in each chip select area.
Table 8.2-4 Enabling and Disabling of BRQ/BGRNTX Sharing in Each Chip Select Area
SREN
Share enabled/disabled
0
BRQ/BGRNTX sharing disabled (CSnX does not become Hi-Z.)
1
BRQ/BGRNTX sharing enabled (CSnX becomes Hi-Z.)
In sharing enabled areas, CSnX becomes Hi-Z when bus is open (when BGRNTX="L" outputting). In
sharing disabled areas, CSnX does not become Hi-Z even when bus is open (when BGRNTX="L"
outputting). Access strobe outputs (RDX, WR1X, WR0X) become Hi-Z only when sharing is enabled
in all areas enabled by CSER.
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MB91461
[bit6] PFEN: PreFetch ENable
Table 8.2-5 lists the enabling and disabling of prefetch in each chip select area.
Table 8.2-5 Enabling and Disabling of Prefetch in Each Chip Select Area
PFEN
Prefetch enabled/disabled
0
Prefetch disabled
1
Prefetch enabled
When an area where prefetch is enabled is read, prefetch is performed to the subsequent address and the
content is stored in a built-in prefetch buffer. When the internal bus accesses to the stored address, the
prefetch data in the prefetch buffer is returned without executing external accesses.
[bit5] WREN: WRite ENable
Table 8.2-6 lists the enabling and disabling of writing to each chip select area.
Table 8.2-6 Enabling and Disabling of Writing to Each Chip Select Area
WREN
Write enabled/disabled
0
Write disabled
1
Write enabled
If an area where write operations are disabled is accessed for a write operation from the internal bus, the
access is ignored and no external access is performed.
Set "1" for the WREN bit of areas where write operations are required, such as data areas.
[bit4] LEND: Little ENDian select
Table 8.2-7 lists the byte ordering in each chip select area.
Table 8.2-7 Byte Ordering in Each Chip Select Area
LEND
Byte ordering
0
Big endian
1
Little endian
LEND bit of ACR0 is constantly set to "0" and so the byte ordering is always big endian.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.2 External Bus Interface Registers
MB91461
[bit3 to bit0] TYP[3:0]: TYPe select
Table 8.2-8 lists the access type of each chip select area.
Table 8.2-8 Access Type of Each Chip Select Area
TYP3
TYP2
TYP1
TYP0
0
X
X
Normal access (Asynchronous SRAM, I/O, ROM/Flash)
1
X
X
Address data multiplex access
(8/16-bit bus width only)
X
0
Disable WAIT insertion by RDY pin
X
1
Enable WAIT insertion by RDY pin
0
X
Use the WR0X and WR1X pins as write strobes
1
X
Setting disabled
0
Setting disabled
1
Setting disabled
0
Access type
X
0
1
0
0
1
0
Setting disabled
0
1
1
Setting disabled
1
0
0
Setting disabled
1
0
1
Setting disabled
1
1
0
Setting disabled
1
1
1
Mask area setting
(The access type is the same as that of the overlapped area) *
Set the access type in combination of each bit.
*: CS area mask setting function
If you want to define an area in where some of the operation settings are changed in a certain CS area
(hereinafter referred to as the base setting area), you can set ACR:TYP[3:0]=1111B in the setting of
another CS area so that the area can function as a mask setting area.
If you do not use the mask setting function, disable the settings of any overlapping area over multiple
CS areas.
Access operations to the mask setting area are as follows:
- CSX corresponding to a mask setting area is not asserted.
- CSX corresponding to a base setting area is asserted.
- For the following ACR settings, the settings on the mask setting area side become valid:
CM71-10159-2E
bit11, bit10 (DBW1, DBW0):
Bus width setting
bit9, bit8 (BST1, BST0):
Burst size setting
bit7 (SREN):
Sharing-enable setting
bit6 (PFEN):
Prefetch-enable setting
bit5 (WREN):
Write-enable setting (* For this setting only, a setting that is
different from that of the base setting area is not allowed.)
bit4 (LEND):
Little endian setting
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MB91461
- For the following ACR setting, the setting on the base setting area side becomes valid:
bit3 to bit0 (TYP3 to TYP0): Access type setting
- For the AWR setting, the setting on the mask setting area side becomes valid.
- For the CHER setting, the setting on the mask setting area side becomes valid.
A mask setting area can be set only within a part of another CS area (base setting area). You cannot set
a mask setting area for an area without a base setting area. Also do not overlap mask setting areas. Use
care when setting ASR and ACR:ASZ[1:0] bits.
Notes:
The following restrictions apply for [bit3 to bit0] TYP[3:0]:
• A write-enable setting cannot be implemented by a mask.
• Set the same write-enable setting for the base CS area and the mask setting area.
• If write operations to a mask setting area are disabled, the area is not masked and operates as a
base CS area.
• If write operations to the base CS area are disabled but are enabled to the mask setting area, the
area becomes no base setting area and malfunctions will occur.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.2
MB91461
8.2.3
Area Wait Register (AWR0 to AWR4)
External Bus Interface Registers
This section explains the details of area wait register.
■ Register Configuration of Area Wait Register (AWR0 to AWR4)
Figure 8.2-3 shows the register configuration of AWR0 to AWR3.
Figure 8.2-3 Register Configuration of AWR0 to AWR3
AWR0 Higher bit31
0000 0660H
W15
AWR0 Lower bit23
0000 0661H
W07
AWR1 Higher bit15
30
29
28
27
26
25
24
W14
W13
W12
W11
W10
W09
W08
22
21
20
19
18
17
16
W06
W05
W04
W03
W02
W01
W00
14
13
12
11
10
9
8
0000 0662H
W15
W14
W13
W12
W11
W10
W09
AWR1 Lower
bit7
6
5
4
3
2
1
0000 0663H
W07
W06
W05
W04
W03
W02
W01
30
29
28
27
26
25
W14
W13
W12
W11
W10
W09
22
21
20
19
18
17
W06
W05
W04
W03
W02
W01
14
13
12
11
10
9
AWR2 Higher bit31
0000 0664H
W15
AWR2 Lower bit23
0000 0665H
W07
AWR3 Higher bit15
0000 0666H
W15
W14
W13
W12
W11
W10
W09
AWR3 Lower
bit7
6
5
4
3
2
1
0000 0667H
W07
W06
W05
W04
W03
W02
W01
14
13
12
11
10
9
AWR4 Higher bit15
0000 0668H
W15
W14
W13
W12
W11
W10
W09
AWR4 Lower
bit7
6
5
4
3
2
1
0000 0669H
W07
W06
W05
W04
W03
W02
W01
Initial value
At INIT
At RST
Access
01111111B
01111111B
R/W
11111011B
11111011B
R/W
W08 XXXXXXXXB XXXXXXXXB
R/W
0
W00 XXXXXXXXB XXXXXXXXB
R/W
24
W08 XXXXXXXXB XXXXXXXXB
R/W
16
W00 XXXXXXXXB XXXXXXXXB
R/W
8
W08 XXXXXXXXB XXXXXXXXB
R/W
0
W00 XXXXXXXXB XXXXXXXXB
R/W
8
W08 XXXXXXXXB XXXXXXXXB
R/W
0
W00 XXXXXXXXB XXXXXXXXB
R/W
AWR0 to AWR4 specify various types of wait timing for each chip select area.
The function of each bit changes according to the access type (TYP[3:0] bits) setting of the ACR0 to ACR4
registers.
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8.2 External Bus Interface Registers
MB91461
■ Normal Access and Address/Data Multiplex Access
A chip select area set with the following setting for the access type (TYP[3:0] bits) of ACR0 to ACR4
registers becomes the area either for normal access or address/data multiplex access operation.
Table 8.2-9 Access Type
TYP3
TYP2
TYP1
TYP0
Access type
0
0
X
X
Normal access
(Asynchronous SRAM, I/O, ROM/Flash)
0
1
X
X
Address data multiplex access
(8/16-bit bus width only)
The functions of each bit in AWR0 to AWR3 for a normal access and address/data multiplex access area
are shown below. Since the initial values of the registers other than AWR0 are undefined, set them before
enabling each area by CSER register.
[bit15 to bit12] W15 to W12: First access wait cycle
These bits set the number of auto-wait cycles to be inserted into the first access cycle for each cycle. For
cycles except burst access cycle, only this wait setting is used.
The CS0 area is set to its initial value 7 (wait). The initial values of other areas are undefined.
Table 8.2-10 First Access Wait Cycle
W15
W14
W13
W12
First access wait cycle
0
0
0
0
Auto-wait cycle 0
0
0
0
1
Auto-wait cycle 1
...
1
1
...
1
1
Auto-wait cycle 15
[bit11 to bit8] W11 to W08: Inpage access wait cycle
These bits set the number of auto-wait cycles of inpage access in burst access. These bits are valid only
in burst access cycle.
Table 8.2-11 Inpage Access Wait Cycle
W11
W10
W09
W08
Inpage access wait cycle
0
0
0
0
Auto-wait cycle 0
0
0
0
1
Auto-wait cycle 1
...
1
1
...
1
1
Auto-wait cycle 15
Even if the same value is set to both first access wait cycle and inpage access wait cycle, the access time
from the address in each access cycle is not the same (since the inpage access cycle includes address
output delay).
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8.2 External Bus Interface Registers
MB91461
[bit7, bit6] W07, W06: Read → Write idle cycle
The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a
write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data
pins maintain the Hi-Z state.
If a write cycle follows a read cycle or an access operation to another chip select area occurs after a read
cycle, the specified idle cycle is inserted.
Table 8.2-12 Read → Write Idle Cycle
Read → Write idle cycle
W07
W06
0
0
0 cycle
0
1
1 cycle
1
0
2 cycles
1
1
3 cycles
[bit5, bit4] W05, W04: Write recovery cycle
The write recovery cycle is set to control the access to a device if the device has a limit for the access
interval period after a write access. During a write recovery cycle, all chip select signals are negated and
the data pins maintain the high impedance state.
If the write recovery cycle is set to "1" or more, one or more write recovery cycles are always inserted
after a write access.
Table 8.2-13 Write Recovery Cycle
CM71-10159-2E
W05
W04
Write recovery cycle
0
0
0 cycle
0
1
1 cycle
1
0
2 cycles
1
1
3 cycles
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8.2 External Bus Interface Registers
MB91461
[bit3] W03: WR1X, WR0X output timing selection
The WR1X, WR0X output timing setting is used to select whether to use a write strobe output as an
asynchronous strobe or as a synchronous write enable. Use it as an asynchronous strobe to support
normal memory I/O, and use it as a synchronous enable to support clock synchronous memory I/O
(such as ASIC built-in memory).
Table 8.2-14 WR1X, WR0X Output Timing Selection
W03
WR1X, WR0X output timing selection
0
SYSCLK synchronous write enable output (Valid from ASX="L")
1
Asynchronous write strobe output (Normal operation)
When selecting synchronous write enable (AWR:W03 bit is "0"), its operations are described as
follows:
• Synchronous write enable output timing is the timing based on the assumption that the output is
captured at the rising edge of the SYSCLK output of external memory access clock. The timing is
different from that of asynchronous strobe output.
• The WR1X, WR0X pin output asserts the synchronous write enable output from the timing when
ASX pin output is asserted. When writing to external bus, the synchronous write enable output
outputs "L". When reading from external bus, the synchronous write enable output outputs "H".
• Write data is outputted from the external data output pin in the next cycle of the cycle in which a
synchronous write enable output is asserted.
• The read strobe output (RDX) functions as an asynchronous read strobe regardless of the WR1X,
WR0X output timing setting. Use it for data I/O direction control as it is.
• When using the synchronous write enable output, the following restrictions are applied:
• Do not set the following additional wait settings:
- CSX → RDX/WR1X,WR0X setup setting (Always write "0" for AWR:W01 bit.)
- First access wait cycle setting (Always write 0000B for AWR:W15 to W12 bits.)
• Do not set the following access type settings (TYP[3:0] bits (bit[3:0]) of ACR register):
- Setting that uses WR1X and WR0X as write strobes (Always write "0" for ACR:TYP1 bit.)
- Address/data multiplex bus setting (Always write "0" for ACR:TYP2 bit.)
- RDY input enable setting (Always write "0" for ACR:TYP0 bit.)
• When using synchronous write enable output, always set the burst length to "1" (set 00B for
ACR:BST[1:0] bits).
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8.2 External Bus Interface Registers
MB91461
[bit2] W02: Address → CSX delay
The address → CSX delay setting is set when a certain setup is required for the address when CSX falls,
or when CSX edges are needed even for consecutive accesses to the same chip select area.
Set the delay of CS0X to CS4X output from address or ASX output.
Table 8.2-15 Address → CSX Delay
Address → CSX delay
W02
0
No delay
1
Delay
If no delay is selected by setting "0", assertion of CS0X to CS4X starts at the same timing that ASX is
asserted. If, at this point, consecutive accesses are made to the same chip select area, assertion of CS0X
to CS4X may continue during both access operations without change.
If delay is specified by selecting "1", assertion of CS0X to CS4X starts when the external memory clock
SYSCLK output rises. If, at this point, consecutive accesses are made to the same chip select area,
CS0X to CS4X negate timing occurs during both access operations.
If CSX delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion
of the delayed CSX (operation is the same as the CSX → RDX/WR1X,WR0X setup setting of W01).
[bit1] W01: CSX → RDX/WR1X,WR0X setup extension cycle
The CSX → RDX/WR1X,WR0X setup extension cycle is set to extend the period before the read/write
strobe is asserted after CSX is asserted. At least one setup extension cycle is inserted before the read/
write strobe is asserted after CSX is asserted.
Table 8.2-16 CSX → RDX/WR1X,WR0X Setup Extension Cycle
CSX → RDX/WR1X,WR0X setup extension cycle
W01
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", RDX/WR1X,WR0X are outputted, at the fastest, from the rising of
external memory clock SYSCLK output right after CSX assertion. Depending on the internal bus
condition, WR0X and WR1X may be delayed one or more cycles.
If 1 cycle is selected by setting "1", RDX/WR1X,WR0X are outputted with delay of one or more
cycles.
When making consecutive accesses within the same chip select area without negating CSX, this setup
extension cycle is not inserted. If a setup extension cycle for determining the address is required, enable
W02 bit and insert the address → CSX delay so that CSX is once negated for each access operation and
this setup extension cycle is enabled.
If CSX delay setting of W02 is inserted, this setup cycle becomes valid regardless of the W01 bit
setting.
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8.2 External Bus Interface Registers
MB91461
[bit0] W00: RDX/WR1X,WR0X → CSX hold extension cycle
The RDX/WR1X,WR0X → CSX hold extension cycle is set to extend the period before negating CSX
after the read/write strobe is negated. One hold extension cycle is inserted before CSX is negated after
the read/ write strobe is negated.
Table 8.2-17 RDX/WR1X,WR0X → CSX Hold Extension Cycle
RDX/WR1X,WR0X → CSX hold extension cycle
W00
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", CS0X to CS3X are negated after passing the hold delay from the
rising edge of external memory clock SYSCLK output after RDX/WR1X,WR0X are negated.
If 1 cycle is selected by setting "1", CS0X to CS4X are negated one cycle later.
When making consecutive accesses within the same chip select area without negating CSX, this hold
extension cycle is not inserted. If a hold extension cycle for determining the address is required, enable
W02 bit and insert the address → CSX delay so that CSX is once negated for each access operation and
this hold extension cycle is enabled.
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8.2 External Bus Interface Registers
MB91461
8.2.4
I/O Wait Register for DMAC (IOWR0 to IOWR2)
This section explains the details of I/O wait register.
■ Register Configuration of IOWR0 to IOWR2
Register configuration of IOWR0 to IOWR2 are as follows.
Figure 8.2-4 Register Configuration of IOWR0 to IOWR2
IOWR0
bit31
30
29
28
27
0000 0678H RYE0 HLD0 WR01 WR00 IW03
IOWR1
bit23
22
21
20
19
0000 0679H RYE1 HLD1 WR11 WR10 IW13
IOWR2
bit15
14
13
12
11
0000 067AH RYE2 HLD2 WR21 WR20 IW23
26
25
24
IW02
IW01
IW00
18
17
16
IW12
IW11
IW10
10
9
8
IW22
IW21
IW20
Initial value
At INIT
At RST
Access
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
xxxxxxxxB
xxxxxxxxB
R/W
[bit31, bit23, bit15] RYE0, RYE1, RYE2: RDY function setting (ReadY Enable 0, 1, 2)
These bits are used to set wait control settings by RDYI for each ch.0 to ch.2 during DMA fly-by
access.
Table 8.2-18 RDY Function Setting
RYEn
RDY function setting
0
RDY input for I/O access is disabled
1
RDY input for I/O access is enabled.
Setting "1" enables wait insertion by RDYI pin during a fly-by transfer in the corresponding channel.
IOWRX and IORDX are extended until RDYI pin is enabled. In synchronization with that extension,
RDX/WR1X,WR0X on the memory side are also extended.
When RDY enable setting is set for the chip select area of the fly-by transfer target by ACR register,
wait insertion by RDYI pin is enabled regardless of RYEn bit of the IOWRX side. Even when RDY
disable setting is set for the chip select area of the fly-by transfer target by ACR register, wait insertion
by RDYI pin is enabled only for fly-by access if RDY is enabled by RYEn bit of the IOWRX side.
If RDY is enabled by fly-by write access to SDRAM, be sure to enable HLD bit before setting the hold
wait.
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8.2 External Bus Interface Registers
MB91461
[bit30, bit22, bit14] HLD0, HLD1, HLD2: Hold wait setting
These bits are used to control the hold cycle of read strobe signal at the transfer source access side
during DMA fly-by access.
Table 8.2-19 Hold Wait Setting
HLDn
Hold wait setting
0
Hold extension cycle is not inserted.
1
Hold extension cycle is inserted to extend read cycle by one cycle
When "0" is set, a read strobe signal of the transfer source access side (RDX0 if memory → I/O, or
IORDX if I/O → memory) and a write strobe signal (IOWRX if memory → I/O, or WRXO[3:0] or
WEX if I/O → memory) are outputted at the same timing.
When "1" is set, read strobe signal is outputted "1" cycle longer to the write strobe signal to ensure the
hold time for transferring data at transfer source access side to the transfer target.
If RDY is enabled by fly-by write access to SDRAM, be sure to enable HLD bit before setting the hold
wait.
[bit29, bit28, bit21, bit20, bit13, bit12] WR01, WR00, WR11, WR10, WR21, WR20: I/O idle cycle setting
These bits are used to set the idle cycle setting for consecutive I/O accesses during DMA fly-by access.
Table 8.2-20 I/O Idle Cycle Setting
WRn1
WRn0
I/O idle cycle setting
0
0
0 cycle
0
1
1 cycle
1
0
2 cycles
1
1
3 cycles
If setting to have one or more idle cycles, idle cycles of the set cycle number are inserted after I/O
access during DMA fly-by access. During idle cycle, all CSXs and strobe outputs are negated and data
pins become high impedance.
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8.2 External Bus Interface Registers
MB91461
[bit27 to bit24, bit19 to bit16, bit11 to bit8]
IW03 to IW00, IW13 to IW10, IW23 to IW20: I/O wait
cycle
These bits are used to specify the auto-wait cycle in I/O access during DMA fly-by access.
Table 8.2-21 I/O Wait Cycle
IWn3
IWn2
IWn1
IWn0
I/O wait cycle
0
0
0
0
0 cycle
0
0
0
1
1 cycle
...
1
1
...
1
1
15 cycles
For the number of wait cycles to be inserted, the cycle number set in the IWnn bit setting of the I/O side
or the cycle number set in the wait setting of the fly-by transfer target (such as memory), whichever is
greater is used for data synchronization between the transfer source and transfer target. For this reason,
more wait cycles than the cycle number set in the IWnn bit may be inserted.
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8.2 External Bus Interface Registers
8.2.5
MB91461
Chip Select Enable Register (CSER)
This section explains the details of chip select enable register.
■ Register Configuration of Chip Select Enable Register (CSER)
Register configuration of CSER is as follows.
Figure 8.2-5 Register Configuration of CSER
Address:
0000 0680H
bit31
30
29
28
Reserved Reserved Reserved
27
26
25
24
Initial value
At INIT
At RST
Access
CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B
R/W
This register enables and disables each chip select area.
[bit31 to bit29] Reserved: Reserved bits
Be sure to set these bits to 000B.
[bit28 to bit24] CSE4 to CSE0: Chip select area enable (Chip select enable 0 to 4)
These bits are the chip select area enable bits for CS0X to CS4X.
The initial value is 00001B, which is enabled only in the CS0 area.
When "1" is written, a chip select area operates according to the settings of ASR0 to ASR4, ACR0 to
ACR4, and AWR0 to AWR4.
Before enabling, be sure to make all settings for the corresponding chip select areas.
Table 8.2-22 Area Control
CSE4 to CSE0
Area control
0
Disabled
1
Enabled
Table 8.2-23 lists CSX corresponding to CSE bit.
Table 8.2-23 CSX Corresponding to CSE Bit
CSE bit
184
Corresponding CSX
Bit [24]:CSE0
CS0X
Bit [25]:CSE1
CS1X
Bit [26]:CSE2
CS2X
Bit [27]:CSE3
CS3X
Bit [28]:CSE4
CS4X
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.2 External Bus Interface Registers
MB91461
8.2.6
CacHe Enable Register (CHER)
This section explains the details of cache enable register.
■ Register Configuration of Cache Enable Register (CHER)
Figure 8.2-6 shows the register configuration of CacHe Enable Register (CHER).
Figure 8.2-6 Register Configuration of CacHe Enable Register (CHER)
Address:
000681H
bit23
22
21
20
Reserved Reserved Reserved
19
18
17
16
Initial value
At INIT
At RST
CHE4 CHE3 CHE2 CHE1 CHE0 11111111B 11111111B
Access
R/W
CHER controls capturing the data read from each chip select area into the built-in cache.
[bit20 to bit16] CHE4 to CHE0: Cache area setting (Cache Enable 4 to 0)
These bits specify to enable or disable cache for each chip select area.
Table 8.2-24 Cache Area Setting
CHE4 to CHE0
CM71-10159-2E
Cache area setting
0
Non-cache area (Data read from this area is not stored in cache.)
1
Cache area (Data read from this area is stored in cache.)
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8.2 External Bus Interface Registers
8.2.7
MB91461
Terminal and Timing Control Register (TCR)
This section explains the details of terminal and timing control register.
■ Register Configuration of Terminal and Timing Control Register (TCR)
Figure 8.2-7 Register Configuration of Terminal and Timing Control Register (TCR)
Address:
bit23
22
21
0000 0683H BREN PSUS PCLR
20
19
18
17
Reserved Reserved Reserved
16
Initial value
At INIT
At RST
RDW1 RDW0 00000000B 0000XXXXB
Access
R/W
The TCR controls functions relating to the external bus interface controller in general such as function
settings and timing controls.
[bit7] BREN: BRQ input enable setting (BRQ enable)
This bit enables BRQ pin input to share an external bus.
Table 8.2-25 BRQ Input Enable Setting
BREN
BRQ input enable setting
0
Bus is not shared by BRQ/BGRNTX. BRQ input is disabled.
1
Bus is shared by BRQ/BGRNTX. BRQ input is enabled.
In the initial state ("0"), BRQ input is ignored.
When "1" is set, after BRQ input becomes "H", the bus is opened (high impedance control) at the bus
opening becomes possible, and BGRNTX is activated ("L" output).
[bit6] PSUS: Prefetch suspension (Prefetch SUSpend)
This bit controls temporary stop of prefetch to all areas.
Table 8.2-26 Prefetch Control
PSUS
Prefetch control
0
Prefetch enabled
1
Prefetch suspended
When "1" is set, a new prefetch operation will not be executed until "0" is written. In this period,
contents in a prefetch buffer will not be erased unless any error occurs to the prefetch buffer. Before
restarting prefetch, clear the prefetch buffer by using bit5:PCLR bit function.
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8.2 External Bus Interface Registers
MB91461
[bit5] PCLR: Prefetch buffer all clear (Prefetch buffer CleaR)
This bit clears all prefetch buffer contents.
Table 8.2-27 Prefetch Buffer Control
PCLR
Prefetch buffer control
0
Normal state
1
Prefetch buffer clear
When writing "1", all prefetch buffer contents are cleared once. After buffer clear is completed, the bit
value is automatically returned to "0". Set PSUS bit to suspend prefetch (set the bit to "1") before
clearing buffer. (You can write 11B to PSUS and PCLR bits at the same time.)
[bit4 to bit2] Reserved: Reserved bits
These are reserved bits. Be sure to set "0".
[bit1, bit0] RDW[1:0]: Wail cycle reduction (ReDuce Wait cycle)
For all chip select areas and I/O channels for fly-by, these bits reduce setting values of automatic access
cycle wait only for the auto-wait cycle all at once without changing the setting values of AWR registers.
The settings for the idle cycle, recovery cycle, setup cycle and hold cycle are not affected.
Table 8.2-28 Wait Cycle Reduction
RDW1
RDW0
Wait cycle reduction
0
0
Normal wait (Setting values of AWR0 to AWR4)
0
1
1/2 of the setting values of AWR0 to AWR4 (Right-shifted by 1 bit)
1
0
1/4 of the setting values of AWR0 to AWR4 (Right-shifted by 2 bits)
1
1
1/8 of the setting values of AWR0 to AWR4 (Right-shifted by 3 bits)
This function is for preventing the excess access cycle wait during low-speed clock operations, such as
while a base clock is low speed or a time division setting of the external bus clock is large.
Normally in such a case, you have to rewrite all AWRs to change wait cycle settings. However, by
using the RDW[1:0] bit function, only access cycle wait values can be reduced all at once without
changing all other AWR settings and so they remain as high-speed clock settings.
Be sure to reset RDW[1:0] bits to 00B before changing the clock setting back to high-speed.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.3 Chip Select Area
8.3
MB91461
Chip Select Area
In the external bus interface, a total of five chip select areas can be set.
The address space of each area can be set in 4 GB space using ASR0 to ASR4 (Area
Select Register) and ACR0 to ACR4 (Area Configuration Register). CS0X to CS4X can be
set in the space between 00040000H and FFFFFFFFH in units of 64 Kbytes to 2048
Mbytes.
When bus access is made to an area specified by these registers, the corresponding
chip select signals CS0X-CS4X become active ("L" output) during the access cycle.
■ Example of Setting ASR and ASZ[1:0]
1. ASR1=0001H ACR1 → ASZ[3:0]=0000B
Chip select area 1 is assigned to 00100000H to 0010FFFFH.
2. ASR2=0040H ACR2 → ASZ[3:0]=0100B
Chip select area 2 is assigned to 00400000H to 004FFFFFH.
3. ASR3=0081H ACR3 → ASZ[3:0]=0111B
Chip select area 3 is assigned to 00800000H to 00FFFFFFH.
Since at this point 8 Mbytes is set for ACR → ASZ[3:0], the unit for boundary becomes 8 Mbytes and so
ASR3[22:16] are ignored.
Before writing to ACR0 is done after a reset, 00000000H to FFFFFFFFH have been assigned to chip select
area 0.
Note:
Set the chip select areas so that there is no overlap.
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8.3 Chip Select Area
MB91461
Figure 8.3-1 shows the chip select area.
Figure 8.3-1 Chip Select Area
00000000H
00000000H
00100000H
Area 1
64 Kbytes
00400000H
Area 2
1 Mbyte
Area 0
00800000H
8 Mbytes
Area 3
00FFFFFFH
FFFFFFFFH
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FFFFFFFFH
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8.4 Endian and Bus Access
8.4
MB91461
Endian and Bus Access
There is a one-to-one correspondence between the WR1X,WR0X control signal and the
byte location on the data bus regardless of the data bus width.
The following summarizes the location of bytes on the data bus used with the specified
data bus width and the corresponding control signal for each bus mode.
■ Relation Ship Between Data Bus Width and Control Signal
● Control signal of normal bus interface
Figure 8.4-1 shows the control signal of normal bus interface.
Figure 8.4-1 Control Signal of Normal Bus Interface
a)16-bit bus width
Data bus
D31
Control
signal
b) 8-bit bus width
Data bus
WR0X
Control
signal
WR0X
D24
WR1X
D16
● Control signal of Time division I/O interface
Figure 8.4-2 shows the control signal of time division I/O interface.
Figure 8.4-2 Control Signal of Time Division I/O Interface
a)16-bit bus width
Data bus
D31
D16
190
b) 8-bit bus width
Output
address
Control
signal
A15 to A08
WR0X
A07 to A00
WR1X
Data bus
Output
address
A07 to A00
−
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Control
signal
WR0X
−
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.4 Endian and Bus Access
MB91461
8.4.1
Big Endian Bus Access
MB91461 allows you to switch between big endian and little endian for each chip select
except CS0 area. When LEND bit of ACR register is set to "1", the area is treated as little
endian.
In normal operations, MB91461 executes external bus access using big endian.
■ Data Format of Big Endian
The relationship between the internal register and the external data bus is as follows.
● Word access (when LD, ST instruction executed)
Figure 8.4-3 Word Access (When LD, ST Instruction Executed)
Internal
register
D31
AA
D23
BB
D15
External
bus
D31
AA
D23
BB
D15
CC
D7
DD
D0
● Halfword access (when LDUH, STH instruction executed)
Figure 8.4-4 Halfword Access (When LDUH, STH Instruction Executed)
a) Output address lower 00
Internal
External
register
bus
D31
D31
AA
D23
D23
BB
D15
D15
AA
D7
BB
D0
CM71-10159-2E
b) Output address lower 10
Internal
External
register
bus
D31
D31
AA
D23
D23
BB
D15
D15
AA
D7
BB
D0
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8.4 Endian and Bus Access
MB91461
● Byte access (when LDUB, STB instruction executed)
Figure 8.4-5 Byte Access (When LDUB, STB Instruction Executed)
a) Output address lower 00
Internal
register
D31
D23
b) Output address lower 01
External
bus
D31
AA
D23
Internal
register
D31
c) Output address lower 10
External
bus
D31
D31
D23
D23
D23
Internal
register
External
bus
D31
AA
D23
d) Output address lower 11
Internal
register
D31
D23
D23
AA
D15
D15
D15
D7
AA
D15
D15
D7
AA
D15
D7
AA
D0
External
bus
D31
D15
D7
AA
D0
D15
AA
D0
D0
■ Data Bus Width
● 16-bit bus width
Figure 8.4-6 16-bit Bus Width
Internal register
External bus
Output address lower
D31
D23
D15
D07
AA
Read/Write
BB
00
10
AA
CC
BB
DD
D31
D23
CC
DD
● 8-bit bus width
Figure 8.4-7 8-bit Bus Width
Internal register
External bus
Output address lower
D31
D23
D15
D07
192
AA
Read/Write
00
01
10
11
AA
BB
CC
DD
D31
BB
CC
DD
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CM71-10159-2E
CHAPTER 8 EXTERNAL BUS INTERFACE
8.4 Endian and Bus Access
MB91461
■ External Bus Access
External bus access (16-bit/8-bit bus width) is shown by the access type (word/half word/byte access) in
Figure 8.4-8, Figure 8.4-9, Figure 8.4-10. Following are also shown in Figure 8.4-11, Figure 8.4-12, Figure
8.4-13.
PA1/PA0
:
Output A1/A0 :
Lower 2 bits of address specified by program
Lower 2 bits of output address
:
Top byte location of output address
+
:
Data byte location to access
(1) to (4)
:
Bus access count
MB91461 does not detect misalignment errors.
Therefore, for word access, the lower two bits of the output address are always 00B regardless of whether
the lower two bits of address specified by the program are 00B, 01B, 10B or 11B. For halfword access, the
lower two bits of the output address are 00B if the lower two bits specified by the program are 00B or 01B,
and are 10B if 10B or 11B.
● 16-bit bus width
Figure 8.4-8 Word Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(2) Output A1/A0=10B
MSB
(b) PA1/PA0=01B
→ (1) Output A1/A0=00B
(2) Output A1/A0=10B
(c) PA1/PA0=10B
(d) PA1/PA0=11B
→ (1) Output A1/A0=00B → (1) Output A1/A0=00B
(2) Output A1/A0=10B
(2) Output A1/A0=10B
LSB
(1)  00
01
(1)  00
01
(1)  00
01
(1)  00
01
(2)  10
11
(2)  10
11
(2)  10
11
(2)  10
11
16-bit
Figure 8.4-9 Half Word Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(b) PA1/PA0=01B
→ (1) Output A1/A0=00B
(c) PA1/PA0=10B
(d) PA1/PA0=11B
→ (1) Output A1/A0=10B → (1) Output A1/A0=10B
(1)  00
01
(1)  00
01
00
01
00
01
10
11
10
11
(1)  10
11
(1)  10
11
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MB91461
Figure 8.4-10 Byte Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(b) PA1/PA0=01B
(c) PA1/PA0=10B
→ (1) Output A1/A0=01B
→ (1) Output A1/A0=10B → (1) Output A1/A0=11B
(d) PA1/PA0=11B
(1)  00
01
(1)  00
01
00
01
00
01
10
11
10
11
(1)  10
11
(1)  10
11
● 8-bit bus width
Figure 8.4-11 Word Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(2) Output A1/A0=01B
(3) Output A1/A0=10B
(4) Output A1/A0=11B
MSB
(b) PA1/PA0=01B
→ (1) Output A1/A0=00B
(2) Output A1/A0=01B
(3) Output A1/A0=10B
(4) Output A1/A0=11B
(c) PA1/PA0=10B
(d) PA1/PA0=11B
→ (1) Output A1/A0=00B → (1) Output A1/A0=00B
(2) Output A1/A0=01B
(2) Output A1/A0=01B
(3) Output A1/A0=10B
(3) Output A1/A0=10B
(4) Output A1/A0=11B
(4) Output A1/A0=11B
LSB
(1) 
00
(1) 
00
(1)  00
(1)  00
(2) 
01
(2) 
01
(2)  01
(2)  01
(3) 
10
(3) 
10
(3)  10
(3)  10
(4) 
11
(4) 
11
(4)  11
(4)  11
8-bit
Figure 8.4-12 Half Word Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(2) Output A1/A0=01B
194
(b) PA1/PA0=01B
→ (1) Output A1/A0=00B
(2) Output A1/A0=01B
(c) PA1/PA0=10B
(d) PA1/PA0=11B
→ (1) Output A1/A0=10B → (1) Output A1/A0=10B
(2) Output A1/A0=11B
(2) Output A1/A0=11B
(1)  00
(1)  00
00
00
(2)  01
(2)  01
01
01
10
10
(1)  10
(1)  10
11
11
(2)  11
(2)  11
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.4 Endian and Bus Access
MB91461
Figure 8.4-13 Byte Access
(a) PA1/PA0=00B
→ (1) Output A1/A0=00B
(b) PA1/PA0=01B
→ (1) Output A1/A0=01B
(c) PA1/PA0=10B
(d) PA1/PA0=11B
→ (1) Output A1/A0=10B → (1) Output A1/A0=11B
(1)  00
00
00
00
01
(1)  01
01
01
10
10
(1)  10
10
11
11
11
(1)  11
■ Example of Connection with External Devices
Figure 8.4-14 Example of Connection with External Devices
FR Core
WR0X
D31
to
D24
WR1X
D23
to
D16
*: For an 8-bit device, a data bus
on the MSB side is used.
A23
to
A00
A23 to A23 to
A01 A00
0
D31
1
D24 D23
0
D16
D31
D24
8-bit device*
16-bit device*
("0"/"1" Address lower 1 bit)
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8.4 Endian and Bus Access
8.4.2
MB91461
Little Endian Bus Access
MB91461 allow you to switch between big endian and little endian for each chip select
except CS0 area. When LEND bit of ACR register is set to "1", the area is treated as little
endian.
By using bus access operations of the big endian, the little endian bus access of
MB91461 are realized by swapping data bus byte locations based on the bus width but
basically using the same output address order and control signal output as for the big
endian.
When connecting, caution is demanded because the big endian area and little endian
area need to be physically divided.
■ Difference Between Little Endian and Big Endian
The followings explain the difference between little endian and big endian.
• Output address order is the same for big endian and little endian.
• Word access
: Byte data on the MSB side corresponding to the big endian address A01,A00=00B
becomes the byte data on the LSB side in the little endian.
In a word access, all byte locations for the 4 bytes in a word are inverted.
• Halfword access
: Byte data on the MSB side corresponding to the big endian address A00 becomes
the byte data on the LSB side in the little endian.
In a halfword access, byte locations for the 2 bytes in a halfword are inverted.
• Byte access
: Byte locations are the same for big endian and little endian.
■ Restrictions on a Little Endian Area
• If prefetch is enabled for a little endian area, be sure to use a word access to access to the area. If the
data in a prefetch buffer is accessed with using an access other than word-length access, a correct endian
conversion may not be performed and so wrong data will be read. This is due to hardware restrictions of
endian conversion mechanism.
• Do not set any instruction codes in a little endian area.
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8.4 Endian and Bus Access
MB91461
■ Data Format
The relationship between the internal register and the external data bus is as follows.
● Word access (when LD, ST instruction executed)
Figure 8.4-15 Word Access (When LD, ST Instruction Executed)
Internal
register
D31
AA
D23
BB
D15
External
bus
D31
BB
DD
AA
CC
D23
D15
CC
D7
DD
D0
● Halfword access (when LDUH, STH instruction executed)
Figure 8.4-16 Halfword Access (When LDUH, STH Instruction Executed)
a) Output address lower 00
Internal
External
register
bus
D31
D31
BB
D23
D23
AA
D15
D15
AA
D7
BB
D0
b) Output address lower 10
Internal
External
register
bus
D31
D31
BB
D23
D23
AA
D15
D15
AA
D7
BB
D0
● Byte access (when LDUB, STB instruction executed)
Figure 8.4-17 Byte Access (When LDUB, STB Instruction Executed)
a) Output address lower 00
Internal
register
D31
D23
External
bus
D31
AA
D23
b) Output address lower 01
Internal
register
D31
c) Output address lower 10
External
bus
D31
D31
D23
D23
D23
Internal
register
External
bus
D31
AA
D23
d) Output address lower 11
Internal
register
D31
D23
D23
AA
D15
D15
D7
D15
D0
CM71-10159-2E
AA
D15
D7
AA
D15
D15
D7
AA
D0
External
bus
D31
D15
D15
D7
AA
D0
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AA
D0
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8.4 Endian and Bus Access
MB91461
■ Data Bus Width
● 16-bit bus width
Figure 8.4-18 16-bit Bus Width
Internal register
External bus
Output address lower
D31
D23
D15
D07
AA
Read/Write
BB
00
10
DD
BB
CC
AA
D31
D23
CC
DD
● 8-bit bus width
Figure 8.4-19 8-bit Bus Width
Internal register
External bus
Output address lower
D31
D23
D15
D07
198
AA
Read/Write
00
01
10
11
DD
CC
BB
AA
D31
BB
CC
DD
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.4 Endian and Bus Access
MB91461
■ Example of Connection with External Devices
● 16-bit bus width
Figure 8.4-20 16-bit Bus Width
FR Core
WR0X
D31
to
D24
WR1X
D23
to
D16
0
1
D31
D24 D23
Big Endian Area
CM71-10159-2E
A31
to
A01
1
D16
D31
0
D24 D23
D16
Little Endian Area
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8.4 Endian and Bus Access
MB91461
● 8-bit bus width
Figure 8.4-21 8-bit Bus Width
FR Core
WR0X
D31
to
D24
D31
A31
to
A00
D24
Big Endian Area
200
D31
D24
Little Endian Area
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.4 Endian and Bus Access
MB91461
8.4.3
Comparison Of External Accesses In Big Endian and
Little Endian
This section shows a comparison of big endian and little endian external access in word
access, halfword access, and byte access for each bus width.
These figures show that all the accesses become big endian in the internal register if an
area is divided into a big endian area and a little endian area and the data bus is
connected according to the examples for connecting to external devices shown in
"8.4.1 Big Endian Bus Access" and "8.4.2 Little Endian Bus Access".
■ Word Access
Table 8.4-1 Word Access (1 / 2)
Bus width
Big endian mode
Little endian mode
Internal register External pin Control pin
Internal register External pin Control pin
D31
address: "0"
D31
AA
BB
D16
address: "0"
D31
BB
D31
WR0X
AA
WR1X
D16
AA
WR0X
WR1X
AA
BB
BB
D00
D00
(1)
(1)
16-bit bus width
Internal register External pin Control pin
D31
address: "2"
D31
CC
DD
D16
Internal register External pin Control pin
D31
WR0X
address: "2"
D31
DD
CC
WR1X
D16
CC
WR1X
CC
DD
DD
D00
D00
(1)
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WR0X
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8.4 Endian and Bus Access
MB91461
Table 8.4-1 Word Access (2 / 2)
Bus width
Big endian mode
Little endian mode
Internal register External pin Control pin
Internal register External pin Control pin
address: "0" "1"
D31
D31
BB AA
WR0X
D24
D31
address: "0" "1"
D31
AA BB
D24
WR0X
AA
AA
BB
BB
D00
D00
D00
D00
(1)
(1) (2)
(2)
8-bit bus width
Internal register External pin Control pin
address: "2" "3"
D31
D31
CC DD
WR0X
D24
Internal register External pin Control pin
address: "2" "3"
D31
D31
DD CC
WR0X
D24
CC
CC
DD
D00
DD
D00
D00
(1) (2)
D00
(1) (2)
■ Byte Access
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8.4 Endian and Bus Access
MB91461
Table 8.4-2 Byte Access (1 / 2)
Bus width
Big endian mode
Little endian mode
Internal register External pin Control pin
address: "0"
D31
D31
AA
WR0X
Internal register External pin Control pin
address: "0"
D31
AA
D31
WR0X
D16
D16
AA
AA
D00
D00
(1)
(1)
Internal register External pin Control pin
address: "1"
D31
D31
BB
D16
Internal register External pin Control pin
address: "1"
D31
D31
BB
WR1X
D16
WR1X
BB
BB
D00
D00
(1)
(1)
16-bit bus width
Internal register External pin Control pin
address: "2"
D31
D31
CC
WR0X
Internal register External pin Control pin
address: "2"
D31
D31
CC
WR0X
D16
D16
CC
CC
D00
D00
(1)
(1)
Internal register External pin Control pin
address: "3"
D31
D31
Internal register External pin Control pin
address: "3"
D31
D31
DD
D16
DD
WR1X
D16
DD
DD
D00
D00
(1)
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WR1X
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8.4 Endian and Bus Access
MB91461
Table 8.4-2 Byte Access (2 / 2)
Bus width
Big endian mode
Little endian mode
Internal register External pin Control pin
address: "0"
D31
D31
AA
WR0X
D24
Internal register External pin Control pin
address: "0"
D31
D31
AA
WR0X
D24
AA
AA
D00
D00
(1)
(1)
Internal register External pin Control pin
address: "1"
D31
D31
BB
WR0X
D24
Internal register External pin Control pin
D31
address: "1"
D31
BB
D24
BB
WR0X
BB
D00
D00
(1)
(1)
8-bit bus width
Internal register External pin Control pin
address: "2"
D31
D31
CC
WR0X
D24
Internal register External pin Control pin
D31
CC
WR0X
CC
D00
D00
(1)
(1)
Internal register External pin Control pin
address: "3"
D31
D31
DD
WR0X
D24
Internal register External pin Control pin
address: "3"
D31
D31
DD
WR0X
D24
DD
DD
D00
D00
(1)
204
address: "2"
D31
CC
D24
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.5 Normal Bus Interface
MB91461
8.5
Normal Bus Interface
For normal bus interface, two clock cycles are the basic bus cycle for both read access
and write access.
■ Basic Timing (for Consecutive Accesses) (TYP[3:0]=0000B, AWR=0008H)
Figure 8.5-1 shows the basic timing for consecutive accesses.
Figure 8.5-1 Basic Timing for Consecutive Accesses
SYSCLK
A23 to A00
#2
#1
ASX
CS4X to CS0X
RDX
Read
D31 to D16
#1
#2
WR1X, WR0X
Write
D31 to D16
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8.5 Normal Bus Interface
MB91461
• ASX is asserted for one cycle in the bus access start cycle.
• A[23:00] output the address of the location of the start byte in word/halfword/byte access from the bus
access start cycle to the bus access end cycle.
• If W02 bit of the AWR0 to AWR4 registers is "0", CS0X to CS3X are asserted at the same timing as
ASX. For consecutive accesses, CS0X to CS4X are not negated. If W00 bit of the AWR register is "0",
CS0X to CS4X are negated after the bus cycle ends. If the W00 bit is "1", CS0X to CS4X are negated
after one cycle after bus access ends.
• RDX, WR0X and WR1X are asserted from the 2nd cycle of the bus access. Negation occurs after the
wait cycle of bits W15 to W12 of the AWR register is inserted. The timing of asserting RDX, WR0X
and WR1X can be delayed by one cycle by setting W01 bit of the AWR register to "1".
• For read access, D[31:16] are read when SYSCLK rises in the cycle in which the wait cycle ended after
RDX was asserted.
• For write access, data output to D[31:16] starts at the timing at which WR0X and WR1X are asserted.
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8.5 Normal Bus Interface
MB91461
■ Read → Write Timing (TYP[3:0]=0000B, AWR=0048H)
Figure 8.5-2 shows read → write timing.
Figure 8.5-2 Read → Write Timing
Read
Idle
Write
SYSCLK
A23 to A00
ASX
CS4X to CS0X
RDX
WR1X, WR0X
D31 to D16
• Setting of W06 bits of the AWR register enables an insertion of 0 or 1 idle cycle.
• Settings in the CS area on the read side are enabled.
• This idle cycle is inserted if the next access after a read access is a write access or an access to another
area.
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8.5 Normal Bus Interface
MB91461
■ Write → Write Timing (TYP[3:0]=0000B, AWR=0018H)
Figure 8.5-3 shows write → write timing.
Figure 8.5-3 Write → Write Timing
Write
Write
recovery
Write
SYSCLK
A23 to A00
ASX
CS4X to CS0X
WR1X, WR0X
D31 to D16
• Setting of W04 bits of the AWR register enables an insertion of 0 or 1 write recovery cycle.
• After all write cycles, recovery cycles are generated.
• Write recovery cycles are also generated if a write access is divided by a access with the bus width
wider than that specified.
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8.5 Normal Bus Interface
MB91461
■ Auto-wait Timing (TYP[3:0]=0000B, AWR=2008H)
Figure 8.5-4 shows the auto-wait timing.
Figure 8.5-4 Auto-Wait Timing
Basic cycle
Wait cycle
SYSCLK
A23 to A00
ASX
CS4X to CS0X
RDX
Read
D31 to D16
WR1X, WR0X
Write
D31 to D16
• Setting of W15 to W12 bits (first wait cycle) of the AWR register enables 0 to 15 auto-wait cycles to be
set.
• In the figure above, two auto-wait cycles are inserted, making a total of four cycles access. If auto-wait
is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the
minimum number of bus cycles may become longer depending on the internal state.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.5 Normal Bus Interface
MB91461
■ External Wait Timing (TYP[3:0]=0001B, AWR=2008H)
Figure 8.5-5 shows external wait timing.
Figure 8.5-5 External Wait Timing
Basic cycle
Auto-wait
2 cycles
Wait cycle
by RDY
SYSCLK
A23 to A00
ASX
CS4X to CS0X
RDX
Read
D31 to D16
WR1X, WR0X
Write
D31 to D16
RDY
Cancel
Wait
Setting "1" for TYP0 bit of the ACR register to enable the external RDY input pin enables an insertion of
the external wait cycle. In the figure above, because waiting using the auto-wait cycle is enabled, the
section of the RDY pin indicated by hatching is disabled. The value of the RDY input pin is evaluated after
the last cycle of the auto-wait cycle. Also, after a wait cycle is completed, the value of the RDY input pin is
disabled until the next access cycle starts.
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8.5 Normal Bus Interface
MB91461
■ CSX Delay Setting (TYP[3:0]=0000B, AWR=000CH)
Figure 8.5-6 shows the CSX delay setting.
Figure 8.5-6 CSX Delay Setting
SYSCLK
A23 to A00
ASX
CS4X to CS0X
RDX
Read
D31 to D16
WR1X, WR0X
Write
D31 to D16
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8.5 Normal Bus Interface
MB91461
■ CSX → RDX/WR1X,WR0X Setup and RDX/WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH)
Figure 8.5-7 shows CSX → RDX/WR1X,WR0X setup and RDX/WR1X,WR0X → CSX hold settings.
Figure 8.5-7 CSX → RDX/WR1X,WR0X Setup and RDX/WR1X,WR0X → CSX Hold Settings
SYSCLK
A23 to A00
ASX
CS4X to CS0X
CSX->RDX/WR1X,WR0X
RDX/WR1X,WR0X->CSX
Delay
Delay
RDX
Read
D31 to D16
WR1X, WR0X
Write
D31 to D16
• Setting "1" for W01 bit of the AWR register enables the CSX → RDX/WR1X,WR0X setup delay to be
set. Set this bit to extend the period after chip select assertion until read/write strobe.
• Setting "1" for W00 bit of the AWR register enables the RDX/WR1X,WR0X → CSX hold delay to be
set. Set this bit to extend the period after read/write strobe negation until chip select negation.
• The CSX → RDX/WR1X,WR0X setup delay (W01 bit) and RDX/WR1X,WR0X → CSX hold delay
(W00 bit) can be set independently.
• When making consecutive accesses within the same chip select area without negating the chip select,
neither a CSX → RDX/WR1X,WR0X setup delay nor an RDX/WR1X,WR0X → CSX hold delay is
inserted.
• If a setup cycle from determining the address or a hold cycle for determining the address is needed, set
"1" for the address → CSX delay setting (W02 bit of the AWR register).
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CHAPTER 8 EXTERNAL BUS INTERFACE
MB91461
8.6
Address/Data Multiplex Interface
8.6 Address/Data Multiplex Interface
This section explains setting of the address/data multiplex interface.
■ Without External Wait (TYP[3:0]=0100B, AWR=0008H)
Figure 8.6-1 shows the setting for the address/data multiplex interface with no external wait.
Figure 8.6-1 Setting for the Address/Data Multiplex Interface without External Wait
SYSCLK
Address[23:0]
A23 to A00
ASX
CS4X to CS0X
RDX
Read
D31 to D16
Address[15:0]
Data
[15:0]
WR1X, WR0X
Write
D31 to D16
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Address[15:0]
Data[15:0]
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8.6 Address/Data Multiplex Interface
MB91461
• Setting the ACR register to TYP[3:0]=01XXB enables the address/data multiplex interface to be set.
• If the address/data multiplex interface is set, set 8-bit or 16-bit for the data bus width (DBW[1:0] bit).
32-bit width is not supported.
• In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle
become the basic access cycle.
• In the address output cycles, ASX is asserted as a output address latch enable signal. However, when
CSX → RDX/WR1X,WR0X setup delay (AWR:W01) is set to "0", the multiplex address output cycle
becomes one cycle only as shown in the figure above and the address cannot be directly latched at the
rising edge of ASX. Therefore, fetch the address at the rising edge of SYSCLK of the cycle in which
"L" is asserted to ASX. If you want to set the address to be directly latched at the rising edge of ASX,
see "■ Setting of CSX → RDX/WR1X,WR0X Setup (TYP[3:0]=0101B, AWR=100BH)".
• As with a normal interface, the address indicating the start of access is outputted to A[23:00] during the
time division bus cycle. Use this setting if you want to use an address of 8/16 bits or more in the
address/data multiplex interface.
• As with the normal interface, auto-wait (AWR:W14 to AWR:W12), read → write idle cycle
(AWR:W06), write recovery (AWR:W04), address → CSX delay (AWR:W02), CSX → RDX/
WR1X,WR0X setup delay (AWR:W01), and RDX/WR1X,WR0X → CSX hold delay (AWR:W00) can
be set.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.6 Address/Data Multiplex Interface
MB91461
■ With External Wait (TYP[3:0]=0101B, AWR=1008H)
Figure 8.6-2 shows the setting for the address/data multiplex interface with external wait.
Figure 8.6-2 Setting for the Address/Data Multiplex Interface with External Wait
SYSCLK
Address[23:0]
A23 to A00
ASX
CS4X to CS0X
RDX
Read
D31 to D16
Data
[15:0]
Address[15:0]
WR1X, WR0X
Write
D31 to D16
Address[15:0]
Data[15:0]
RDY
Setting the ACR register to TYP[3:0]=01X1B enables RDY input in the address/data multiplex interface.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.6 Address/Data Multiplex Interface
MB91461
■ Setting of CSX → RDX/WR1X,WR0X Setup (TYP[3:0]=0101B, AWR=100BH)
Figure 8.6-3 shows setting of CSX → RDX/WR1X,WR0X setup.
Figure 8.6-3 Setting of CSX → RDX/WR1X,WR0X Setup
SYSCLK
A23 to A00
Address[23:0]
ASX
CS4X to CS0X
RDX
Read
D31 to D16
Address[15:0]
Data
[15:0]
Address[15:0]
Data[15:0]
WR1X, WR0X
Write
D31 to D16
Setting "1" for the CSX → RDX/WR1X,WR0X setup delay (AWR:W01) enables the multiplex address
output cycle to be extended by one cycle as shown in the above figure, allowing the address to be latched
directly at the rising edge of ASX. Use this setting if you want to use ASX as an ALE (Address Latch
Enable) strobe without using SYSCLK.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.7 DMA Access
MB91461
8.7
DMA Access
This section explains setting of DMA access.
■ 2-cycle Transfer (The Timing is the Same as for Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.) (TYP[3:0]=0000B, AWR=0008H)
Figure 8.7-1 shows the setting of 2-cycle transfer.
* When a wait is not set on the I/O side.
Figure 8.7-1 Setting of 2-Cycle Transfer
SYSCLK
A23 to A00
I/O address
ASX
CS4X to CS0X
(I/O side)
WR1X, WR0X
D31 to D16
Bus access is the same as that of the interface for non-DMA transfer.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.7 DMA Access
MB91461
■ 2-cycle Transfer (External → I/O) (TYP[3:0]=0000B, AWR=0008H)
Figure 8.7-2 shows the setting of 2-cycle transfer (external → I/O).
* When a wait is not set on the memory and I/O.
Figure 8.7-2 Setting of 2-Cycle Transfer (External → I/O)
MCLK
A23 to A00
Memory address
Idle
I/O address
ASX
CS4X to CS0X
RDX
CS4X to CS0X
WR1X, WR0X
D31 to D16
Bus access is the same as that of the interface for non-DMAC transfer.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.7 DMA Access
MB91461
■ 2-cycle Transfer (I/O → External) (TYP[3:0]=0000B, AWR=0008H)
Figure 8.7-3 shows the setting of 2-cycle transfer (I/O → external).
* When a wait is not set on the memory and I/O.
Figure 8.7-3 Setting of 2-Cycle Transfer (I/O → External)
MCLK
A23 to A00
I/O address
Idle
Memory address
ASX
CS4X to CS0X
WR1X, WR0X
CS4X to CS0X
RDX
D31 to D16
Bus access is the same as that of the interface for non-DMAC transfer.
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CHAPTER 8 EXTERNAL BUS INTERFACE
8.8 Procedure for Setting Registers
8.8
MB91461
Procedure for Setting Registers
For setting procedure concerning with external bus interface, follow the principle
described below.
■ Procedure for Setting External Bus Interface
1) Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding
area is not used ("0"). If you change the settings while "1" is set, access before and after the change
cannot be guaranteed.
2) Use the following procedure to change a register:
(1) Set "0" for the CSER bit corresponding to the applicable area.
(2) Set both ASR and ACR at the same time using word access.
To access to ASR and ACR using half word access, set ACR after setting ASR.
(3) Set AWR.
(4) Set the CSER bit corresponding to the applicable area.
3) The CS0X area is enabled after a reset is released. If the area is used as a program area, the register
contents need to be rewritten while the CSER bit is "1". In this case, make the settings described in
2) and 3) above in the initial state with a low-speed internal clock. Then, switch the clock to a highspeed clock.
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CHAPTER 9
I/O PORT
This chapter describes I/O ports and the configuration
and functions of the registers.
9.1 Overview of I/O Ports
9.2 I/O Port Data Register
9.3 Setting of Port Function Register
9.4 Selection of Pin Input Level
9.5 Pull-up and Pull-down Control Register
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CHAPTER 9 I/O PORT
9.1 Overview of I/O Ports
9.1
MB91461
Overview of I/O Ports
This section provides an overview of the I/O ports.
■ Basic Block Diagram of the I/O Port
MB91461 can be used as an I/O port if settings are made so that the external bus interfaces or peripherals
corresponding to pins do not use the pins as input/output pins.
Figure 9.1-1 shows the basic configuration of the I/O port.
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9.1 Overview of I/O Ports
MB91461
Figure 9.1-1 Basic Block Diagram of the I/O Port
Port bus
PILR
EPILR
External bus interface input
Peripheral input
CMOS
PDRD read
&
Automotive
&
PDRD
0
CLKP
CMOS
hysteresis
1
&
STOP or
GPORTEN
PDR read
PPER
P-ch
Pull-up /
down
control
PPCR
Output driver
1. Peripheral output
2. Peripheral output
Pin
Output
MUX
PDR
N-ch
DDR
port
direction
control
PFR
EPFR
PODR
PDR:
PDRD:
DDR:
PFR:
EPFR:
PILR:
EPILR:
PPER:
PPCR:
CM71-10159-2E
Port data register
Port data direct read register
Data direction register
Port function register
Extra PFR port function register
Port input level selection register
Port input level selection register
Port pull-up/-down enable register
Port pull-up/-down control register
Address 000H + PDR + #port (Port 00: 000H, port 01: 001H, etc.)
Address = PDR + D00H
Address = PDR + D40H
Address = PDR + D80H
Address = PDR + DC0H
Address = PDR + E40H
Address = PDR + E80H
Address = PDR + EC0H
Address = PDR + F00H
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CHAPTER 9 I/O PORT
9.1 Overview of I/O Ports
MB91461
■ General Specification of Ports
The following rules apply to all ports.
• As for the port input, to prevent the penetration current being generated before the setting of the port
with software, all initial values are set. Set each port pin based on its function.
• For each port, the port data direct read register (PDRD) that samples pin data with CLKP is provided.
This register is read only.
• For each port, the data direction register (DDR) that switches port input/output direction is provided. All
the ports become input (DDR=00H) after reset.
- Port input mode (PFR = 0 and DDR = 0)
PDRD read: Sampled pin data is read.
PDR read: Sampled pin data is read.
PDR write: PDR setting value is written. No effect on the pin value.
- Port output mode (PFR = 0 and DDR = 1)
PDRD read: Sampled pin data is read.
PDR read: PDR register value is read.
PDR write: PDR setting value is written to the corresponding external pin.
• When a read-modify-write (RMW) instruction (bit operation) is executed, the PDR register always
becomes read regardless of the data direction register (DDR).
• The port function register (PFR) and the extra port function register (EPFR) is provided in a specified
port. To enable the function determined by EPFR=1, PFR=1 also must be set. On MB90V460, the
operation with EPFR=1 and PFR=0 settings is the same as the one in the port input/output mode
(reserved for future use).
• For each port, the port input level register (PILR) that inputs the input level (CMOS hysteresis/
Automotive [/TTL]) bitwise is provided. The initial value differs for each port function.
The input level can be set in any device mode. See "Table 9.4-2 Pin Input Level Selection Register
Setting".
• A pull-up resistor and a pull-down resistor (50 kΩ) that are enabled by its own pull-up/pull-down enable
register (PPER) and pull-up/pull-down control register (PPCR) bitwise are provided in a specified port.
See "9.5 Pull-up and Pull-down Control Register".
• For each port, one or two port function registers PFRs and (if needed) one extra PFR (EPFR) are
provided. By combining together, they operate as up to 3 resource I/Os per pin. See "9.3 Setting of Port
Function Register".
• The port setting that is controlled by MD[2:0] pin and by the mode register MODR overwrites the
setting in the port register. For example, the external bus mode overwrites the port register setting.
External bus signal output can be disabled by setting the PFR of a pin to the port mode (PFR=0).
• A resource input line is normally connected to a pin and is enabled by setting the appropriate function in
the resource. There are some exceptions as shown in "9.3 Setting of Port Function Register".
• An external interrupt input line is always connected to a pin and is enabled at the external interrupt unit.
• In the STOP mode (with STCR:STOP setting and with no STCR:HIZ setting), all pins maintain its own
state (input or output based on the setting before becoming STOP mode) and the input stages and lines
are fixed internally to avoid crossing current. If the corresponding pin is set by using PFR = 1 setting
and the corresponding external interrupt is enabled in the ENIR0 and ENIR1 registers, an external
interrupt input pin is not fixed. Pull-up and pull-down are enabled.
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CHAPTER 9 I/O PORT
9.1 Overview of I/O Ports
MB91461
• In the STOP-HIZ mode (with STCR:STOP and STCR:HIZ settings), all pins are switched to input (high
impedance state) and all the input stages and lines are fixed internally to avoid fluctuations. If the
corresponding pin is set by using PFR = 1 setting and the corresponding external interrupt is enabled in
the ENIR0 and ENIR1 registers, an external interrupt pin is not fixed. Pull-up and pull-down are
disabled.
• Resource output lines are enabled by setting the corresponding PFR/EPFR bits in the port. For details,
see "9.3 Setting of Port Function Register". In addition, the LIN-UART output (SOT) must be enabled
by setting the SOE bit in LIN-UART control.
• Resource bidirectional signals (SCK of LIN-UART, etc.) are enabled by setting the corresponding PFR/
EPFR bits in the port. Signal direction is controlled by the resource settings such as the output enable
bit. For details, see "9.3 Setting of Port Function Register".
Notes:
There is no register switched between general-purpose port input and peripheral input. The value
input via an external pin is always passed to the general-purpose port and peripheral circuit.
Even with the DDR output setting, the value output to the outside is always propagated to the
general-purpose port and peripheral circuit.
For use as a peripheral input, use DDR input and enable each peripheral’s input signal.
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CHAPTER 9 I/O PORT
9.2 I/O Port Data Register
9.2
MB91461
I/O Port Data Register
This section shows the port data register (PDR), data direction register (DDR) and port
data direct read register (PDRD).
■ Port Data Register (PDR)
This register stores output data of each port.
Figure 9.2-1 The Configuration of Port Data Register (PDR)
PDR14
PDR15
PDR16
PDR17
PDR18
PDR19
PDR20
PDR21
PDR22
PDR23
PDR24
PDR28
PDR29
Address
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
00001CH
00001DH
bit7
6
5
4
−
−
−
−
PDR14_3 PDR14_2 PDR14_1 PDR14_0
3
−
−
−
−
PDR15_3 PDR15_2 PDR15_1 PDR15_0
PDR16_7
−
−
−
−
2
−
1
−
0
−
PDR17_7 PDR17_6 PDR17_5 PDR17_4 PDR17_3 PDR17_2 PDR17_1 PDR17_0
−
−
PDR18_2 PDR18_1 PDR18_0
−
PDR19_6 PDR19_5 PDR19_4
−
−
−
−
PDR19_2 PDR19_1 PDR19_0
−
PDR20_6 PDR20_5 PDR20_4
−
PDR20_2 PDR20_1 PDR20_0
−
PDR21_6 PDR21_5 PDR21_4
−
PDR21_2 PDR21_1 PDR21_0
PDR22_7 PDR22_6 PDR22_5 PDR22_4 PDR22_3 PDR22_2
−
PDR23_6
−
−
PDR22_0
PDR23_4 PDR23_3 PDR23_2 PDR23_1 PDR23_0
PDR24_7 PDR24_6 PDR24_5 PDR24_4 PDR24_3 PDR24_2 PDR24_1 PDR24_0
−
−
−
PDR28_4 PDR28_3 PDR28_2 PDR28_1 PDR28_0
PDR29_7 PDR29_6 PDR29_5 PDR29_4 PDR29_3 PDR29_2 PDR29_1 PDR29_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
----XXXXB
----XXXXB
X-------B
XXXXXXXXB
-----XXXB
-XXX-XXXB
-XXX-XXXB
-XXX-XXXB
XXXXXX-XB
-X-XXXXXB
XXXXXXXXB
---XXXXXB
XXXXXXXXB
R/W
■ Data Direction Register (DDR)
This register sets I/O direction of each port. All ports become input mode after a reset.
Figure 9.2-2 The Configuration of Data Direction Register (DDR)
DDR14
DDR15
DDR16
DDR17
DDR18
DDR19
DDR20
DDR21
DDR22
DDR23
DDR24
DDR28
DDR29
Address
000D4EH
000D4FH
000D50H
000D51H
000D52H
000D53H
000D54H
000D55H
000D56H
000D57H
000D58H
000D5CH
000D5DH
bit7
6
5
4
-
-
-
-
DDR14_3 DDR14_2 DDR14_1 DDR14_0
-
-
-
-
DDR15_3 DDR15_2 DDR15_1 DDR15_0
DDR16_7
-
-
-
-
2
-
1
-
0
-
DDR17_7 DDR17_6 DDR17_5 DDR17_4 DDR17_3 DDR17_2 DDR17_1 DDR17_0
-
-
DDR18_2 DDR18_1 DDR18_0
-
DDR19_6 DDR19_5 DDR19_4
-
DDR19_2 DDR19_1 DDR19_0
-
DDR20_6 DDR20_5 DDR20_4
-
DDR20_2 DDR20_1 DDR20_0
-
DDR21_6 DDR21_5 DDR21_4
-
DDR21_2 DDR21_1 DDR21_0
-
-
-
DDR22_7 DDR22_6 DDR22_5 DDR22_4 DDR22_3 DDR22_2
-
DDR23_6
-
-
DDR22_0
DDR23_4 DDR23_3 DDR23_2 DDR23_1 DDR23_0
DDR24_7 DDR24_6 DDR24_5 DDR24_4 DDR24_3 DDR24_2 DDR24_1 DDR24_0
-
-
-
DDR28_4 DDR28_3 DDR28_2 DDR28_1 DDR28_0
DDR29_7 DDR29_6 DDR29_5 DDR29_4 DDR29_3 DDR29_2 DDR29_1 DDR29_0
R/W
226
3
R/W
R/W
R/W
R/W
R/W
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R/W
Initial value
----0000B
----0000B
0-------B
00000000B
-----000B
-000-000B
-000-000B
-000-000B
000000-0B
-0-00000B
00000000B
---00000B
00000000B
R/W
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CHAPTER 9 I/O PORT
9.2 I/O Port Data Register
MB91461
■ Port Data Direct Read Register (PDRD)
This register is a read-only register and is used to read the input value directly even if the port is in an
output state.
Figure 9.2-3 The Configuration of Input Port Direct Read Register (PDRD)
PDRD14
PDRD15
PDRD16
PDRD17
PDRD18
PDRD19
PDRD20
PDRD21
PDRD22
PDRD23
PDRD24
PDRD28
PDRD29
Address
000D0EH
000D0FH
000D10H
000D11H
000D12H
000D13H
000D14H
000D15H
000D16H
000D17H
000D18H
000D1CH
000D1DH
bit7
6
5
4
-
-
-
-
PDRD14_3 PDRD14_2 PDRD14_1 PDRD14_0
-
-
-
-
PDRD15_3 PDRD15_2 PDRD15_1 PDRD15_0
PDRD16_7
-
-
-
-
2
-
1
-
0
-
PDRD17_7 PDRD17_6 PDRD17_5 PDRD17_4 PDRD17_3 PDRD17_2 PDRD17_1 PDRD17_0
-
-
PDRD18_2 PDRD18_1 PDRD18_0
-
PDRD19_6 PDRD19_5 PDRD19_4
-
PDRD19_2 PDRD19_1 PDRD19_0
-
PDRD20_6 PDRD20_5 PDRD20_4
-
PDRD20_2 PDRD20_1 PDRD20_0
-
-
-
-
PDRD21_6 PDRD21_5 PDRD21_4
-
PDRD21_2 PDRD21_1 PDRD21_0
PDRD22_7 PDRD22_6 PDRD22_5 PDRD22_4 PDRD22_3 PDRD22_2
-
PDRD23_6
-
-
PDRD22_0
PDRD23_4 PDRD23_3 PDRD23_2 PDRD23_1 PDRD23_0
PDRD24_7 PDRD24_6 PDRD24_5 PDRD24_4 PDRD24_3 PDRD24_2 PDRD24_1 PDRD24_0
-
-
-
PDRD28_4 PDRD28_3 PDRD28_2 PDRD28_1 PDRD28_0
PDRD29_7 PDRD29_6 PDRD29_5 PDRD29_4 PDRD29_3 PDRD29_2 PDRD29_1 PDRD29_0
R
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3
R
R
R
R
R
FUJITSU MICROELECTRONICS LIMITED
R
Initial value
----XXXXB
----XXXXB
X-------B
XXXXXXXXB
-----XXXB
-XXX-XXXB
-XXX-XXXB
-XXX-XXXB
XXXXXX-XB
-X-XXXXXB
XXXXXXXXB
---XXXXXB
XXXXXXXXB
R
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
9.3
MB91461
Setting of Port Function Register
This section explains the function of port function register.
■ Port 14
Port 14 is controlled by PFR14 and EPFR14.
When the corresponding bit of PFR14 is "0", the pin is used as a general-purpose port, and when it is "1",
the external pin becomes a peripheral input. Input selection to ICU (Input Capture Unit) is made by a
combination of PFR and EPFR.
Figure 9.3-1 Configuration of Control Register (Port 14)
Address
PFR14 000D8EH
EPFR14 000DCEH
228
bit7
6
5
4
−
−
−
−
PFR14_3 PFR14_2 PFR14_1 PFR14_0 ----0000B
3
−
−
−
−
EPFR14_3 EPFR14_2 EPFR14_1 EPFR14_0
−
−
−
−
R/W
2
R/W
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1
R/W
0
Initial value
----0000B
R/W
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
Table 9.3-1 Function of Control Register (Port 14)
Bit name
Value
00B
01B
PFR14_3/EPFR14_3
10B
11B
Input is made from the external pin to the following two:
• External trigger input of reload timer 3
• External trigger input of PPG3
LSYN output of LIN-UART3 is connected to internal ICU3 input.
00B
External pin is used as a general-purpose port (P14_2). *
LSYN output of LIN-UART2 is connected to ICU2 input.
10B
Input is made from the external pin to the following three:
• ICU2 input
• External trigger input of reload timer 2
• External trigger input of PPG2
11B
Input is made from the external pin to the following two:
• External trigger input of reload timer 2
• External trigger input of PPG2
LSYN output of LIN-UART2 is connected to ICU2 input.
00B
External pin is used as a general-purpose port (P14_1). *
LSYN output of LIN-UART1 is connected to ICU1 input.
01B
PFR14_1/EPFR14_1
10B
Input is made from the external pin to the following three:
• ICU1 input
• External trigger input of reload timer 1
• External trigger input of PPG1
11B
Input is made from the external pin to the following two:
• External trigger input of reload timer 1
• External trigger input of PPG1
LSYN output of LIN-UART1 is connected to ICU1 input.
00B
External pin is used as a general-purpose port (P14_0).
LSYN output of LIN-UART0 is connected to ICU0 input.
01B
PFR14_0/EPFR14_0
External pin is used as a general-purpose port (P14_3). *
LSYN output of LIN-UART3 is connected to ICU3 input. Measured LSYN pulse
width in LIN communication can be used to detect the baud rate in LIN slave
operation.
Input is made from the external pin to the following three:
• ICU3 input
• External trigger input of reload timer 3
• External trigger input of PPG3
01B
PFR14_2/EPFR14_2
Function
10B
Input is made from the external pin to the following three:
• ICU0 input
• External trigger input of reload timer 0
• External trigger input of PPG0
11B
Input is made from the external pin to the following two:
• External trigger input of reload timer 0
• External trigger input of PPG0
LSYN output of LIN-UART0 is connected to ICU0 input.
*: Even if a port is selected, reload timer trigger input and PPG trigger input are enabled.
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 15
Port 15 is controlled by PFR15 and EPFR15.
When the PFR is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an
output pin for peripheral macro (OCU or reload timer).
Figure 9.3-2 Configuration of Control Register (Port 15)
Address
PFR15 000D8FH
EPFR15 000DCFH
bit7
6
5
4
−
−
−
−
PFR15_3 PFR15_2 PFR15_1 PFR15_0 ----0000B
3
−
−
−
−
EPFR15_3 EPFR15_2 EPFR15_1 EPFR15_0
−
−
−
−
R/W
2
R/W
1
R/W
0
Initial value
----0000B
R/W
Table 9.3-2 Function of Control Register (Port 15)
Bit name
PFR15_3/EPFR15_3
PFR15_2/EPFR15_2
PFR15_1/EPFR15_1
PFR15_0/EPFR15_0
230
Value
Function
0XB
P15_3: External pin is used as a general-purpose port (P15_3).
10B
OCU3: External pin is used as OCU3 output.
11B
TOT3: External pin is used as reload timer 3 output.
0XB
P15_2: External pin is used as a general-purpose port (P15_2).
10B
OCU2: External pin is used as OCU2 output.
11B
TOT2: External pin is used as reload timer 2 output.
0XB
P15_1: External pin is used as a general-purpose port (P15_1).
10B
OCU1: External pin is used as OCU1 output.
11B
TOT1: External pin is used as reload timer 1 output.
0XB
P15_0: External pin is used as a general-purpose port (P15_0).
10B
OCU0: External pin is used as OCU0 output.
11B
TOT0: External pin is used as reload timer 0 output.
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 16
Port 16 is controlled by PFR16 and EPFR16.
Figure 9.3-3 Configuration of Control Register (Port 16)
Address
PFR16 000D90H
EPFR16 000DD0H
bit7
6
5
4
PFR16_7
−
−
−
EPFR16_7
−
−
−
R/W
−
−
−
3
2
1
0
−
−
−
−
Initial value
0-------B
0-------B
Table 9.3-3 Function of Control Register (Port 16)
Bit name
Value
PFR16_7/EPFR16_7
Function
0XB
P16_7: External pin is used as a general-purpose port (P16_7).
10B
Setting is disabled.
1XB
ATGX: External pin is used as ATGX input. *
*: When using a peripheral as an input, the input is enabled even a general-purpose port is selected.
■ Port 17
Port 17 is controlled by PFR17.
Figure 9.3-4 Configuration of Control Register (Port 17)
PFR17
Address
bit7
6
5
4
3
2
1
0
Initial value
000D91H PFR17_7 PFR17_6 PFR17_5 PFR17_4 PFR17_3 PFR17_2 PFR17_1 PFR17_0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 9.3-4 Function of Control Register (Port 17)
Bit name
PFR17_7
PFR17_6
PFR17_5
PFR17_4
PFR17_3
PFR17_2
PFR17_1
PFR17_0
CM71-10159-2E
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
P17_7: External pin is used as a general-purpose port (P17_7).
PPG7: Used as PPG output (PPG7).
P17_6: External pin is used as a general-purpose port (P17_6).
PPG6: Used as PPG output (PPG6).
P17_5: External pin is used as a general-purpose port (P17_5).
PPG5: Used as PPG output (PPG5).
P17_4: External pin is used as a general-purpose port (P17_4).
PPG4: Used as PPG output (PPG4).
P17_3: External pin is used as a general-purpose port (P17_3).
PPG3: Used as PPG output (PPG3).
P17_2: External pin is used as a general-purpose port (P17_2).
PPG2: Used as PPG output (PPG2).
P17_1: External pin is used as a general-purpose port (P17_1).
PPG1: Used as PPG output (PPG1).
P17_0: External pin is used as a general-purpose port (P17_0).
PPG0: Used as PPG output (PPG0).
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 18
Port 18 is controlled by PFR18.
Figure 9.3-5 Configuration of Control Register (Port 18)
Address
PFR18 000D92H
EPFR18 000DD2H
bit7
6
5
4
3
−
−
−
−
−
PFR18_2 PFR18_1 PFR18_0
2
1
0
−
−
−
−
−
EPFR18_2
-
-
−
−
−
−
−
R/W
R/W
R/W
Initial value
-----000B
-----0--B
Table 9.3-5 Function of Control Register (Port 18)
Bit name
PFR18_2/EPFR18_2
PFR18_1
PFR18_0
Value
Function
0XB
P18_2: External pin is used as a general-purpose port (P18_2).
10B
SCK6: Used as SCK of LIN-UART6.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *
11B
Setting is disabled.
0B
P18_1: External pin is used as a general-purpose port (P18_1).
1B
SOT6: Used as SOT of LIN-UART6.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
0B
P18_0: External pin is used as a general-purpose port (P18_0).
1B
SIN6: Used as SIN of LIN-UART6. *
*: When using a peripheral as an input, the input is enabled even a general-purpose port is selected.
232
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 19
Port 19 is controlled by PFR19.
Figure 9.3-6 Configuration of Control Register (Port 19)
Address
PFR19 000D93H
EPFR19 000DD3H
bit7
6
5
4
3
2
1
0
−
PFR19_6 PFR19_5 PFR19_4
−
PFR19_2 PFR19_1 PFR19_0
−
EPFR19_6
-
-
−
EPFR19_2
-
-
R/W
−
R/W
R/W
R/W
−
R/W
R/W
Initial value
-000-000B
-0---0---B
Table 9.3-6 Function of Control Register (Port 19)
Bit name
PFR19_6/EPFR19_6
PFR19_5
PFR19_4
PFR19_2/EPFR19_2
PFR19_1
PFR19_0
Value
Function
0XB
P19_6: External pin is used as a general-purpose port (P19_6).
10B
SCK5: Used as SCK of LIN-UART5.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *
11B
Setting is disabled.
0B
P19_5: External pin is used as a general-purpose port (P19_5).
1B
SOT5: Used as SOT of LIN-UART5.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
0B
P19_4: External pin is used as a general-purpose port (P19_4).
1B
SIN5: Used as SIN of LIN-UART5.
0XB
P19_2: External pin is used as a general-purpose port (P19_2).
10B
SCK4: Used as SCK of LIN-UART4.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *
11B
Setting is disabled.
0B
P19_1: External pin is used as a general-purpose port (P19_1).
1B
SOT4: Used as SOT of LIN-UART4.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
0B
P19_0: External pin is used as a general-purpose port (P19_0).
1B
SIN4: Used as SIN of LIN-UART4. *
*: When using a peripheral as an input, the input is enabled even a general-purpose port is selected.
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 20
Port 20 is controlled by PFR20 and EPFR20.
Figure 9.3-7 Configuration of Control Register (Port 20)
Address
PFR20 000D94H
EPFR20 000DD4H
bit7
6
5
4
3
2
1
0
−
PFR20_6 PFR20_5 PFR20_4
−
PFR20_2 PFR20_1 PFR20_0
−
EPFR20_6 EPFR20_5 EPFR20_4
−
EPFR20_2 EPFR20_1 EPFR20_0
−
R/W
R/W
R/W
−
R/W
R/W
Initial value
-000-000B
-000-000B
R/W
Table 9.3-7 Function of Control Register (Port 20)
Bit name
PFR20_6/EPFR20_6
PFR20_5/EPFR20_5
PFR20_4/EPFR20_4
PFR20_2/EPFR20_2
PFR20_1/EPFR20_1
PFR20_0/EPFR20_0
Value
Function
0XB
P20_6: External pin is used as a general-purpose port.
10B
SCK3: Used as SCK of LIN-UART3.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *1
11B
FRCK3: Used as CK of free-run timer 3. *2
0XB
P20_5: External pin is used as a general-purpose port.
10B
SOT3: Used as SOT of LIN-UART3.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
11B
Setting is disabled.
0XB
P20_4: External pin is used as a general-purpose port.
10B
SIN3: Used as SIN of LIN-UART3. *1
11B
Setting is disabled.
0XB
P20_2: External pin is used as a general-purpose port.
10B
SCK2: Used as SCK of LIN-UART2.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *1
11B
FRCK3: Used as CK of free-run timer3. *2
0XB
P20_1: External pin is used as a general-purpose port.
10B
SOT2: Used as SOT of LIN-UART2.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
11B
Setting is disabled.
0XB
P20_0: External pin is used as a general-purpose port.
10B
SIN2: Used as SIN of LIN-UART2. *1
11B
Setting is disabled.
*1: When using a peripheral as an input, the input is enabled even a general-purpose port is selected.
*2: Input clock of free-run timer (FRCKx) is always inputted regardless of PFR and EPFR settings.
234
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 21
Port 21 is controlled by PFR21 and EPFR21.
Figure 9.3-8 Configuration of Control Register (Port 21)
Address
PFR21 000D95H
EPFR21 000DD5H
bit7
6
5
4
3
2
1
0
−
PFR21_6 PFR21_5 PFR21_4
−
PFR21_2 PFR21_1 PFR21_0
−
EPFR21_6 EPFR21_5 EPFR21_4
−
EPFR21_2 EPFR21_1 EPFR21_0
−
R/W
R/W
R/W
−
R/W
R/W
Initial value
-000-000B
-000-000B
R/W
Table 9.3-8 Function of Control Register (Port 21)
Bit name
PFR21_6/EPFR21_6
PFR21_5/EPFR21_5
PFR21_4/EPFR21_4
PFR21_2/EPFR21_2
PFR21_1/EPFR21_1
PFR21_0/EPFR21_0
Value
Function
0XB
P21_6: External pin is used as a general-purpose port.
10B
SCK1: Used as SCK of LIN-UART1.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *1
11B
FRCK1: Used as CK of free-run timer 1. *2
0XB
P21_5: External pin is used as a general-purpose port.
10B
SOT1: Used as SOT of LIN-UART1.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
11B
Setting is disabled.
0XB
P21_4: External pin is used as a general-purpose port.
10B
SIN1: Used as SIN of LIN-UART1. *1
11B
Setting is disabled.
0XB
P21_2: External pin is used as a general-purpose port.
10B
SCK0: Used as SCK of LIN-UART0.
When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial
mode register. *1
11B
FRCK0: Used as CK of free-run timer 0. *2
0XB
P21_1: External pin is used as a general-purpose port.
10B
SOT0: Used as SOT of LIN-UART0.
When using as SOT output, set SOE bit of LIN-UART serial mode register
to "1".
11B
Setting is disabled.
0XB
P21_0: External pin is used as a general-purpose port.
10B
SIN0: Used as SIN of LIN-UART0. *1
11B
Setting is disabled.
*1: When using a peripheral as an input, the input is enabled even a general-purpose port is selected.
*2: Input clock of free-run timer (FRCKx) is always inputted regardless of PFR and EPFR settings.
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 22
Port 22 is controlled by PFR22.
In normal operation, interrupt inputs (INT15, INT14, INT13, and INT12) are inputted regardless of PFR
setting. In STOP mode, the input to internal INT input is as follows:
• When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal.
• When PFR=1: The value of the external pin is inputted to internal INT input.
Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP
mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by
external interrupt registers or setting PFR to "1" and processing by the external pins are needed.
Figure 9.3-9 Configuration of Control Register (Port 22)
PFR22
Address
bit7
6
5
4
3
2
000D96H PFR22_7 PFR22_6 PFR22_5 PFR22_4 PFR22_3 PFR22_2
R/W
R/W
R/W
R/W
R/W
R/W
1
−
−
0
Initial value
PFR22_0 000000-0B
R/W
Table 9.3-9 Function of Control Register (Port 22)
Bit name
PFR22_7
Value
0
P22_7: External pin is used as a general-purpose port.
1
SCL1: Used as SCL I/O of I2C_1.
0
P22_6: External pin is used as a general-purpose port.
INT15: Input to INT15.
1
SDA1: Used as SDA I/O of I2C_1.
INT15: Input to INT15.
Set "1" when using INT15 for canceling STOP mode.
0
P22_5: External pin is used as a general-purpose port.
1
SCL0: Used as SCL I/O of I2C_0.
0
P22_4: External pin is used as a general-purpose port.
INT14: Input to INT14.
1
SDA0: Used as SDA I/O of I2C_0.
INT14: Input to INT14.
Set "1" when using INT14 for canceling STOP mode.
0
P22_3: External pin is used as a general-purpose port.
1
Setting is disabled.
0
P22_2: External pin is used as a general-purpose port.
INT13: Input to INT13.
1
IINT13: Input to INT13.
Set "1" when using INT13 for canceling STOP mode.
0
P22_0: External pin is used as a general-purpose port.
INT12: Input to INT12.
1
INT12: Input to INT12.
Set "1" when using INT12 for canceling STOP mode.
PFR22_6
PFR22_5
PFR22_4
PFR22_3
PFR22_2
PFR22_0
236
Function
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 23
Port 23 is controlled by PFR23.
In normal operation, interrupt inputs (INT11, INT10, INT9, and INT8) are inputted regardless of PFR
setting. In STOP mode, the input to internal INT input is as follows:
• When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal.
• When PFR=1: The value of the external pin is inputted to internal INT input.
Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP
mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by
external interrupt registers or setting PFR to "1" and processing by the external pins are needed.
Figure 9.3-10 Configuration of Control Register (Port 23)
PFR23
Address
000D97H
bit7
6
5
−
PFR23_6
−
−
R/W
−
4
3
2
1
0
Initial value
PFR23_4 PFR23_3 PFR23_2 PFR23_1 PFR23_0 -0-00000B
R/W
R/W
R/W
R/W
R/W
Table 9.3-10 Function of Control Register (Port 23)
Bit name
Value
0
P23_6: External pin is used as a general-purpose port.
INT11: Input to INT11.
1
INT11: Input to INT11.
Set "1" when using INT11 for canceling STOP mode.
0
P23_4: External pin is used as a general-purpose port.
INT10: Input to INT10.
1
INT10: Input to INT10.
Set "1" when using INT10 for canceling STOP mode.
0
P23_3: External pin is used as a general-purpose port.
1
TX1: Used as TX of CAN1.
0
P23_2: External pin is used as a general-purpose port.
RX1: Input to RX of CAN1.
INT9: Input to INT9.
1
RX1: Input to RX of CAN1.
INT9: Input to INT9.
Set "1" when using INT9 for canceling STOP mode.
0
P23_1: External pin is used as a general-purpose port.
1
TX0: Used as TX of CAN0.
0
P23_0: External pin is used as a general-purpose port.
RX0: Input to RX of CAN0.
INT8: Input to INT8.
1
X0: Input to RX of CAN0.
INT8: Input to INT8.
Set "1" when using INT8 for canceling STOP mode.
PFR23_6
PFR23_4
PFR23_3
PFR23_2
PFR23_1
PFR23_0
CM71-10159-2E
Function
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 24
Port 24 is controlled by PFR24.
In normal operation, interrupt inputs (INT7, INT6, INT5, INT4, INT3, INT2, INT1 and INT0) are inputted
regardless of PFR setting. In STOP mode, the input to internal INT input is as follows:
• When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal.
• When PFR=1: The value of the external pin is inputted to internal INT input.
Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP
mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by
external interrupt registers or setting PFR to "1" and processing by the external pins are needed.
Figure 9.3-11 Configuration of Control Register (Port 24)
PFR24
238
Address
bit7
6
5
4
3
2
1
0
Initial value
000D98H PFR24_7 PFR24_6 PFR24_5 PFR24_4 PFR24_3 PFR24_2 PFR24_1 PFR24_0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
Table 9.3-11 Function of Control Register (Port 24)
Bit name
Value
0
P24_7: External pin is used as a general-purpose port.
INT7: Input to INT7.
1
INT7: Input to INT7.
Set "1" when using INT7 for canceling STOP mode.
0
P24_6: External pin is used as a general-purpose port.
INT6: Input to INT6.
1
INT6: Input to INT6.
Set "1" when using INT6 for canceling STOP mode.
0
P24_5: External pin is used as a general-purpose port.
INT5: Input to INT5.
1
SCL2: Used as SCL of I2C_2.
INT5: Input to INT5.
Set "1" when using INT5 for canceling STOP mode.
0
P24_4: External pin is used as a general-purpose port.
INT4: Input to INT4.
1
SDA2: Used as SDA of I2C_2.
INT4: Input to INT4.
Set "1" when using INT4 for canceling STOP mode.
0
P24_3: External pin is used as a general-purpose port.
INT3: Input to INT3.
1
INT3: Input to INT3.
Set "1" when using INT3 for canceling STOP mode.
0
P24_2: External pin is used as a general-purpose port.
INT2: Input to INT2.
1
INT2: Input to INT2.
Set "1" when using INT2 for canceling STOP mode.
0
P24_1: External pin is used as a general-purpose port.
INT1: Input to INT1.
1
IINT1: Input to INT1.
Set "1" when using INT1 for canceling STOP mode.
0
P24_0: External pin is used as a general-purpose port.
INT0: Input to INT0.
1
INT0: Input to INT0.
Set "1" when using INT0 for canceling STOP mode.
PFR24_7
PFR24_6
PFR24_5
PFR24_4
PFR24_3
PFR24_2
PFR24_1
PFR24_0
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Function
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CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 28
Since port 28 is also used as an input of A/D converter, set the corresponding bit of ADER (analog input
enable register) as well as the corresponding bit of PFR28 to "0" to use as a general-purpose port.
Figure 9.3-12 Configuration of Control Register (Port 28)
Address
bit
PFR28 000D9CH
ADERL 0001A2H
high byte
7
6
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
4
3
2
1
0
Initial value
PFR28_4 PFR28_3 PFR28_2 PFR28_1 PFR28_0 00000000B
ADE12 ADE11 ADE10
R/W
R/W
R/W
ADE9
R/W
ADE8
R/W
00000000B
Table 9.3-12 Function of Control Register (Port 28)
Bit name
Value
00B
PFR28_4 / ADE12
PFR28_3 / ADE11
PFR28_2 / ADE10
PFR28_1 / ADE9
PFR28_0 / ADE8
01B, 10B
P28_4: External pin is used as a general-purpose port.
Setting is disabled.
11B
AN12: Used as an analog input of A/D converter.
00B
P28_3: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN11: Used as an analog input of A/D converter.
00B
P28_2: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN10: Used as an analog input of A/D converter.
00B
P28_1: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN9: Used as an analog input of A/D converter.
00B
P28_0: External pin is used as a general-purpose port.
01B, 10B
11B
240
Function
Setting is disabled.
AN8: Used as an analog input of A/D converter.
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 9 I/O PORT
9.3 Setting of Port Function Register
MB91461
■ Port 29
Since port 29 is also used as an input of A/D converter, set the corresponding bit of ADER (analog input
enable register) as well as the corresponding bit of PFR29 to "0" to use as a general-purpose port.
Figure 9.3-13 Configuration of Control Register (Port 29)
Address
bit7
6
5
4
3
2
1
0
Initial value
PFR29 000D9DH PFR29_7 PFR29_6 PFR29_5 PFR29_4 PFR29_3 PFR29_2 PFR29_1 PFR29_0 00000000B
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1 ADE0 00000000B
ADERL 0001A3H ADE7
low_byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 9.3-13 Function of Control Register (Port 29)
Bit name
Value
00B
PFR29_7 / ADE7
PFR29_6 / ADE6
PFR29_5 / ADE5
PFR29_4 / ADE4
PFR29_3 / ADE3
PFR29_2 / ADE2
PFR29_1 / ADE1
PFR29_0 / ADE0
01B, 10B
P29_7: External pin is used as a general-purpose port.
Setting is disabled.
11B
AN7: Used as an analog input of A/D converter.
00B
P29_6: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN6: Used as an analog input of A/D converter.
00B
P29_5: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN5: Used as an analog input of A/D converter.
00B
P29_4: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN4: Used as an analog input of A/D converter.
00B
P29_3: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN3: Used as an analog input of A/D converter.
00B
P29_2: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN2: Used as an analog input of A/D converter.
00B
P29_1: External pin is used as a general-purpose port.
01B, 10B
Setting is disabled.
11B
AN1: Used as an analog input of A/D converter.
00B
P29_0: External pin is used as a general-purpose port.
01B, 10B
11B
CM71-10159-2E
Function
Setting is disabled.
AN0: Used as an analog input of A/D converter.
FUJITSU MICROELECTRONICS LIMITED
241
CHAPTER 9 I/O PORT
9.4 Selection of Pin Input Level
9.4
MB91461
Selection of Pin Input Level
Input level of the pins can be selected by setting registers.
■ Pin Input Level
Table 9.4-1 shows the input levels.
Table 9.4-1 Input Level
VIL
VIH
CMOS
VIL = 0.3 × VDD
VIH = 0.7 × VDD
CMOS Schmitt trigger 1
VIL = 0.3 × VDD
VIH = 0.7 × VDD
CMOS Schmitt trigger 2
VIL = 0.2 × VDD
VIH = 0.8 × VDD
Automotive
VIL = 0.5 × VDD
VIH = 0.8 × VDD
Name
■ Selection of Pin Input Level
Selection of input level for each pin is performed using the pin input level selection registers (PILR,
EPIRL). Table 9.4-2 shows the settings of the pin input level selection registers.
Table 9.4-2 Pin Input Level Selection Register Setting
PILRxy
Pin input level
0 [Initial Value]
CMOS Schmitt trigger1
1
CMOS Schmitt trigger2
Figure 9.4-1 The Structure of Selection of Pin Input Level
PILR14
PILR15
PILR16
PILR17
PILR18
PILR19
PILR20
PILR21
PILR22
PILR23
PILR24
PILR28
PILR29
Address
000E4EH
000E4FH
000E50H
000E51H
000E52H
000E53H
000E54H
000E55H
000E56H
000E57H
000E58H
000E5CH
000E5DH
bit7
6
5
4
-
-
-
-
PILR14_3 PILR14_2 PILR14_1 PILR14_0
-
-
-
-
PILR15_3 PILR15_2 PILR15_1 PILR15_0
PILR16_7
-
-
-
-
2
-
1
-
0
-
PILR17_7 PILR17_6 PILR17_5 PILR17_4 PILR17_3 PILR17_2 PILR17_1 PILR17_0
-
-
PILR18_2 PILR18_1 PILR18_0
-
PILR19_6 PILR19_5 PILR19_4
-
-
PILR19_2 PILR19_1 PILR19_0
-
PILR20_6 PILR20_5 PILR20_4
-
PILR20_2 PILR20_1 PILR20_0
-
-
-
PILR21_6 PILR21_5 PILR21_4
-
PILR21_2 PILR21_1 PILR21_0
PILR22_7 PILR22_6 PILR22_5 PILR22_4 PILR22_3 PILR22_2
-
PILR23_6
-
-
PILR22_0
PILR23_4 PILR23_3 PILR23_2 PILR23_1 PILR23_0
PILR24_7 PILR24_6 PILR24_5 PILR24_4 PILR24_3 PILR24_2 PILR24_1 PILR24_0
-
-
-
PILR28_4 PILR28_3 PILR28_2 PILR28_1 PILR28_0
PILR29_7 PILR29_6 PILR29_5 PILR29_4 PILR29_3 PILR29_2 PILR29_1 PILR29_0
R/W
242
3
R/W
R/W
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
R/W
Initial value
----0000B
----0000B
0-------B
00000000B
-----000B
-000-000B
-000-000B
-000-000B
----00-0B
-0-00000B
00--0000B
---00000B
00000000B
R/W
CM71-10159-2E
CHAPTER 9 I/O PORT
9.5 Pull-up and Pull-down Control Register
MB91461
9.5
Pull-up and Pull-down Control Register
The pin has a function that adds the pull-up or pull-down of 50 kΩ. This function can be
controlled by software in unit of a bit.
■ Pull-up and Pull-down Control
The pull-up and pull-down functions are enabled by the port pull-up and pull-down enable register (PPER),
and the pull-up and pull-down are controlled by the port pull-up and pull-down control register (PPCR).
The pull-up or pull-down of the pin is automatically disabled in the following conditions:
• Port is in the output state.
• In STOP mode
■ Port Pull-up and Pull-down Enable Register
Table 9.5-1 shows the setting of port pull-up and pull-down enable register.
Ports also used as I2C interface and ports also used as A/D converter input do not have pull-up and pulldown controls.
Table 9.5-1 Setting of Port Pull-up and Pull-down Enable Register
Port pull-up and pull-down enable register
Bit
PPERxy
0 [Initial value]
1
Pull-up and pull-down are invalid.
Pull-up and pull-down are valid.
Figure 9.5-1 The Configuration of Port Pull-up and Pull-down Enable Register
PPER14
PPER15
PPER16
PPER17
PPER18
PPER19
PPER20
PPER21
PPER22
PPER23
PPER24
PPER28
PPER29
Address
000ECEH
000ECFH
000ED0H
000ED1H
000ED2H
000ED3H
000ED4H
000ED5H
000ED6H
000ED7H
000ED8H
000EDCH
000EDDH
bit7
6
5
4
-
-
-
-
PPER14_3 PPER14_2 PPER14_1 PPER14_0
-
-
-
-
PPER15_3 PPER15_2 PPER15_1 PPER15_0
PPER16_7
-
-
-
-
2
1
-
-
0
-
PPER17_7 PPER17_6 PPER17_5 PPER17_4 PPER17_3 PPER17_2 PPER17_1 PPER17_0
-
-
-
-
-
PPER18_2 PPER18_1 PPER18_0
-
PPER19_6 PPER19_5 PPER19_4
-
PPER19_2 PPER19_1 PPER19_0
-
PPER20_6 PPER20_5 PPER20_4
-
PPER20_2 PPER20_1 PPER20_0
-
PPER21_6 PPER21_5 PPER21_4
-
PPER21_2 PPER21_1 PPER21_0
-
-
-
-
PPER23_6
-
PPER24_7 PPER24_6
-
-
-
-
-
-
PPER22_3 PPER22_2
PPER22_0
PPER23_4 PPER23_3 PPER23_2 PPER23_1 PPER23_0
-
PPER24_3 PPER24_2 PPER24_1 PPER24_0
PPER28_4 PPER28_3 PPER28_2 PPER28_1 PPER28_0
PPER29_7 PPER29_6 PPER29_5 PPER29_4 PPER29_3 PPER29_2 PPER29_1 PPER29_0
R/W
CM71-10159-2E
3
R/W
R/W
R/W
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
Initial value
----0000B
----0000B
0-------B
00000000B
-----000B
-000-000B
-000-000B
-000-000B
----00-0B
-0-00000B
00--0000B
00000000B
00000000B
R/W
243
CHAPTER 9 I/O PORT
9.5 Pull-up and Pull-down Control Register
MB91461
■ Port Pull-up and Pull-down Control Register
Table 9.5-2 shows the setting of port pull-up and pull-down control register. The set value of each bit is
enabled only when the corresponding PPER is set.
Ports also used as I2C interface and ports also used as A/D converter input do not have pull-up and pulldown controls.
Table 9.5-2 Setting of Port Pull-up and Pull-down Control Register
Port pull-up and pull-down control register
Bit
PPCRxy
0
1 [Initial value]
Pull-down
Pull-up
Figure 9.5-2 The Configuration of Port Pull-up and Pull-down Control Register
PPCR14
PPCR15
PPCR16
PPCR17
PPCR18
PPCR19
PPCR20
PPCR21
PPCR22
PPCR23
PPCR24
PPCR28
PPCR29
Address
000F0EH
000F0FH
000F10H
000F11H
000F12H
000F13H
000F14H
000F15H
000F16H
000F17H
000F18H
000F1CH
000F1DH
bit7
6
5
4
-
-
-
-
PPCR14_3 PPCR14_2 PPCR14_1 PPCR14_0
3
-
-
-
-
PPCR15_3 PPCR15_2 PPCR15_1 PPCR15_0
PPCR16_7
-
-
-
-
2
-
1
-
0
-
PPCR17_7 PPCR17_6 PPCR17_5 PPCR17_4 PPCR17_3 PPCR17_2 PPCR17_1 PPCR17_0
-
-
PPCR18_2 PPCR18_1 PPCR18_0
-
PPCR19_6 PPCR19_5 PPCR19_4
-
-
-
PPCR19_2 PPCR19_1 PPCR19_0
-
PPCR20_6 PPCR20_5 PPCR20_4
-
PPCR20_2 PPCR20_1 PPCR20_0
-
PPCR21_6 PPCR21_5 PPCR21_4
-
PPCR21_2 PPCR21_1 PPCR21_0
-
-
-
-
PPCR23_6
-
PPCR24_7 PPCR24_6
-
-
-
-
-
-
PPCR22_3 PPCR22_2
-
PPCR22_0
PPCR23_4 PPCR23_3 PPCR23_2 PPCR23_1 PPCR23_0
-
PPCR24_3 PPCR24_2 PPCR24_1 PPCR24_0
PPCR28_4 PPCR28_3 PPCR28_2 PPCR28_1 PPCR28_0
PPCR29_7 PPCR29_6 PPCR29_5 PPCR29_4 PPCR29_3 PPCR29_2 PPCR29_1 PPCR29_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
----1111B
----1111B
1-------B
11111111B
-----111B
-111-111B
-111-111B
-111-111B
----11-1B
-1-11111B
11--1111B
11111111B
11111111B
R/W
Note:
For the period that pull-up or pull-down is allowed (PPER=1), write access to the PPCR is invalid and
the register value is not updated. Changing the set value of the PPCR is valid only when the
corresponding PPER is "0".
244
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10
INTERRUPT CONTROLLER
This chapter describes the overview of the interrupt
controller, configuration and functions of the registers,
and interrupt controller operation.
10.1 Overview of the Interrupt Controller
10.2 Interrupt Controller Registers
10.3 Interrupt Controller Operation
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
245
CHAPTER 10 INTERRUPT CONTROLLER
10.1 Overview of the Interrupt Controller
10.1
MB91461
Overview of the Interrupt Controller
The interrupt controller controls interrupt acceptance and arbitration processing.
■ Hardware Configuration of the Interrupt Controller
This module consists of the following components:
• ICR register
• Interrupt priority decision circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancellation request generator
■ Main Functions of the Interrupt Controller
This module has the following main functions:
• Detecting NMI requests and interrupt requests
• Deciding priority (using a level or number)
• Passing (to the CPU) an interrupt level of the interrupt factor based on the priority decision
• Passing (to the CPU) an interrupt number of the interrupt factor based on the priority decision
• Instructing for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level
other than 11111B (to CPU)
• Generating a hold request cancellation request for the bus master
246
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.1 Overview of the Interrupt Controller
MB91461
■ Interrupt Controller Registers
Figure 10.1-1 shows the interrupt controller registers.
Figure 10.1-1 Interrupt Controller Registers
Register
Address
bit7
6
5
4
3
2
1
0
ICR00
000440H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
000441H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
000442H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
000443H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
000444H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
000445H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
000446H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
000447H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
000448H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
000449H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
00044AH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
00044BH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
00044CH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
00044DH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
00044EH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
00044FH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
000450H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
000451H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
000452H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
000453H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
000454H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
000455H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
000456H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
000457H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
000458H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
000459H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
00045AH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
00045BH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
00045CH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
00045DH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
00045EH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
00045FH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
000460H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
000461H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
000462H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
000463H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
000464H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
(Continued)
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
247
CHAPTER 10 INTERRUPT CONTROLLER
10.1 Overview of the Interrupt Controller
MB91461
(Continued)
Register
Address
bit7
6
5
4
3
2
1
0
ICR37
000465H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
000466H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
000467H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
000468H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
000469H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
00046AH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
00046BH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
00046CH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
00046DH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
00046EH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
00046FH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR48
000470H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR49
000471H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR50
000472H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR51
000473H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR52
000474H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR53
000475H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR54
000476H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR55
000477H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR56
000478H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR57
000479H
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR58
00047AH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR59
00047BH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR60
00047CH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR61
00047DH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR62
00047EH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
ICR63
00047FH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
R
R/W
R/W
R/W
R/W
Register
Address
bit7
6
5
4
3
2
1
0
HRCL
000045H
MHALTI
−
−
LVL4
LVL3
LVL2
LVL1
LVL0
R
R/W
R/W
R/W
R/W
R/W
248
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.1 Overview of the Interrupt Controller
MB91461
■ Block Diagram of the Interrupt Controller
Figure 10.1-2 shows a block diagram of the interrupt controller.
Figure 10.1-2 Block Diagram of the Interrupt Controller
WAKEUP ("1" when level ≠ 11111B)
UNMI
Priority decision
NMI
processing
Level4 to Level0
5
Level
and
vector
generation
Level decision
RI00
·
·
·
RI63
( DLYIRQ)
ICR00
·
·
·
ICR63
Vector
decision
HLDREQ
cancellation
request
6
MHALTI
VCT5 to VCT0
R-bus
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
249
CHAPTER 10 INTERRUPT CONTROLLER
10.2 Interrupt Controller Registers
10.2
MB91461
Interrupt Controller Registers
This section describes the configuration and functions of the interrupt controller
registers.
■ Details of the Interrupt Controller Registers
The interrupt controller has the following two registers:
• Interrupt Control Register (ICR)
• HRCL (Hold Request Cancellation Request Register)
250
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.2 Interrupt Controller Registers
MB91461
10.2.1
Interrupt Control Register (ICR)
An interrupt control register (ICR) is provided for each of the interrupt input and sets the
interrupt level of the corresponding interrupt request.
■ Bit Configuration of the Interrupt Control Register (ICR)
The following shows the bit configuration of the interrupt control register (ICR).
Figure 10.2-1 Bit Configuration of the Interrupt Control Register (ICR)
bit
7
6
5
4
3
2
1
0
Initial value
Address: ch.00 000440H
ch.63 00047FH
−
−
−
ICR4
ICR3
ICR2
ICR1
ICR0
---11111B
R
R/W
R/W
R/W
R/W
[bit4 to bit0] ICR4 to ICR0
These interrupt level setting bits specify the interrupt level of the corresponding interrupt request.
If an interrupt level defined in this register is higher than the level mask value defined in the ILM
register of the CPU, the interrupt request is masked by the CPU.
These bits are initialized to 11111B by reset.
Table 10.2-1 shows the relationship between available interrupt level setting bits and interrupt levels.
Table 10.2-1 Relationship Between Available Interrupt Level Setting Bits and Interrupt
Levels
ICR4*
ICR3
ICR2
ICR1
ICR0
0
0
0
0
0
0
0
1
1
1
0
14
0
1
1
1
1
15
1
0
0
0
0
16
1
0
0
0
1
17
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
*: ICR4 is always "1". "0" cannot be written to this bit.
CM71-10159-2E
Interrupt level
Reserved by system
NMI
Maximum level can be set
(High)
(Low)
Interrupt disabled
FUJITSU MICROELECTRONICS LIMITED
251
CHAPTER 10 INTERRUPT CONTROLLER
10.2 Interrupt Controller Registers
10.2.2
MB91461
HRCL (Hold Request Cancellation Request Register)
HRCL is a level setting register used to generate a hold request cancellation request.
■ Bit Configuration of the Hold Request Cancellation Request Register (HRCL)
The following shows the bit configuration of the hold request cancellation request register (HRCL).
Figure 10.2-2 Bit Configuration of the Hold Request Cancellation Request Register (HRCL)
HRCL
bit
Address: 000039H
7
6
5
4
3
2
1
0
Initial value
MHALTI
−
−
LVL4
LVL3
LVL2
LVL1
LVL0
0--11111B
R
R/W
R/W
R/W
R/W
R/W
[bit7] MHALTI
MHALTI is the DMA transfer suppression bit controlled by an NMI request. An NMI request sets this
bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit in the same way as
a normal interrupt routine.
[bit4 to bit0] LVL4 to LVL0
These bits set the interrupt level used to issue a hold request cancellation request to the bus master.
If an interrupt request with a higher level than the level defined in the HRCL register occurs, a hold
request cancellation request is issued to the bus master.
The LVL4 bit is fixed to "1" and "0" cannot be written to this bit.
252
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
10.3
Interrupt Controller Operation
This section describes the operation of the interrupt controller.
■ Priority Decision
The interrupt controller selects the interrupt factor with the highest priority from among those that occur
simultaneously and outputs the interrupt level and the interrupt number of that factor to the CPU.
The following shows the priority decision criteria for interrupt factor:
1) NMI
2) Factor that meets the following conditions:
- Factor with a value other than 31 for the interrupt level (31 means interrupt is disabled.)
- Factor with the smallest value for the interrupt level
- Factor with the smallest interrupt number among those satisfy the both conditions above
If no interrupt factor is selected according to the above decision criteria, 31 (11111B) is outputted as the
interrupt level. The interrupt number at this time is undefined.
Table 10.3-1 shows the relationship among the interrupt factors, interrupt numbers, and interrupt levels.
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (1 / 6)
Interrupt number
Interrupt factor
Interrupt level
TBR default
address
Resource
Number *
Decimal
Hexadecimal
Reset
0
00H
−
−
3FCH
000FFFFCH
−
Mode vector
1
01H
−
−
3F8H
000FFFF8H
−
Reserved by system
2
02H
−
−
3F4H
000FFFF4H
−
Reserved by system
3
03H
−
−
3F0H
000FFFF0H
−
Reserved by system
4
04H
−
−
3ECH
000FFFECH
−
Reserved by system (UDSU)
5
05H
−
−
3E8H
000FFFE8H
−
Reserved by system (UDSU)
6
06H
−
−
3E4H
000FFFE4H
−
Coprocessor absent trap
7
07H
−
−
3E0H
000FFFE0H
−
Coprocessor error trap
8
08H
−
−
3DCH
000FFFDCH
−
INTE instruction
9
09H
−
−
3D8H
000FFFD8H
−
Reserved by system
10
0AH
−
−
3D4H
000FFFD4H
−
Reserved by system
11
0BH
−
−
3D0H
000FFFD0H
−
Step trace trap
12
0CH
−
−
3CCH
000FFFCCH
−
NMI request (tool)
13
0DH
−
−
3C8H
000FFFC8H
−
CM71-10159-2E
Register
address
Offset
Setting
register
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CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (2 / 6)
Interrupt number
Interrupt factor
Interrupt level
TBR default
address
Resource
Number *
Decimal
Hexadecimal
Undefined instruction
exception
14
0EH
−
−
3C4H
000FFFC4H
−
NMI request
15
0FH
15(F)
Fixed
15(F)
Fixed
3C0H
000FFFC0H
−
External interrupt 0
16
10H
440H
3BCH
000FFFBCH
0
ICR00
3B8H
000FFFB8H
1
3B4H
000FFFB4H
2
3B0H
000FFFB0H
3
3ACH
000FFFACH
−
3A8H
000FFFA8H
−
3A4H
000FFFA4H
−
3A0H
000FFFA0H
−
39CH
000FFF9CH
−
398H
000FFF98H
−
394H
000FFF94H
−
390H
000FFF90H
−
38CH
000FFF8CH
−
388H
000FFF88H
−
384H
000FFF84H
−
380H
000FFF80H
−
37CH
000FFF7CH
4
378H
000FFF78H
5
374H
000FFF74H
−
370H
000FFF70H
−
36CH
000FFF6CH
−
368H
000FFF68H
−
364H
000FFF64H
−
360H
000FFF60H
−
35CH
000FFF5CH
−
358H
000FFF58H
−
External interrupt 1
17
11H
External interrupt 2
18
12H
External interrupt 3
19
13H
External interrupt 4
20
14H
External interrupt 5
21
15H
External interrupt 6
22
16H
External interrupt 7
23
17H
External interrupt 8
24
18H
External interrupt 9
25
19H
External interrupt 10
26
1AH
External interrupt 11
27
1BH
External interrupt 12
28
1CH
External interrupt 13
29
1DH
External interrupt 14
30
1EH
External interrupt 15
31
1FH
Reload timer 0
32
20H
Reload timer 1
33
21H
Reload timer 2
34
22H
Reload timer 3
35
23H
Reserved by system
36
24H
Reserved by system
37
25H
Reserved by system
38
26H
Reload timer 7
39
27H
Free-run timer 0
40
28H
Free-run timer 1
254
41
29H
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
Register
address
Offset
Setting
register
441H
442H
443H
444H
445H
446H
447H
448H
449H
44AH
44BH
44CH
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (3 / 6)
Interrupt number
Interrupt factor
Free-run timer 2
Decimal
Hexadecimal
42
2AH
Free-run timer 3
43
2BH
Reserved by system
44
2CH
Reserved by system
45
2DH
Reserved by system
46
2EH
Reserved by system
47
2FH
CAN 0
48
30H
CAN 1
49
31H
Reserved by system
50
32H
Reserved by system
51
33H
Reserved by system
52
34H
Reserved by system
53
35H
LIN-UART 0 RX
54
36H
LIN-UART 0 TX
55
37H
LIN-UART 1 RX
56
38H
LIN-UART 1 TX
57
39H
LIN-UART 2 RX
58
3AH
LIN-UART 2 TX
59
3BH
LIN-UART 3 RX
60
3CH
LIN-UART 3 TX
61
3DH
Reserved by system
62
3EH
Delayed interrupt
63
3FH
Reserved by system
64
40H
Reserved by system
65
41H
LIN-UART 4 RX
66
42H
LIN-UART 4 TX
67
43H
LIN-UART 5 RX
68
44H
LIN-UART 5 TX
CM71-10159-2E
69
45H
Interrupt level
Setting
register
Register
address
ICR13
44DH
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
(ICR24)
ICR25
ICR26
44EH
44FH
450H
451H
452H
453H
454H
455H
456H
457H
458H
459H
45AH
Offset
TBR default
address
Resource
Number *
354H
000FFF54H
−
350H
000FFF50H
−
34CH
000FFF4CH
−
348H
000FFF48H
−
344H
000FFF44H
−
340H
000FFF40H
−
33CH
000FFF3CH
−
338H
000FFF38H
−
334H
000FFF34H
−
330H
000FFF30H
−
32CH
000FFF2CH
−
328H
000FFF28H
−
324H
000FFF24H
6
320H
000FFF20H
7
31CH
000FFF1CH
8
318H
000FFF18H
9
314H
000FFF14H
−
310H
000FFF10H
−
30CH
000FFF0CH
−
308H
000FFF08H
−
304H
000FFF04H
−
300H
000FFF00H
−
2FCH
000FFEFCH
−
2F8H
000FFEF8H
−
2F4H
000FFEF4H
10
2F0H
000FFEF0H
11
2ECH
000FFEECH
12
2E8H
000FFEE8H
13
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CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (4 / 6)
Interrupt number
Interrupt factor
LIN-USART 6 RX
Decimal
Hexadecimal
70
46H
LIN-USART 6 TX
71
47H
Reserved by system
72
48H
Reserved by system
73
49H
I2C_0 / I2C_2
74
4AH
Interrupt level
Setting
register
Register
address
ICR27
45BH
ICR28
ICR29
I2C_1 / I2C_3
75
4BH
Reserved by system
76
4CH
Reserved by system
77
4DH
Reserved by system
78
4EH
Reserved by system
79
4FH
Reserved by system
80
50H
Reserved by system
81
51H
Reserved by system
82
52H
Reserved by system
83
53H
Reserved by system
84
54H
Reserved by system
85
55H
Reserved by system
86
56H
Reserved by system
87
57H
Reserved by system
88
58H
Reserved by system
89
59H
Reserved by system
90
5AH
Reserved by system
91
5BH
Input capture 0
92
5CH
Input capture 1
93
5DH
Input capture 2
94
5EH
Input capture 3
95
5FH
Reserved by system
96
60H
Reserved by system
256
97
61H
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
45CH
45DH
45EH
45FH
460H
461H
462H
463H
464H
465H
566H
467H
468H
FUJITSU MICROELECTRONICS LIMITED
Offset
TBR default
address
Resource
Number *
2E4H
000FFEE4H
−
2E0H
000FFEE0H
−
2DCH
000FFEDCH
−
2D8H
000FFED8H
−
2D4H
000FFED4H
−
2D0H
000FFED0H
−
2CCH
000FFECCH
−
2C8H
000FFEC8H
−
2C4H
000FFEC4H
−
2C0H
000FFEC0H
−
2BCH
000FFEBCH
−
2B8H
000FFEB8H
−
2B4H
000FFEB4H
−
2B0H
000FFEB0H
−
2ACH
000FFEACH
−
2A8H
000FFEA8H
−
2A4H
000FFEA4H
−
2A0H
000FFEA0H
−
29CH
000FFE9CH
−
298H
000FFE98H
−
294H
000FFE94H
−
290H
000FFE90H
−
28CH
000FFE8CH
−
288H
000FFE88H
−
284H
000FFE84H
−
280H
000FFE80H
−
27CH
000FFE7CH
−
278H
000FFE78H
−
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (5 / 6)
Interrupt number
Interrupt factor
Reserved by system
Decimal
Hexadecimal
98
62H
Reserved by system
99
63H
Output capture 0
100
64H
Output capture 1
101
65H
Output capture 2
102
66H
Output capture 3
103
67H
Reserved by system
104
68H
Reserved by system
105
69H
Reserved by system
106
6AH
Reserved by system
107
6BH
Reserved by system
108
6CH
Reserved by system
109
6DH
Reserved by system
110
6EH
Reserved by system
111
6FH
PPG0
112
70H
PPG1
113
71H
PPG2
114
72H
PPG3
115
73H
PPG4
116
74H
PPG5
117
75H
PPG6
118
76H
PPG7
119
77H
Reserved by system
120
78H
Reserved by system
121
79H
Reserved by system
122
7AH
Reserved by system
123
7BH
Reserved by system
124
7CH
Reserved by system
CM71-10159-2E
125
7DH
Interrupt level
Setting
register
Register
address
ICR41
469H
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
ICR48
ICR49
ICR50
ICR51
ICR52
ICR53
ICR54
46AH
46BH
46CH
46DH
46EH
46FH
470H
471H
472H
473H
474H
475H
476H
Offset
TBR default
address
Resource
Number *
274H
000FFE74H
−
270H
000FFE70H
−
26CH
000FFE6CH
−
268H
000FFE68H
−
264H
000FFE64H
−
260H
000FFE60H
−
25CH
000FFE5CH
−
258H
000FFE58H
−
254H
000FFE54H
−
250H
000FFE50H
−
24CH
000FFE4CH
−
248H
000FFE48H
−
244H
000FFE44H
−
240H
000FFE40H
−
23CH
000FFE3CH
15
238H
000FFE38H
−
234H
000FFE34H
−
230H
000FFE30H
−
22CH
000FFE2CH
−
228H
000FFE28H
−
224H
000FFE24H
−
220H
000FFE20H
−
21CH
000FFE1CH
−
218H
000FFE18H
−
214H
000FFE14H
−
210H
000FFE10H
−
20CH
000FFE0CH
−
208H
000FFE08H
−
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
Table 10.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (6 / 6)
Interrupt number
Interrupt factor
Reserved by system
Decimal
Hexadecimal
126
7EH
Reserved by system
127
7FH
Reserved by system
128
80H
Reserved by system
129
81H
Reserved by system
130
82H
Reserved by system
131
83H
Real time clock
132
84
Interrupt level
Setting
register
Register
address
ICR55
477H
ICR56
ICR57
ICR58
Reserved by system
133
85H
A/D converter 0
134
85
ICR59
Reserved by system
135
87H
Reserved by system
136
88H
Reserved by system
137
89H
Reserved by system
138
8AH
Reserved by system
139
8BH
Time base overflow
140
8CH
PLL clock gear
141
8DH
DMA controller
142
8EH
ICR60
ICR61
ICR62
ICR63
478H
479H
47AH
47BH
47CH
47DH
47EH
47FH
Offset
TBR default
address
Resource
Number *
204H
000FFE04H
−
200H
000FFE00H
−
1FCH
000FFDFCH
−
1F8H
000FFDF8H
−
1F4H
000FFDF4H
−
1F0H
000FFDF0H
−
1ECH
000FFDECH
−
1E8H
000FFDE8H
−
1E4H
000FFDE4H
14
1E0H
000FFDE0H
−
1DCH
000FFDDCH
−
1D8H
000FFDD8H
−
1D4H
000FFDD4H
−
1D0H
000FFDD0H
−
1CCH
000FFDCCH
−
1C8H
000FFDC8H
−
1C4H
000FFDC4H
−
1C0H
000FFDC0H
−
Main/sub oscillation
stabilization wait
143
8FH
Reserved by system
144
90H
−
−
1BCH
000FFDBCH
−
Use in INT instruction
145
:
255
91H
:
FFH
−
−
1B8H
:
000H
000FFDB8H
:
000FFC00H
−
258
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
■ NMI (Non Maskable Interrupt)
NMI has the highest priority among the interrupt factors handled by this module.
Therefore, NMI is always selected if it occurs at the same time as other interrupt factors do.
● NMI generation
If an NMI occurs, the following information is reported to the CPU:
• Interrupt level: 15 (01111B)
• Interrupt number: 15 (0001111B)
● NMI detection
The external interrupt and NMI module sets and detects the NMI. This module only generates an interrupt
level, interrupt number, and MHALTI in response to an NMI request.
● DMA transfer suppression by NMI
If an NMI request is generated, the MHALTI bit of the HRCL register is set to "1" to suppress DMA
transfer. To cancel the suppression of DMA transfer, clear the MHALTI bit to "0" at the end of the NMI
routine.
■ Hold Request Cancellation Request
If an interrupt with a high priority is processed during CPU hold (during DMA transfer), the device that has
generated the hold request must cancel the request. Set the interrupt level used as the criterion of generating
a cancellation request in the HRCL register.
● Generation criteria
If an interrupt factor with a higher interrupt level than the level defined in the HRCL register is generated, a
hold request cancellation request is generated.
HRCL register interrupt level > Interrupt level after a priority decision
→ Cancellation request is generated
HRCL register interrupt level ≤ Interrupt level after a priority decision
→ Cancellation request is not generated
Unless the interrupt factor that has caused the cancellation request is cleared, the cancellation request
remains valid and so no DMA transfer occurs as a result. Be sure to clear the corresponding interrupt
factor. If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL register is
"1".
CM71-10159-2E
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259
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
● Available setting levels
Values that can be set in the HRCL register range from 10000B to 11111B, which is the same range as for
the ICR.
If this register is set to 11111B, a cancellation request is issued for all the interrupt levels. If this register is
set to 10000B, a cancellation request is issued only for an NMI.
Table 10.3-2 shows the settings of interrupt levels for the hold request cancellation request generation.
Table 10.3-2 Settings of Interrupt Levels for the Hold Request Cancellation Request
Generation
16
NMI only
17
NMI, Interrupt level 16
18
NMI, Interrupt levels 16 and 17
···
Interrupt level for cancellation request generation
···
HRCL register
31
NMI, Interrupt levels 16 to 30 [Initial value]
After a reset, DMA transfer is suppressed at any interrupt levels. Since DMA transfer cannot be performed
if an interrupt has been occurred, be sure to set the HRCL register to the appropriate value.
■ Return from Standby Mode (Sleep/Stop)
This module implements a function that causes a return from stop mode if an interrupt request occurs. If at
least one interrupt request that includes NMI from the peripheral is generated (with an interrupt level other
than 11111B), a return request from stop mode is generated for the clock controller.
Since the priority decision unit restarts operation when a clock is supplied after returning from stop, the
CPU executes instructions until the result of the priority decision unit is obtained.
The same operation occurs for a return from the sleep state. Registers in this module can be accessed even
in the sleep state.
Notes:
• A return from shutdown mode by NMI request is not supported.
• A return from stop mode by NMI request can be possible. However, be sure to set NMI so that
valid inputs in the stop state can be detected.
• Set an interrupt level to 11111B in the corresponding peripheral control register for an interrupt
factor that you do not want to cause a return from stop or sleep.
260
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 10 INTERRUPT CONTROLLER
10.3 Interrupt Controller Operation
MB91461
■ Example of Using the Hold Request Cancellation Request Function (HRCL)
To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request to the
DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA,
allowing the CPU to perform priority operations.
● Control register
1) HRCL (Hold request cancellation level setting register): This module:
If an interrupt with a higher interrupt level than the level defined in this register occurs, a hold request
cancellation request is issued to DMA. This register sets the level to be used as the criterion for this
purpose.
2) ICR: This module:
This register sets a higher level than the level in the HRCL register for the ICR corresponding to the
interrupt factor to be used.
● Hardware configuration
Figure 10.3-1 shows the flow of each signal for hold request.
Figure 10.3-1 Flow of Each Signal for Hold Request
This module
IRQ
Bus access request
MHALTI
I-unit
DHREQ
DMA
B-unit
DHREQ: D-bus hold request
CPU
DHACK: D-bus hold acknowledge
(ICR)
IRQ:
(HRCL)
DHACK
Interrupt request
MHALTI: Hold request cancellation request
● Sequence
Figure 10.3-2 shows the interrupt level HRCL < ICR (LEVEL).
Figure 10.3-2 Interrupt Level HRCL < ICR (LEVEL)
RUN
CPU
Bus hold
Interrupt processing
(1)
(2)
Bus hold (DMA transfer)
Example of
interrupt routine
Bus access request
(1) Interrupt
factor clear
···
DHREQ
DHACK
(2) RETI
IRQ
LEVEL
MHALTI
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10.3 Interrupt Controller Operation
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If an interrupt request occurs, the interrupt level changes and if the interrupt level is higher than the level
defined in the HRCL register, MHALTI becomes "H" level for DMA. This causes DMA to cancel an
access request and the CPU to return from the hold state to perform the interrupt processing.
Figure 10.3-3 shows the interrupt level HRCL < ICR (interrupt I) < ICR (interrupt II).
Figure 10.3-3 Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
Bus hold
CPU
Interrupt
processing II
Interrupt I
(3)
(4)
Interrupt
processing I
(1)
Bus hold
(DMA transfer)
(2)
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
[Example of interrupt routine]
(1), (3) Interrupt factor clear
to
(2), (4) RETI
The above example shows a case that an interrupt with a higher priority occurs while interrupt routine I is
being executed.
While the interrupt with a higher level than the level in the HRCL register is occurring, DHREQ is kept at a
low level.
Note:
Be especially careful about the relationship between interrupt levels to be defined in the HRCL and
ICR.
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CHAPTER 11
EXTERNAL INTERRUPT
CONTROLLER
This chapter describes the overview of the external
interrupt controller, configuration and functions of the
registers and external interrupt controller operation.
11.1 Overview of the External Interrupt Controller
11.2 External Interrupt Controller Registers
11.3 Operation of the External Interrupt Controller
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11.1 Overview of the External Interrupt Controller
11.1
MB91461
Overview of the External Interrupt Controller
The external interrupt controller is a block that controls external interrupt requests inputted
to INT pin.
The type can be selected from the following four types as the request level/edge to be
detected.
• "H" level
• "L" level
• Rising edge
• Falling edge
■ List of the External Interrupt Controller Registers
External interrupt controller registers are shows as follows.
Figure 11.1-1 Bit Configuration of External Interrupt Controller Registers
bit
bit
bit
bit
264
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
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External interrupt enable
register (ENIR)
External interrupt factor
register (EIRR)
Request level setting
register (ELVR)
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CHAPTER 11 EXTERNAL INTERRUPT CONTROLLER
11.1 Overview of the External Interrupt Controller
MB91461
■ Block Diagram of the External Interrupt Controller
Figure 11.1-2 shows a block diagram of the external interrupt controller.
Figure 11.1-2 Block Diagram of the External Interrupt Controller
R-bus
8
Interrupt
request
17
Interrupt enable register
Gate
17
Factor F/F
Edge detection circuit
INT0 to INT15
NMI
8
Interrupt factor register
16
Request level setting register
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11.2 External Interrupt Controller Registers
11.2
MB91461
External Interrupt Controller Registers
This section describes the configuration and functions of the external interrupt
controller registers.
■ Details of External Interrupt Controller Registers
The external interruption controller registers are the following three types:
• External Interrupt Enable Register (ENIR)
• External Interrupt Factor Register (EIRR)
• External Interrupt Request Level Setting Register (ELVR)
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11.2 External Interrupt Controller Registers
MB91461
11.2.1
External Interrupt Enable Register (ENIR)
ENIR controls the masking of external interrupt request output.
■ Bit Configuration of ENIR
Figure 11.2-1 shows the bit configuration of the interrupt enable register.
Figure 11.2-1 Bit Configuration of the Interrupt Enable Register
bit 7
6
5
4
3
2
1
0
ENIR0 Address: 000031H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
bit 7
6
5
4
3
2
1
0
ENIR1 Address: 000035H EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8
Initial value
00000000B
[R/W]
00000000B
[R/W]
The interrupt request output corresponding to the bit to which "1" is written in this register is enabled
(INT0 enabling is controlled by EN0), and a request is outputted to the interrupt controller. The pin
corresponding to the bit to which "0" is written holds the interrupt factor but does not generate a request to
the interrupt controller.
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11.2 External Interrupt Controller Registers
11.2.2
MB91461
External Interrupt Factor Register (EIRR)
EIRR indicates the presence of the corresponding external interrupt request when
reading this register, and clears the contents of the flip-flop indicating this interrupt
request when writing to this register.
■ Bit Configuration of EIRR
Bit configuration of the external interrupt factor register is as follows.
Figure 11.2-2 Bit Configuration of the External Interrupt Factor Register
bit 15
14
13
12
11
10
9
8
EIRR0 Address: 000030H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
bit 15
14
13
12
11
10
9
8
EIRR1 Address: 000034H ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8
Initial value
00000000B
[R/W]
00000000B
[R/W]
When this EIRR register is read, the operation becomes as follows depending on the value.
If the read value of this EIRR register is "1", there is an external interrupt request at the pin corresponding
to the bit. When "0" is written to this register, the request flip-flop of the corresponding bit is cleared.
Writing "1" is invalid.
For a read by a read-modify-write (RMW) instruction, "1" is read.
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11.2 External Interrupt Controller Registers
MB91461
11.2.3
External Interrupt Request Level Setting Register (ELVR)
ELVR is the register that selects a request detection.
■ Bit Configuration of ELVR
Bit configuration of the external interrupt request level setting is as follows.
Figure 11.2-3 Bit Configuration of the External Interrupt Request Level Setting
bit 7
ELVR0 Address: 000032H LB3
bit 15
000033H LB7
6
5
4
3
2
1
0
Initial value
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
14
13
12
11
10
9
8
Initial value
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00000000B
[R/W]
bit 7
6
5
4
3
ELVR1 Address: 000036H LB11 LA11 LB10 LA10 LB9
2
1
0
LA9
LB8
LA8
bit 15
14
13
12
11
10
9
8
000037H LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12
Initial value
00000000B
Initial value
00000000B
[R/W]
In ELVR, two bits each are assigned to each interrupt channel and the setting is as shown below.
Even though each bit of the EIRR is cleared while the request input is level-base operation, the
corresponding bit is set again as long as the input is at active level.
Table 11.2-1 shows the assignment of ELVR.
Table 11.2-1 Assignment of ELVR
LBx, LAx
Operation
00B
Detecting a request with "L" level [Initial value]
01B
Detecting a request with "H" level
10B
Detecting a request with rising edge
11B
Detecting a request with falling edge
Notes:
• Edge detection cannot be set for the interrupts that cause return from the STOP mode and the
shut-down mode.
• If external interrupt request level is changed, internal interrupt request may be occurred. So clear
the external interrupt register (EIRR) after changing the external interrupt request level. When you
want to clear the external interrupt request level register once.
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11.3 Operation of the External Interrupt Controller
11.3
MB91461
Operation of the External Interrupt Controller
This section explains the operation of the external interruption controller.
■ External Interrupt Operation
After a request level and an enable register are set, if a request set in the ELVR register is inputted to the
corresponding pin, this module generates an interrupt request signal to the interrupt controller. When
priorities of the interrupts generated simultaneously in the interrupt controller is determined and if the
priority of the interrupt from this resource is the highest, the corresponding interrupt is generated.
Figure 11.3-1 shows the external interrupt operation.
Figure 11.3-1 External Interrupt Operation
External interrupt
ELVR
Resource
request
Interrupt controller
ICR Y Y
EIRR
ENIR
CPU
IL
CMP
ICR X X
CMP
ILM
Factor
■ Operation Procedure of External Interrupt
Use the following procedure to set registers located in the external interrupt controller:
1. Set the port to be used as a external interrupt input and shared general-purpose I/O port to input port.
2. Disable the target bit in the interrupt enable register (ENIR).
3. Set the target bit in the external interrupt request level setting register (ELVR).
4. Read the external interrupt request level setting register (ELVR).
5. Clear the target bit in the external interrupt source register (EIRR).
6. Enable the target bit in the interrupt enable register (ENIR).
(Simultaneous writing of 16-bit data is supported for steps 5) and 6)).
Before setting registers in this module, be sure to disable the enable register. In addition, before enabling
the enable register, be sure to clear the factor register. This procedure is required to prevent an interrupt
factor from occurring by mistake while a register is being set or an interrupt is enabled.
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CHAPTER 11 EXTERNAL INTERRUPT CONTROLLER
11.3 Operation of the External Interrupt Controller
MB91461
■ External Interrupt Request Level
If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock
machine cycles) is required to detect an edge.
If the request input level is a level setting, even when a request input arrives from the outside and is then
cancelled, the request to the interrupt controller remains valid because a factor holding circuit exists
internally.
The factor register must be cleared to cancel the request to the interrupt controller.
Figure 11.3-2 shows the clearing of the factor holding circuit when a level is set.
Figure 11.3-2 Clearing of the Factor Holding Circuit When a Level is Set
Interrupt input
Level detection
Factor F/F
(Factor holding circuit)
Enable gate
Interrupt
controller
Continuing to hold a factor unless cleared
Figure 11.3-3 shows the interrupt factor and the interrupt request to the interrupt controller when interrupt
is enabled.
Figure 11.3-3 Interrupt Factor and Interrupt Request to the Interrupt Controller
When Interrupt is Enabled
Interrupt input
"H" level
Interrupt request to
interrupt controller
Becoming invalid by clearing factor F/F
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11.3 Operation of the External Interrupt Controller
MB91461
■ Precautions when Returning from STOP State Using External Interrupt
The external interrupt signal that is initially input to the INT pin in a STOP state is input asynchronously,
allowing the device to return from the STOP state. Note, however, that there are periods from the release of
the STOP state till the end of the oscillation stabilization wait time, in such periods the input of other
external interrupt signals cannot be identified (period of b + c + d in Figure 11.3-4). This is because the
external input signal after the release of STOP mode is synchronized with the internal clock; consequently,
the corresponding interrupt source cannot be retained while the clock is still unstable.
Therefore, input an external interrupt signal after the oscillation stabilization wait time has passed, when
inputting an external interrupt after the release of STOP mode.
Figure 11.3-4 Operational Sequence for Returning from STOP State by External Interrupt
INT1
INT0
Internal
STOP
"L"
s
"H"
Regulator
Internal
operation
(RUN)
Implement command (RUN)
X0
Internal
clock
Interrupt flag clear
INTR0
INTE0
"1" (Set to enable before switching to STOP mode)
INTR1
INTE1
"1" enable (Set before switching to STOP mode)
(e)RUN
(a) STOP (b) Regulator stabilization wait time (d) Oscillation stabilization time
(c) Oscillator oscillation time
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CHAPTER 11 EXTERNAL INTERRUPT CONTROLLER
11.3 Operation of the External Interrupt Controller
MB91461
■ Operation when Recovering from STOP Mode
The operation when recovery from STOP mode is triggered by an external interrupt from an operating
circuit is as follows.
● Processing prior to entering STOP mode
Setting External Interrupt Route
It is necessary to permit the interrupt input route for release STOP status before the device transits to
STOP status. These configuration are made using the EISSR register. Under normal conditions (i.e., any
status other than STOP), the interrupt input route is permitted, so there is no need for special
recognition. In STOP status, however, the input path is controlled by the EISSR register value.
External Interrupt Inputs
If recovering from STOP status, the external interrupt signals send an input signal asynchronously.
When this interrupt signal is asserted, the internal STOP signal is immediately turned OFF. At the same
time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Regulator stabilization wait time
The mechanism for switching from the regulator used during STOP mode to the regulator used during
RUN mode is invoked when the internal STOP signal is fallen. As misoperation may occur if internal
operation starts before the voltage output of the RUN mode regulator has stabilized, a delay time is used to
wait for the internal output voltage to stabilize. The clock remains halted during this time.
● Oscillator startup time
The clock oscillation starts after the regulator stabilization delay time elapses. The startup time of the
oscillator depends on the type of oscillator used.
● Oscillation stabilization wait time
After the oscillator startup time elapses, the device waits for the oscillation stabilization wait time which is
generated internally. This time is specified by the OS1 and OS0 bits in the standby control register. After
the oscillation stabilization wait time elapses, the internal clock supply starts and execution of the interrupt
handler for the external interrupt starts. At the same time the external interrupts other than the return source
from STOP mode become able to be received.
Note:
When "H" was input externally to INT0 through INT15 and the following operation is conducted, the
request flag EIRR will be set even if "L" is not input externally:
1. An interrupt pin is set with PFR.
2. The interrupt detection level is set to "L".
3. An interrupt is enabled.
To avoid this, clear EIRR between steps 2. and 3.
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11.3 Operation of the External Interrupt Controller
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MB91461
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CHAPTER 12
REALOS RELATED
HARDWARE
This chapter describes overview, configurations/
functions of registers, and operations of REALOS.
12.1 Delayed Interrupt Module
12.2 Bit Search Module
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CHAPTER 12 REALOS RELATED HARDWARE
12.1 Delayed Interrupt Module
12.1
MB91461
Delayed Interrupt Module
This section describes the overview of the delayed interrupt module, configuration and
functions of the register, and delayed interrupt module operation.
■ Overview of the Delayed Interrupt Module
The delayed interrupt module is used to generate interrupts for switching tasks.
By using this module, an interrupt request for the CPU can be generated or cancelled from a software
program.
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CHAPTER 12 REALOS RELATED HARDWARE
MB91461
12.1.1
Overview of Delayed Interrupt Module
12.1 Delayed Interrupt Module
This section describes the register list, details and operation of the delayed interrupt
module.
■ Register List of Delayed Interrupt Module
A register list of the delayed interrupt module is as follows.
Figure 12.1-1 Bit Configuration of Delayed Interrupt Module
bit
Address: 000038H
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
DLYI
R/W
DICR
■ Block Diagram of Delayed Interrupt Module
Figure 12.1-2 shows the block diagram of the delayed interrupt module.
Figure 12.1-2 Block Diagram of the Delayed Interrupt Module
R-bus
Interrupt request
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12.1 Delayed Interrupt Module
12.1.2
MB91461
Delayed Interrupt Module Register
This section describes the configuration and functions of the delayed interrupt module
register.
■ DICR (Delayed Interrupt Module Register)
DICR is a register that controls delayed interrupts.
The following shows the bit configuration of the delayed interrupt module register (DICR).
Figure 12.1-3 Bit Configuration of the Delayed Interrupt Module Register (DICR)
bit
Address: 000038H
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
DLYI
R/W
-------0B (Initial value)
[bit0] DLYI
Table 12.1-1 DLYI
DLYI
Description
0
Delayed interrupt factor is cancelled. No request exists. [Initial value]
1
Delayed interrupt factor is generated.
This bit controls the generation and cancellation of the corresponding interrupt factors.
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CHAPTER 12 REALOS RELATED HARDWARE
12.1 Delayed Interrupt Module
MB91461
12.1.3
Operation of the Delayed Interrupt Module
The delayed interrupt is used to generate an interrupt for switching tasks. By using this
function, an interrupt request for the CPU can be generated and cancelled from a
software program.
■ Interrupt Number
The delayed interrupt is assigned to the interrupt factor corresponding to the largest interrupt number.
The delayed interrupt is assigned to the interrupt number 63 (3FH).
■ DLYI Bit of DICR
Writing "1" to this bit generates a delayed interrupt factor. Writing "0" to it cancels a delayed interrupt
factor.
This bit is the same as the interrupt factor flag for a normal interrupt. Therefore, clear this bit and switch
tasks together in the interrupt routine.
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CHAPTER 12 REALOS RELATED HARDWARE
12.2 Bit Search Module
12.2
MB91461
Bit Search Module
This section describes the overview of the bit search module, configuration and
functions of the registers, and bit search module operation.
■ Overview of the Bit Search Module
The bit search module searches for "0", "1", or any changed points in the data written to the input register
and then returns the detected bit locations.
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CHAPTER 12 REALOS RELATED HARDWARE
12.2 Bit Search Module
MB91461
12.2.1
Overview of Bit Search Module
This section describes the configuration and functions of the bit search module registers.
■ Register List of Bit Search Module
Figure 12.2-1 shows the register list of the bit search module.
Figure 12.2-1 Bit Configuration of Register List of Bit Search Module
bit 31
0
Address: 0003F0H
BSD0
0-detection data register
Address: 0003F4H
BSD1
1-detection data register
Address: 0003F8H
BSDC
Changed point detection data register
Address: 0003FCH
BSRR
Detection result register
■ Block Diagram of Bit Search Module
Figure 12.2-2 shows the block diagram of the bit search module.
Figure 12.2-2 Block Diagram of the Bit Search Module
D-bus
Input latch
Address decoder
Detection mode
Making data of 1 detection
Bit search circuit
Search result
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12.2 Bit Search Module
12.2.2
MB91461
Bit Search Module Registers
This section describes the configuration and functions of the bit search module registers.
■ 0-detection Data Register (BSD0)
This register detects 0 in the written value.
Figure 12.2-3 shows the register configuration of the 0-detection data register (BSD0).
Figure 12.2-3 The Register Configuration of the 0-detection Data Register (BSD0)
bit 31
0
000003F0H
→ Write only
→ Undefined
R/W
Initial value
The initial value at a reset is undefined. The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instruction.)
■ 1-detection Data Register (BSD1)
Figure 12.2-4 shows the register configuration of the 1-detectoin data register (BSD1).
Figure 12.2-4 The Register Configuration of the 1-detectoin Data Register (BSD1)
bit 31
0
000003F4H
R/W
Initial value
→ Readable/Writable
→ Undefined
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instruction.)
• Writing:
"1" is detected in the written value.
• Reading:
Saved data of the internal state in the bit search module is read. This register is used to save and restore
the original state when the bit search module is used by an interrupt handler, etc.
Even if data is written to the 0-detection data register or changed point detection data register, the data
can be saved and restored by using only the 1-detection data register.
The initial value at a reset is undefined.
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CHAPTER 12 REALOS RELATED HARDWARE
12.2 Bit Search Module
MB91461
■ Changed Point Detection Data Register (BSDC)
A changed point is detected in the written value.
Figure 12.2-5 shows the register configuration of the changed point detection data register (BSDC).
Figure 12.2-5 The Register Configuration of the Changed Point Detection Data Register (BSDC)
bit 31
0
000003F8H
→ Write only
→ Undefined
R/W
Initial value
The initial value at a reset is undefined.
The read value is undefined.
Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer
instruction.)
■ Detection Result Register (BSRR)
The result of 0 detection, 1 detection, or changed point detection is read.
The data register written last is used to determine which detection result to be read.
Figure 12.2-6 shows the register configuration of the detection result register (BSRR).
Figure 12.2-6 The Register Configuration of the Detection Result Register (BSRR)
bit 31
0
000003FCH
R/W
Initial value
CM71-10159-2E
→ Read only
→ Undefined
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12.2 Bit Search Module
12.2.3
MB91461
Operation of the Bit Search Module
This section explains the operation of the bit search module.
■ 0 Detection
The bit search module scans data written to the 0-detection data register from MSB to LSB and returns the
location where the first "0" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is given in Table 12.2-1.
If a "0" is not found (that is, the value is FFFFFFFFH), the value 32 is returned as the search result.
[Execution example]
Write data
Read value (decimal)
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
■ 1 Detection
The bit search module scans data written to the 1-detection data register from MSB to LSB and returns the
location where the first "1" is detected.
The detection result can be obtained by reading the detection result register. The relationship between the
detected location and the return value is given in Table 12.2-1.
If a "1" is not found (that is, the value is 00000000H), the value 32 is returned as the search result.
[Execution example]
Write data
284
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
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12.2 Bit Search Module
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■ Changed Point Detection
The bit search module scans data written to the changed point detection data register from bit30 to the LSB,
and compares with the MSB value.
The first location where a value that is different from that of the MSB is detected is returned. The detection
result can be obtained by reading the detection result register.
The relationship between the detected location and the return value is given in Table 12.2-1.
If a changed point is not detected, 32 is returned. In changed point detection, 0 is never returned as a result.
[Execution example]
Write data
Read value (decimal)
00100000000000000000000000000000B (20000000H)
→
2
00000001001000110100010101100111B (01234567H)
→
7
00000000000000111111111111111111B (0003FFFFH)
→
14
00000000000000000000000000000001B (00000001H)
→
31
00000000000000000000000000000000B (00000000H)
→
32
11111111111111111111000000000000B (FFFFF000H)
→
20
11111000010010011110000010101010B (F849E0AAH)
→
5
10000000000000101010101010101010B (8002AAAAH)
→
1
11111111111111111111111111111111B (FFFFFFFFH)
→
32
Table 12.2-1 lists the bit locations and return values (decimal).
Table 12.2-1 Bit Locations and Return Values (Decimal)
CM71-10159-2E
Detected
bit location
Return
value
Detected
bit location
Return
value
Detected
bit location
Return
value
Detected
bit location
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Not exist
32
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12.2 Bit Search Module
MB91461
■ Save and Restore Processing
If it is necessary to save and restore the internal state of the bit search module, such as when the bit search
module is used in an interrupt handler, use the following procedure:
1) Read the 1-detection data register and save its contents (save).
2) Use the bit search module.
3) Write the data saved in 1) to the 1-detection data register (restore).
With the above operation, the value obtained when the detection result register is read the next time
corresponds to the value written to the bit search module before 1).
If the data register written last is the 0-detection data register or changed point detection data register, the
value is restored correctly with the above procedure.
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DMAC (DMA CONTROLLER)
This chapter describes the overview of the DMAC,
configuration and functions of the registers, and DMAC
operation.
13.1 Overview of DMAC (DMA Controller)
13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
13.3 Explanation of the DMAC (DMA Controller) Operation
13.4 Operational Flow of DMAC (DMA Controller)
13.5 Data Path of DMAC (DMA Controller)
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13.1 Overview of DMAC (DMA Controller)
13.1
MB91461
Overview of DMAC (DMA Controller)
DMAC (DMA Controller) is used to implement DMA (Direct Memory Access) transfer in
FR family devices.
By using DMA transfer controlled by DMAC (DMA Controller), various types of data
transfer can be performed at high-speed without using the CPU and so the system
performance is improved.
■ Hardware Configuration of DMAC
The DMAC (DMA Controller) consists of the following main components:
• Five independent DMA channels
• Independent access control circuit for five channels
• 32-bit address register (reload selectable: ch.0 to ch.5)
• 16-bit transfer count register (reload selectable: one per channel)
• 4-bit block count register (one per channel)
• 2-cycle transfer
■ Main Function of DMAC
The following are the main functions related to data transfer by the DMA controller (DMAC):
● Independent data transfer can be performed for multiple channels (5ch)
• Priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
• The priority can be switched between ch.0 and ch.1.
• DMAC activation factor
- Request from built-in peripheral (shares interrupt requests, including the external interrupts)
- Software request (register write)
• Transfer mode
- Burst transfer, step transfer, and block transfer
- Addressing mode: 32-bit addressing
(increment/decrement/fixed: the address increment/decrement range is fixed to ± 1, 2, and 4)
- Data types: Byte, halfword, and word length
- Selectable from single-shot or reload
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13.1 Overview of DMAC (DMA Controller)
MB91461
■ Overview of the DMAC Registers
Figure 13.1-1 lists the overview of the DMAC registers.
Figure 13.1-1 Overview of DMAC Registers
ch.0 control/status register A
DMACA0
bit 31
000200H
ch.0 control/status register B
DMACB0
000204H
ch.1 control/status register A
DMACA1
000208H
ch.1 control/status register B
DMACB1
00020CH
ch.2 control/status register A
DMACA2
000210H
ch.2 control/status register B
DMACB2
000214H
ch.3 control/status register A
DMACA3
000218H
ch.3 control/status register B
DMACB3
00021CH
ch.4 control/status register A
DMACA4
000220H
ch.4 control/status register B
DMACB4
000224H
All-channel control register
DMACR
000240H
24
bit 31
DMASA0
001000H
ch.0 transfer destination address setting register DMADA0
001004H
ch.1 transfer source address setting register
DMASA1
001008H
ch.1 transfer destination address setting register DMADA1
00100CH
ch.2 transfer source address setting register
DMASA2
001010H
ch.2 transfer destination address setting register DMADA2
001014H
ch.3 transfer source address setting register
DMASA3
001018H
ch.3 transfer destination address setting register DMADA3
00101CH
ch.4 transfer source address setting register
DMASA4
001020H
ch.4 transfer destination address setting register DMADA4
001024H
ch.0 transfer source address setting register
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16
20
19
15
8
7
0
0
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13.1 Overview of DMAC (DMA Controller)
MB91461
■ Block Diagram of DMAC
Figure 13.1-2 shows the block diagram of the DMAC.
Figure 13.1-2 Block Diagram of DMAC
Write back
Counter
DMA transfer request
to bus controller
Buffer
Selector
DTC 2-stage register DTCR
DMA
activation factor
select circuit
&
request
reception control
Peripheral activation request/stop input
External pin activation request/stop input
Counter
DSS[2:0]
Priority level
circuit
Buffer
TYPE.MOD,WS
Peripheral interrupt clear
MCLREQ
DDN register
DSAD 2-stage register
SADM,SASZ[7:0]
X-bus
Status
transition
circuit
Bus control section
Selector
Selector
IRQ[4:0]
SADR
Write back
Selector
Counter buffer
Counter buffer
Address
290
BLK register
DMA controller
Access
To interrupt controller
ERIE,EDIE
Selector
Read/write
control
DDN
Address counter
To bus
controller
Bus control section
Read
Write
DDAD 2-stage register
DADM,DASZ[7:0] DADR
Write back
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
13.2
Detailed Explanation of the DMAC (DMA Controller)
Registers
This section explains details of each register of DMAC.
■ Notes on Setting Registers
Some bits in the DMAC may only be set when the DMA is stopped. If set during operation (transfer),
correct operation cannot be guaranteed.
An asterisk (*) indicates bits that will affect operation if set during DMAC transfer. Rewrite this bit while
DMAC transfer is stopped (in a state where activation is disabled or the transfer is temporarily stopped).
Values set while DMA transfer activation is disabled (DMACR:DMAE=0 or DMACA:DENB=0) become
valid when DMA activation is enabled.
Values set while DMA transfer is temporarily stopped (DMACR:DMAH[3:0] ≠ 0000B or DMACA:
PAUS=1) become valid when the temporary stop is cancelled.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
13.2.1
MB91461
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status
Registers A
DMACA0 to DMACA4 are registers that control the operation of each channel of DMAC.
Each register is set independently for each channel.
■ Bit Function of DMACA0 to DMACA4
Figure 13.2-1 shows the bit function of DMACA0 to DMACA4.
Figure 13.2-1 Bit Function of DMACA0 to DMACA4
bit
31
30
29
28
27
DENB PAUS STRG
bit
15
14
13
26
25
24
23
IS [4 : 0]
11
11
10
22
21
20
19
Reserved
9
8
7
6
5
18
17
16
BLK [3 : 0]
4
3
2
1
0
DTC [15 : 0]
(Initial value: 00000000H)
[bit31] DENB (Dma ENaBle): DMA operation enable bit
This bit enables or disables DMA transfer activation for each transfer channel.
Once a channel is enabled, DMA transfer starts when a generated transfer request is accepted. All
transfer requests that are generated for a channel where the activation is disabled become invalid.
When the specified number of transfers on an activated channel has been completed, this bit is set to "0"
and the transfer stops.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0"
write) only after temporarily stopping DMA using the PAUS bit [bit30: DMACA]. If the transfer is
forced to stop without temporarily stopping DMA, DMA stops but the transferred data cannot be
guaranteed. Check whether DMA is stopped using the DSS[2:0] bits (bit18 to bit16: DMACB).
Table 13.2-1 DMA Operation Enable Bit
DENB
Function
0
DMA operation is disabled on the corresponding channel. [Initial value]
1
DMA operation is enabled on the corresponding channel.
• At a reset or when a stop request is accepted: Initialized to "0".
• Read/write is enabled.
If the operation of all channels is disabled by bit31: DMAE bit of the DMAC all-channel control
register DMACR, writing "1" to this bit is disabled and the stopped state is maintained. If the operation
is disabled by the above bit while the operation is enabled by this bit, this bit becomes "0" and the
transfer is stopped (forced stop).
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
[bit30] PAUS (PAUSe): Temporary stop instruction
This bit controls temporary stop of DMA transfer for the corresponding channel. If this bit is set, DMA
transfer is not performed until this bit is cleared. (While DMA is stopped, DSS bits become 1XXB).
If this bit is set before DMA activation and then DMA is activated, DMA remains paused.
New transfer requests that occur while this bit is set are accepted, but no transfer starts until this bit is
cleared (See "13.3.10 Transfer Request Acceptance and Transfer").
Table 13.2-2 Temporary Stop Instruction
PAUS
Function
0
DMA operation is enabled on the corresponding channel. [Initial value]
1
DMA operation is temporarily stopped on the corresponding channel.
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit29] STRG (Software TRiGger): Transfer request
This bit generates a DMA transfer request for the corresponding channel. Writing "1" to this bit
generates a transfer request after writing to the register is completed, and the transfer on the
corresponding channel is started. However, if the corresponding channel is not activated, writing to this
bit is ignored.
Table 13.2-3 Transfer Request Bit
STRG
Function
0
Invalid [Initial value]
1
DMA activation request
• At a reset: Initialized to "0".
• Read value is always "0".
• Only write value "1" is valid, and "0" has no effect on the operation.
Note:
If a transfer request is set by this bit transfer is activated by writing the DMAE bit, the transfer
request is valid and transfer starts. If this bit is written at the same time as the PAUS bit is writing as
"1", the transfer request is valid but DMA transfer does not start until the PAUS bit is cleared to "0".
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
[bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer factor selection
These bits select the factor of a transfer request as shown below. However, the software transfer request
triggered by the STRG bit function remains valid regardless of this setting.
Table 13.2-4 Transfer Factor Selection
IS
(Input Source)
Function
Transfer stop
request
00000B
Software transfer request only
00001B
to
01101B
Setting disabled
01110B
External pin (DREQ) "H" level or ↑ edge
01111B
External pin (DREQ) "L" level or ↓ edge
10000B
External interrupt 0
−
10001B
External interrupt 1
−
10010B
External interrupt 2
−
10011B
External interrupt 3
−
10100B
Reload timer 0
−
10101B
Reload timer 1
−
10110B
LIN-UART0 RX (Reception completed)
10111B
LIN-UART0 TX (Transmission completed)
11000B
LIN-UART1 RX (Reception completed)
11001B
LIN-UART1 TX (Transmission completed)
11010B
LIN-UART4 RX (Reception completed)
11011B
LIN-UART4 TX (Transmission completed)
11100B
LIN-UART5 RX (Reception completed)
11101B
LIN-UART5 TX (Transmission completed)
−
11110B
A/D converter
−
11111B
PPG0
−
−
Yes
−
Yes
−
Yes
−
Yes
• At a reset: Initialized to 00000B.
• Read/write is enabled.
If DMA activation by peripheral function interrupt is set (IS=1XXXXB), disable interrupts of the
selected function with the ICR register. When the DMA transfer is activated by the software transfer
request while the DMA activation by the interrupt of the peripheral function is set, the factor is cleared
to the corresponding peripherals after transfer ends. Therefore, since there is a possibility of clearing an
original transfer request, do not start by the software transfer request when the DMA transfer by the
interrupt of the peripheral function is set.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
[bit23 to bit20] Reserved: Reserved bits
Read value is fixed to 0000B. Writing to these bits is invalid.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification
These bits specify the size for block transfer for the corresponding channel. The value specified by
these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the
data width setting).
Be sure to set 01H (size 1) when not performing block transfer.
Table 13.2-5 Block Size Specification
BLK
XXXXB
Function
Block size specified for the corresponding channel
• At a reset: Initialized to 0000B.
• Read/write is enabled.
• If "0" is specified for all bits, the block size becomes 16 words.
• Reading always returns the block size (reload value).
[bit15 to bit00] DTC15 to DTC0 (Dma Terminal Count register)*: Transfer count register
This register stores the number of transfers performed. Each register consists of 16-bit length.
All registers have a dedicated reload register. When using it on channels that allow the transfer count
register to be reloaded, the initial setting value is automatically returned to the register when the transfer
completes.
Table 13.2-6 Transfer Count Register
DTC
XXXXH
Function
Transfer number specified for the corresponding channel
When DMA transfer starts, the data in this register is stored in the counter buffer in the dedicated DMA
transfer counter and the value is counted -1 (decremented) by one after each transfer. When DMA
transfer completes, the value of the counter buffer is written back to this register and the DMA
operation ends. Thus, the transfer number specification value cannot be read during DMA operation.
• At a reset: Initialized to 0000H.
• Read/write is enabled. For DTC access, be sure to use halfword length or word length access.
• Reading the register returns the counter value. The reload value cannot be read.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
13.2.2
MB91461
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status
Registers B
DMACB0 to DMACB4 are registers that control the operation of each channel of DMAC.
Each register is set independently for each channel.
■ Bit Function of DMACB0 to DMACB4
Figure 13.2-2 shows the bit function of DMACB0 to DMACB4.
Figure 13.2-2 Bit Function of DMACB0 to DMACB4
bit
31
30
29
28
TYPE [1 : 0] MOD [1 : 0]
bit
15
14
13
11
27
26
25
24
23
22
21
20
19
18
WS [1 : 0] SADM DADM DTCR SADR DADR ERIE EDIE
11
10
9
8
7
6
5
SASZ [7 : 0]
4
3
17
16
DSS [2 : 0]
2
1
0
DASZ [7 : 0]
(Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXXB)
[bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer type setting
These bits specify the operation type of the corresponding channel as described below.
2-cycle transfer mode:
This mode sets the transfer source address (DMASA) and transfer destination address (DMADA) and
performs a transfer by repeating the read operation and write operation for the number of times
specified by the transfer count.
Table 13.2-7 Transfer Type Setting
TYPE
Function
00B
2-cycle transfer [Initial value]
01B
Setting disabled
10B
Setting disabled
11B
Setting disabled
• At a reset: Initialized to 00B.
• Read/write is enabled.
• Always set these bits to 00B.
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MB91461
[bit29, bit28] MOD1, MOD0 (MODe)*: Transfer mode setting
These bits set the operating mode of the correspondence channel as follows.
Table 13.2-8 Transfer Mode Setting
MOD
Function
00B
Block/step transfer mode [Initial value]
01B
Burst transfer mode
10B
Setting disabled
11B
Setting disabled
• At a reset: Initialized to 00B.
• Read/write is enabled.
[bit27, bit26] WS1, WS0 (Word Size): Transfer data width selection
These bits select the transfer data width for the corresponding channel. The specified number of
transfers is performed in units of the data width specified in this register.
Table 13.2-9 Transfer Data Width Selection
WS
Function
00B
BYTE unit transfer [Initial value]
01B
HALF-WORD unit transfer
10B
WORD width unit transfer
11B
Setting disabled
• At a reset: Initialized to 00B.
• Read/write is enabled.
[bit25] SADM (Source-ADdr, count-Mode select)*:
Transfer source address count mode specification
This bit specifies the address process for each transfer of the transfer source address for the
corresponding channel.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer source address count width (SASZ). When the transfer is completed,
the next access address is written to the corresponding address register (DMASA).
As a result, the transfer source address register is not updated until DMA transfer is completed.
To fix the address, set this bit to "0" or "1", and set the address count widths (SASZ and DASZ) to "0".
Table 13.2-10 Transfer Source Address Count Mode Specification
SADM
Function
0
Transfer source address is incremented. [Initial value]
1
Transfer source address is decremented.
• At a reset: Initialized to "0".
• Read/write is enabled.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
[bit24] DADM (Destination-ADdr, Count-Mode select)*:
Transfer destination address count mode specification
This bit specifies the address process for each transfer of the transfer destination address for the
corresponding channel.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer destination address count width (DASZ). When the transfer is
completed, the next access address is written to the corresponding address register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is completed.
To fix the address, set this bit to "0" or "1", and set the address count widths (SASZ and DASZ) to "0".
Table 13.2-11 Transfer Destination Address Count Mode Specification
DADM
Function
0
Transfer destination address is incremented. [Initial value]
1
Transfer destination address is decremented.
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit23] DTCR (DTC-reg, Reload)*: Transfer count register reload specification
This bit controls the reload function for the transfer count register in the corresponding channel.
If reloading operation is enabled by this bit, the count register value is restored to its initial value after
transfer is completed, then DMAC stops and enters the wait state for a new transfer request (activation
request by STRG or IS setting). (If this bit is "1", DENB bit is not cleared.)
Transfer is forcibly stopped when DENB=0 or DMAE=0 is set.
If reload operation of the transfer counter is disabled, a single-shot operation that stops when transfer is
completed is performed even if reloading is specified in the address register. In this case, the DENB bit
is cleared.
Table 13.2-12 Transfer Count Register Reload Specification
DTCR
Function
0
Transfer count register reloading is disabled. [Initial value]
1
Transfer count register reloading is enabled.
• At a reset: Initialized to "0".
• Read/write is enabled.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
MB91461
[bit22] SADR (Source-ADdr.-reg, Reload)*: Transfer source address register reload specification
This bit controls the reload function for the transfer source address register in the corresponding
channel.
When reloading operation is enabled by this bit, the transfer source address register value is restored to
its initial value after transfer is completed.
If reload operation of the transfer counter is disabled, a single-shot operation that stops when transfer is
completed is performed even if reloading is specified in the address register. In this case, the address
register value stops at a state that the initial value is reloaded.
When this bit disables reloading, the value of the address register when transfer is completed is the next
access address of the last address (that is, if incrementing is specified, the incremented address).
Table 13.2-13 Transfer Source Address Register Reload Specification
SADR
Function
0
Transfer source address register reloading is disabled. [Initial value]
1
Transfer source address register reloading is enabled.
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit21] DADR (Dest.-ADdr.-reg, Reload)*: Transfer destination address register reload specification
This bit controls the reload function for the transfer destination address register in the corresponding
channel.
When reloading is enabled by this bit, the transfer destination address register value is restored to its
initial value after transfer is completed.
The details of other functions are the same as those described for bit22:SADR.
Table 13.2-14 Transfer Destination Address Register Reload Specification
DADR
Function
0
Transfer destination address register reloading is disabled. [Initial value]
1
Transfer destination address register reloading is enabled.
• At a reset: Initialized to "0".
• Read/write is enabled.
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MB91461
[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable
This bit controls the generation of an interrupt for termination when an error occurs. The content of the
error is indicated in DSS2 to DSS0. Note that an interrupt occurs only for specific termination factors
and not for all termination factors. (Refer to description of bits DSS2 to DSS0.)
Table 13.2-15 Error Interrupt Output Enable
ERIE
Function
0
Error interrupt request output is disabled. [Initial value]
1
Error interrupt request output is enabled.
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable
This bit controls the generation of an interrupt when transfer ends normally.
Table 13.2-16 End Interrupt Output Enable
EDIE
Function
0
End interrupt request output is disabled. [Initial value]
1
End interrupt request output is enabled.
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer stop factor indication
These bits indicate a code (exit code) of 3 bits that indicates the factor of stopping or termination of
DMA transfer on the corresponding channel.
The exit codes are as follows.
Table 13.2-17 Transfer Stop Factor Indication
DSS
000B
Function
Initial value
X01B
Interrupt
generation
None
-
None
X10B
Transfer stop request
Error
X11B
Normal end
End
1XXB
DMA temporary stop (by DMAH bit, PAUS bit, and interrupts, etc.)
None
The transfer stop request is only set when a request from a peripheral circuit is used.
The "interrupt generation" column indicates the type of interrupt requests that can be generated.
• At a reset: Initialized to 000B.
• Writing 000B clears these bits.
• Although read/write is enabled, only writing 000B is valid.
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[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*: Transfer source address count size
specification
These bits specify increment/decrement width for each transfer of each transfer source address
(DMASA) for the corresponding channel. The value set by these bits becomes the address increment/
decrement width for each transfer unit. The address increment/decrement width is complied with the
specification of the transfer source address count mode (SADM).
Table 13.2-18 Transfer Source Address Count Size Specification
SASZ
Function
00H
Address fixed
01H
Byte unit transfer
02H
Halfword unit transfer
04H
Word unit transfer
Others
Setting disabled
• At a reset: Initialized to 00000000B.
• Read/write is enabled.
• If setting other than a fixed address, be sure to set the same transfer unit as the transfer data width
(WS).
[bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*: Transfer destination address count size
specification
These bits specify increment/decrement width for each transfer of each transfer destination address
(DMADA) for the corresponding channel. The value set by these bits becomes the address increment/
decrement width for each transfer unit. The address increment/decrement width is complied with the
specification of the transfer destination address count mode (DADM).
Table 13.2-19 Transfer Destination Address Count Size Specification
DASZ
Function
00H
Address fixed
01H
Byte unit transfer
02H
Halfword unit transfer
04H
Word unit transfer
Others
Setting disabled
• At a reset: Initialized to 00000000B.
• Read/write is enabled.
• If setting other than a fixed address, be sure to set the same transfer unit as the transfer data width
(WS).
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
13.2.3
MB91461
DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/
Transfer Destination Address Setting Registers
DMASA0 to DMASA4 / DMADA0 to DMADA4 are registers that control the operation of
each channel of DMAC. Each register is set independently for each channel.
■ Bit Configuration of DMASA0 to DMASA4 / DMADA0 to DMADA4
Each bit function of DMASA0 to DMASA4 / DMADA0 to DMADA4 is indicated as follows.
Figure 13.2-3 Bit Function of DMASA0 to DMASA4 / DMADA0 to DMADA4
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DMASA [31 : 16]
bit
15
14
13
11
11
10
9
8
7
DMASA [15 : 0]
(Initial value: XXXXXXXXH)
bit
31
30
29
28
27
26
25
24
23
DMADA [31 : 16]
bit
15
14
13
11
11
10
9
8
7
DMADA [15 : 0]
(Initial value: 00000000H)
These registers store the transfer source and destination addresses. These are composed of 32-bit length.
[bit31 to bit0] DMASA31 to DMASA0 (DMA Source Addr)*: Transfer source address setting
These bits set the transfer source address.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
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[bit31 to bit0] DMADA31 to DMADA0 (DMA Destination Addr)*: Transfer destination address setting
These bits set the transfer destination address.
When the DMA transfer is activated, the data of this register is stored in the counter buffer of a
dedicated DMA address counter and address count is performed for each transfer based on the setting.
When the DMA transfer is completed, the contents of the counter buffer are written back to this register
and then DMA ends. Thus, the address counter value cannot be read during DMA operation.
All registers have a dedicated reload register. When used on channels for which reloading the transfer
source and destination address registers is enabled, the register is automatically reloaded with its initial
value when transfer completes. In this case, other address registers are not affected.
• At a reset: Initialized to 00000000H.
• Read/write is enabled. Be sure to access to this register with 32-bit data.
• During transfer, reading returns the previous address value before transfer starts. After transfer
completes, reading returns the next access address value. The reload value cannot be read. Therefore,
the transfer address cannot be read in real time.
• Set "0" for a nonexistent upper bit.
Note:
Do not set DMAC’s own registers in this register. Performing DMA transfer to DMAC’s own registers
is not allowed.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
13.2.4
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DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC All-Channel
Control Register
DMACR controls the operation of all the five DMAC channels. Be sure to access to this
register using byte length.
■ Bit Configuration of DMACR
Figure 13.2-4 shows the bit function of DMACR.
Figure 13.2-4 Bit Function of DMACR
bit
bit
31
30
29
28
DMAE
27
26
25
−
−
PM01
15
14
13
11
11
10
9
−
−
−
−
−
−
−
24
23
22
21
20
19
18
17
16
−
−
−
−
−
−
−
−
8
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
DMAH [3 : 0]
(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXB)
[bit31] DMAE (DMA Enable): DMA operation enable
This bit controls operation for all DMA channels.
If DMA operation is disabled by this bit, transfer operations on all channels are disabled regardless of
the start/stop settings for each channel and the operating status. Any requests on channels where transfer
is in progress are cancelled and transfer stops at the block boundary. In a disabled state, all activation
operations to each channel are ignored.
If this bit enables DMA operation, start/stop operations are enabled for all channels. Enabling DMA
operation by this bit itself does not start transfer for each channel.
DMA operation can be forced to stop by writing "0" to this bit. However, be sure to use forced stop ("0"
write) only after temporarily stopping DMA using the DMAH[3:0] bits (bit27 to bit24: DMACR). If
forced stopping is carried out without temporarily stopping DMA, DMA stops but the transfer data
cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits (bit18 to bit16:
DMACB).
Table 13.2-20 DMA Operation Enable
DMAE
Function
0
DMA operation is disabled on all channels. [Initial value]
1
DMA operation is enabled on all channels.
• At a reset: Initialized to "0".
• Read/write is enabled.
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13.2 Detailed Explanation of the DMAC (DMA Controller) Registers
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[bit28] PM01 (Priority Mode ch.0, ch.1 robin): Channel priority rotation
This bit is set to switch priority for each transfer between ch.0 and ch.1.
Table 13.2-21 Channel Priority Rotation
PM01
Function
0
Priority is fixed. (ch.0 > ch.1) [Initial value]
1
Priority is switched. (ch.1 > ch.0)
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit27 to bit24] DMAH3 to DMAH0 (DMA Halt): DMA temporary stop
These bits stop temporarily DAM transfer for all DMA channels. Setting these bits stops DMA transfer
on all channels until the bits are cleared again.
If these bits are set before enabling DMA, all channels remain paused.
Any transfer requests that occur for channels where DMA transfer is enabled (DENB=1) while these
bits are set are valid but transfer does not start until the bits are cleared.
Table 13.2-22 DMA Temporary Stop
DMAH
Function
DMA operation is enabled on all channels. [Initial value]
0000B
DMA is temporarily stopped.
Other than 0000B
• At a reset: Initialized to "0".
• Read/write is enabled.
[bit30, bit29, bit23 to bit0] −: Reserved bits
Read value is undefined.
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13.3 Explanation of the DMAC (DMA Controller) Operation
13.3
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Explanation of the DMAC (DMA Controller) Operation
This section explains the operational overview, details of the transfer request setting,
transfer sequence and operation of DMAC.
■ Overview of the DMAC
This block built into FR family devices is a multi-functional DMA controller and controls data transfer at
high speed without using CPU instruction operations.
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13.3 Explanation of the DMAC (DMA Controller) Operation
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13.3.1
Operational Overview of DMAC (DMA Controller)
This section explains the operational overview of DAMC.
■ Main Operations of DMAC
The operation of each function can be set independently for each transfer channel.
After each channel is enabled, the channel does not actually start transfer until the specified transfer request
is detected.
On detecting a transfer request, the DMAC outputs a DMA transfer request to the bus controller and starts
transfer on receiving bus access rights from the bus controller. The transfer is carried out based on a
sequence of the mode settings set independently for each channel.
■ Transfer Mode
Each DMA channel performs transfer operation according to the transfer mode set by the MOD[1:0] bits of
its DMACB register.
● Block/step transfer
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops
requesting the bus controller for transfer until the next transfer request is accepted.
One block transfer unit: Specified block size (DMACA:BLK[3:0]).
● Burst transfer
With one transfer request, the transfer continues until the specified number of transfers is completed.
Specified number of transfers: Block size × transfer count (DMACA:BLK[3:0] ×
DMACA:DTC[15:0])
■ Transfer Type
● 2-cycle transfer (Normal transfer)
The DMA controller operates a read operation and a write operation as one unit of operation.
The DMAC reads the data from the address in the transfer source register and then writes it to the address
in the transfer destination register.
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■ Transfer Address
The following types of addressing are available and can be set independently for each channel transfer
source and transfer destination.
● Specifying the address for 2-cycle transfer
The value read from a register (DMASA, DMADA) in which an address has been set in advance is used as
the address for access.
After accepting a transfer request, DMA stores the address from the register in the temporary storage buffer
and then starts transfer.
After each transfer (access), the address counter is used to generate the next access address (incremented,
decremented, or fixed can be selected) and this new address is returned to the temporary storage buffer. The
contents of the temporary storage buffer are written back to the register (DMASA, DMADA) after each
block transfer unit is completed.
Therefore, the address register (DMASA, DMADA) value is updated only by each block transfer unit, and
so the address during transfer cannot be read in real time.
■ Number of Transfers and End of Transfer
● Number of transfers
The transfer count register is decremented (-1) after transfer of each block completes. When the transfer
count register reaches "0" indicating that the specified number of transfers have been performed, the
DMAC displays the exit code and then stops or restarts.
Like the address registers, the transfer count register is only updated after each block is transferred.
If reloading the transfer count register is disabled, transfer ends. If enabled, the register is initialized with
its initial value and the DMAC enters a wait state for transfer (DMACB:DTCR).
● End of transfer
Factors for the transfer end are shown below. When transfer ends, a factor is indicated as the exit code
(DMACB:DSS[2:0]).
• End of the specified transfer number (DMACA:BLK[3:0] × DMACA:DTC[15:0]) → Normal end
• A transfer stop request is generated from a peripheral circuit → Error
• An address error is generated → Error
• A reset is generated → Reset
A transfer stop factor indication (DSS) is displayed and a transfer end interrupt/error interrupt can be
generated for each end factor.
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13.3.2
Transfer Request Setting
Explanation of the DMAC (DMA Controller) Operation
The following two types of transfer requests can be used to start DMA transfer.
• Built-in peripheral request
• Software request
Software requests can always be used regardless of the settings of other requests.
■ Internal Peripheral Request
The transfer request is generated by an interrupt from a built-in peripheral circuit.
For each channel, set which peripheral interrupt is used to generate a transfer request (DMACA:IS[4:0]=1XXXXB).
This request and an external transfer request cannot be used at the same time.
Note:
Because an interrupt request used in a transfer request can be seen as an interrupt request to the
CPU, disable interrupts in the interrupt controller setting (ICR register).
■ Software Request
Writing to the trigger bit in the register generates the transfer request (DMACA:STRG).
This request can be used independently from the above transfer request at any time.
If a software request occurs concurrently with activation (enabling transfer), a DMA transfer request is
outputted to the bus controller immediately and then transfer starts.
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13.3.3
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Transfer Sequence
The transfer type and the transfer mode that determine the operation sequence after DMA
transfer activation can be set independently for each channel (DMACB:TYPE[1:0] and
MOD[1:0] settings).
■ Selecting Transfer Sequence
The following sequences can be selected by register settings:
• Burst 2-cycle transfer
• Block/step 2-cycle transfer
■ Burst 2-cycle Transfer
The specified number of transfers is performed for each transfer factor. For a 2-cycle transfer, 32-bit area
can be specified for a transfer source/transfer destination address.
A peripheral transfer request or a software transfer request can be specified as a transfer factor.
Table 13.3-1 lists the specifiable transfer address for burst 2-cycle transfer.
Table 13.3-1 Specifiable Transfer Address for Burst 2-Cycle Transfer
Transfer source address
specification
Direction
Transfer destination address
specification
All 32-bit areas specifiable
→
All 32-bit areas specifiable
[Characteristics of burst transfer]
• Each time a transfer request is received, transfer continues until the transfer count register reaches
"0". The number of transfers is the block size × the number of transfers (DMACA:BLK[3:0] ×
DMACA:DTC[15:0]).
• If a transfer request is generated once again during a transfer, the request is ignored.
• When the reload function is enabled for the transfer count register, a subsequent transfer request is
accepted after transfer completes.
• If a transfer request for another channel with a higher priority is received during transfer, the channel
is switched at the boundary of the block transfer unit and it will not be returned until the transfer
request for the channel is cleared.
Figure 13.3-1shows the example of burst transfer.
Figure 13.3-1 Example of Burst Transfer
Transfer request ↑ (edge)
Bus operation
Transfer number
CPU
SA
DA
4
SA
DA
3
SA
DA
2
SA
DA
1
CPU
0
Transfer end
(Example of burst transfer with external pin rising edge activation,
block number=1, and transfer number=4)
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■ Step/Block Transfer 2-cycle Transfer
For a step/block transfer (transfer for each transfer request is performed as many times as the specified
block count), 32-bit area can be specified as the transfer source/transfer destination address.
Table 13.3-2 shows the specifiable transfer addresses for step/block transfer 2-cycle transfer.
Table 13.3-2 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer
Transfer source address specification
Direction
Transfer destination address
specification
All 32-bit areas specifiable
→
All 32-bit areas specifiable
■ Step Transfer
If "1" is set for the block size, a step transfer sequence is selected.
[Characteristics of step transfer]
• If a transfer request is received, the transfer request is cleared after one transfer operation and then the
transfer is stopped. (The DMA transfer request to the bus controller is canceled.)
• If a transfer request is generated once again during a transfer, the request is ignored.
• If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched after the transfer is stopped and then restarted. For step transfer, priority is only meaningful for
the case when transfer requests are generated simultaneously.
■ Block Transfer
If a value other than "1" is specified for the block size, a block transfer sequence is selected.
[Characteristics of block transfer]
Except that each transfer consists of multiple transfer cycles (specified by the number of blocks), the
operation is the same as for step transfer. Figure 13.3-2 shows the example of block transfer.
Figure 13.3-2 Example of Block Transfer
Transfer request ↑ (edge)
Bus operation
Block number
Transfer number
CPU
SA
DA
SA
2
DA
1
CPU
SA
0
2
DA
SA
DA
1
2
1
Transfer end
(Example of block transfer with external pin rising edge activation, block number=2, and transfer number=2)
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13.3 Explanation of the DMAC (DMA Controller) Operation
13.3.4
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DMA Transfer in General
This section explains the DMA transfer operation.
■ Block Size
The unit of transfer data is the collection of data of as many as the number set in the block size setting
register (× data width).
Since the data to be transferred in one transfer cycle is fixed to the value specified by the data width, one
transfer unit consists of the number of transfer cycles for the specified block size.
During a transfer, if a transfer request with higher priority is accepted or if a transfer temporary stop request
is generated, the transfer stops only at the transfer unit boundary whether or not the transfer is a block
transfer. Although this prevents data in the data block from undesirable splitting or temporary stopping, it
may cause the response to be slower if the block size is large.
Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be
guaranteed.
■ Reload Operation
In this module, the following three types of reload function are available to be set for each channel:
(1) Transfer count register reload function
After transfer is performed the specified number of times, the initial value is set in the transfer count
register again and waiting for an activation request.
Use this setting to perform any of the transfer sequences repeatedly.
If reloading is not enabled, the count register remains at "0" after the specified number of transfers is
completed and no further transfers are performed.
(2) Transfer source address register reload function
After transfer is performed the specified number of times, the initial value is set in the transfer
source address register again.
Use this setting if repeatedly performing a transfer from a fixed area in the transfer source address
area.
If reloading is not enabled, after the specified number of transfers is completed, the value in the
transfer source address register becomes the next address. Use this setting if the address area is not
fixed.
(3) Transfer destination address register reload function
After transfer is performed the specified number of times, the initial value is set in the transfer
destination address register again.
Use this setting if repeatedly performing a transfer to a fixed area in the transfer destination address
area.
(Other features are the same as (2).)
Enabling the reload functions for transfer source and destination address registers by itself does not cause
transfer to restart after the specified number of transfers is completed. It only causes the address registers to
be reloaded with their initial values.
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[Special case of operation mode and reload operation]
When a transfer is executed in the continuous transfer mode by external pin input level detection, if a
reload function of the transfer count register is used, the transfer is continued by reloading without
stopping even if the transfer is completed while input is continued.
If you want to stop the transfer at the end of transfer and restart it from the input detection, do not set a
reload setting.
When using burst, block, or step transfer modes, transfer is suspended once after the reload is
performed at the end of the transfer operation, and no further transfer is performed until a new transfer
request input is detected.
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13.3 Explanation of the DMAC (DMA Controller) Operation
13.3.5
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Addressing Mode
The transfer destination address and transfer source address are specified
independently for each transfer channel.
The specification method is explained below. Use transfer sequence to specify
addresses.
■ Address Register Specification
In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register
(DMASA) and the transfer destination address in the transfer destination address setting register
(DMADA).
[Features of the address register]
32-bit length register
[Function of the address register]
• The registers are read each time an access is performed and outputted to the address bus.
• The address counter is used to calculate the address for the next access at the same time and the
address register is updated by the address of the result of this calculation.
• The address calculation is selected from either incrementing or decrementing calculation
independently for each channel, transfer source, and transfer destination. The width of the address
increment or decrement is specified by the address count size specification register values (DMACB:
SASZ, DASZ).
• When the reload function is not enabled for an address register, address of the result of the address
calculation remains in the register after the transfer ends.
• If the reload function is enabled, the initial value of the address is reloaded.
Reference:
If an overflow or underflow occurs as a result of 32-bit length address calculation, the result is
detected as an address error and a transfer on the corresponding channel is stopped. (Refer to
"Table 13.2-17").
Notes:
• Do not set addresses of DMAC’s own registers in the address registers.
• Do not transfer to DMAC’s own registers by the DMAC.
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13.3.6
Data Types
13.3 Explanation of the DMAC (DMA Controller) Operation
Select the data length (data width) to be transferred in one transfer operation from the
following:
• Byte
• Halfword
• Word
■ Access Address
Since the word boundary specification is also observed in DMA transfer, different low-order bits are
ignored if an address with a different data length is specified for the transfer destination/transfer source
address.
• Word:
The actual access address is a 4-byte length starting with 00B in the lowest 2 bits.
• Halfword:
The actual access address is a 2-byte length starting with "0" in the lowest 1 bit.
• Byte:
The actual access address and the addressing are the same.
If the lowest-order bits in the transfer source address and transfer destination address are different, the
addresses as set are outputted on the internal address bus. However, each transfer target on the bus is
accessed after the addresses are corrected according to the above rules.
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13.3 Explanation of the DMAC (DMA Controller) Operation
13.3.7
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Transfer Number Control
The transfer number is specified within the range of the maximum 16-bit length (1 to
65536 times). Set the number of transfers in the transfer count register (DMACA:DTC).
■ Transfer Count Register and Reload Operation
The register value is stored in a temporary storage buffer when transfer starts, and is decremented by the
transfer counter. When the counter value becomes "0", it is detected as the end of transfer for the specified
count, and the transfer on the channel is stopped or waiting for a restart request (when reload is specified).
[Features of transfer count registers]
• Each register has 16-bit length.
• Each register has a dedicated reload register.
• Setting the register value to "0" results in transfer being performed 65536 times.
[Reload operation]
• Register has a reload function and the reload function is valid only if it is enabled.
• The initial value of the count register is saved in the reload register when transfer is activated.
• Once the count of the transfer counter reaches to "0", a signal indicating transfer completion is
outputted as well as the initial value is read from the reload register and written to the count register.
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13.3 Explanation of the DMAC (DMA Controller) Operation
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13.3.8
CPU Control
When a DMA transfer request is accepted, DMA issues a transfer request to the bus
controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus
operation and DMA transfer starts.
■ DMA Transfer and Interrupts
During DMA transfer, if an NMI request or an interrupt request with a higher level than the hold suppress
level set by the HRCL register of the interrupt controller occurs, DMAC temporarily cancels the transfer
request to the bus controller at a transfer unit boundary (one block) and temporarily stops the transfer until
the interrupt request is cleared. In the meantime, the transfer request is retained internally. After the
interrupt request is cleared, DMAC issues a transfer request to the bus controller again to acquire the right
to use the bus and then restarts DMA transfer.
If an interrupt level is lower than the level set by the HRCL register, interrupt requests are not accepted
until DMA transfer ends. If a DMA transfer request is generated during an interrupt processing with a
lower level than the level of the HRCL setting value, the transfer request is accepted and the interrupt
processing operation is stopped until the transfer ends.
In the default setting, DMA transfer request level is set to the lowest level, in which the transfer is stopped
for all the interrupt requests and the interrupt processing is prioritized.
■ DMA Suppression
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device
interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as
there are any interrupt requests. When all interrupt factors are cleared, the suppression feature no longer
works and the DMA transfer is restarted by the interrupt processing routine.
Thus, if you want to suppress restart of DMA transfer after clearing interrupt factors in the interrupt factor
processing routine at a level that interrupts DMA transfer, use the DMA suppression function.
The DMA suppression function is activated by writing a non-zero value to the DMAH[3:0] bits in the
DMA all-channel control register and is stopped by setting the bits to "0".
This function is mainly used in the interrupt processing routines. Before the interrupt factors are cleared in
an interrupt processing routine, the content of DMA suppression register is incremented by 1. By doing
this, no DMA transfer will not be performed from then on.
After interrupt processing, the contents of DMAH[3:0] bits is decremented by 1 before returning.
If multiple interrupts have occurred, DMA transfer continues to be suppressed since the contents of
DMAH[3:0] bits do not become "0" yet. If a single interrupt has occurred, the contents of DMAH[3:0] bits
become "0" and so the DMA requests are then enabled immediately.
Note:
• Since the register has only four bits, this function cannot be used for multiple interrupts exceeding
15 levels.
• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than
other interrupt levels.
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13.3 Explanation of the DMAC (DMA Controller) Operation
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Starting Operation
Starting of DMA transfer is controlled independently for each channel, but before
transfer starts, the operation of all channels needs to be enabled.
■ Enabling Operations for All Channels
Before activated in each DMAC channel, operation for all channels needs to be enabled in advance with the
DMA operation enable bit (DMACR:DMAE).
All start settings and transfer requests that occurred before operation is enabled become invalid.
■ Starting Transfer
The transfer operation can be started by the operation enable bit of the control register for each channel. If a
transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified
mode.
■ Starting from Temporary Stop State
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary
stop state is maintained even though the transfer operation is started. If transfer requests occur in this
period, they are accepted and retained.
A transfer is started from the point where a temporary stop is cancelled.
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13.3.10 Transfer Request Acceptance and Transfer
This section explains the acceptance of transfer request and the contents of transfer.
■ Transfer Request Acceptance and the Transfer
Sampling for transfer requests set for each channel starts after starting.
When activation of peripheral interrupts is selected, the DMAC continues the transfer operation until the
transfer request is cleared. If it is cleared, the transfer is stopped in each transfer unit (activation of
peripheral interrupts).
Since peripheral interrupts are handled as level detections, the interrupt needs to be generated using
interrupt clear by DMA.
Transfer requests are always accepted while requests for other channels are being accepted and the transfer
is being performed. The channel that will be used for transfer is determined for each transfer unit by
checking the priority.
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Clearing Peripheral Interrupts by DMA
This DMA has a function that clears peripheral interrupts. This function works when
peripheral interrupt is selected as the DMA activation factor (when IS[4:0]= 1XXXXB).
Peripheral interrupts are cleared only for the set activation factors. That is, only the
peripheral functions set by IS[4:0] are cleared.
■ Timing for Clearing an Interrupt by DMA
The timing for clearing an interrupt depends on the transfer mode. (See section "13.4 Operational Flow of
DMAC (DMA Controller)").
[Block/step transfer]
If block transfer is selected, a clear signal is generated after one block (step) transfer.
[Burst transfer]
If burst transfer is selected, a clear signal is generated after transfer is performed the specified number
of times.
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13.3.12 Temporary Stop
13.3 Explanation of the DMAC (DMA Controller) Operation
This section explains the case when the DMA transfer stops temporarily.
■ Setting of Temporary Stop by Writing to the Control Register
(Set Independently for Each Channel or All Channels Simultaneously)
If temporary stop is set using a temporary stop bit, transfer on the corresponding channel is stopped until
cancellation setting of the temporary stop is set again. Temporary stop can be checked by DSS bits.
Transfer is restarted when temporary stop is canceled.
■ NMI/Hold Suppression Level Interrupt Processing
If an NMI request or an interrupt request with a higher level than the hold suppression level occurs, all
channels on which transfer is in progress are temporarily stopped at the boundary of the transfer unit and
the bus right is opened to give priority to NMI/interrupt processing. Transfer requests accepted during
NMI/interrupt processing are retained, and wait for the completion of NMI processing.
Channels for which requests are retained restart transfer after NMI/interrupt processing is completed.
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Operation End/Stop
The end of DMA transfer is controlled independently for each channel. It is also possible
to disable operation for all channels at once.
■ End of Transfer
If reload operation is disabled, transfer is stopped after the transfer count register becomes "0", then
"Normal end" is displayed as the exit code, and all subsequent transfer requests are disabled.
(DMACA:DENB bit is cleared.)
If reload operation is enabled, the initial value is reloaded after the transfer count register becomes "0", then
"Normal end" is displayed as the exit code, and the state enters a wait state for transfer requests once again.
(DMACA:DENB bit is not cleared.)
■ Disabling All Channels
If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC
operations, including operations on active channels, are stopped. Then, even if the operation of all channels
is enabled again, no transfer is performed unless each channel is restarted individually. In this case, no
interrupt occurs.
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13.3 Explanation of the DMAC (DMA Controller) Operation
MB91461
13.3.14 Error Stop
In addition to normal end by the completion of transfer for the number of times
specified, stopping by various types of errors and forced stopping are provided.
■ Transfer Stop Requests from Peripheral Circuits
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an
error is detected (Example: Error when data is received at or sent from a communications system
peripheral).
The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the exit code
and stops the transfer on the corresponding channel.
■ Occurrence of an Address Error
If an inappropriate addressing is executed in each addressing mode, an address error is detected (An
"inappropriate addressing" is, for example, "a case if an overflow or underflow occurs in the address
counter when a 32-bit address is specified").
If an address error is detected, "Address error occurs" is displayed as the exit code and the transfer on the
corresponding channel is stopped.
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.3 Explanation of the DMAC (DMA Controller) Operation
13.3.15
MB91461
DMAC Interrupt Control
DMAC interrupt control can output interrupts for each DMAC channel independently
from peripheral interrupts that become transfer requests.
■ Interrupts That DMAC Interrupt Control can Output
• Transfer end interrupt:
Occurs only when operation ends normally.
• Error interrupt:
Transfer stop request from peripheral circuit (error due to a peripheral)
Occurrence of address error (error due to software)
All of these interrupts are outputted according to the content of the exit code.
An interrupt request can be cleared by writing 000B to DSS2 to DSS0 (exit code) of DMACS.
Be sure to clear the exit code by writing 000B before restarting.
If reload operation is enabled, the transfer is automatically restarted. At this point, however, the exit code is
not cleared and is retained until a new exit code is written when the next transfer ends.
Since only one end factor can be displayed in an exit code, the result after evaluating the priority is
displayed when multiple factors occur simultaneously. The interrupt that occurs at this point complies with
the displayed exit code.
The following shows the priority in order of descending priority for displaying exit codes:
• Reset
• Clearing by writing 000B
• Peripheral stop request
• Normal end
• Stopping by detecting address error
• Channel selection and control
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.3 Explanation of the DMAC (DMA Controller) Operation
MB91461
13.3.16 DMA Transfer during Sleep Mode
The DMAC can also operate in sleep mode.
This section explains the DMA transfer in a sleep state.
■ Notes on DMA Transfer in Sleep Mode
If DMA transfer during a sleep mode, ensure the following points:
• Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before the device enters
sleep mode.
• The sleep mode is cancelled by an interrupt. Thus, if a peripheral interrupt is selected as a DMAC
activation factor, interrupts must be disabled by the interrupt controller.
Similarly, if you do not want to cancel the sleep mode by a DMAC end interrupt, disable DMAC end
interrupts.
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.3 Explanation of the DMAC (DMA Controller) Operation
13.3.17
MB91461
Channel Selection and Control
Up to five channels can be simultaneously set as transfer channels.
In general, an independent function can be set for each channel.
■ Priority Among Channels
Since DMA transfer is allowed only in one channel at a time, priority must be set for the channels. Two
modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group
(Refer to "■ Channel Group").
● Fixed mode
The priority is fixed by channel number in ascending order.
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is accepted during a transfer, the transfer channel is switched to
the channel with the higher priority when the transfer for the transfer unit (number set in the block size
specification register × data width) ends.
When higher priority transfer is completed, transfer is restarted on the previous channel.
Figure 13.3-3 shows the DMA transfer in fixed mode.
Figure 13.3-3 DMA Transfer in Fixed Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
CPU
SA
Transfer channel
DA
SA
ch.1
DA
SA
ch.0
DA
SA
ch.0
DA
CPU
ch.1
ch.0 transfer end
ch.1 transfer end
● Rotation mode (between ch.0 and ch.1 only)
The initial state after operation is enabled is set to the same order as fixed mode, but the priorities of the
channels are reversed at the end of each transfer operation. Thus, if more than one transfer request is
outputted at the same time, the channel is switched per each transfer unit.
This mode is effective when continuous/burst transfer is set.
Figure 13.3-4 shows the DMA transfer operation in rotation mode.
Figure 13.3-4 DMA Transfer in Rotation Mode
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer channel
CPU
SA
DA
ch.1
SA
DA
ch.0
SA
DA
ch.1
SA
DA
CPU
ch.0
ch.0 transfer end
ch.1 transfer end
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.3 Explanation of the DMAC (DMA Controller) Operation
MB91461
■ Channel Group
Set the selection of priority as the unit explained in the table below.
Table 13.3-3 shows the DMA priority selection setting.
Table 13.3-3 DMA Priority Selection Setting
CM71-10159-2E
Mode
Priority
Remarks
Fixed
ch.0 > ch.1
−
Rotation
ch.0 > ch.1
↑↓
ch.0 < ch.1
The initial state is shown in the upper row.
If transfer occurs in the state of the upper row, the
priority is inverted.
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.4 Operational Flow of DMAC (DMA Controller)
13.4
MB91461
Operational Flow of DMAC (DMA Controller)
Figure 13.4-1 and Figure 13.4-2 show operational flows of DMA transfer.
■ Operational Flow of Block Transfer
Figure 13.4-1 Block Transfer
DMA stop
DENB=>0
DENB=1
Activation
request wait
Reload enabled
Activation request
Initial address, transfer number,
block number loading
Transfer source address
access address calculation
Access is executed only once
when accessing by fly-by.
Transfer destination address
access address calculation
BLK=0
Only when peripheral interrupt
activation factor is selected.
Address, transfer number,
block number writing back
Interrupt clear is generated.
Interrupt clear
DTC=0
DMA transfer end
DMA interrupt is generated.
Block transfer
• Activation is enabled by all activation factors (select).
• Access is enabled to all areas.
• Block number is settable.
• Interrupt clear is issued after the completion of block number.
• DMA interrupt is issued after the completion of specified transfer number.
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.4 Operational Flow of DMAC (DMA Controller)
MB91461
■ Operational Flow of Burst Transfer
Figure 13.4-2 Burst Transfer
DMA stop
DENB=>0
DENB=1
Reload enabled
Activation
request wait
Initial address, transfer number,
block number loading
Transfer source address
access address calculation
Access is executed only once
when accessing by fly-by.
Transfer destination address
access address calculation
BLK=0
DTC=0
Address, transfer number,
block number writing back
Only when peripheral interrupt
activation factor is selected.
Interrupt clear
Interrupt clear is generated.
DMA transfer end
DMA interrupt is generated.
Burst transfer
• Activation is enabled by all activation factors (select).
• Access is enabled to all areas.
• Block number is settable.
• DMA interrupt is issued after the completion of specified transfer number.
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.5 Data Path of DMAC (DMA Controller)
13.5
MB91461
Data Path of DMAC (DMA Controller)
This section shows data paths for each transfer.
■ Data Paths During 2-cycle Transfer
Figure 13.5-1 to Figure 13.5-6 show data paths during 2-cycle transfer.
Figure 13.5-1 External Area → External Area Transfer
External Area ⇒ External Area Transfer
CPU
I-bus
X-bus
Bus controller
D-bus
DMAC
Write cycle
I-bus
Data buffer
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
Read cycle
MB91xxx
CPU
DMAC
External bus I/F
MB91xxx
F-bus
I/O
RAM
I/O
Figure 13.5-2 External Area → Internal RAM Area Transfer
Read cycle
CPU
I-bus
X-bus
Bus controller
D-bus
Data buffer
MB91xxx
DMAC
Write cycle
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
330
External bus I/F
DMAC
CPU
MB91xxx
External bus I/F
External Area ⇒ Internal RAM Area Transfer
F-bus
I/O
FUJITSU MICROELECTRONICS LIMITED
RAM
I/O
CM71-10159-2E
CHAPTER 13 DMAC (DMA CONTROLLER)
13.5 Data Path of DMAC (DMA Controller)
MB91461
Figure 13.5-3 External Area → Built-in I/O Area Transfer
Read cycle
CPU
I-bus
X-bus
Bus controller
D-bus
MB91xxx
DMAC
Write cycle
I-bus
Data buffer
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
DMAC
CPU
MB91xxx
External bus I/F
External Area ⇒ Built-in I/O Area Transfer
F-bus
RAM
I/O
I/O
Figure 13.5-4 Built-in I/O Area → Built-in RAM Area Transfer
Read cycle
CPU
I-bus
X-bus
Bus controller
D-bus
Data buffer
MB91xxx
DMAC
Write cycle
I-bus
X-bus
Bus controller
D-bus
F-bus
RAM
CM71-10159-2E
External bus I/F
DMAC
CPU
MB91xxx
External bus I/F
Built-in I/O Area ⇒ Built-in RAM Area Transfer
F-bus
I/O
FUJITSU MICROELECTRONICS LIMITED
RAM
I/O
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CHAPTER 13 DMAC (DMA CONTROLLER)
13.5 Data Path of DMAC (DMA Controller)
MB91461
Figure 13.5-5 Internal RAM Area → External Area Transfer
Read cycle
CPU
I-bus
X-bus
Bus controller
Data buffer
D-bus
MB91xxx
DMAC
Write cycle
I-bus
X-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
External bus I/F
DMAC
CPU
MB91xxx
External bus I/F
Internal RAM Area ⇒ External Area Transfer
F-bus
RAM
I/O
I/O
Figure 13.5-6 Internal RAM Area → Built-in I/O Area Transfer
Read cycle
X-bus
CPU
I-bus
Bus controller
D-bus
Data buffer
MB91xxx
DMAC
Write cycle
X-bus
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
332
I/O
FUJITSU MICROELECTRONICS LIMITED
External bus I/F
DMAC
CPU
MB91xxx
External bus I/F
Internal RAM Area ⇒ Built-in I/O Area Transfer
F-bus
RAM
I/O
CM71-10159-2E
CHAPTER 14
CAN CONTROLLER
This chapter describes the functions and operations of
the CAN controller.
14.1 Features of CAN
14.2 CAN Block Diagram
14.3 CAN Registers
14.4 CAN Register Functions
14.5 CAN Controller Functions
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CHAPTER 14 CAN CONTROLLER
14.1 Features of CAN
14.1
MB91461
Features of CAN
CAN conforms to the CAN Protocol Version 2.0A/B, which is a standard protocol for
serial communication. It is widely used in industrial fields including automobile and
factory automation.
■ Features of CAN
CAN has the following features:
• Support for the CAN Protocol Version 2.0A/B
• Support for bit rates up to 1 Mbps
• Identification mask for each message object
• Support for the programmable FIFO mode
• Maskable interrupt
• Support for the programmable loop-back mode for self test operation
• Reading/writing from/to the message buffer through the interface register
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CHAPTER 14 CAN CONTROLLER
14.2 CAN Block Diagram
MB91461
14.2
CAN Block Diagram
Figure 14.2-1 shows the CAN block diagram.
Figure 14.2-1 CAN Block Diagram
CAN_TX CAN_RX
C_CAN
Message handler
CAN controller
Message RAM
Register group
Interrupt
DataOUT
DataIN
Address[7:0]
Control
Reset
Clock
CPU interface
■ CAN Controller
Controls the serial register for serial/parallel conversion used for transferring the CAN protocol and
transmission/reception messages.
■ Message RAM
Stores message objects.
■ Register Group
All registers used in CAN.
■ Message Handler
Controls the message RAM and CAN controller.
■ CPU Interface
Controls the interface of the FR family internal bus.
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CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
14.3
MB91461
CAN Registers
CAN has the following registers:
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler expansion register (BRPE)
• IFx command request register (IFxCREQ)
• IFx command mask register (IFxCMSK)
• IFx mask registers 1, 2 (IFxMSK1, IFxMSK2)
• IFx arbitration registers 1, 2 (IFxARB1, IFxARB2)
• IFx message control register (IFxMCTR)
• IFx data registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
• CAN transmission request registers 1, 2 (TREQR1, TREQR2)
• CAN New Data registers 1, 2 (NEWDT1, NEWDT2)
• CAN interrupt pending registers 1, 2 (INTPND1, INTPND2)
• CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2)
• CAN clock prescaler register (CANPRE)
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CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
MB91461
■ List of the General Control Registers
Table 14.3-1 List of General Control Registers
Register
Address
Comment
+0
+1
CAN control register
Base-addr + 00H
Initial value
Initial value
Initial value
CAN status register
bit7 to bit0
bit15 to bit8
bit7 to bit0
Reserved
CTRLR
Reserved
STATR
00000000B
00000001B
00000000B
00000000B
CAN bit timing register
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
RP, REC[6:0]
TEC[7:0]
TSeg2[2:0],
TSeg1[3:0]
SJW[1:0],
BRP[5:0]
00000000B
00000000B
00100011B
00000001B
CAN interrupt register
Base-addr + 08H
+3
bit15 to bit8
CAN error counter
Base-addr + 04H
+2
CAN test register
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
IntId15 to IntId8
IntId7 to IntId0
Reserved
TESTR
00000000B
00000000B
00000000B
00000000B
r0000000B
CAN prescaler expansion register
Base-addr + 0CH
Initial value
CM71-10159-2E
Reserved
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Reserved
BRP3 to BRP0
Reserved
Reserved
00000000B
00000000B
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
−
The error counter is read
only.
The bit timing register is
set to be writable by
setting CCE.
The interrupt register
is read only.
The test register is set
to be usable by setting
TSET.
Value "r" in TESTR
indicates the value of
the CAN_RX pin.
The prescaler
expansion register is
set to be writable by
setting CCE.
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CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
MB91461
■ List of the Message Interface Registers
Table 14.3-2 List of Message Interface Registers (1 / 2)
Register
Address
Comment
+0
+1
IF1 command request register
Base-addr + 10H
Initial value
Initial value
Initial value
IF1 command mask register
bit7 to bit0
bit15 to bit8
bit7 to bit0
BUSY
Mess. No. 5 to 0
Reserved
IF1CMSK
00000000B
00000001B
00000000B
00000000B
bit7 to bit0
bit15 to bit8
bit7 to bit0
MXtd. MDir,
Msk28 to Msk24
Msk23 to Msk16
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
11111111B
11111111B
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MsgVal, Xtd, Dir,
ID28 to ID24
ID23 to ID16
ID15 to ID8
ID7 to ID0
00000000B
00000000B
00000000B
00000000B
Base-addr + 20H
Initial value
bit7 to bit0
bit15 to bit8
bit7 to bit0
IF1MCTR
IF1MCTR
Reserved
Reserved
00000000B
00000000B
00000000B
00000000B
Base-addr + 24H
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[0]
Data[1]
Data[2]
Data[3]
00000000B
00000000B
00000000B
00000000B
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[4]
Data[5]
Data[6]
Data[7]
00000000B
00000000B
00000000B
00000000B
Initial value
338
IF1 data register A1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[3]
Data[2]
Data[1]
Data[0]
00000000B
00000000B
00000000B
00000000B
IF1 data register B2
Base-addr + 34H
IF1 data register B2
bit7 to bit0
IF1 data register A2
Base-addr + 30H
IF1 data register A2
bit7 to bit0
IF1 data register B1
−
Reserved
bit15 to bit8
IF1 data register A1
−
IF1 arbitration register 1
IF1 message control register
Base-addr + 1CH
−
IF1 mask register 1
bit15 to bit8
IF1 arbitration register 2
Base-addr + 18H
+3
bit15 to bit8
IF1 mask register 2
Base-addr + 14H
+2
IF1 data register B1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[7]
Data[6]
Data[5]
Data[4]
00000000B
00000000B
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
−
Big endian byte
Big endian byte
Little endian byte
Little endian byte
CM71-10159-2E
CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
MB91461
Table 14.3-2 List of Message Interface Registers (2 / 2)
Register
Address
Comment
+0
+1
IF2 command request register
Base-addr + 40H
Initial value
Initial value
Initial value
IF2 command mask register
bit7 to bit0
bit15 to bit8
bit7 to bit0
BUSY
Mess. No. 5 to 0
Reserved
IF2CMSK
00000000B
00000001B
00000000B
00000000B
bit7 to bit0
bit15 to bit8
bit7 to bit0
MXtd. MDir,
Msk28 to Msk24
Msk23 to Msk16
Msk15 to Msk8
Msk7 to Msk0
11111111B
11111111B
11111111B
11111111B
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
IF2MCTR
IF2MCTR
Reserved
Reserved
00000000B
00000000B
00000000B
00000000B
Base-addr + 50H
Initial value
bit7 to bit0
bit15 to bit8
bit7 to bit0
IF2MCTR
IF2MCTR
Reserved
Reserved
00000000B
00000000B
00000000B
00000000B
Base-addr + 54H
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[0]
Data[1]
Data[2]
Data[3]
00000000B
00000000B
00000000B
00000000B
Initial value
bit15 to bit8
bit7 to bit0
bit15 to bit8
Data[4]
Data[5]
Data[6]
Data[7]
00000000B
00000000B
00000000B
00000000B
Initial value
CM71-10159-2E
IF2 data register A1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[3]
Data[2]
Data[1]
Data[0]
00000000B
00000000B
00000000B
00000000B
IF2 data register B2
Base-addr + 64H
IF2 data register B2
bit7 to bit0
IF2 data register A2
Base-addr + 60H
IF2 data register A2
bit7 to bit0
IF2 data register B1
−
Reserved
bit15 to bit8
IF2 data register A1
−
IF2 arbitration register 1
IF2 message control register
Base-addr + 4CH
−
IF2 mask register 1
bit15 to bit8
IF2 arbitration register 2
Base-addr + 48H
+3
bit15 to bit8
IF2 mask register 2
Base-addr + 44H
+2
IF2 data register B1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
Data[7]
Data[6]
Data[5]
Data[4]
00000000B
00000000B
00000000B
00000000B
FUJITSU MICROELECTRONICS LIMITED
−
Big endian byte
Big endian byte
Little endian byte
Little endian byte
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CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
MB91461
■ List of the Message Handler Registers
Table 14.3-3 List of Message Handler Registers
Register
Address
Comment
+0
+1
CAN transmission request register 2
Base-addr + 80H
Initial value
Base-addr + 84H
Base-addr + 88H
Base-addr + 8CH
Initial value
Base-addr + 94H
Base-addr + 98H
Base-addr + 9CH
Base-addr + A0H
Initial value
Base-addr + A4H
Base-addr + A8H
Base-addr + ACH
Initial value
Base-addr + B4H
Base-addr + B8H
Base-addr + BCH
340
CAN transmission request register 1
bit7 to bit0
bit15 to bit8
bit7 to bit0
TxRqst32 to
TxRqst25
TxRqst24 to
TxRqst17
TxRqst16 to
TxRqst9
TxRqst8 to
TxRqst1
00000000B
00000000B
00000000B
00000000B
Reserved (used when the number of message buffers is 32 or more)
CAN data update register 1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
NewDat32 to
NewDat25
NewDat24 to
NewDat17
NewDat16 to
NewDat9
NewDat8 to
NewDat1
00000000B
00000000B
00000000B
00000000B
Reserved (used when the number of message buffers is 33 or more)
CAN interrupt pending register 2
CAN interrupt pending register 1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
IntPnd32 to
IntPnd25
IntPnd24 to
IntPnd17
IntPnd16 to
IntPnd9
IntPnd8 to
IntPnd1
00000000B
00000000B
00000000B
00000000B
Reserved (used when the number of message buffers is 65 or more)
CAN message validation register 2
Base-addr +B0H
+3
bit15 to bit8
CAN data update register 2
Base-addr + 90H
+2
CAN message validation register 1
bit15 to bit8
bit7 to bit0
bit15 to bit8
bit7 to bit0
MsgVal32 to
MsgVal25
MsgVal24 to
MsgVal17
MsgVal16 to
MsgVal9
MsgVal8 to
MsgVal1
00000000B
00000000B
00000000B
00000000B
Reserved (used when the number of message buffers is 33 or more)
FUJITSU MICROELECTRONICS LIMITED
The transmission
request register is
read only.
−
The data update
register is read
only.
−
The interrupt
pending register is
read only.
−
The message
validation register
is read only.
−
CM71-10159-2E
CHAPTER 14 CAN CONTROLLER
14.3 CAN Registers
MB91461
■ Clock Prescaler Register
Table 14.3-4 Clock Prescaler Register
Register
Address
0004C0H
Initial value
CM71-10159-2E
Comment
+0
+1
+2
+3
CAN prescaler
register
−
−
−
bit3 to bit0
−
−
−
CANPRE[3:0]
−
−
−
00000000B
−
−
−
FUJITSU MICROELECTRONICS LIMITED
CAN prescaler
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CHAPTER 14 CAN CONTROLLER
14.4 CAN Register Functions
14.4
MB91461
CAN Register Functions
Address space of 256 bytes (64 words) is assigned to the CAN registers. The CPU
accesses to the message RAM via the message interface register.
This section lists the CAN registers and their detailed functions.
■ General Control Registers
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler expansion register (BRPER)
■ Message Interface Registers
• IFx command request register (IFxCREQ)
• IFx command mask register (IFxCMSK)
• IFx mask registers 1, 2 (IFxMSK1, IFxMSK2)
• IFx arbitration registers 1, 2 (IFxARB1, IFxARB2)
• IFx message control register (IFxMCTR)
• IFx data registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
■ Message Handler Registers
• CAN transmission request registers 1, 2 (TREQR1, TREQR2)
• CAN data update registers 1, 2 (NEWDT1, NEWDT2)
• CAN interrupt pending registers 1, 2 (INTPND1, INTPND2)
• CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2)
■ Prescaler Register
CAN clock prescaler register (CANPRE)
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CM71-10159-2E
CHAPTER 14 CAN CONTROLLER
MB91461
14.4.1
General Control Register
14.4 CAN Register Functions
The general control registers control the CAN protocol and operation mode, and provide
status information.
■ General Control Registers
• CAN control register (CTRLR)
• CAN status register (STATR)
• CAN error counter (ERRCNT)
• CAN bit timing register (BTR)
• CAN interrupt register (INTR)
• CAN test register (TESTR)
• CAN prescaler expansion register (BRPER)
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14.4 CAN Register Functions
14.4.1.1
MB91461
CAN Control Register (CTRLR)
The CAN control register (CTRLR) controls the operation mode of the CAN controller.
■ Register Configuration
Figure 14.4-1 Bit Configuration of CAN Control Register (CTRLR)
CAN control register (High-order byte)
bit
Address: Base+00H
Read/Write →
Initial value →
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
CAN control register (Low-order byte)
bit
Address: Base+01H
Read/Write →
Initial value →
7
6
5
4
3
2
1
0
Test
R/W
0
CCE
R/W
0
DAR
R/W
0
Reserved
EIE
R/W
0
SIE
R/W
0
IE
R/W
0
Init
R/W
0
R/W
0
■ Register Functions
[bit15 to bit8] Reserved: Reserved bits
00000000B is read from these bits.
To write a value to these bits, set 00000000B.
[bit7] Test: Test mode enable bit
Table 14.4-1 Test Mode Enable Bit
Test
Function
0
Normal operation [Initial value]
1
Test mode
[bit6] CCE: Bit timing register writing enable bit
Table 14.4-2 Bit Timing Register Writing Enable Bit
CCE
344
Function
0
Disables writing to the CAN bit timing register and CAN prescaler expansion register. [Initial value]
1
Enables writing to the CAN bit timing register and CAN prescaler expansion
register. This setting is valid when the Init bit is "1".
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14.4 CAN Register Functions
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[bit5] DAR: Automatic re-transmission disable bit
Table 14.4-3 Automatic Re-transmission Disable Bit
DAR
Function
0
Enables automatic re-transmission of a message when arbitration is lost or
an error is detected. [Initial value]
1
Disables automatic re-transmission of a message.
Based on the CAN specification (Refer to "ISO11898, 6.3.3 Recovery Management"), the CAN
controller automatically re-transmits a frame when arbitration is lost or an error is detected during
transmission. To enable the automatic re-transmission, reset the DAR bit to "0". To operate CAN in the
Time Triggered CAN (TTCAN, refer to "ISO11898-1") environment, you need to set the DAR bit to
"1".
In the mode where the DAR bit is set to "1", the operations of the TxRqst and NewDat bits in the
message object change as follows (For the message object, refer to "14.4.3 Message Object".):
• When frame transmission starts, the TxRqst bit in the message object is reset to "0", whereas the
NewDat bit remains to be set.
• When frame transmission finishes successfully, NewDat is reset to "0".
• When an arbitration loss or an error is found in the transmission, NewDat remains to be set. To
resume transmission, you need to set TxRqst to "1" from the CPU.
[bit4] Reserved: Reserved bit
"0" is read from this bit.
To write a value to this bit, set "0".
[bit3] EIE: Error interrupt code enable bit
Table 14.4-4 Error Interrupt Code Enable Bit
CM71-10159-2E
EIE
Function
0
Disables the setting of the interrupt code to the CAN interrupt register
according to the change in the BOff or EWarn bit in the CAN status register.
[Initial value]
1
Enables the setting of the status interrupt code to the CAN interrupt register
according to the change in the BOff or EWarn bit in the CAN status register.
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[bit2] SIE: Status interrupt code enable bit
Table 14.4-5 Status Interrupt Code Enable Bit
SIE
Function
0
Disables the setting of the interrupt code to the CAN interrupt register
according to the change in the TxOk, RxOk, or LEC bit in the CAN status
register. [Initial value]
1
Enables the setting of the status interrupt code to the CAN interrupt register
according to the change in the TxOk, RxOk, or LEC bit in the CAN status
register.
The change in the TxOk, RxOk, or LEC bit which occurred due to the writing from the CPU is not set in the CAN interrupt register.
[bit1] IE: Interrupt enable bit
Table 14.4-6 Interrupt Enable Bit
IE
Function
0
Disables the occurrence of an interrupt. [Initial value]
1
Enables the occurrence of an interrupt.
[bit0] Init: Initialization bit
Table 14.4-7 Initialization Bit
Init
Function
0
Enables the operation of the CAN controller.
1
Perform initialization. [Initial value]
• The bus-off recovery sequence (Refer to "CAN specification Rev. 2.0".) cannot be shortened by
setting/canceling the Init bit. When the device is set to bus-off, the CAN controller itself sets the Init
bit to "1" to stop all the bus operations. When the Init bit is cleared to "0" in the bus-off status, the
bus operation will be stopped until bus idle occurs 129 times continuously (11-bit recessive is
counted as one.). The error counter will be reset after the execution of the bus-off recovery sequence.
• Start writing to the CAN bit timing register after setting the Init and CCE bits to "1".
• Before changing to the low-power consumption mode (stop mode or clock mode), write "1" to the
INIT bit to initialize the CAN controller.
• To use the CAN prescaler to change the division ratio of the clock which is provided to the CAN
interface (CAN clock), set the INIT bit to "1" before changing the setting of the CAN prescaler
register.
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14.4 CAN Register Functions
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14.4.1.2
CAN Status Register (STATR)
The CAN status register (STATR) indicates the CAN status and CAN bus status.
■ Register Configuration
Figure 14.4-2 Bit Configuration of CAN Status Register (STATR)
CAN status register (High-order byte)
bit
Address: Base+02H
Read/Write →
Initial value →
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
6
5
4
3
2
1
0
RxOk
R/W
0
TxOk
R/W
0
R/W
0
LEC
R/W
0
R/W
0
CAN status register (Low-order byte)
bit
Address: Base+03H
Read/Write →
Initial value →
7
BOff
R
0
EWarn EPass
R
R
0
0
■ Register Functions
[bit15 to bit8] Reserved: Reserved bits
"0" is read from these bits.
To write a value to this bit, set "0".
[bit7] BOff: Bus-off bit
Table 14.4-8 Bus-off Bit
BOff
Function
0
The CAN controller is not in the bus-off status (Bus Active). [Initial value]
1
The CAN controller is in the bus-off status.
[bit6] EWarn: Warning bit
Table 14.4-9 Warning Bit
EWarn
CM71-10159-2E
Function
0
Both the transmission and reception counters show a value lower than 96.
[Initial value]
1
Either the transmission or reception counter shows a value 96 or higher.
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[bit5] EPass: Error passive bit
Table 14.4-10 Error Passive Bit
EPass
Function
0
Both the transmission and reception counters show a value lower than 128
(Error Active status). [Initial value]
1
The reception counter shows RP bit=1, and the transmission counter shows a
value 128 or higher (Error Passive status).
[bit4] RxOk: Message reception OK bit
Table 14.4-11 Message Reception OK Bit
RxOk
Function
0
The message reception is abnormal or in a bus idle status. [Initial value]
1
The message reception is normal.
[bit3] TxOk: Message transmission OK bit
Table 14.4-12 Message Transmission OK Bit
TxOk
Function
0
The message transmission is abnormal or in a bus idle status. [Initial value]
1
The message transmission is normal.
Note:
The RxOk and TxOk bits can be reset by the CPU only.
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[bit2 to bit0] LEC: Last error code bit
Table 14.4-13 Last Error Code Bit
LEC
000B
001B
010B
011B
Status
Normal
Indicates that the message is transmitted or received
normally. [Initial value]
Stuff error
Indicates that dominant or recessive was detected in the
message for 6 bits or more consecutively.
Form error
Indicates that the fixed format section of the reception frame
was received in error.
Ack error
Indicates that the transmission message was not
acknowledged by other nodes.
Bit1 error
Indicates that dominant was detected in the transmission data
of a message other than the arbitration field even after
recessive was transmitted.
Bit0 error
Indicates that recessive was detected in the transmission data
of a message even after dominant was transmitted. During the
bus recovery, this bit is set every time 11-bit recessive is
detected. Reading this bit allows monitoring of the bus
recovery sequence.
CRC error
Indicates that the CRC data in the received message did not
match with the calculation result of the CRC data.
Undetected
When the read value of the LEC bit is "111B" after writing
"111B" to the LEC bit from the CPU, it indicates that no
transmission/reception was made during the period. (Bus Idle
status)
100B
101B
110B
111B
Function
The LEC bit retains the code which indicates the last error occurred on the CAN bus. When the transfer
of a message (reception/transmission) is complete without an error, this bit is set to 000B. The
undetected code 111B should be set by the CPU in order to check code updating.
• The status interrupt code (8000H) is set to the CAN interrupt register when the BOff or EWarn bit
changes while the EIE bit is "1", or when one of the RxOk, TxOk, and LEC bits changes while the
SIE bit is "1".
• Since the RxOk and TxOk bits are updated by writing to the CPU, the RxOK and TxOK bits set by
the CAN controller are not retained. To use the RxOk and TxOk bits, clear them within (45 × BT)
hours after either of RxOk or TxOk bit is set to "1". "BT" represents one bit time.
• When the SIE bit is set to "1" and an interrupt occurs due to the change of the LEC bit, do not write
a value to the CAN status register.
• Such interrupt will not occur due to the change of the EPass bit or the writing by the CPU to the
RxOk, TxOk, or LEC bit.
• Even when the BOff bit or EPass bit is set to "1", the EWarn bit is set to "1".
• Reading this register clears the status interrupt code (8000H) of the CAN interrupt register.
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14.4.1.3
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CAN Error Counter (ERRCNT)
The CAN error counter (ERRCNT) shows the reception error passive display as well as
the reception and transmission error counters.
■ Register Configuration
Figure 14.4-3 Bit Configuration of CAN Error Counter (ERRCNT)
CAN error counter register (High-order byte)
bit
15
14
13
12
11
10
9
8
Address: Base+04H
Read/Write →
Initial value →
RP
R
0
R
0
R
0
REC6 to REC0
R
R
R
0
0
0
R
0
R
0
4
2
1
0
R
0
R
0
R
0
CAN error counter register (Low-order byte)
bit
Address: Base+05H
Read/Write →
Initial value →
7
R
0
6
R
0
5
R
0
3
TEC7 to TEC0
R
R
0
0
■ Register Functions
[bit15] RP: Reception error passive display
Table 14.4-14 Reception Error Passive Display
RP
Function
0
The reception error counter is not in the error passive status of the CAN
specification. [Initial value]
1
The reception error counter is in the error passive status of the CAN
specification.
[bit14 to bit8] REC6 to REC0: Reception error counter
The value of the reception error counter. The range of the value is 0 to 127.
[bit7 to bit0] TEC7 to TEC0: Transmission error counter
The value of the transmission error counter. The range of the value is 0 to 255.
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14.4 CAN Register Functions
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14.4.1.4
CAN Bit Timing Register (BTR)
The CAN bit timing register (BTR) sets the prescaler and bit timing.
■ Register Configuration
Figure 14.4-4 Bit Configuration of CAN Bit Timing Register (BTR)
CAN bit timing register (High-order byte)
bit
Address: Base+06H
Read/Write →
Initial value →
15
14
13
12
11
10
R/W
0
TSeg2
R/W
1
R/W
0
R
0
5
4
3
Reserved
R
0
9
8
R
0
R
1
R
1
2
1
0
R/W
0
R/W
1
TSeg1
CAN bit timing register (Low-order byte)
bit
Address: Base+07H
Read/Write →
Initial value →
7
6
SJW
R/W
R/W
0
0
R/W
0
R/W
0
BRP
R/W
R/W
0
0
The CAN bit timing register and CAN prescaler expansion register must be set while the CCE and Init bits
in the CAN control register are set to "1".
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■ Register Functions
[bit15] Reserved: Reserved bit
"0" is read from this bit.
To write a value to this bit, set "0".
[bit14 to bit12] TSeg2: Time segment 2 setting bit
The valid setting values are 0 to 7. The value of TSeg2+1 will be time segment 2.
Time segment 2 corresponds to the phase buffer segment (PHASE_SEG2) of the CAN specification.
[bit11 to bit8] TSeg1: Time segment 1 setting bit
The valid setting values are 1 to 15. Setting "0" is prohibited. The value of TSeg1+1 will be time
segment 1.
Time segment 1 corresponds to the propagation segment (PROP_SEG) + phase buffer segment 1
(PHASE_SEG1) of the CAN specification.
[bit7, bit6] SJW: Resynchronization jump width setting bit
The valid setting values are 0 to 3. The value of SJW+1 will be the resynchronization jump width.
[bit5 to bit0] BRP: Baud rate prescaler setting bit
The valid setting values are 0 to 63. The value of BRP+1 will be the baud rate prescaler.
The frequency of the CAN clock (fsys) is divided to determine the basic unit hour (tq) of the CAN
controller.
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14.4 CAN Register Functions
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14.4.1.5
CAN Interrupt Register (INTR)
The CAN interrupt register (INTR) shows the message interrupt code and status
interrupt code.
■ Register Configuration
Figure 14.4-5 Bit Configuration of CAN Interrupt Register (INTR)
CAN interrupt register (High-order byte)
bit
15
14
13
Address: Base+08H
Read/Write →
Initial value →
R
0
R
0
R
0
12
11
IntId15 to IntId8
R
R
0
0
10
9
8
R
0
R
0
R
0
2
1
0
R
0
R
0
R
0
CAN interrupt register (Low-order byte)
bit
Address: Base+09H
Read/Write →
Initial value →
CM71-10159-2E
7
R
0
6
R
0
5
R
0
4
3
IntId7 to IntId0
R
R
0
0
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■ Register Functions
Table 14.4-15 Functions of CAN Interrupt Register (INTR)
IntId
Function
0000H
No interrupt
0001H to 0020H
Message interrupt code
(The interrupt factor is the message object No.)
0021H to 7FFFH
Not used
8000H
Status interrupt code
(Interrupt by the change of the CAN status register.)
8001H to FFFFH
Not used
When two or more interrupt codes are pending, the CAN interrupt register indicates the interrupt code of
the highest priority. Even if an interrupt code has been set to the CAN interrupt register, when an interrupt
code of higher priority is generated, the CAN interrupt register is updated to the interrupt code of higher
priority.
The interrupt code of the highest priority is the status interrupt code (8000H), followed by the message
interrupt codes (0001H, 0002H, 0003H, ... , 0020H).
When the IntId bit is set to a value other than 0000H, and the IE bit in the CAN control register is set to "1",
the interrupt signal to the CPU becomes valid. When the value of the IntId bit is set to 0000H (the interrupt
factor is reset) or the IE bit in the CAN control register is reset to "0", the interrupt signal becomes invalid.
When the IntPnd bit in the corresponding message object (For details of the message object, refer to "14.4.3
Message Object".) is cleared to "0", the message interrupt code is cleared.
The status interrupt code is cleared when the CAN status register is read.
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14.4 CAN Register Functions
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14.4.1.6
CAN Test Register (TESTR)
The CAN test register (TESR) sets the test mode and monitors the RX pin. Refer to
"14.5.7 Test Mode" for the operation.
■ Register Configuration
Figure 14.4-6 Bit Configuration of CAN Test Register (TESTR)
CAN test register (High-order byte)
bit
Address: Base+0AH
Read/Write →
Initial value →
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
1
0
CAN test register (Low-order byte)
bit
Address: Base+0BH
Read/Write →
Initial value →
7
6
5
4
3
2
Rx
R
(r)
Tx1
R/W
0
Tx0
R/W
0
LBack
R/W
0
Silent
R/W
0
Basic
R/W
0
Reserved Reserved
R
0
R
0
The initial value of the Rx in bit7 (r) shows the level on the CAN bus.
To write a value to the CAN test register (TESTR), do it after setting the Test bit in the CAN control
register (CTRLR) to "1". The test mode is enabled when the Test bit in the CAN control register is set to
"1". If the Test bit in the CAN control register is set to "0" during the test mode, the test mode is switched
to the normal mode.
■ Register Functions
[bit15 to bit8] Reserved: Reserved bits
00000000B is read from these bits.
To write a value to these bits, set 00000000B.
[bit7] Rx: Rx pin monitor bit
Table 14.4-16 Rx Pin Monitor Bit
Rx
CM71-10159-2E
Function
0
Indicates that the CAN bus is dominant.
1
Indicates that the CAN bus is recessive.
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[bit6, bit5] Tx1, Tx0: TX pin control bit
Table 14.4-17 TX Pin Control Bit
Tx1, Tx0
Function
00B
Normal operation [Initial value]
01B
A sampling point is output to the Tx pin.
10B
Dominant is output to the Tx pin.
11B
Recessive is output to the Tx pin.
If the Tx bit is set to a value other than 00B, the message cannot be transmitted.
[bit4] LBack: Loop-back mode
Table 14.4-18 Loop-back Mode
LBack
Function
0
Disables the loop-back mode. [Initial value]
1
Enables the loop-back mode.
[bit3] Silent: Silent mode
Table 14.4-19 Silent Mode
Silent
Function
0
Disables the silent mode. [Initial value]
1
Enables the silent mode.
[bit2] Basic: Basic mode
Table 14.4-20 Basic Mode
Basic
Function
0
Disables the basic mode. [Initial value]
1
Enables the basic mode.
The IF1 register is used as a transmission message, and the IF2 register is used
as a reception message.
[bit1, bit0] Reserved: Reserved bits
00B is read from these bits.
To write a value to these bits, set 00B.
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14.4 CAN Register Functions
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14.4.1.7
CAN Prescaler Expansion Register (BRPER)
When the CAN prescaler expansion register (BRPER) is combined with the prescaler
specified with the CAN bit timing register, the prescaler used by the CAN controller is
expanded.
■ Register Configuration
Figure 14.4-7 Bit Configuration of CAN Prescaler Expansion Register (BRPER)
CAN prescaler expansion register (High-order byte)
bit
Address: Base+0CH
Read/Write →
Initial value →
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
4
3
2
1
0
CAN prescaler expansion register (Low-order byte)
bit
Address: Base+0DH
Read/Write →
Initial value →
7
6
5
Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R/W
0
BRPE
R/W
R/W
0
0
R/W
0
■ Register Functions
[bit15 to bit4] Reserved: Reserved bits
000000000000B is read from these bits.
To write a value to these bits, set 000000000000B.
[bit3 to bit0] BRPE: Baud rate prescaler expansion bit
Combining BRP of the CAN bit timing register with BRPE allows the expansion of the baud rate
prescaler to 1023 at maximum.
The value of "{BRPE (MSB:4 bits), BRP (LSB:6 bits)} + 1" will be the prescaler value of the CAN
controller.
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14.4 CAN Register Functions
14.4.2
MB91461
Message Interface Register
Two sets of message interface registers are available to control the access from the
CPU to the message RAM.
There are two sets of message interface registers used to control the access from the CPU to the message
RAM. These two sets of registers avoid the conflict of the access from the CPU and CAN controller to the
message RAM by buffering the transferred (or to-be-transferred) data (message object). The message
objects are transferred simultaneously between the message interface register and the message RAM (For
details of the message objects, refer to "14.4.3 Message Object".).
Except for the basic test mode, the functions of the two sets of message interface registers are identical and
can be operated independently. For example, message interface register IF2 can be used for reading from
the message RAM, while message interface register IF1 is used for writing to the message RAM. Table
14.4-21 shows the two sets of message interface registers.
The message interface register consists of command registers (command request and command mask
registers) and message buffer register controlled by the command registers (mask, arbitration, message
control, and data registers). The command mask register indicates the direction of the data transfer and
which part of the message object is transferred. The command request register selects a message No. and
performs the operation specified with the command mask register.
Table 14.4-21 Message Interface Registers IF1 and IF2
Address
358
IF1 register set
Address
IF2 register set
Base + 10H
IF1 command request
Base + 40H
IF2 command request
Base + 12H
IF1 command mask
Base + 42H
IF2 command mask
Base + 14H
IF1 mask 2
Base + 44H
IF2 mask 2
Base + 16H
IF1 mask 1
Base + 46H
IF2 mask 1
Base + 18H
IF1 arbitration 2
Base + 48H
IF2 arbitration 2
Base + 1AH
IF1 arbitration 1
Base + 4AH
IF2 arbitration 1
Base + 1CH
IF1 message control
Base + 4CH
IF2 message control
Base + 20H
IF1 data A1
Base + 50H
IF2 data A1
Base + 22H
IF1 data A2
Base + 52H
IF2 data A2
Base + 24H
IF1 data B1
Base + 54H
IF2 data B1
Base + 26H
IF1 data B2
Base + 56H
IF2 data B2
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CHAPTER 14 CAN CONTROLLER
14.4 CAN Register Functions
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14.4.2.1
IFx Command Request Register (IFxCREQ)
The IFx command request register (IFxCREQ) selects the message No. of the message
RAM, and controls the message transfer between the message RAM and message buffer
registers. In the basic test mode, IF1 is used for transmission control, and IF2 is used for
reception control.
■ Register Configuration
Figure 14.4-8 Bit Configuration of IFx Command Request Register (IFxCREQ)
IFx command request register (High-order byte)
Address: Base+10H
bit15
14
13
Base+40H BUSY Reserved Reserved
Read/Write →
Initial value →
10
9
8
Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
IFx command request register (Low-order byte)
Address: Base+11H
bit7
6
5
Base+41H Reserved
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R
0
11
R
0
Read/Write →
Initial value →
R/W
0
12
R/W
0
R/W
0
Message Number
R/W
R/W
R/W
0
0
0
■ Register Functions
As soon as a message No. is written to the IFx command request register, message transfer starts between
the message RAM and message buffer registers (mask, arbitration, message control, and data registers).
This writing operation sets the BUSY bit to "1" to indicate the transfer is being processed. When the
transfer finishes, the BUSY bit is reset to "0".
When the CPU makes access to the message interface register while the BUSY bit is "1", the CPU is set to
wait until the BUSY bit is set to "0" (for 3- to 6-cycle period counted by the clock after the command
request register is written).
The usage of the BUSY bit is different in the basic test mode. The IF1 command request register is used as
a transmission message. When the BUSY bit is set to "1", the register directs to start message transmission.
When the message transfer finishes successfully, the BUSY bit is reset to "0". The message transfer can be
discontinued any time by resetting the BUSY bit to "0".
The IF2 command request register is used as a reception message. When the BUSY bit is set to "1", the
received message is stored into the IF2 message interface register.
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[bit15] BUSY: Busy flag bit
• In the mode other than the basic test mode
Table 14.4-22 Busy Flag Bit
BUSY
Function
0
Indicates that data transfer is not performed between the message interface
register and message RAM. [Initial value]
1
Indicates that data transfer is being performed between the message interface
register and message RAM.
• In the basic test mode
- IF1 command request register
Table 14.4-23 Busy Flag Bit
BUSY
Function
0
Disables message transmission.
1
Enables message transmission.
- IF2 command request register
Table 14.4-24 Busy Flag Bit
BUSY
Function
0
Disables message reception.
1
Enables message reception.
The BUSY bit is readable and writable. In the mode other than the basic test mode, writing any value to
this bit does not affect the operation (For details of the basic mode, refer to "14.5.7 Test Mode").
[bit14 to bit7] Reserved: Reserved bits
00000000B is read from these bits.
To write a value to these bits, set 00000000B.
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[bit5 to bit0] Message Number: Message No.
Table 14.4-25 Message No.
Message
Number
CM71-10159-2E
Function
00H
Setting disabled.
When this value is set, it is interpreted as 20H, and message 20H will
be read.
01H to 20H
The specified message No. will be processed.
21H to 3FH
Setting disabled.
When one of these values is set, it is interpreted as 01H to 1FH, and the
message of the corresponding number will be read.
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14.4.2.2
MB91461
IFx Command Mask Register (IFxCMSK)
The IFx command mask register (IFxCMSK) controls the direction of the data transfer
between the message interface register and message RAM, and specifies the data to be
updated. In the basic test mode, the setting of this register is invalid.
■ Register Configuration
Figure 14.4-9 Bit Configuration of IFx Command Mask Register (IFxCMSK)
IFx command mask register (High-order byte)
Address: Base+12H
bit15
14
13
Base+42H Reserved Reserved Reserved
Read/Write →
Initial value →
R
0
R
0
R
0
IFx command mask register (Low-order byte)
Address: Base+13H
bit7
6
5
Base+43H
WR/RD Mask
Arb
Read/Write →
Initial value →
R/W
0
R/W
0
R/W
0
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved
R
0
R
0
R
0
R
0
R
0
4
3
2
1
0
Control
CIP
TxRqst/
NewDat
R/W
0
R/W
0
R/W
0
Data A Data B
R/W
0
R/W
0
In the basic test mode, the setting of this register is invalid.
■ Register Functions
[bit15 to bit8] Reserved: Reserved bits
00000000B is read from these bits.
To write a value to these bits, set 00000000B.
[bit7] WR/RD: Write/read control bit
Table 14.4-26 Write/read Control Bit
362
WR/RD
Function
0
Indicates that data is read from the message RAM. The reading from the
message RAM is triggered by writing a message No. to the IFx command
request register. The data read from the message RAM depends on the
settings of the Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and Data
B bits. [Initial value]
1
Indicates that data is written to the message RAM. The writing to the
message RAM is triggered by writing a message No. to the IFx command
request register. The data written to the message RAM depends on the
settings of the Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and Data
B bits.
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After reset, the data in the message RAM is indeterminate. It is prohibited to read the data in the
message RAM when the data is indeterminate.
The meanings of bit6 to bit0 of the IFx command mask register vary depending on the transfer direction
setting (WR/RD bit).
● When the transfer direction is "write" (WR/RD=1)
[bit6] Mask: Mask data update bit
Table 14.4-27 Mask Data Update Bit
Mask
Function
0
Do not update the mask data (ID mask + MDir + MXtd) of the message
object.* [Initial value]
1
Update the mask data (ID mask + MDir + MXtd) of the message object.*
*: Refer to "14.4.3 Message Object".
[bit5] Arb: Arbitration data update bit
Table 14.4-28 Arbitration Data Update Bit
Arb
Function
0
Do not update the arbitration data (ID + Dir + Xtd + MsgVal) of the message
object.* [Initial value]
1
Update the arbitration data (ID + Dir + Xtd + MsgVal) of the message
object.*
*: Refer to "14.4.3 Message Object".
[bit4] Control: Control data update bit
Table 14.4-29 Control Data Update Bit
Control
Function
0
Do not update the control data (IFx message control register) of the message
object.* [Initial value]
1
Update the control data (IFx message control register) of the message
object.*
*: Refer to "14.4.3 Message Object".
[bit3] CIP: Interrupt clear bit
Setting either "0" or "1" to this bit does not affect the operation of the CAN controller.
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[bit2] TxRqst/NewDat: Message transmission request bit
Table 14.4-30 Message Transmission Request Bit
TxRqst/NewDat
Function
0
Set "0" to the TxRqst bits in the message object* and the CAN
transmission request register. [Initial value]
1
Set "1" to the TxRqst bits in the message object* and the CAN
transmission request register. (Transmission request)
*: Refer to "14.4.3 Message Object".
When the TxRqst/NewDat bit in the IFx command mask register is set to "1", the setting of the TxRqst bit
in the IFx message control register is invalid.
[bit1] Data A: Data0 to Data3 update bit
Table 14.4-31 Data0 to Data3 Update Bit
Data A
Function
0
Do not update data 0 to 3 of the message object.* [Initial value]
1
Update data 0 to 3 of the message object.*
*: Refer to "14.4.3 Message Object".
[bit0] Data B: Data4 to Data7 update bit
Table 14.4-32 Data4 to Data7 Update Bit
Data B
Function
0
Do not update data 4 to 7 of the message object.* [Initial value]
1
Update data 4 to 7 of the message object.*
*: Refer to "14.4.3 Message Object".
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● When the transfer direction is "read" (WR/RD=0)
The IntPnd and NewDat bits can be reset to "0" by the read access to the message object. In the IntPnd and
NewDat bits in the IFx message control register, however, the values of IntPnd and NewDat bits before the
reset by the read access are stored.
These settings are invalid in the basic test mode.
[bit6] Mask: Mask data update bit
Table 14.4-33 Mask Data Update Bit
Mask
Function
0
Do not transfer data (ID mask + MDir + MXtd) from the message object * to
IFx mask register 1/2. [Initial value]
1
Transfer data (ID mask + MDir + MXtd) from the message object * to IFx
mask register 1/2.
*: Refer to "14.4.3 Message Object".
[bit5] Arb: Arbitration data update bit
Table 14.4-34 Arbitration Data Update Bit
Arb
Function
0
Do not transfer data (ID + Dir + Xtd + MsgVal) from the message object * to
IFx arbitration register 1/2. [Initial value]
1
Transfer data (ID + Dir + Xtd + MsgVal) from the message object * to IFx
arbitration register 1/2.
*: Refer to "14.4.3 Message Object".
[bit4] Control: Control data update bit
Table 14.4-35 Control Data Update Bit
Control
CM71-10159-2E
Function
0
Do not transfer data from the message object * to the IFx message control
register. [Initial value]
1
Transfer data from the message object * to the IFx message control register.
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[bit3] CIP: Interrupt clear bit
Table 14.4-36 Interrupt Clear Bit
CIP
Function
0
Retain the IntPnd bits in the message object * and the CAN interrupt
pending register. [Initial value]
1
Clear the IntPnd bits in the message object * and the CAN interrupt pending
register to "0".
*: Refer to "14.4.3 Message Object".
[bit2] TxRqst/NewDat: Data update bit
Table 14.4-37 Data Update Bit
TxRqst/NewDat
Function
0
Retain the NewDat bits in the message object * and the CAN data
update register. [Initial value]
1
Clear the NewDat bits in the message object * and the CAN data
update register to "0".
*: Refer to "14.4.3 Message Object".
[bit1] Data A: Data0 to Data3 update bit
Table 14.4-38 Data0 to Data3 Update Bit
Data A
Function
0
Retain the data of the message object * and CAN data register A1/A2.
[Initial value]
1
Update the data of the message object * and CAN data register A1/A2.
*: Refer to "14.4.3 Message Object".
[bit0] Data B: Data4 to Data7 update bit
Table 14.4-39 Data4 to Data7 Update Bit
Data B
Function
0
Retain the data of the message object * and CAN data register B1/B2. [Initial
value]
1
Update the data of the message object * and CAN data register B1/B2.
*: Refer to "14.4.3 Message Object".
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14.4.2.3
IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2)
The IFx mask registers (IFxMSK1, IFxMSK2) are used to write/read the message object
mask data to/from the message RAM. In the basic test mode, the mask data being set is
invalid.
For the functions of each bit, refer to "14.4.3 Message Object".
■ Register Configuration
Figure 14.4-10 Bit Configuration of IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2)
IFx mask register 2 (High-order byte)
Address: Base+14H
bit15
14
Base+44H
MXtd MDir
Read/Write →
Initial value →
R/W
1
R/W
1
IFx mask register 2 (Low-order byte)
Address: Base+15H
bit7
6
Base+45H
Read/Write →
Initial value →
R/W
1
R/W
1
IFx mask register 1 (High-order byte)
Address: Base+16H
bit15
14
Base+46H
Read/Write →
Initial value →
R/W
1
R/W
1
IFx mask register 1 (Low-order byte)
Address: Base+17H
bit7
6
Base+47H
Read/Write →
Initial value →
R/W
1
R/W
1
13
12
Reserved
R
1
R/W
1
5
4
R/W
1
13
R/W
1
5
R/W
1
11
10
Msk28 to Msk24
R/W
R/W
R/W
1
1
1
3
2
11
Msk15 to Msk8
R/W
R/W
1
1
4
3
Msk7 to Msk0
R/W
R/W
1
1
8
R/W
1
1
0
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Msk23 to Msk16
R/W
R/W
R/W
1
1
1
12
9
For the description of each bit in the IFx mask register, refer to "14.4.3 Message Object".
"1" is read from the reserved bit in the register (bit13 of IFx mask register 2). To write a value to this bit,
write "1".
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14.4.2.4
MB91461
IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2)
The IFx arbitration registers (IFxARB1, IFxARB2) are used to write/read the message object
arbitration data to/from the message RAM. The setting of this register is invalid in the basic
test mode.
For the functions of each bit, refer to "14.4.3 Message Object".
■ Register Configuration
Figure 14.4-11 Bit Configuration of IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2)
IFx arbitration register 2 (High-order byte)
Address: Base+18H
bit15
14
Base+48H MsgVal
Xtd
Read/Write →
Initial value →
R/W
0
R/W
0
IFx arbitration register 2 (Low-order byte)
Address: Base+19H
bit7
6
Base+49H
Read/Write →
Initial value →
R/W
0
R/W
0
IFx arbitration register 1 (High-order byte)
Address: Base+1AH
bit15
14
Base+4AH
Read/Write →
Initial value →
R/W
0
R/W
0
IFx arbitration register 1 (Low-order byte)
Address: Base+1BH
bit7
6
Base+4BH
Read/Write →
Initial value →
R/W
0
R/W
0
13
12
Dir
R/W
0
R/W
0
5
4
R/W
0
13
R/W
0
5
R/W
0
11
3
11
ID15 to ID8
R/W
R/W
0
0
4
9
ID28 to ID24
R/W
R/W
R/W
0
0
0
ID23 to ID16
R/W
R/W
0
0
12
10
3
ID7 to ID0
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
For the description of each bit in the IFx arbitration register, refer to "14.4.3 Message Object".
When the MsgVal bit in the message object is cleared to "0" during transmission, the TxOk bit in the CAN
status register is set to "1" at the completion of the transmission. However, the TxRqst bits in the message
object and the CAN transmission request register are not cleared to "0". In such a case, use the message
interface register to clear the TxRqst bits to "0".
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14.4.2.5
IFx Message Control Register (IFxMCTR)
The IFx message control register (IFxMCTR) is used to write/read the message object
control data to/from the message RAM. In the basic test mode, the IF1 message control
register is disabled. The NewDat and MsgLst bits in the IF2 message control register
operate normally, and the DLC bit shows DLC of the received message. The other control
bits operate as invalid ("0").
For the functions of each bit, refer to "14.4.3 Message Object".
■ Register Configuration
Figure 14.4-12 Bit Configuration of IFx Message Control Register (IFxMCTR)
IFx message control register (High-order byte)
Address: Base+1CH
bit15
14
13
12
Base+4CH NewDat MsgLst IntPnd UMask
Read/Write → R/W
R/W
R/W
R/W
Initial value →
0
0
0
0
IFx message control register (Low-order byte)
Address: Base+1DH
bit7
6
5
Base+4DH
EoB Reserved Reserved
Read/Write →
Initial value →
R/W
0
R
0
R
0
4
11
10
TxIE
R/W
0
RxIE
R/W
0
3
2
Reserved
R
0
R/W
0
9
8
RmtEn TxRqst
R/W
R/W
0
0
1
DLC3 to DLC0
R/W
R/W
0
0
0
R/W
0
For the description of each bit in the IFx message control register, refer to "14.4.3 Message Object".
The TxRqst, NewDat, and IntPnd bits operate as follows depending on the setting of the WR/RD bit in the
IFx command mask register.
● When the transfer direction is "write" (IFx command mask register: WR/RD=1)
The TxRqst bit in this register is enabled only when the TxRqst/NewDat bit in the IFx command mask
register is set to "0".
● When the transfer direction is "read" (IFx command mask register: WR/RD=0)
When the CIP bit in the IFx command mask register is set to "1", and the IntPnd bits in the message object
and CAN interrupt pending register are reset by writing a message No. to the IFx command request
register, the value of the IntPnd bit before the reset is stored in this register.
When the TxRqst/NewDat bit in the IFx command mask register is set to "1", and the NewDat bits in the
message object and CAN data update register are reset by writing a message No. to the IFx command
request register, the value of the NewDat bit before the reset is stored in this register.
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14.4.2.6
MB91461
IFx Data Registers A1, A2, B1, B2
(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
The IFx data registers (IFxDTA1, IFxDTA2, IFxDTAB1, IFXDTB2) are used to write/read
the message object's transmission data to/from the message RAM. These registers are
used for the transmission of data frames only, and not used for the transmission of
remote frames.
■ Register Configuration
Table 14.4-40 Register Configuration
addr+0
addr+1
addr+2
addr+3
IFx message data register A1 (Address: 20H & 50H)
Data (0)
Data (1)
-
-
IFx message data register A2 (Address: 22H & 52H)
-
-
Data (2)
Data (3)
IFx message data register B1 (Address: 24H & 54H)
Data (4)
Data (5)
-
-
Data (6)
Data (7)
IFx message data register B2 (Address: 26H & 56H)
IFx message data register A2 (Address: 30H & 60H)
Data (3)
Data (2)
-
-
IFx message data register A1 (Address: 32H & 62H)
-
-
Data (1)
Data (0)
IFx message data register B2 (Address: 34H & 64H)
Data (7)
Data (6)
-
-
IFx message data register B1 (Address: 36H & 66H)
-
-
Data (5)
Data (4)
Figure 14.4-13 Bit Configuration of IFx Data Register
IFx data register
15
7
bit
Read/Write →
Initial value →
R/W
0
14
6
R/W
0
13
5
R/W
0
12
4
11
3
Data
R/W
R/W
0
0
10
2
9
1
8
0
R/W
0
R/W
0
R/W
0
■ Register Functions
● Transmission message data setting
The setting data is sent from MSB (bit7, bit15), and in the order of Data (0), Data (1), ... , Data (7).
● Reception message data
The reception message data is stored from MSB (bit7, bit15), and in the order of Data (0), Data (1), ... ,
Data (7).
If the reception message data is less than 8 bytes, the data stored in the remaining byte(s) in the data
register will be indeterminate.
The data transfer to the message object is processed in the unit of 4 bytes of Data A or Data B.
Consequently, it is impossible to update only the part of data in the 4 bytes.
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14.4.3
Message Object
The message RAM contains 32 (128 in some types) message objects. To avoid the
conflict of the accesses from the CPU and CAN controller to the message RAM, the CPU
cannot directly access to the message object. These accesses are made via the IFx
message interface register.
This section describes the configuration and functions of the message object.
■ Configuration of the Message Object
Table 14.4-41 Message Object
UMask
Msk28 to
Msk0
MsgVal ID28 to ID0
MXtd
MDir
Xtd
Dir
EoB
NewDat
DLC3 to
Data0
DLC0
Data1
MsgLst
RxIE
TxIE
IntPnd
RmtEn TxRqst
Data2
Data3
Data4
Data5
Data6
Data7
Note:
The message object cannot be initialized by setting the Init bit in the CAN control register or by
hardware reset. After using hardware reset, cancel the reset and then initialize the message RAM by
the CPU or set MsgVal of the message RAM to "0".
■ Functions of the Message Object
The ID28 to ID0, Xtd, and Dir bits are used to specify the ID and message type when a message is sent.
When a message is received, they are used by the acceptance filter together with the Msk28 to Msk0,
MXtd, and MDir bits.
The data frame or remote frame which passed the acceptance filter is stored in the message object. The
value of Xtd expresses that the frame is an expansion frame or a standard frame. When Xtd is "1", 29-bit ID
(expansion frame) is received. When Xtd is "0", 11-bit ID (standard frame) is received.
If the received data frame or remote frame matches with one or more message objects, it is stored in the
matching message object which has the smallest message No. For details, refer to "Acceptance filter for
reception messages" in "14.5.3 Message Reception Operation".
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MsgVal: Message validation bit
Table 14.4-42 Message Validation Bit
MsgVal
Function
0
The message object is invalid.
The message cannot be transmitted or received.
1
The message object is valid.
The message can be transmitted or received.
• During the initialization process before the Init bit in the CAN control register is reset to "0", reset
the MsgVal bits in all unused message objects from the CPU.
• Be sure to reset the MsgVal bit to "0" before changing the values of ID28 to ID0, Xtd, Dir, and
DLC3 to DLC0, or when the message object is not required.
• When the MsgVal bit is cleared to "0" during transmission, the TxOk bit in the CAN status register
is set to "1" at the completion of the transmission. However, the TxRqst bits in the message object
and the CAN transmission request register are not cleared to "0". In such a case, use the message
interface register to clear the TxRqst bits to "0".
UMask: Acceptance mask enable bit
Table 14.4-43 Acceptance Mask Enable Bit
UMask
Function
0
Do not use Msk28 to Msk0, MXtd, and MDir.
1
Use Msk28 to Msk0, MXtd, and MDir.
• Change the UMask bit when the Init bit in the CAN control register is "1", or when the MsgVal bit is
"0".
• When the Dir bit is "1" and the RmtEn bit is "0", the operation varies depending on the UMask
setting.
• When UMask is set to "1", TxRqst bit is reset to "0" after a remote frame which passed the
acceptance filter is received. The received ID, IDE, RTR, and DLC are stored in the message object,
the NewDat bit is set to "1", and the data is not changed (The remote frame is treated as if it is a data
frame).
• When UMask is "0", the value of the TxRqst bit is retained even when a remote frame is received.
The remote frame is ignored.
ID28 to ID0: Message ID
Table 14.4-44 Message ID
ID28 to ID0
372
Function
ID28 to ID0
Specifies 29-bit ID (expansion frame).
ID28 to ID18
Specifies 11-bit ID (standard frame).
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Msk28 to Msk0: ID mask
Table 14.4-45 ID Mask
Msk
Function
0
Mask the bit which corresponds to the ID of the message object.
1
Do not mask the bit which corresponds to the ID of the message object.
When 11-bit ID (standard frame) is specified to the message object, the ID of the received data frame is
written to ID28 to ID18. Msk 28 to Msk 18 are used for the ID mask.
Xtd: Expansion ID enable bit
Table 14.4-46 Expansion ID Enable Bit
Xtd
Function
0
The message object is 11-bit ID (standard frame).
1
The message object is 29-bit ID (expansion frame).
MXtd: Expansion ID mask bit
Table 14.4-47 Expansion ID Mask Bit
MXtd
Function
0
Mask the expansion ID bit (IDE) by the acceptance filter.
1
Do not mask the expansion ID bit (IDE) by the acceptance filter.
Dir: Message direction bit
Table 14.4-48 Message Direction Bit
Dir
CM71-10159-2E
Function
0
Indicates the direction of the reception.
When TxRqst is set to "1", a remote frame is transmitted. When TxRqst is
set to "0", the data frame which passed the acceptance filter is received.
1
Indicates the direction of the transmission.
When TxRqst is set to "1", a data frame is transmitted. When TxRqst is set to
"0" and RmtEn is set to "1", the remote frame which passed the acceptance
filter is received, and TxRqst is set to "1" by the CAN controller itself.
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MDir: Message direction mask bit
Table 14.4-49 Message Direction Mask Bit
MDir
Function
0
Mask the message direction bit (Dir) by the acceptance filter.
1
Do not mask the message direction bit (Dir) by the acceptance filter.
Note:
Set the MDir bit to "1" at all times.
EoB: End of buffer bit (For details, refer to "14.5.4 FIFO Buffer Function".)
Table 14.4-50 End of Buffer Bit
EoB
Function
0
The message object is used as an FIFO buffer, and it is not the final
message.
1
The message object is single or the final message object in an FIFO buffer.
The EoB bit is used to configure an FIFO buffer of 2 to 32 messages.
To use a single message object (do not use FIFO), be sure to set the EoB bit to "1".
NewDat: Data update bit
Table 14.4-51 Data Update Bit
NewDat
Function
0
No valid data exists.
1
Valid data exists.
MsgLst: Message lost
Table 14.4-52 Message Lost
MsgLst
Function
0
Message was not lost.
1
Message was lost.
The MsgLst bit is enabled only when the Dir bit is set to "0" (reception).
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RxIE: Reception interrupt flag enable bit
Table 14.4-53 Reception Interrupt Flag Enable Bit
RxIE
Function
0
Do not change the value of IntPnd after a successful frame reception.
1
Set IntPnd to "1" after a successful frame reception.
TxIE: Transmission interrupt flag enable bit
Table 14.4-54 Transmission Interrupt Flag Enable Bit
TxIE
Function
0
Do not change the value of IntPnd after a successful frame transmission.
1
Set IntPnd to "1" after a successful frame transmission.
IntPnd: Interrupt pending bit
Table 14.4-55 Interrupt Pending Bit
IntPnd
Function
0
No interrupt factor exists.
1
Interrupt factor exists.
If there is no other interrupts which have higher priority, the IntId bit in the
CAN interrupt register points to this message object.
RmtEn: Remote enable
Table 14.4-56 Remote Enable
RmtEn
Function
0
The value of TxRqst is not changed when a remote frame is received.
1
TxRqst is set to "1" when the Dir bit is "1" and a remote frame is received.
When the Dir bit is "1" and the RmtEn bit is "0", the operation varies depending on the UMask setting.
• When UMask is set to "1", TxRqst bit is reset to "0" after a remote frame which passed the
acceptance filter is received. The received ID, IDE, RTR, and DLC are stored in the message object,
the NewDat bit is set to "1", and the data is not changed. (The remote frame is treated as if it is a data
frame.)
• When UMask is "0", the value of the TxRqst bit is retained even when a remote frame is received.
The remote frame is ignored.
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TxRqst: Transmission request bit
Table 14.4-57 Transmission Request Bit
TxRqst
Function
0
Transmission idle status (neither during transmission nor in the transmission
standby status).
1
During transmission or in the transmission standby status.
DLC3 to DLC0: Data length code
Table 14.4-58 Data Length Code
DLC3 to DLC0
Function
0 to 8
The data frame length is 0 to 8 bytes.
9 to 15
Setting disabled.
Setting these values is assumed to be 8-byte length.
When a data frame is received, the DLC bit stores the received DLC.
Data0 to Data7: Data0 to Data7
Table 14.4-59 Data0 to Data7
Data0 to Data7
Function
Data 0
The 1st data byte of a CAN data frame
Data 1
The 2nd data byte of a CAN data frame
Data 2
The 3rd data byte of a CAN data frame
Data 3
The 4th data byte of a CAN data frame
Data 4
The 5th data byte of a CAN data frame
Data 5
The 6th data byte of a CAN data frame
Data 6
The 7th data byte of a CAN data frame
Data 7
The 8th data byte of a CAN data frame
• The serial output to the CAN bus is output from MSB (bit7 or bit15).
• If the reception message data is less than 8 bytes, the data stored in the remaining byte(s) in the data
register will be indeterminate.
• The data transfer to the message object is processed in the unit of 4 bytes of Data A or Data B.
Consequently, it is impossible to update only the part of data in the 4 bytes.
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14.4.4
Message Handler Register
14.4 CAN Register Functions
All message handler registers are read only. The TxRqst, NewDat, IntPnd, MsgVal, and
IntId bits in the message object show the status of the object.
■ Message Handler Register
• CAN transmission request registers 1, 2 (TREQR1, TREQR2)
• CAN data update registers 1, 2 (NEWDT1, NEWDT2)
• CAN interrupt pending registers 1, 2 (INTPND1, INTPND2)
• CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2)
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14.4.4.1
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CAN Transmission Request Register
(TREQR1, TREQR2)
The CAN transmission request register (TREQR1, TREQR2) shows the status of the
TxRqst bit in every message object. By reading the TxRqst bit, you can check which
message object has a pending transmission request.
■ Register Configuration
Figure 14.4-14 Bit Configuration of CAN Transmission Request Register (TREQR1, TREQR2)
CAN transmission request register 2 (High-order byte)
bit
Address: Base+80H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
10
9
8
TxRqst32 to TxRqst25
R
R
R
0
0
0
R
0
R
0
2
1
0
TxRqst24 to TxRqst17
R
R
R
0
0
0
R
0
R
0
10
9
8
TxRqst16 to TxRqst9
R
R
R
0
0
0
R
0
R
0
CAN transmission request register 2 (Low-order byte)
bit
Address: Base+81H
Read/Write →
Initial value →
7
6
5
R
0
R
0
R
0
4
3
CAN transmission request register 1 (High-order byte)
bit
Address: Base+82H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
CAN transmission request register 1 (Low-order byte)
bit
Address: Base+83H
Read/Write →
Initial value →
378
7
R
0
6
5
2
1
0
R
0
TxRqst8 to TxRqst1
R
R
R
R
0
0
0
0
4
3
R
0
R
0
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■ Register Functions
TxRqst32 to TxRqst1: Transmission request bit
Table 14.4-60 Transmission Request Bit
TxRqst
Function
0
Transmission idle status (neither during transmission nor in the transmission
standby status).
1
During transmission or in the transmission standby status.
The set/reset condition of the TxRqst bit is as follows:
• Set condition
- When the IFx command mask register’s WR/RD is set to "1", and its TxRqst is set to "1", the
TxRqst bit in a specific object can be set by writing a message No. to the IFx command request
register.
- When the IFx command mask register’s WR/RD is set to "1", its TxRqst is set to "0", and the IFx
message control register’s TxRqst is set to "1", the TxRqst bit in a specific object can be set by
writing a message No. to the IFx command request register.
- The TxRqst bit is set when the Dir bit is set to "1", the RmtEn bit to "1", and a remote frame
which passed the acceptance filter is received.
• Reset condition
- When the IFx command mask register’s WR/RD is set to "1", its TxRqst is set to "0", and the IFx
message control register’s TxRqst is set to "0", the TxRqst bit in a specific object can be reset by
writing a message No. to the IFx command request register.
- The TxRqst bit is reset when the frame transmission finishes successfully.
- When Dir is set to "1", RmtEn is set to "0", and UMask is set to "1", the TxRqst bit is reset by the
reception of a remote frame which passed the acceptance filter.
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14.4.4.2
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CAN Data Update Register (NEWDT1, NEWDT2)
The CAN data update register (NEWDT1, NEWDT2) shows the status of the NewDat bit
in every message object. By reading the NewDat bit, you can check which message
object has an updated data.
■ Register Configuration
Figure 14.4-15 Bit Configuration of CAN Data Update Register (NEWDT1, NEWDT2)
CAN data update register 2 (High-order byte)
bit
Address: Base+90H
Read/Write →
Initial value →
15
14
13
12
11
10
9
8
R
0
R
0
NewDat32 to NewDat25
R
R
R
R
0
0
0
0
R
0
R
0
CAN data update register 2 (Low-order byte)
bit
Address: Base+91H
Read/Write →
Initial value →
7
6
5
4
3
2
1
0
R
0
R
0
NewDat24 to NewDat17
R
R
R
R
0
0
0
0
R
0
R
0
10
9
8
NewDat16 to NewDat9
R
R
R
0
0
0
R
0
R
0
2
1
0
NewDat8 to NewDat1
R
R
R
0
0
0
R
0
R
0
CAN data update register 1 (High-order byte)
bit
Address: Base+92H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
CAN data update register 1 (Low-order byte)
bit
Address: Base+93H
Read/Write →
Initial value →
380
7
6
5
R
0
R
0
R
0
4
3
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■ Register Functions
NewDat32 to NewDat1: Data update bit
Table 14.4-61 Data Update Bit
NewDat32 to NewDat1
Function
0
No valid data exists.
1
Valid data exists.
The set/reset condition of the NewDat bit is as follows:
• Set condition
- When the IFx command mask register’s WR/RD is set to "1", and the IFx message control
register’s NewDat is set to "1", the NewDat bit in a specific object can be set by writing a
message No. to the IFx command request register.
- The NewDat bit is set when a data frame which passed the acceptance filter is received.
- When Dir is set to "1", RmtEn is set to "0", and UMask is set to "1", the NewDat bit is set by the
reception of a remote frame which passed the acceptance filter.
• Reset condition
- When the IFx command mask register’s WR/RD is set to "0", and its NewDat is set to "1", the
NewDat bit in a specific object can be reset and by writing a message No. to the IFx command
request register.
- When the IFx command mask register’s WR/RD to "1", and the IFx message control register’s
NewDat is set to "0", the NewDat bit in a specific object can be reset by writing a message No. to
the IFx command request register.
- The NewDat bit is reset after data has been transferred to the transmitting shift register (internal
register).
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14.4.4.3
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CAN Interrupt Pending Register (INTPND1, INTPND2)
The CAN interrupt pending register (INTPND1, INTPND2) shows the status of the IntPnd
bit in every message object. By reading the IntPnd bit, you can check which message
object has a pending interrupt.
■ Register Configuration
Figure 14.4-16 Bit Configuration of CAN Interrupt Pending Register (INTPND1, INTPND2)
CAN interrupt pending register 2 (High-order byte)
bit
Address: Base+A0H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
10
9
8
IntPnd32 to IntPnd25
R
R
R
0
0
0
R
0
R
0
2
1
0
IntPnd24 to IntPnd17
R
R
R
0
0
0
R
0
R
0
10
9
8
IntPnd16 to IntPnd9
R
R
R
0
0
0
R
0
R
0
2
1
0
R
0
R
0
R
0
CAN interrupt pending register 2 (Low-order byte)
bit
Address: Base+A1H
Read/Write →
Initial value →
7
6
5
R
0
R
0
R
0
4
3
CAN interrupt pending register 1 (High-order byte)
bit
Address: Base+A2H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
CAN interrupt pending register 1 (Low-order byte)
bit
Address: Base+A3H
Read/Write →
Initial value →
382
7
6
5
R
0
R
0
R
0
4
3
IntPnd8 to IntPnd1
R
R
0
0
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■ Register Functions
IntPnd32 to IntPnd1: Interrupt pending bit
Table 14.4-62 Interrupt Pending Bit
IntPnd32 to IntPnd1
Function
0
No interrupt factor exists.
1
Interrupt factor exists.
The set/reset condition of the IntPnd bit is as follows:
• Set condition
- When TxIE is set to "1", this bit is set by the successful completion of frame transmission.
- When RxIE is set to "1", this bit is set by the successful completion of the reception of a frame
which passed the acceptance filter.
• Reset condition
- When the IFx command mask register’s WR/RD is set to "1", and its IntPnd is set to "1", the
IntPnd bit in a specific object can be reset by writing a message No. to the IFx command request
register.
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14.4.4.4
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CAN Message Validation Register
(MSGVAL1, MSGVAL2)
The CAN message validation register (MSGVAL1, MSGVAL2) shows the status of the
MsgVal bit in every message object. By reading the MsgVal bit, you can check which
message object is valid.
■ Register Configuration
Figure 14.4-17 Bit Configuration of CAN Message Validation Register (MSGVAL1, MSGVAL2)
CAN message validation register 2 (High-order byte)
bit
Address: Base+B0H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
10
9
8
MsgVal32 to MsgVal25
R
R
R
0
0
0
R
0
R
0
2
1
0
MsgVal24 to MsgVal17
R
R
R
0
0
0
R
0
R
0
10
9
8
MsgVal16 to MsgVal9
R
R
R
0
0
0
R
0
R
0
CAN message validation register 2 (Low-order byte)
bit
Address: Base+B1H
Read/Write →
Initial value →
7
6
5
R
0
R
0
R
0
4
3
CAN message validation register 1 (High-order byte)
bit
Address: Base+B2H
Read/Write →
Initial value →
15
14
13
R
0
R
0
R
0
12
11
CAN message validation register 1 (Low-order byte)
bit
Address: Base+B3H
Read/Write →
Initial value →
384
7
R
0
6
5
2
1
0
R
0
MsgVal8 to MsgVal1
R
R
R
R
0
0
0
0
4
3
R
0
R
0
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■ Register Functions
MsgVal32 to MsgVal1: Message validation bit
Table 14.4-63 Message Validation Bit
MsgVal32 to MsgVal1
Function
0
The message object is invalid.
The message cannot be transmitted or received.
1
The message object is valid.
The message can be transmitted or received.
The set/reset condition of the MsgVal bit is as follows:
• Set condition
The MsgVal bit in a specific object can be set by setting IFx arbitration register 2’s MsgVal to "1"
and writing a message No. to the IFx command request register.
• Reset condition
The MsgVal bit in a specific object can be reset by setting IFx arbitration register 2’s MsgVal to "0"
and writing a message No. to the IFx command request register.
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14.4.5
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CAN Prescaler Register (CANPRE)
The CAN prescaler register (CANPRE) selects the clock source for the CAN prescaler
and defines the division ratio of the CAN clock provided to the CAN interface. Before
changing the value of this register, set the initialization bit (Init) of the CAN control
register (CTRLR) to "1" and stop the operation of all buses.
■ Register Configuration
Figure 14.4-18 Bit Configuration of CAN Prescaler Register (CANPRE)
CAN prescaler register
bit
Address: ch.0 00C000H
ch.1 00C100H
15
14
13
12
Reserved Reserved CPCKS1 CPCKS0
Read/Write →
Initial value →
R
0
R
0
R/W
0
R/W
0
11
10
9
8
DVC3
DVC2
DVC1
DVC0
R/W
0
R/W
0
R/W
0
R/W
0
■ Register Functions
[bit15, bit14] Reserved: Reserved bits
00B is read from these bits.
Writing to these bits is not reflected to the register.
[bit13, bit12] CPCKS1, CPCKS0: CAN prescaler clock source selection bit
Table 14.4-64 CAN Prescaler Clock Source Selection Bit
CPCKS[1:0]
386
CAN prescaler clock source
00B
CPU clock (80 MHz max.) [Initial value]
01B
PLL output (200 MHz max.)
10B
Setting disabled.
11B
Source oscillation clock (20 MHz max.)
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[bit11 to bit8] DVC3 to DVC0: CAN clock setting bit
Table 14.4-65 CAN Clock Setting Bit
DVC3 to DVC0
CAN clock
0000B
Select a 1/1 cycle of the prescaler clock source. [Initial value]
0001B
Select a 1/2 cycle of the prescaler clock source.
0010B
Select a 1/3 cycle of the prescaler clock source.
:
:
1110B
Select a 1/15 cycle of the prescaler clock source.
1111B
Select a 1/16 cycle of the prescaler clock source.
• Before changing the value of the CAN prescaler setting bit, set the initialization bit in the CAN
control register to "1" and stop the operation of all buses.
• Set the frequency of the CAN clock which is provided to the CAN interface by setting this register to
20 MHz or less.
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14.5 CAN Controller Functions
14.5
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CAN Controller Functions
This section describes the operations and functions of the CAN controller.
The following functions are explained:
• Message Object
• Message Transmission Operation
• Message Reception Operation
• FIFO Buffer Function
• Interrupt Function
• Bit Timing
• Test Mode
• Software Initialization
• CAN Clock Prescaler
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14.5.1
Message Object
14.5 CAN Controller Functions
This section describes the message objects in the message RAM and the interfaces
being used.
■ Message Object
The message object settings in the message RAM (except for the MsgVal, NewDat, IntPnd, and TxRqst
bits) are not initialized by hardware reset. Therefore, you need to initialize the message objects from the
CPU, or to disable the MsgVal bit (MsgVal=0). The CAN bit timing register must be set while the Init bit
in the CAN control register is "0".
To set a message object, configure appropriate message interface registers (IFx mask register, IFx
arbitration register, the IFx message control register, and IFx data register), and write a message No. to the
IFx command request register. The data of the interface register is transferred to the specified message
object.
When the Init bit in the CAN control register is cleared to "0", the CAN controller starts operation. The
reception message which passed the acceptance filter is stored in the message RAM. The message for
which a transmission request is pending is transferred from the message RAM to the shift register of the
CAN controller, and then sent to the CAN bus.
The CPU reads reception messages and updates transmission messages via the message interface registers.
The interrupt to the CPU occurs based on the settings of the CAN control register and IFx message control
register (message objects).
■ Data Transmission/Reception to/from the Message RAM
When the data transfer between the message interface register and message RAM starts, the BUSY bit in
the IFx command request register is set to "1". When the data transfer is complete, the BUSY bit is cleared
to "0". (Refer to Figure 14.5-1.)
The IFx command mask register sets either of all-data transfer or partial-data transfer of a message object.
Due to the structure of the message RAM, it is impossible to write a single bit/byte of a message object. All
data of a message object is always written to the message RAM. Consequently, the data transfer from the
message interface register to the message RAM requires a execution cycle of read-modify-write (RMW)
instruction.
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Figure 14.5-1 Data Transfer Between Message Interface Register and Message RAM
Start
Write to
IFx command request register.
NO
YES
BUSY = 1
Interrupt = 0
NO
YES
WR/RD = 1
Read from message RAM to
message interface register.
Read from message RAM to
message interface register.
Write from message interface register to
message RAM.
BUSY = 0
Interrupt = 1
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14.5.2
Message Transmission Operation
This section describes the settings and transmission operations for the transmission
message objects.
■ Message Transmission
When no data transfer is detected between the message interface register and message RAM, the MsgVal
bit in the CAN message validation register and the TxRqst bit in the CAN transmission request register are
evaluated. Then, a valid message object which has a pending transmission request and the highest priority
is transmitted to the transmission shift register. At this point, the NewDat bit in the message object is reset
to "0".
When the transmission is complete successfully and the message object has no new data (NewDat=0), the
TxRqst bit is reset to "0". If TxIE is set to "1", the IntPnd bit is set to "1" after successful transmission. If
the CAN controller loses arbitration on the CAN bus, or if an error occurs during transmission, the message
is re-transmitted immediately after the CAN bus becomes idle.
■ Transmission Priority
The transmission priority of the message objects are determined by the message numbers. Message object 1
has the highest priority, and message object 32 (or the maximum message object No. implemented) has the
lowest priority. Consequently, when two or more transmission requests are pending, the message object
with smaller message No. is transmitted.
■ Transmission Message Object Setting
Figure 14.5-2 shows the initialization of transmission message object.
Figure 14.5-2 Initialization of Transmission Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
1
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
0
appl.
0
RmtEn TxRqst
appl.
0
The IFx arbitration register (ID28 to ID0 and Xtd bits) is provided by the application and defines the ID
and message type of the transmission message.
When a standard frame (11-bit ID) is set, ID28 through ID18 are used, and ID17 through ID0 are invalid.
When an expansion frame (29-bit ID) is set, ID28 through ID0 are used.
When the TxIE bit is set to "1", the IntPnd bit is set to "1" after the message object is transmitted
successfully.
When the RmtEn bit is set to "1", the TxRqst bit is set to "1" after the corresponding remote frame is
received, and the data frame is transmitted automatically.
The settings of the data registers (DLC3 to DLC0, Data0 to Data7) are provided by the application.
When UMask= 1, the IFx mask registers (Msk28 to Msk0, UMask, MXtd, and MDir bits) receive remote
frames having IDs grouped by the mask setting. Then, the registers are used to enable transmission (Set the
TxRqst bit to "1".). For details, refer to "Remote frame" in "14.5.3 Message Reception Operation".
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Note:
It is prohibited to set the Dir bit in the IFx mask register to enable mask.
■ Updating a Transmission Message Object
The CPU can update the data of transmission message objects via the message interface register.
The data of the transmission message object is written in the unit of 4 bytes of the corresponding IFx data
register (IFx data register A or IFx data register B). Therefore, you cannot change only one byte of the
transmission message object.
To update only 8 bytes of data, first write 0087H to the IFx command mask register. By writing a message
No. to the IFx command request register, the data of the transmission message object (8-byte data) is
updated and "1" is written to the TxRqst bit at the same time.
To transmit the data immediately following the message No. currently transmitted, set the TxRqst and
NewDat bits to "1". By this, the TxRqst bit is not reset to "0" and data can be transmitted continuously.
When both NewDat bit and TxRqst bit are set to "1", the NewDat bit is reset to "0" after transmission starts.
• To update data, write the data in the unit of 4 bytes of IFx data register A or IFx data register B.
• To update data only, set the NewDat and TxRqst bits to "1".
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14.5.3
Message Reception Operation
14.5 CAN Controller Functions
This section describes the settings and reception operations for the reception message
objects.
■ Acceptance Filter for Reception Messages
When the arbitration/control fields of the message (ID + IDE + RTR + DLC) are completely shifted to the
CAN controller reception shift register, the scan of the message RAM starts for the comparison with valid
message objects to find a match.
During the scan, the arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are
loaded from the message object in the message RAM, and the arbitration fields of the message object and
shift register are compared including the mask data.
This operation is repeated until the match of the arbitration fields of the message object and shift register is
detected, or until the operation reaches the last word of the message RAM. When the match is detected, the
scan of the message RAM stops, and the CAN controller starts processing according to the type of the
reception frame (data frame or remote frame).
■ Reception Priority
The reception priority of the message objects are determined by the message numbers. Message object 1
has the highest priority, and message object 32 (or the maximum message object No. implemented) has the
lowest priority. Consequently, when two or more message objects are found to be a match by the
acceptance filter, the message object with a smaller message No. is received.
■ Data Frame Reception
The CAN controller transfers and stores the reception message from the shift register to the message RAM
of the message object which was found to be a match by the acceptance filter. The data to be stored is not
only data bytes, but also all the arbitration fields and data length codes. The same is true even when the IFx
mask register is set for masking (in order to retain the ID and data bytes).
When new data is received, the NewDat bit is set to "1". When the CPU reads a message object, reset the
NewDat bit to "0". If the NewDat bit is already set to "1" when a message is received, the preceding data is
assumed to be lost, and the MsgLst bit is set to "1".
When the RxIE bit is set to "1" and a message buffer is received, the IntPnd bit in the CAN interrupt
pending register is set to "1". At this point, the TxRqst bit in the corresponding message object is reset to
"0", in order to disable transmission when a request data frame is received during the transmission of a
remote frame.
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■ Remote Frame
The following three types of processing are available when a remote frame is received: The processing
during the remote frame reception is selected based on the settings of the matching message object.
• Dir=1 (transmission direction), RmtEn=1, UMask=1 or 0
The matching remote frame is received, only the TxRqst bit in this message object is set to "1", and the
data frame for the remote frame is automatically returned (transmitted). (The bits other than the TxRqst
bit in the message object are not changed.)
• Dir=1 (transmission direction), RmtEn=0, UMask=0
The reception is disabled even if the received remote frame matches with the message object. The
remote frame becomes invalid. (The TxRqst bit in this message object is not changed.)
• Dir=1 (transmission direction), RmtEn=0, UMask=1
When the received remote frame matches with the message object, the TxRqst bit in the message object
is reset to "0", and the remote frame is processed as a received data frame. The received arbitration field
and control field (ID + IDE + RTR + DLC) are stored in the message object in the message RAM. The
NewDat bit in the message object is set to "1". The data field of the message object is not changed.
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■ Reception Message Object Setting
Figure 14.5-3 shows the initialization of reception message object.
Figure 14.5-3 Initialization of Reception Message Object
MsgVal
Arb
Data
Mask
EoB
Dir
1
appl.
appl.
appl.
1
0
NewDat MsgLst
0
0
RxIE
TxIE
IntPnd
appl.
0
0
RmtEn TxRqst
0
0
The IFx arbitration register (ID28 to ID0, Xtd bit) is provided by the application. It defines the ID and
message type of the reception message used for the acceptance filter.
When a standard frame (11-bit ID) is set, ID28 through ID18 are used, and ID17 through ID0 are invalid.
When a standard frame is received, ID17 through ID0 are reset to "0". When an expansion frame (29-bit
ID) is set, ID28 through ID0 are used.
When the RxIE bit is set to "1" and a reception data frame is stored in the message object, the IntPnd bit is
set to "1".
The data length code (DLC3 to DLC0) is provided by the application. When the CAN controller stores a
reception data frame into the message object, it stores the reception data length code and the 8-byte data. If
the data length code is less than 8, indeterminate data is written as the rest of the message object data.
When UMask=1, the IFx mask register (Msk28 to Msk0, UMask, MXtd, and MDir bits) is used to enable
the reception of data frames having IDs grouped by the mask setting. For details, refer to "Data frame
reception" in "14.5.3 Message Reception Operation".
Note:
It is prohibited to set the Dir bit in the IFx mask register for masking.
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■ Reception Message Processing
The CPU can read reception messages any time via the message interface register.
In normal times, "007FH" is written to the IFx command mask register. Then the message No. of the
message object is written to the IFx command request register. By this, the reception message of the
specified message No. is transferred from the message RAM to the message interface register. During this
process, the NewDat and IntPnd bits in the message object can be cleared to "0" by setting the IFx
command mask register.
As for the processing of the reception message, the message is received when it is found to be a match by
the acceptance filter. If the message object uses the masking by the acceptance filter, the data to be masked
is removed from the acceptance filter, and whether or not to receive the message is judged.
The NewDat bit indicates whether a new message was received after the last message object was read.
The MsgLst bit indicates that the preceding data was lost because the next reception data is received before
the preceding reception data was read from the message object. The MsgLst bit is not reset automatically.
When a matching data frame is received by the acceptance filter while the remote frame is being
transmitted, the TxRqst bit is automatically reset to "0".
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14.5.4
FIFO Buffer Function
14.5 CAN Controller Functions
This section describes the configuration of the message objects in the FIFO buffer and
the FIFO buffer operations used for the reception message processing.
■ Configuration of the FIFO Buffer
The configuration of the reception message object in the FIFO buffer is the same as the configuration of the
normal reception message object except for the EoB bit (For details, refer to "Setting a reception message
object" in "14.5.3 Message Reception Operation").
The FIFO buffer uses two or more reception message objects by concatenating them. To store a reception
message into such FIFO buffer using the ID and masking of the reception message object, the ID and mask
settings of the message objects must be the same.
The first reception message object in the FIFO buffer is the object with the smaller message No. which has
the highest priority. It is necessary to set the EoB bit in the last reception message object in the FIFO buffer
to "1" to indicate the end of the FIFO buffer block (As for the message objects other than the last message
object using the FIFO buffer configuration, set their EoB bits to "0").
• Be sure to use the same ID and mask settings for the message objects used in the FIFO buffer.
• When the FIFO buffer is not used, be sure to set the EoB bit of the message object to "1".
■ Message Reception by the FIFO Buffer
When the reception message matches with the ID of the FIFO buffer, it is stored in the reception message
object having the smallest message No. in the FIFO buffer.
When a message is stored in the reception message object in the FIFO buffer, the NewDat bit in the
reception message object is set to "1". When the EoB bit of the reception message object is "0" and its
NewDat bit is set to "1", the reception message object is protected and the CAN controller cannot write to
the FIFO buffer until the operation reaches the last reception message object (EoB bit=1).
Unless "0" is written to the NewDat bit in the reception message object (canceling write protection) with
valid data being stored until the last FIFO buffer, the message received next is written to the last message
object, and the previous message is overwritten.
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■ Reading from the FIFO Buffer
To use the CPU to read the content of the reception message object, write the reception message No. to the
IFx command request register. Then, the data is transferred to the message interface register, and can be
read by the CPU. To do this, set the IFx command mask register’s WR/RD to "0" (read), TxRqst/
NewDat=1, IntPnd=1, and reset the NewDat and IntPnd bits to "0".
To ensure the function of the FIFO buffer, the reception message object having the smallest message No. in
the FIFO buffer must be read first.
Figure 14.5-4 shows how the CPU processes the message objects concatenated by the FIFO buffer.
Figure 14.5-4 Processing of FIFO Buffer by CPU
Start
Message interrupt
Read CAN interrupt register.
8000H
0000H
Value of CAN interrupt register
Other than 8000H and 0000H
Execute status interrupt.
Message No. =
Value of CAN interrupt register
End (Normal processing)
Write (Message No.) to
IFx command request register.
Read message interface register
(Reset: NewDat=0, IntPnd=0)
Read IFx message control register.
No
NewDat = 1
Yes
Read IFx message data register A, B.
Yes
EoB = 1
No
Message No. = Message No. 1
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14.5.5
Interrupt Function
14.5 CAN Controller Functions
This section describes interrupt processing using the status interrupt (IntId=8000H) and
message interrupt (IntId message No.).
When two or more interrupts are pending, the CAN interrupt register shows the interrupt code of the
highest priority among the pending codes. The time order specified to the interrupt codes is ignored, and
the interrupt code of the highest priority is always shown. The interrupt code is retained until it is cleared
by the CPU.
The status interrupt (IntId bit=8000H) has the highest priority.
The priority of the message interrupt is set higher for the message with a smaller message No., and is set
lower for the message with a larger message No.
The message interrupt is cleared by clearing the IntPnd bit in the message object. The status interrupt is
cleared by reading the CAN status register.
The IntPnd bit in the CAN interrupt pending register indicates whether an interrupt is pending or not. If
there is no pending interrupt, the IntPnd is "0".
When the IntPnd bit is set to "1" while the IE bit in the CAN control register and the TxIE and RxIE bits in
the IFx message control register are "1", an interrupt signal to the CPU becomes active. The interrupt signal
is retained to be active until the CAN interrupt pending register is cleared to "0" (interrupt factor reset), or
until the IE bit in the CAN control register is reset to "0".
When the CAN interrupt register is 8000H, it indicates that the CAN status register is updated by the CAN
controller. This interrupt has the highest priority. The interrupt by updating the CAN status register can be
used to enable or disable the setting of the CAN interrupt register with the EIE and SIE bits in the CAN
control register. The interrupt signal to the CPU can be controlled with the IE bit in the CAN control
register.
The RxOk, TxOk, and LEC bits in the CAN status register can be updated (reset) by writing data from the
CPU. This writing, however, cannot set or reset interrupt.
When the CAN interrupt register is set to the value other than 8000H and 0000H, it indicates that the
message interrupt is pending, and the pending message interrupt of the highest priority is shown.
The CAN interrupt register is updated even when the IE bit is reset.
The factor of the message interrupt to the CPU can be checked with the CAN interrupt register or CAN
interrupt pending register. (Refer to "14.4.4 Message Handler Register".) It is possible to clear a
message interrupt and read the message data simultaneously. When the message interrupt indicated by the
CAN interrupt register is cleared, the interrupt of the second highest priority is set to the CAN interrupt
register and waits for the next interrupt processing. When no interrupt exists, the CAN interrupt register
indicates 0000H.
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• The status interrupt (IntId=8000H) is cleared by the read access of the CAN status register.
• The status interrupt (IntId=8000H) is not triggered by the write access to the CAN status register.
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14.5.6
Bit Timing
This section describes the overview of bit timing and the bit timing operations in the
CAN controller.
Each CAN node in the CAN network has its own clock oscillator (generally, a quartz oscillator). The time
parameters of the bit time can be configured individually for the CAN nodes. Even when the oscillation
cycles (fosc) of the CAN nodes vary, a common bit rate can be created.
The frequencies of these oscillators vary a little depending on the change in temperature or voltage, or the
deterioration of components. As long as the variations remain within the allowable range of the oscillator
(df), the CAN node can compensate different bit rate by re-synchronizing it with the bit stream.
The bit time is divided into four segments in accordance with the CAN specification (Refer to Figure 14.55.). It consists of a synchronization segment (Sync_Seg), a propagation time segment (Prop_Seg), phase
buffer segment 1 (Phase_Seg1), and phase buffer segment 2 (Phase_Seg2). Each segment consists of
programmable time quantities (Refer to Table 14.5-1.). The basic unit time quantity (tq) of the bit time is
defined with the CAN clock (fsys) and baud rate prescaler (BRP) as follows:
tq = BRP / fsys
The CAN clock (fsys) is a clock generated by the CAN prescaler. The synchronization segment (Sync_Seg)
expresses the timing within the bit time where the edge of the CAN bus is expected. The propagation time
segment (Prop_Seg) compensates the physical delay time in the CAN network. The phase buffer segments
(Phase_Seg1, Phase_Seg2) designate sampling points. The re-synchronization jump width (SJW) defines
the width of the sampling point movement during re-synchronization in order to compensate an edge phase
error.
Figure 14.5-5 Bit Timing
1 bit time (BT)
Sync
_Seg
Prop_Seg
1 unit time (tq)
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Phase_Seg1
Phase_Seg2
Sampling point
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Table 14.5-1 CAN Bit Time Parameters
Parameter
Range
Function
BRP
[1-32]
Sync_Seg
1 tq
Prop_Seg
[1-8] tq
Compensation for the physical delay time
Phase_Seg1
[1-8] tq
Compensation for the edge phase error before the sample point.
It may be temporarily extended due to synchronization.
Phase_Seg2
[1-8] tq
Compensation for the edge phase error after the sample point.
It may be temporarily shortened due to synchronization.
SJW
[1-4] tq
Re-synchronization jump width
It is not longer than either of the phase buffer segments.
Definition of the length of time quantity (tq)
The length is fixed. Synchronization with the system clock
Figure 14.5-6 shows the bit timing in the CAN controller.
Figure 14.5-6 Bit Timing in CAN Controller
1 bit time (BT)
Sync
_Seg
TEG1
1 unit time
(tq)
402
TEG2
Sampling point
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Table 14.5-2 CAN Controller Parameters
Parameter
Range
Function
BRPE,BRP
[0-1023]
Definition of the length of time quantity (tq).
The prescaler can be expanded up to 1024 by using the bit timing register and prescaler expansion register.
Sync_Seg
1 tq
TSEG1
[1-15] tq
Time segment before the sampling point.
It corresponds to Prop_Seg and Phase_Seg1.
It can be controlled by the bit timing register.
TSEG2
[0-7] tq
Time segment after the sampling point.
It corresponds to Phase_Seg2.
It can be controlled by the bit timing register.
SJW
[0-3] tq
Re-synchronization jump width.
It can be controlled by the bit timing register.
Synchronization with the CAN clock.
The length is fixed.
The relationships between the parameters are as follows:
tq = ([BRPE,BRP] + 1) / fsys
BT = SYNC_SEG + TEG1 + TEG2
= (1 + (TSEG1 + 1) + (TSEG2 + 1)) × tq
= (3 + TSEG1 + TSEG2) × tq
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14.5.7
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Test Mode
This section describes the setting procedure and operations of the test mode.
■ Setting the Test Mode
Setting the Test bit in the CAN control register to "1" activates the test mode. In the test mode, the Tx1,
Tx0, LBack, Silent, and Basic bits in the CAN test register are enabled.
When the Test bit in the CAN control register is reset to "0", all test register functions are disabled.
■ Silent Mode
Setting the Silent bit in the CAN test register to "1" sets the CAN controller to the silent mode.
In the silent mode, data frames and remote frames can be received, but only recessives are output to the
CAN bus, and messages and ACK are not transmitted.
When the CAN controller is requested to send dominant bits (ACK bit, overload flag, active error flag),
they are sent to the RX side by the fold-back circuit inside of the CAN controller. This operation means
that the RX side receives dominant bits which are sent back from the inside of the CAN controller although
the status is recessive on the CAN bus.
In the silent mode, the traffic on the CAN bus can be analyzed without being affected by the transmission
of dominant bits (ACK bit, error flag).
Figure 14.5-7 shows the CAN controller in the silent mode.
Figure 14.5-7 CAN Controller in Silent Mode
CAN_TX
CAN_RX
CAN controller
Silent bit = 1
Tx
Rx
CAN Core
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■ Loop-back Mode
Setting the LBack bit in the CAN test register to "1" sets the CAN controller to the loop-back mode.
The loop-back mode can be used for the self-diagnosis function.
In the loop-back mode, the TX and RX sides are connected inside the CAN controller. The message sent by
the CAN controller is treated as a message received by the RX side, and the message which passed the
acceptance filter is stored in the reception buffer.
Figure 14.5-8 shows the CAN controller in the loop-back mode.
Figure 14.5-8 CAN Controller in Loop-back Mode
CAN_TX
CAN_RX
Tx
Rx
CAN controller
CAN Core
To maintain the independence from external signals, the dominant bits in the acknowledge slot of a data/
remote frame are not sampled. Consequently, the CAN controller does not generate acknowledge errors,
which it normally generates, in this test mode.
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■ Combination of the Silent Mode and Loop-back Mode.
Setting both LBack and Silent bits in the CAN test register to "1" enables the combined operation of the
loop-back mode and silent mode.
This mode can be used for a hot self-test. In a hot self-test, the test of the CAN controller in the loop-back
mode provides fixed output of recessives to the CAN_TX pin and ignores the input from the CAN_RX pin.
Consequently, the test does not affect the operation of the CAN system.
Figure 14.5-9 shows the CAN controller when the silent mode and the loop-back mode are combined.
Figure 14.5-9 CAN Controller When Silent Mode and Loop-back Mode Are Combined
CAN_TX
CAN_RX
CAN controller
LBack bit,Silent bit = 1
Tx
Rx
CAN Core
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■ Basic Mode
Setting the Basic bit in the CAN test register to "1" sets the CAN controller in the basic mode.
In the Basic mode, the CAN controller operates without using the message RAM.
The IF1 message interface register is used to control transmission.
Before starting message transmission, set the content to be transmitted in the IF1 message interface register.
Then, request transmission by setting the BUSY bit in the IF1 command request register to "1". Setting the
BUSY bit to "1" indicates that the IF1 message interface register is locked, or transmission is pending.
When the BUSY bit is set to "1", the CAN controller operates as follows:
As soon as the CAN bus becomes idle, the content of the IF1 message interface register is loaded to the
transmission shift register and transmission starts. When the transmission is complete successfully, the
BUSY bit is reset to "0", and the locked IF1 message interface register is unlocked.
When transmission is pending, you can discontinue the transmission by resetting the BUSY bit in the IF1
command request register to "0". If the BUSY bit is reset to "0" during transmission, the re-transmission
which is performed in the cases of arbitration loss or error is disabled.
The IF2 message interface register is used to control reception.
All messages are received without using the acceptance filter. Setting the BUSY bit in the IF2 command
request register to "1" enables reading the content of the received message.
When the BUSY bit is set to "1", the CAN controller operates as follows:
The received message (content of the reception shift register) is stored in the IF2 message interface register
without using the acceptance filter.
When a new message is stored in the IF2 message interface register, the CAN controller sets the NewDat
bit to "1". If another new message is received while the NewDat bit is "1", the CAN controller sets the
MsgLst bit to "1".
• In the basic mode, the control mode settings of all message objects and IFx command mask registers
concerning the control/status bit are invalid.
• The message No. of the command request register is invalid.
• The NewDat and MsgLst bits in the IF2 message control register operate as normal, DLC3 to DLC0
show the received DLC, and other control bits are read as "0".
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■ Software Control by the CAN_TX Pin
CAN_TX, the CAN transmission pin, has the following four output functions:
• Serial data output (normal output)
• CAN sampling point signal output to monitor the bit timing of the CAN controller
• Fixed output of dominants
• Fixed output of recessives
The fixed outputs of dominants and recessives can be used to check the physical layer of the CAN bus as
well as to monitor CAN_RX of the CAN reception pin.
The output mode of the CAN_TX pin can be controlled by the Tx1 and Tx0 bits in the CAN test register.
To use the CAN message transmission, or the loop-back, silent, or basic mode, you need to set CAN_TX to
the serial data output.
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14.5.8
Software Initialization
14.5 CAN Controller Functions
This section describes the details of the software initialization.
The factors that cause software initialization are as follows:
• Hardware reset
• Setting the Init bit in the CAN control register
• Transition to the bus-off status
The reset by hardware initializes everything other than the message RAM (except for MsgVal, NewDat,
IntPnd, and TxRqst bits). After the hardware reset, the message RAM should be initialized by the CPU, or
the message RAM’s MsgVal must be set to "0". To set a bit timing register, set it before clearing the Init bit
in the CAN control register to "0".
The Init bit in the CAN control register is set to "1" when the following occurs:
• The CPU writes "1".
• Hardware reset
• Bus-off
When the Init bit is set to "1", all message transmission/reception on the CAN bus is stopped, and the
CAN_TX pin for the CAN bus output is set to recessive output. (Except for the CAN_TX test mode).
When the Init bit is set to "1", no error counters and registers change.
When the Init and CCE bits in the CAN control register are set to "1", the bit timing register and prescaler
expansion register for baud rate control can be set.
Resetting the Init bit to "0" terminates the software initialization. The Init bit can be reset to "0" only by the
access from the CPU.
When 11-bit recessives continuously occur (= bus idle) after the Init bit was reset to "0", messages are
transferred after being synchronized with the data transfer on the CAN bus.
Before changing the message object masks, ID, XTD, EoB, and RmtEn, set MsgVal to invalid.
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14.5.9
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CAN Clock Prescaler
This section describes the switching of the CAN clock while PLL is running.
■ Block Diagram
Figure 14.5-10 shows the CAN Clock Prescaler block diagram.
The clock provided to the CAN is decided according to the setting of the CAN clock prescaler register
(CANPRE).
Figure 14.5-10 CAN Clock Prescaler Block Diagram
CPU clock
CAN
Interface
Clock
unit
Clock
Divider
CAN
Controller
X0
PLL
CPCK[1:0]
DVC[3:0]
CANPRE
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■ Clock Switching Procedure
The following procedure is recommended to switch the clock by using the CAN clock prescaler.
Figure 14.5-11 Clock Switching Procedure
Switching CAN clock :
OSCILLATOR -> PLL
Switching CAN clock :
PLL -> OSCILLATOR
Set bit Init in the CAN
Control Register
Set bit Init in the CAN
Control Register
Enable PLL
Set prescaler value
Wait for PLL Lock Time
Disable PLL
Set prescaler value
Reset bit Init in the CAN
Control Register
Reset bit Init in the CAN
Control Register
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■ CAN Clock Frequency
The following table shows the CAN clock frequency generated by setting CPCKS[1:0] and DVC[3:0] of
CANPRE (When a 18 MHz quartz oscillator is connected).
Table 14.5-3 CAN Clock Frequency
DVC[3:0]
CPCKS[1:0]=00B
(when 72 MHz CPU
clock is selected)
CPCKS[1:0]=01B
(when 144 MHz PLL
output is selected)
CPCKS[1:0]=11B
(when 18 MHz source oscillation
clock is selected)
0000B
72.00 MHz (Setting disabled)
144.00 MHz (Setting disabled)
18.00 MHz
0001B
36.00 MHz (Setting disabled)
72.00 MHz (Setting disabled)
9.00 MHz
0010B
24.00 MHz (Setting disabled)
48.00 MHz (Setting disabled)
6.00 MHz
0011B
18.00 MHz
36.00 MHz (Setting disabled)
4.50 MHz
0100B
14.40 MHz
28.80 MHz (Setting disabled)
3.60 MHz
0101B
12.00 MHz
24.00 MHz (Setting disabled)
3.00 MHz
0110B
10.29 MHz
20.57 MHz (Setting disabled)
2.57 MHz
0111B
9.00 MHz
18.00 MHz
2.25 MHz
1000B
8.00 MHz
16.00 MHz
2.00 MHz
1001B
7.20 MHz
14.40 MHz
1.80 MHz
1010B
6.55 MHz
13.09 MHz
1.64 MHz
1011B
6.00 MHz
12.00 MHz
1.50 MHz
1100B
5.54 MHz
11.08 MHz
1.38 MHz
1101B
5.14 MHz
10.29 MHz
1.29 MHz
1110B
4.80 MHz
9.60 MHz
1.33 MHz
1111B
4.50 MHz
9.00 MHz
1.25 MHz
• Before changing the value of the CAN prescaler setting bit, set the initialization bit in the CAN control
register to "1" and stop the operation of all buses.
• Set the CAN clock to 20 MHz or lower.
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CHAPTER 15
LIN-UART
This chapter describes functions and operations of the
LIN-compatible LIN-UART.
15.1 Overview of LIN-UART
15.2 Configuration of LIN-UART
15.3 LIN-UART Registers
15.4 LIN-UART Interrupts
15.5 LIN-UART Baud Rate Setting
15.6 LIN-UART Operations
15.7 Notes on Using LIN-UART
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CHAPTER 15 LIN-UART
15.1 Overview of LIN-UART
15.1
MB91461
Overview of LIN-UART
LIN (Local Interconnect Network)-compatible LIN-UART (Universal Asynchronous
Receiver and Transmitter) is a general-purpose serial data communication interface
which achieves asynchronous/synchronous communication with external devices. The
LIN-UART supports bidirectional communication functions (normal mode), master/slave
communication functions (multiprocessor mode in a master system), and LIN-bus
system (both master and slave operations).
■ Overview
The LIN-UART is a general-purpose serial data communication interface used for data transmission/
reception with other CPUs or peripheral circuits, especially with LIN devices. Table 15.1-1 lists the LINUART Functions.
Table 15.1-1 LIN-UART Functions (1 / 2)
Item
Function
Data buffer
Full-duplex buffer
Serial input
In asynchronous mode, a received value is determined by 5 oversampling operations.
Transfer mode
• Clock synchronous (start/stop synchronization or start/stop bit selectable)
• Clock asynchronous (start/stop bit)
Transfer rate
• Dedicated 15-bit baud rate generator is provided.
• External clock input can be used, which is adjustable by a reload counter.
Data length
• 7 bits (Cannot be used in synchronous and LIN modes)
• 8 bits
Signal mode
NRZ (Non Return Zero) format
Start bit timing
In asynchronous mode, clock synchronization with the falling edge of the start bit.
Reception error detection
• Framing error
• Overrun error
• Parity error
Interrupt request
• Reception interrupt (reception completion/reception error detection)
• Transmission interrupt (transmission completion)
• Bus Idle interrupt (belongs to reception interrupt)
• LIN-Synch-Break interrupt (belongs to reception interrupt)
Master/slave communication
function
(multiprocessor mode)
One-to-many (One master and multiple slaves) communication available
(supported by either of a master or slave system)
Synchronization mode
Function as master or slave LIN-UART
Transmission cable
Direct access available
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15.1 Overview of LIN-UART
MB91461
Table 15.1-1 LIN-UART Functions (2 / 2)
Item
Function
LIN bus options
• Operation as a master device
• Operation as a slave device
• Generation of LIN-Synch-Break
• Detection of LIN-Synch-Break
• Detection of the start/stop edges in the LIN-Synch-Field with ICU
Synchronous serial clock
The synchronous serial clock can be continuously output from the SCK pin for
synchronous communication using start/stop bits.
Clock delay option
Special synchronous clock mode for clock delay (for SPI)
■ Operation Modes of LIN-UART
The LIN-UART offers four operation modes which are specified with the MD0 and MD1 bits in the serial
mode register (SMR). Mode 0 and mode 2 are used for bidirectional serial communication, and mode 1 is
for master/slave communication. Mode 3 is for LIN master/slave communication.
Table 15.1-2 Operation Modes of LIN-UART
Data length
Operation mode
Parity
disabled
0
Normal mode
bit7 or bit8
1
Multiprocessor mode
bit7 or
bit8 + 1 (*2)
2
Normal mode
bit8
3
LIN mode
bit8
Parity
enabled
−
−
Synchronization
mode
Data bit
detection*1
Stop bit
length
Asynchronous
bit1 or bit2
L/M
Asynchronous
bit1 or bit2
L/M
Synchronous
bit0, bit1 or
bit2
L/M
Asynchronous
bit1
L
*1: Indicates that the transfer starts from LSB first or MSB first.
*2: "+1" is used to show the address/data selection in the multiprocessor mode when a parity bit is not used.
Note:
Mode 1 (multiprocessor mode) supports the operations of both the LIN-UART master and slave in a
master/slave system. In mode 3, the functions of the LIN-UART are fixed to 8N1 format and LSB
first.
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15.1 Overview of LIN-UART
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When the mode is changed, the LIN-UART stops transmission and reception, and waits for and changes to
the new action.
Table 15.1-3 lists the mode bit settings.
Table 15.1-3 Mode Bit Settings
416
MD1
MD0
Mode
Function
0
0
0
Asynchronous (Normal mode)
0
1
1
Asynchronous (Multiprocessor mode)
1
0
2
Synchronous (Normal mode)
1
1
3
Asynchronous (LIN mode)
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CHAPTER 15 LIN-UART
MB91461
15.2
Configuration of LIN-UART
15.2 Configuration of LIN-UART
This section describes the configuration of the LIN-UART.
■ LIN-UART Block Diagram
The LIN-UART consists of the following blocks:
• Reload counter
• Reception control circuit
• Reception shift register
• Reception data register (RDR)
• Transmission control circuit
• Transmission shift register
• Transmission data register (TDR)
• Error detection circuit
• Oversampling unit
• Interrupt generation circuit
• LIN-Synch-Break and Synch-Field detection circuit
• Bus Idle detection circuit
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Extended communication control register (ECCR)
• Extended communication status/control register (ESCR)
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15.2 Configuration of LIN-UART
MB91461
■ LIN-UART Block Diagram
Figure 15.2-1 LIN-UART Block Diagram
PE
ORE
FRE
Transmission clock
CLK
TIE
Reception clock
Reload
Counter
SCK
RIE
RECEPTION
CONTROL
CIRCUIT
Pin
LBD
Interrupt Generation
circuit
BIE
Transmission
Start circuit
Start bit
Detection circuit
SIN
LBIE
TRANSIMISSION
CONTROL
CIRCUIT
RBI
TBI
Pin
Restart Reception
Reload Counter
Oversampling
Unit
Received Bit
counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
Transmission
IRQ
SOT
Pin
RDRF
Reception
complete
SIN
Signal to
ICU
Reception shift
register
LIN sync break
and Synch Field
Detection circuit
Reception
IRQ
TDRE
SOT
SIN
Transmission
shift register
LIN break
generation
circuit
Transmission
start
Error
Detection
RDR
Bus Idle
Detection circuit
TDR
STR
PE
ORE
FRE
RBI
LBR
LBL1
LBL0
TBI
LBD
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
418
SSR
register
MD1
MD0
(OTO)
(EXT)
(REST)
UPCL
SCKE
SOE
SMR
register
PEN
P
SBL
CL
AD
CRE
RXE
TXE
SCR
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
ESCR
Rregister
CCO
SCES
FUJITSU MICROELECTRONICS LIMITED
LBR
MS
SPI
SSM
BIE
RBI
ECCR
register
TBI
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CHAPTER 15 LIN-UART
15.2 Configuration of LIN-UART
MB91461
■ Description of the Blocks
● Reload counter
The reload counter operates as a dedicated baud rate generator. The transmission/reception clocks are
generated from an external clock or an internal clock. The reload counter has a 15-bit register to store a
reload value. The actual count value of the transmission reload counter can be read from the value of
BGR0/BGR1.
● Reception control circuit
The reception control circuit consists of a received bit counter, a start bit detection circuit, and a received
parity counter.
The received bit counter counts received data bits. When the reception of one data item of the specified
data length is complete, the received bit counter sets a reception data register full flag.
The start bit detection circuit detects a start bit from serial input signals, and sends out a signal to the reload
counter in synchronization with the falling edge of the start bit.
The received parity counter calculates the parity of the received data.
● Reception shift register
The reception shift register captures the received data input from the SIN pin by shifting the data bit by bit.
When the reception is complete, the reception shift register transfers the received data to the reception data
register (RDR).
● Reception data register (RDR)
The reception data register retains the received data. Serial input data is converted and stored into this
register.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, a transmission start circuit, and a
transmission parity counter.
The transmission bit counter counts transmission data bits. When the transmission of one data item of the
specified data length is complete, the transmission bit counter sets a transmission data register empty flag.
The transmission start circuit starts transmission when data is written to the TDR.
If parity is enabled, the transmission parity counter generates a parity bit of the transmission data.
● Transmission shift register
The transmission shift register shifts the transmission data written to the transmission data register (TDR)
and outputs the data bit by bit to the SOT pin.
● Transmission data register (TDR)
Transmission data is set to the transmission data register. The data written to this register is converted into
serial data and is output.
● Error detection circuit
The error detection circuit checks whether an error occurred during the last reception. When it detects an
error occurrence, it sets the corresponding error flag.
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● Oversampling unit
The oversampling unit repeats oversampling of the data input from the SIN pin for five times. This unit is
disabled in the synchronous operation mode.
● Interrupt generation circuit
The interrupt generation circuit controls every interrupt. When an interrupt is enabled and an interrupt
factor for the interrupt arises, the interrupt is generated immediately.
● LIN-Break and Synch-Field detection circuit
The LIN-Break and LIN-Synch-Break detection circuit detects a LIN-Break when the LIN master node is
sending out a message handler. When a LIN-Break is detected, the LBD flag bit is generated. The first and
fifth falling edges in the Synch-Field are detected by this circuit. Then an internal signal is sent to the input
capture in order to measure an accurate serial clock cycle of the transmission master node.
● LIN-Break generation circuit
The LIN-Break generation circuit generates a LIN-Synch-Break of a specified length.
● Bus Idle detection circuit
The Bus Idle detection circuit detects the status where neither reception nor transmission is performed (bus
idle). When such a status is detected, the circuit generates flag bits TBI and RBI.
● Serial mode register (SMR)
The serial mode register is used for the following operations:
• Select the operation mode of the LIN-UART.
• Select clock input.
• Select whether the external clock is connected 1-to-1 or connected to the reload-counter.
• Restart the dedicated reload timer.
• Reset the LIN-UART (The register settings are saved.).
• Enable the output at the serial output pin (SOT).
• Switch the input/output at the serial clock pin (SCK).
● Serial control register (SCR)
The serial control register is used for the following operations:
• Select whether to enable or disable parity bits.
• Select the type of parity bits.
• Specify the stop bit length.
• Specify the data length.
• Specify the frame data format in mode 1.
• Clear an error flag.
• Enable transmission.
• Enable reception.
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15.2 Configuration of LIN-UART
MB91461
● Serial status register (SSR)
The serial status register checks the transmission/reception and error statuses. It is also used to enable
transmission/reception interrupts and set the transfer direction (LSB first/MSB first).
● Extended status/control register (ESCR)
The extended status/control register sets the LIN functions. It specifies the direct access to the SIN and
SOT pins and the settings for the LIN-UART synchronous clock mode.
● Extended communication control register (ECCR)
The extended communication control register specifies the Bus Idle detection interrupt, sets the
synchronous clock, and generates a LIN-Break.
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CHAPTER 15 LIN-UART
15.3 LIN-UART Registers
15.3
MB91461
LIN-UART Registers
Figure 15.3-1 shows the LIN-UART registers.
■ LIN-UART Registers
Figure 15.3-1 LIN-UART Registers
SCR
Address: 000040H, 000048H, bit15
000050H, 000058H,
000060H, 000068H, PEN
000070H
14
13
12
11
10
9
8
P
SBL
CL
AD
CRE
RXE
TXE
Read/Write
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
SMR
Address: 000041H, 000049H, bit7
000051H, 000059H,
000061H, 000069H, MD1
000071H
Read/Write
R/W
R/W
R/W
R/W
W
W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSR
Address: 000042H, 00004AH, bit15
000052H, 00005AH,
000062H, 00006AH, PE
000072H
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
1
0
0
0
Address: 000043H, 00004BH,
000053H, 00005BH,
000063H, 00006BH,
000073H
bit7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
RDR/TDR
ESCR
Address: 000044H, 00004CH, bit15
000054H, 00005CH,
000064H, 00006CH, LBIE
000074H
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
X
0
0
(Continued)
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15.3 LIN-UART Registers
MB91461
(Continued)
ECCR
Address: 000045H, 00004DH,
000055H, 00005DH,
000065H, 00006DH,
000075H
bit7
6
5
4
3
2
1
0
Reserved
LBR
MS
SCDE
SSM
BIE
RBI
TBI
Read/Write
−
W
R/W
R/W
R/W
R/W
R
R
Initial value
0
0
0
0
0
0
X
X
14
13
12
11
10
9
8
B14
B13
B12
B11
B10
B09
B08
BGR1
Address: 000080H, 000082H, bit15
000084H, 000086H,
Reserved
000088H, 00008AH,
00008CH
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
BGR0
Address: 000081H, 000083H,
000085H, 000087H,
000089H, 00008BH,
00008DH
bit7
6
5
4
3
2
1
0
B07
B06
B05
B04
B03
B02
B01
B00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
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15.3.1
MB91461
Serial Control Register (SCR)
The serial control register (SCR) specifies parity bits, selects the stop bit length and
data length, selects the frame data format in mode 1, clears a reception error flag, and
enable transmission/reception.
■ Serial Control Register (SCR)
Figure 15.3-2 Bit Configuration of Serial Control Register (SCR)
SCR
Address: 000040H, 000048H, bit15
000050H, 000058H,
000060H, 000068H, PEN
000070H
14
13
12
11
10
9
8
P
SBL
CL
AD
CRE
RXE
TXE
Read/Write
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit15] PEN: Parity enable bit
Table 15.3-1 Parity Enable Bit
PEN
Parity enable
0
Parity disabled [Initial value]
1
Parity enabled
This bit selects whether or not to add parity to the transmission data in the serial asynchronous mode.
Parity is detected during reception.
Parity is added in mode 0, and in mode 2 when the SSM bit in the ECCR is set. In mode 3 (LIN mode),
this bit is fixed to "0" (Parity disabled).
[bit14] P: Parity selection bit
Table 15.3-2 Parity Selection Bit
P
Parity selection
0
Even parity [Initial value]
1
Odd parity
When parity is enabled, this bit selects whether to use even parity (0) or odd parity (1).
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[bit13] SBL: Stop bit length selection bit
Table 15.3-3 Stop Bit Length Selection Bit
SBL
Stop bit length
0
1 bit [Initial value]
1
2 bits
This bit selects the stop bit length of an asynchronous data frame. When the SSM bit in the ECCR is set,
the stop bit length is selected also for a synchronous data frame. In mode 3 (LIN mode), this bit is fixed
to "0" (1 bit).
[bit12] CL: Data length selection bit
Table 15.3-4 Data Length Selection Bit
CL
Data length
0
7 bits [Initial value]
1
8 bits
This bit specifies the length of transmission/reception data. In modes 2 and 3, this bit is fixed to "1" (8
bits).
[bit11] AD: Address/data selection bit
Table 15.3-5 Address/Data Selection Bit
AD
Address/data bit
0
Data bit [Initial value]
1
Address bit
This bit specifies the data format used in the multiprocessor mode (mode 1). Writing to this bit is used
for the master CPU, and reading this bit is used for the slave CPU. Value "1" indicates an address
frame, and "0" indicates a data frame.
Note:
For the usage of the AD bit, refer to "15.7 Notes on Using LIN-UART".
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[bit10] CRE: Reception error flag clear bit
Table 15.3-6 Reception Error Flag Clear Bit
Reception error clear
CRE
Write
0
Invalid [Initial value]
1
Clear all reception errors
(PE, FRE, ORE).
Read
Read value is always "0".
This bit clears the PE, FRE, and ORE flags of the serial status register (SSR). It also clears a reception
error interrupt factor.
Writing "1" to this bit clears the error flags. Writing "0" is invalid.
Reading this bit always returns "0".
Note:
When the reception error flag is cleared without disabling the reception, the reception is interrupted
once at that timing and then it restarts. Therefore, when the reception is restarted, Incorrect data
might be received.
[bit9] RXE: Reception enable bit
Table 15.3-7 Reception Enable Bit
RXE
Reception enable
0
Disable reception. [Initial value]
1
Enable reception.
This bit enables the LIN-UART’s reception operation. When this bit is set to "0", the LIN-UART stops
receiving data frames. This bit remains invalid for the LIN-Break detection in modes 0 and 3.
[bit8] TXE: Transmission enable bit
Table 15.3-8 Transmission Enable Bit
TXE
Transmission enable
0
Disable transmission. [Initial value]
1
Enable transmission.
This bit enables the LIN-UART’s transmission operation. When this bit is set to "0", the LIN-UART
stops transmitting data frames.
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15.3.2
Serial Mode Register (SMR)
The serial mode register (SMR) selects the operation mode and baud rate clock. It also
specifies the I/O direction of the serial clock (SCK) and enables serial outputs.
■ Serial Mode Register (SMR)
Figure 15.3-3 Bit Configuration of Serial Mode Register (SMR)
SMR
Address: 000041H, 000049H, bit7
000051H, 000059H,
000061H, 000069H, MD1
000071H
6
5
4
3
2
1
0
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
Read/Write
R/W
R/W
R/W
R/W
W
W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit7, bit6] MD1, MD0: Operation mode selection bit
Table 15.3-9 Operation Mode Selection Bit
MD0
MD1
Operation mode setting
0
0
Mode 0: Asynchronous normal mode [Initial value]
1
0
Mode 1: Asynchronous multiprocessor mode
0
1
Mode 2: Synchronous mode
1
1
Mode 3: Asynchronous LIN mode
These bits are used to set the operation mode of the LIN-UART.
[bit5] OTO: 1-to-1 external clock selection bit
Table 15.3-10 1-to-1 External Clock Selection Bit
OTO
External clock selection
0
Use an external clock for the baud rate generator (reload counter).
[Initial value]
1
Use an external clock as a serial clock.
When this bit is set, an external clock is directly used as a serial clock for the LIN-UART. This function
is used when the LIN-UART operates as a slave in the synchronous mode.
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[bit4] EXT: External clock selection bit
Table 15.3-11 External Clock Selection Bit
EXT
External serial clock enable
0
Use the built-in baud rate generator (reload counter). [Initial value]
1
Use an external clock as a serial clock.
This bit selects the clock used for the reload counter.
[bit3] REST: Transmission reload counter restart bit
Table 15.3-12 Transmission Reload Counter Restart Bit
Transmission reload counter restart
REST
Write
0
Invalid [Initial value]
1
Restart the counter.
Read
Read value is always "0".
Writing "1" to this bit restarts the reload counter. Writing "0" is invalid.
Reading this bit always returns "0".
[bit2] UPCL: LIN-UART clear bit (software reset)
Table 15.3-13 LIN-UART Clear Bit (Software Reset)
LIN-UART clear (software reset)
UPCL
Write
0
Invalid [Initial value]
1
Reset the LIN-UART.
Read
Read value is always "0".
When "1" is written to this bit, the LIN-UART is reset immediately, but the register setting values are
saved.
Reception/transmission is discontinued.
All error flags are cleared and the reception data register (RDR) is set to 00H.
Writing "0" is invalid.
Reading this bit always returns "0".
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[bit1] SCKE: Serial clock output enable
Table 15.3-14 Serial Clock Output Enable
SCKE
Serial clock output enable
0
External clock input [Initial value]
1
Serial clock output
This bit controls the input/output at the serial clock pin (SCK).
When this bit is set to "0", the SCK pin operates as a general-purpose port/serial clock input pin. When
this bit is set to "1", the pin operates as a serial clock output pin.
Note:
To use the SCK pin for a serial clock input (SCKE=0), set the port as an input port. To use it for a
serial clock output, you need to set the SCKE bit as well as the port function register (PFR)
corresponding to the SCK pin. For details of the port function register setting, refer to "CHAPTER 9
I/O PORT".
Also, select an external clock by setting the external clock selection bit (EXT=1).
[bit0] SOE: Serial data output enable bit
Table 15.3-15 Serial Data Output Enable Bit
SOE
Serial data output enable
0
Disable SOT output. [Initial value]
1
Enable SOT output.
This bit enables serial output.
When this bit is set to "1", serial data output is enabled.
Note:
To use the SOT pin for serial output, you need to set the SOE bit as well as the corresponding port
function register (PFR). For details of the port function register setting, refer to "CHAPTER 9 I/O
PORT".
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15.3 LIN-UART Registers
15.3.3
MB91461
Serial Status Register (SSR)
The serial status register (SSR) shows the transmission/reception status and the
occurrence of errors. It also controls transmission/reception interrupts.
■ Serial Status Register (SSR)
Figure 15.3-4 Bit Configuration of Serial Status Register (SSR)
SSR
Address: 000042H, 00004AH, bit15
000052H, 00005AH,
PE
000062H, 00006AH,
000072H
14
13
12
11
10
9
8
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
1
0
0
0
[bit15] PE: Parity error flag bit
Table 15.3-16 Parity Error Flag Bit
PE
Parity error
0
No parity error occurred. [Initial value]
1
Parity error occurred during reception.
If a parity error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written to
the CRE bit in the serial control register (SCR).
When this bit and the RIE bit are "1", a reception interrupt request is output.
When this flag is set, the data in the reception data register (RDR) is invalid.
[bit14] ORE: Overrun error flag bit
Table 15.3-17 Overrun Error Flag Bit
ORE
Overrun error
0
No overrun error occurred. [Initial value]
1
Overrun error occurred during reception.
If an overrun error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written
to the CRE bit in the serial control register (SCR).
When this bit and the RIE bit are "1", a reception interrupt request is output.
When this flag is set, the data in the reception data register (RDR) is invalid.
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[bit13] FRE: Framing error flag bit
Table 15.3-18 Framing Error Flag Bit
FRE
Framing error
0
No framing error occurred. [Initial value]
1
Framing error occurred during reception.
If a framing error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written to
the CRE bit in the serial control register (SCR).
When this bit and the RIE bit are "1", a reception interrupt request is output.
When this flag is set, the data in the reception data register (RDR) is invalid.
[bit12] RDRF: Reception data full flag bit
Table 15.3-19 Reception Data Full Flag Bit
RDRF
Reception data register full
0
Reception data register contains no data. [Initial value]
1
Reception data register contains data.
This flag shows the status of the reception data register (RDR).
When received data is stored in the RDR, this bit is set to "1". This bit is cleared to "0" only when the
RDR is read.
When this bit and the RIE bit are "1", a reception interrupt request is output.
[bit11] TDRE: Transmission data empty flag bit
Table 15.3-20 Transmission Data Empty Flag Bit
TDRE
Transmission data register empty
0
Transmission data register contains data.
1
Transmission data register contains no data. [Initial value]
This flag shows the status of the transmission data register (TDR).
This bit is cleared to "0" when transmission data is written to the TDR. This bit is set to "1" when data
is stored into the transmission shift register and transmission starts.
When this bit and the TIE bit are "1", a transmission interrupt request is output.
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[bit10] BDS: Transfer direction selection bit
Table 15.3-21 Transfer Direction Selection Bit
BDS
Transfer direction setting
0
Transmission/reception uses "LSB first" method. [Initial value]
1
Transmission/reception uses "MSB first" method.
Setting this bit selects the transfer direction of the serial transfer data to either of LSB first (BDS=0) or
MSB first (BDS=1).
In mode 3 (LIN mode), this bit is fixed to "0".
Note:
During reading/writing of the serial data register, the high-order side and low-order side of the serial
data is switched. When the value of this bit is changed after data is written to the RDR, the data is
invalid.
[bit9] RIE: Reception interrupt request enable bit
Table 15.3-22 Reception Interrupt Request Enable Bit
RIE
Reception interrupt request enable
0
Disable reception interrupts. [Initial value]
1
Enable reception interrupts.
This bit controls the reception interrupt request to the CPU.
When this bit is set and the reception data flag bit (RDRF) is set to "1" or an error flag (PE, ORE, FRE)
is set, a reception interrupt request is issued.
[bit8] TIE: Transmission interrupt request enable bit
Table 15.3-23 Transmission Interrupt Request Enable Bit
TIE
Transmission interrupt request enable
0
Disable transmission interrupts. [Initial value]
1
Enable transmission interrupts.
This bit controls the transmission interrupt request to the CPU.
When this bit is set and the TDRE bit is set to "1", a transmission interrupt request is issued.
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15.3 LIN-UART Registers
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15.3.4
Transmission/Reception Data Registers (RDR/TDR)
The reception data register (RDR) retains received data, and the transmission data
register retains transmission data. The RDR and TDR are located at the same address.
■ Transmission/Reception Data Registers (RDR/TDR)
Figure 15.3-5 Reception/Transmission Data Registers
RDR/TDR
bit7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Address: 000043H, 00004BH,
000053H, 00005BH,
000063H, 00006BH,
000073H
[bit7 to bit0] D7 to D0: Data registers
Table 15.3-24 Data Registers
Access
Data register
Read
Read from the reception data register
Write
Write to the transmission data register
● Reception
RDR is a register to store received data. The transferred serial data signal received at the SIN pin is
converted in the shift register and stored into this register. If the data length is 7 bits, the most significant
bit (D7) is "0". When reception is complete, the data is stored into this register, and the reception data full
flag bit (SSR: RDRF bit) is set to "1". If a reception interrupt request is enabled in this situation, a reception
interrupt occurs.
Read the RDR when the RDRF bit in the SSR is set to "1". When the RDR is read, the RDRF bit is
automatically cleared to "0". If a reception interrupt is enabled and no reception error occurs, the reception
interrupt is also cleared.
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● Transmission
When transmission is enabled and transmission data is written to the transmission data register, the data is
transferred to the transmission shift register, converted into serial data, and transmitted from the serial data
output (SOT) pin. When the data length is 7 bits, the most significant bit (D7) is not transmitted.
When transmission data is written to this register, the transmission data empty flag bit (SSR: TDRE bit) is
cleared to "0". When the transfer to the transmission shift register is complete, the TDRE bit is set to "1".
When the TDRE bit is "1", the next transmission data can be written to this register. If a transmission
interrupt request is enabled, a transmission interrupt occurs. When a transmission interrupt occurs, or when
the TDRE bit is "1", write the next data.
Note:
The TDR is a write-only register, and the RDR is a read only register. Since these registers are
located at the same address, the read value and write value are different. Therefore, do not access
to these registers with a read-modify-write (RMW) instruction.
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15.3
MB91461
15.3.5
Extended Status/Control Register (ESCR)
LIN-UART Registers
The extended status/control register sets the LIN functions. It also enables the direct
access to the SIN and SOT pins and specifies the LIN-UART synchronous clock mode.
■ Extended Status/Control Register (ESCR)
Figure 15.3-6 Bit Configuration of Extended Control Register (ESCR)
ESCR
Address: 000044H, 00004CH, bit15
000054H, 00005CH,
LBIE
000064H, 00006CH,
000074H
14
13
12
11
10
9
8
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
x
0
0
[bit15] LBIE: LIN-Break detection interrupt enable bit
Table 15.3-25 LIN-Break Detection Interrupt Enable Bit
LBIE
LIN-Break detection interrupt enable
0
Disable LIN-Break interrupts. [Initial value]
1
Enable LIN-Break interrupts.
This bit enables an interrupt which is generated when a LIN-Break is detected.
[bit14] LBD: LIN-Break detection flag bit
Table 15.3-26 LIN-Break Detection Flag Bit
LIN-Break detection
LBD
Write
Read
0
Clear the LIN-Break detection flag.
LIN-Break was not detected.
[Initial value]
1
Invalid
LIN-Break was detected.
When a LIN-Break is detected, this bit is set to "1". This flag bit is cleared when "0" is written to it. If a
LIN-Break detection interrupt has been enabled, the interrupt is also cleared.
For a read-modify-write (RMW) instruction, the return value is always "1". This, however, does not
mean that a LIN-Break was detected.
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[bit13, bit12] LBL1, LBL0: LIN-Break length selection bit
Table 15.3-27 LIN-Break Length Selection Bit
LBL0
LBL1
LIN-Break length
0
0
LIN-Break length is 13 bits. [Initial value]
1
0
LIN-Break length is 14 bits.
0
1
LIN-Break length is 15 bits.
1
1
LIN-Break length is 16 bits.
These bits define the serial bit length of the LIN-Break generated in the LIN-UART. For the LIN-Break
reception, the length is always fixed to 11 bits.
[bit11] SOPE: Serial output pin direct access enable bit
Table 15.3-28 Serial Output Pin Direct Access Enable Bit
SOPE
Serial output pin direct access
0
Disable the direct access to the serial output pin. [Initial value]
1
Enable the direct access to the serial output pin.
Setting this bit to "1" enables the direct writing to the SOT pin.
For details, refer to Table 15.3-30 .
[bit10] SIOP: Serial I/O pin direct access enable bit
Table 15.3-29 Serial I/O Pin Direct Access Enable Bit
Serial I/O pin direct access enable
SIOP
Write (SOPE=1)
0
SOT outputs "0"
1
SOT outputs "1" [Initial value]
Read
The value of SIN is read.
For a normal read instruction, the value at the SIN pin is returned. Writing to this bit sets the value at
the SOT pin. For a read-modify-write (RMW) instruction, the value at SOT is returned.
For details, refer to Table 15.3-30 .
Table 15.3-30 SOPE and SIOP Operations
436
SOPE
SIOP
Write to SIOP
Read from SIOP
0
R/W
The SOT pin is not affected.
The written value is retained.
The value of SIN is read.
1
R/W
Value is written to the SOT pin
and is output.
The value of SIN is read.
1
RMW
The value of the SOT pin is read and written.
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Note:
A setting value of this bit is effective only for the TXE bit of serial control register (SCR) is "0".
[bit9] CCO: Continuous clock output enable bit
Table 15.3-31 Continuous Clock Output Enable Bit
CCO
Continuous clock output (mode 2)
0
Disable continuous clock output. [Initial value]
1
Enable continuous clock output.
When the LIN-UART operates as a master in mode 2 (synchronous mode) and the SCK pin is set for
output, setting this bit enables the continuous serial clock output from SCK.
[bit8] SCES: Serial clock edge selection bit
Table 15.3-32 Serial Clock Edge Selection Bit
SCES
Serial clock edge selection
0
Perform sampling at the rising edge of the clock (normal). [Initial value]
1
Perform sampling at the falling edge of the clock (Inverted clock).
This bit inverts the internal serial clock in mode 2 (synchronous mode). When the LIN-UART operates
as a master in mode 2 (synchronous mode) and the SCK pin is set for output, the output clock is also
inverted.
When the LIN-UART operates as a slave in mode 2, the sampling edge changes from a rising edge to a
falling edge.
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15.3.6
MB91461
Extended Communication Control Register (ECCR)
The extended communication control register (ECCR) specifies the Bus Idle detection
interrupt, sets the synchronous clock, and generates a LIN-Break.
■ Extended Communication Control Register (ECCR)
Figure 15.3-7 Bit Configuration of Extended Communication Control Register
ECCR
bit7
6
5
4
3
2
1
0
Reserved
LBR
MS
SCDE
SSM
BIE
RBI
TBI
Read/Write
−
W
R/W
R/W
R/W
R/W
R
R
Initial value
0
0
0
0
0
0
x
x
Address: 000045H, 00004DH,
000055H, 00005DH,
000065H, 00006DH,
000075H
[bit7] Reserved: Reserved bit
This bit is reserved. Be sure to write "0" to this bit.
[bit6] LBR: LIN-Break setting bit
Table 15.3-33 LIN-Break Setting Bit
LIN-Break setting
LBR
Write
0
Invalid [Initial value]
1
Generate LIN-Break.
Read
Read value is always "0".
When the operation mode is mode 0 or 3, writing "1" to this bit generates a LIN-Break of the length
specified with LBL1 and LBL0 in the ESCR.
[bit5] MS: Master/slave mode selection bit
Table 15.3-34 Master/Slave Mode Selection Bit
MS
Master/slave function in mode 2
0
Master mode (Generates a serial clock.) [Initial value]
1
Slave mode (Receives an external serial clock.)
This bit sets the LIN-UART in mode 2 (synchronous mode) to a master or a slave. When set as a
master, the LIN-UART generates a synchronous clock. When set as a slave, it receives an external
serial clock.
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Note:
When setting the LIN-UART as a slave, set the clock source to an external clock for the 1-to-1
external clock input (SMR: SCKE=0, EXT=1, OTO=1).
[bit4] SCDE: Serial clock delay enable bit
Table 15.3-35 Serial Clock Delay Enable Bit
SCDE
Serial clock delay enable in mode 2
0
Disable clock delay. [Initial value]
1
Enable clock delay.
When the LIN-UART operates in mode 2 and this bit is set, the serial output clock delays one machine
cycle.
[bit3] SSM: Start/stop bit mode enable
Table 15.3-36 Start/Stop Bit Mode Enable
SSM
Start/stop synchronization in mode 2
0
Disable start/stop bits in mode 2. [Initial value]
1
Enable start/stop bits in mode 2.
When the LIN-UART operates in mode 2, setting this bit adds start and stop bits for synchronization. In
the other modes (modes 0, 1, and 3), this bit is fixed to "0".
[bit2] BIE: Bus idle interrupt enable
Table 15.3-37 Bus Idle Interrupt Enable
BIE
Bus idle interrupt enable
0
Disable Bus Idle interrupts. [Initial value]
1
Enable Bus Idle interrupts.
When neither reception nor transmission is performed (RBI=1, TBI=1), this bit enables a reception
interrupt.
Do not use this bit when the SSM bit is "0" in mode 2.
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[bit1] RBI: Reception bus idle flag bit
Table 15.3-38 Reception Bus Idle Flag Bit
RBI
Reception bus idle
0
During reception
1
Reception idle
When nothing is received at the SIN pin, this bit is set to "1".
Do not use this bit when the SSM bit is "0" in mode 2.
[bit0] TBI: Transmission bus idle flag bit
Table 15.3-39 Transmission Bus Idle Flag Bit
TBI
Transmission bus idle
0
During transmission
1
Transmission idle
When nothing is transmitted at the SOT pin, this bit is set to "1".
Do not use this bit when the SSM bit is "0" in mode 2.
Note:
When setting the operation mode of the LIN-UART to mode 2, do not use the BIE, RBI, and TBI bits
if the SSM bit is "0".
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15.3
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15.3.7
Baud Rate/Reload Counter Register (BGR)
LIN-UART Registers
The baud rate/reload counter register (BGR) sets the division ratio of the serial clock. It
can also be used to read the accurate value of the transmission reload counter.
■ Baud Rate/Reload Counter Register (BGR)
Figure 15.3-8 Baud Rate/Reload Counter Register
BGR1
Address: 000080H, 000082H, bit15
000084H, 000086H,
Reserved
000088H, 00008AH,
00008CH
14
13
12
11
10
9
8
B14
B13
B12
B11
B10
B09
B08
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
B07
B06
B05
B04
B03
B02
B01
B00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
BGR0
Address: 000081H, 000083H,
000085H, 000087H,
000089H, 00008BH,
00008DH
[bit15] Reserved: Reserved bit
This bit is reserved. Read value is always "0".
[bit14 to bit8] B14 to B08: Baud rate generator register 1
Table 15.3-40 Baud Rate Generator Register 1
B14 to B08
Baud rate generator register 1
Write
Write bit14 to bit8 of the reload value to the counter.
Read
Read count bit14 to bit8.
[bit7 to bit0] B07 to B00: Baud rate generator register 0
Table 15.3-41 Baud Rate Generator Register 0
B07 to B00
CM71-10159-2E
Baud rate generator register 0
Write
Write bit7 to bit0 of the reload value to the counter.
Read
Read count bit7 to bit0.
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■ Baud Rate/Reload Counter Register (BGR)
The baud rate/reload counter register (BGR) sets the division ratio of the serial clock.
This register can be read/written with byte access or half-word access.
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15.4 LIN-UART Interrupts
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15.4
LIN-UART Interrupts
The LIN-UART provides reception interrupts and transmission interrupts. An interrupt
request is generated when any of the following occurs:
• Received data is stored to the reception data register (RDR), or a reception error
occurs.
• Transmission data is transferred from the transmission data register (TDR) to the
transmission shift register.
• LIN-Break is detected.
• Bus Idle (No transmission/reception operation)
■ LIN-UART Interrupts
Table 15.4-1 shows the interrupt control bits and interrupt factors of LIN-UART.
Table 15.4-1 Interrupt Control Bits and Interrupt Factors of LIN-UART
Reception/
Interrupt
transmission/
request flag bit
ICU
Reception
Transmission
Flag
register
Operation mode
Interrupt factor
0
1
2
3
Interrupt
factor
enable bit
How to clear the
interrupt
request
RDRF
SSR
O
O
O
O
Received data
written to RDR
Read the received
data.
ORE
SSR
O
O
O
O
Overrun error
FRE
SSR
O
O
▲
O
Framing error
PE
SSR
O
X
▲
X
Parity error
LBD
ESCR
O
X
X
O
Detection of LINSync-Break
ESCR: LBIE
Write "1" to the
LBD bit in
ESCR.
TBI & RBI
ECCR
O
O
▲
O
Bus Idle
ECCR: BIE
Receive or
transmit data.
TDRE
SSR
O
O
O
O
Transmission
register empty
SSR: TIE
Write
transmission data.
ICP
ICS
O
X
X
O
First falling edge in
ICS: ICP
LIN-Sync-Field
Dsiabe ICP
temporarily.
ICP
ICS
O
X
X
O
Fifth falling edge in
ICS: ICP
LIN-Sync-Field
Disable ICP.
SSR: RIE
Write "1" to the
reception error
clear bit
(SSR: CRE).
ICU
O : Available
▲ : Available when ECCR’s SSM bit is "1".
X : Unavailable
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■ Reception Interrupt
When one of the following events occurs during reception, the corresponding flag bit in the serial status
register (SSR) is set to "1".
• Completion of data reception: RDRF
The received data is transferred from the serial input shift register to the reception data register (RDR)
and becomes readable.
• Overrun error: ORE
RDRF=1 and the RDR was not read from the CPU.
• Framing error: FRE
During the stop bit reception, "0" was received.
• Parity error: PE
An incorrect parity bit was detected.
When a reception interrupt is enabled (SSR: RIE=1) and any of these flags is set to "1", a reception
interrupt is generated.
When the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". This is the
only method to clear the RDRF flag.
All error flags are cleared to "0" when "1" is written to the reception error flag clear bit (CRE) in the serial
control register (SCR).
Note:
The CRE bit is write-only. When "1" is written, it retains the value for one machine cycle.
■ Transmission Interrupt
When transmission data is transferred from the transmission data register (TDR) to the transmission shift
register (this occurs when the shift register is empty and transmission data exists), the transmission data
register empty flag bit (TDRE) in the serial status register (SSR) is set to "1". If the transmission interrupt
enable bit (TIE) in the SSR has been set in this situation, an interrupt request is generated.
Note:
The initial value of TDRE is "1". Consequently, a transmission interrupt is generated as soon as the
TIE flag is set to "1". The TDRE flag is reset only when data is written to the transmission data
register (TDR).
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■ LIN-Synch-Break Interrupt
This interrupt is available when the LIN-UART is in mode 0 or operates as a LIN slave in mode 3.
When the serial input bus continues to be "0" for 11 bit times or longer (dominant), the LIN-Break
detection flag bit (LBD) in the extended status/control register (ESCR) is set to "1". When this occurs, the
reception error flag is set to "1" after 9 bit times. Therefore, set the RIE or RXE flag to "0" if you want to
perform the LIN-Synch-Break detection only. Otherwise, you must have a reception error interrupt be
generated first, and then use an interrupt processing routine to wait for LBD=1.
When "1" is written to the LBD flag, the interrupt and the LBD flag are cleared. This ensures that the CPU
reliably detects a LIN-Synch-Break during the procedure of the serial clock adjustment for the LIN master
described below.
■ LIN-Synch-Field Edge Detection Interrupt
This interrupt is available when the LIN-UART is in mode 0 or operates as a LIN slave in mode 3.
After a LIN-Break is detected, the LIN-UART shows the falling edge of the reception bus. At the same
time, an interrupt signal connected to the ICU is set to "1". This signal is reset at the 5th falling edge in the
LIN-Synch-Field. In either case, the ICU generates an interrupt as long as both edges are detected and an
ICU interrupt has been enabled. The difference in the counter values detected by the ICU is eight times
greater than that of the serial clock. Using this result enables calculation of baud rate for the dedicated
reload counter.
Since the reload counter is automatically reset when the falling edge of the start bit is detected, restart
operation is unnecessary.
■ Bus Idle Interrupt
When no reception activity is detected at the SIN pin, the RBI flag bit in the ECCR is set to "1". Similarly,
when no transmission activity is detected at the SOT pin, the TBI flag bit is set to "1". When the Bus Idle
enable bit (BIE) in the ECCR is set and both Bus Idle flags (TBI and RBI) are set to "1", an interrupt is
generated.
Note:
When "0" is written to the SIOP bit while the SOPE bit is "1", the TBI flag is set to "0" even when no
bus activity is detected. The TBI and RBI bits cannot be used when the SSM bit in the ECCR register
is "0" in mode 2 (synchronous mode).
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Figure 15.4-1 shows the generation of the Bus Idle interrupt.
Figure 15.4-1 Generation of Bus Idle Interrupt
Transmission
data
Reception
data
TBI
RBI
Reception
IRQ
: Start bit
446
: Stop bit
: Data bit
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15.4 LIN-UART Interrupts
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15.4.1
Reception Interrupt Generation and Flag Set Timing
This section describes a reception interrupt factor, reception completion (SSR: RDRF
bit), and the occurrence of reception errors (SSR: PE, ORE, and FRE bits).
■ Reception Interrupt Generation and Flag Set Timing
When the reception interrupt enable flag bit (RIE) in the serial status register (SSR) is set to "1" and the
data reception is complete (RDRF=1), an interrupt is generated. This interrupt is generated when a stop bit
is detected in mode 0, 1, 2 (SSM=1), or 3, or when the last data bit is read in mode 2 (SSM=0).
Note:
If a reception error occurs, the content of the reception data register is invalid regardless of the
operation mode.
Figure 15.4-2 Reception Activity and Flag Set Timing
Receive data
(mode 0/mode 3)
ST
D0
D1
D2
D5
D6
D7/
P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
D6
D7
AD
SP
ST
D0
D1
D2
D4
D5
D6
D7
D0
Receive data
(mode 2)
PE*1, FRE
RDRF
ORE*2
(if RDRF=1)
*1: The PE flag will always remain "0" in mode 1 or mode 3.
*2: ORE only occurs, if the reception data is not read by
the CPU (RDRF=1) and another fram is read.
ST: Start Bit
SP: Stop Bit
Reception interrupt occurs
AD: Mode 1 (multi processor) address/data selection bit
Note:
Figure 15.4-2 does not show all reception options available in modes 0 and 3.
Only "7p1" and "8N1" are shown here (p="E"[even] or "O"[odd]).
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Figure 15.4-3 ORE Set Timing
Receive
data
RDRF
ORE
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15.4 LIN-UART Interrupts
MB91461
15.4.2
Transmission Interrupt Generation and Flag Timing
A transmission interrupt is generated when the transmission data register (TDR) is
ready to accept writing of the next transmission data.
■ Transmission Interrupt Generation and Flag Timing
A transmission interrupt is generated when the transmission data register (TDR) is ready to accept writing
of the next transmission data. When the transmission interrupt enable bit (TIE) in the serial status register
(SSR) is set to "1" to enable a transmission interrupt, and the TDR becomes empty, a transmission interrupt
is generated.
The transmission register empty (TDRE) flag bit in the SSR indicates whether the TDR is empty. The
TDRE bit is read only. This flag is cleared only when data is written to the TDR.
Figure 15.4-4 shows the transmission activity and flag set timing.
Figure 15.4-4 Transmission Activity and Flag Set Timing
Transmission interrupt occurs
Transmission interrupt occurs
Mode 0,1 or 3:
Write to TDR
TDRE
Serial output
P
P
ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP
Transmission interrupt occurs
Transmission interrupt occurs
Mode 2 (SSM = 0):
Write to TDR
TDRE
Serial output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
ST: Start bit D0 to D7: data bits
P: Parity
AD: Address/data selection bit (mode1)
SP: Stop bit
Note:
The example in Figure 15.4-4 does not show all transmission options available in mode 0.
Only "8p1" (p="E"[even] or "O"[odd]) is shown here. When the SSM bit is "0" in modes 3 and 2, parity
is not added.
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15.4 LIN-UART Interrupts
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■ Transmission Interrupt Request Generation Timing
When a transmission interrupt is enabled (SSR: TIE bit=1) and the TDRE flag is set to "1", a transmission
interrupt request is generated.
Note:
The initial value of the TDRE is "1". Therefore, a transmission completion interrupt is set as soon as
a transmission interrupt is enabled (TIE=1). The TDRE is read only. The TDRE flag is cleared only
when data is written to the transmission data register (TDR). Be sure to determine proper timing to
enable a transmission interrupt.
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15.5
LIN-UART Baud Rate Setting
15.5 LIN-UART Baud Rate Setting
Any of the following can be selected as a serial clock for the LIN-UART.
• Dedicated baud rate generator (reload counter)
• External clock (Clock input from the SCK pin)
• External clock used for the baud rate generator (reload counter)
■ Selecting the Baud Rate for the LIN-UART
Figure 15.5-1 shows the baud rate selection circuit (reload counter). Baud rate can be selected from the
following three options:
● Dedicated baud rate generator (reload counter)
The LIN-UART has independent reload counters for the transmission and reception serial clocks
respectively. Baud rate is set based on the 15-bit reload value stored in the baud rate generator register
(BGR).
The reload counter divides the frequency of the machine clock using the setting value in the baud rate
generator register.
● External clock (1-to-1 mode)
The clock input received at the LIN-UART’s clock input pin (SCK) is directly used as baud rate.
● External clock used for the dedicated baud rate generator
It is also possible to connect an external clock to the reload counter inside the device. In this option, the
external clock is used as a replacement of the internal machine clock.
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Figure 15.5-1 Baud Rate Selection Circuit (Reload Counter)
REST
Start bit falling
edge detected
Reload Value: v
Rxc = 0?
Set
Reception
15-bit Reload Counter Reload
Rxc = v/2?
FF
Reset
0
1
EXT
Reload Value: v
Txc = 0?
CLK
SCK
(External
clock
input)
0
Set
Transmission
15-bit Reload Counter Reload
1
Count Value: Txc
Reception
Clock
Txc = v/2?
FF
Reset
0
OTO
1
Transmission
Clock
Internal data bus
EXT
REST
OTO
452
SMR
register
B14
B13
B12
B11
B10
B09
B08
BGR1
register
B07
B06
B05
B04
B03
B02
B01
B00
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BGR0
register
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CHAPTER 15 LIN-UART
MB91461
15.5.1
Baud Rate Setting
15.5 LIN-UART Baud Rate Setting
This section describes the baud rate setting procedure and the calculation result of the
serial clock frequency.
■ Baud Rate Calculation
The baud rate generator register (BGR) sets the 15-bit reload counter.
Use the following formula to calculate the baud rate.
v = [φ / b] − 1
Where, "φ" is the machine clock frequency, and "b" is the baud rate.
● Calculation example
When the machine clock is 16 MHz and the target baud rate is 19200 bps, the reload value "v" can be
calculated as follows:
v = [16 × 106 / 19200] − 1 = 832
The precise value of the baud rate can be obtained by the following re-calculation:
bexact = φ / (v + 1) = 16 × 106 / 833 = 19207.6831 bps
Note:
When the reload value is set to "0", the reload counter stops. Consequently, the minimum division
ratio is 2.
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■ Examples of Baud Rate Settings by Machine Clock Frequencies
Table 15.5-1 lists the examples of baud rate settings by machine clock frequency.
Table 15.5-1 Examples of Baud Rate Settings By Machine Clock Frequency
Baud rate
(bps)
9 MHz
10 MHz
18 MHz
20 MHz
value
dev.
value
dev.
value
dev.
value
dev.
4M
−
−
−
−
−
−
4
0
2M
4
10.00
4
0.00
8
0.00
9
0
1M
8
0.00
9
0.00
17
0.00
19
0
500000
17
0.00
19
0.00
35
0.00
39
0
460800
−
−
−
−
38
-0.16
−
−
250000
35
0.00
39
0.00
71
0.00
79
0
230400
38
-0.16
−
−
77
-0.16
−
−
153600
58
0.69
64
-0.16
116
-0.16
129
-0.16
125000
71
0.00
79
0.00
143
0.00
159
0
115200
77
-0.16
86
0.22
155
-0.16
173
0.22
76800
116
-0.16
129
-0.16
233
-0.16
259
-0.16
57600
155
-0.16
173
0.22
312
0.16
346
-0.06
38400
233
-0.16
259
-0.16
468
0.05
520
0.03
28800
312
0.16
346
-0.06
624
0.00
693
-0.06
19200
468
0.05
520
0.03
937
0.05
1041
0.03
10417
863
0.00
959
0.00
1727
0.00
1919
0
9600
937
0.05
1041
0.03
1874
0.00
2083
0.03
7200
1249
0.00
1388
0.01
2499
0.00
2777
0.01
4800
1874
0.00
2082
-0.02
3749
0.00
4166
0.01
2400
3749
0.00
4166
0.01
7499
0.00
8332
0
1200
7499
0.00
8332
0.00
14999
0.00
16666
0
600
14999
0.00
16666
0.00
29999
0.00
−
−
300
29999
0.00
−
−
−
−
−
−
Note:
The unit of the deviation (dev.) is %.
The maximum synchronization baud rate is 5 divisions of the machine clock.
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■ Using an External Clock
When the EXT bit in the SMR is set, an external pin SCK is selected for clock input. The external clock is
treated in the same manner as the internal MCU clock. It is designed, by connecting the SCK pin to a
1.8432-MHz quartz oscillator, for example, to use the reload counter to select every baud rate of PC-16550LIN-UART.
When the "1-to-1" external clock input mode (SMR: OTO bit) is selected, the SCK signal is directly
connected to the LIN-UART serial clock input. This is necessary to use the LIN-UART as a slave device in
mode 2 (synchronous mode).
Note:
In either case, the clock signal is synchronized with the MCU clock inside the LIN-UART. This means
that the clock ratio which cannot be divided may result in unstable signals.
■ Example of Counting
Figure 15.5-2 shows the example of counting by reload counters. In this example, the reload value is
assumed to be 832.
Figure 15.5-2 Example of Counting by Reload Counters
Transmission/
Reception Clock
Reload
Count
001
000
832
831
830
829
828
827
412
411
410
Reload Count value
Transmission/
Reception Clock
Reload
Count
417
416
415
414
413
Note:
The falling edge of the serial clock signal is always after |(v + 1) / 2|.
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15.5.2
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Restarting Reload Counter
The reload counter can be restarted with the following factors:
(Common to the transmission and reception reload counters)
• MCU reset
• LIN-UART software clear (SMR: UPCL bit)
• LIN-UART software restart (SMR: REST bit)
(Reception reload counter only)
• Falling edge of the start bit in asynchronous mode
■ Software Restart
When the REST bit in the serial mode register (SMR) is set, both transmission/reception reload counters
are restarted at the next clock cycle. This function is provided to use the transmission reload counter as a
timer.
Figure 15.5-3 shows the example of reload counter restart operation. The reload value is assumed as 100.
Figure 15.5-3 Example of Reload Counter Restart Operation
MCU
Clock
Reload Counter
Clock Outputs
REST
Reload
Value
37
36 35 100 99
98
97
96
95
94
93
92
91
90
89 88
87
Read
BGR0/BGR1
Data
Bus
90
: Don’t care
In this example, the MCU clock cycle count (cyc) after the REST is set is obtained as follows:
cyc = v − c + 1 = 100 − 90 + 1 = 11
Where, "v" is the reload value, and "c" is the readout counter value.
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Note:
When the LIN-UART is reset by the UPCL bit in the SMR, the reload counter is also restarted.
■ Automatic Restart
In the asynchronous mode of the LIN-UART, the reception reload counter is restarted when the falling
edge of the start bit is detected. This is intended to synchronize the serial input shift register with the input
serial data.
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15.6 LIN-UART Operations
15.6
MB91461
LIN-UART Operations
In operation mode 0, the LIN-UART normally operates for bidirectional serial
communication. In mode 2 or mode 3, it offers bidirectional communication as a master
or a slave. In mode 1, it offers multiprocessor communication as a master or a slave.
■ LIN-UART Operations
● Operation mode
The LIN-UART can be used in four operation modes: Modes 0 to 3. Table 15.6-1 shows available
operation modes according to the connection settings between the CPUs and the data transfer type.
Table 15.6-1 Operation Modes of LIN-UART
Data length
Operation mode
0 Normal mode
1 Multiprocessor mode
Parity
disabled
7-bit or 8-bit
7-bit or 8bit + 1 (*2)
2 Normal mode
3 LIN mode
Parity
enabled
−
8-bit
8-bit
−
Synchronization
Stop bit
length
Data direction
*1
Asynchronous
1-bit or 2-bit L/M
Asynchronous
1-bit or 2-bit L/M
Synchronous
0-bit, 1-bit or
L/M
2-bit
Asynchronous
1-bit
L
*1: Indicates the type of the transfer data (LSB first or MSB first).
*2: "+1" expresses the bit displayed in the address/data section which is added instead of the parity bit in
the multiprocessor mode.
Note:
Mode 1 supports both master and slave operations of the LIN-UART in the master/slave connection
system. In mode 3, the functions of the LIN-UART are fixed as 8N1 format, LSB first.
When the mode is changed, the LIN-UART stops all the current transmission/reception operations
and starts the next action.
■ Connection between CPUs
Either the external clock "1-to-1" connection (normal mode) or the master/slave connection (multiprocessor
mode) can be selected. In either connection, the settings of the data length, parity, and synchronization
method must be the same in all CPUs.
Select the operation mode according to the following instructions:
• In the "1-to-1" connection, set the two CPUs in operation mode 0 (asynchronous transfer mode) or
operation mode 2 (synchronous transfer mode). To use mode 2, be sure to set one CPU as a master, and
the other as a slave.
• In the master/slave connection, select operation mode 1 and use the CPUs as either a master or a slave.
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■ Synchronization Method
In the asynchronous operation mode, the LIN-UART reception clock is automatically synchronized with
the falling edge of the reception start bit.
In the synchronous operation mode, the synchronization is performed either by the clock signal of the
master device, or by the LIN-UART itself if it operates as a master.
■ Single Mode
The LIN-UART treats data as NRZ (Non Return to Zero) format data.
■ Operation Enable Bit
The LIN-UART controls transmission and reception using the transmission enable bit (SCR: TXE bit) and
the reception enable bit (SCR: RXE bit). When the operation is disabled, the transmission and reception
will stop in the following steps respectively:
• When the reception operation is disabled during reception (inputting data to the reception shift register),
the frame reception finishes. After the received data in the reception data register (RDR) is read, the
reception stops.
• When transmission operation is disabled during transmission (outputting data from the transmission
shift register), the transmission continues until no data remains in the transmission data register (TDR),
and then stops.
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15.6.1
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Operation in Asynchronous Mode
(Operation Modes 0 and 1)
When the LIN-UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Transfer Data Format
The data transfer in the asynchronous mode starts with the start bit ("L" level), and ends with the stop bit
(the least 1 bit, "H" level). The direction of the bit stream (LSB first or MSB first) is determined by the
BDS bit in the serial status register (SSR). When a parity bit is enabled, it is placed between the last data bit
and the stop bit.
In operation mode 0, the length of the data frame is 7 or 8 bits, including the address/data separation bit
which is used instead of a parity bit. The stop bit length is selectable from 1 bit or 2 bits.
The bit length of the transfer frame can be calculated as follows:
Bit length = 1 + d + p + s
(d = Data bit [7-bit or 8-bit], p = Parity [0-bit or 1-bit], s = Stop bit [1-bit or 2-bit])
Figure 15.6-1 Transfer Data Format (Operation Modes 0 and 1)
*1
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7
*2
SP
AD
SP
SP
*1: D7 (bit 7) if parity is not provided and data length is 8 bits
P (parity) if parity is provided and data length is 7 bits
*2: Only if SBL-Bit of SCR is set to "1"
ST: Start Bit
SP: Stop Bit
AD: Address/data selectio n bit in mode 1 (multiprocessor mode)
Note:
When the BDS bit in the serial status register (SSR) is set to "1" (MSB first), the bit stream is
processed in the order of D7, D6, ..., D1, D0, (P).
When two bits are selected as stop bits, both of them are detected during reception. The reception data full
flag (RDRF), however, is set to "1" at the reception of the first stop bit. If the second stop bit is detected
and the next start bit is not detected, the Bus Idle flag (ECCR: RBI bit) is set to "1".
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■ Transmission Operation
When the transmission data register empty flag (TDRE) bit in the serial status register (SSR) is set to "1",
data is allowed to be written to the transmission data register (TDR). When data is written to the TDR, the
TDRE flag is set to "0". When the transmission operation is enabled by the TXE bit in the serial control
register (SCR), the data is written to the transmission shift register, and the transmission starts at the next
serial clock cycle, beginning with the start bit. This sets the TDRE flag to "1", and then it is possible to
write the next data to the TDR.
When a transmission interrupt is enabled (TIE=1), the interrupt is generated by the TDRE flag. Since the
initial value of the TDRE flag is "1", the interrupt occurs as soon as the TIE bit is set to "1".
If the bit length is set to 7 bits (CL=0), the most significant bit (MSB) of the TDR becomes an unused bit
regardless of the bit direction setting of the BDS bit (LSB first or MSB first).
■ Reception Operation
Reception operation is performed when it is enabled by the RXE flag bit in the SCR. When the start bit is
detected, a data frame is received according to the format specified in the SCR. When an error occurs, the
corresponding error flag (PE, ORE, or FRE) is set. After the data frame is received, the data is transferred
from the serial shift register to the reception data register (RDR), and the reception data register full flag
(RDRF) bit in the SSR is set. To clear the RDRF flag, the RDR must be read from the CPU. When a
reception interrupt is enabled (RIE=1), the interrupt is generated by the RDRF.
If the data length is set to 7 bits (CL=0), the most significant bit (MSB) of the RDR becomes an unused bit
regardless of the bit direction setting of the BDS bit (LSB first or MSB first).
Note:
When the RDRF flag is set and no error occurs, the reception data register (RDR) contains valid
data.
Set the reception enable flag (RXE) to "1" while the reception bus level is "H".
■ Stop Bit
For transmission, one bit or two bits can be selected as stop bits. When two stop bits are set for reception,
both are detected. This is intended to properly set the reception Bus Idle (RBI) flag in the ECCR after the
detection of the second stop bit.
■ Error Detection
In mode 0, parity, overrun, and framing errors can be detected.
In mode 1, overrun and framing errors can be detected. Parity is not used in this mode.
■ Parity
In mode 0 (and in mode 2 where the SSM bit in the ECCR is set), when the parity enable (PEN) bit in the
serial control register (SCR) is set, the LIN-UART performs parity calculation (during transmission) or
parity detection and check (during reception).
The P bit in the SCR specifies whether to use odd parity or even parity.
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15.6.2
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Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer is used in the LIN-UART operation mode 2 (normal
mode).
■ Transfer Data Format
In the synchronous mode, when the SSM bit in the extended communication control register (ECCR) is "0",
8-bit data is transferred without waiting for start/stop bits. The data format in mode 2 depends on the clock
signal.
Figure 15.6-2 shows the transfer data format (operation mode 2).
Figure 15.6-2 Transfer Data Format (Operation Mode 2)
Reception or transfer data
(ECCR:SSM=0, SCR:PEN=0)
D0
D1
D2
D3
D4
D5
D6
D7
Reception or transfer data
(ECCR:SSM=1, SCR:PEN=0)
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
*
SP
Reception or transfer data
(ECCR:SSM=1, SCR:PEN=1)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
*
SP
*: Only if SBL-Bit of SCR is set to
ST: Start Bit
SP: Stop Bit
P: Parity Bit
■ Clock Inversion and Start/Stop Bits in Mode 2
If the SCES bit in the extended status/control register (ESCR) is set, the serial clock is inverted. As a result,
if the LIN-UART is a slave, it captures data at the falling edge of the reception serial clock. When the LINUART is a master and the SCES bit is set, the clock signal’s mark level becomes "0". When the SSM bit in
the extended communication control register (ECCR) is set, start and stop bits are added to the data format
as in the case of the asynchronous mode.
Figure 15.6-3 Transfer Data Format with Inverted Clock
Mark level
Reception or transmission clock
(SCES=0, CCO=0):
Reception or transmission clock
(SCES=1, CCO=0):
Data stream (SSM=1)
(here: no parity, 1 stop bit)
Mark level
ST
SP
Data frame
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■ Clock Supply
In the clock synchronous mode (normal mode), the number of transmitted/received bits is equal to the
number of clock cycles. If the start/stop synchronization communication is enabled, the number of clock
cycles matches with the value including the start/stop bits.
If the internal clock (dedicated reload timer) is selected, the data received with clock synchronization is
automatically generated when it is transmitted.
If the external clock is selected, data is stored in the transmission data register, and the clock cycle for each
bit to be sent is supplied or generated externally. When the SCES is "0", the mark level ("H") is retained
before transmission starts and after transmission finishes.
Setting the SCDE bit in the ECCR delays the transmission clock signal by 1 machine cycle so that the
transmission data is valid and stable at any falling edge of the clock. (This is necessary for the receiving
device to capture data at the rising or falling edge of the clock.) This function is disabled when the CCO is
set.
Figure 15.6-4 Delayed Transmission Clock Signal (SCDE=1)
Transmission data
writing
Reception data sample edg (SCES = 0)
Mark level
Transmitting or
receiving clock
(normal)
Mark level
Transmitting clock
(SCDE=1)
Mark level
Transmission and
reception data
0
1
1
0
LSB
1
0
Data
0
1
MSB
When the serial clock edge selection (SCES) bit in the ESCR is set, the LIN-UART clock is inverted, and
the received data is captured at the falling edge of the clock. In this case, make sure that the serial data is
valid at the falling edge of the clock.
When the LIN-UART is a master and the CCO bit in the extended status/control register (ESCR) is set, the
serial clock is continuously output from the SCK pin. In this case, be sure to use both start and stop bits to
clearly notify the receiver of the beginning and end of a data frame. Figure 15.6-5 lists the continuous
clock output in mode 2.
Figure 15.6-5 Continuous Clock Output in Mode 2
Reception or transmission clock
(SCES=0, CCO=1):
Reception or transmission clock
(SCES=1, CCO=1):
Data stream (SSM=1)
(here: no parity, 1 stop bit)
ST
SP
Data frame
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■ Error Detection
When start/stop bits are not used (ECCR: SSM=0), only overrun errors are detected.
■ Communication
The initialization of the synchronous communication mode requires the following settings:
• Baud rate generator register (BGR)
Set a reload value to the dedicated baud rate reload counter.
• Serial mode register (SMR)
MD1, MD0:
10B (Mode 2)
SCKE:
"1" (for using the dedicated baud rate reload counter)
"0" (external clock input)
• Serial control register (SCR)
RXE, TXE:
Set these flag bits to "1".
SBL, AD:
No stop bit; No address/data separation; The value is invalid.
CL:
Automatically fixed to 8-bit data; The value is invalid.
CRE:
"1" (The error flag is cleared for initialization; Transmission/reception stops.)
When SSM=0: No parity; The setting values of PEN and P are invalid.
When SSM=1: The setting values of PEN and P are valid.
• Serial status register (SSR)
BDS:
"0" (LSB first), "1" (MSB first)
RIE:
"1" (Interrupt enabled), "0" (Interrupt disabled)
TIE:
"1" (Interrupt enabled), "0" (Interrupt disabled)
• Extended communication control register (ECCR)
SSM:
"0" (No start/stop bits, normal)
"1" (with start/stop bits, special)
MS:
"0" (Master mode; The LIN-UART generates a serial clock.)
"1" (Slave mode; The LIN-UART receives a serial clock from an external device.)
To start communication, write data into the transmission data register (TDR). To only receive data, stop the
output with the serial output enable (SOE) bit in the SMR, and write dummy data to the TDR.
Note:
As in the asynchronous mode, you can use a continuous clock, start/stop bits, and bidirectional
communication.
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
15.6.3
Operation with LIN Function (Operation Mode 3)
The LIN-UART can be used as either a LIN master device or a LIN slave device. Mode 3
has been assigned to the LIN function. Setting the LIN-UART to mode 3 specifies the
data format to 8N1, LSB first.
■ LIN-UART as LIN Master
In the LIN master mode, the master determines the baud rate of the entire bus. Consequently, slave devices
are synchronized with the master device. The baud rate specified in the master operation after initialization
is retained.
When "1" is written to the LBR bit in the extended communication control register (ECCR), "L" level of 13
to 16 bit times is output to the SOT pin. This signifies a LIN-Sync-Break and the start of LIN message.
As a result, the TDRE flag in the serial status register (SSR) is set to "0". This flag is reset to "1" after the
break, and generates a transmission interrupt to the CPU when the TIE bit in the SSR is "1".
The length of the Sync-Break to be transmitted can be set with the LBL1 and LBL0 bits in the ESCR as
shown in Table 15.6-2 .
Table 15.6-2 LIN-Break Length
LBL1
LBL0
Break length
0
0
13 bit times
0
1
14 bit times
1
0
15 bit times
1
1
16 bit times
The Synch-Field can be transmitted as one byte 55H after the LIN-Break. To prevent a transmission
interrupt, you can write 55H to the TDR by writing "1" to the LBR even if the TDRE flag is "0". The
transmission shift register waits until the LIN-Break finishes, and then shifts the TDR value. In this case,
no interrupt is generated after the LIN-Break and before the start bit.
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■ LIN-UART as LIN Slave
In the LIN slave mode, the LIN-UART synchronizes with the baud rate of the master. If reception is
disabled (RXE=0) but the LIN-Break interrupt is enabled (LBIE=1), and the Synch-Break to the LIN
master is detected and indicated by the LBD flag in the ESCR, the LIN-UART generates a reception
interrupt. Writing "0" to this bit clears the interrupt.
Then, the baud rate of the LIN master is analyzed. The LIN-UART detects the first falling edge in the
Synch-Field. The LIN-UART signals it to the input capture (ICU) via the internal signal, and resets the
signal to the ICU at the fifth falling edge. Therefore, it is necessary to specify the ICU as the LIN input
capture and enable its interrupts. The period when the signal to the ICU is "1" is the accurate baud rate of
the LIN master divided by 8.
The baud rate setting value can be calculated as follows:
Without timer overflow: BGR value = (b − a) / 8
With timer overflow:
BGR value = (Max + b − a) / 8
Where, "Max" is the maximum value of the timer, "a" is the value of the ICU counter register after the first
interrupt, and "b" is the value of the ICU counter register after the second interrupt.
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
■ LIN-Synch-Break Interrupt Detection and Flag
When a LIN-Synch-Break is detected in the slave mode, the LIN-Break detection (LBD) flag in the ESCR
is set to "1". If the LIN-Break interrupt enable (LBIE) bit has been set, it is considered to be an interrupt
factor.
Figure 15.6-6 shows the timing of the LIN-Synch-Break detection and flag setting.
Figure 15.6-6 Timing of LIN-Synch-Break Detection and Flag Setting
Serial clock
cycle#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial
clock
Serial
input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs, if RXE=1
Reception interrupt occurs, if RXE=0
When reception is enabled (RXE=1) and an reception interrupt is enabled (RIE=1), the reception data
framing error (FRE) flag bit becomes a reception interrupt factor 2 bit times ("8N1") faster than the LINBreak interrupt. If you want to use the LIN-Break, set the RXE to "0".
The LBD can be used in operation modes 0 and 3.
Figure 15.6-7 Operation of LIN-UART as LIN Slave
Serial
clock
Serial
Input
(LIN bus)
LBR cleared
by CPU
LBD
Internal
ICU
Signal
Synch break (e.g. 14 Tbit)
CM71-10159-2E
Synch field
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15.6 LIN-UART Operations
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■ LIN Bus Timing
Figure 15.6-8 LIN Bus Timing and LIN-UART Signals
Old serial clock
No clock used
(calibration frame)
New (calibrated) serial clock
ICU count
LIN bus
(SIN)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal to
ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR
by CPU
Reception Interrupt enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD -> 0)
IRQ from ICU
IRQ cleared: Begin of Input Capture
IRQ from ICU
IRQ cleared: Calculate & set new baud rate
LBIE disable
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR
RDR read by CPU
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CHAPTER 15 LIN-UART
MB91461
15.6.4
Direct Access to Serial Pins
15.6 LIN-UART Operations
The LIN-UART allows the direct access to the values of transmission pins (SOT) and
reception pins (SIN).
■ Direct Access to LIN-UART Pins
The LIN-UART provides a function to directly access to the value of the serial input/output pins by using
software. Reading the SIOP bit in the ESCR enables monitoring of the serial input data. When the serial
output pin direct access enable (SOPE) bit in the ESCR is set, the software can fix the output value from
the SOT pin. This is possible only when the transmission shift register is empty, such as when there is no
transmission activity.
In the LIN mode, this function can be used to read back the data which you have transmitted. It can also be
used for error handling when some physical failure exists on the single-wire LIN bus.
Note:
The SIOP retains the value which was written most recently. To prevent unnecessary edge output,
write a value to the SIOP before configuring the access to the output pin.
During the read-modify-write (RMW) instruction to the SIOP bit, the value of the SOT pin is returned.
For the normal read instruction, the value of the SIN pin is returned.
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15.6 LIN-UART Operations
15.6.5
MB91461
Bidirectional Communication Function (Normal Mode)
Operation modes 0 and 2 offer normal serial bidirectional communication. Select
operation mode 0 for asynchronous communication, and operation mode 2 for
synchronous communication.
■ Bidirectional Communication Function
Figure 15.6-9 shows the LIN-UART settings in operation modes 0 and 2.
Figure 15.6-9 LIN-UART Settings in Operation Modes 0 and 2
bit 15
14
13
12
11
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
Mode 0 → ❍
❍
❍
❍
X
0
❍
❍
0
0
X
0
0
0
1
❍
Mode 2 →
❑
❑
X
X
0
❍
❍
1
0
❍
❍
0
0
❍
❍
SCR, SMR
PEN
❑
SSR,
TDR/RDR
10
9
PE ORE FRE RDRF TDRE BDS RIE
8
TIE
Mode 0 → ❍
❍
❍
❍
❍
❍
❍
❍
Mode 2 →
❍
❑
❍
❍
❍
❍
❍
❑
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
7
6
5
4
3
2
1
0
Set conversion data (during writing)
Retain reception data (during reading)
Reserved
LBR MS SCDE SSM BIE
RBI
TBI
Mode 0 → ❍
❍
❍
❍
❍
❍
X
X
❍
X
X
X
❍
❍
❍
Mode 2 →
X
X
X
❍
❍
❍
❍
X
❍
❍
❍
❑
❑
❑
X
❍ : Bit used
X : Bit not used
1 : Set 1
0 : Set 0
❑ : Bit used if SSM=1 (Synchronous start-/stop-bit mode)
+ : Bit automatically set to correct value
■ Connection between CPUs
Figure 15.6-10 shows the connection example for bidirectional communication in LIN-UART operation
mode 2.
Figure 15.6-10 Connection Example for Bidirectional Communication in LIN-UART Operation Mode 2
SOT
SOT
SIN
SIN
SCK
Output
Input
CPU-1 (Master)
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SCK
CPU-2 (Slave)
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
15.6.6
Master/Slave Communication Function
(Multiprocessor Mode)
In the master/slave mode, the LIN-UART communication with multiple CPUs is possible
from either a master or slave system.
■ Master/Slave Communication Function
Figure 15.6-11 shows the LIN-UART settings in operation mode 1.
Figure 15.6-11 LIN-UART Settings in Operation Mode 1
bit 15
SCR, SMR
Mode 1 →
SSR,
TDR/RDR
14
13
12
11
10
9
PEN
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
+
X
❍
❍
❍
❍
0
PE ORE FRE RDRF TDRE BDS RIE
Mode 1 →
X
❍
❍
❍
❍
❍
❍
8
❍
TIE
X
X
X
X
❍
❍
X
6
0
1
5
0
4
0
3
0
2
0
1
1
0
❍
Set conversion data (during writing)
Retain reception data (during reading)
❍
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
Mode 1 →
7
Reserved
LBR MS SCDE SSM BIE
X
X
X
X
X
❍
RBI
TBI
❍
❍
❍ : Bit used
X
1
0
+
: Bit not used
: Set 1
: Set 0
: Bit automatically set to correct value
■ Connection between CPUs
Figure 15.6-12 shows the connection example of LIN-UART master/slave communication. The LINUART can be used for the master or slave CPU.
Figure 15.6-12 Connection Example of LIN-UART Master/Slave Communication
SOT
SIN
Master CPU
SOT
SIN
Slave CPU #0
CM71-10159-2E
SOT
SIN
Slave CPU #1
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15.6 LIN-UART Operations
MB91461
■ Function Settings
For the master/slave communication, set the operation mode and data transfer mode as shown in the table
below:
Table 15.6-3 Settings of Master/Slave Communication Functions
Operation mode
Data
Master CPU
Address
transmission/ Mode 1
reception
(AD bit
transmission/
Data
transmission/ reception)
Parity
Synchronization
method
Stop bit
None
Asynchronous
1 bit or 2 bits
Slave CPU
Mode 2 (AD
bit
transmission/
reception)
reception
AD=1 +
7-bit or 8-bit
address
AD=0 +
7-bit or 8-bit
data
Bit direction
LSB first or
MSB first
■ Communication Procedure
When the master CPU transmits address data, communication starts. The AD bit in the address data is set to
"1", and the communication target CPU is selected. Each slave CPU checks the address data. When the
address data indicates the address assigned to one of the slave CPUs, the slave CPU communicates with the
master CPU (normal mode).
The following is a flowchart of the master/slave communication (multiprocessor mode).
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
Figure 15.6-13 Flowchart of Master/Slave Communication
(Master CPU)
(Slave CPU)
Start
Start
Set operation mode 1
Set operation mode 1
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set SIN pin as the
serial data input pin.
Set SOT pin as the
serial data output pin.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set "1" in AD bit
Set TXE = RXE = 1
Set TXE = RXE = 1
Receive Byte
Send Slave Address
Is
AD bit = 1 ?
Waiting
NO
YES
Bus-idle
Interrupt
Does
Slave Address
match ?
Set "0" in AD bit
NO
YES
Communication with
slave CPU
Is
communication
complete?
Communication with
master CPU
NO
YES
Is
communication
complete?
NO
YES
Communicate
with another
slave CPU?
NO
YES
Set TXE = RXE = 0
End
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
15.6.7
MB91461
LIN Communication Function
The LIN-UART communication with LIN devices is possible with either LIN master or LIN
slave system.
■ LIN Master/Slave Communication Function
Figure 15.6-14 shows the LIN-UART settings in operation mode 3 (LIN).
Figure 15.6-14 LIN-UART Settings in Operation Mode 3 (LIN)
bit 15
SCR, SMR
14
13
12
11
PEN
P
SBL
CL
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
+
X
+
+
Mode 3 →
SSR,
TDR/RDR
X
10
0
9
❍
PE ORE FRE RDRF TDRE BDS RIE
Mode 3 →
X
❍
❍
❍
❍
+
❍
8
❍
TIE
❍
❍
❍
❍
❍
X
6
1
1
5
0
4
0
3
0
2
1
0
1
0
❍
Set conversion data (during writing)
Retain reception data (during reading)
❍
ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS
Mode 3 → ❍
7
0
Reserved
LBR MS SCDE SSM BIE
❍
X
X
X
RBI
TBI
❍
❍
❍
❍ : Bit used
X
1
0
+
: Bit not used
: Set 1
: Set 0
: Bit automatically set to correct value
■ LIN Device Connection
Figure 15.6-15 shows the connection example of LIN bus system. The LIN-UART can be configured as
either of a LIN master or a LIN slave.
Figure 15.6-15 Connection Example of LIN Bus System
SOT
SOT
LIN bus
SIN
LIN-Master
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Single-WireTransceiver
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LIN-Slave
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
15.6.8
Sample Flowchart for LIN-UART in LIN Communication
Mode (Operation Mode 3)
This section provides the sample flowcharts for the LIN-UART in the LIN communication
mode.
■ LIN-UART as a Master Device
Figure 15.6-16 Flowchart for LIN-UART in LIN Master Mode
START
Initialization:
Set Operat. mode 3
(8N1 data format)
TIE = 0, RIE = 0
Send
Message?
NO
YES
Send Synch Break:
write "1" to ECCR:
LBR, TIE = 1;
Send Sleep Mode
TDR = 80H
TIE = 0
Send Synch Field:
TDR = 55H
Wake up
from CPU?
YES
NO
Send Sleep
Mode?
Send Wake up signal
RIE = 0
TIE = 1
TDR = 80H
RIE = 1
YES
NO
Send Identify Field:
TDR = Id
Write to
slave?
NO
YES
00H, 80H
or C0H
received?
TIE = 1
Write data to slave
TIE = 0
RIE = 0
YES
Errors
occurred?
NO
TIE = 0
RIE = 1
Read data from slave
RIE = 0
CM71-10159-2E
NO
YES
Error Handler
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
■ LIN-UART as a Slave Device
Figure 15.6-17 Flowchart for LIN-UART in LIN Slave Mode
START
A
B
Initialization:
Set Operat. mode 3
(8N1 data format)
C
RIE = 0; LBIE = 1;
RXE = 0
Error
occurred?
Slave
address
match?
NO
E
NO
C
YES
YES
Master
wants to
send data?
Waiting
(slave
action)
LBD = 1
LIN break interrupt
NO
YES
Awaiting message from
LIN master.
Write "0" to LBD to
clear interrupt Enable
ICU interrupt .
(both edge)
Receive data
+ check sum
80H
received?
(sleep mode)
NO
S
RIE = 0
TIE = 1
Calculate
checksum
Send data
(On next page)
Waiting
(slave
action)
TIE = 0
YES
ICU Interrupt
B
Read ICU value and
store it.
Clear Interrupt.
Waiting
(slave
action)
C
Master
wants to
send data?
NO
YES
C
ICU Interrupt
Read ICU value.
Calculate new baud rate.
Set it to Reload Counter.
Clear Interrupt.
Waiting
(slave
action)
E
Error handler
Bus -idle
Interrupt
C
Receive identifier
RIE = 1; RXE = 1
A
(Continued)
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CHAPTER 15 LIN-UART
15.6 LIN-UART Operations
MB91461
(Continued)
S
Wake up
from CPU?
NO
Send Wake up signal
RIE = 0
TIE = 1
TDR = 80H
YES
RIE = 1
NO
CM71-10159-2E
00H, 80H
or C0H
received?
TIE = 0
YES
RIE = 0
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CHAPTER 15 LIN-UART
15.7 Notes on Using LIN-UART
15.7
MB91461
Notes on Using LIN-UART
This section provides the notes on using the LIN-UART.
■ Operation Setting
The LIN-UART’s serial control register (SCR) has the TXE (transmission) and RXE (reception) operation
enable bits. These bits are disabled by default. Before starting transfer for either of transmission or
reception operation, these bits must be enabled. The transfer can be discontinued by disabling these bits.
Since a single-wire bus system such as ISO9141 (LIN bus system) offers mono-directional communication,
do not enable these two bits simultaneously. The LIN-UART receives also the data sent by itself because
reception is automatically performed.
■ Communication Mode Setting
Set the communication mode while the system is not operating. If the operation mode is changed during
transmission or reception, the transmission or reception is stopped and the data being transferred will be
lost.
■ Transmission Interrupt Enable Timing
The initial value of the transmission data empty flag bit (SSR: TDRE bit) is "1" (There is no transmission
data, and writing of transmission data is enabled.). A transmission interrupt request is generated as soon as
the transmission interrupt request is enabled (SSR: TIE bit set to "1"). To prevent this interrupt from
generating, set the TIE flag to "1" after the transmission data is written to the TDR register.
■ Using LIN in Operation Mode 3
The LIN functions can also be used in mode 0 (transmission/reception break); however, using operation
mode 3 sets the LIN-UART data format automatically to the LIN format (8N1, LSB first). To apply the
LIN-UART to the LIN bus protocol, use operation mode 3. The transmission time of the break is
changeable; however, it must be at least 11 serial bit times.
■ Changing Operation Settings
Be sure to reset the LIN-UART after changing its operation settings. Carefully check the presence of the
start/stop bits in mode 2 (synchronous mode), in particular.
When the settings of the serial mode register (SMR) are changed, the setting of UPCL bit cannot be set at
the same time to reset the LIN-UART. Otherwise, the LIN-UART may not operate properly. Set the other
bits in the SMR first, and then to set the UPCL bit.
■ Setting LIN Slave
To initialize the LIN-UART to use it as a LIN slave, make sure to set the baud rate before receiving the
first LIN synchronization break. This is necessary for the reliable detection of the LIN synchronization
break of 13 bit times at minimum.
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CHAPTER 15 LIN-UART
15.7 Notes on Using LIN-UART
MB91461
■ Software Compatibility
Although this LIN-UART is similar to the one included in the conventional MCU, its software is not
compatible. The programming models are almost the same, but the register configuration is different.
Furthermore the baud rate is now set with a reload value, not by selecting a preset value.
■ Bus Idle Function
The Bus Idle function cannot be used in synchronous mode 2.
■ AD Bit in the Serial Control Register (SCR)
Note the following when using the AD bit (address/data bit used in the multiprocessor mode) in the serial
control register (SCR):
When this bit is read, the AD bit which is received most recently is returned. When this bit is written, the
AD bit during transmission is set. Consequently, the AD bit operates as both control bit and flag bit.
Internally, the received data and transmission data are stored into different registers. For a read-modifywrite (RMW) instruction, the received data is read, processed, and then written as transmission data. If the
bit in the same register is accessed by the same type of instruction, incorrect value may be set in the AD bit.
To prevent the problem, perform the write-access to this bit before transmission. Or, set all bits correctly at
the same time using byte access.
Unlike transmission data register, the AD bit does not retain data. If this bit is updated during transmission
operation, the AD bit of the data being transmitted is modified.
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CHAPTER 15 LIN-UART
15.7 Notes on Using LIN-UART
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CM71-10159-2E
CHAPTER 16
I2C INTERFACE
This chapter describes overview, register configuration/
function, and operation of the I2C interface.
16.1 I2C Interface Overview
16.2 I2C Interface Register
16.3 Explanation of I2C Interface Operation
16.4 Operation Flowchart
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CHAPTER 16 I2C INTERFACE
16.1 I2C Interface Overview
16.1
MB91461
I2C Interface Overview
The I2C interface uses the serial I/O port for supporting the inter-IC bus to serve as the
master/slave device on the I2C bus.
■ Feature of I2C Interface
The feature of the I2C interface is as the following.
• Transmitting and receiving of master/slave device
• Arbitration
• Clock synchronization
• Detection of slave address/general call address
• Detection of transfer direction
• Function to generate/detect the iterative START condition
• Detection of bus error
• Supports 10-/7-bit slave address
• Performs slave address receive acknowledge control in master mode
• Supports composite slave address
• Interrupt at transmission/bus error
• Supports standard mode (max. 100 kbps) and high-speed mode (max. 400 kbps)
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CHAPTER 16 I2C INTERFACE
16.1 I2C Interface Overview
MB91461
■ I2C Interface Registers
The registers of the I2C interface are as the following.
• Bus status register (IBSR)
Figure 16.1-1 Bit Configuration of Bus Status Register (IBSR)
IBSR
Address: 0000D1H, 0000DDH
bit7
6
5
4
3
2
1
0
000369H
BB
RSC
AL
LRB
TRX
AAS
GCA
ADT
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
• Bus control register (IBCR)
Figure 16.1-2 Bit Configuration of Bus Control Register (IBCR)
IBCR
Address: 0000D0H, 0000DCH bit15
000368H BER
14
13
12
11
10
9
8
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
• Clock control register (ICCR)
Figure 16.1-3 Bit Configuration of Clock Control Register (ICCR)
ICCR
Address: 0000DAH, 0000E6H bit15
14
000372H Reserved NSF
CM71-10159-2E
13
12
11
10
9
8
EN
CS4
CS3
CS2
CS1
CS0
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
0
0
1
1
1
1
1
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MB91461
• 10-bit slave address register (ITBA)
Figure 16.1-4 Bit Configuration of 10-bit Slave Address Register (ITBA)
ITBAH
Address: 0000D2H, 0000DEH bit15
14
13
12
11
10
00036AH Reserved Reserved Reserved Reserved Reserved Reserved
9
8
TA9
TA8
Read/Write
−
−
−
−
−
−
R/W
R/W
Initial value
−
−
−
−
−
−
0
0
Address: 0000D3H, 0000DFH
bit7
6
5
4
3
2
1
0
00036BH
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
ITBAL
• 10-bit slave address mask register (ITMK)
Figure 16.1-5 Bit Configuration of 10-bit Slave Address Mask Register (ITMK)
ITMKH
Address: 0000D4H, 0000E0H bit15
00036CH ENTB
14
RAL
13
12
11
10
Reserved Reserved Reserved Reserved
9
8
TM9
TM8
Read/Write
R/W
R
−
−
−
−
R/W
R/W
Initial value
0
0
−
−
−
−
1
1
Address: 0000D5H, 0000E1H
bit7
6
5
4
3
2
1
0
00036DH
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
1
1
1
1
1
1
1
1
ITMKL
• 7-bit slave address register (ISBA)
Figure 16.1-6 Bit Configuration of 7-bit Slave Address Register (ISBA)
ISBA
Address: 0000D7H, 0000E3H
bit7
00036FH Reserved
484
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
0
0
0
0
0
0
0
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16.1 I2C Interface Overview
MB91461
• 7-bit slave address mask register (ISMK)
Figure 16.1-7 Bit Configuration of 7-bit Slave Address Mask Register (ISMK)
ISMK
Address: 0000D6H, 0000E2H bit15
00036EH ENSB
14
13
12
11
10
9
8
SM6
SM5
SM4
SM3
SM2
SM1
SM0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
1
1
1
1
1
1
1
• Data register (IDAR)
Figure 16.1-8 Bit Configuration of Data Register (IDAR)
IDAR
Address: 0000D9H, 0000E5H
bit7
6
5
4
3
2
1
0
000371H
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
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16.1 I2C Interface Overview
■ Block Diagram of
I 2C
MB91461
Interface
The block diagram of the I2C interface is shown in the Figure 16.1-9 .
Figure 16.1-9 Block Diagram of I2C Interface
ICCR
EN
I2C operation enable
ICCR
Clock division 2
2345
32
CS4
CS3
CS2
CS1
CS0
Sync
Clock selection 2 (1/12)
Shift clock edge
change timing
IB SR
BB
RSC
Bus busy
Repeat start
Last bit
LRB
TRX
Start/stop
condition detection
Transmitting/
receiving
Error
First byte
ADT
Arbitration lost detection
AL
IB CR
SCLI
SCLO
BER
R-bus
Shift clock generation
BEIE
Interrupt request
IRQ
INTE
SDA
SDAO
INT
IB CR
SCC
MSS
ACK
GCAA
End
Start
Mater
ACK enable
Start/stop condition
occurrence
GC-ACK enable
IDAR
IB SR
Slave
AAS
Global call
GCA
Slave address
comparison
ISMK
FNSB
ITMK
ENTB
RAL
ITBA
486
ITMK
ISBA
ISMK
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16.2 I2C Interface Register
MB91461
16.2
I2C Interface Register
This section describes the configuration and function of the register used in the I2C
interface.
■ I2C Interface Register Overview
I2C interface register includes the following eight types.
• Bus Status Register (IBSR)
• Bus Control Register (IBCR)
• Clock Control Register (ICCR)
• 10-bit Slave Address Register (ITBA)
• 10-bit Slave Address Mask Register (ITMK)
• 7-bit Slave Address Register (ISBA)
• 7-bit Slave Address Mask Register (ISMK)
• Data Register (IDAR)
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16.2.1
MB91461
Bus Status Register (IBSR)
Bus status register (IBSR) has the following functions.
• Bus busy detection
• Repeated START condition detection
• Arbitration lost detection
• Acknowledge detection
• Data transfer direction display
• Slave addressing detection
• General call address detection
• Address data transfer detection
■ Bus Status Register (IBSR)
The register configuration of the bus status register (IBSR) is as the following.
Figure 16.2-1 Bit Configuration of Bus Status Register (IBSR)
IBSR
Address: 0000D1H, 0000DDH
bit7
6
5
4
3
2
1
0
000369H
BB
RSC
AL
LRB
TRX
AAS
GCA
ADT
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
This register is read only. All bits of the register are automatically controlled by the hardware. When I2C
interface is not enabled (EN of ICCR=0), all bits of this register are cleared.
[bit7] BB: Bus busy bit
This bit indicates the status of the I2C bus.
Table 16.2-1 BB (Bus Busy Bit)
Value
488
Description
0
The STOP condition detected [Initial value]
1
The START condition detected (The bus is in use)
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[bit6] RSC: Repeated start condition bit
This bit detects the iterative START condition.
Table 16.2-2 RSC (Repeated Start Condition Bit)
RSC
Description
0
The iterative START condition not detected [Initial value]
1
The iterative START condition detected
This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition is
detected.
[bit5] AL: Arbitration lost detect bit
This bit is used to detect arbitration lost.
Table 16.2-3 AL (Arbitration Lost Detect Bit)
AL
Description
0
Arbitration lost not detected [Initial value]
1
Arbitration lost occurred during transmitting to master
This bit is cleared when "0" is written to the INT bit or when "1" is written to the MSS bit of the IBCR
register.
Examples of arbitration lost:
• Transmit data does not match SDA line data on SCL rising edge
• Iterative START condition caused at first bit of data by another master
• SCL line of I2C interface driven to "L" by another slave, so unable to generate START or STOP
condition
[bit4] LRB: Acknowledge store bit
This bit stores an acknowledge signal from the receive side.
Table 16.2-4 LRB (Acknowledge Store Bit)
LRB
Description
0
Slave acknowledge detected [Initial value]
1
Slave acknowledge not detected
This bit is rewritten when acknowledge is detected (receive 9 bits).
This bit is cleared when the START or STOP condition is detected.
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[bit3] TRX: Transferring data bit
This bit indicates the transmission state during data transfer.
Table 16.2-5 TRX (Transferring Data Bit)
TRX
Description
0
Data transmission not in progress [Initial value]
1
Data transmission in progress
• This bit is set to "1" in the following cases: START condition generated in master mode
- Transfer of first byte ends at read access (transmission) in slave mode
- Transmission in progress in master mode
• This bit is set to "0" in the following cases: Bus in idle state (BB=0:IBCR)
- At arbitration lost
- "1" written to SCC at master interrupt (MSS=1, INT=1)
- MSS bit cleared at master interrupt (MSS=1, INT=1)
- No acknowledge at end of transfer in slave mode
- Reception in progress in slave mode
- Data receiving from slave in master mode
[bit2] AAS: Slave address detect bit
This bit detects the slave address.
Table 16.2-6 AAS (Slave Address Detect Bit)
AAS
Description
0
Slave address not specified [Initial value]
1
Slave address specified
This bit is cleared when the (iterative) START or STOP condition is detected.
This bit is set when the 7-/10-bit slave address is detected.
[bit1] GCA: General call address detect bit
This bit is used to detect a general call address (00H).
Table 16.2-7 GCA (General Call Address Detect Bit)
GCA
Description
0
Detect no general call address [Initial value]
1
Detect general call address
This bit is cleared when the (iterative) START or STOP condition is detected.
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MB91461
[bit0] ADT: Address data transfer bit
This bit is the slave address receive detect bit.
Table 16.2-8 ADT (Address Data Transfer Bit)
ADT
Description
0
Receive data not at slave address (or bus free) [Initial value]
1
Receive data at slave address
This bit is set to "1" when START is detected. When the header at the slave address is detected at 10-bit
write access, this bit is cleared after the second byte; in other cases, it is cleared after the first byte.
"After the first/second byte" means:
• "0" is written to MSS bit during master interrupt (MSS=1, INT=1:IBCR)
• "1" is written to SCC bit during master interrupt (MSS=1, INT=1:IBCR)
• INT bit is cleared
• Start of all transfer bytes when data not to be transferred as master/slave address
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16.2.2
MB91461
Bus Control Register (IBCR)
The bus control register (IBCR) has the following functions.
• Interrupt enable flag
• Interrupt generation flag
• Bus error detection flag
• Repeated START condition generation
• Master/slave mode selection
• General call acknowledge generation enable
• Data byte acknowledge generation enable
■ Bus Control Register (IBCR)
Figure 16.2-2 shows the bit configuration of bus control register (IBCR).
Figure 16.2-2 Bit Configuration of Bus Control Register (IBCR)
IBCR
Address: 0000D0H, 0000DCH bit15
000368H BER
14
13
12
11
10
9
8
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Perform writing to the bus control register (IBCR) when INT bit is "1" or transfer is started. Do not perform
writing during transferring because change of ACK bit or GCAA bit may cause detection of a bus error.
When the I2C interface is not enabled (EN=0:ICCR), all bits except the BER and BEIE bits are cleared.
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[bit15] BER: Bus error flag
This is the bus error interrupt request flag bit. "1" is always read when this bit is read using the readmodify-write (RMW) instruction.
(Writing)
Table 16.2-9 BER (Bus Error Flag)
BER
Description
0
Bus error interrupt request flag cleared
1
No meaning
(Reading)
Table 16.2-10 BER (Bus Error Flag)
BER
Description
0
Bus error not detected [Initial value]
1
The error condition detected
When this bit is set, the EN bit of the CCR register is cleared, the I2C interface is stopped, and data
transfer is suspended. Also, all bits of the IBSR and IBCR registers are cleared except the BER and
BEIE bits. Clear this bit before enabling (EN=1) the I2C interface again.
This bit is set to "1" in the following cases:
1) START or STOP condition is detected at illegal location (during slave address transfer or data
transfer).
2) In 10-bit read access, the read-access slave address header is received before making 10-bit write
access to the first byte.
3) START condition is detected during transfer in master mode.
In 1) and 2), when operation of the I2C interface is enabled during transfer, an illegal bus error report
is prohibited, so the flag is set after reception of the first STOP condition.
[bit14] BEIE: Bus error interrupt enable bit
This bit enables a bus error interrupt.
Table 16.2-11 BEIE (Bus Error Interrupt Enable Bit)
BEIE
Description
0
Bus error interrupt disabled [Initial value]
1
Bus error interrupt enabled
When this bit is "1" and the BER bit is set to "1", an interrupt occurs.
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MB91461
[bit13] SCC: Start condition continue bit
This bit continues the iterative START condition.
(Writing)
Table 16.2-12 SCC (Start Condition Continue Bit)
SCC
Description
0
No meaning
1
The iterative START condition occurs during transfer in the master mode.
The read value of this bit is always "0".
When "1" is written to this bit during master mode (MSS=1, INT=1), the iterative START condition
occurs, clearing the INT bit automatically.
[bit12] MSS: Master/slave select bit
This bit selects between master and slave.
Table 16.2-13 MSS (Master/Slave Select Bit)
MSS
Description
0
Slave mode [Initial value]
1
The master mode established, the START condition occurs, and the value of
the IDAR register is transmitted as the slave address.
• When arbitration lost occurs during transmission in the master mode, this bit is cleared, causing the
slave mode.
• When "0" is written to this bit with the master interrupt flag set (MSS=1, INT=1), the INT bit is
cleared automatically, causing the STOP condition and then ending transfer.
Note: The MSS bit functions as the direct reset. Occurrence of the STOP condition can be checked
by referring to the BB bit of the IBSR register.
• When "1" is written to this bit while the bus is idle (MSS=0, BB=0), the START condition occurs,
transmitting the IDAR value.
• When "1" is written to this bit while the bus is in use (BB=1, TRX=0, MSS=0), the I2C interface
waits until the bus is freed, and then starts transmission. When the I2C interface is addressed during
this wait as the slave involving write access, the bus is freed after transfer has ended.
During this wait, when transmission is in progress as the slave (IBCR:AAS=1, TRX=1), data
transmission is not performed even when the bus is freed. It is important to check whether or not the
I2C interface is specified as the slave (IBSR:AAS=1), whether or not data transmission ends
normally at the next interrupt (IBCR:MSS=1), and whether or not an illegal end occurs
(IBSR:AL=1).
Note:
Under the following condition, transmission of general-call address is prohibited because it cannot be
received as a slave.
LSI other than MB91461 exists on the bus and MB91461 transmits general-call address as a master
and arbitration lost occurs at second byte or later.
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[bit11] ACK: Acknowledge bit
This bit generates acknowledge in accordance with the data receive enable bit.
Table 16.2-14 ACK (Acknowledge Bit)
ACK
Description
0
Acknowledge not generated in response to data reception [Initial value]
1
Acknowledge generated in response to data reception
• This bit is disabled at slave address reception in the slave mode. When the I2C interface detects the
7- or 10-bit slave address designation with the corresponding enable bit (ITMK:ENTB,
ISMK:ENSB) set, acknowledge is returned.
• Write to this bit while the interrupt flag is set (INT=1) or while the bus is free (IBSR:BB=0), or
while the I2C interface is stopped (ICCR:EN=0).
[bit10] GCAA: General call address acknowledge bit
This bit enables generation of an acknowledge signal when a general call address is received.
Table 16.2-15 GCAA (General Call Address Acknowledge Bit)
GCAA
Description
0
Acknowledge not generated in response to reception of general call address
[Initial value]
1
Acknowledge generated in response to reception of general call address
Write to this bit while the interrupt flag is set (INT=1), or while the bus is freed (IBSR:BB=0), or while
the I2C interface is stopped (ICCR:EN=0).
• When the general call address is received, setting both this bit and ACK bit to "1" enable the
acknowledge response generation.
• When the general call address is transmitted, setting this bit to "1" enable the acknowledge response
generation.
• With data received by slave receiving (including the case in which the arbitration lost occurs after
transmission of general call address as master), acknowledge bit output is enabled when both ACK
bit and this bit are "1".
• Do not change the setting of this bit when GCA bit of the bus status register (IBSR) is "1".
[bit9] INTE: Interrupt enable bit
This bit enables an interrupt.
Table 16.2-16 INTE (Interrupt Enable Bit)
INTE
Description
0
Interrupt disabled [Initial value]
1
Interrupt enabled
When the INT bit is "1" and this bit is "1", an interrupt is generated.
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[bit8] INT: Interrupt request flag
This is a transfer end interrupt request flag bit. "1" is always read when this bit is read using the readmodify-write (RMW) instruction.
(Writing)
Table 16.2-17 INT (Interrupt Request Flag)
INT
Description
0
The transfer end interrupt request flag is cleared. [Initial value]
1
No meaning
(Reading)
Table 16.2-18 INT (Interrupt Request Flag)
INT
Description
0
Transfer has not ended or data is not to be transferred, or the bus is freed.
[Initial value]
1
This bit is set when the following conditions are met at completion of 1 byte
transfer including the acknowledge bit:
• Bus master
• The address is specified as a slave address
• General call address received
• Arbitration lost
When the address is specified as a slave address, this bit is set at the end of
slave address reception containing acknowledge.
When this bit is "1", the SCL line is kept "L" level. When "0" is written to this bit, it is cleared, the SCL
line is freed, the next byte is transferred, and the iterative START or STOP condition is generated.
This bit is cleared when "1" is written to the SCC bit or to the MSS bit.
Notes:
At conflict between SCC, MSS, and INT bits:
When write to the SCC, MSS, and INT bits occurs simultaneously, a conflict occurs between:
transfer of the next byte, occurrence of the iterative START condition, and occurrence of the STOP
condition. The priority at this time is shown below.
• Transfer of next byte and occurrence of STOP condition
When "0" is written to the INT bit and to the MSS bit, write to the MSS bit is prior to write to the
INT bit, generating the STOP condition.
• Transfer of next byte and occurrence of START condition
When "0" is written to the INT bit and "1" is written to the SCC bit, writing to the SCC bit is prior to
writing to the INT bit, generating the iterative START condition and transmitting the IDAR value.
• Occurrence of iterative START condition and occurrence of STOP condition
When "1" is written to the SCC bit and "0" is written to the MSS bit, clearing of the MSS bit is prior
to writing to the SCC bit, generating the STOP condition and enabling the I2C interface in the
slave mode.
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Regarding the timing shown in Figure 16.2-3 and Figure 16.2-4 , when the command causing
generation of the START condition is executed (MSS=1:IBCR), interrupt (INT=1:IBCR) caused by
the arbitration lost detect (AL=1:IBSR) does not occur.
• Conditions for no occurrence of interrupt caused by arbitration lost detect (1)
With the START condition not detected (BB=0:IBSR), the command causing generation of the
START condition is executed (MSS=1:IBCR) when the level of SDA pin or SCL pin is "L".
Figure 16.2-3 Timing Diagram for No Occurrence of Interrupt Caused by Arbitration Lost Detect
SCL pin or SDA pin is "L" level.
SCL pin
"L"
SDA pin
"L"
2
I C operation enable state(EN bit=1)
1
Master mode setting (MSS=1)
Arbitration lost detect (AL bit=1)
Bus busy (BB bit)
0
Interrupt (INT bit)
0
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• Conditions for no occurrence of interrupt caused by arbitration lost detect (2)
With the I2C bus occupied by the other master, I2C operation is enabled (EN=1:ICCR) and the
command causing generation of the START condition is executed (MSS=1:IBCR).
As shown in Figure 16.2-4 , if the other master of I2C bus begins transmission when I2C operation
is disabled (EN=0:ICCR), the START condition is not detected (BB=0:IBSR) with I2C bus
occupied.
Figure 16.2-4 Timing Diagram for No Occurrence of Interrupt Caused by Arbitration Lost Detect
Start Condition
INT bit interrupt does
not occur at 9th clock.
Stop Condition
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DATA
ACK
EN bit
MSS bit
AL bit
BB bit
0
INT bit
0
If these may occur, the following procedure needs to be executed on a software.
1) Execute a command causing generation of the START condition (MSS=1:IBCR).
2) Wait for 3-bit data transmission at the I2C transfer frequency set in ICCR by using timer
function or other. (*)
Example:
I2C transfer frequency = 100 kHz
3-bit data transmission time = {1 / (100 ✕ 103)} ✕ 3 = 30 ms
(*): If the arbitration lost is detected, AL will be "1" after the 3-bit data transmission at the
I2C transfer frequency subsequent to MSS bit setting.
3) Check AL bit and BB bit of IBSR. If AL is "1" and BB is "0", initialize I2C by setting EN bit of
ICCR to "0".
If state of AL bit and BB bit is other than above, execute the normal process.
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MB91461
A flow example is shown below.
Master mode setting
Set MSS bit of the bus control register (IBCR) to "1"
Wait for 3-bit data transmission at the I2C transfer
frequency set in the clock control register (ICCR).
NO
BB=0 and AL=1
YES
Set EN bit and initialize I2C
Normal process
• Occurrence of interrupt caused by arbitration lost detect
With the bus busy detected (BB=1:IBSR), if a command causing generation of the START
condition is executed (MSS=1:IBCR) and the arbitration lost is performed, INT will be "1" when
AL=1 is detected and interrupt will occur.
Figure 16.2-5 Occurrence of Interrupt Caused by Arbitration Lost Detect
Interrupt occurs at 9th clock.
Start Condition
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DATA
EN bit
MSS bit
AL bit
AL bit cleared by software
BB bit
INT bit cleared by software
and SCL freed
INT bit
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16.2 I2C Interface Register
16.2.3
MB91461
Clock Control Register (ICCR)
The clock control register (ICCR) has the following functions.
• Noise filter enable
• I2C interface operation enable
• Serial clock frequency set
■ Clock Control Register (ICCR)
Figure 16.2-6 shows the bit configuration of the clock control register (ICCR).
Figure 16.2-6 Bit Configuration of Clock Control Register (ICCR)
ICCR
Address: 0000DAH, 0000E6H bit15
000372H Reserved
14
13
12
11
10
9
8
NSF
EN
CS4
CS3
CS2
CS1
CS0
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
0
0
1
1
1
1
1
[bit15] Reserved: Reserved bit
Always read value of this bit is "0".
[bit14] NSF: Noise filter enable bit
This bit enables the noise filter placed on SDA pin and SCL pin. This noise filter suppresses input
spikes (CLKP 1 to CLKP 1.5 cycle). When the transmit/receive rate is 100 kbps or faster, set this bit to
"1".
[bit13] EN: Operation enable bit
This bit enables the operation of the I2C interface.
Table 16.2-19 EN (Operation Enable Bit)
Value
Description
0
Operation disabled [Initial value]
1
Operation enabled
Notes:
• When the operation of the I2C interface is prohibited, transmission/reception is stopped at once.
• Please prohibit operating after confirming the generation of the stop condition (IBSR:BB=0) when
you prohibit the operation of the I2C interface after "0" is written in the MSS bit and the stop
condition is generated (ICCR:EN=0).
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16.2 I2C Interface Register
MB91461
[bit12 to bit8] CS4 to CS0: Clock period select bit
These bits set the serial clock frequency.
These bits can be written to only when operation of the I2C interface is disabled (EN=0) or when the
EN bit is cleared.
The shift clock frequency (fsck) is set by the following expression:
[Noise filter disabled]
φ
fsck =
n × 12+18
N>0
φ : Peripheral clock (=CLKP)
N>0
φ : Peripheral clock (=CLKP)
(+1) means uncertainty of noise filter
[Noise filter enabled]
φ
fsck =
n × 12+19(+1)
Table 16.2-20 Register Setting
N
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
···
···
···
···
···
···
31
1
1
1
1
1
Setting of CS4 to CS0=00000B is disabled.
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16.2 I2C Interface Register
16.2.4
MB91461
10-bit Slave Address Register (ITBA)
This section describes configuration and function of the 10-bit slave address register
(ITBA).
■ 10-bit Slave Address Register (ITBA)
Figure 16.2-7 shows the bit configuration of the 10-bit slave address register (ITBA) is as the following.
Figure 16.2-7 Bit Configuration of 10-bit Slave Address Register (ITBA)
ITBAH
Address: 0000D2H, 0000DEH bit15
14
13
12
11
10
00036AH Reserved Reserved Reserved Reserved Reserved Reserved
9
8
TA9
TA8
Read/Write
−
−
−
−
−
−
R/W
R/W
Initial value
−
−
−
−
−
−
0
0
Address: 0000D3H, 0000DFH
bit7
6
5
4
3
2
1
0
00036BH
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
ITBAL
Perform writing to the 10-bit slave address register (ITBA) when the I2C interface is disabled
(EN=0:ICCR).
[bit15 to bit10] Reserved: Reserved bits
"0" is always read from these bits.
[bit9 to bit0] TA9 to TA0: 10-bit slave address bit
When a slave address is received in the slave mode with the 10-bit address enabled (ITMK:ENTB=1),
the received address and ITBA are compared.
Acknowledge is transmitted to the master after the address header at the 10-bit write access is received.
The first/second byte (receive data) compares with the ITBAL register. When a match is detected, the
acknowledge signal is transmitted to the master device, setting the AAS bit.
The I2C interface responds to reception of the address header at the 10-bit read access after occurrence
of the iterative START condition.
All the bits of the slave address are masked by the ITMK setting. The receive slave address is
overwritten by the ITBA register. This register (ITBA register) is enabled only when AAS (IBSR
register) is "1".
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CHAPTER 16 I2C INTERFACE
16.2
MB91461
16.2.5
10-bit Slave Address Mask Register (ITMK)
I2C Interface Register
This section describes configuration and function of the 10-bit slave address mask
register (ITMK) .
■ 10-bit Slave Address Mask Register (ITMK)
Figure 16.2-8 shows the bit configuration of the 10-bit slave address mask register (ITMK).
Figure 16.2-8 Bit Configuration of 10-bit Slave Address Mask Register (ITMK)
ITMKH
Address: 0000D4H, 0000E0H bit15
00036CH ENTB
14
RAL
13
12
11
10
Reserved Reserved Reserved Reserved
9
8
TM9
TM8
Read/Write
R/W
R
−
−
−
−
R/W
R/W
Initial value
0
0
−
−
−
−
1
1
Address: 0000D5H, 0000E1H
bit7
6
5
4
3
2
1
0
00036DH
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
1
1
1
1
1
1
1
1
ITMKL
[bit15] ENTB: 10-bit slave address enable bit
This bit enables the 10-bit slave address operation.
Write to this bit when the I2C interface is stopped (ICCR:EN=0).
[bit14] RAL: Slave address length bit
This bit indicates the slave address length.
This bit can be used to determine which transfer length (10 bits or 7 bits) will be enabled when both the
10-bit slave address operation enable bit and the 7-bit slave address operation enable bit are enabled
(ENTB=1 and ENSB=1).
This bit is enabled when the AAS bit (IBSR) is "1".
This bit is cleared when operation of the interface is disabled (ICCR:EN=0).
This bit is read only.
[bit13 to bit10] Reserved: Reserved bit
"1" is always read from these bits.
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16.2 I2C Interface Register
MB91461
[bit9 to bit0] TM9 to TM0: 10-bit slave address mask bit
These bits mask bits of the 10-bit slave address register (ITBA). Write to this register when operation of
the I2C interface is disabled (ICCR:EN=0).
Setting these bits makes it possible to transmit acknowledge to the composite 10-bit slave address. Set
these bits to "1" when using this register at comparison of the 10-bit slave address. The received slave
address is overwritten by ITBA. When ASS=1 (IBSR), the specified slave address can be identified by
reading the ITBA register.
Each bit (TM9 to TM0) of ITMK corresponds to each bit of the ITBA address. When the value of TM9
to TM0 is "1", the ITBA address is enabled; when the value of TM9 to TM0 is "0", the ITBA address is
disabled.
Example: When ITBA address = 0010010111B
and ITMK address = 1111111100B,
the slave address area is 0010010100B to 0010010111B.
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16.2 I2C Interface Register
MB91461
16.2.6
7-bit Slave Address Register (ISBA)
This section describes configuration and function of the 7-bit slave address register
(ISBA).
■ 7-bit Slave Address Register (ISBA)
Figure 16.2-9 shows the bit configuration of the 7-bit slave address register (ISBA).
Figure 16.2-9 Bit Configuration of 7-bit Slave Address Register (ISBA)
ISBA
Address: 0000D7H, 0000E3H
bit7
00036FH Reserved
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Read/Write
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
0
0
0
0
0
0
0
Perform writing to the 7-bit slave address register (ISBA) when the I2C interface is disabled (EN=0:ICCR).
[bit7] Reserved: Reserved bit
"0" is always read from this bit.
[bit6 to bit0] SA6 to SA0: Slave address bit
When 7-bit slave address is already enabled (ISMK:ENSB=1) when a slave address is received in the
slave mode, the received slave address and ISBA are compared. When a slave address match is detected,
acknowledge is transmitted to the master, setting the AAS bit.
The I2C interface returns acknowledge in response to reception of the address header at the 7-bit read
access after the occurrence of the iterative START condition.
All the bits of the slave address are masked by the ISMK setting. The receive slave address is
overwritten by the ISBA register. This register is enabled only when the AAS register (IBSR register) is
"1".
The I2C interface does not compare ISBA with the receive slave address when the 10-bit slave address
is specified or the general call is received.
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16.2 I2C Interface Register
16.2.7
MB91461
7-bit Slave Address Mask Register (ISMK)
The 7-bit slave address mask register (ISMK) includes the 7-bit slave address mask and
the 7-bit slave address enable bit.
■ 7-bit Slave Address Mask Register (ISMK)
Figure 16.2-10 shows the bit configuration of the 7-bit slave address mask register (ISMK).
Figure 16.2-10 Bit Configuration of 7-bit Slave Address Mask Register (ISMK)
ISMK
Address: 0000D6H, 0000E2H bit15
00036EH ENSB
14
13
12
11
10
9
8
SM6
SM5
SM4
SM3
SM2
SM1
SM0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
1
1
1
1
1
1
1
Perform writing to the 7-bit slave address mask register (ISMK) when the I2C interface is disabled
(EN=0:ICCR).
[bit15] ENSB: 7-bit slave address enable bit
This is the 7-bit slave address operation enable bit.
[bit14 to bit8] SM6 to SM0: 7-bit slave address mask bit
These bits mask the bits of the 7-bit slave address register (ISBA).
Setting these bits makes it possible to transmit acknowledge to the composite 7-bit slave address. When
using this register at comparison of the 7-bit slave address, set these bits to "1". The received slave
address is overwritten by ISBA. When ASS=1 (IBSR), the specified slave address can be identified by
reading the ISBA register.
After the I2C interface is enabled, the slave address (ISBA) is rewritten by the reception operation;
when the slave address is rewritten by ISMK, operation may not be as expected unless ISMK is re-set.
Each bit (SM6 to SM0) of ISMK corresponds to each bit of the ISBA address. When the value of SM6
to SM0 is "1", the ISBA address is enabled; when the value of SM6 to SM0 is "0", the ISBA address is
disabled.
Example: When ISBA address = 0010111B
and ISMK address =1111100B,
the slave address area is 0010100B to 0010111B.
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CHAPTER 16 I2C INTERFACE
16.2 I2C Interface Register
MB91461
16.2.8
Data Register (IDAR)
This section describes the data register (IDAR).
■ Data Register (IDAR)
Figure 16.2-11 shows the bit configuration of the data register (IDAR).
Figure 16.2-11 Bit Configuration of Data Register (IDAR)
IDAR
Address: 0000D9H, 0000E5H
bit7
6
5
4
3
2
1
0
000371H
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit7 to bit0] D7 to D0: Data bit
The data register (IDAR) is used for serial transfer. This register is transferred from MSB.
The write side of the IDAR register has a double buffer. When the bus is busy (BB=1), write data is
loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or when the bus is idle
(IBSR:BB=0), transfer data is loaded into the internal transfer register.
At reading, the register for serial transfer is read directly, so receive data is valid only when the INT bit
(IBCR) is set.
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16.3 Explanation of I2C Interface Operation
16.3
MB91461
Explanation of I2C Interface Operation
The I2C bus is a bidirectional bus with one serial data line (SDA) and one serial clock
line (SCL).
The I2C interface has two open-drain I/O pins (SDA and SCL) to provide wired logic.
■ START Condition
When "1" is written to the MSS bit with the bus free (BB=0, MSS=0), the I2C interface enters into the
master mode, generating the START condition. At this time, it transmits the value of the IDAR register as
the slave address.
When "1" is written to the SCC bit, with the bus master mode enabled and with the interrupt flag set
(IBCR:MSS=1, INT=1), the iterative START condition is generated.
When "1" is written to the MSS bit with the bus in use (IBSR:BB=1, TRX=0, MSS=0 or IBCR:INT=0), the
bus is freed and transmission is started.
When write (reception) access is made in the slave mode, transfer ends, the bus is freed and transmission
starts. When the interface is transmitting data at this time, transmission does not occur even when the bus is
freed.
The interface must be checked for the following:
• Whether or not the interface is specified as the slave (IBCR:MSS=0, IBSR:AAS=1)
• Whether or not the data byte can be transmitted normally at the next interrupt (IBSR:AL=1)
■ STOP Condition
When "0" is written to the MSS bit, with the master mode in effect (IBCR:MSS=1, INT=1), the STOP
condition is generated, making a transition to the slave mode. When "0" is written to the MSS bit under
other conditions, the write is ignored.
An attempt is made to generate the STOP condition after the MSS bit is cleared. When the SCL line is
driven to "L" before generating the STOP condition, the STOP condition is not generated. An interrupt is
generated after the next byte is transferred.
Note:
It takes some time from when "0" is written to the MSS bit until the STOP condition is generated.
When operation of the I2C interface is disabled (ICCR:EN=0) before generating the START
condition, the I2C interface stops immediately, generating illegal clocks in the SCL line. When
disabling operation of the I2C interface (ICCR:EN=0), do so after ensuring that the START condition
is generated (IBSR:BB=0).
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16.3 Explanation of I2C Interface Operation
MB91461
■ Slave Address Detection
In the slave mode, the START condition is generated and then BB is set to "1", transmitting the data from
the master to the IDAR register.
[When 7-bit slave address operation enabled] (ENSB=1 in ISMK)
After reception of 8-bit data, the IDAR register and the ISBA register are compared. At comparison,
each bit of the ISBA register is masked by the ISMK register.
When a match occurs, AAS is set to "1", transmitting an acknowledge to the master. After this, bit0 of
the receive data (bit0 of IDAR register after reception) is reversed and then stored in the TRX bit.
[When 10-bit slave address operation enabled] (ENTB=1 in ITMK)
When the 10-bit address header section (11110B, TA1, TA0, write) is detected, an acknowledge is
transmitting to the master, and bit0 of the receive data is reversed and then stored in the TRX bit. No
interrupt occurs at this time.
Then, the next transfer data and ITBA register low-order data are compared. At this comparison, each
bit of the ITBA register is masked by the ISMK register.
When a match occurs, AAS is set to "1", sending an acknowledge to the master. An interrupt occurs at
this time.
When the value is specified as a slave address and the iterative START condition is detected, the 10-bit
address header section (11110B, TA1, TA0, read) is received and then "1" is set at AAS, generating an
interrupt.
There are 10-bit slave address register (ITBA) and 7-bit slave address register (ISBA). An acknowledge
can be transmitted to the 10-bit and 7-bit addresses by enabling both the 10-bit slave address operation
and the 7-bit slave address operation (ENSB=1 in ISMK, ENTB=1 in ITMK).
In the slave mode (AAS=1), the receive slave address length is determined by the RAL bit of the ITMK
register. In the master mode, it is possible not to generate slave addresses in the I2C interface by
disabling operation of both (ISMK:ENSB=0, ITMK:ENTB=0).
All slave addresses can be masked by setting the ITMK and ISMK registers.
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16.3 Explanation of I2C Interface Operation
MB91461
■ Slave Address Mask
The slave address mask register (ITMK, ISMK) can mask each bit of the slave address register. Bits that are
set to "1" by the mask register are subject to address comparison, but bits that are set to "0" are ignored. In
the slave mode (IBSR:AAS=1), receive slave addresses can be read from ITBA (10-bit address) and ISBA
(7-bit address).
When the bit mask is cleared, the slave address register can always be accessed as a slave, so it can be used
as a bus monitor.
Note:
Even if there are no other slave devices, the slave address register returns an acknowledge when a
slave address is received, so the slave address register cannot be used as a real bus monitor.
■ Slave Addressing
In the master mode, after a START condition is generated, the BB bit and TRX bit are set to "1" and the
value in the IDAR register is output from MSB first. When an acknowledge signal is received from the
slave after address data is transmitted, bit0 (of the IDAR register after transmitting data) of transmit data is
inverted and stored in the TRX bit. This operation is also performed under the iterative START condition.
Since the address is a 10-bit slave address write, 2 bytes are transmitted. The first byte is the header "1 1 1 1
0 A9 A8 0" indicating a 10-bit sequence; the second byte is the slave address low-order 8 bits (A7 to A0).
The 10-bit slave address read transmits the above bytes, generating the iterative START condition and the
header "1 1 1 1 0 A9 A8 1" indicating read access simultaneously.
■ Arbitration
Arbitration occurs when one master and another master are transmitting data at the same time. When the
transmit data is "1" and data on the SDA line is Low, arbitration is regarded as having been lost and the AL
bit is set to "1".
At the first bit of data, when an unnecessary START condition is detected or generation of the START
condition or STOP condition fails, AL is set to "1".
When arbitration lost occurs, MSS=0 and TRX=0 will occur, enabling the slave receive mode in which an
acknowledge is returned when the own slave address of the interface is received.
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16.3 Explanation of I2C Interface Operation
MB91461
■ Acknowledge
An acknowledge is transmitted to the transmitting side by the receiving side. At data reception, the ACK bit
(IBCR) can be used to select whether or not to transmit an acknowledge at reception.
Even when an acknowledge is not returned from the master at slave-mode data transmission (read access
from another master), the TRX bit is set to "0", enabling the receive mode. Then, when the slave frees the
SCL line, the master can generate the STOP condition.
In the master mode, whether or not acknowledge is returned can be checked by reading the LRB bit
(IBSR).
If an arbitration lost occurs after transmission of the general call address, set both ACK bit and GCAA bit
to "1" when performing the acknowledge response at receiving data (including generated data). With other
setting, the acknowledge response is not performed.
■ Bus Error
A bus error is regarded as having occurred when the following conditions are met, and the I2C interface is
set in the stopped state.
• A violation of the basic regulations is detected on the I2C bus during data transfer (including ACK bit).
• A STOP condition in the master mode is detected.
• A violation of the basic regulations is detected on the I2C bus when the bus is idle.
■ Communication Error Not Causing Error
When, an illegal clock is generated in the SCL line due to noise, etc., during master mode transmission, the
transmit bit counter of the I2C interface advances fast and may cause a hang-up with "L" set at the SDA line
at the ACK cycle. No error (AL=1,BER=1) occurs for this illegal clock.
In this case, perform error handling as follows:
• When LRB is "1", with MSS set to "1", TRX set to "1", and INT set to "1", determine that a
communication error has occurred.
• Set EN to "0" and then to "1"; SCL will generate one pseudo-clock.
This causes the slave to free the bus.
The period from when EN is set to "0" until it is set to "1" should be the period during which the slave
can recognize the clock (approximately same as the "H" period of the transmit clock).
• When EN is "0", IBSR and IBCR are cleared, so perform retransmission processing under the START
condition. At this time, no STOP condition is generated by BSS=0.
Then, secure a period of "n × 7 × tCPP" or more from when EN is set to "1" until MSS is set to "1"
(START condition).
Example: For high-speed mode: 6 × 7 × 40 ≅ 2.333 μs
For standard mode: 27 × 7 × 40 ≅ 10.50 μs
(CLKP=18 MHz)
Note:
When BER is set, clear does not occur due to EN=0, so perform clear and then retransmission.
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16.3 Explanation of I2C Interface Operation
MB91461
■ Others
• After arbitration lost has occurred, whether or not the interface is addressed must be determined via
software.
When arbitration lost has occurred, the interface is set as a slave via hardware, but after completion of 1byte transfer, both the CLK line and the DATA line are driven to "L". Consequently, if the interface is
not addressed, the CLK line and the DATA line must be freed immediately; if the interface is addressed,
preparations for slave transmission or for slave reception must be made and then the CLK line and the
DATA line must be freed. (These processes must be performed via software.)
• The I2C bus has only one interrupt; so when an interrupt condition is satisfied at completion of 1-byte
transfer, an interrupt factor occurs.
Since two or more interrupt conditions must be determined using one interrupt, each flag must be
checked within the interrupt routine. The interrupt conditions at completion of 1-byte transfer are given
below.
- When bus master
- When slave addressed
- When general call address received
- When arbitration lost occurred
• When arbitration lost is detected, an interrupt factor does not occur immediately; it occurs at completion
of 1-byte transfer.
When arbitration lost is detected, the interface is set as a slave by hardware but an interrupt factor still
occurs, outputting a total of 9 clocks. Since an interrupt factor does not occur immediately arbitration
lost, processing cannot be performed immediately after arbitration lost.
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16.4 Operation Flowchart
MB91461
16.4
Operation Flowchart
This section shows the operation flowchart. The shown examples include slave address
and data transfer, and receive data.
■ Example of Slave Address and Data Transfer
Figure 16.4-1 shows the example of slave address and data transfer.
Figure 16.4-1 Example of Slave Address and Data Transfer
7-bit slave addressing
Transfer data
Start
Start
Clear (or set) BER bit.
Enable interface
operation (EN=1).
Slave address for
write access
IDAR=S; address << 1+RW
IDAR=byte data
MSS=1 INT=0
INT=0
NO
NO
INT=1?
INT=1?
YES
YES
YES
YES
BER=1?
NO
AL=1?
Bus error
BER=1?
NO
YES Perform
reactivation/transfer
via AAS checking.
AL=1?
NO
NO
ACK?
(LRB=0?)
YES Perform
reactivation/transfer
via AAS checking.
NO
ACK?
(LRB=0?)
YES
NO
YES
Prepare for data transfer.
Transfer of
last byte
YES
NO
Completion of trans
t ansfer:
· Slave does not generate ACK or
master cannot receive ACK.
· Set EN to "0" and then perform
retransmission.
CM71-10159-2E
Completion of trans
t ansfer:
·
Generate iterative START
and STOP conditions.
·
Check occurrence of STOP
condition (BB=0)
and then set EN to "0".
FUJITSU MICROELECTRONICS LIMITED
Completion of trans
t ansfer:
At transmission:
· Slave does not generate
ACK or master cannot
receive ACK.
· Set EN to "0" and then
perform retransmission.
At reception:
ACK not generated;
generate the iterative START
and STOP conditions.
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CHAPTER 16 I2C INTERFACE
16.4 Operation Flowchart
MB91461
■ Example of Receive Data
Figure 16.4-2 shows the example of receive data.
Figure 16.4-2 Example of Receive Data
Start
Slave address of
read access
When the data is the last
read data from the slave,
clear the ACK bit.
INT=0
NO
INT=1?
YES
YES
BER=1?
Bus error; perform
reactivation.
NO
NO
Transfer of
the last byte
YES
Completion of transfer:
Generate the iterative START
and STOP conditions.
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CHAPTER 16 I2C INTERFACE
16.4 Operation Flowchart
MB91461
■ Interrupt Handling
Figure 16.4-3 shows the interrupt handling.
Figure 16.4-3 Interrupt Handling
Start
NO
Receive interrupt
from other modules
INT=1?
YES
BER=1?
YES Bus error; perform
reactivation.
NO
YES
GCA=1?
NO
NO
Transfer failed;
retry.
Detect general call during
slave mode.
YES
AAS=1?
YES
AL=1?
AL=1?
YES Arbitration lost;
perform transfer again.
NO
NO
YES
LRB=1?
YES
ADT=1?
Start new data transfer
at next interrupt;
if necessary,
change ACK bit.
No slave ACK;
generate STOP and
iterative START
conditions.
NO
YES
NO
TRX=1?
YES
NO
TRX=1?
NO
Read receive data
from IDAR.
if necessary,
Change ACK bit.
Write next
transmit
data to
IDAR.
Read receive data
from IDAR.
If necessary,
change ACK bit.
Write next transmit
data to IDAR or
clear MSS bit.
Clear INT bit.
Completion of ISR
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16.4 Operation Flowchart
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CHAPTER 17
16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the
configuration and functions of registers, and 16-bit
reload timer operation.
17.1 Overview of the 16-bit Reload Timer
17.2 16-bit Reload Timer Registers
17.3 16-bit Reload Timer Operation
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17.1 Overview of the 16-bit Reload Timer
17.1
MB91461
Overview of the 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a
prescaler for creating an internal count clock, and a control register.
■ Overview of the 16-bit Reload Timer (RLT)
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating
an internal count clock, and a control register.
This device has 5 channels of 16-bit reload timers (RLT0 to RLT3, RLT7). One of them (RLT7) can be
used for A/D convert trigger.
The clock source can be selected from three internal clocks (resource clock divided by 2, 8, and 32) and an
external event (An external event cannot be selected for only RLT7).
■ Block Diagram of 16-bit Reload Timer
Figure 17.1-1 shows the block diagram of the 16-bit reload timer.
Figure 17.1-1 Block Diagram of the 16-bit Reload Timer
16-bit reload register
(TMRLR)
Reload
R-bus
16-bit down counter
(THR)
RELD
UF
OUTL
OUT
CTL
Count
enable
INTE
UF
CNTE
IRQ
TRG
Clock
selector
CSL1
CSL0
EXCK
Prescaler
Prescaler
clear
External timer
output
IN CTL
CSL1
CSL0
TOE0 to TOE3
External
trigger selection
Bits in PFRK
External trigger input
φ
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CHAPTER 17 16-BIT RELOAD TIMER
17.2 16-bit Reload Timer Registers
MB91461
17.2
16-bit Reload Timer Registers
This section describes the configuration and functions of registers used by the 16-bit
reload timer.
■ 16-bit Reload Timer Registers
Figure 17.2-1 16-bit Reload Timer Registers
TMCSR (Upper)
14
13
12
Address: 0001B6H, 0001BEH bit15
0001C6H, 0001CEH Reserved Reserved Reserved Reserved
0001EEH
11
10
CL1
CSL0
9
8
MOD2 MOD1
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
4
3
2
1
0
RELD
INTE
UF
CNTE
TRG
TMCSR (Lower)
6
5
Address: 0001B7H, 0001BFH bit7
0001C7H, 0001CFH MOD0 Reserved OUTL
0001EFH
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
TMR
Address: 0001B2H, 0001BAH bit15
0001C2H, 0001CAH
0001EAH
0
Read/Write
R
Initial value
xxxxH
TMRLR
Address: 0001B0H, 0001B8H bit15
0001C0H, 0001C8H
0001E8H
CM71-10159-2E
0
Read/Write
W
Initial value
xxxxH
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17.2 16-bit Reload Timer Registers
17.2.1
MB91461
Control Status Register (TMCSR)
The control status register (TMCSR) controls the 16-bit timer operating modes and
interrupts.
■ Bit Configuration of the Control Status Register (TMCSR)
Figure 17.2-2 Bit Configuration of the Control Status Register (TMCSR)
TMCSR (Upper)
14
13
12
11
Address: 0001B6H, 0001BEH bit15
0001C6H, 0001CEH Reserved Reserved Reserved Reserved CSL1
0001EEH
10
CSL0
9
8
MOD2 MOD1
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
4
3
2
1
0
RELD
INTE
UF
CNTE
TRG
TMCSR (Lower)
6
5
Address: 0001B7H, 0001BFH bit7
0001C7H, 0001CFH MOD0 Reserved OUTL
0001EFH
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit15 to bit12] Reserved: Reserved bit
These bits are reserved.
In a read operation, 0000B is always read.
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CHAPTER 17 16-BIT RELOAD TIMER
17.2 16-bit Reload Timer Registers
MB91461
[bit11, bit10] CSL1, CSL0: Count source select bit
These bits are the count source select bits. Either an internal clock or an external event can be selected
as the count source.
The following table lists the count sources that can be selected using these bits.
An external event cannot be selected for only RLT7. Set other than CSL1=CSL0=1.
Table 17.2-1 CSL1, CSL0 (Count Source Select Bit)
Count source
(φ: Resource clock)
φ=18 MHz
φ=9 MHz
φ/21 [Initial value]
0.11 μs
0.22 μs
Internal clock
φ/23
0.44 μs
0.89 μs
0
Internal clock
φ/25
1.78 μs
3.56 μs
1
External event
−
−
CSL1
CSL0
0
0
Internal clock
0
1
1
1
Countable edges used when an external event is the count source are set using the MOD1 and MOD0
bits.
The minimum pulse width required for an external clock is 2 × T (T: peripheral clock machine cycle).
[bit9, bit8, bit7] MOD2, MOD1, MOD0: Mode bit
These bits set the operating modes. These bits have different functions if the count source is an internal
clock or an external clock.
• Internal clock: Reload trigger setting
• External clock: Count valid edge setting
Be sure to set "0" for MOD2.
[Reload trigger setting used when an internal clock is selected]
If the selected count source is an internal clock and a valid edge is input according to the setting of the
MOD2, MOD1, and MOD0 bits, the contents of the reload register are loaded, and the count operation
is continued.
There is no external trigger pin for RLT7, so always set MOD[2:0] = 000B (software trigger).
Table 17.2-2 MOD2, MOD1, MOD0 (Mode Bit)
CM71-10159-2E
MOD2
MOD1
MOD0
Valid edge
0
0
0
Software trigger [initial value]
0
0
1
External trigger (rising edge)
0
1
0
External trigger (falling edge)
0
1
1
External trigger (both edges)
1
X
X
Setting disabled
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17.2 16-bit Reload Timer Registers
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[Valid edge setting used when an external clock is selected]
If the selected count source is an external event and a valid edge is input according to the setting of the
MOD2, MOD1, and MOD0 bits, events are counted.
Table 17.2-3 MOD2, MOD1, MOD0 (Mode Bit)
MOD2
MOD1
MOD0
Valid edge
X
0
0
− [Initial value]
X
0
1
External trigger (rising edge)
X
1
0
External trigger (falling edge)
X
1
1
External trigger (both edges)
Reloading during an external event occurs for an underflow and a software trigger.
[bit6] Reserved: Reserved bit
This bit is reserved.
In a read operation, "0" is always read.
[bit5] OUTL: Output level
This bit sets the external timer output level. The output level is reversed depending on whether this bit
is "0" or "1".
The timer output of RLT7, which has no external output pin, is connected to A/D converter. When
RLT7 is selected as A/D convert trigger, the A/D converter starts to convert using the rising edge of the
timer output as the trigger. See the after-mentioned notice.
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CHAPTER 17 16-BIT RELOAD TIMER
17.2 16-bit Reload Timer Registers
MB91461
[bit4] RELD: Reload enable bit
This bit is the reload enable bit. When it is set to "1", reload mode is started. As soon as the counter
value underflows from 0000H to FFFFH, the contents of the reload register are loaded into the counter,
and the count operation is continued.
When this bit is set to "0", one-shot mode is started. As soon as the counter value underflows from
0000H to FFFFH, counter operation stops.
Table 17.2-4 RELD (Reload Enable Bit)
PFRxy
OUTL
RELD
0
X
X
Output disabled [initial state]
0
"H" level square wave during counting
• Count stop: "L"
• Count in process: "H"
• Underflow: "L"
1
"L" level toggle output when the counter starts
• Count stop: "L"
• Count in process: "L"
→ Toggle output every underflow
0
"L" level square wave during counting
• Count stop: "H"
• Count in process: "L"
• Underflow: "H"
1
"H" level toggle output when the counter starts
• Count stop: "H"
• Count in process: "H"
→ Toggle output every underflow
1
1
1
1
0
0
1
1
Output waveform
PFRxy represents PFR register value of the corresponding pin.
[bit3] INTE: Interrupt request enable bit
This bit is the interrupt request enable bit. When the INTE bit is set to "1" and the UF bit is set to "1",
an interrupt request is generated. When the INTE bit is set to "0", no interrupt request is generated.
[bit2] UF: Underflow interrupt flag
This bit is the timer interrupt request flag. As soon as the counter value underflows from 0000H to
FFFFH, this bit is set to "1". Write "0" to this bit to clear it.
Writing "1" to this bit is meaningless.
A read-modify-write (RMW) instruction always reads "1" from this bit.
[bit1] CNTE: Count enable bit
This bit is the timer count enable bit. Write "1" to this bit to enter the start trigger wait state. Write "0"
to this bit to stop the count operation.
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17.2 16-bit Reload Timer Registers
MB91461
[bit0] TRG: Trigger bit
This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the contents
of the reload register into the counter, and start the count operation.
Writing "0" to this bit is meaningless. The read value is always "0".
The trigger input to this register is valid only if CNTE=1. No effect occurs if CNTE=0.
Notes:
• Rewrite bits other than UF, CNTE, and TRG only when CNTE=0.
• Do not set OUTL bit and CNTE/TRG simultaneously.
When RLT7 is selected as A/D convert trigger, the register setting order of OUTL bit and A/D
converter may cause the A/D converter to start at unintended timing because the A/D converter
starts to convert using the rising edge of the timer output as the trigger.
For example, to start A/D convert when the counter underflows in one-shot mode of RLT7, set as
the following procedure.
Set OUTL bit. (OUTL setting of TMCSR)
→ Set A/D convert trigger selection. (STS1 and STS0 setting of ADCS1)
→ RLT7 count start (CNTE and TRG setting of TMCSR)
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CHAPTER 17 16-BIT RELOAD TIMER
17.2 16-bit Reload Timer Registers
MB91461
17.2.2
16-bit Timer Register (TMR)
The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer.
■ Bit Configuration of the 16-bit Timer Register (TMR)
Figure 17.2-3 Bit Configuration of the 16-bit Timer Register (TMR)
TMR
Address: 0001B2H, 0001BAH bit15
0001C2H, 0001CAH
0001EAH
0
Read/Write
R
Initial value
xxxxH
The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer. The initial value is
undefined. Be sure to read this register using a 16-bit data transfer instruction.
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CHAPTER 17 16-BIT RELOAD TIMER
17.2 16-bit Reload Timer Registers
17.2.3
MB91461
16-bit Reload Register (TMRLR)
The 16-bit reload register (TMRLR) holds the initial value of a counter.
■ Bit Configuration of the 16-bit Reload Register (TMRLR)
Figure 17.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR)
TMRLR
Address: 0001B0H, 0001B8H bit15
0001C0H, 0001C8H
0001E8H
0
Read/Write
W
Initial value
xxxxH
The 16-bit reload register (TMRLR) holds the initial value of a counter. The initial value is undefined. Be
sure to read this register using a 16-bit data transfer instruction.
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CHAPTER 17 16-BIT RELOAD TIMER
17.3 16-bit Reload Timer Operation
MB91461
17.3
16-bit Reload Timer Operation
This section describes the following operations of the 16-bit reload timer:
• Internal clock operation
• Underflow operation
• Operation of the output pin function
■ Internal Clock Operation
If the timer operates with a divide-by clock of the internal clock, one of the clocks created by dividing the
machine clock by 2, 8, or 32 can be selected as the clock source.
To start a count operation as soon as counting is enabled, write 1 to the CNTE and TRG bits of the control
status register.
While the timer is running (CNTE=1), trigger input occurring due to the TRG bit is always valid, regardless
of the operating mode.
Time T (T: resource clock machine cycle) is required between input of the counter start trigger and the
actual loading the reload register data into the counter.
Figure 17.3-1 Startup and Operations of the Counter
Count clock
Reload data
Counter
-1
-1
-1
Data load
CNTE register
TRG register
T
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CHAPTER 17 16-BIT RELOAD TIMER
17.3 16-bit Reload Timer Operation
MB91461
■ Underflow Operation
An underflow is an event occurring when the counter value changes from 0000H to FFFFH. Thus, an
underflow occurs when the count is [reload register setting value + 1].
If the RELD bit of the control status register is set to "1" when an underflow occurs, the contents of the reload
register are loaded, and the count operation is continued. If the RELD bit is set to "0", the counter stops at
FFFFH.
Figure 17.3-2 Underflow Operation
RELD=1
Count clock
Counter
0000H
Reload data
0000H
FFFFH
-1
-1
-1
Data load
Underflow set
RELD=0
Count clock
Counter
Underflow set
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CHAPTER 17 16-BIT RELOAD TIMER
17.3 16-bit Reload Timer Operation
MB91461
■ Operation of the Output Pin Function
The TOT pins provide toggle output that is reversed for an underflow in reload mode or pulse output that
indicates that counting is in progress in one-shot mode. The output polarity can be set in the OUTL bit of
the register. If OUTL=0, toggle output is "0" for the initial value and the one-shot pulse output is "1" while
a count operation is in progress. If OUTL=1, the output waveform is reversed.
Figure 17.3-3 Output Pin Function Operation [RELD=1, OUTL=0]
Count started
Underflow
Reversed if OUTL=1
TOT0 to TOT3
CNTE
Generalpurpose port
Startup trigger
Figure 17.3-4 Output Pin Function Operation [RELD=0, OUTL=0]
Count started
Underflow
TOT0 to TOT3
CNTE
Reversed if OUTL=1
Generalpurpose port
Startup trigger
Startup trigger wait status
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CHAPTER 17 16-BIT RELOAD TIMER
17.3 16-bit Reload Timer Operation
MB91461
■ Operating States of the Counter
The counter state is determined by the CNTE bit of the control register and the WAIT signal, which is an
internal signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state);
the startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT status); and the operation state, when
CNTE=1 and WAIT=0 (RUN state)
Figure 17.3-5 Status Transitions of the Counter.
Reset
State transition caused by hardware
State transition caused by register access
STOP
CNTE=0, WAIT=1
Counter: Retains the value
when it stops;
undefined just after reset
CNTE=1
TRG=0
WAIT
CNTE=1
TRG=1
CNTE=1, WAIT=1
Counter: Retains the value when
it stops; undefined from just after
reset until data is loaded
TRG=1
LOAD
RUN
RELD · UF
CNTE=1, WAIT=0
Counter: Running
TRG=1
CNTE=1,WAIT=0
Loads contents of reload register
into counter
RELD · UF
Loading completed
■ Notice
• The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1 (timer
enable: CNTE) of the control status register is set to "1".
• If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the
clear operation does not occur.
• If the device attempts to write to and reload the data into the 16-bit reload register at the same time, old
data is loaded into the counter. New data is loaded into the counter only at the next reload timing.
• If the device attempts to load and count the 16-bit timer register at the same time, the load (reload)
operation takes precedence.
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CHAPTER 18
16-BIT FREE-RUN TIMER
This chapter describes the functions and operation of
the 16-bit free-run timer.
18.1 Overview of 16-bit Free-run Timer
18.2 16-bit Free-run Timer Registers
18.3 16-bit Free-run Timer Operation
18.4 Notes on Using the 16-bit Free-run Timer
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18.1 Overview of 16-bit Free-run Timer
18.1
MB91461
Overview of 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit timer (up counter) and control circuit. The
16-bit free-run timer can be used with input capture and/or output compare.
■ Overview of 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter and control status register. The count value from
the 16-bit free-run timer is used as the base time (base timer) for the output compare and the input capture.
• The count clock can be selected from four different clocks.
• An interrupt can be generated when a counter overflow occurs.
• A mode setting is available that initializes the counter when a match with the value in compare register
in the output compare occurs.
• The free-run timer, the input capture, and the output compare unit operate cooperatively by the
following combinations.
- Free-run timer 0, input capture 0, 1
- Free-run timer 1, input capture 2, 3
- Free-run timer 2, output compare 0, 1
- Free-run timer 3, output compare 2, 3
■ Block Diagram of the 16-bit Free-run Timer
Interrupt
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Frequency
divider
φ
R-bus
FRCK
Clock selection
16-bit free-run timer
(TCDT)
Clock
To internal circuit (T15 to T00)
Comparator
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.2 16-bit Free-run Timer Registers
MB91461
18.2
16-bit Free-run Timer Registers
This section describes the 16-bit free-run timer registers.
■ 16-bit Free-run Timer Registers
Figure 18.2-1 Bit Configuration of 16-bit Free-run Timer Registers
TCDT (Upper)
bit15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
IVF
IVFE
CLR
CLK1
CLK0
Address: 0001F0H, 0001F4H
0001F8H, 0001FCH
TCDT (Lower)
Address: 0001F1H, 0001F5H
0001F9H, 0001FDH
TCCS
Address: 0001F3H, 0001F7H ECLK
0001FBH, 0001FFH
CM71-10159-2E
STOP MODE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
x
0
0
0
0
0
0
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.2 16-bit Free-run Timer Registers
18.2.1
MB91461
Timer Data Register (TCDT)
The timer data register is used to read the count value of the 16-bit free-run timer.
■ Timer Data Register (TCDT)
Figure 18.2-2 Bit Configuration of Timer Data Register (TCDT)
TCDT (Upper)
bit15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Address: 0001F0H, 0001F4H
0001F8H, 0001FCH
TCDT (Lower)
Address: 0001F1H, 0001F5H
0001F9H, 0001FDH
The counter value of the timer data register is initialized to 0000H by a reset. Write to this register to set the
timer value.
Note that this register must be written to in the stop state (STOP=1 in TCCS register).
The 16-bit free-run timer is initialized as a result of the following:
• Reset
• Setting the clear bit (CLR) of the timer control status register to "1"
• Match of the value of the compare clear register in the output compare and the counter value (Mode
setting is required).
Note:
Access to the TCDT register must be half word (16 bits) access.
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.2
MB91461
18.2.2
Timer Control Status Register (TCCS)
16-bit Free-run Timer Registers
The timer control status register (TCCS) is used to control the count value of the 16-bit
free-run timer.
■ Timer Control Status Register (TCCS)
TCCS
bit7
Address: 0001F3H, 0001F7H ECLK
0001FBH, 0001FFH
6
5
4
IVF
IVFE
3
STOP MODE
2
1
0
CLR
CLK1
CLK0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
x
0
0
0
0
0
0
[bit7] ECLK: Clock selection bit
This bit selects either the internal count clock source or external count clock source for the 16-bit freerun timer. Change the clock source while the output compare and input capture are stopped.
Table 18.2-1 Clock Selection Bit
ECLK
Clock selection
0
Selects the internal clock source (CLKP) [Initial value]
1
Selects the external pin (FRCK)
Note:
If the internal clock is selected, set the count clock in bit1 and bit0 (CLK1 and CLK0 of the TCDT
register). This count clock is handled as the base clock.
The minimum pulse width required for the external clock is 2 x T (T: peripheral clock machine cycle).
If the external clock is specified and the output compare is used, a compare match or interrupt
occurs at the next clock cycle. For a compare match to be output and an interrupt to occur, at least
one clock cycle must be input after the compare match.
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.2 16-bit Free-run Timer Registers
MB91461
[bit6] IVF: Interrupt request flag
IVF is the interrupt request flag of the 16-bit free-run timer.
When the 16-bit free-run timer overflows or when, as a result of the mode setting, a match with
compare register is detected, this bit is set to "1".
An interrupt occurs when the interrupt request enable bit (IVFE) is set.
Write "0" to this bit to clear it. A read-modify-write (RMW) instruction always reads "1" from this bit.
Table 18.2-2 Interrupt Request Flag
IVF
Interrupt request flag
0
No interrupt request
1
Interrupt request
Note:
The initial value of the IVF bit immediately after a reset clear is "0". But, after an overflow occurs, the
initial value of the IVF bit read is "1" because the timer counter automatically performs the count
operation following a reset clear.
[bit5] IVFE: Interrupt enable bit
IVFE is the interrupt enable bit of the 16-bit free-run timer.
When this bit is set to "1" and the interrupt flag (IVF) is set to "1", an interrupt occurs.
Table 18.2-3 Interrupt Enable Bit
IVFE
Interrupt enabled
0
Interrupt disabled [Initial value]
1
Interrupt enabled
[bit4] STOP: Stop bit
The STOP bit is used to stop counting by the 16-bit free-run timer.
Table 18.2-4 Stop Bit
STOP
Count operation
0
Counting enabled (operation) [Initial value]
1
Counting disabled (stop)
Note:
When the 16-bit free-run timer stops, the output compare operation also stops.
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.2 16-bit Free-run Timer Registers
MB91461
[bit3] MODE: Mode setting bit
The MODE bit is used to set the initialization conditions of the 16-bit free-run timer.
When this bit is set to "0", the counter value can be initialized by a reset and the clear bit (bit2: CLR).
When this bit is set to "1", the counter value can be initialized as the result of a match with the value of
compare register of the output compare as well as by a reset and the clear bit (bit2: CLR).
Table 18.2-5 Mode Setting Bit
MODE
Timer initialization condition
0
Initialization caused by a reset or the clear bit [Initial value]
1
Initialization caused by a reset, the clear bit, or compare register
[bit2] CLR: Timer clear bit
The CLR bit is used to initialize the value of the operating 16-bit free-run timer to 0000H.
When "1" is written to this bit, the timer value is initialized to 0000H.
"0" is always read from this bit.
Note:
The counter value is initialized at the change point of the count value. After "1" is written to CLR bit,
the counter clear request is canceled if "0" is written to the CLR bit before the counter is cleared.
To initialize the counter value while the timer is stopped, write 0000H to the data register.
[bit1, bit0] CLK1, CLK0: Count clock selection bits
The CLK1 and CLK0 bits are used to select the count clock of the 16-bit free-run timer.
Immediately after a value is written to these bits, the clock is updated. Therefore, be sure to stop the
output compare and input capture operation before writing a value to these bits.
Table 18.2-6 Count Clock Selection Bits
CLK1
CLK0
Count clock (φ)
φ=18 MHz
φ=9 MHz
0
0
φ/22
0.22 μs
0.44 μs
0
1
φ/24
0.89 μs
1.78 μs
1
0
φ/25
1.78 μs
3.56 μs
1
1
φ/26
3.56 μs
7.11 μs
φ: Resource clock (CLKP)
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.3 16-bit Free-run Timer Operation
18.3
MB91461
16-bit Free-run Timer Operation
The 16-bit free-run timer starts counting from counter value 0000H after a reset is
cleared. This counter value is used as the base time for 16-bit output compare and 16bit input capture.
■ 16-bit Free-run Timer Operation
The counter value is cleared in the following cases:
• An overflow occurs.
• A compare match with the compare clear register (compare register in the output compare) value (A
mode setting is required).
• "1" is written to the CLR bit of the TCCS register during operation.
• 0000H is written to the TCDT register while the timer is stopped.
• A reset occurs.
An interrupt can occur when an overflow occurs or when the counter is cleared because a compare match
with the compare clear register value occurs (A mode setting is required for a compare match interrupt).
Figure 18.3-1 Clearing of Counter Because of an Overflow
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Interrupt
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CHAPTER 18 16-BIT FREE-RUN TIMER
18.3 16-bit Free-run Timer Operation
MB91461
Figure 18.3-2 Clearing of Counter Because of a Compare Match with the Compare Clear Register Value
Counter value
FFFFH
Match
BFFFH
Match
7FFFH
3FFFH
0000H
Time
Reset
Compare register
BFFFH
Interrupt
■ Clear Timing of the 16-bit Free-run Timer
The counter can be cleared by a reset, software, or a match with the compare clear register.
A reset and software clear the counter as soon as the clear occurs. A match with the compare clear register,
however, clears the counter in synchronization with the count timing.
Figure 18.3-3 Clear Timing of the 16-bit Free-run Timer
Compare clear
register value
N
Counter clear
Counter value
N
0000H
■ Count Timing of the 16-bit Free-run Timer
The 16-bit free-run timer counts up according to an input clock (internal or external clock). When an
external clock is selected, the clock’s falling edge ↓ is synchronized with the system clock, then the falling
edge of the internal count clock is counted.
Figure 18.3-4 Count Timing of the 16-bit Free-run Timer
External clock input
Internal count clock
Counter value
CM71-10159-2E
N
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N+1
539
CHAPTER 18 16-BIT FREE-RUN TIMER
18.4 Notes on Using the 16-bit Free-run Timer
18.4
MB91461
Notes on Using the 16-bit Free-run Timer
This section contains notes on using the 16-bit free-run timer.
■ Notes on Using the 16-bit Free-run Timer
• If the interrupt request flag is set and cleared at the same time, setting of the flag takes precedence and
the clear operation is ineffective.
• If "1" is written to bit2 (counter initialization bit: CLR) of the control status register, the bit retains the
value until the internal counter is cleared, then clears itself when the internal counter is cleared. If "1" is
written to counter initialization bit at the same time that the bit is cleared, the write takes precedence,
and the counter initialization bit retains "1" until the next clear timing.
• The counter is cleared only during operation of the internal counter (The internal prescaler is also in
operation). To clear the counter while it is stopped, write 0000H to the timer count data register.
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CHAPTER 19
INPUT CAPTURE
This chapter describes the functions and operation of
the input capture.
19.1 Overview of the Input Capture
19.2 Input Capture Registers
19.3 Input Capture Operation
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CHAPTER 19 INPUT CAPTURE
19.1 Overview of the Input Capture
19.1
MB91461
Overview of the Input Capture
The input capture detects rising edges, falling edges, or both edges on the signal input
from an external pin and saves the value of the 16-bit free-run timer at that time to a
register. The unit can also generate an interrupt when an edge is detected.
The input capture consists of an input capture data register and control register.
■ Overview of the Input Capture
Each input capture has its own external input pin.
• The active edge on the external input can be selected from the following three options :
- Rising edge
- Falling edge
- Both edges
• The input capture can generate an interrupt when an active edge on the external input is detected.
• The free-run timer and the input capture operate cooperatively by the following combinations.
- Free-run timer 0, input capture 0, 1
- Free-run timer 1, input capture 2, 3
■ Block Diagram of the Input Capture
Figure 19.1-1 Block Diagram
Count value from 16-bit
free-run timer (T15 to T00)
R-bus
Capture data register ch.0
IN0
Input pin
Edge detection
EG11
Count value from 16-bit
free-run timer (T15 to T00)
EG10
EG01
IN1
Input pin
Edge detection
Capture data register ch.1
ICP1
ICP0
ICE1
EG00
ICE0
Interrupt
Interrupt
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CHAPTER 19 INPUT CAPTURE
19.2 Input Capture Registers
MB91461
19.2
Input Capture Registers
The input capture has the following two registers:
• Input capture register (IPCP0 to IPCP3)
• Input capture control register (ICS01,ICS23)
This section describes these registers in detail.
■ Input Capture Registers
Figure 19.2-1 Bit Configuration of Input Capture Registers
IPCP (Upper)
bit15
14
13
12
11
10
9
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Address:
IPCP0: 000184H
IPCP1: 000186H
IPCP2: 000188H
IPCP3: 00018AH
IPCP (Lower)
Address:
IPCP0: 000185H
IPCP1: 000187H
IPCP2: 000189H
IPCP3: 00018BH
ICS
Address:
ICS01: 000181H
ICS23: 000183H
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CHAPTER 19 INPUT CAPTURE
19.2 Input Capture Registers
19.2.1
MB91461
Input Capture Register (IPCP0 to IPCP3)
The input capture register (IPCP0 to IPCP3) retains the 16-bit free-run timer value when
the device detects the valid edge of a waveform input from the corresponding external
pin.
■ Bit Configuration of the Input Capture Register (IPCP0 to IPCP3)
Figure 19.2-2 Bit Configuration of the Input Capture Register (IPCP0 to IPCP3)
IPCP (Upper)
Address:
IPCP0: 000184H
IPCP1: 000186H
IPCP2: 000188H
IPCP3: 00018AH
bit15
14
13
12
11
10
9
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
IPCP (Lower)
Address:
IPCP0: 000185H
IPCP1: 000187H
IPCP2: 000189H
IPCP3: 00018BH
The input capture register retains the 16-bit free-run timer value when the device detects the valid edge of a
waveform input from the corresponding external pin. The value of this register is undefined after a reset.
Access this register using 16-bit or 32-bit data. Writing to this register is not permitted.
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CHAPTER 19 INPUT CAPTURE
19.2 Input Capture Registers
MB91461
19.2.2
Input Capture Control Register (ICS01,ICS23)
The input capture control register (ICS01,ICS23) is used to control an input capture
interrupt or an edge detection.
■ Bit Configuration of the Input Capture Control Register (ICS01,ICS23)
Figure 19.2-3 Bit Configuration of the Input Capture Control Register (ICS01,ICS23)
ICS
bit7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Address:
ICS01: 000181H
ICS23: 000183H
[bit7, bit6] ICP1, ICP0: Input capture interrupt flags
These bits are input capture interrupt flags. When a valid edge from the external input pin is detected,
these bits are set to "1". If the interrupt enable bits (ICE3 to ICE0) are also set, the detection of a valid
edge causes an interrupt to be generated. Write "0" to these bits to clear them. Writing "1" is
meaningless. A read-modify-write (RMW) instruction always reads "1" from these bits.
Table 19.2-1 Input Capture Interrupt Flags
ICP0/ICP1
Interrupt flag
0
Valid edge not detected [Initial value]
1
Valid edge detected
[bit5, bit4] ICE1, ICE0: Input capture interrupt enable bits
These bits are the input capture interrupt enable bits. If they are set to "1" and the input capture interrupt
flags (ICP1, ICP0) are also set to "1", an input capture interrupt occurs.
Table 19.2-2 Input Capture Interrupt Enable Bits
ICE0/ICE1
CM71-10159-2E
Input capture interrupt enable
0
Interrupt disabled [Initial value]
1
Interrupt enabled
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CHAPTER 19 INPUT CAPTURE
19.2 Input Capture Registers
MB91461
[bit3 to bit0] EG11, EG10, EG01, EG00 (EG31, EG30, EG21, EG20): Edge selection bits
These bits are used to select a valid edge polarity for external input. They also enable an input capture
operation.
Table 19.2-3 Edge Selection Bits
EGn1
EGn0
Edge polarity detection
0
0
Edge not detected (stopped) [Initial value]
0
1
Rising edge detected ↑
1
0
Falling edge detected ↓
1
1
Both edges (rising and falling edges) detected ↑ & ↓
The number n in EGn1/EGn0 corresponds to the input capture channel number.
n = 0 to 3
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CHAPTER 19 INPUT CAPTURE
19.3 Input Capture Operation
MB91461
19.3
Input Capture Operation
When the 16-bit input capture detects the specified valid edge, it can read the value of
the 16-bit free-run timer into the capture register and generate an interrupt.
■ 16-bit Input Capture Operation
Figure 19.3-1 Example of Timing for Input Capture Reading
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
IN0
IN1
IN2
Data register 0
Undefined
3FFFH
Data register 2
BFFFH
Undefined
Data register 1
Undefined
BFFFH
7FFFH
Capture 0 interrupt
Capture 1 interrupt
Capture 2 interrupt
Capture 0 = Rising edge
Capture 1 = Falling edge
Capture 2 = Both edges
CM71-10159-2E
Interrupt generated again due to a valid edge
Interrupt cleared by software
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CHAPTER 19 INPUT CAPTURE
19.3 Input Capture Operation
MB91461
■ 16-bit Input Capture Input Timing
Figure 19.3-2 Example of 16-bit Input Capture Input Timing
φ
Counter value
N
N+1
Input capture input
Valid edge
Capture signal
Capture register value
N+1
Interrupt
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CHAPTER 20
OUTPUT COMPARE UNIT
This chapter describes the functions and operation of
the output compare unit.
20.1 Overview of the Output Compare Unit
20.2 Output Compare Unit Registers
20.3 Output Compare Unit Operation
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CHAPTER 20 OUTPUT COMPARE UNIT
20.1 Overview of the Output Compare Unit
20.1
MB91461
Overview of the Output Compare Unit
The output compare module consists of a compare register, compare output latch, and
control register.
■ Features of the Output Compare Unit
• The compare registers operate independently.
Each compare register has a corresponding output pin and interrupt flag.
• The output pin can be controlled using two compare registers as a pair.
The output pin is reversed using two compare registers.
• The initial value of each output pin default can be set.
• Interrupts can be generated at a compare match.
• The free-run timer and the output compare unit operate cooperatively by the following combinations.
- Free-run timer 2, output compare 0, 1
- Free-run timer 3, output compare 2, 3
■ Block Diagram of the Output Compare Unit
Figure 20.1-1 Block Diagram of Output Compare Unit
OTD1
OTD0
Compare register
Compare circuit
R-bus
Compare register
OTE0
Output
Compare
output latch
OTE1
Output
CMOD
Compare circuit
CST1
Compare
output latch
CST0
ICP1
ICP0
ICE1
ICE0
16-bit free-run timer
Interrupt output
Interrupt output
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CHAPTER 20 OUTPUT COMPARE UNIT
20.2 Output Compare Unit Registers
MB91461
20.2
Output Compare Unit Registers
The output compare unit has the compare register and control register.
■ Output Compare Unit Registers
Figure 20.2-1 Bit Configuration of Output Compare Unit Registers
OCCP (Upper)
bit15
14
13
12
11
10
9
8
C15
C14
C13
C12
C11
C10
C09
C08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit15
14
13
12
11
10
9
8
CMOD Reserved Reserved
OTD1
OTD0
Address:
OCCP0: 000190H
OCCP1: 000192H
OCCP2: 000194H
OCCP3: 000196H
OCCP (Lower)
Address:
OCCP0: 000191H
OCCP1: 000193H
OCCP2: 000195H
OCCP3: 000197H
OCS (Upper)
Address:
OCS01: 00018CH
OCS23: 00018EH
Reserved Reserved Reserved
Read/Write
−
−
−
R/W
−
−
R/W
R/W
Initial value
1
1
1
0
1
1
0
0
bit7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
CST1
CST0
Read/Write
R/W
R/W
R/W
R/W
−
−
R/W
R/W
Initial value
0
0
0
0
1
1
0
0
OCS (Lower)
Address:
OCS01: 00018DH
OCS23: 00018FH
CM71-10159-2E
Reserved Reserved
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CHAPTER 20 OUTPUT COMPARE UNIT
20.2 Output Compare Unit Registers
20.2.1
MB91461
Compare Register (OCCP0 to OCCP3)
This section describes the compare register (OCCP0 to OCCP3) in detail.
■ Bit Configuration of the Compare Register (OCCP0 to OCCP3)
Figure 20.2-2 Bit Configuration of the Compare Register (OCCP0 to OCCP3)
OCCP (Upper)
bit15
14
13
12
11
10
9
8
C15
C14
C13
C12
C11
C10
C09
C08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
Address:
OCCP0: 000190H
OCCP1: 000192H
OCCP2: 000194H
OCCP3: 000196H
OCCP (Lower)
Address:
OCCP0: 000191H
OCCP1: 000193H
OCCP2: 000195H
OCCP3: 000197H
■ Functions of the Compare Register (OCCP0 to OCCP3)
The compare register is the 16-bit compare register that is compared with the 16-bit free-run timer. Since
the initial value of the register is undefined, set the compare value before enabling startup.
Access the compare register using 16-bit or 32-bit data. When the register value and the 16-bit free-run
timer value match, a compare signal is generated and the output compare interrupt flag is set. When the
corresponding bit of the port function register (PFR) is set and output is enabled, the output level
corresponding to the compare register is reversed.
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CHAPTER 20 OUTPUT COMPARE UNIT
MB91461
20.2.2
Control Register (OCS01,OCS23)
20.2 Output Compare Unit Registers
This section describes the control register (OCS01,OCS23) in detail.
■ Bit Configuration of the Control Register (OCS01,OCS23)
Figure 20.2-3 Bit Configuration of the Control Register (OCS01,OCS23)
OCS (Upper)
Address:
OCS01: 00018CH
OCS23: 00018EH
bit15
14
13
Reserved Reserved Reserved
12
11
10
9
8
CMOD Reserved Reserved
OTD1
OTD0
Read/Write
−
−
−
R/W
−
−
R/W
R/W
Initial value
1
1
1
0
1
1
0
0
bit7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
CST1
CST0
Read/Write
R/W
R/W
R/W
R/W
−
−
R/W
R/W
Initial value
0
0
0
0
1
1
0
0
OCS (Lower)
Address:
OCS01: 00018DH
OCS23: 00018FH
Reserved Reserved
[bit15 to bit13] Reserved: Reserved bits
These bits are reserved bits. In a read operation, 111B is always read from these bits.
[bit12] CMOD: Mode bit
Switches the mode for reversing the pin output level for a compare match if pin output is enabled.
• When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is
reversed.
- The level is reversed when compare register 0 (2) provides a match.
- The level is reversed when compare register 1 (3) provides a match.
• When CMOD=1,
- The level is reversed when compare register 0 (2) provides a match.
- The level is reversed when compare registers 0 (2) or 1 (3) provides a match.
[bit11, bit10] Reserved: Reserved bits
These bits are reserved bits. In a read operation, 11B is always read from these bits.
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CHAPTER 20 OUTPUT COMPARE UNIT
20.2 Output Compare Unit Registers
MB91461
[bit9, bit8] OTD1, OTD0: Compare pin output level change bits
Use these bits to change the pin output level when the output compare register pin output is enabled.
Write to these bits after stopping the compare operation. In a read operation, the output compare pin
output value is read from these bits.
Table 20.2-1 Compare Pin Output Level Change Bits
OTD1, OTD0
Compare pin output level
0
The compare pin output changes to "0". [Initial value]
1
The compare pin output changes to "1".
[bit7, bit6] ICP1, ICP0: Interrupt flags
These bits are interrupt flags for an output compare. They are set to "1" if the compare registers and the
16-bit free-run timer value match. When the interrupt request bits (ICE1, ICE0) are enabled and these
bits are set to "1", an output compare interrupt occurs. Write "0" to these bits to clear them. Writing "1"
is meaningless. A read-modify-write (RMW) instruction always reads "1" from these bits.
Table 20.2-2 Interrupt Flags
ICP1, ICP0
Interrupt flag
0
No output compare match [Initial value]
1
Output compare match
If an external clock is specified for the free-run timer, a compare match or interrupt occurs at the next
clock. For a compare match to be output and an interrupt to occur, at least one clock must be input to
the external clock of the free-run timer after the compare match.
[bit5, bit4] ICE1, ICE0: Interrupt enable bits
These bits enable an output compare interrupt. When they are set to "1" and the interrupt flags (ICP0
and ICP1) are set to "1", an output compare interrupt occurs.
Table 20.2-3 Interrupt Enable Bits
ICE1, ICE0
Interrupt enable
0
Output compare interrupt disabled [Initial value]
1
Output compare interrupt enabled
[bit3, bit2] Reserved: Reserved bits
These are the reserved bits. In a read operation, 11B is always read from these bits.
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CHAPTER 20 OUTPUT COMPARE UNIT
20.2 Output Compare Unit Registers
MB91461
[bit1, bit0] CST1, CST0: Match operation enable bits
These bits enable a match operation with the 16-bit free-run timer. Before enabling the compare
operation, be sure to set the compare register value and the output control register value.
Table 20.2-4 Match Operation Enable Bits
CST1, CST0
Match operation enable
0
Compare operation disabled [Initial value]
1
Compare operation enabled
Since output compare is synchronized with the 16-bit free-run timer, stopping the 16-bit free-run timer
also stops the compare operation.
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CHAPTER 20 OUTPUT COMPARE UNIT
20.3 Output Compare Unit Operation
20.3
MB91461
Output Compare Unit Operation
The 16-bit output compare operation compares the specified compare register value
and the 16-bit free-run timer value. If a match occurs, the interrupt flag is set and the
output level is reversed.
■ 16-bit Output Compare Operation
The compare operation can be executed for each channel independently (when CMOD=0).
Figure 20.3-1 Example of Output Waveform When Compare Registers 0 and 1 are Used
(The Initial Value of the Output is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0 value
BFFFH
Compare register 1 value
7FFFH
OP0 Output
OP1 Output
Compare 0 interrupt
Compare 1 interrupt
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CHAPTER 20 OUTPUT COMPARE UNIT
20.3 Output Compare Unit Operation
MB91461
The output level can be changed if two compare registers are used (when CMOD=1).
Figure 20.3-2 Example of Output Waveform When the Compare Registers 0 and 1 are Used
(The Initial Value of the Output is "0")
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0 value
BFFFH
Compare register 1 value
7FFFH
OP0 Output
OP1 Output
Compare 0 interrupt
Compare 1 interrupt
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CHAPTER 20 OUTPUT COMPARE UNIT
20.3 Output Compare Unit Operation
MB91461
■ 16-bit Output Compare Operation Timing
The output level can be changed if two compare registers are used (when CMOD=1).
When the values of the free-run timer and the specified compare register match, the output compare unit
generates a compare match signal to reverse the output and generate an interrupt. Reversal of output due to
a compare match occurs in synchronization with the count timing of the counter.
● Compare register rewrite timing
When rewritten, the compare register is not compared with the counter value.
Figure 20.3-3 Compare Register Rewrite Timing
Counter value
N
N+1
N+2
N+3
Match signal not generated
Compare clear register 0 value
M
N+1
Compare register 0 write
Compare clear register 1 value
L
N+3
Compare register 1 write
Compare 0 stopped
Compare 1 stopped
● Compare match, interrupt timing
Figure 20.3-4 Compare Match, Interrupt Timing
Count clock
Counter value
Compare register value
N
N+1
N+2
N+3
N
Compare match
Pin output
Interrupt
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CHAPTER 20 OUTPUT COMPARE UNIT
20.3 Output Compare Unit Operation
MB91461
● Pin output timing
Figure 20.3-5 Pin Output Timing
Counter value
Compare register value
N
N+1
N+1
N+1
N
Compare match
Pin output
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CHAPTER 20 OUTPUT COMPARE UNIT
20.3 Output Compare Unit Operation
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MB91461
CM71-10159-2E
CHAPTER 21
PPG (PROGRAMMABLE
PULSE GENERATOR)
This chapter describes the registers, function, and
operation of the PPG.
21.1 Overview of PPG
21.2 PPG Registers
21.3 PPG Operation
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.1 Overview of PPG
21.1
MB91461
Overview of PPG
The PPG can output high-precision PWM waves at an arbitrary cycle and duty ratio.
Each of the channels consists of a 16-bit down-counter, cycle setting 16-bit register with
buffer, duty setting 16-bit register with buffer, and pin controller. The control status
register for each channel is used to indicate the operation control mode. General
control registers 10 and 20 are common registers shared by each channel for its
control.
■ Features
The count clock for the 16-bit down-counter can be selected from among the following four types:
• Clocks: FCLKP, FCLKP/4, FCLKP/16, FCLKP/64 (FCLKP: Clock for peripherals)
• The counter can be set to FFFFH by a reset or underflow.
The 16-bit down-counter causes an underflow when it changes from 0000H to FFFFH.
• Each channel has output pin.
• Registers
Cycle setting register: Data reload register with buffer
Duty setting register: Compare register with buffer
• Output pin control
A duty match causes an output 1.
An underflow causes an output 0.
The output value fix mode enables output of all "L" or all "H".
The polarity reverse can also be specified.
• An interrupt factor can be generated using any combination of the following:
Activation trigger of PPG (software trigger)
Occurrence of counter borrow (cycle match)
Occurrence of duty match
Occurrence of counter borrow (cycle match) or occurrence of duty match
• You can set simultaneous activation of two or more channels using software or reload timer. You can
also set restarting the PPG during operation.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.1 Overview of PPG
MB91461
■ Block Diagram of PPG
● Configuration diagram of the entire PPG0 to PPG7 and the reload timer connection
Figure 21.1-1 Configuration Diagram of the Entire PPG
PPG0 to PPG3
External trigger 0
External trigger 1
Output pins
TRG input
PPG ch.0
PPG0
TRG input
PPG ch.1
PPG1
TRG input
PPG ch.2
PPG2
TRG input
PPG ch.3
PPG3
External trigger 2
External trigger 3
Selector
Reload timer 0
Reload timer 1
General
control
register 20
Select signal
General control register 10
(Indicates trigger input)
PPG4 to PPG7
Selector
Reload timer 2
Reload timer 3
General
control
register 21
Select signal
Output pins
TRG input
PPG ch.4
PPG4
TRG input
PPG ch.5
PPG5
TRG input
PPG ch.6
PPG6
TRG input
PPG ch.7
PPG7
General control register 11
(Indicates trigger input)
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.1 Overview of PPG
MB91461
● Configuration diagram of PPG (1 channel)
Figure 21.1-2 Configuration Diagram of PPG (1 Channel)
Cycle setting register
Duty setting register
PCSR
PDUT
Prescaler
CMP
FCLKP/1
Clock
Load
FCLKP/4
16-bit down-counter
FCLKP/16
FCLKP/64
Start
Underflow
PPG mask
Peripheral
clock (FCLKP)
PPG
output
Reversal bit
Enable
Internal trigger (EN0 to EN3)
GCN20
Reload Timer
ch.0, ch.1 input
Edge
detection
Interrupt
selection
IRQ
(Interrupt request signal)
Software trigger
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
21.2
PPG Registers
This section lists the PPG registers and details their functions.
■ PPG Registers
Figure 21.2-1 PPG Registers
GCN10 (Upper)
bit15
Address: 000100H
14
13
12
11
TSEL33 to TSEL30
10
9
8
TSEL23 to TSEL20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
0
bit7
6
5
4
3
2
1
0
GCN10 (Lower)
Address: 000101H
TSEL13 to TSEL10
TSEL03 to TSEL00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
bit15
14
13
12
11
10
9
8
GCN11 (Upper)
Address: 000104H
TSEL73 to TSEL70
TSEL63 to TSEL60
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
0
bit7
6
5
4
3
2
1
0
GCN11 (Lower)
Address: 000105H
TSEL53 to TSEL50
TSEL43 to TSEL40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
bit7
6
5
4
3
2
1
0
EN3
EN2
EN1
EN0
GCN2
Address: Reserved Reserved Reserved Reserved
GCN20: 000103H
GCN21: 000107H
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
(Continued)
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
(Continued)
PTMR (Upper)
Address: 000110H, 000118H bit15
000120H, 000128H
000130H, 000138H D15
000140H, 000148H
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
Read/Write
R
R
R
R
R
R
R
R
Initial value
1
1
1
1
1
1
1
1
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
R
R
R
R
R
R
R
R
Initial value
1
1
1
1
1
1
1
1
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
PTMR (Lower)
Address: 000111H, 000119H
000121H, 000129H
000131H, 000139H
000141H, 000149H
PCSR (Upper)
Address: 000112H, 00011AH bit15
000122H, 00012AH
D15
000132H, 00013AH
000142H, 00014AH
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
PCSR (Lower)
Address: 000113H, 00011BH
000123H, 00012BH
000133H, 00013BH
000143H, 00014BH
PDUT (Upper)
Address: 000114H, 00011CH bit15
000124H, 00012CH
D15
000134H, 00013CH
000144H, 00014CH
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
(Continued)
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
(Continued)
PDUT (Lower)
Address: 000115H, 00011DH
000125H, 00012DH
000135H, 00013DH
000145H, 00014DH
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
14
13
12
11
10
9
8
CKS1
CKS0
PCNH
Address: 000116H, 00011EH bit15
000126H, 00012EH
CNTE
000136H, 00013EH
000146H, 00014EH
STGR MDSE RTRG
PGMS Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
Initial value
0
0
0
0
0
0
0
−
6
5
4
3
2
1
0
EGS0
IREN
IRQF
IRS1
IRS0 Reserved OSEL
PCNL
Address: 000117H, 00011FH bit7
000127H, 00012FH
EGS1
000137H, 00013FH
000147H, 00014FH
CM71-10159-2E
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
−
R/W
Initial value
0
0
0
0
0
0
−
0
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
21.2.1
MB91461
Control Status Registers (PCNH, PCNL)
The control status registers (PCNH and PCNL) are a register per each channel for
controlling the operation mode setting, the start enable, the clock selection, the output
mask, the trigger input edge selection, and the interrupt enable. Also the registers
indicate the interrupt status flag.
■ Structure of the Control Status Registers (PCNH, PCNL)
Figure 21.2-2 Configuration of the Control Status Registers
PCNH
Address: 000116H, 00011EH bit15
000126H, 00012EH
CNTE
000136H, 00013EH
000146H, 00014EH
14
13
12
STGR MDSE RTRG
11
10
CKS1
CKS0
9
8
PGMS Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
Initial value
0
0
0
0
0
0
0
−
6
5
4
3
2
1
0
EGS0
IREN
IRQF
IRS1
IRS0 Reserved OSEL
PCNL
Address: 000117H, 00011FH bit7
000127H, 00012FH
EGS1
000137H, 00013FH
000147H, 00014FH
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
−
R/W
Initial value
0
0
0
0
0
0
−
0
■ Functions of the PCNH/PCNL Bits
[bit15] CNTE: Counter operation enable
This bit enables or disables operation of the 16-bit down-counter.
Table 21.2-1 Counter Operation Enable
CNTE
Function
0
Disable the operation [Initial value]
1
Enable the operation
[bit14] STGR: Software trigger
Setting this bit to "1" causes a software trigger to activate PPG.
The bit returns a value of "0" whenever read.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit13] MDSE: Operation mode
This bit selects PWM operation for generating a continuous stream of pulses or one-shot operation for
generating a single pulse.
Table 21.2-2 Operation Mode
MDSE
Function
0
PWM operation [Initial value]
1
One-shot operation
[bit12] RTRG: Restart enable bit
This bit enables or disables restart using a trigger input.
Table 21.2-3 Restart Enable Bit
RTRG
Function
0
Disables restarting. [Initial value]
1
Enables restarting.
[bit11, bit10] CKS1, CKS0: Clock select
These bits select the count clock for the 16-bit down-counter.
Table 21.2-4 Selecting the Count Clock
CKS1
CKS0
Count clock
0
0
FCLKP/1 [Initial value]
0
1
FCLKP/4
1
0
FCLKP/16
1
1
FCLKP/64
FCLKP: Peripheral macro operation clock
[bit9] PGMS: PPG output mask
When set to "1", this bit sets the PPG output to "L" or "H" regardless of the mode, cycle, and duty
settings.
Table 21.2-5 PPG Output Mask
Polarity
PPG output
Normal polarity
"L" level output [Initial value]
Inverted polarity
"H" level output
Use OSEL bit (bit0 of the control status register) to specify the output polarity.
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21.2 PPG Registers
MB91461
[bit8] Unused bit
[bit7, bit6] EGS1, EGS0: Trigger input select
These bits select the effective edge for the trigger input selected by general control register 10
(GCN10).
Table 21.2-6 Trigger Input Select
EGS1
EGS0
Trigger input edge
0
0
Invalid [Initial value]
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
[bit5] IREN: Interrupt request enable
This bit enables or disables interrupt requests.
Table 21.2-7 Interrupt Request Enable
IREN
Function
0
Disable interrupt requests [Initial value]
1
Enable interrupt requests
[bit4] IRQF: Interrupt request flag
When the interrupt source selected by bit3 and bit2 (IRS1 and IRS0) is generated with bit5 (IREN)
enabling interrupt requests, this bit is set, generating an interrupt request to the CPU.
This bit is cleared by writing "0" to it. Writing "1" to this bit does not change the bit value.
When read by a read-modify-write (RMW) instruction, the bit returns "1" regardless of the bit value.
If this bit is selected as a DMAC trigger, DMA transfer request occurs. In this case, this bit is cleared by
DMAC at the transfer.
[bit3, bit2] IRS1, IRS0: Interrupt source select
These bits select the interrupt source.
Table 21.2-8 Selecting the Interrupt Source
IRS1
IRS0
Interrupt source
0
0
Generation of a software trigger or trigger input [Initial value]
0
1
Occurrence of counter borrow (cycle match)
1
0
Occurrence of duty match
1
1
Occurrence of counter borrow (cycle match) or occurrence of duty match
[bit1] Unused bit
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit0] OSEL: PPG output polarity select
This bit sets the PPG output polarity.
The bit is used in combination with bit9 (PGMS) to specify the following:
Table 21.2-9 PPG Output Polarity and Edge
PGMS
OSEL
PPG output
Polarity
After reset
0
0
Normal polarity [Initial value]
"L" output
0
1
Inverted polarity
Normal
polarity
1
0
Fixed at "L" output
"H" output
1
1
Fixed at "H" output
Inverted
polarity
CM71-10159-2E
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Duty match
Underflow
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
21.2.2
MB91461
PPG Cycle Setting Register (PCSR)
The PPG cycle setting register (PCSR) is a 16-bit reload register for setting the PPG cycle.
■ Configuration of the PPG Cycle Setting Register (PCSR)
Figure 21.2-3 Configuration of the PPG Cycle Setting Register
PCSR (Upper)
Address: 000112H, 00011AH bit15
000122H, 00012AH
D15
000132H, 00013AH
000142H, 00014AH
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
PCSR (Lower)
Address: 000113H, 00011BH
000123H, 00012BH
000133H, 00013BH
000143H, 00014BH
■ Functions of the PCSR
This register has a buffer. PCSR setting value is loaded from the buffer to counter when a counter borrow
occurs or a trigger input is detected.
An counter borrow is caused when the counter reaches "the PCSR set value + 1" count after starting
counting. The cycle is the value obtained by multiplying "the count clock cycle" by "PCSR set value + 1"
count.
Be sure to write to the PPG duty setting register (PDUT) after writing to the PPG cycle setting register.
To write to this register, access it using half word (16-bit) or word (32-bit) data.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
21.2.3
PPG Duty Setting Register (PDUT)
The PPG duty setting register (PDUT) is a 16-bit register for setting the duty of the
output wave.
■ Configuration of the PPG Duty Setting Register (PDUT)
Figure 21.2-4 Configuration of the PPG Duty Setting Register
PDUT (Upper)
Address: 000114H, 00011CH bit15
000124H, 00012CH
D15
000134H, 00013CH
000144H, 00014CH
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
PDUT (Lower)
Address: 000115H, 00011DH
000125H, 00012DH
000135H, 00013DH
000145H, 00014DH
■ Functions of the PDUT
The PPG duty setting register sets the duty of the PPG output waveform. When the value matches with the
16-bit counter of the PPG, the PPG output polarity is inverted.
The PPG output pulse width is the value obtained by multiplying "the count clock cycle" by "the PDUT set
value + 1" count.
The PDUT values should be set as "PCSR > PDUT". Setting the register values as "PCSR < PDUT" results
in undefined PPG output.
Setting the PPG cycle setting and PPG duty setting registers to the same value produces all "H" output with
normal polarity (OSEL=0) or all "L" output with inverted polarity (OSEL=1).
To write to this register, access it using half word (16-bit) or word (32-bit) data.
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21.2 PPG Registers
21.2.4
MB91461
PPG Timer Register (PTMR)
The PPG timer register (PTMR) is used to read the count value.
■ Configuration of the PPG Timer Register (PTMR)
Figure 21.2-5 Configuration of the PPG Timer Register
PTMR (Upper)
Address: 000110H, 000118H bit15
000120H, 000128H
D15
000130H, 000138H
000140H, 000148H
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
Read/Write
R
R
R
R
R
R
R
R
Initial value
1
1
1
1
1
1
1
1
bit7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Read/Write
R
R
R
R
R
R
R
R
Initial value
1
1
1
1
1
1
1
1
PTMR (Lower)
Address: 000111H, 000119H
000121H, 000129H
000131H, 000139H
000141H, 000149H
■ Functions of the PTMR
The PPG timer register (PTMR) is a register from which the count value is read.
To read a value from this register, access it using half word (16-bit) data. Using a byte data cannot read
correctly.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
21.2.5
General Control Register 10 (GCN10)
General control register 10 (GCN10) selects the PPG0 to PPG3 trigger input source.
■ Configuration of General Control Register 10 (GCN10)
Figure 21.2-6 Configuration of General Control Register 10 (GCN10)
GCN10 (Upper)
bit15
Address: 000100H
14
13
12
11
TSEL33 to TSEL30
10
9
8
TSEL23 to TSEL20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
0
bit7
6
5
4
3
2
1
0
GCN10 (Lower)
Address: 000101H
TSEL13 to TSEL10
TSEL03 to TSEL00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
■ Functions of the GCN10
[bit15 to bit12] TSEL33 to TSEL30: PPG ch.3 input select
Table 21.2-10 Selecting the PPG ch.3 Trigger Input
TSEL33 to TSEL30
PPG ch.3 trigger input
CM71-10159-2E
bit15
bit14
bit13
bit12
0
0
0
0
GCN20 EN0 bit
0
0
0
1
GCN20 EN1 bit
0
0
1
0
GCN20 EN2 bit
0
0
1
1
GCN20 EN3 bit [Initial value]
0
1
0
0
16-bit reload timer ch.0
0
1
0
1
16-bit reload timer ch.1
0
1
1
x
Setting prohibited
1
0
0
0
External trigger 0
1
0
0
1
External trigger 1
1
0
1
0
External trigger 2
1
0
1
1
External trigger 3
1
1
x
x
Setting prohibited
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit11 to bit8] TSEL23 to TSEL20: PPG ch.2 trigger input select
Table 21.2-11 Selecting the PPG ch.2 Trigger Input
TSEL23 to TSEL20
PPG ch.2 trigger input
bit11
bit10
bit9
bit8
0
0
0
0
GCN20 EN0 bit
0
0
0
1
GCN20 EN1 bit
0
0
1
0
GCN20 EN2 bit [Initial value]
0
0
1
1
GCN20 EN3 bit
0
1
0
0
16-bit reload timer ch.0
0
1
0
1
16-bit reload timer ch.1
0
1
1
x
Setting prohibited
1
0
0
0
External trigger 0
1
0
0
1
External trigger 1
1
0
1
0
External trigger 2
1
0
1
1
External trigger 3
1
1
x
x
Setting prohibited
[bit7 to bit4] TSEL13 to TSEL10: PPG ch.1 trigger input select
Table 21.2-12 Selecting the PPG ch.1 Trigger Input
TSEL13 to TSEL10
PPG ch.1 trigger input
576
bit7
bit6
bit5
bit4
0
0
0
0
GCN20 EN0 bit
0
0
0
1
GCN20 EN1 bit [Initial value]
0
0
1
0
GCN20 EN2 bit
0
0
1
1
GCN20 EN3 bit
0
1
0
0
16-bit reload timer ch.0
0
1
0
1
16-bit reload timer ch.1
0
1
1
x
Setting prohibited
1
0
0
0
External trigger 0
1
0
0
1
External trigger 1
1
0
1
0
External trigger 2
1
0
1
1
External trigger 3
1
1
x
x
Setting prohibited
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit3 to bit0] TSEL03 to TSEL00: PPG ch.0 trigger input select
Table 21.2-13 Selecting the PPG ch.0 Trigger Input
TSEL03 to TSEL00
PPG ch.0 trigger input
CM71-10159-2E
bit3
bit2
bit1
bit0
0
0
0
0
GCN20 EN0 bit [Initial value]
0
0
0
1
GCN20 EN1 bit
0
0
1
0
GCN20 EN2 bit
0
0
1
1
GCN20 EN3 bit
0
1
0
0
16-bit reload timer ch.0
0
1
0
1
16-bit reload timer ch.1
0
1
1
x
Setting prohibited
1
0
0
0
External trigger 0
1
0
0
1
External trigger 1
1
0
1
0
External trigger 2
1
0
1
1
External trigger 3
1
1
x
x
Setting prohibited
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
21.2.6
MB91461
General Control Register 11 (GCN11)
General control register 11 (GCN11) selects the PPG4 to PPG7 trigger input source.
■ Configuration of the General Control Register 11 (GCN11)
Figure 21.2-7 Configuration of the General Control Register 11 (GCN11)
GCN11 (Upper)
bit15
Address: 000104H
14
13
12
11
TSEL73 to TSEL70
10
9
8
TSEL63 to TSEL60
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
0
1
0
bit7
6
5
4
3
2
1
0
GCN11 (Lower)
Address: 000105H
TSEL53 to TSEL50
TSEL43 to TSEL40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
■ Functions of the GCN11
[bit15 to bit12] TSEL73 to TSEL70: PPG ch.7 trigger input select
Table 21.2-14 Selecting the PPG ch.7 Trigger Input
TSEL73 to TSEL70
PPG ch.7 trigger input
578
bit15
bit14
bit13
bit12
0
0
0
0
GCN21 EN0 bit
0
0
0
1
GCN21 EN1 bit
0
0
1
0
GCN21 EN2 bit
0
0
1
1
GCN21 EN3 bit [Initial value]
0
1
0
0
16-bit reload timer ch.2
0
1
0
1
16-bit reload timer ch.3
0
1
1
x
Setting prohibited
1
x
x
x
Setting prohibited
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit11 to bit8] TSEL63 to TSEL60: PPG ch.6 trigger input select
Table 21.2-15 Selecting the PPG ch.6 Trigger Input
TSEL63 to TSEL60
PPG ch.6 trigger input
bit11
bit10
bit9
bit8
0
0
0
0
GCN21 EN0 bit
0
0
0
1
GCN21 EN1 bit
0
0
1
0
GCN21 EN2 bit [Initial value]
0
0
1
1
GCN21 EN3 bit
0
1
0
0
16-bit reload timer ch.2
0
1
0
1
16-bit reload timer ch.3
0
1
1
x
Setting prohibited
1
x
x
x
Setting prohibited
[bit7 to bit4] TSEL53 to TSEL50: PPG ch.5 trigger input select
Table 21.2-16 Selecting the PPG ch.5 Trigger Input
TSEL53 to TSEL50
PPG ch.5 trigger input
CM71-10159-2E
bit7
bit6
bit5
bit4
0
0
0
0
GCN21 EN0 bit
0
0
0
1
GCN21 EN1 bit [Initial value]
0
0
1
0
GCN21 EN2 bit
0
0
1
1
GCN21 EN3 bit
0
1
0
0
16-bit reload timer ch.2
0
1
0
1
16-bit reload timer ch.3
0
1
1
x
Setting prohibited
1
x
x
x
Setting prohibited
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
[bit3 to bit0] TSEL43 to TSEL40: PPG ch.4 trigger input select
Table 21.2-17 Selecting the PPG ch.4 Trigger Input
TSEL43 to TSEL40
PPG ch.4 trigger input
580
bit3
bit2
bit1
bit0
0
0
0
0
GCN21 EN0 bit [Initial value]
0
0
0
1
GCN21 EN1 bit
0
0
1
0
GCN21 EN2 bit
0
0
1
1
GCN21 EN3 bit
0
1
0
0
16-bit reload timer ch.2
0
1
0
1
16-bit reload timer ch.3
0
1
1
x
Setting prohibited
1
x
x
x
Setting prohibited
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.2 PPG Registers
MB91461
21.2.7
General Control Register 2 (GCN20,GCN21)
General control register 2 (GCN20,GCN21) is used to generate an activation trigger by
software. This register can activate 4 channels at a same time.
■ Configuration of the General Control Register 2 (GCN20,GCN21)
Figure 21.2-8 Configuration of the General Control Register 2 (GCN20,GCN21)
GCN20,GCN21
bit7
6
5
4
Address: Reserved Reserved Reserved Reserved
GCN20: 000103H
GCN21: 000107H
3
2
1
0
EN3
EN2
EN1
EN0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
■ Functions of the GCN20,GCN21
If the EN0 to EN3 bits in GCN20, GCN21 register are selected as the activation trigger source by general
control register 1 (GCN1), the written value of EN0 to EN3 is passed to the PPG trigger input as it is. The
trigger input edge is selected by bit7 and bit6 (EGS1 and EGS0) in the control status register (PCNL).
Multiple PPG timer channels can be activated at the same time by using this register.
Be sure to write "0" to bit7 to bit4 in this register.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
21.3
MB91461
PPG Operation
This section describes the operation of the PPG. There are two PPG output operation
modes: PWM operation and one-shot operation modes.
■ PPG Operation
The PWM operation mode outputs a continuous stream of pulses; the one-shot operation mode outputs a
single pulse.
The items covered in this section are shown below:
• PWM operation
• One-shot operation
• Interrupts
• All "L" and all "H" PPG outputs
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
21.3.1
PWM Operation
The PWM operation mode outputs a continuous stream of pulses.
■ PWM Operation
The PWM operation mode outputs a continuous stream of pulses from the time at which an activation
trigger is detected. The output pulse cycle can be controlled by changing the value in the cycle setting
register (PCSR). The duty can also be controlled by changing the value in the duty setting register (PDUT).
When setting the output pulse cycle and duty ratio, be sure to write data to the PDUT register after writing
data to the PCSR register.
■ PPG Output Timing
When the activation trigger is detected, the cycle setting value is loaded into the counter and the downcounter starts counting.
When the counter value and the duty setting value (PDUT) match, the PPG output polarity is inverted.
If the counter causes an underflow, the value set in the PCSR register (cycle) is loaded into the counter and
the PPG output polarity is inverted.
When the trigger restarting has been disabled, a trigger input causes no effect on PPG output (Refer to
Figure 21.3-1).
When the trigger restarting has been enabled, a trigger input causes PCSR value to be loaded into the
counter even during counting. Then the counting is continued (Refer to Figure 21.3-2).
[Equations for calculating the PPG output pulse cycle and duty ratio]
Pm = T(m+1) μs
Pn = T(n+1) μs
CM71-10159-2E
Pm: Output pulse cycle
Pn: Output pulse width
T: Count clock cycle
m: Value set in the cycle setting register (PCSR)
n: Value set in the duty setting register (PDUT)
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
● PWM operation timing example 1 (Trigger restarting disabled, PPG output: Normal polarity)
Figure 21.3-1 PWM Operation Timing Example 1
(Trigger Restarting Disabled, PPG Output: Normal Polarity)
Rising edge detected
Restarted by the trigger
Activation trigger
Count value
m
n
Time
0
PPG output
Pn
Pm
Pm: Output pulse cycle
m: PCSR value
Pn: Output pulse "H" width
n: PDUT value
● PWM operation timing example 2 (Trigger restarting enabled, PPG output: Normal polarity)
Figure 21.3-2 PWM Operation Timing Example 2
(Trigger Restarting Enabled, PPG Output: Normal Polarity)
Rising edge detected
Restarted by the trigger
Activation trigger
Count value
m
n
Time
0
PPG output
Pn
Pm
Pm: Output pulse cycle
m: PCSR value
584
Pn: Output pulse "H" width
n: PDUT value
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CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
21.3.2
One-Shot Operation
The one-shot operation mode outputs a single pulse.
■ One-Shot Operation
The one-shot operation mode outputs a single pulse upon detection of an activation trigger.
The output pulse cycle can be controlled by changing the value in the cycle setting register (PCSR).
The output pulse width can also be controlled by changing the value in the duty setting register (PDUT).
When setting the output pulse cycle and width (duty ratio), be sure to write data to the PDUT register after
writing data to the PCSR register.
One-shot operation mode also depends on whether restarting has been disabled or enabled. When restarting
is enabled, PCSR value is reloaded to the counter at the time of receiving a restarting trigger. Then the
counting is continued
● One-shot operation timing example when Trigger restarting is disabled, PPG output: Normal polarity)
Figure 21.3-3 One-Shot Operation Timing Example When Trigger Restarting is Disabled
Activation trigger
Rising edge detected
Trigger ignored
Counter value
m
n
Time
0
PPG output
Pn
Pm
Pm = T(m+1)
Pn = T(n+1)
CM71-10159-2E
Pm: Output pulse cycle
Pn: Output pulse "H" width
T: Count clock cycle
m: PCSR value
n: PDUT value
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
● One-shot operation timing example when trigger restarting is enabled (Normal polarity)
Figure 21.3-4 One-Shot Operation Timing Example When Trigger Restarting is Enabled
Activation trigger
Rising edge detected
Restarted by trigger
Counter value
m
n
Time
0
PPG output
Pn
Pm
Pm = T(m+1)
Pn = T(n+1)
586
Pm: Output pulse cycle
Pn: Output pulse "H" width
T: Count clock cycle
m: PCSR value
n: PDUT value
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CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
21.3.3
Interrupts
Interrupt resources generated in PPG are followings:
• Activation of the PPG timer (software trigger or external trigger)
• Occurrence of an underflow
• Occurrence of a duty match
• Occurrence of an underflow or duty match
■ Interrupt Operation
The interrupt request signal to the CPU is generated by setting bits in the control status register (PCNL) as
follows:
• Use bit5 as the interrupt enable bit (IREN) to enable interrupts.
• Use bit3 and bit2 as the interrupt source select bits (IRS1 and IRS0) to select the desired interrupt
source.
• Bit (IRQF) is the interrupt request flag and indicates the interrupt occurrence status.
Figure 21.3-5 shows an interrupt timing diagram.
Figure 21.3-5 Interrupt Source and Timing
Activation trigger
2.5T max*
Load
Clock
Count value
X
0003 H
0002 H
0001 H
0000 H
0003 H
PPG output
Interrupt
Effective edge
Duty match
Counter borrow
*: It takes up to 2.5T (T: count clock cycle) from applying the activation trigger
to loading the count value.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
21.3.4
MB91461
All "L" and All "H" PPG Outputs
This section provides examples of producing all "L" and all "H" PPG outputs.
■ All "L" or All "H" Output
Writing "1" to bit9, or the PPG output mask select bit (PGMS), in the control status register (PCNH) masks
the PPG output to the "L" level (normal polarity) or "H" level (inverted polarity) regardless of the mode,
cycle, and duty settings.
Figure 21.3-6 Example of Producing All "L" PPG Output
PPG output
Decrease
the duty
value.
Use an interrupt upon an borrow to write
"1" to the PGMS (mask bit).
Using the borrow interrupt to write "0" to
the PGMS can output the PPG waveform
without hazard output.
Figure 21.3-7 Example of Producing All "H" PPG Output
PPG output
Increase
the duty
value
588
Use an interrupt upon a compare match to
set the duty setting register to the same
value as the cycle setting register value.
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
21.3.5
Activation of Multiple Channels
Multiple channels can be activated concurrently by selecting the start trigger by using
the general control register 10 (GCN10). An example of activation using GCN20 is given
below.
■ Activating Multiple PPG Channels Using Software
[Setting procedure]
(1) Set the cycle setting register (PCSR) to the cycle setting value.
(2) Set the duty setting register (PDUT) to the duty ratio value.
Note: Be sure to write data to the PDUT register after writing data to the PCSR register.
(3) Set the GCN10 register to determine the trigger input source for each channel you want to activate.
ch.0: EN0
ch.1: EN1
ch.2: EN2
ch.3: EN3
(4) Set the control status registers (PCNL, PCNH) corresponding to the channels to be activated.
Table 21.3-1 Setting Example of Activate Channel
Bit
Function
No.
Abbreviation
Value
15
CNTE
1
Timer operation enabled
14
STGR
0
STGR is not activated because GCN20 is used.
13
MDSE
0
PWM operation
12
RTRG
0
Reactivation disabled
11
CKS1
0
10
CKS0
0
9
PGMS
0
Output not masked
8
−
0
Unused bit
7
EGS1
0
6
EGS0
1
5
IREN
1
Interrupt enabled
4
IRQF
0
Interrupt factor cleared
3
IRS1
0
2
IRS0
1
0
OSEL
0
Count clock: FCLKP/1 (No division)
Activation on rising edge
Interrupt request occurs due to counter borrow
Normal polarity
(5) Write data to general control register (GCN20) to generate the activation trigger.
To activate ch.0 and ch.1 at the same time, write "1" to the EN0 and EN1 bits in the GCN20 register.
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CHAPTER 21 PPG (PROGRAMMABLE PULSE GENERATOR)
21.3 PPG Operation
MB91461
■ Multiple Activation Using a Trigger from the Reload Timer
In step (3) in the above setting procedure, select the 16-bit reload timer as the trigger input source.
In step (5), activate the 16-bit reload timer in place of general control register 2 (GCN20).
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CM71-10159-2E
CHAPTER 22
REAL TIME CLOCK
This chapter describes the register structure and
functions, and the operation of RTC module for the real
time clock.
22.1 Register Configuration of Real Time Clock
22.2 Block Diagram of Real Time Clock
22.3 Register Details of Real Time Clock
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CHAPTER 22 REAL TIME CLOCK
22.1 Register Configuration of Real Time Clock
22.1
MB91461
Register Configuration of Real Time Clock
This section shows the register configuration of the real time clock.
■ Real Time Clock Registers
Figure 22.1-1 Bit Configuration of Real Time Clock Registers
WTCRH
bit15
Address: 0004A2H INTE3
14
13
12
11
10
9
8
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
TST1
TST0
−
−
ST
WTCRL
Address: 0004A3H TST2
RUN Reserved
Read/Write
R/W
R/W
R/W
−
R
−
−
R/W
Initial value
0
0
0
−
0
0
−
0
bit23
22
21
20
19
18
17
16
Address: 0004A5H
−
−
−
D20
D19
D18
D17
D16
Read/Write
−
−
−
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
X
X
X
X
X
bit15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit31
30
29
28
27
26
25
24
−
−
−
H4
H3
H2
H1
H0
Read/Write
−
−
−
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
X
X
X
X
X
WTBR (Upper)
WTBR (Middle)
Address: 0004A6H
WTBR (Lower)
Address: 0004A7H
WTHR
Address: 0004A8H
(Continued)
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CM71-10159-2E
CHAPTER 22 REAL TIME CLOCK
22.1 Register Configuration of Real Time Clock
MB91461
(Continued)
WTMR
bit23
22
21
20
19
18
17
16
Address: 0004A9H
−
−
M5
M4
M3
M2
M1
M0
Read/Write
−
−
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
X
X
X
X
X
X
bit15
14
13
12
11
10
9
8
−
−
S5
S4
S3
S2
S1
S0
Read/Write
−
−
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
X
X
X
X
X
X
WTSR
Address: 0004AAH
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CHAPTER 22 REAL TIME CLOCK
22.2 Block Diagram of Real Time Clock
22.2
MB91461
Block Diagram of Real Time Clock
This section shows the block diagram of the real time clock.
■ Block Diagram of Real Time Clock
Figure 22.2-1 Block Diagram of Real Time Clock
Inside RTC
Outside RTC
8 clock
divider
Oscillation clock
UPDT
2 clock
divider
21-bit prescaler
Sub-second
register
ST
Second counter Minute counter
Hour counter
2 clock
divider
6 bits
Sub-second
counter
overflow
INTE0 INT0
6 bits
5 bits
Second/minute/hour register
INTE1 INT1
INTE2 INT2
INTE3 INT3
IRQ
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CM71-10159-2E
CHAPTER 22 REAL TIME CLOCK
22.3
MB91461
22.3
Register Details of Real Time Clock
Register Details of Real Time Clock
This section describes the detailed register configuration of the real time clock.
■ Timer Control Register (WTCRH, WTCRL)
Figure 22.3-1 Bit Configuration of the Timer Control Register (WTCRH, WTCRL)
WTCRH
bit15
Address: 0004A2H INTE3
14
13
12
11
10
9
8
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
TST1
TST0
−
−
ST
WTCRL
Address: 0004A3H TST2
RUN Reserved
Read/Write
R/W
R/W
R/W
−
R
−
−
R/W
Initial value
0
0
0
−
0
0
−
0
−: Unused bit
[bit15 to bit8] INT3 to INT0, INTE3 to INTE0: Interrupt flags and Interrupt enable bits
INT0 to INT3 are the interrupt flags. They are set when the sub-second counter, second counter, minute
counter, and hour counter overflow respectively. If the INT bit is set while the corresponding INTE bit
is "1", the interrupt signal is generated. These flags are intended to generate the interrupt signal every
sub-second/second/minute/hour/day. Writing "0" to the INT bits clears the flags and writing "1" does
not have any effect. Any read-modify-write (RMW) instruction performed on the INT bit results
reading "1".
Table 22.3-1 Interrupt Flags and Interrupt Enable Bits
Interrupt
Factor
Interrupt enable bit
Interrupt flag
Second interrupt
Sub-second counter overflow
INTE0
INT0
Minute interrupt
Second counter overflow
INTE1
INT1
Hour interrupt
Minute counter overflow
INTE2
INT2
Day interrupt
Hour counter overflow
INTE3
INT3
[bit7 to bit5] TST2 to TST0: Test bits
These bits are prepared for the device test.
In any user applications, they should be set to 000B.
[bit4] Unused bit
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22.3 Register Details of Real Time Clock
MB91461
[bit3] RUN: Flag
This bit can be read only and if "1" is read it indicates that the RTC module is actively operating.
[bit2] Reserved bit
This bit is a reserved bit. Write always "0".
[bit1] Unused bit
[bit0] ST: Start bit
When the ST bit is set to "1", the watch timer loads second/minute/hour values from the registers and
starts its operation. When it is reset to "0", all the counters and the prescalers are reset to "0" and halts.
This bit can also be used for updating the counter values. Set ST bit to "0", wait for RUN to go to "0",
update the counter values and set ST bit to "1".
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CM71-10159-2E
CHAPTER 22 REAL TIME CLOCK
22.3 Register Details of Real Time Clock
MB91461
■ Sub-second Registers
Figure 22.3-2 Bit Configuration of Sub-second Registers
WTBR (Upper)
bit23
22
21
20
19
18
17
16
Address: 0004A5H
−
−
−
D20
D19
D18
D17
D16
Read/Write
−
−
−
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
X
X
X
X
X
bit7
6
5
4
3
2
1
0
Address: 0004A6H
D15
D14
D13
D12
D11
D10
D9
D8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
bit15
14
13
12
11
10
9
8
Address: 0004A7H
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
WTBR (Middle)
WTBR (Lower)
−: Unused bit
[bit23 to bit21] Unused bits
[bit20 to bit0] D20 to D0
The sub-second register stores the reload value for the 21-bit prescaler. This value is reloaded after the
reload counter reaches "0". Note that when modifying all three bytes, make sure the reload operation
will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the
incorrect value of the combination of new data and old data bytes. It is generally recommended that the
sub-second registers are updated while the ST bit is "0". If the sub-second registers are set to "0", the
21-bit prescaler does not operate at all.
The clock supplied to RTC has the frequency which equals the 8 clock divider of the oscillation. And
the 2 divider of the RTC clock (= 16 divider) is the counter clock of the 21-bit prescaler.
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CHAPTER 22 REAL TIME CLOCK
22.3 Register Details of Real Time Clock
MB91461
WTBR resister set value for generating 1 second is as follows.
Table 22.3-2 WTBR Resister Setting Value
598
Oscillation clock
(MHz)
Oscillation clock
cycle (ns)
21-bit prescaler
clock cycle (μs)
9.00
111.11
1.78
281249
044AA1
10.00
100.00
1.60
312499
04C4B3
12.00
83.33
1.33
374999
05B8D7
14.00
71.43
1.14
437499
06ACFB
16.00
62.50
1.00
499999
07A11F
18.00
55.56
0.89
562499
089543
20.00
50.00
0.80
624999
098967
FUJITSU MICROELECTRONICS LIMITED
WTBR set value WTBR set value
(dec)
(hex)
CM71-10159-2E
CHAPTER 22 REAL TIME CLOCK
22.3 Register Details of Real Time Clock
MB91461
■ Hour/Minute/Second Register
Figure 22.3-3 Bit Configuration of Hour/Minute/Second Register
WTHR
bit31
30
29
28
27
26
25
24
Address: 0004A8H
−
−
−
H4
H3
H2
H1
H0
Read/Write
−
−
−
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
−
X
X
X
X
X
bit23
22
21
20
19
18
17
16
Address: 0004A9H
−
−
M5
M4
M3
M2
M1
M0
Read/Write
−
−
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
X
X
X
X
X
X
bit15
14
13
12
11
10
9
8
−
−
S5
S4
S3
S2
S1
S0
Read/Write
−
−
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
−
−
X
X
X
X
X
X
WTMR
WTSR
Address: 0004AAH
−: Unused bit
The hour/minute/second registers store the time information. It is a binary representation of the hour,
minute and second.
Reading these registers simply returns the counter values.
Since there are three byte-registers, make sure the obtained values from the registers are consistent. i.e.
Obtained value of "1 hour, 59 minute, 59 second" could be "0 hour, 59 minute, 59 second" or "1 hour, 0
minute, 0 second" or "2 hour, 0 minute, 0 second".
If reading is done at the moment of the counter overflow, it is possible to read wrong values. So reading
should be either triggered by an interrupt of the RTC or the following procedure should be followed:
1. Clear interrupt flags (INT) of the RTC module
2. Read registers
3. If flags are set after reading (time overflow occurred during reading), read again.
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CHAPTER 22 REAL TIME CLOCK
22.3 Register Details of Real Time Clock
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MB91461
CM71-10159-2E
CHAPTER 23
A/D CONVERTER
This chapter describes the overview, register
configuration and function, and operation of the A/D
converter.
23.1 Overview of A/D Converter
23.2 Block Diagram of A/D Converter
23.3 Registers of A/D Converter
23.4 Operation of A/D Converter
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CHAPTER 23 A/D CONVERTER
23.1 Overview of A/D Converter
23.1
MB91461
Overview of A/D Converter
This A/D converter converts analog input voltage to digital values.
This section describes the overview of the A/D converter.
● Feature of A/D converter
The A/D converter has the following features:
• Conversion time: 1.0 μs at minimum per channel
• The serial-parallel conversion method with a sample & hold circuit is used.
• 10-bit resolution (switching between 8 and 10 bits.)
• Analog input can be selected from 13 channels by software.
• Conversion mode
• Single conversion mode:
Scan conversion mode:
conversion of one selected channel.
continuous conversion of multiple channels, programmable for up to 13/
16 channels
Continuous conversion mode: Repeatedly convert the specified channels.
Stop conversion mode:
Convert one channel then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
• Interrupt request
At completion of A/D conversion, an interrupt request can be generated to the CPU.
• Selectable start factor
The start factor can be selected from software, external trigger (falling edge), and 16-bit reload timer
ch.7 (rising edge).
● Input impedance
The sampling circuit of the A/D converter is shown in the following equivalent circuit.
Figure 23.1-1 Input Impedance
Analog
Signal
source
Rext
ANx
Analog SW
Rext = Tsamp / (7 + Cin ) − Rin
602
Rin: max 1.9kΩ
(AVCC ≥ 2.7V)
Cin: max 14.7pF
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A/D Converter
CM71-10159-2E
CHAPTER 23 A/D CONVERTER
23.2 Block Diagram of A/D Converter
MB91461
23.2
Block Diagram of A/D Converter
Figure 23.2-1 shows the block diagram of A/D converter.
■ Block Diagram of A/D Converter
Figure 23.2-1 Block Diagram of A/D Converter
AVRH/
AVCC AVRL AVSS
D/A converter
MPX
Sequential comparison register
Internal data bus
·····
AN12
Input circuit
AN0
Comparator
Decoder
Sample &
hold circuit
Data register
A/D control register 0
A/D control register 1
ATGX pin
Operation clock
16-bit reload timer 7
CLKP
CM71-10159-2E
Prescaler
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
23.3
MB91461
Registers of A/D Converter
This section describes the register configuration and function of the A/D converter.
■ Overview of A/D Converter Registers
The A/D converter has the following six types of registers.
• Analog input enable register (ADER)
• Control status register (ADCS1, ADCS0)
• Data register (ADCR)
• Conversion time set register (ADCT)
• Start channel set register (ADSCH)
• End channel set register (ADECH)
■ Registers
Figure 23.3-1 Bit Configuration of A/D Converter
ADERH (Lower)
bit7
6
5
4
3
2
1
0
Address: 0001A1H
−
−
−
−
−
−
−
−
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit15
14
13
12
11
10
9
8
Address: 0001A2H
−
−
−
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
ADERL (Upper)
ADE12 ADE11 ADE10 ADE9
ADE8
ADERL (Lower)
Address: 0001A3H ADE7
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit15
14
13
12
11
10
9
8
Address: 0001A4H BUSY
INT
INTE
PAUS
STS1
STS0
ADCS1
STRT reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
(Continued)
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
(Continued)
ADCS0
bit7
Address: 0001A5H MD1
6
5
4
3
2
1
0
MD0
S10
ACH4
ACH3
ACH2
ACH1
ACH0
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
bit15
14
13
12
11
10
9
8
−
−
−
−
−
−
D9
D8
ADCR1
Address: 0001A6H
Read/Write
−
−
−
−
−
−
R
R
Initial value
−
−
−
−
−
−
X
X
bit7
6
5
4
3
2
1
0
Address: 0001A7H
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit15
14
13
12
11
10
9
8
Address: 0001A8H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
bit7
6
5
4
3
2
1
0
Address: 0001A9H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
0
1
1
0
0
bit15
14
13
12
11
10
9
8
−
−
−
−
ANS3
ANS2
ANS1
ANS0
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
bit7
6
5
4
3
2
1
0
−
−
−
−
ANE3
ANE2
ANE1
ANE0
ADCR0
ADCT1
ADCT0
ADSCH
Address: 0001AAH
ADECH
Address: 0001ABH
CM71-10159-2E
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
23.3.1
MB91461
Analog Input Enable Register (ADER)
The ADER bits correspond to the pins used for analog input. Always set these bits to "1".
■ A/D Enable Register (ADER)
Figure 23.3-2 Bit Configuration of A/D Enable Register (ADER)
ADERH (Lower)
bit7
6
5
4
3
2
1
0
Address: 0001A1H
−
−
−
−
−
−
−
−
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit15
14
13
12
11
10
9
8
Address: 0001A2H
−
−
−
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit7
6
5
4
3
2
1
0
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
ADERL (Upper)
ADE12 ADE11 ADE10 ADE9
ADE8
ADERL (Lower)
Address: 0001A3H ADE7
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit7 to bit0] Reserved bits
Reserved bits. Always set them to "0".
[bit12 to bit0] ADE12 to ADE0: A/D input enable
Table 23.3-1 A/D Input Enable
ADE
Function
0
General-purpose port [Initial value]
1
Analog input
These bits are initialized to 00000000H when reset.
Always set these bits to "1" for the start channel and end channel of this register.
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
23.3.2
A/D Control Status Register (ADCS)
The A/D control status register (ADCS) is used to control the A/D converter and to
indicate the status. Do not update the ADCS register during A/D converting.
■ A/D Control Status Register 1 (ADCS1)
Figure 23.3-3 Bit Configuration of A/D Control Status Register 1 (ADCS1)
ADCS1
bit15
14
13
12
11
10
Address: 0001A4H BUSY
INT
INTE
PAUS
STS1
STS0
9
8
STRT reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
[bit7] BUSY: Busy flag and stop
Table 23.3-2 BUSY (Busy Flag and Stop)
BUSY
Function
Reading
A/D converter operation indication bit. Set on activation of A/D conversion and cleared
on completion of conversion for last channel.
Writing
Writing 0 to this bit during A/D conversion forcibly terminates conversion. Use to forcibly terminate in continuous and stop modes.
Bits for operation indication cannot be set to "1".
Read-modify-write (RMW) instructions read the bit as "1".
Cleared on the completion of A/D conversion for the last channel in single conversion mode.
In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".
This bit is initialized to "0" by a reset.
Note:
Do not specify forcible termination and software activation (BUSY = 0 and STRT = 1) at the same
time.
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
[bit6] INT: Interrupt
This bit is set when conversion data is written in ADCR.
If bit5 (INTE) is "1" when this bit is set, an interrupt request is generated.
This bit is cleared by writing "0".
This bit is initialized to "0" by a reset.
If DMA is used, this bit is cleared when DMA transfer completes.
Note:
Only clear this bit by writing "0" when A/D conversion is halted.
[bit5] INTE: Interrupt enable
This bit enables or disables the conversion completion interrupt.
Table 23.3-3 INTE (Interrupt Enable)
INTE
Function
0
Disable interrupt [Initial value]
1
Enable interrupt
This bit is initialized to "0" by a reset.
[bit4] PAUS: A/D converter pause
This bit is set when A/D conversion temporarily halts.
The A/D converter has only one register to store the conversion result. Therefore the previous
conversion result is lost if it is not transferred by DMA when performing continuous conversion.
To avoid this problem, the next conversion data is not stored in the data register until the previous value
has been transferred by DMA. A/D conversion halts during this time. A/D conversion restarts when
DMA transfer completes.
This bit is only meaningful when using DMA.
- Cleared only by writing "0". (not cleared by DMA transfer completion.)
Unable to be cleared during waiting for DMA transferred.
- See the description of the conversion data protection function in the section "23.4 Operation of A/D
Converter".
- This bit is initialized to "0" when a reset.
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
[bit3, bit2] STS1 and STS0: A/D Start source select
These bits are initialized to "00B" when a reset.
Setting these bits selects the A/D start factor.
Table 23.3-4 STS1 and STS0 (A/D Start Source Select)
STS1
STS0
Function
0
0
Start by software [Initial value]
0
1
Start by external pin trigger or by software
1
0
Start by 16-bit reload timer or by software
1
1
Start by external pin trigger, by 16-bit reload timer or by software
In the mode in which two or more A/D conversion start factors are used, A/D conversion is started
using the A/D conversion start factor that occurs first.
The setting of the start source changes immediately after these bits are rewritten. Therefore it is
important to pay attention to rewriting during A/D converting.
- The external pin trigger detects a falling edge. If the external trigger is selected by writing these bits
when the external trigger input level is "L", the A/D may start.
- When 16-bit reload timer is selected, 16-bit reload timer 7 output is selected and a rising edge of the
16-bit reload timer output is detected. Refer to "CHAPTER 17 16-BIT RELOAD TIMER" for the
order of A/D setting and timer setting.
[bit1] STRT: Start
A/D converter is started by writing "1" to this bit (start by software).
Write "1" again to restart.
This bit is initialized to "0" by a reset.
Restart by setting this bit is ignored in the continuous mode or the stop mode. Check BUSY bit before
writing "1" (Clear BUSY bit before a restart).
Do not perform start by software and forced stop concurrently (STRT = 1, BUSY = 0).
[bit0] Reserved bit
Always set this bit to "0".
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
■ A/D Control Status Register 0 (ADCS0)
Figure 23.3-4 Bit Configuration of A/D Control Status Register 0 (ADCS0)
ADCS0
bit7
Address: 0001A5H MD1
6
5
4
3
2
1
0
MD0
S10
ACH4
ACH3
ACH2
ACH1
ACH0
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
[bit7, bit6] MD1, MD0: A/D converter mode set
MD1 and MD0 bits set the operation mode.
These bits are initialized to "00B" by a reset.
Table 23.3-5 MD1, MD0 (A/D Converter Mode Set)
MD1
MD0
Operation mode
0
0
Single mode: Disabled restart during operation [Initial value]
0
1
Single mode: Disabled restart during operation
1
0
Continuous mode: Disabled restart during operation
1
1
Stop mode: Disabled restart during operation
• Single mode
Continuous A/D conversion from selected channel(s) ANS4 to ANS0 to selected channel(s) ANE4 to
ANE0 with a pause after every conversion cycle.
• Continuous mode
Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selected channels ANE4
to ANE0.
• Stop mode
A/D conversion for each channel from selected channels ANS4 to ANS0 to selected channels ANE4
to ANE0, followed by a pause. Restart is determined by the occurrence of a start source.
• When A/D conversion is started in continuous mode or stop mode, conversion operation continued
until forcibly stopped by the BUSY bit.
• Conversion is forcibly stopped by writing "0" to the BUSY bit.
• Conversion after forcible stop starts from selected channel(s) ANS4 to ANS0.
• All restarts are disabled for any of the timer, external trigger and software start sources in single,
continuous and stop modes.
[bit5] S10
This bit selects the conversion resolution. When this bit is set to "0", 10-bit A/D conversion is selected,
otherwise, 8-bit A/D conversion is selected and ADCR0 stores the result.
This bit is initialized to "0" by a reset.
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
[bit4 to bit0] ACH4 to ACH0: Analog convert select channel
These bits represent the channel currently being A/D converted.
These bits are initialized to 00000B by a reset.
Table 23.3-6 Conversion Channel
ACH4
ACH3
ACH2
ACH1
ACH0
Conversion channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
Table 23.3-7 Function
CM71-10159-2E
ACH
Function
Reading
These bits represent the channel currently being converted during A/D conversion
(BUSY bit = 1) and represent the forcibly stopped channel when a forcibly stop occurs
with BUSY bit = 0.
Writing
Writing to these bits are ignored.
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
23.3.3
MB91461
Data Register (ADCR1, ADCR0)
Data register (ADCR1, ADCR0) stores the digital value of the conversion result from the
A/D converter. ADCR0 stores the lower-order 8 bits and ADCR1 stores the higher-order
2 bits of the conversion result. The register value is updated at the completion of each
conversion. The register normally stores the result of the previous conversion.
■ Data Register (ADCR1, ADCR0)
Figure 23.3-5 Bit Configuration of Data Register (ADCR1, ADCR0)
ADCR1
bit15
14
13
12
11
10
9
8
Address: 0001A6H
−
−
−
−
−
−
D9
D8
Read/Write
−
−
−
−
−
−
R
R
Initial value
−
−
−
−
−
−
X
X
bit7
6
5
4
3
2
1
0
Address: 0001A7H
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
ADCR0
Bit15 to bit10 of ADCR1 are read as 000000B.
The A/D converter has a conversion data protection function. See the section "23.4 Operation of A/D
Converter".
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CHAPTER 23 A/D CONVERTER
23.3 Registers of A/D Converter
MB91461
23.3.4
Conversion Time Setting Register (ADCT)
A/D conversion time setting register (ADCT) controls the sampling period and the
comparison period of the analog input. The A/D conversion time is set by this ADCT
register.
Do not write to ADCT register during a A/D conversion operation.
■ Conversion Time Setting Register
Figure 23.3-6 Bit Configuration of Conversion Time Setting Register
ADCT1
bit15
14
13
12
11
10
9
8
Address: 0001A8H
CT5
CT4
CT3
CT2
CT1
CT0
ST9
ST8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
bit7
6
5
4
3
2
1
0
Address: 0001A9H
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
0
1
1
0
0
ADCT0
[bit15 to bit10] CT5 to CT0: A/D comparison time set
These bits specify the clock divider value of the comparison operation period.
Set CT5 to CT0 to 000001B for no divider (=CLKP).
Do not set CT5 to CT0 to 000000B.
These bits are initialized to 000100B by a reset.
Compare time = CT setting value × CLKP cycle × 10 + (4 × CLKP cycle)
Note:
Set CT5 to CT0 so that 660 ns or more of the compare time is obtained.
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23.3 Registers of A/D Converter
MB91461
[bit9 to bit0] ST9 to ST0: A/D input sampling time set
These bits specify the sampling time of the analog input.
These bits are initialized to 0000101100B by a reset.
Sampling time required for A/D conversion (required sampling time) is determined depending on Rext
value. Therefore set ST9 to ST0 so that the obtained time is same or longer than the required sampling
time.
• Calculating formula for required sampling time
Required sampling time (Tsamp) = (Rext + Rin) × Cin × 7
• Calculating formula for ST9 to ST0 setting value
ST9 to ST0 setting value ≥ Required sampling time (Tsamp) ÷ CLKP cycle
Example: CLKP = 18 MHz, AVCC ≥ 3.0 V, Rext = 15 kΩ
Tsamp = (15 × 103 + 1.9 × 103) × 14.7 × 10-12 × 7 = 1.74s
→ ST = 1.74 × 10-6 ÷ (1/18.0 × 106 ) = 31.3 → Set 32 (0000100000B) or more.
Note:
0000000000B, 0000000001B and 0000000010B must not be set to ST9 to ST0.
Set Rext so that 400 ns or more of the sampling time is obtained.
■ Recommended Setting Value
To obtain the best conversion time, the following setting value is recommended.
Table 23.3-8 Recommended Setting Value
CLKP
(MHz)
Comparison time
(CT5 to CT0)
Sampling time
(ST9 to ST0)
ADCT
setting
value
Conversion time (μs)
9
000001B
0000001001B
0409H
1.56 + 1.00 = 2.56
18
000010B
0000010010B
0812H
1.33 + 1.00 = 2.33
(AVCC ≥ 3.0V, Rext ≤ 5.1 kΩ)
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CHAPTER 23 A/D CONVERTER
23.3
MB91461
23.3.5
Start Channel Setting Register (ADSCH)
End Channel Setting Register (ADECH)
Registers of A/D Converter
Registers for setting the start channel and the end channel of the A/D conversion.
Do not write to ADSCH or ADECH during A/D conversion.
■ Start Channel Setting Register (ADSCH) and End Channel Setting Register (ADECH)
Figure 23.3-7 Bit Configuration of Start Channel Setting Register (ADSCH)
and End Channel Setting Register (ADECH)
ADSCH
bit15
14
13
12
11
10
9
8
−
−
−
−
ANS3
ANS2
ANS1
ANS0
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
bit7
6
5
4
3
2
1
0
−
−
−
−
ANE3
ANE2
ANE1
ANE0
Address: 0001AAH
ADECH
Address: 0001ABH
Read/Write
−
−
−
−
R/W
R/W
R/W
R/W
Initial value
−
−
−
−
0
0
0
0
These bits specify the start channel and the end channel of the A/D conversion.
When the same channel is written to ANS4 to ANS0 and ANE4 to ANE0, the conversion is performed for
only one channel (single channel conversion).
In a continuous mode or a stop mode, after the conversion of the channel set by these bits are completed,
return to the start channel set by ANS4 to ANS0 is performed.
Note:
Set the start channel and the end channel so that always ANS is same or smaller than ANE.
If ANS is larger than ANE, correct operation is not assured.
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23.3 Registers of A/D Converter
MB91461
[bit12 to bit8] ANS4 to ANS0 (A/D start channel set)
[bit4 to bit0] ANE4 to ANE0 (A/D end channel set)
Table 23.3-9 Start/end Channel
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
Start/end channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
x
x
x
x
Setting disabled
Note:
Please do not set the A/D start channel setting by the read-modify-write (RMW) instruction after
setting the start channel to the A/D start channel setting (ANS4, ANS3, ANS2, ANS1, ANS0).
The last conversion channel is read from the ANS4, ANS3, ANS2, ANS1, and ANS0 bits until the A/
D conversion operating starts.
Therefore, when ANE4, ANE3, ANE2, ANE1, and ANE0 bits are set by the read-modify-write (RMW)
instruction after setting the start channel to ANS4, ANS3, ANS2, ANS1, and ANS0 bits, the value of
the ANE4, ANE3, ANE2, ANE1, and ANE0 bits may be overwritten.
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CHAPTER 23 A/D CONVERTER
MB91461
23.4
Operation of A/D Converter
23.4 Operation of A/D Converter
The A/D converter operates using the successive approximation method with 10-bit or
8-bit selectable resolution. This section describes the operation mode of the A/D
converter.
■ A/D Conversion Data
The conversion data register (ADCR0 and ADCR1) is rewritten at each completion of the conversion
because this A/D converter has only one register (16-bit) for storing the conversion result. Therefore the
alone A/D converter is not suitable for a continuous conversion. It is recommended to transfer the
conversion data to the memory using DMA during conversion.
■ Single Mode
In single mode, the analog input signals selected by the ANS bits and ANE bits are converted in order until
the completion of conversion on the end channel determined by the ANE bits. A/D conversion then ends. If
the start channel and end channel are the same (ANS = ANE), only a single channel conversion is
performed.
Examples:
• ANS = 00000B, ANE = 00011B
Start  AN0  AN1  AN2  AN3  (End)
• ANS = 00010B, ANE = 00010B
Start  AN2  (End)
■ Continuous Mode
In continuous mode, the analog input signals selected by the ANS bits and ANE bits are converted in order
until the completion of conversion on the end channel determined by the ANE bits, then the converter
returns to the ANS channel for analog input and repeats the process continuously. When the start and end
channels are the same (ANS = ANE), conversion is performed continuously for a single channel.
Examples:
• ANS = 00000B, ANE = 00011B
Start  AN0  AN1  AN2  AN3  AN0  AN1 (repeat)
• ANS = 00010B, ANE = 00010B
Start  AN2  AN2  AN2 (repeat)
In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to the BUSY
bit forcibly stops the conversion operation.) Note that forcibly terminating operation halts the current
conversion during mid-conversion. (If operation is forcibly terminated, the value in the conversion register
is the result of the most recently completed conversion.)
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CHAPTER 23 A/D CONVERTER
23.4 Operation of A/D Converter
MB91461
■ Stop Mode
In stop mode, the analog input signals selected by the ANS bits and ANE bits are converted in order, but
conversion operation pauses for each channel. The pause is released by applying another start signal.
At the completion of conversion on the end channel determined by the ANE bits, the converter returns to
the ANS channel for analog input signal and repeats the conversion process continuously. When the start
and end channels are the same (ANS = ANE), only a single channel conversion is performed.
Examples:
• ANS = 00000B, ANE = 00011B
Start  AN0 stop  start  AN1  stop  start  AN2  stop  start 
AN3  stop  start  AN0  stop  start  AN1 (repeat)
• ANS = 00010B, ANE = 00010B
Start  AN2  stop  start  AN2  stop  start  AN2 (repeat)
In stop mode, the startup source is only the source determined by the STS1, STS0 bits.
This mode enables synchronization of the conversion start signal.
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CHAPTER 24
FLASH MEMORY SUPPORT
This chapter describes the support of the on-board flash
memory serial programming.
24.1 Flash Memory Serial Programming
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CHAPTER 24 FLASH MEMORY SUPPORT
24.1 Flash Memory Serial Programming
24.1
MB91461
Flash Memory Serial Programming
MB91461 supports the serial programming for FLASH memory connected to external
buses.
■ Flash Memory Serial Programming
MB91F467R has a support function for on-board FLASH serial programming.
This is called serial download function. With this function, data can be downloaded to the internal RAM
and the program can be executed by jumping to the downloaded address. To use this function, several port
settings and mode terminal settings are required.
Table 24.1-1 Setting for Using Serial Download
P15_2
P15_3
Serial communication function
0
0
Asynchronous serial download
0
1
Synchronous serial download
Canceling the reset (INITX) by P15 and mode pin settings (MD3 to MD0 = 0100B), enables the serial
download function. LIN-UART ch0(SIN0,SOT0,SCK0) is used in a serial download. The communication
conditions are as follows.
Table 24.1-2 Communication Condition for Serial Download
Communication
mode
Clock
Parity
Stop bit
Transfer
direction
Data length
Asynchronous
Internal
None
1
8 bit
From LSB
Synchronous
External
None
None
8 bit
From LSB
The baud rate generator is set as follows
Table 24.1-3 Baud Rate Setting
Crystal
620
BGR0
Baud rate
Error
10MHz
BGR0=103H
4808bps
0.16% (for 4800)
20MHz
BGR0=103H
9615bps
0.16% (for 9600)
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX
The appendix describes pin states in each CPU state,
notes on using the little-endian areas, a list of FR family
instructions, and notes on using MB91461.
APPENDIX A Instruction Lists
APPENDIX B I/O Map
APPENDIX C Interrupt Vector
APPENDIX D DMA Transfer Request Source
APPENDIX E Pin State at Serial Programming Mode
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APPENDIX
MB91461
APPENDIX A
Instruction Lists
This section includes Instruction Lists of MB91460 super-series CPU.
A.1 Meaning of Symbols
A.2 Instruction Lists
A.3 Instruction Maps
A.4 Instruction Maps of Instruction Format TYPE-E
Code: CM71-00504-1E
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APPENDIX A Instruction Lists
MB91461
A.1 Meaning of Symbols
This section describes the meaning of symbols used in the Instruction Lists.
A.1.1
Mnemonic and Operation Columns
These are the symbols used in Mnemonic and Operation columns of Instruction Lists.
i4
It is 4-bit immediate data. 0(0H) to 15(FH) in case of zero extension and -16(0H) to -1(FH) in case of
minus extension can be specified.
Table A.1-1 Zero Extension and Minus Extension Values of 4-bit Immediate Data
Specified Value
Bit Pattern
Zero Extension
Minus Extension
0000B
0
-16
0001B
1
-15
0010B
2
-14
...
1101B
13
-3
1110B
14
-2
1111B
15
-1
i8
8-bit immediate data, range 0 (00H) to 255 (FFH)
i20
20-bit immediate data, range 0 (00000H) to 1,048,575 (FFFFFH)
i32
32-bit immediate data, range 0 (0000 0000H) to 4,294,967,295 (FFFF FFFFH)
s8
Signed 8-bit immediate data, range -128 (80H) to 127 (7FH)
s10
Signed 10-bit immediate data, range -512 (200H) to 508 (1FCH) in multiples of 4
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APPENDIX
MB91461
u4
Unsigned 4-bit immediate data, range 0 (0H) to 15 (FH)
u8
Unsigned 8-bit immediate data, range 0 (00H) to 255 (FFH)
u10
Unsigned 10-bit immediate data, range 0 (000H) to 1020 (3FCH) in multiples of 4
udisp6
Unsigned 6-bit address values, range 0 (00H) to 60 (3CH) in multiples of 4
disp8
Signed 6-bit address values, range -128(80H) to 127(7FH)
disp9
Signed 9-bit address values, range -256(100H) to 254(0FEH) in multiples of 2
disp10
Signed 10-bit address values, range -512(200H) to 508(1FCH) in multiples of 4
dir8
Unsigned 8-bit address values, range 0 (00H) to 255 (FFH)
dir9
Unsigned 9-bit address values, range 0 (000H) to 510 (1FEH) in multiples of 2
dir10
Unsigned 10-bit address values, range 0 (000H) to 1020 (3FCH)in multiples of 4
label9
Branch address, range 256 (100H) to 254 (0FEH) in multiples of 2 for the value of Program Counter
(PC) +2
label12
Branch address, range - 2048 (800H) to 2046 (7FEH) in multiples of 2 for the value of Program Counter
(PC) +2
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APPENDIX A Instruction Lists
MB91461
rel8
Signed 8-bit relative address. Result which is double the value of rel8 for the value of Program Counter
(PC) +2 will denote the Branch Destination Address. Range -128 (80H) to 127 (7FH)
rel11
Signed 11-bit relative address. Result which is double the value of rel11 for the value of Program
Counter (PC) +2 will denote the Branch Destination Address. Range -1024 (400H) to 1023 (3FFH)
Ri, Rj
Indicates General-purpose Registers (R0 to R15)
Table A.1-2 Specification of General-purpose Register based on Rj/Ri
Ri / Rj
Register
Ri / Rj
Register
0000
R0
1000
R8
0001
R1
1001
R9
0010
R2
1010
R10
0011
R3
1011
R11
0100
R4
1100
R12
0101
R5
1101
R13
0110
R6
1110
R14
0111
R7
1111
R15
Rs
Indicates Dedicated Registers (TBR, RP, USP, SSP, MDH, MDL)
Table A.1-3 Specification of Dedicated Register based on Rs
Rs
Register
Rs
0000
Table Base Register (TBR)
1000
0001
Return Pointer (RP)
1001
0010
System Stack Pointer (SSP)
1010
0011
User Stack Pointer (USP)
1011
0100
Multiplication/Division Register (MDH)
1100
0101
Multiplication/Division Register (MDL)
1101
0110
0111
Register
Reserved (Disabled)
1110
Reserved (Disabled)
1111
(reglist)
Indicates 8-bit Register list. Register corresponding to each bit value can be specified.
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APPENDIX
MB91461
Table A.1-4 Correspondence between reglist of LDM0, LDM1 Instruction and
General-purpose Register
LDM0 Instruction
LDM1 Instruction
reglist
Register
reglist
Register
bit0
R0
bit0
R8
bit1
R1
bit1
R9
bit2
R2
bit2
R10
bit3
R3
bit3
R11
bit4
R4
bit4
R12
bit5
R5
bit5
R13
bit6
R6
bit6
R14
bit7
R7
bit7
R15
Table A.1-5 Correspondence between reglist of STM0, STM1 Instruction and
General-purpose Register
STM0 Instruction
A.1.2
STM1 Instruction
reglist
Register
reglist
Register
bit0
R7
bit0
R15
bit1
R6
bit1
R14
bit2
R5
bit2
R13
bit3
R4
bit3
R12
bit4
R3
bit4
R11
bit5
R2
bit5
R10
bit6
R1
bit6
R9
bit7
R0
bit7
R8
Operation Column
These are symbols used in Operation Column of Instruction Lists and operation of Detailed Execution
Instructions.
extu( )
Indicates a zero extension operation, in which portion lacking higher bits is complemented by adding
"0" bit.
extn( )
Indicates a minus extension operation, in which portion lacking higher bits is complemented by adding
"1" bit.
exts( )
Indicates a sign extension operation, in which zero extension is performed for the data within ( ) if MSB
is "0" and a minus extension is performed if MSB is "1".
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APPENDIX A Instruction Lists
MB91461
&
Indicates logical calculation of each bit (AND)
|
Indicates the logical sum of each bit (OR)
^
Indicates Dedicated Logical Sum of each bit (EXOR)
()
Indicates specification of indirect address. It is address memory read/write value of the Register or
formula within ( ).
{}
Indicate the calculation priority. Since ( ) is used for specifying indirect address, different bracket
namely { } is used.
if (Condition) then {formula} or if (condition) then {Formula 1} else {Formula 2}
Indicates the execution of conditions. If the conditions are established, formula after ‘then’ is executed
and when the conditions are not established, formula next to ‘else’ is executed. Formula can be
described variously using the { }.
[m:n]
Bits from m to n are extracted and targeted for operation.
A.1.3
Format Column
Symbols used in the Format Column of the Instruction Lists.
A to H
Indicates the Instruction Formats. A to H correspond to TYPE-A to TYPE-H.
A.1.4
OP Column
Hexadecimal value used in the Instruction Lists. They denote operation codes (OP, SUB-OP). They branch
into the following depending on the Instruction Format.
TYPE-A, TYPE-C, TYPE-D, TYPE-G
2-digit hexadecimal value represents 8-bit OP code
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APPENDIX
MB91461
TYPE-B
2-digit hexadecimal value represents higher 4 bits of OP code with lower 4 bits of 0000B.
TYPE-E, TYPE-E’, TYPE-H
4-digit hexadecimal value represents higher 8 bits of OP code with higher 2 digits, 4-bits of SUB-OP
code with the next 1 digit and the remainder with "0".
TYPE-F
2-digit hexadecimal code represents higher 5 bits of OP code with lower 3 bits of 000B.
A.1.5
CYC Column
Symbols used in CYC Column of Instruction Lists and the member of execution cycles of Detailed
Execution Instructions. Numerical values represent CPU clock cycles.
a
Memory access cycles. Cycles change depending on the access target. Minimum value is 1 cycle.
b
Memory access cycles. Cycles change depending on the access target. Minimum value is 1 cycle.
When the Register which is target of load operation is referred to by the succeeding Instruction, an
interlock will be applied from that point and the number of execution cycles will increase by 1.
c
An interlock will be applied when the immediately next Instruction is read and written to
Multiplication/Division Register (R15, SSP and USP).
An interlock will be applied when the immediately next Instruction is the Instruction Format A.
Cycles will be increased by 1. Otherwise it will be 2 cycles. However, minimum value is 1 cycle.
d
An interlock will be applied when the immediately next Instruction refers to Multiplication/Division
Register (MDH/MDL) and the number of execution cycles will be increased by 1. Otherwise it will be 2
cycles. However, Minimum value is 1 cycle.
An interlock will be always applied when the Special Register (TBR, RP, USP, SSP, MDH, or MDL) is
accessed by the "ST Rs, @R15-" instruction located immediately after the DIV1 Instruction. The
number of execution cycles will be increased by 1 with the interlock. Otherwise it will be 2 cycles.
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APPENDIX A Instruction Lists
MB91461
A.1.6
FLAG Column
Symbols used for flag change in the Flag Column of Instruction Lists and Detailed Execution Instructions.
Represents change in Negative Flag (N), Zero Flag (Z), Overflow Flag (V), Carry Flag (C) of the Condition
Code Register (CCR).
C
Varies depending on the result of operation
No change
0
Value becomes "0"
1
Value becomes "1"
A.1.7
RMW Column
Symbols used in the RMW Column of Instruction Lists. It represents whether or not it is Read-ModifyWrite Instruction.
Instruction is not Read-Modify-Write Instruction.
❍
Instruction is Read-Modify-Write Instruction.
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APPENDIX
MB91461
A.2
Instruction Lists
This section indicates Instruction Lists of MB91460 Super-series CPU.
There are a total of 165 instructions in MB91460 Super-series CPU. These instructions are divided into the
following 16 categories.
•
Add/Subtract Instructions (10Instructions)
•
Compare Calculation Instructions (3 Instructions)
•
Logical Calculation Instructions (12 Instructions)
•
Bit Operation Instructions (8 Instructions)
•
Multiply/ Divide Instructions (10 Instructions)
•
Shift Instructions (9 Instructions)
•
Immediate Data Transfer Instructions (3 Instructions)
•
Memory Load Instructions (13 Instructions)
•
Memory Store Instructions (13 Instructions)
•
Inter-Register Transfer Instructions/Dedicated Register Transfer Instructions (5 Instructions)
•
Non-delayed Branching Instructions (23 Instructions)
•
Delayed Branching Instructions (20 Instructions)
•
Direct Addressing Instructions (14 Instructions)
•
Other Instructions (16 Instructions)
•
Resource instruction (2 Instructions)
•
Coprocessor control instruction (4 Instructions)
Table A.2-1 Add/Subtract Instructions (10Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
ADD Rj, Ri
A
A6
1
CCCC
-
Ri+Rj → Ri
ADD #i4, Ri
C
A4
1
CCCC
-
Ri+extu(i4) → Ri
i4 is zero extension
ADD2 #i4, Ri
C
A5
1
CCCC
-
Ri+extn(i4) → Ri
i4 is Minus extension
ADDC Rj, Ri
A
A7
1
CCCC
-
Ri+Rj+C → Ri
Add with carry
ADDN Rj, Ri
A
A2
1
----
-
Ri+Rj → Ri
ADDN #i4, Ri
C
A0
1
----
-
Ri+extu(i4) → Ri
i4 is Zero extension
ADDN2 #i4, Ri
C
A1
1
----
-
Ri+extn(i4) → Ri
i4 is Minus extension
SUB Rj, Ri
A
AC
1
CCCC
-
Ri-Rj → Ri
SUBC Rj, Ri
A
AD
1
CCCC
-
Ri-Rj-C →Ri
SUBN Rj, Ri
A
AE
1
----
-
Ri-Rj → Ri
Mnemonic
630
Operation
FUJITSU MICROELECTRONICS LIMITED
Remarks
Add with carry
CM71-10159-2E
APPENDIX A Instruction Lists
MB91461
Table A.2-2 Compare Calculation Instructions (3 Instructions)
Mnemonic
CMP Rj, Ri
CMP #i4, Ri
CMP2 #i4, Ri
Format
OP
CYC
FLAG
NZVC
RMW
A
C
C
AA
A8
A9
1
1
1
CCCC
CCCC
CCCC
-
Operation
Ri-Rj
Ri-extu(i4)
Ri-extn(i4)
Remarks
i4 is Zero extension
i4 is Minus extension
Table A.2-3 Logical Calculation Instructions (12 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
A
A
A
A
A
A
A
A
A
A
A
A
82
84
85
86
92
94
95
96
9A
9C
9D
9E
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC--
❍
❍
❍
❍
❍
❍
❍
❍
❍
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR Rj, Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
Operation
Remarks
Ri & Rj → Ri
(Ri) & Rj → (Ri)
(Ri) & Rj → (Ri)
(Ri) & Rj → (Ri)
Ri | Rj → Ri
(Ri) | Rj → (Ri)
(Ri) | Rj → (Ri)
(Ri) | Rj → (Ri)
Ri ^ Rj → Ri
(Ri) ^ Rj → (Ri)
(Ri) ^ Rj → (Ri)
(Ri) ^ Rj → (Ri)
Word
Word
Half-Word
Byte
Word
Word
Half-Word
Byte
Word
Word
Half-Word
Byte
Table A.2-4 Bit Operation Instructions (8 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
BANDL #u4, @Ri
C
80
1+2a
----
❍
(Ri) & {F0H+u4} → (Ri)
Lower 4- bit
BANDH #u4, @Ri
C
81
1+2a
----
❍
(Ri) & {u4<<4+0FH} → (Ri)
Higher 4 bit
BORL #u4, @Ri
BORH #u4, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
BTSTL #u4, @Ri
BTSTH #u4, @Ri
C
C
C
C
C
C
90
91
98
99
88
89
1+2a
1+2a
1+2a
1+2a
2+a
2+a
------------0C-CC--
❍
❍
❍
❍
-
(Ri) | u4 → (Ri)
(Ri) | {u4<<4} → (Ri)
(Ri) ^ u4 → (Ri)
(Ri) ^ {u4<<4} → (Ri)
(Ri) & u4
(Ri) & {u4<<4}
Lower 4- bit
Higher 4 bit
Lower 4- bit
Higher 4 bit
Lower 4- bit
Higher 4 bit
Operation
Remarks
Table A.2-5 Multiply/ Divide Instructions (10 Instructions)
Mnemonic
Format
OP
CYC
MUL Rj, Ri
MULU Rj, Ri
MULH Rj, Ri
MULUH Rj, Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
A
A
A
A
E
E
E
E
E’
E’
AF
AB
BF
BB
97-4
97-5
97-6
97-7
9F-6
9F-7
5
5
3
3
1
1
d
1
1
1
CM71-10159-2E
FLAG
NZVC
CCCCCCCC-CC--------C-C
-C-C
-------
Operation
RMW
-
Ri
Ri
Ri
Ri
× Rj → MDH,MDL
× Rj → MDH,MDL
× Rj → MDL
× Rj → MDL
In the Specified
Instruction Sequence
MDL ÷ Ri → MDL
MDL%Ri → MDH
Remarks
32 × 32 bit = 64 bit
Unsigned
16 × 16 bit = 32 bit
Unsigned
Step Calculation
32 ÷ 32 bit = 32 bit
FUJITSU MICROELECTRONICS LIMITED
631
APPENDIX
MB91461
Table A.2-6 Shift Instructions (9 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
LSL Rj, Ri
A
B6
1
CC-C
-
Ri << Rj → Ri
LSL #u4, Ri
C
B4
1
CC-C
-
Ri << u4 → Ri
LSL2 #u4, Ri
C
B5
1
CC-C
-
Ri << {u4+16} → Ri
LSR Rj, Ri
A
B2
1
CC-C
-
Ri >> Rj → Ri
LSR #u4, Ri
C
B0
1
CC-C
-
Ri >> u4 → Ri
LSR2 #u4, Ri
C
B1
1
CC-C
-
Ri >> {u4+16} → Ri
ASR Rj, Ri
A
BA
1
CC-C
-
Ri >> Rj → Ri
Mnemonic
Operation
Remarks
Logical Shift
Logical Shift
ASR #u4, Ri
C
B8
1
CC-C
-
Ri >> u4 → Ri
ASR2 #u4, Ri
C
B9
1
CC-C
-
Ri >> {u4+16} → Ri
Arithmetic Shift
Table A.2-7 Immediate Data Transfer Instructions (3 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
LDI:32 #i32, Ri
H
9F-8
3
----
-
i32 → Ri
LDI:20 #i20, Ri
G
9B
2
----
-
extu(i20) → Ri
Higher 12-Bits are Zero extension
LDI:8 #i8, Ri
B
C0
1
----
-
extu(i8) → Ri
Higher 24-Bits are Zero extension
Operation
Remarks
Table A.2-8 Memory Load Instructions (13 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
LD @Rj, Ri
A
04
b
----
-
(Rj) → Ri
LD @(R13, Rj), Ri
A
00
b
----
-
(R13+Rj) → Ri
LD @(R14, disp10), Ri
B
20
b
----
-
(R14+o8 × 4) → Ri
LD @(R15, udisp6), Ri
C
03
b
----
-
(R15+u4 × 4) → Ri
LD @R15+, Ri
E
07-0
b
----
-
(R15) → Ri,
R15+4 → R15
LD @R15+, Rs
E
07-8
b
----
-
(R15) → Rs,
R15+4 → R15
LD @R15+, PS
E
07-9
1+a+C
CCCC
-
(R15) → PS,
R15+4 → R15
LDUH @Rj, Ri
A
05
b
----
-
extu((Rj)) → Ri
LDUH @(R13, Rj), Ri
A
01
b
----
-
extu((R13+Rj)) → Ri
Mnemonic
Operation
LDUH @(R14, disp9), Ri
B
40
b
----
-
extu((R14+o8 × 2)) → Rj
LDUB @Rj, Ri
A
06
b
----
-
extu((Rj)) → Ri
LDUB @(R13, Rj), Ri
A
02
b
----
-
extu((R13+Rj)) → Ri
LDUB @(R14, disp8), Ri
B
60
b
----
-
extu((R14+o8)) → Ri
Remarks
Word
HalfWord
Zero extension
Byte
Zero extension
• Relation of field "o8" in the Instruction Format TYPE-B and field "u4" in TYPE-C Format to the values
disp8 to disp10, udisp6 in assembly notation is as follows.
o8 = disp8
o8 = disp9 >> 1
o8 = disp10 >> 2
u4 = udisp6 >> 2
632
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX A Instruction Lists
MB91461
Table A.2-9 Memory Store Instructions (13 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
ST Ri, @Rj
A
14
a
----
-
Ri → (Rj)
ST Ri, @(R13, Rj)
A
10
a
----
-
Ri → (R13+Rj)
ST Ri, @(R14, disp10)
B
30
a
----
-
Ri → (R14+o8 × 4)
ST Ri, @(R15, udisp6)
C
13
a
----
-
Ri → (R15+u4 × 4)
ST Ri, @-R15
E
17-0
a
----
-
R15-4 → R15,
Ri → (R15)
ST Rs, @-R15
E
17-8
a
----
-
R15-4 → R15,
Rs → (R15)
ST PS, @-R15
E
17-9
a
----
-
R15-4 → R15,
PS → (R15)
STH Ri, @Rj
A
15
a
----
-
Ri → (Rj)
STH Ri, @(R13, Rj)
A
11
a
----
-
Ri → (R13+Rj)
STH Ri, @(R14, disp9)
B
50
a
----
-
Ri → (R14+o8 × 2)
STB Ri, @Rj
A
16
a
----
-
Ri → (Rj)
STB Ri, @(R13, Rj)
A
12
a
----
-
Ri → (R13+Rj)
STB Ri, @(R14, disp8)
B
70
a
----
-
Ri → (R14+o8)
Mnemonic
Operation
Remarks
Word
Half-Word
Byte
• Relation of field "o8" in the Instruction Format TYPE-B and field "u4" in TYPE-C Format to the values
disp8 to disp10, udisp6 in assembly notation is as follows.
o8 = disp8
o8 = disp9 >> 1
o8 = disp10 >> 2
u4 = udisp6 >> 2
Table A.2-10 Inter-Register Transfer Instructions/Dedicated Register Transfer Instructions (5
Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
Operation
MOV Rj, Ri
A
8B
1
----
-
Rj → Ri
Transfer between general-purpose Registers
MOV Rs, Ri
A
B7
1
----
-
Rs → Ri
Rs: Dedicated Register
MOV Ri, Rs
A
B3
1
----
-
Ri → Rs
Rs: Dedicated Register
MOV PS, Ri
E
17-1
1
----
-
PS → Ri
PS: Program Status
MOV Ri, PS
E
07-1
c
CCCC
-
Ri → PS
PS: Program Status
CM71-10159-2E
Remarks
FUJITSU MICROELECTRONICS LIMITED
633
APPENDIX
MB91461
Table A.2-11 Non-delayed Branching Instructions (23 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
JMP @Ri
E
97-0
2
----
-
Ri → PC
CALL label12
F
D0
2
----
-
PC+2 → RP,
PC+2+exts(rel11 × 2) → PC
CALL @Ri
RET
E
E’
97-1
97-2
2
2
-------
-
Mnemonic
Operation
Remarks
PC+2 → RP, Ri → PC
RP → PC
SSP-4 → SSP, PS → (SSP),
SSP-4 → SSP, PC+2 → (SSP),
0 → CCR:I, 0 → CCR:S,
(TBR+3FC-u8 × 4) → PC
SSP → SSP, PS → (SSP),
SSP → SSP, PC+2 → (SSP),
0 → CCR:S, 4 → ILM,
(TBR+3D8) → PC
(SSP) → PC, SSP+4 → SSP,
(SSP) → PS, SSP+4 → SSP
INT #u8
D
1F
3+3a
----
-
INTE
E’
9F-3
3+3a
----
-
RETI
E’
97-3
2+2a
----
-
BNO label9
BRA label9
D
D
E1
E0
1
2
-------
-
No branch
BEQ label9
D
E2
2/1
----
-
BNE label9
D
E3
2/1
----
-
BC label9
D
E4
2/1
----
-
BNC label9
D
E5
2/1
----
-
BN label9
D
E6
2/1
----
-
BP label9
D
E7
2/1
----
-
BV label9
D
E8
2/1
----
-
BNV label9
D
E9
2/1
----
-
if (Z==1) then
PC+2+exts(rel8 × 2) → PC
if (Z==0) then
PC+2+exts(rel8 × 2) → PC
if (C==1) then
PC+2+exts(rel8 × 2) → PC
if (C==0) then
PC+2+exts(rel8 × 2) → PC
if (N==1) then
PC+2+exts(rel8 × 2) → PC
if (N==0) then
PC+2+exts(rel8 × 2) → PC
if (V==1) then
PC+2+exts(rel8 × 2) → PC
if (V==0) then
PC+2+exts(rel8 × 2) → PC
BLT label9
D
EA
2/1
----
-
BGE label9
D
EB
2/1
----
-
BLE label9
D
EC
2/1
----
-
BGT label9
D
ED
2/1
----
-
BLS label9
D
EE
2/1
----
-
BHI label9
D
EF
2/1
----
-
PC+2+exts(rel8 × 2) → PC
if (V ^ N==1) then
PC+2+exts(rel8 × 2) → PC
if (V ^ N==0) then
PC+2+exts(rel8 × 2) → PC
if ({V ^ N} | Z==1) then
PC+2+exts(rel8 × 2) → PC
if ({V ^ N} | Z==0) then
PC+2+exts(rel8 × 2) → PC
if (C or Z==1) then
PC+2+exts(rel8 × 2) → PC
if (C or Z==0) then
PC+2+exts(rel8 × 2) → PC
• The value of "2/1" in CYC Column indicates 2 cycles if branching and 1 if not branching.
• It is necessary to set the Stack Flag (S) to "0" for RETI execution.
• The field "rel8" in TYPE_D Instruction Format and the field "rel11" in TYPE-F Format have the
following relation to the values of label9, label12 in assembly notation.
rel8 = (label9-PC-2)/2
rel11 = (label12-PC-2)/2
634
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX A Instruction Lists
MB91461
Table A.2-12 Delayed Branching Instructions (20 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
JMP:D @Ri
E
9F-0
1
----
-
Ri → PC
CALL:D label12
F
D8
1
----
-
PC+4 → RP,
PC+2+exts(rel11 × 2) → PC
CALL:D @Ri
E
9F-1
1
----
-
PC+4 → RP, Ri → PC
RET:D
E’
9F-2
1
----
-
RP → PC
BNO:D label9
D
F1
1
----
-
No branch
BRA:D label9
D
F0
1
----
-
PC+2+exts(rel8 × 2) → PC
BEQ:D label9
D
F2
1
----
-
if (Z==1) then
PC+2+exts(rel8 × 2) → PC
BNE:D label9
D
F3
1
----
-
if (Z==0) then
PC+2+exts(rel8 × 2) → PC
BC:D label9
D
F4
1
----
-
if (C==1) then
PC+2+exts(rel8 × 2) → PC
BNC:D label9
D
F5
1
----
-
if (C==0) then
PC+2+exts(rel8 × ) → PC
BN:D label9
D
F6
1
----
-
if (N==1) then
PC+2+exts(rel8 × 2) → PC
BP:D label9
D
F7
1
----
-
if (N==0) then
PC+2+exts(rel8 × 2) → PC
BV:D label9
D
F8
1
----
-
if (V==1) then
PC+2+exts(rel8 × 2) → PC
BNV:D label9
D
F9
1
----
-
if (V==0) then
PC+2+exts(rel8 × 2) → PC
BLT:D label9
D
FA
1
----
-
if (V ^ N==1) then
PC+2+exts(rel8 × 2) → PC
BGE:D label9
D
FB
1
----
-
if (V ^ N==0) then
PC+2+exts(rel8 × 2) → PC
BLE:D label9
D
FC
1
----
-
if ({V ^ N} | Z==1) then
PC+2+exts(rel × 2) → PC
BGT:D label9
D
FD
1
----
-
if ({V ^ N} | Z==0) then
PC+2+exts(rel8 × 2) → PC
BLS:D label9
D
FE
1
----
-
if (C or Z==1) then
PC+2+exts(rel8 × 2) → PC
BHI:D label9
D
FF
1
----
-
if (C or Z==0) then
PC+2+exts(rel8 × 2) → PC
Mnemonic
Operation
Remarks
• Delayed Branching Instructions are branched after always executing the following Instruction (the Delay
Slot).
• The field "rel8" in TYPE-D instruction format and the field "rel11" in TYPE-D format have the
following relation to the values label9, label12 in assembly notation.
rel8 = (label9-PC-2)/2
rel11 = (label12-PC-2)/2
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
635
APPENDIX
MB91461
Table A.2-13 Direct Addressing Instructions (14 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
DMOV @dir10, R13
D
08
b
----
-
(dir8 × 4) → R13
DMOV R13, @dir10
D
18
a
----
-
R13 → (dir8 × 4)
DMOV @dir10, @R13+
D
0C
2a
----
-
(dir8 × 4) → (R13),
R13+4 → (R13)
DMOV @R13+, @dir10
D
1C
2a
----
-
(R13) → (dir8 × 4),
R13+4 → (R13)
DMOV @dir10, @-R15
D
0B
2a
----
-
R15-4 → (R15),
(dir8 × 4) → (R15)
DMOV @R15+, @dir10
D
1B
2a
----
-
(R15) → (dir8 × 4),
R15+4 → (R15)
DMOVH @dir9, R13
D
09
b
----
-
(dir8 × 2) → R13
DMOVH R13, @dir9
D
19
a
----
-
R13 → (dir8 × 2)
DMOVH @dir9, @R13+
D
0D
2a
----
-
(dir8 × 2) → (R13),
R13+2 → (R13)
DMOVH @R13+, @dir9
D
1D
2a
----
-
(R13) → (dir8 × 2),
R13+2 → (R13)
DMOVB @dir8, R13
D
0A
b
----
-
(dir8) → R13
DMOVB R13, @dir8
D
1A
a
----
-
R13 → (dir8)
DMOVB @dir8, @R13+
D
0E
2a
----
-
(dir8) → (R13),
R13+2 → (R13)
DMOVB @R13+, @dir8
D
1E
2a
----
-
(R13) → (dir8),
R13+2 → (R13)
Mnemonic
Operation
Remarks
Word
Half-Word
Byte
• The field "dir8" in TYPE-D Instruction format has the following relation to the values of dir8, dir9, dir10
in assembly notation.
dir8 = dir8
dir8 = dir9 >> 1
dir8 = dir10 >> 2
636
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX A Instruction Lists
MB91461
Table A.2-14 Other Instructions (16 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
NOP
E’
9F-A
1
----
-
No change
ANDCCR #u8
D
83
c
CCCC
-
CCR & u8 → CCR
ORCCR #u8
D
93
c
CCCC
-
CCR | u8 → CCR
STILM #u8
D
87
1
----
-
u8 → ILM
ADDSP #s10
D
A3
1
----
-
R15+s8 × 4 → R15
EXTSB Ri
E
97-8
1
----
-
exts(Ri[7:0]) → Ri
Sign extension 8 → 32
EXTUB Ri
E
97-9
1
----
-
extu(Ri[7:0]) → Ri
Zero extension8 → 32
EXTSH Ri
E
97-A
1
----
-
exts(Ri[15:0]) → Ri
Sign extension 16 → 32
EXTUH Ri
E
97-B
1
----
-
extu(Ri[15:0]) → Ri
Zero extension16 → 32
LDM0 (reglist)
D
8C
*1
----
-
(R15) → reglist,
R15+4 → R15
Load Multiple
R0 to R7
LDM1 (reglist)
D
8D
*1
----
-
(R15) → reglist,
R15+4 → R15
Load Multiple
R8 to R15
STM0 (reglist)
D
8E
*2
----
-
R15-4 → R15,
reglist → (R15)
Store multiple
R0 to R7
STM1 (reglist)
D
8F
*2
----
-
R15-4 → R15,
reglist → (R15)
Store multiple
R8 to R15
ENTER #u10
D
0F
1+a
----
-
R14 → (R15-4),
R15-4 → R14,
R15-extu(u8 × 4) → R15
Function entry processing
LEAVE
E’
9F-9
b
----
-
R14+4 → R15,
(R15-4) → R14
Function exit processing
XCHB @Rj, Ri
A
8A
2a
----
❍
Ri → TEMP,
extu((Rj)) → Ri,
TEMP → (Rj)
Byte data for semaphore processing
Mnemonic
Operation
Remarks
Sets ILM immediate value
*1: The number of execution cycles for LDM0(reglist) and LDM1(reglist) is a × (n-1) + 1 cycles when "n" is the number of
registers designated.
*2: The number of execution cycles for STM0(reglist)and STM1(reglist) is a × n + 1 when "n" is the number of registers
designated.
• In the ADDSP Instruction, the field s8 in TYPE-D Instruction Format has the following relation to the
value of s10 in assembly notation.
s8 = s10 >> 2
• In the ENTER Instruction, the field u8 in TYPE-D Instruction Format has the following relation to the
value of u10 in assembly notation.
u8 = u10 >> 2
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
637
APPENDIX
MB91461
Table A-15 Resource Instructions
Type
OP
CYC
FLAG
NZVC
LDRES @Ri+, #u4
C
BC
a
----
(Ri) → u4 resource
Ri+=4
u4: Channel number
STRES #u4, @Ri+
C
BD
a
----
u4 resource → (Ri)
Ri+=4
u4: Channel number
Mnemonic
Operation
Remarks
Note:
This series cannot use these instructions because it has no resource with the channel number used for
the resource instructions.
Table A-16 Coprocessor Control Instructions
Type
OP
CYC
FLAG
NZVC
COPOP #u4, #u8, CRj, CRi
E
9F-C
2+a
----
Operation instruction
COPLD
#u4, #u8, Rj, CRi
E
9F-D
1+2a
----
Rj → CRi
COPST
#u4, #u8, CRj, Ri
E
9F-E
1+2a
----
CRj → Ri
COPSV #u4, #u8, CRj, Ri
E
9F-F
1+2a
----
CRj → Ri
Mnemonic
Operation
Remarks
No error trap
Note:
• Since this series has no coprocessor, these instructions cannot be used.
638
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
CM71-10159-2E
0
1
LD @ (R15,
udisp6),Ri
LD @Rj,Ri
3
4
[email protected],Ri
E format
DMOV
@d10,R13
DMOVH @d9, DMOVH
R13
R13, @d 9
DMOVB@ d8, DMOVB
R13
R13, @d 8
DMOV
DMOV
@d10,@–R15 @R15+,@d10
DMOV
DMOV
@d10,@R13+ @R13+,@d10
DMOVH @d9, DMOVH
@R13+
@R13+, @ d9
DMOVB
DMOVB
@d8, @R13+ @R13+, @ d8
ENTER #u10
6
7
8
9
A
B
C
D
E
F
FUJITSU MICROELECTRONICS LIMITED
INT
#u8
DMOV
R13,@d10
E format
STB Ri,@Rj
[email protected],Ri
5
STH Ri,@ Rj
ST Ri,@ Rj
ST Ri,
@(R15,ud6)
LDUH
STH Ri,
@(R13,Rj), Ri @(R13,Rj)
LDUB
STB Ri ,
@(R13,Rj), Ri @(R13,Rj)
1
2
LD @(R13,Rj), ST Ri,
Ri
@(R13,Rj)
0
LD @(R14,
disp10),Ri
2
ST R
@(R14,
disp10)
3
LDUH
@(R14,
disp9),Ri
4
STH
Ri,@(R14,
disp9)
5
LDUB
@(R14,
disp8),Ri
6
8
9
ORCCR
#u8
OR Rj, Ri
BORH
#u4,@Ri
BORL
#u4,@Ri
ANDB
Rj,@Ri
ANDH
Rj,@Ri
STM1
(reglist)
STM0
(reglist)
LDM1
(reglist)
LDM0
(reglist)
MOV Rj,Ri
XCHB
@Rj,Ri
BT STH
#u4,@Ri
A
ASR #u4,Ri
MOV Rs, Ri
LSL Rj,Ri
ASR Rj,Ri
SUBN Rj,Ri
MUL Rj,Ri
E format
MULH Rj,Ri
SUBCRj, Ri STRES
#u4,@Ri+
LDRES
@Ri+,#u4
MULU R j, Ri MULUH
Rj, Ri
CMP Rj,Ri
CMP2 #i4,Ri ASR2
#u4,Ri
CMP #i4,Ri
ADDCRj,Ri
EORB
Rj,@Ri
EORH
Rj,@Ri
LSL #u4,Ri
MOV Ri, Rs
LSR Rj, Ri
LSR2 #u4,Ri
ADD2 #i4,Ri LSL2 #u4,Ri
ADD #i4,Ri
ADDSP
#s10
ADDN Rj,Ri
ADDN2
#i4,Ri
EORRj,@ Ri SUB R j, Ri
LD:20
#i20,Ri
EOR Rj,Ri
BEORH
#u4,@Ri
B
ADDN# i4,Ri LSR #u4,Ri
ORB Rj,@Ri ADD Rj,Ri
ORH
Rj,@Ri
AND Rj,@Ri OR Rj,@Ri
ANDCCR
#u8
AND Rj,Ri
BANDH
#u4,@Ri
BANDL
#u4,@Ri
STILM #u8 E format
STB
Ri,@(R14,
BT STL
BEORL
disp8)
#u4,@Ri
#u4,@Ri
7
Higher 4 bits
LDI:8 #i 8,Ri
C
CALL:D
label12
CALL
label12
D
E
BHI label9
BLS label9
BGT label9
BLE label9
BGE label9
BLT label9
BNV label9
BV label9
BP label9
BN label9
BNC label9
BC label9
BNE label9
BEQ label9
BNO label9
BRA label9
F
BHI:D
label9
BLS:D
label9
BGT:D
label9
BLE:D
label9
BGE:D
label9
BLT:D label9
BNV:D
label9
BV:D
label9
BP:D
label9
BN:D
label9
BNC:D
label9
BC:D
label9
BNE:D
label9
BEQ:D
label9
BNO:D
label9
BRA:D
label9
APPENDIX A Instruction Lists
MB91461
A.3 Instruction Maps
Instruction maps are as follows.
Table A.3-1 illustrates in tabular form 8-bit operation codes (OP) for each instruction. Instructions where
operation code (OP) is less than 8 bits, they have been converted into 8 bit by packing them to MSB side.
Table A.3-1 Instruction MaAp
Lower 4 b its
639
APPENDIX
MB91461
A.4
Instruction Maps of Instruction Format TYPE-E
Instruction Maps of TYPE-E and TYPE-E' instruction formats are illustrated.
Table A.4-1 illustrates in tabular form 8-bit operation codes (OP) and 4-bit sub-operation codes (SUB-OP)
for each instruction.
Table A.4-1 Instruction Map of Instruction Format TYPE-E
Higher 8 bits
Lower 4 bits
07
17
97
9F
0
LD @R15+,Ri
ST Ri,@-R15
JMP @Ri
JMP:D @Ri
1
MOV Ri,PS
MOV PS,Ri
CALL @Ri
CALL:D @Ri
2
-
-
RET
RET:D
3
-
-
RETI
INTE
4
-
-
DIV0S Ri
-
5
-
-
DIV0U Ri
-
6
-
-
DIV1 Ri
DIV3
7
-
-
DIV2 Ri
DIV4S
8
LD @R15+,Rs
ST Rs,@-R15
EXTSB Ri
LDI:32 #i32,Ri
9
LD @R15+,PS
ST PS,@-R15
EXTUB Ri
LEAVE
A
-
-
EXTSH Ri
NOP
B
-
-
EXTUH Ri
COPOP #u4,#CC,CRj,CRi
C
-
-
-
COPLD #u4,#CC,Rj,CRi
D
-
-
-
COPST #u4,#CC,CRj,Ri
E
-
-
-
COPSV #u4,#CC,CRj,Ri
-: Undefined
640
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX B I/O Map
MB91461
APPENDIX B I/O Map
Addresses showed in Table B-1 are allocated to the registers built-in MB91461.
■ How to Read the I/O Map
Address
000000H
+0
PDR0[R/W]B
XXXXXXXX
Register
+2
+1
PDR1 [R/W]B PDR2 [R/W]B
XXXXXXXX
XXXXXXXX
Block
+3
PDR3 [R/W]B T-unit
XXXXXXXX port data
register
Read/write attribute, access unit (B: byte, H: half word, W: word)
Initial value of register after a reset
Register name (The register in column 1 register is at address 4n,
the register in column 2 is at address 4n+1.)
Address of leftmost register (when performing word access,
the register in column 1 is placed at the MSB end.)
Bit value of the register shows initial value by the following way.
"1":
initial value "1"
"0":
initial value "0"
"X": initial value "X"
"−":
CM71-10159-2E
No register exists physically.
FUJITSU MICROELECTRONICS LIMITED
641
APPENDIX
MB91461
Table B-1 I/O Map (1 / 20)
Register
Address
Block
+0
+1
+2
+3
PDR14 [R/W] B,H
----XXXX
PDR15 [R/W] B,H
----XXXX
000000H
Reserved
000004H
Reserved
000008H
Reserved
00000CH
Reserved
000010H
PDR16 [R/W] B,H
X-------
PDR17 [R/W] B,H
XXXXXXXX
PDR18 [R/W] B,H
-----XXX
PDR19 [R/W] B,H
-XXX-XXX
000014H
PDR20 [R/W] B,H
-XXX-XXX
PDR21 [R/W] B,H
-XXX-XXX
PDR22 [R/W] B,H
XXXXXX-X
PDR23 [R/W] B,H
-X-XXXXX
000018H
PDR24 [R/W] B,H
XXXXXXXX
00001CH
PDR28 [R/W] B,H
---XXXXX
R-bus port data register
PDR29 [R/W] B,H
XXXXXXXX
Reserved
000020H
Reserved
000024H
to
00002CH
Reserved
Reserved
000030H
EIRR0 [R/W] B
00000000
ENIR0 [R/W] B
00000000
ELVR0 [R/W] B,H
00000000 00000000
External interrupt
(INT0 to INT7)
NMI
000034H
EIRR1 [R/W] B
00000000
ENIR1 [R/W] B
00000000
ELVR1 [R/W] B,H
00000000 00000000
External interrupt
(INT 8 to INT15 )
000038H
DICR [R/W] B
-------0
HRCL [R/W] B
0--11111
Reserved
Delay interrupt
Reserved
00003CH
642
Reserved
000040H
SCR00 [R/W,W]
B,H,W
00000000
SMR00 [R/W,W]
B,H,W
00000000
000044H
ESCR00 [R/W] B,H
00000X00
ECCR00
[R/W,R,W] B,H
-00000XX
000048H
SCR01 [R/W,W]
B,H,W
00000000
SMR01 [R/W,W]
B,H,W
00000000
00004CH
ESCR01 [R/W] B,H
00000X00
ECCR01
[R/W,R,W] B,H
-00000XX
Reserved
SSR00 [R/W,R]
B,H,W
00001000
RDR00/TDR00
[R/W] B,H,W
00000000
UART (LIN) 0
Reserved
SSR01 [R/W,R]
B,H,W
00001000
RDR01/TDR01
[R/W] B,H,W
00000000
LIN-UART 1
Reserved
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (2 / 20)
Register
Address
Block
+0
+1
+2
+3
000050H
SCR02 [R/W,W]
B,H,W
00000000
SMR02 [R/W,W]
B,H,W
00000000
SSR02 [R/W,R]
B,H,W
00001000
RDR02/TDR02
[R/W] B,H,W
00000000
000054H
ESCR02
[R/W]B,H 00000X00
ECCR02
[R/W,R,W] B,H
-00000XX
000058H
SCR03 [R/W,W]
B,H,W
00000000
SMR03 [R/W,W]
B,H,W
00000000
00005CH
ESCR03
[R/W] B,H
00000X00
ECCR03
[R/W,R,W] B,H
-00000XX
000060H
SCR04 [R/W,W]
B,H,W
00000000
SMR04 [R/W,W]
B,H,W
00000000
SSR04 [R/W,R]
B,H,W
00001000
RDR04/TDR04
[R/W] B,H,W
00000000
000064H
ESCR04 [R/W]
B,H,W
00000X00
ECCR04
[R/W,R,W] B,H,W
-00000XX
FSR04 [R]
B,H,W
---00000
FCR04 [R/W]
B,H,W
0001-000
000068H
SCR05 [R/W,W]
B,H,W
00000000
SMR05 [R/W,W]
B,H,W
00000000
SSR05 [R/W,R]
B,H,W
00001000
RDR05/TDR05
[R/W] B,H,W
00000000
00006CH
ESCR05 [R/W]
B,H,W
00000X00
ECCR05
[R/W,R,W] B,H,W
-00000XX
FSR05 [R]
B,H,W
---00000
FCR05 [R/W]
B,H,W
0001-000
000070H
SCR06 [R/W,W]
B,H,W
00000000
SMR06 [R/W,W]
B,H,W
00000000
SSR06 [R/W,R]
B,H,W
00001000
RDR06/TDR06
[R/W] B,H,W
00000000
000074H
ESCR06 [R/W]
B,H,W
00000X00
ECCR06
[R/W,R,W] B,H,W
-00000XX
FSR06 [R]
B,H,W
---00000
FCR06 [R/W]
B,H,W
0001-000
LIN-UART 2
Reserved
SSR03 [R/W,R]
B,H,W
00001000
RDR03/TDR03
[R/W] B,H,W
00000000
LIN-UART 3
Reserved
LIN-UART 4
LIN-UART 5
LIN-UART 6
000078H
to
00007CH
Reserved
Reserved
000080H
BGR100 [R/W]
B,H,W
00000000
BGR000 [R/W]
B,H,W
00000000
BGR101 [R/W]
B,H,W
00000000
BGR001 [R/W]
B,H,W
00000000
000084H
BGR102 [R/W]
B,H,W
00000000
BGR002 [R/W]
B,H,W
00000000
BGR103 [R/W]
B,H,W
00000000
BGR003 [R/W]
B,H,W
00000000
000088H
BGR104 [R/W]
B,H,W
00000000
BGR004 [R/W]
B,H,W
00000000
BGR105 [R/W]
B,H,W
00000000
BGR005 [R/W]
B,H,W
00000000
00008CH
BGR106 [R/W]
B,H,W
00000000
BGR006 [R/W]
B,H,W
00000000
000090H
to
0000CCH
CM71-10159-2E
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
Baud rate
generator UART (LIN)
0 to 6
Baud rate
generator UART (LIN)
0 to 6
Reserved
643
APPENDIX
MB91461
Table B-1 I/O Map (3 / 20)
Register
Address
0000D0H
0000D4H
Block
+0
+1
IBCR0 [R/W] B,H
00000000
IBSR0 [R] B,H
00000000
ITBAH0 [R/W] B,H ITBAL0 [R/W] B,H
------00
00000000
ISBA0 [R/W] B,H
-0000000
Reserved
Reserved
IDAR0 [R/W] B,H
00000000
0000DCH
IBCR1 [R/W] B,H
00000000
IBSR1 [R] B,H
00000000
0000E4H
+3
ITMKH0 [R/W] B,H ITMKL0 [R/W] B,H ISMK0 [R/W] B,H
00----11
11111111
01111111
0000D8H
0000E0H
ICCR0 [R/W] B
-0011111
ISBA1 [R/W] B,H
-0000000
IDAR1 [R/W] B,H
00000000
Reserved
Reserved
I2C 0
ITBAH1 [R/W] B,H ITBAL1 [R/W] B,H
------00
00000000
ITMKH1 [R/W] B,H ITMKL1 [R/W] B,H ISMK1 [R/W] B,H
00----11
11111111
01111111
0000E8H
to
0000FCH
ICCR1 [R/W] B
-0011111
Reserved
I2C 1
Reserved
000100H
GCN10 [R/W] B,H
00110010 00010000
Reserved
GCN20 [R/W] B
----0000
PPG control
0 to 3
000104H
GCN11 [R/W] B,H
00110010 00010000
Reserved
GCN21 [R/W] B
----0000
PPG control
4 to 7
Reserved
000108H
644
+2
Reserved
000110H
PTMR00 [R] H
11111111 11111111
PCSR00 [W] H
XXXXXXXX XXXXXXXX
000114H
PDUT00 [W] H
XXXXXXXX XXXXXXXX
PCNH00 [R/W] B,H PCNL00 [R/W] B,H
00000000
000000-0
000118H
PTMR01 [R] H
11111111 11111111
PCSR01 [W] H
XXXXXXXX XXXXXXXX
00011CH
PDUT01 [W] H
XXXXXXXX XXXXXXXX
PCNH01 [R/W] B,H PCNL01 [R/W] B,H
00000000
000000-0
000120H
PTMR02 [R] H
11111111 11111111
PCSR02 [W] H
XXXXXXXX XXXXXXXX
000124H
PDUT02 [W] H
XXXXXXXX XXXXXXXX
PCNH02 [R/W] B,H PCNL02 [R/W] B,H
00000000
000000-0
000128H
PTMR03 [R] H
11111111 11111111
PCSR03 [W] H
XXXXXXXX XXXXXXXX
00012CH
PDUT03 [W] H
XXXXXXXX XXXXXXXX
PCNH03 [R/W] B,H PCNL03 [R/W] B,H
00000000
000000-0
000130H
PTMR04 [R] H
11111111 11111111
PCSR04 [W] H
XXXXXXXX XXXXXXXX
000134H
PDUT04 [W] H
XXXXXXXX XXXXXXXX
PCNH04 [R/W] B,H PCNL04 [R/W] B,H
00000000
000000-0
000138H
PTMR05 [R] H
11111111 11111111
PCSR05 [W] H
XXXXXXXX XXXXXXXX
00013CH
PDUT05 [W] H
XXXXXXXX XXXXXXXX
PCNH05 [R/W] B,H PCNL05 [R/W] B,H
00000000
000000-0
FUJITSU MICROELECTRONICS LIMITED
PPG 0
PPG 1
PPG 2
PPG 3
PPG 4
PPG 5
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (4 / 20)
Register
Address
Block
+0
+1
+2
+3
000140H
PTMR06 [R] H
11111111 11111111
PCSR06 [W] H
XXXXXXXX XXXXXXXX
000144H
PDUT06 [W] H
XXXXXXXX XXXXXXXX
PCNH06 [R/W] B,H PCNL06 [R/W] B,H
00000000
000000-0
000148H
PTMR07 [R] H
11111111 11111111
PCSR07 [W] H
XXXXXXXX XXXXXXXX
00014CH
PDUT07 [W] H
XXXXXXXX XXXXXXXX
PCNH07 [R/W] B,H PCNL07 [R/W] B,H
00000000
000000-0
000170H
to
00017CH
000180H
Reserved
ICS01 [R/W] B
00000000
Reserved
Reserved
ICS23 [R/W] B
00000000
IPCP0 [R] H
XXXXXXXX XXXXXXXX
IPCP1 [R] H
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R] H
XXXXXXXX XXXXXXXX
IPCP3 [R] H
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
11101100 00001100
OCS23 [R/W]
11101100 00001100
000190H
OCCP0 [R/W] H
XXXXXXXX XXXXXXXX
OCCP1 [R/W] H
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W] H
XXXXXXXX XXXXXXXX
OCCP3 [R/W] H
XXXXXXXX XXXXXXXX
0001A0H
Reserved
ADERH [R/W] B,H,W
00000000 00000000
ADCS0 [R/W] B,H
00000000
0001A8H
ADCT1 [R/W] B,H ADCT0 [R/W] B,H ADSCH [R/W] B,H ADECH [R/W] B,H
00010000
00101100
---00000
---00000
0001ACH
Reserved
0001B4H
Reserved
0001B8H
TMRLR1 [W] H
XXXXXXXX XXXXXXXX
0001BCH
CM71-10159-2E
Reserved
Output compare
0 to 3
ADERL [R/W] B,H,W
00000000 00000000
ADCS1 [R/W] B,H
00000000
TMRLR0 [W] H
XXXXXXXX XXXXXXXX
Input capture
0 to 3
Reserved
0001A4H
0001B0H
PPG 7
Reserved
000184H
000198H
to
00019CH
PGG 6
ADCR1 [R] B,H
000000XX
ADCR0 [R] B,H
XXXXXXXX
A/D converter
Reserved
TMR0 [R] H
XXXXXXXX XXXXXXXX
TMCSRC0 [R/W]
B,H
---00000
TMCSRC0 [R/W]
B,H
0-000000
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSRC1 [R/W]
B,H
---00000
TMCSRC1 [R/W]
B,H
0-000000
FUJITSU MICROELECTRONICS LIMITED
Reload timer 0
(PPG 0, 1)
Reload timer 1
(PPG 2, 3)
645
APPENDIX
MB91461
Table B-1 I/O Map (5 / 20)
Register
Address
Block
+0
0001C0H
+1
TMRLR2 [W] H
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W] H
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
to
0001E4H
0001E8H
646
+2
+3
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSRC2 [R/W]
B,H
---00000
TMCSRC2 [R/W]
B,H
0-000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSRC3 [R/W]
B,H
---00000
TMCSRC3 [R/W]
B,H
0-000000
Reserved
TMRLR7 [W] H
XXXXXXXX XXXXXXXX
Reload timer 2
(PPG 4, 5)
Reload timer 3
(PPG 6, 7)
Reserved
TMR7 [R] H
XXXXXXXX XXXXXXXX
TMCSRC7 [R/W]
B,H
0-000000
Reload timer 7
(A/D converter)
0001ECH
Reserved
TMCSRC7 [R/W]
B,H
---00000
0001F0H
TCDT0 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
-0000000
Free-run timer 0
(ICU 0, 1)
0001F4H
TCDT1 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
-0000000
Free-run timer 1
(ICU 2, 3)
0001F8H
TCDT2 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
-0000000
Free-run timer 2
(OCU 0, 1)
0001FCH
TCDT3 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
-0000000
Free-run timer 3
(OCU 2, 3)
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (6 / 20)
Register
Address
Block
+0
+1
+2
+3
000200H
DMACA0 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
B,H,W
00--0000
Reserved
000244H
to
000254H
Reserved
000258H
to
000364H
Reserved
000368H
00036CH
000370H
Reserved
IBCR2 [R/W] B,H
00000000
IBSR2 [R] B,H
00000000
ITBAH2 [R/W] B,H ITBAL2 [R/W] B,H
------00
00000000
ITMKH2 [R/W] B,H ITMKL2 [R/W] B,H ISMK2 [R/W] B,H
00----11
11111111
01111111
ISBA2 [R/W] B,H
-0000000
IDAR2 [R/W] B,H
00000000
Reserved
Reserved
ICCR2 [R/W] B
-0011111
000374H
to
0003BCH
Reserved
0003C0H
Reserved
0003C4H
0003D0H
CM71-10159-2E
DMAC
I2C 2
Reserved
ISIZE [R/W] B
------11
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
Instruction cache
Reserved
647
APPENDIX
MB91461
Table B-1 I/O Map (7 / 20)
Register
Address
Block
+0
0003E4H
648
+1
+2
+3
ICHRC [R/W] B
0-000000
Reserved
0003E8H
to
0003ECH
Reserved
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
000440H
ICR00 [R/W] B,H,W ICR01 [R/W] B,H,W ICR02 [R/W] B,H,W ICR03 [R/W] B,H,W
---11111
---11111
---11111
---11111
000444H
ICR04 [R/W] B,H,W ICR05 [R/W] B,H,W ICR06 [R/W] B,H,W ICR07 [R/W] B,H,W
---11111
---11111
---11111
---11111
000448H
ICR08 [R/W] B,H,W ICR09 [R/W] B,H,W
---11111
---11111
00044CH
ICR12 [R/W] B,H,W ICR13 [R/W] B,H,W
---11111
---11111
Instruction cache
Reserved
Bit search module
Reserved
Reserved
ICR11 [R/W] B,H,W
---11111
Interrupt
controller
Reserved
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (8 / 20)
Register
Address
Block
+0
+1
+2
+3
000450H
ICR16 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
000454H
ICR20 [R/W] B,H,W ICR21 [R/W] B,H,W ICR22 [R/W] B,H,W ICR23 [R/W] B,H,W
---11111
---11111
---11111
---11111
Reserved
000458H
Reserved
ICR25 [R/W] B,H,W ICR26 [R/W] B,H,W ICR27 [R/W] B,H,W
---11111
---11111
---11111
00045CH
Reserved
ICR29 [R/W] B,H,W
---11111
000460H
Reserved
Reserved
000464H
Reserved
000468H
Reserved
ICR38 [R/W] B,H,W ICR39 [R/W] B,H,W
---11111
---11111
ICR42 [R/W] B,H,W ICR43 [R/W] B,H,W
---11111
---11111
00046CH
Reserved
000470H
ICR48 [R/W] B,H,W ICR49 [R/W] B,H,W ICR50 [R/W] B,H,W ICR51 [R/W] B,H,W
---11111
---11111
---11111
---11111
000474H
Reserved
000478H
Reserved
ICR58 [R/W] B,H,W ICR59 [R/W] B,H,W
---11111
---11111
00047CH
Reserved
ICR62 [R/W] B,H,W ICR63 [R/W] B,H,W
---11111
---11111
000480H
RSRR [R/W] B,H,W STCR [R/W] B,H,W TBCR [R/W] B,H,W CTBR [W] B,H,W
10000000
00110011
X0000X00
XXXXXXXX
000484H
CLKR [R/W] B,H,W
00000000
DIVR0 [R/W]
B,H,W
00000011
PLLDIVM [R/W]
B,H
---00000
PLLDIVN [R/W]
B,H
---00000
000490H
Reserved
000494H
to
00049CH
Reserved
CM71-10159-2E
DIVR1 [R/W]
B,H,W
00000000
Reserved
000488H
00048CH
WPR [W] B,H,W
XXXXXXXX
Interrupt
controller
Clock control
Reserved
Reserved
PLL interface
Reserved
FUJITSU MICROELECTRONICS LIMITED
649
APPENDIX
MB91461
Table B-1 I/O Map (9 / 20)
Register
Address
Block
+0
+1
0004A0H
Reserved
WTCER [R/W] B,H
------00
0004A4H
Reserved
0004A8H
WTHR [R/W] B,H
---XXXXX
WTMR [R/W] B,H
--XXXXXX
WTSR [R/W] B
--XXXXXX
CANPRE [R/W] B,H
00000000
CAN
(clock control)
HWDCS [R/W,W] B
00011000
Reserved
Reserved
0004D0H
Reserved
0004D8H
Reserved
Reserved
OSCR [R/W] B,H
00---000
Real-time clock
Reserved
Reserved
0004CCH
0004D4H
Hardware
watchdog
Interval timer
Reserved
SHDE [R/W] B
0-------
Reserved
EXTE [R/W] B,H
00000000
EXTLV [R/W] B,H
00000000 00000000
0004DCH
to
00063CH
650
WTCR [R/W] B,H
00000000 000-00-0
Reserved
0004C4H
0004C8H
+3
WTBR [R/W] B, B,H
---XXXXX XXXXXXXX XXXXXXXX
0004ACH
to
0004BCH
0004C0H
+2
EXTF [R/W] B,H
00000000
Reserved
Reserved
Shutdown
controller
Reserved
000640H
ASR0 [R/W] B,H,W
00000000 00000000
ACR0*2 [R/W] B,H,W
1111XX00 00000000
000644H
ASR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
FUJITSU MICROELECTRONICS LIMITED
External bus
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (10 / 20)
Register
Address
Block
+0
000650H
+1
+2
ASR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
+3
ACR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
Reserved
000654H
000658H
Reserved
00065CH
Reserved
000660H
AWR0 [R/W] B,H,W
01111111 11111011
AWR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
Reserved
00066CH
Reserved
000670H
Reserved
000674H
000678H
Reserved
IOWR0 [R/W]
B,H,W
XXXXXXXX
IOWR1 [R/W]
B,H,W
XXXXXXXX
00067CH
000680H
IOWR2 [R/W]
B,H,W
XXXXXXXX
CSER [R/W] B,H,W CHER [R/W] B,H,W
00000001
11111111
000688H
to
0007F8H
Reserved
MODR [W] B
XXXXXXXX
Reserved
Reserved
000800H
to
000CFCH
Reserved
000D00H
Reserved
000D04H
Reserved
000D08H
Reserved
000D10H
CM71-10159-2E
Reserved
PDRD16 [R] B,H
X-------
PDRD17 [R] B,H
XXXXXXXX
TCR [R/W]*3
B,H,W
0000XXXX
Reserved
Reserved
000D0CH
Reserved
Reserved
000684H
0007FCH
External bus
Mode register
Reserved
R-bus port data
direct read register
PDRD14 [R] B,H
----XXXX
PDRD15 [R] B,H
----XXXX
PDRD18 [R] B,H
-----XXX
PDRD19 [R] B,H
-XXX-XXX
FUJITSU MICROELECTRONICS LIMITED
651
APPENDIX
MB91461
Table B-1 I/O Map (11 / 20)
Register
Address
+1
+2
+3
000D14H
PDRD20 [R] B,H
-XXX-XXX
PDRD21 [R] B,H
-XXX-XXX
PDRD22 [R] B,H
XXXXXX-X
PDRD23 [R] B,H
-X-XXXXX
000D18H
PDRD24 [R] B,H
XXXXXXXX
000D1CH
PDRD28 [R] B,H
---XXXXX
Reserved
PDRD29 [R] B,H
XXXXXXXX
Reserved
000D20H
Reserved
000D24H
to
000D3CH
Reserved
000D40H
Reserved
000D44H
Reserved
000D48H
Reserved
000D4CH
Reserved
DDR14 [R/W] B,H
----0000
DDR15 [R/W] B,H
----0000
DDR16 [R/W] B,H
0-------
DDR17 [R/W] B,H
00000000
DDR18 [R/W] B,H
-----000
DDR19 [R/W] B,H
-000-000
000D54H
DDR20 [R/W] B,H
-000-000
DDR21 [R/W] B,H
-000-000
DDR22 [R/W] B,H
000000-0
DDR23 [R/W] B,H
-0-00000
000D58H
DDR24 [R/W] B,H
---00000
000D5CH
DDR28 [R/W] B,H
---00000
DDR29 [R/W] B,H
00000000
Reserved
Reserved
000D64H
to
000D7CH
Reserved
000D80H
Reserved
000D84H
Reserved
000D88H
Reserved
Reserved
PFR16 [R/W] B,H
0-------
R-bus port
direction register
Reserved
000D60H
000D90H
R-bus port data
direct read register
Reserved
000D50H
000D8CH
652
Block
+0
PFR17 [R/W] B,H
00000000
Reserved
R-bus port function register
PFR14 [R/W] B,H
----0000
PFR15 [R/W] B,H
----0000
PFR18 [R/W] B,H
-----000
PFR19 [R/W] B,H
-000-000
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (12 / 20)
Register
Address
Block
+0
+1
+2
+3
000D94H
PFR20 [R/W] B,H
-000-000
PFR21 [R/W] B,H
-000-000
PFR22 [R/W] B,H
000000-0
PFR23 [R/W] B,H
-0-00000
000D98H
PFR24 [R/W] B,H
00000000
Reserved
Reserved
Reserved
000D9CH
PFR28 [R/W] B,H
---00000
PFR29 [R/W] B,H
00000000
R-bus port function register
Reserved
000DA0H
Reserved
000DA4H
to
000DBCH
Reserved
000DC0H
Reserved
000DC4H
Reserved
000DC8H
Reserved
000DCCH
Reserved
Reserved
EPFR14 [R/W] B,H EPFR15 [R/W] B,H
----0000
----0000
Reserved
000DD0H
EPFR16 [R/W] B,H EPFR17 [R/W] B,H EPFR18 [R/W] B,H EPFR19 [R/W] B,H
0------00000000
-----000
-000-000
000DD4H
EPFR20 [R/W] B,H EPFR21 [R/W] B,H EPFR22 [R/W] B,H EPFR23 [R/W] B,H
-000-000
-000-000
000000-0
-0-00000
000DD8H
EPFR24 [R/W] B,H
00000000
000DDCH
EPFR28 [R/W] B,H EPFR29 [R/W] B,H
---00000
00000000
Reserved
000DE0H
Reserved
000DE4H
to
000DFCH
Reserved
000E00H
to
000E3CH
Reserved
CM71-10159-2E
R-bus expansion port
function
register
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
653
APPENDIX
MB91461
Table B-1 I/O Map (13 / 20)
Register
Address
Block
+0
+2
+3
PILR14 [R/W] B,H
----0000
PILR15 [R/W] B,H
----0000
000E40H
Reserved
000E44H
Reserved
000E48H
Reserved
000E4CH
Reserved
000E50H
PILR16 [R/W] B,H
0-------
PILR17 [R/W] B,H
00000000
PILR18 [R/W] B,H
-----000
PILR19 [R/W] B,H
-000-000
000E54H
PILR20 [R/W] B,H
-000-000
PILR21 [R/W] B,H
-000-000
PILR22 [R/W] B,H
000000-0
PILR23 [R/W] B,H
-0-00000
000E58H
PILR24 [R/W] B,H
00000000
000E5CH
PILR28 [R/W] B,H
---00000
R-bus pin input
level selection
register
Reserved
PILR29 [R/W] B,H
00000000
Reserved
000E60H
to
000EBCH
Reserved
000EC0H
Reserved
000EC4H
Reserved
000EC8H
Reserved
000ECCH
654
+1
PPER14 [R/W] B,H PPER15 [R/W] B,H
----0000
----0000
Reserved
000ED0H
PPER16 [R/W] B,H PPER17 [R/W] B,H PPER18 [R/W] B,H PPER19 [R/W] B,H
0------00000000
-----000
-000-000
000ED4H
PPER20 [R/W] B,H PPER21 [R/W] B,H PPER22 [R/W] B,H PPER23 [R/W] B,H
-000-000
-000-000
000000-0
-0-00000
000ED8H
PPER24 [R/W] B,H
00000000
000EDCH
PPER28 [R/W] B,H PPER29 [R/W] B,H
---00000
00000000
R-bus port
pull-up/pull-down
enable register
Reserved
000EE0H
Reserved
000EE4H
to
000EFCH
Reserved
Reserved
FUJITSU MICROELECTRONICS LIMITED
Reserved
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (14 / 20)
Register
Address
Block
+0
+1
+2
000F00H
Reserved
000F04H
Reserved
000F08H
Reserved
000F0CH
+3
PPCR14 [R/W] B,H PPCR15 [R/W] B,H
----1111
----1111
Reserved
000F10H
PPCR16 [R/W] B,H PPCR17 [R/W] B,H PPCR18 [R/W] B,H PPCR19 [R/W] B,H
1-------111-111
111111-1
-1-11111
000F14H
PPCR20 [R/W] B,H PPCR21 [R/W] B,H PPCR22 [R/W] B,H PPCR23 [R/W] B,H
-111-111
-111-111
111111-1
-1-11111
000F18H
PPCR24 [R/W] B,H
---11111
000F1CH
PPCR28 [R/W] B,H PPCR29 [R/W] B,H
---11111
11111111
Reserved
Reserved
000F20H
Reserved
000F24H
to
000F3CH
Reserved
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
007FFCH
Reserved
008000H
to 00BFFCH
Reserved
CM71-10159-2E
R-bus port
pull-up/pull-down
control register
Reserved
DMAC
DMAC
Reserved
FUJITSU MICROELECTRONICS LIMITED
655
APPENDIX
MB91461
Table B-1 I/O Map (15 / 20)
Register
Address
Block
+0
+1
+3
00C000H
CTRLR0 [R/W] B,H
00000000 00000001
STATR0 [R/W] B,H
00000000 00000000
00C004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0 [R/W] B,H,W
00100011 00000001
00C008H
INTR0 [R]B,H,W
00000000 00000000
TESTR0 [R/W]B,H,W
00000000 X0000000
00C00CH
BRPE0 [R/W]B,H,W
00000000 00000000
Reserved
00C010H
IF1CREQ0 [R/W] B,H
00000000 00000001
IF1CMSK0 [R/W] B,H
00000000 00000000
00C014H
IF1MSK20 [R/W] B,H,W
11111111 11111111
IF1MSK10 [R/W] B,H,W
11111111 11111111
00C018H
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1ARB10 [R/W] B,H,W
00000000 00000000
00C01CH
IF1MCTR0 [R/W] B,H,W
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTA20 [R/W] B,H,W
00000000 00000000
00C024H
IF1DTB10 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W]B,H,W
00000000 00000000
00C028H
to
00C02CH
CAN 0 control
register
CAN 0 IF 1
register
Reserved
00C030H
IF1DTA20 [R/W] B,H,W
00000000 00000000
IF1DTA10 [R/W] B,H,W
00000000 00000000
00C034H
IF1DTB20 [R/W] B,H,W
00000000 00000000
IF1DTB10 [R/W] B,H,W
00000000 00000000
00C038H
to
00C03CH
656
+2
Reserved
FUJITSU MICROELECTRONICS LIMITED
CAN 0 IF 1
register
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (16 / 20)
Register
Address
Block
+0
+1
+2
+3
00C040H
IF2CREQ0 [R/W] B,H
00000000 00000001
IF2CMSK0 [R/W] B,H
00000000 00000000
00C044H
IF2MSK20 [R/W] B,H,W
11111111 11111111
IF2MSK10 [R/W] B,H,W
11111111 11111111
00C048H
IF2ARB20 [R/W] B,H,W
00000000 00000000
IF2ARB10 [R/W] B,H,W
00000000 00000000
00C04CH
IF2MCTR0 [R/W] B,H,W
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W] B,H,W
00000000 00000000
IF2DTA20 [R/W] B,H,W
00000000 00000000
IF2DTB10 [R/W] B,H,W
00000000 00000000
IF2DTB20 [R/W] B,H,W
00000000 00000000
00C054H
00C058H
to
00C05CH
Reserved
00C060H
IF2DTA20 [R/W] B,H,W
00000000 00000000
IF2DTA10 [R/W] B,H,W
00000000 00000000
00C064H
IF2DTB20 [R/W] B,H,W
00000000 00000000
IF2DTB10 [R/W] B,H,W
00000000 00000000
00C068H
to
00C07CH
00C080H
Reserved
TREQR20 [R] B,H,W
00000000 00000000
TREQR10 [R] B,H,W
00000000 00000000
00C084H
Reserved
00C088H
Reserved
00C08CH
Reserved
00C090H
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
00C094H
Reserved
00C098H
Reserved
00C09CH
Reserved
CM71-10159-2E
CAN 0 IF 2
register
FUJITSU MICROELECTRONICS LIMITED
CAN 0
status flag
657
APPENDIX
MB91461
Table B-1 I/O Map (17 / 20)
Register
Address
Block
+0
00C0A0H
+2
INTPND20 [R] B,H,W
00000000 00000000
+3
INTPND10 [R] B,H,W
00000000 00000000
00C0A4H
Reserved
00C0A8H
Reserved
00C0ACH
Reserved
00C0B0H
658
+1
MSGVAL20 [R] B,H,W
00000000 00000000
MSGVAL10 [R] B,H,W
00000000 00000000
00C0B4H
Reserved
00C0B8H
Reserved
00C0BCH
Reserved
00C0C0H
to
00C0FCH
Reserved
00C100H
CTRLR1 [R/W] B,H
00000000 00000001
STATR1 [R/W] B,H
00000000 00000000
00C104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1 [R/W] B,H,W
00100011 00000001
00C108H
INTR1 [R] B,H,W
00000000 00000000
TESTR1 [R/W] B,H,W
00000000 X0000000
00C10CH
BRPE1 [R/W] B,H,W
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W] B,H
00000000 00000001
IF1CMSK1 [R/W] B,H
00000000 00000000
00C114H
IF1MSK21 [R/W] B,H,W
11111111 11111111
IF1MSK11 [R/W] B,H,W
11111111 11111111
00C118H
IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1ARB11 [R/W] B,H,W
00000000 00000000
00C11CH
IF1MCTR1 [R/W] B,H,W
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTA21 [R/W] B,H,W
00000000 00000000
00C124H
IF1DTB11 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
FUJITSU MICROELECTRONICS LIMITED
CAN 0
status flag
CAN 1
control register
CAN 1 IF 1
register
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (18 / 20)
Register
Address
Block
+0
+1
00C128H
to
00C12CH
+2
+3
Reserved
00C130H
IF1DTA21 [R/W] B,H,W
00000000 00000000
IF1DTA11 [R/W] B,H,W
00000000 00000000
00C134H
IF1DTB21 [R/W] B,H,W
00000000 00000000
IF1DTB11 [R/W] B,H,W
00000000 00000000
00C138H
to
00C13CH
Reserved
00C140H
IF2CREQ1 [R/W]B,H
00000000 00000001
IF2CMSK1 [R/W]B,H
00000000 00000000
00C144H
IF2MSK21 [R/W]B,H,W
11111111 11111111
IF2MSK11 [R/W]B,H,W
11111111 11111111
00C148H
IF2ARB21 [R/W]B,H,W
00000000 00000000
IF2ARB11 [R/W]B,H,W
00000000 00000000
00C14CH
IF2MCTR1 [R/W]B,H,W
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]B,H,W
00000000 00000000
IF2DTA21 [R/W]B,H,W
00000000 00000000
00C154H
IF2DTB11 [R/W]B,H,W
00000000 00000000
IF2DTB21 [R/W]B,H,W
00000000 00000000
00C158H
to
00C15CH
IF2DTA21 [R/W]B,H,W
00000000 00000000
IF2DTA11 [R/W]B,H,W
00000000 00000000
00C164H
IF2DTB21 [R/W]B,H,W
00000000 00000000
IF2DTB11 [R/W]B,H,W
00000000 00000000
00C168H
to
00C17CH
00C184H
CAN 1 IF 2
register
Reserved
00C160H
00C180H
CAN 1 IF 1
register
Reserved
TREQR21 [R]B,H,W
00000000 00000000
TREQR11 [R]B,H,W
00000000 00000000
Reserved
CAN 1
status flag
00C188H
Reserved
00C18CH
Reserved
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
659
APPENDIX
MB91461
Table B-1 I/O Map (19 / 20)
Register
Address
Block
+0
00C190H
+2
NEWDT21 [R]B,H,W
00000000 00000000
Reserved
00C198H
Reserved
00C19CH
Reserved
INTPND21 [R]B,H,W
00000000 00000000
INTPND11 [R]B,H,W
00000000 00000000
00C1A4H
Reserved
00C1A8H
Reserved
00C1ACH
Reserved
00C1B0H
+3
NEWDT11 [R]B,H,W
00000000 00000000
00C194H
00C1A0H
660
+1
MSGVAL21 [R]B,H,W
00000000 00000000
CAN 1
status flag
MSGVAL11 [R]B,H,W
00000000 00000000
00C1B4H
Reserved
00C1B8H
Reserved
00C1BCH
Reserved
00C1C0H
to
00C1FCH
Reserved
00F000H
to
00FFFCH
Reserved
010000H
to
013FFCH
Cache TAG way 1 (010000H to 0107FCH)
014000H
to
017FFCH
Cache TAG way 2 (014000H to 0147FCH)
Reserved
Instruction cache
018000H
to
01BFFCH
Cache RAM way 1 (018000H to 0187FCH)
01C000H
to
01FFFCH
Cache RAM way 2 (01C000H to 01C7FCH)
020000H
to
02FFFCH
Reserved
FUJITSU MICROELECTRONICS LIMITED
Reserved
CM71-10159-2E
APPENDIX B I/O Map
MB91461
Table B-1 I/O Map (20 / 20)
Register
Address
Block
+0
+1
+2
030000H
to
03FFFCH
I/D-RAM: 64 Kbytes
(instruction access is 0 wait cycle, data access is 1 wait cycle)
040000H
to
07FFFCH
External memory area (256 Kbytes)
080000H
to
0BFFFCH
External memory area (256 Kbytes)
0C0000H
to
0FFFF4H
External memory area (256 Kbytes)
0FFFF8H
FMV [R]
0FFFFCH
FRV [R]
100000H
to
13FFFCH
External memory area (256 Kbytes)
140000H
to
17FFFCH
External memory area (256 Kbytes)
180000H
to
1BFFFCH
External memory area (256 Kbytes)
1C0000H
to
1FFFFCH
External memory area (256 Kbytes)
200000H
to
2FFFFCH
External memory area (1 Mbyte)
300000H
to
3FFFFCH
External memory area (1 Mbyte)
+3
I/D-RAM
64 Kbytes
External bus
Reset vector/
mode vector
External bus
*1 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2 : ACR0[11:10] depends on the mode vector fetch information on bus width.
*3 : TCR[3:0] INIT value = 0000, the value is kept after RST.
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
661
APPENDIX
MB91461
APPENDIX C Interrupt Vector
The interrupt vector table lists the interrupt sources with their corresponding jump
address (vector address) and interrupt control registers (ICR00 to ICR63) assigned to
each MB91461 interrupt.
Table C-1 Interrupt Vector (1 / 6)
Interrupt number
Interrupt source
HexaDecimal
decimal
Interrupt level
Setting
register
Register
address
Offset
TBR default
address
Resource
Number *1
Reset
0
00H
⎯
⎯
3FCH
000FFFFCH
2
Mode vector
1
01H
⎯
⎯
3F8H
000FFFF8H
3
System reserved
2
02H
⎯
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03H
⎯
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04H
⎯
⎯
3ECH
000FFFECH
⎯
System reserved
5
05H
⎯
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06H
⎯
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07H
⎯
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08H
⎯
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09H
⎯
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0AH
⎯
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0BH
⎯
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0CH
⎯
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0DH
⎯
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0EH
⎯
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0FH
15 (0FH)
Fixed
15 (0FH)
Fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10H
440H
3BCH
000FFFBCH
⎯
ICR00
3B8H
000FFFB8H
⎯
3B4H
000FFFB4H
⎯
3B0H
000FFFB0H
⎯
External interrupt 1
17
11H
External interrupt 2
18
12H
ICR01
External interrupt 3
662
19
13H
441H
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX C Interrupt Vector
MB91461
Table C-1 Interrupt Vector (2 / 6)
Interrupt number
Interrupt source
External interrupt 4
HexaDecimal
decimal
20
Interrupt level
Setting
register
Register
address
ICR02
442H
14H
External interrupt 5
21
15H
External interrupt 6
22
16H
ICR03
External interrupt 7
23
17H
External interrupt 8
24
18H
ICR04
External interrupt 9
25
19H
External interrupt 10
26
1AH
ICR05
External interrupt 11
27
1BH
External interrupt 12
28
1CH
ICR06
External interrupt 13
29
1DH
External interrupt 14
30
1EH
ICR07
External interrupt 15
31
1FH
Reload timer 0
32
20H
ICR08
Reload timer 1
33
21H
Reload timer 2
34
22H
ICR09
Reload timer 3
35
23H
System reserved
36
24H
ICR10
System reserved
37
25H
System reserved
38
26H
ICR11
Reload timer 7
39
27H
Free-run timer 0
40
28H
ICR12
Free-run timer 1
41
29H
Free-run timer 2
42
2AH
ICR13
Free-run timer 3
43
2BH
System reserved
44
2CH
ICR14
System reserved
45
2DH
System reserved
46
2EH
ICR15
System reserved
CM71-10159-2E
47
2FH
443H
444H
445H
446H
447H
448H
449H
44AH
44BH
44CH
44DH
44EH
44FH
Offset
TBR default
address
Resource
Number *1
3ACH
000FFFACH
⎯
3A8H
000FFFA8H
⎯
3A4H
000FFFA4H
⎯
3A0H
000FFFA0H
⎯
39CH
000FFF9CH
⎯
398H
000FFF98H
⎯
394H
000FFF94H
⎯
390H
000FFF90H
⎯
38CH
000FFF8CH
⎯
388H
000FFF88H
⎯
384H
000FFF84H
⎯
380H
000FFF80H
⎯
37CH
000FFF7CH
4
378H
000FFF78H
5
374H
000FFF74H
⎯
370H
000FFF70H
⎯
36CH
000FFF6CH
⎯
368H
000FFF68H
⎯
364H
000FFF64H
⎯
360H
000FFF60H
⎯
35CH
000FFF5CH
⎯
358H
000FFF58H
⎯
354H
000FFF54H
⎯
350H
000FFF50H
⎯
34CH
000FFF4CH
⎯
348H
000FFF48H
⎯
344H
000FFF44H
⎯
340H
000FFF40H
⎯
FUJITSU MICROELECTRONICS LIMITED
663
APPENDIX
MB91461
Table C-1 Interrupt Vector (3 / 6)
Interrupt number
Interrupt source
CAN0
HexaDecimal
decimal
48
Interrupt level
Setting
register
Register
address
ICR16
450H
30H
CAN1
49
31H
System reserved
50
32H
ICR17
System reserved
51
33H
System reserved
52
34H
ICR18
System reserved
53
35H
LIN-USART 0 RX
54
36H
ICR19
LIN-USART 0 TX
55
37H
LIN-USART 1 RX
56
38H
ICR20
LIN-USART 1 TX
57
39H
LIN-USART 2 RX
58
3AH
ICR21
LIN-USART 2 TX
59
3BH
LIN-USART 3 RX
60
3CH
ICR22
LIN-USART 3 TX
61
3DH
System reserved
62
3EH
Delay interrupt
63
3FH
System reserved*2
64
40H
System reserved*2
65
41H
LIN-USART 4 RX
66
42H
67
43H
LIN-USART 5 RX
68
44H
69
45H
LIN-USART 6 RX
70
46H
71
47H
System reserved
72
48H
73
49H
I2C_0/I2C_2
74
4AH
ICR29
I2C_1
664
75
4BH
455H
456H
458H
ICR28
System reserved
454H
(ICR24)
ICR27
LIN-USART 6 TX
453H
457H
ICR26
LIN-USART 5 TX
452H
ICR23*3
ICR25
LIN-USART 4 TX
451H
459H
45AH
45BH
45CH
45DH
FUJITSU MICROELECTRONICS LIMITED
Offset
TBR default
address
Resource
Number *1
33CH
000FFF3CH
⎯
338H
000FFF38H
⎯
334H
000FFF34H
⎯
330H
000FFF30H
⎯
32CH
000FFF2CH
⎯
328H
000FFF28H
⎯
324H
000FFF24H
6
320H
000FFF20H
7
31CH
000FFF1CH
8
318H
000FFF18H
9
314H
000FFF14H
⎯
310H
000FFF10H
⎯
30CH
000FFF0CH
⎯
308H
000FFF08H
⎯
304H
000FFF04H
⎯
300H
000FFF00H
⎯
2FCH
000FFEFCH
⎯
2F8H
000FFEF8H
⎯
2F4H
000FFEF4H
10
2F0H
000FFEF0H
11
2ECH
000FFEECH
12
2E8H
000FFEE8H
13
2E4H
000FFEE4H
⎯
2E0H
000FFEE0H
⎯
2DCH
000FFEDCH
⎯
2D8H
000FFED8H
⎯
2D4H
000FFED4H
⎯
2D0H
000FFED0H
⎯
CM71-10159-2E
APPENDIX C Interrupt Vector
MB91461
Table C-1 Interrupt Vector (4 / 6)
Interrupt number
Interrupt source
System reserved
HexaDecimal
decimal
76
Interrupt level
Setting
register
Register
address
ICR30
45EH
4CH
System reserved
77
4DH
System reserved
78
4EH
ICR31
System reserved
79
4FH
System reserved
80
50H
ICR32
System reserved
81
51H
System reserved
82
52H
ICR33
System reserved
83
53H
System reserved
84
54H
ICR34
System reserved
85
55H
System reserved
86
56H
ICR35
System reserved
87
57H
System reserved
88
58H
ICR36
System reserved
89
59H
System reserved
90
5AH
ICR37
System reserved
91
5BH
Input capture 0
92
5CH
ICR38
Input capture 1
93
5DH
Input capture 2
94
5EH
ICR39
Input capture 3
95
5FH
System reserved
96
60H
ICR40
System reserved
97
61H
System reserved
98
62H
ICR41
System reserved
99
63H
Output compare 0
100
64H
ICR42
Output compare 1
101
65H
Output compare 2
102
66H
ICR43
Output compare 3
CM71-10159-2E
103
67H
45FH
460H
461H
462H
463H
464H
465H
466H
467H
468H
469H
46AH
46BH
Offset
TBR default
address
Resource
Number *1
2CCH
000FFECCH
⎯
2C8H
000FFEC8H
⎯
2C4H
000FFEC4H
⎯
2C0H
000FFEC0H
⎯
2BCH
000FFEBCH
⎯
2B8H
000FFEB8H
⎯
2B4H
000FFEB4H
⎯
2B0H
000FFEB0H
⎯
2ACH
000FFEACH
⎯
2A8H
000FFEA8H
⎯
2A4H
000FFEA4H
⎯
2A0H
000FFEA0H
⎯
29CH
000FFE9CH
⎯
298H
000FFE98H
⎯
294H
000FFE94H
⎯
290H
000FFE90H
⎯
28CH
000FFE8CH
⎯
288H
000FFE88H
⎯
284H
000FFE84H
⎯
280H
000FFE80H
⎯
27CH
000FFE7CH
⎯
278H
000FFE78H
⎯
274H
000FFE74H
⎯
270H
000FFE70H
⎯
26CH
000FFE6CH
⎯
268H
000FFE68H
⎯
264H
000FFE64H
⎯
260H
000FFE60H
⎯
FUJITSU MICROELECTRONICS LIMITED
665
APPENDIX
MB91461
Table C-1 Interrupt Vector (5 / 6)
Interrupt number
Interrupt source
System reserved
HexaDecimal
decimal
104
Interrupt level
Setting
register
Register
address
ICR44
46CH
68H
System reserved
105
69H
System reserved
106
6AH
ICR45
System reserved
107
6BH
System reserved
108
6CH
ICR46
System reserved
109
6DH
System reserved
110
6EH
System reserved
111
6FH
PPG0
112
70H
PPG1
113
71H
PPG2
114
72H
115
73H
PPG4
116
74H
46FH
ICR48
470H
ICR50
PPG5
117
75H
PPG6
118
76H
ICR51
PPG7
119
77H
System reserved
120
78H
ICR52
System reserved
121
79H
System reserved
122
7AH
ICR53
System reserved
123
7BH
System reserved
124
7CH
ICR54
System reserved
125
7DH
System reserved
126
7EH
ICR55
System reserved
127
7FH
System reserved
128
80H
ICR56
System reserved
129
81H
System reserved
130
82H
ICR57
System reserved
666
131
83H
46EH
ICR47*3
ICR49
PPG3
46DH
471H
472H
473H
474H
475H
476H
477H
478H
479H
FUJITSU MICROELECTRONICS LIMITED
Offset
TBR default
address
Resource
Number *1
25CH
000FFE5CH
⎯
258H
000FFE58H
⎯
254H
000FFE54H
⎯
250H
000FFE50H
⎯
24CH
000FFE4CH
⎯
248H
000FFE48H
⎯
244H
000FFE44H
⎯
240H
000FFE40H
⎯
23CH
000FFE3CH
15
238H
000FFE38H
⎯
234H
000FFE34H
⎯
230H
000FFE30H
⎯
22CH
000FFE2CH
⎯
228H
000FFE28H
⎯
224H
000FFE24H
⎯
220H
000FFE20H
⎯
21CH
000FFE1CH
⎯
218H
000FFE18H
⎯
214H
000FFE14H
⎯
210H
000FFE10H
⎯
20CH
000FFE0CH
⎯
208H
000FFE08H
⎯
204H
000FFE04H
⎯
200H
000FFE00H
⎯
1FCH
000FFDFCH
⎯
1F8H
000FFDF8H
⎯
1F4H
000FFDF4H
⎯
1F0H
000FFDF0H
⎯
CM71-10159-2E
APPENDIX C Interrupt Vector
MB91461
Table C-1 Interrupt Vector (6 / 6)
Interrupt number
Interrupt source
Real-time clock
HexaDecimal
decimal
132
Interrupt level
133
85H
A/D converter 0
134
86H
135
87H
System reserved
136
88H
137
89H
System reserved
138
8AH
ICR61
System reserved
139
8BH
Time base overflow
140
8CH
ICR62
PLL clock gear
141
8DH
DMA controller
142
8EH
Main/sub oscillation stabilization
wait
143
8FH
System reserved
144
90H
Used by the INT instruction
145
:
255
91H
:
FFH
1ECH
000FFDECH
⎯
1E8H
000FFDE8H
⎯
1E4H
000FFDE4H
14
1E0H
000FFDE0H
⎯
1DCH
000FFDDCH
⎯
1D8H
000FFDD8H
⎯
1D4H
000FFDD4H
⎯
1D0H
000FFDD0H
⎯
1CCH
000FFDCCH
⎯
1C8H
000FFDC8H
⎯
1C4H
000FFDC4H
⎯
1C0H
000FFDC0H
⎯
⎯
1BCH
000FFDBCH
⎯
⎯
1B8H
:
000H
000FFDB8H
:
000FFC00H
⎯
47AH
ICR60
System reserved
Resource
Number *1
ICR58
ICR59
System reserved
TBR default
address
Register
address
84H
System reserved
Offset
Setting
register
ICR63
⎯
⎯
47BH
47CH
47DH
47EH
47FH
*1 : The peripheral resources to which RN (Resource Number) is assigned are capable of being DMA transfer activation
sources. In addition, RN has a one-to-one correspondence with an IS (Input Source) of the DMAC channel control
register A(DMACA0 to DMACA4), and the IS (Input Source) can be obtained by representing RN in a binary number
and adding “1” to the head of it.
*2 : Used by REALOS
*3 : ICR23 and ICR47 are interchangeable by setting REALOS bit (address 0C03H ISO[0]).
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
667
APPENDIX
MB91461
APPENDIX D DMA Transfer Request Source
MB91461 has the following DMA transfer request source.
Table D-1 DMA Transfer Request Source
IS
(Input Source)
668
Function
Transfer stop request
00000B
Software transfer request only
00001B
to
01101B
Setting disabled
01110B
External pin (DREQ) "H" level or rising edge ↑
01111B
External pin (DREQ) "L" level or falling edge ↓
10000B
External interrupt 0
−
10001B
External interrupt 1
−
10010B
External interrupt 2
−
10011B
External interrupt 3
−
10100B
Reload timer 0
−
10101B
Reload timer 1
−
10110B
LIN-UART0 RX (Receive completed)
10111B
LIN-UART0 TX (Transmission completed)
11000B
LIN-UART1 RX (Receive completed)
11001B
LIN-UART1 TX (Transmission completed)
11010B
LIN-UART4 RX (Receive completed)
11011B
LIN-UART4 TX (Transmission completed)
11100B
LIN-UART5 RX (Receive completed)
11101B
LIN-UART5 TX (Transmission completed)
−
11110B
A/D converter
−
11111B
PPG0
−
FUJITSU MICROELECTRONICS LIMITED
−
Performed
−
Performed
−
Performed
−
Performed
CM71-10159-2E
APPENDIX E Pin State at Serial Programming Mode
MB91461
APPENDIX E Pin State at Serial Programming Mode
This section describes the pin state at serial programming mode.
■ List of Pin State at Serial Programming Mode
Table E-1 List of Pin State at Serial Programming Mode (1 / 5)
Pin number
Pin name
I/O
Output
Input
Pull-up/down
2
P24_2
I/O
Output Hi-Z
Input enable
off
3
P24_3
I/O
Output Hi-Z
Input enable
off
4
P22_6
I/O
Output Hi-Z
Input enable
-
5
P22_7
I/O
Output Hi-Z
Input enable
-
6
P24_4
I/O
Output Hi-Z
Input enable
-
7
P24_5
I/O
Output Hi-Z
Input enable
-
8
P13_0
I/O
Output Hi-Z
Input enable
off
9
P13_1
I/O
Output Hi-Z
Input enable
off
10
P13_2
I/O
Output Hi-Z
Input enable
off
14
C_1
15
P09_4
I/O
Output Hi-Z
Input enable
off
16
P09_3
I/O
Output Hi-Z
Input enable
off
17
P09_2
I/O
Output Hi-Z
Input enable
off
18
P09_1
I/O
Output Hi-Z
Input enable
off
19
P09_0
I/O
Output Hi-Z
Input enable
off
20
P11_0
I/O
Output Hi-Z
Input enable
off
21
P11_1
I/O
Output Hi-Z
Input enable
off
22
P08_7
I/O
Output Hi-Z
Input enable
off
23
P08_6
I/O
Output Hi-Z
Input enable
off
24
P08_5
I/O
Output Hi-Z
Input enable
off
25
P08_4
I/O
Output Hi-Z
Input enable
off
26
P08_1
I/O
Output Hi-Z
Input enable
off
27
P08_0
I/O
Output Hi-Z
Input enable
off
28
NMIX
I
-
Input enable
Pull-up
29
P10_6
I/O
Output Hi-Z
Input enable
off
?30
P10_5
I/O
Output Hi-Z
Input enable
off
31
P10_4
I/O
Output Hi-Z
Input enable
off
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
669
APPENDIX
MB91461
Table E-1 List of Pin State at Serial Programming Mode (2 / 5)
Pin number
Pin name
I/O
Output
Input
Pull-up/down
32
P10_3
I/O
Output Hi-Z
Input enable
off
33
P10_2
I/O
Output Hi-Z
Input enable
off
34
P10_1
I/O
Output Hi-Z
Input enable
off
35
P10_0
I/O
Output Hi-Z
Input enable
off
39
X0
I
-
Input enable
-
40
X1
I/O
Output Hi-Z
Input enable
-
42
X0A
I
-
Input enable
-
43
X1A
I/O
Output Hi-Z
Input enable
-
46
P01_0
I/O
Output Hi-Z
Input enable
off
47
P01_1
I/O
Output Hi-Z
Input enable
off
48
P01_2
I/O
Output Hi-Z
Input enable
off
49
P01_3
I/O
Output Hi-Z
Input enable
off
50
P01_4
I/O
Output Hi-Z
Input enable
off
51
P01_5
I/O
Output Hi-Z
Input enable
off
52
P01_6
I/O
Output Hi-Z
Input enable
off
53
P01_7
I/O
Output Hi-Z
Input enable
off
54
P00_0
I/O
Output Hi-Z
Input enable
off
55
P00_1
I/O
Output Hi-Z
Input enable
off
56
P00_2
I/O
Output Hi-Z
Input enable
off
59
P00_3
I/O
Output Hi-Z
Input enable
off
60
P00_4
I/O
Output Hi-Z
Input enable
off
61
P00_5
I/O
Output Hi-Z
Input enable
off
62
P00_6
I/O
Output Hi-Z
Input enable
off
63
P00_7
I/O
Output Hi-Z
Input enable
off
64
P07_0
I/O
Output Hi-Z
Input enable
off
65
P07_1
I/O
Output Hi-Z
Input enable
off
66
P07_2
I/O
Output Hi-Z
Input enable
off
67
P07_3
I/O
Output Hi-Z
Input enable
off
?68
P07_4
I/O
Output Hi-Z
Input enable
off
69
P07_5
I/O
Output Hi-Z
Input enable
off
70
P07_6
I/O
Output Hi-Z
Input enable
off
71
P07_7
I/O
Output Hi-Z
Input enable
off
72
P06_0
I/O
Output Hi-Z
Input enable
off
75
P06_1
I/O
Output Hi-Z
Input enable
off
670
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX E Pin State at Serial Programming Mode
MB91461
Table E-1 List of Pin State at Serial Programming Mode (3 / 5)
Pin number
Pin name
I/O
Output
Input
Pull-up/down
76
P06_2
I/O
Output Hi-Z
Input enable
off
77
P06_3
I/O
Output Hi-Z
Input enable
off
78
P06_4
I/O
Output Hi-Z
Input enable
off
79
P06_5
I/O
Output Hi-Z
Input enable
off
80
P06_6
I/O
Output Hi-Z
Input enable
off
81
P06_7
I/O
Output Hi-Z
Input enable
off
82
P05_0
I/O
Output Hi-Z
Input enable
off
83
P05_1
I/O
Output Hi-Z
Input enable
off
84
P05_2
I/O
Output Hi-Z
Input enable
off
85
P05_3
I/O
Output Hi-Z
Input enable
off
86
P05_4
I/O
Output Hi-Z
Input enable
off
87
P05_5
I/O
Output Hi-Z
Input enable
off
90
P05_6
I/O
Output Hi-Z
Input enable
off
91
P05_7
I/O
Output Hi-Z
Input enable
off
82
P05_0
I/O
Output Hi-Z
Input enable
off
92
P16_7
I/O
Output Hi-Z
Input enable
off
93
P17_4
I/O
Output Hi-Z
Input enable
off
94
P17_5
I/O
Output Hi-Z
Input enable
off
95
P17_6
I/O
Output Hi-Z
Input enable
off
96
P17_7
I/O
Output Hi-Z
Input enable
off
97
WDRESETX
O
Output
-
-
98
P29_0
I/O
Output Hi-Z
Input enable
off
99
P29_1
I/O
Output Hi-Z
Input enable
off
100
P29_2
I/O
Output Hi-Z
Input enable
off
?101
P29_3
I/O
Output Hi-Z
Input enable
off
102
P29_4
I/O
Output Hi-Z
Input enable
off
103
P29_5
I/O
Output Hi-Z
Input enable
off
104
P29_6
I/O
Output Hi-Z
Input enable
off
105
P29_7
I/O
Output Hi-Z
Input enable
off
106
P28_0
I/O
Output Hi-Z
Input enable
off
107
P28_1
I/O
Output Hi-Z
Input enable
off
108
P28_2
I/O
Output Hi-Z
Input enable
off
109
P28_3
I/O
Output Hi-Z
Input enable
off
110
P28_4
I/O
Output Hi-Z
Input enable
off
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
671
APPENDIX
MB91461
Table E-1 List of Pin State at Serial Programming Mode (4 / 5)
Pin number
Pin name
I/O
Output
Input
Pull-up/down
111
P28_5
I/O
Output Hi-Z
Input enable
off
112
P28_6
I/O
Output Hi-Z
Input enable
off
113
P28_7
I/O
Output Hi-Z
Input enable
off
117
P22_4
I/O
Output Hi-Z
Input enable
-
118
P22_5
I/O
Output Hi-Z
Input enable
-
119
P24_0
I/O
Output Hi-Z
Input enable
off
120
P24_1
I/O
Output Hi-Z
Input enable
off
121
P24_6
I/O
Output Hi-Z
Input enable
off
122
P24_7
I/O
Output Hi-Z
Input enable
off
123
P23_0
I/O
Output Hi-Z
Input enable
off
124
P23_1
I/O
Output Hi-Z
Input enable
off
125
P23_2
I/O
Output Hi-Z
Input enable
off
126
P23_3
I/O
Output Hi-Z
Input enable
off
127
MD3
I
-
MD3 = 0
Pull-down
128
MD2
I
-
MD2 = 1
-
129
MD1
I
-
MD1 = 0
-
130
MD0
I
-
MD0 = 0
-
131
INITX
I
-
Input enable
Pull-up
134
P21_0
I/O
Output Hi-Z
SIN0
off
135
P21_1
I/O
SOT0
-
off
136
P21_2
I/O
SCK0*1
-
off
137
P21_4
I/O
Output Hi-Z
Input enable
off
138
P21_5
I/O
Output Hi-Z
Input enable
off
139
P21_6
I/O
Output Hi-Z
Input enable
off
140
P20_0
I/O
Output Hi-Z
Input enable
off
141
P20_1
I/O
Output Hi-Z
Input enable
off
142
P20_2
I/O
Output Hi-Z
Input enable
off
143
P20_4
I/O
Output Hi-Z
Input enable
off
144
P20_5
I/O
Output Hi-Z
Input enable
off
145
P20_6
I/O
Output Hi-Z
Input enable
off
148
P19_0
I/O
Output Hi-Z
Input enable
off
149
P19_1
I/O
Output Hi-Z
Input enable
off
150
P19_2
I/O
Output Hi-Z
Input enable
off
151
P19_4
I/O
Output Hi-Z
Input enable
off
672
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
APPENDIX E Pin State at Serial Programming Mode
MB91461
Table E-1 List of Pin State at Serial Programming Mode (5 / 5)
Pin number
Pin name
I/O
Output
Input
Pull-up/down
152
P19_5
I/O
Output Hi-Z
Input enable
off
153
P19_6
I/O
Output Hi-Z
Input enable
off
154
P18_0
I/O
Output Hi-Z
Input enable
off
155
P18_1
I/O
Output Hi-Z
Input enable
off
156
P18_2
I/O
Output Hi-Z
Input enable
off
157
P15_0
I/O
Output Hi-Z
Input enable
off
158
P15_1
I/O
Output Hi-Z
Input enable
off
159
P15_2
I/O
Output Hi-Z
Input enable
off
160
P15_3
I/O
Output Hi-Z
Input enable
off
163
P23_4
I/O
Output Hi-Z
Input enable
off
164
P23_6
I/O
Output Hi-Z
Input enable
off
165
P22_0
I/O
Output Hi-Z
Input enable
off
166
P22_2
I/O
Output Hi-Z
Input enable
off
167
P22_3
I/O
Output Hi-Z
Input enable
off
168
P14_0
I/O
Output Hi-Z
Input enable
off
169
P14_1
I/O
Output Hi-Z
Input enable
off
170
P14_2
I/O
Output Hi-Z
Input enable
off
?171
P14_3
I/O
Output Hi-Z
Input enable
off
172
P17_0
I/O
Output Hi-Z
Input enable
off
173
P17_1
I/O
Output Hi-Z
Input enable
off
174
P17_2
I/O
Output Hi-Z
Input enable
off
175
P17_3
I/O
Output Hi-Z
Input enable
off
FUJISTU FLASH MCU Programmer is used.
after it resets "H" output
after control program is downloaded Hi-Z
It is recommended to use the mode pin level by fixation programming the serial usually. Please note that there is a pinl that
enters the state of the output when you change the MD2 pin as follows.
Operation mode: MD0=MD1=L, MD2=H, MD3=L, P15_2=P15_3=L
When MD2 changes "H" to "L" on the way.
P21_2:
After it resets "H" output
After control program is downloaded Hi-Z
P23_0:
"H" Output
P23_1:
After it resets "L" output
After it downloads "H" output
P23_2:
Pulse output of the main clock frequency
Unused at time of the serial programming I/O is in the state of Hi-Z.
CM71-10159-2E
FUJITSU MICROELECTRONICS LIMITED
673
APPENDIX
MB91461
674
FUJITSU MICROELECTRONICS LIMITED
CM71-10159-2E
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
675
INDEX
Index
Numerics
0 Detection
0 Detection ...................................................... 284
0-detection Data Register (BSD0) ...................... 282
0-detection Data Register
0-detection Data Register (BSD0) ...................... 282
1 Detection
1 Detection ...................................................... 284
1-detection Data Register (BSD1) ...................... 282
1-detection Data Register
1-detection Data Register (BSD1) ...................... 282
10-bit Slave Address Register
10-bit Slave Address Register (ITBA) ................ 502
16-bit Free-run Timer
16-bit Free-run Timer Operation ........................ 538
16-bit Free-run Timer Registers ......................... 533
Block Diagram of the 16-bit Free-run Timer ....... 532
Clear Timing of the 16-bit Free-run Timer.......... 539
Count Timing of the 16-bit Free-run Timer ......... 539
Notes on Using the 16-bit Free-run Timer........... 540
Overview of 16-bit Free-run Timer .................... 532
16-bit Free-run Timer Registers
16-bit Free-run Timer Registers ......................... 533
16-bit Input Capture
16-bit Input Capture Input Timing ..................... 548
16-bit Input Capture Operation .......................... 547
16-bit Output Compare
16-bit Output Compare Operation ...................... 556
16-bit Output Compare Operation Timing .......... 558
16-bit Reload Register
Bit Configuration of the 16-bit Reload Register
(TMRLR) ........................................... 526
16-bit Reload Timer
16-bit Reload Timer Registers ........................... 519
Block Diagram of 16-bit Reload Timer............... 518
Overview of the 16-bit Reload Timer (RLT) ....... 518
16-bit Reload Timer Registers
16-bit Reload Timer Registers ........................... 519
16-bit Timer Register
Bit Configuration of the 16-bit Timer Register
(TMR)................................................ 525
2-cycle Transfer
2-cycle Transfer (External → I/O)
(TYP[3:0]=0000B, AWR=0008H) ......... 218
2-cycle Transfer (I/O → External)
(TYP[3:0]=0000B, AWR=0008H) ......... 219
676
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H)......... 217
Burst 2-cycle Transfer ...................................... 310
Data Paths During 2-cycle Transfer ................... 330
Step/Block Transfer 2-cycle Transfer................. 311
32-bit ←→ 16-bit Bus Converter
32-bit ←→ 16-bit Bus Converter......................... 32
7-bit Slave Address Mask Register (ISMK)
7-bit Slave Address Mask Register (ISMK) ........ 506
7-bit Slave Address Register
7-bit Slave Address Register (ISBA).................. 505
INDEX
A
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) ............ 610
A/D Control Status Register 1 (ADCS1) ............ 607
A/D Conversion
A/D Conversion Data ....................................... 617
A/D Converter
Block Diagram of A/D Converter ...................... 603
Overview of A/D Converter Registers................ 604
A/D Converter Registers
Overview of A/D Converter Registers................ 604
A/D Enable Register
A/D Enable Register (ADER) ........................... 606
Acceptance Filter
Acceptance Filter for Reception Messages.......... 393
Access Address
Access Address................................................ 315
Access Mode
Access Mode ..................................................... 64
Acknowledge
Acknowledge................................................... 511
ACR
Register Configuration of Area Configuration
Register (ACR0 to ACR3) ................... 169
Activating Multiple PPG Channels
Activating Multiple PPG Channels Using
Software............................................. 589
AD Bit
AD Bit in the Serial Control Register (SCR) ....... 479
ADCR
Data Register (ADCR1, ADCR0) ...................... 612
ADCS
A/D Control Status Register 0 (ADCS0) ............ 610
A/D Control Status Register 1 (ADCS1) ............ 607
Address Register Specification
Address Register Specification .......................... 314
Address/Data Multiplex Access
Normal Access and Address/Data Multiplex
Access ............................................... 176
Addressing
Direct Addressing .............................................. 34
Direct Addressing Area ...................................... 28
Slave Addressing ............................................. 510
ADECH
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH)........................................... 615
ADER
A/D Enable Register (ADER) ........................... 606
ADSCH
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH)........................................... 615
All "L" or All "H" Output
All "L" or All "H" Output..................................588
Arbitration
Arbitration .......................................................510
Area Configuration Register
Register Configuration of Area Configuration
Register (ACR0 to ACR3) ....................169
Area Select Register
Register Configuration of ASR0 to ASR4
(Area Select Register) ..........................168
Area Wait Register
Register Configuration of Area Wait Register
(AWR0 to AWR4)...............................175
Arithmetic Operations
Arithmetic Operations .........................................33
ASR
Example of Setting ASR and ASZ[1:0]...............188
Register Configuration of ASR0 to ASR4
(Area Select Register) ..........................168
ASZ
Example of Setting ASR and ASZ[1:0]...............188
Automatic Restart
Automatic Restart .............................................457
Auto-wait Timing
Auto-wait Timing
(TYP[3:0]=0000B, AWR=2008H) .........209
AWR
2-cycle Transfer (External → I/O)
(TYP[3:0]=0000B, AWR=0008H) .........218
2-cycle Transfer (I/O → External)
(TYP[3:0]=0000B, AWR=0008H) .........219
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H) .........217
Auto-wait Timing
(TYP[3:0]=0000B, AWR=2008H) .........209
Basic Timing (for Consecutive Accesses)
(TYP[3:0]=0000B, AWR=0008H) .........205
CSX → RDX/WR1X,WR0X Setup and RDX/
WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH).........212
CSX Delay Setting
(TYP[3:0]=0000B, AWR=000CH).........211
External Wait Timing
(TYP[3:0]=0001B, AWR=2008H) .........210
Read → Write Timing
(TYP[3:0]=0000B, AWR=0048H) .........207
Register Configuration of Area Wait Register
(AWR0 to AWR4)...............................175
Setting of CSX → RDX/WR1X,WR0X Setup
(TYP[3:0]=0101B, AWR=100BH).........216
With External Wait
(TYP[3:0]=0101B, AWR=1008H) .........215
677
INDEX
Without External Wait
(TYP[3:0]=0100B, AWR=0008H) ......... 213
Write → Write Timing
(TYP[3:0]=0000B, AWR=0018H) ......... 208
B
Base Clock Division Setting Register
DIVR0: Base Clock Division Setting
Register 0 ............................................. 98
DIVR1: Base Clock Division Setting
Register 1 ........................................... 101
Basic Block Diagram
Basic Block Diagram of the I/O Port .................. 222
Basic Mode
Basic Mode...................................................... 407
Basic Programming Model
Basic Programming Model.................................. 35
Basic Timing
Basic Timing (for Consecutive Accesses)
(TYP[3:0]=0000B, AWR=0008H) ......... 205
Baud Rate
Baud Rate Calculation ...................................... 453
Baud Rate/Reload Counter Register
(BGR) ........................................ 441, 442
Examples of Baud Rate Settings by Machine Clock
Frequencies ........................................ 454
Selecting the Baud Rate for the LIN-UART ........ 451
Baud Rate/Reload Counter Register
Baud Rate/Reload Counter Register
(BGR) ........................................ 441, 442
BGR
Baud Rate/Reload Counter Register
(BGR) ........................................ 441, 442
Bidirectional Communication
Bidirectional Communication Function .............. 470
Big Endian
Data Format of Big Endian................................ 191
Difference Between Little Endian
and Big Endian ................................... 196
Bit Configuration
Bit Configuration of DMACR ........................... 304
Bit Configuration of DMASA0 to DMASA4/
DMADA0 to DMADA4 ...................... 302
Bit Configuration of EIRR ................................ 268
Bit Configuration of ELVR ............................... 269
Bit Configuration of ENIR ................................ 267
Bit Configuration of the 16-bit Reload Register
(TMRLR) ........................................... 526
Bit Configuration of the 16-bit Timer Register
(TMR)................................................ 525
Bit Configuration of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Bit Configuration of the Control Register
(OCS01,OCS23) ................................. 553
678
Bit Configuration of the Control Status Register
(TMCSR) ........................................... 520
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23) ....................... 545
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3)................................ 544
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Bit Function
Bit Function of DMACA0 to DMACA4............. 292
Bit Function of DMACB0 to DMACB4 ............. 296
Bit Ordering
Bit Ordering ...................................................... 44
Bit Search Module
Block Diagram of Bit Search Module ................ 281
Overview of the Bit Search Module ................... 280
Register List of Bit Search Module .................... 281
Block Diagram
Basic Block Diagram of the I/O Port.................. 222
Block Diagram ............................................ 5, 410
Block Diagram of 16-bit Reload Timer .............. 518
Block Diagram of A/D Converter ...................... 603
Block Diagram of Bit Search Module ................ 281
Block Diagram of Clock Generation Control
Block ................................................... 84
Block Diagram of Delayed Interrupt Module ...... 277
Block Diagram of DMAC................................. 290
Block Diagram of External Bus Interface ........... 165
Block Diagram of Hardware Watchdog
Timer................................................. 157
Block Diagram of I2C Interface......................... 486
Block Diagram of PPG ..................................... 563
Block Diagram of Real Time Clock ................... 594
Block Diagram of the 16-bit Free-run Timer....... 532
Block Diagram of the External Interrupt
Controller........................................... 265
Block Diagram of the Input Capture .................. 542
Block Diagram of the Interrupt Controller .......... 249
Block Diagram of the Interval Timer ................. 124
Block Diagram of the Output Compare Unit ....... 550
LIN-UART Block Diagram ...................... 417, 418
Block Size
Block Size....................................................... 312
Block Transfer
Block Transfer................................................. 311
Operational Flow of Block Transfer................... 328
Step/Block Transfer 2-cycle Transfer................. 311
Branch
Branch .............................................................. 33
Branch Instructions with a Delay Slot .................. 48
Description of the Branch Operation
with a Delay Slot .................................. 48
Overview of the Branch Instructions .................... 47
INDEX
BSD
0-detection Data Register (BSD0)...................... 282
1-detection Data Register (BSD1)...................... 282
BSDC
Changed Point Detection Data Register
(BSDC).............................................. 283
BSRR
Detection Result Register (BSRR) ..................... 283
Built-in ROM
Bus Mode 1 (Built-in ROM &
External Bus Mode) .............................. 65
Burst
Burst 2-cycle Transfer ...................................... 310
Burst Transfer
Operational Flow of Burst Transfer.................... 329
Bus Access
External Bus Access......................................... 193
Bus Control Register
Bus Control Register (IBCR) ............................ 492
Bus Error
Bus Error ........................................................ 511
Bus Idle
Bus Idle Function............................................. 479
Bus Idle Interrupt ............................................. 445
Bus Interface
Block Diagram of External Bus Interface ........... 165
Features of External Bus Interface ..................... 164
Overview of External Bus Interface
Registers ............................................ 167
Procedure for Setting External Bus Interface ...... 220
Register List of External Bus Interface............... 166
Bus Mode
Bus Mode.......................................................... 64
Bus Mode 0 (Single Chip Mode) ......................... 65
Bus Mode 1 (Built-in ROM & External Bus Mode)
............................................................ 65
Bus Mode 2 (External ROM & External Bus Mode)
............................................................ 65
Bus Status Register
Bus Status Register (IBSR) ............................... 488
Bus Timing
LIN Bus Timing............................................... 468
Byte
Byte Ordering .................................................... 44
Byte Access..................................................... 202
C
Cache
Cache Entry Update ......................................... 140
Cache Size Register (ISIZE) ............................. 135
Cache State in Various Operating Modes ........... 139
Instruction Cache ............................................... 31
Instruction Cache Area for Caching ................... 140
Instruction Cache Control Register (ICHCR) ...... 135
Register Configuration of Cache Enable Register
(CHER) ..............................................185
Cache Enable Register
Register Configuration of Cache Enable Register
(CHER) ..............................................185
Cache Size Register
Cache Size Register (ISIZE) ..............................135
Calculation
Baud Rate Calculation.......................................453
CAN
CAN Clock Frequency ......................................412
CAN Controller................................................335
Features of CAN...............................................334
CAN_TX
Software Control by the CAN_TX Pin................408
Cancellation Request
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .....................252
Example of Using the Hold Request Cancellation
Request Function (HRCL) ....................261
Hold Request Cancellation Request ....................259
Capture Input
16-bit Input Capture Input Timing......................548
Caution
Caution on Operations during PLL Clock
Mode....................................................22
CCR
Condition Code Register (CCR) ...........................38
Changed Point Detection
Changed Point Detection ...................................285
Changed Point Detection Data Register
(BSDC) ..............................................283
Changed Point Detection Data Register
Changed Point Detection Data Register
(BSDC) ..............................................283
Changing Operation Settings
Changing Operation Settings .............................478
Channel
Activating Multiple PPG Channels Using
Software .............................................589
Channel Group .................................................327
Disabling All Channels .....................................322
Enabling Operations for All Channels.................318
Priority Among Channels ..................................326
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH) ...........................................615
CHER
Register Configuration of Cache Enable Register
(CHER) ..............................................185
Chip
Bus Mode 0 (Single Chip Mode) ..........................65
Register Configuration of Chip Select Enable Register
(CSER)...............................................184
679
INDEX
Chip Select Enable Register
Register Configuration of Chip Select Enable Register
(CSER) .............................................. 184
Clear
Clear Timing of the 16-bit Free-run Timer.......... 539
CTBR: Time-base Counter Clear Register ............ 94
Clearing
Timing for Clearing an Interrupt by DMA .......... 320
CLKB
CPU Clock (CLKB) ........................................... 81
CLKP
Peripheral Clock (CLKP) .................................... 81
CLKR
CLKR: Clock Source Control Register ................. 95
CLKT
External Bus Clock (CLKT) ................................ 82
Clock
Block Diagram of Clock Generation Control
Block ................................................... 84
CAN Clock Frequency...................................... 412
Caution on Operations during PLL Clock
Mode ................................................... 22
CLKR: Clock Source Control Register ................. 95
Clock Automatic Gear Up-Down ....................... 117
Clock Control Register (ICCR).......................... 500
Clock Inversion and Start/Stop Bits in Mode 2 .... 462
Clock Prescaler Register ................................... 341
Clock Supply ................................................... 463
Clock Switching Procedure ............................... 411
CPU Clock (CLKB) ........................................... 81
CSCFG: Clock Source Configuration
Register .............................................. 103
DIVR0: Base Clock Division Setting
Register 0 ............................................. 98
DIVR1: Base Clock Division Setting
Register 1 ........................................... 101
Examples of Baud Rate Settings by Machine Clock
Frequencies ........................................ 454
External Bus Clock (CLKT) ................................ 82
Internal Clock Generation ................................... 77
Internal Clock Operation................................... 527
Notes on Using External Clock............................ 21
Peripheral Clock (CLKP) .................................... 81
Real Time Clock Registers ................................ 592
Selection of Clock .............................................. 77
Using an External Clock ................................... 455
Clock Control Register
Clock Control Register (ICCR).......................... 500
Clock Generation
Block Diagram of Clock Generation Control
Block ................................................... 84
Internal Clock Generation ................................... 77
Clock Prescaler Register
Clock Prescaler Register ................................... 341
680
Clock Source Configuration Register
CSCFG: Clock Source Configuration
Register ............................................. 103
Clock Source Control Register
CLKR: Clock Source Control Register................. 95
Clock Supply
Clock Supply................................................... 463
Combination
Combination of the Silent Mode and Loop-back
Mode. ................................................ 406
Communication
Bidirectional Communication Function .............. 470
Communication ............................................... 464
Communication Error Not Causing Error ........... 511
Communication Mode Setting ........................... 478
Communication Procedure................................ 472
Extended Communication Control Register
(ECCR).............................................. 438
LIN Master/Slave Communication Function....... 474
Master/Slave Communication Function.............. 471
Compare
16-bit Output Compare Operation...................... 556
16-bit Output Compare Operation Timing .......... 558
Bit Configuration of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Block Diagram of the Output Compare Unit ....... 550
Features of the Output Compare Unit................. 550
Functions of the Compare Register (OCCP0 to
OCCP3) ............................................. 552
Output Compare Unit Registers......................... 551
Compare Register
Bit Configuration of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Functions of the Compare Register
(OCCP0 to OCCP3) ........................... 552
Condition Code Register
Condition Code Register (CCR) .......................... 38
Configuration
Bit Configuration of DMACR ........................... 304
Bit Configuration of DMASA0 to DMASA4/
DMADA0 to DMADA4 ...................... 302
Bit Configuration of EIRR ................................ 268
Bit Configuration of ELVR............................... 269
Bit Configuration of ENIR................................ 267
Bit Configuration of the 16-bit Reload Register
(TMRLR)........................................... 526
Bit Configuration of the 16-bit Timer Register
(TMR) ............................................... 525
Bit Configuration of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Bit Configuration of the Control Register
(OCS01,OCS23) ................................. 553
Bit Configuration of the Control Status Register
(TMCSR) ........................................... 520
INDEX
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23) ....................... 545
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3)................................ 544
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Configuration of General Control Register 10
(GCN10) ............................................ 575
Configuration of the FIFO Buffer ...................... 397
Configuration of the General Control Register 11
(GCN11) ............................................ 578
Configuration of the General Control Register 2
(GCN20,GCN21) ................................ 581
Configuration of the Message Object ................. 371
Configuration of the PPG Cycle Setting Register
(PCSR) .............................................. 572
Configuration of the PPG Duty Setting Register
(PDUT).............................................. 573
Configuration of the PPG Timer Register
(PTMR) ............................................. 574
CSCFG: Clock Source Configuration
Register.............................................. 103
Hardware Configuration of DMAC.................... 288
Hardware Configuration of the Interrupt
Controller........................................... 246
Register Configuration
................. 344, 347, 350, 351, 353, 355,
357, 359, 362, 367, 368, 369,
370, 378, 380, 382, 384, 386
Register Configuration of Area Configuration
Register (ACR0 to ACR3) ................... 169
Register Configuration of Area Wait Register
(AWR0 to AWR4) .............................. 175
Register Configuration of ASR0 to ASR4
(Area Select Register).......................... 168
Register Configuration of Cache Enable Register
(CHER).............................................. 185
Register Configuration of Chip Select Enable Register
(CSER) .............................................. 184
Register Configuration of
IOWR0 to IOWR2 .............................. 181
Register Configuration of Terminal and Timing
Control Register (TCR) ....................... 186
Connection
Connection between CPUs................ 458, 470, 471
Dedicated DSU4 (ICE) Connection Pin................ 24
Example of Connection
with External Devices.................. 195, 199
LIN Device Connection .................................... 474
Consecutive Accesses
Basic Timing (for Consecutive Accesses)
(TYP[3:0]=0000B, AWR=0008H)......... 205
Continuous Mode
Continuous Mode............................................. 617
Control Register
Bit Configuration of the Control Register
(OCS01,OCS23)..................................553
Setting of Temporary Stop
by Writing to the Control Register
(Set Independently for Each Channel or All
Channels Simultaneously) ....................321
Control Signal
Relation Ship Between Data Bus Width and Control
Signal .................................................190
Control Status Register
Bit Configuration of the Control Status Register
(TMCSR)............................................520
Structure of the Control Status Registers
(PCNH, PCNL) ...................................568
Conversion
A/D Conversion Data........................................617
Conversion Time Setting Register ......................613
Conversion Time Setting Register
Conversion Time Setting Register ......................613
Coprocessor
Coprocessor Absent Trap ....................................62
Coprocessor Error Trap .......................................62
Count Timing
Count Timing of the 16-bit Free-run Timer .........539
Counter
Baud Rate/Reload Counter Register
(BGR) ........................................441, 442
CTBR: Time-base Counter Clear Register.............94
Operating States of the Counter..........................530
Program Counter (PC).........................................41
TBCR: Time-base Counter Control Register .........91
Time-base Counter ...........................................104
CPU
CPU ..................................................................31
CPU Clock (CLKB)............................................81
CPU Interface ..................................................335
CPUs
Connection between CPUs ................458, 470, 471
Crystal Oscillator Circuit
Crystal Oscillator Circuit.....................................20
CSCFG
CSCFG: Clock Source Configuration
Register ..............................................103
CSER
Register Configuration of Chip Select Enable Register
(CSER)...............................................184
CSX
CSX → RDX/WR1X,WR0X Setup and RDX/
WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH).........212
CSX Delay Setting
(TYP[3:0]=0000B, AWR=000CH).........211
Setting of CSX → RDX/WR1X,WR0X Setup
(TYP[3:0]=0101B, AWR=100BH).........216
681
INDEX
CTBR
CTBR: Time-base Counter Clear Register ............ 94
Cycle
Configuration of the PPG Cycle Setting Register
(PCSR)............................................... 572
Cycle of Hardware Watchdog Timer .................. 160
D
Data Bus Width
Data Bus Width........................................ 192, 198
Relation Ship Between Data Bus Width and Control
Signal................................................. 190
Data Direction Register
Data Direction Register (DDR).......................... 226
Data Format
Data Format..................................................... 197
Data Format of Big Endian................................ 191
Transfer Data Format................................ 460, 462
Data Frame
Data Frame Reception ...................................... 393
Data Register
Data Register (ADCR1, ADCR0) ...................... 612
Data Register (IDAR) ....................................... 507
Data Transfer
Example of Slave Address and Data Transfer...... 513
DDR
Data Direction Register (DDR).......................... 226
Debugger
Note on Debugger .............................................. 23
Dedicated DSU4
Dedicated DSU4 (ICE) Connection Pin ................ 24
Delay
Branch Instructions with a Delay Slot................... 48
CSX Delay Setting
(TYP[3:0]=0000B, AWR=000CH) ........ 211
Description of Operation without a Delay Slot ...... 50
Description of the Branch Operation
with a Delay Slot................................... 48
Instructions without a Delay Slot ......................... 50
Restrictions on the Operation
with a Delay Slot................................... 49
Delayed Interrupt
Block Diagram of Delayed Interrupt Module ...... 277
DICR (Delayed Interrupt Module Register) ........ 278
Overview of the Delayed Interrupt Module ......... 276
Register List of Delayed Interrupt Module .......... 277
Delayed Interrupt Module Register
DICR (Delayed Interrupt Module Register) ........ 278
Description
Description of Operation without a Delay Slot ...... 50
Description of the Blocks .................................. 419
Description of the Branch Operation
with a Delay Slot................................... 48
682
Details
Details of External Interrupt Controller
Registers ............................................ 266
Details of the Interrupt Controller Registers........ 250
Detection Result Register
Detection Result Register (BSRR) ..................... 283
Device
Device States................................................... 120
Example of Connection
with External Devices.................. 195, 199
LIN Device Connection .................................... 474
LIN-UART as a Master Device ......................... 475
LIN-UART as a Slave Device ........................... 476
Operation States of the Device .......................... 121
Overview of Reset (Device Initialization)............. 69
Overview of the Device State Control ................ 119
DICR
DICR (Delayed Interrupt Module Register) ........ 278
DLYI Bit of DICR ........................................... 279
Difference
Difference Between Little Endian and Big Endian
......................................................... 196
Direct Access
Direct Access to LIN-UART Pins...................... 469
Direct Address
Direct Addressing .............................................. 34
Direct Addressing Area ...................................... 28
Disabling
Disabling All Channels..................................... 322
Division Ratio
Initializing the Division Ratio Setting .................. 83
Setting the Division Ratio ................................... 83
DIVR
DIVR0: Base Clock Division Setting
Register 0............................................. 98
DIVR1: Base Clock Division Setting
Register 1........................................... 101
DLYI
DLYI Bit of DICR ........................................... 279
DMA
DMA Suppression............................................ 317
DMA Transfer and Interrupts ............................ 317
Notes on DMA Transfer in Sleep Mode ............. 325
Timing for Clearing an Interrupt by DMA .......... 320
DMAC
Block Diagram of DMAC................................. 290
Hardware Configuration of DMAC.................... 288
Interrupts That DMAC Interrupt Control can
Output ............................................... 324
Main Function of DMAC.................................. 288
Main Operations of DMAC............................... 307
Overview of the DMAC ................................... 306
Overview of the DMAC Registers ..................... 289
DMAC Registers
Overview of the DMAC Registers ..................... 289
INDEX
DMACA
Bit Function of DMACA0 to DMACA4............. 292
DMACB
Bit Function of DMACB0 to DMACB4 ............. 296
DMACR
Bit Configuration of DMACR ........................... 304
DMADA
Bit Configuration of DMASA0 to DMASA4/
DMADA0 to DMADA4 ...................... 302
DMASA
Bit Configuration of DMASA0 to DMASA4/
DMADA0 to DMADA4 ...................... 302
E
ECCR
Extended Communication Control Register
(ECCR).............................................. 438
EIRR
Bit Configuration of EIRR ................................ 268
EIT
EIT Features...................................................... 51
EIT Interrupt Levels ........................................... 52
EIT Operation.................................................... 59
EIT Triggers...................................................... 51
EIT Vector Table ............................................... 56
Returning from EIT............................................ 51
EITs
Priority of Accepting EITs .................................. 57
ELVR
Bit Configuration of ELVR............................... 269
Enabling
Enabling Operations for All Channels ................ 318
Enabling PLL Operation ..................................... 78
End
End of Transfer................................................ 322
Number of Transfers and End of Transfer........... 308
End Channel Setting Register
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH)........................................... 615
ENIR
Bit Configuration of ENIR................................ 267
Error
Bus Error ........................................................ 511
Communication Error Not Causing Error ........... 511
Coprocessor Error Trap ...................................... 62
Error Detection ........................................ 461, 464
Occurrence of an Address Error......................... 323
ESCR
Extended Status/Control Register (ESCR) .......... 435
Example
Example of Connection
with External Devices.................. 195, 199
Example of Counting........................................ 455
Example of Receive Data ..................................514
Example of Setting ASR and ASZ[1:0]...............188
Example of Slave Address
and Data Transfer ................................513
Example of Using the Hold Request Cancellation
Request Function (HRCL) ....................261
Examples of Baud Rate Settings by Machine Clock
Frequencies.........................................454
Extended Communication Control Register
Extended Communication Control Register
(ECCR) ..............................................438
Extended Status/Control Register
Extended Status/Control Register (ESCR)...........435
External Bus
Block Diagram of External Bus Interface ............165
Bus Mode 1 (Built-in ROM & External Bus Mode)
............................................................65
Bus Mode 2 (External ROM & External Bus Mode)
............................................................65
External Bus Access .........................................193
External Bus Clock (CLKT) ................................82
External Bus Setting ...........................................22
Features of External Bus Interface......................164
Overview of External Bus Interface
Registers.............................................167
Procedure for Setting External Bus Interface .......220
Register List of External Bus Interface................166
External Bus Interface Registers
Overview of External Bus Interface
Registers.............................................167
External Clock
Notes on Using External Clock ............................21
Using an External Clock....................................455
External Devices
Example of Connection
with External Devices ..................195, 199
External I/O
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H) .........217
External Interrupt
Block Diagram of the External Interrupt
Controller ...........................................265
Details of External Interrupt Controller
Registers.............................................266
External Interrupt Operation ..............................270
External Interrupt Request Level ........................271
List of the External Interrupt Controller
Registers.............................................264
Operation Procedure of External Interrupt...........270
External Interrupt Controller Registers
Details of External Interrupt Controller
Registers.............................................266
683
INDEX
List of the External Interrupt Controller
Registers ............................................ 264
External ROM
Bus Mode 2 (External ROM &
External Bus Mode)............................... 65
External Wait
External Wait Timing
(TYP[3:0]=0001B, AWR=2008H) ......... 210
With External Wait
(TYP[3:0]=0101B, AWR=1008H) ......... 215
Without External Wait
(TYP[3:0]=0100B, AWR=0008H) ......... 213
Functions of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Functions of the GCN10 ................................... 575
Functions of the GCN11 ................................... 578
Functions of the GCN20,GCN21 ....................... 581
Functions of the Message Object ....................... 371
Functions of the PCNH/PCNL Bits.................... 568
Functions of the PCSR ..................................... 572
Functions of the PDUT..................................... 573
Functions of the PTMR .................................... 574
LIN Master/Slave Communication Function....... 474
Main Function of DMAC.................................. 288
Main Functions of the Interrupt Controller ......... 246
Master/Slave Communication Function.............. 471
Operation of the Interval Timer Function ........... 128
Operation of the Output Pin Function................. 529
Register Functions .......... 344, 347, 350, 352, 354,
355, 357, 359, 362, 370,
379, 381, 383, 385, 386
F
Feature
EIT Features ...................................................... 51
Feature of I2C Interface..................................... 482
Features............................................... 2, 107, 562
Features of CAN .............................................. 334
Features of External Bus Interface ..................... 164
Features of the Internal Architecture .................... 29
Features of the Output Compare Unit ................. 550
FIFO
Configuration of the FIFO Buffer ...................... 397
Message Reception by the FIFO Buffer .............. 397
Reading from the FIFO Buffer........................... 398
Flag
I Flag ................................................................ 53
LIN-Synch-Break Interrupt Detection
and Flag ............................................. 467
Reception Interrupt Generation
and Flag Set Timing ............................ 447
Transmission Interrupt Generation
and Flag Timing.................................. 449
Format
Data Format..................................................... 197
Data Format of Big Endian................................ 191
Transfer Data Format................................ 460, 462
Free-run Timer
16-bit Free-run Timer Operation ........................ 538
16-bit Free-run Timer Registers ......................... 533
Block Diagram of the 16-bit Free-run Timer ....... 532
Clear Timing of the 16-bit Free-run Timer.......... 539
Count Timing of the 16-bit Free-run Timer ......... 539
Notes on Using the 16-bit Free-run Timer........... 540
Overview of 16-bit Free-run Timer .................... 532
Function
Bidirectional Communication Function .............. 470
Bit Function of DMACA0 to DMACA4 ............. 292
Bit Function of DMACB0 to DMACB4 ............. 296
Bus Idle Function ............................................. 479
Example of Using the Hold Request Cancellation
Request Function (HRCL).................... 261
Function of Hardware Watchdog Timer.............. 160
Function Settings.............................................. 472
684
G
GCN
Configuration of General Control Register 10
(GCN10) ............................................ 575
Configuration of the General Control Register 11
(GCN11) ............................................ 578
Configuration of the General Control Register 2
(GCN20,GCN21)................................ 581
Functions of the GCN10 ................................... 575
Functions of the GCN11 ................................... 578
Functions of the GCN20,GCN21 ....................... 581
Gear
Clock Automatic Gear Up-Down....................... 117
General Control Register
Configuration of General Control Register 10
(GCN10) ............................................ 575
Configuration of the General Control Register 11
(GCN11) ............................................ 578
Configuration of the General Control Register 2
(GCN20,GCN21)................................ 581
General Control Registers ......................... 342, 343
List of the General Control Registers ................. 337
General Specification
General Specification of Ports ........................... 224
General-purpose Registers
General-purpose Registers .................................. 36
H
Handling
Interrupt Handling............................................ 515
Hardware Configuration
Hardware Configuration of DMAC.................... 288
Hardware Configuration of the Interrupt
Controller........................................... 246
INDEX
Hardware Watchdog Reset
Hardware Watchdog Reset.................................. 72
Hardware Watchdog Timer
Block Diagram of Hardware Watchdog Timer
.......................................................... 157
Cycle of Hardware Watchdog Timer.................. 160
Function of Hardware Watchdog Timer ............. 160
Hardware Watchdog Timer ............................... 156
Hardware Watchdog Timer Period Register........ 159
Hardware Watchdog Timer Register .................. 158
Notes on Using Hardware Watchdog Timer........ 162
Hardware Watchdog Timer Period Register
Hardware Watchdog Timer Period Register........ 159
Hardware Watchdog Timer Register
Hardware Watchdog Timer Register .................. 158
Harvard ←→ Princeton Bus Converter
Harvard ←→ Princeton Bus Converter ................ 32
Hold Request
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Example of Using the Hold Request Cancellation
Request Function (HRCL) ................... 261
Hold Request Cancellation Request ................... 259
Hold Request Cancellation Request Register
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Hold Setting
CSX → RDX/WR1X,WR0X Setup and RDX/
WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH) ........ 212
Hold Suppression
NMI/Hold Suppression Level Interrupt
Processing .......................................... 321
Hour/Minute/Second Register
Hour/Minute/Second Register ........................... 599
How to Read
How to Read the I/O Map ................................. 641
HRCL
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Example of Using the Hold Request Cancellation
Request Function (HRCL) ................... 261
I
I Flag
I Flag ................................................................ 53
I/O
2-cycle Transfer (External → I/O)
(TYP[3:0]=0000B, AWR=0008H)......... 218
2-cycle Transfer (I/O → External)
(TYP[3:0]=0000B, AWR=0008H)......... 219
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H) .........217
Basic Block Diagram of the I/O Port ..................222
How to Read the I/O Map..................................641
I/O Circuit Types................................................15
I/O Pins ...........................................................166
2
I C Interface
Block Diagram of I2C Interface..........................486
Feature of I2C Interface.....................................482
I2C Interface Register Overview ........................487
I2C Interface Registers ......................................483
2
I C Interface Register
I2C Interface Register Overview ........................487
I2C Interface Registers ......................................483
IBCR
Bus Control Register (IBCR) .............................492
IBSR
Bus Status Register (IBSR)................................488
ICCR
Clock Control Register (ICCR) ..........................500
ICE
Dedicated DSU4 (ICE) Connection Pin ................24
ICHCR
Instruction Cache Control Register (ICHCR).......135
ICR
Bit Configuration of the Interrupt Control Register
(ICR)..................................................251
ICR Mapping .....................................................54
Interrupt Control Register (ICR) Bit Structure .......54
ICS
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23)........................545
IDAR
Data Register (IDAR) .......................................507
Idle
Bus Idle Function .............................................479
Bus Idle Interrupt..............................................445
ILM
ILM...................................................................53
Interrupt Level Mask Register (ILM)....................41
INIT
Setting Initialization Reset (INIT) ........................70
Setting Initialization Reset (INIT) Release
Sequence ..............................................73
Initialization
INITX Pin Input
(Setting Initialization Reset Pin)..............71
Operation Initialization Reset (RST).....................70
Operation Initialization Reset (RST) Release
Sequence ..............................................73
Overview of Reset (Device Initialization) .............69
Setting Initialization Reset (INIT) ........................70
685
INDEX
Setting Initialization Reset (INIT) Release
Sequence .............................................. 73
Wait Time after Setting Initialization ................... 79
Initializing
Initializing the Division Ratio Setting................... 83
INITX
INITX Pin Input
(Setting Initialization Reset Pin) ............. 71
Input Capture
16-bit Input Capture Input Timing ..................... 548
16-bit Input Capture Operation .......................... 547
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23) ....................... 545
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3P) .............................. 544
Block Diagram of the Input Capture................... 542
Input Capture Registers..................................... 543
Overview of the Input Capture........................... 542
Input Capture Control Register
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23) ....................... 545
Input Capture Register
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3) ................................ 544
Input Capture Registers..................................... 543
Input Timing
16-bit Input Capture Input Timing ..................... 548
Instruction
Branch Instructions with a Delay Slot................... 48
Instruction Cache ............................................... 31
Instruction Cache Area for Caching ................... 140
Instruction Cache Control Register (ICHCR) ...... 135
Instructions without a Delay Slot ......................... 50
Operation of the INT Instruction.......................... 60
Operation of the INTE Instruction........................ 60
Operation of the RETI Instruction ........................ 62
Operation of the Undefined Instruction
Exception ............................................. 61
Other Instructions............................................... 34
Overview of the Branch Instructions .................... 47
Instruction Cache Control Register
Instruction Cache Control Register (ICHCR) ...... 135
INT
Operation of the INT Instruction.......................... 60
INTE
Operation of the INTE Instruction........................ 60
Interface
Block Diagram of External Bus Interface............ 165
Block Diagram of I2C Interface ......................... 486
CPU Interface .................................................. 335
Feature of I2C Interface..................................... 482
Features of External Bus Interface ..................... 164
I2C Interface Register Overview ........................ 487
I2C Interface Registers...................................... 483
List of the Message Interface Registers............... 338
686
Message Interface Registers .............................. 342
Overview of External Bus Interface
Registers ............................................ 167
Procedure for Setting External Bus Interface ...... 220
Register List of External Bus Interface............... 166
Internal Architecture
Features of the Internal Architecture .................... 29
Structure of the Internal Architecture ................... 30
Internal Clock
Internal Clock Generation ................................... 77
Internal Clock Operation .................................. 527
Internal Peripheral Request
Internal Peripheral Request ............................... 309
Internal RAM
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H)......... 217
Interrupt
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Block Diagram of Delayed Interrupt Module ...... 277
Block Diagram of the External Interrupt
Controller........................................... 265
Block Diagram of the Interrupt Controller .......... 249
Bus Idle Interrupt ............................................. 445
Details of External Interrupt Controller
Registers ............................................ 266
Details of the Interrupt Controller Registers........ 250
DICR (Delayed Interrupt Module Register) ........ 278
EIT Interrupt Levels........................................... 52
External Interrupt Operation ............................. 270
External Interrupt Request Level ....................... 271
Hardware Configuration of the Interrupt
Controller........................................... 246
Interrupt Control Register (ICR) Bit Structure ...... 54
Interrupt Controller Registers ............................ 247
Interrupt Handling............................................ 515
Interrupt Level Mask Register (ILM) ................... 41
Interrupt Number ............................................. 279
Interrupt Operation........................................... 587
Interrupt Stack ................................................... 55
Interrupts That DMAC Interrupt Control can
Output ............................................... 324
Interval Interrupt.............................................. 128
LIN-Synch-Break Interrupt ............................... 445
LIN-Synch-Break Interrupt Detection
and Flag ............................................. 467
LIN-Synch-Field Edge Detection Interrupt ......... 445
List of the External Interrupt Controller
Registers ............................................ 264
Main Functions of the Interrupt Controller ......... 246
NMI (Non Maskable Interrupt).......................... 259
NMI/Hold Suppression Level Interrupt
Processing .......................................... 321
Operation Procedure of External Interrupt .......... 270
INDEX
Overview of the Delayed Interrupt Module......... 276
Precautions when Returning from STOP State Using
External Interrupt ................................ 272
Reception Interrupt .......................................... 444
Reception Interrupt Generation
and Flag Set Timing ............................ 447
Register List of Delayed Interrupt Module.......... 277
Timing for Clearing an Interrupt by DMA .......... 320
Transmission Interrupt...................................... 444
Transmission Interrupt Enable Timing ............... 478
Transmission Interrupt Generation
and Flag Timing.................................. 449
Transmission Interrupt Request Generation
Timing ............................................... 450
Interrupt Control
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Interrupt Control Register (ICR) Bit Structure ...... 54
Interrupts That DMAC Interrupt Control can
Output................................................ 324
Interrupt Control Register
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Interrupt Control Register (ICR) Bit Structure ...... 54
Interrupt Controller
Block Diagram of the Interrupt Controller .......... 249
Details of the Interrupt Controller Registers........ 250
Hardware Configuration of the Interrupt
Controller........................................... 246
Interrupt Controller Registers ............................ 247
Main Functions of the Interrupt Controller ......... 246
Interrupt Controller Registers
Details of the Interrupt Controller Registers........ 250
Interrupt Controller Registers ............................ 247
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 41
Interrupt Request
External Interrupt Request Level ....................... 271
Transmission Interrupt Request Generation
Timing ............................................... 450
Interrupts
DMA Transfer and Interrupts ............................ 317
Interrupts That DMAC Interrupt Control can
Output................................................ 324
Level Mask for Interrupts/NMI ........................... 53
LIN-UART Interrupts....................................... 443
Operation of User Interrupts and NMI.................. 59
Interval Duration
Interval Duration of the Interval Timer............... 124
Interval Interrupt
Interval Interrupt.............................................. 128
Interval Timer
Block Diagram of the Interval Timer ................. 124
Interval Duration of the Interval Timer............... 124
Interval Timer Operation .................................. 129
Operation of the Interval Timer Function ............128
Precautions for Use of the Interval Timer............129
Registers in the Interval Timer ...........................126
IOWR
Register Configuration of
IOWR0 to IOWR2...............................181
IPCP
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3) ................................544
ISBA
7-bit Slave Address Register (ISBA) ..................505
ISIZE
Cache Size Register (ISIZE) ..............................135
ISMK
7-bit Slave Address Mask Register (ISMK).........506
ITBA
10-bit Slave Address Register (ITBA) ................502
ITMK
10-bit Slave Address Mask Register (ITMK).......503
L
Latch-up
Preventing Latch-up............................................20
Level Mask
Interrupt Level Mask Register (ILM)....................41
Level Mask for Interrupts/NMI ............................53
LIN Bus Timing
LIN Bus Timing ...............................................468
LIN Device
LIN Device Connection.....................................474
LIN in Operation Mode 3
Using LIN in Operation Mode 3.........................478
LIN Master/Slave
LIN Master/Slave Communication Function .......474
LIN Slave
Setting LIN Slave .............................................478
LIN-Synch-Break
LIN-Synch-Break Interrupt................................445
LIN-Synch-Break Interrupt Detection
and Flag..............................................467
LIN-Synch-Field Edge Detection Interrupt..........445
LIN-UART
Direct Access to LIN-UART Pins ......................469
LIN-UART as a Master Device..........................475
LIN-UART as a Slave Device............................476
LIN-UART as LIN Master ................................465
LIN-UART as LIN Slave ..................................466
LIN-UART Block Diagram .......................417, 418
LIN-UART Interrupts .......................................443
LIN-UART Operations .....................................458
LIN-UART Registers ........................................422
Operation Modes of LIN-UART ........................415
Selecting the Baud Rate for the LIN-UART ........451
687
INDEX
LIN-UART Registers
LIN-UART Registers........................................ 422
List
List of the External Interrupt Controller
Registers ............................................ 264
List of the General Control Registers.................. 337
List of the Message Handler Registers................ 340
List of the Message Interface Registers............... 338
Register List of Bit Search Module .................... 281
Register List of Delayed Interrupt Module .......... 277
Register List of External Bus Interface ............... 166
Little Endian
Difference Between Little Endian
and Big Endian ................................... 196
Restrictions on a Little Endian Area ................... 196
Load
Load and Store................................................... 33
Logical Operations
Logical Operations and Bit Manipulation ............. 34
Loop-back
Combination of the Silent Mode and Loop-back
Mode.................................................. 406
Loop-back Mode .............................................. 405
M
Machine Clock
Examples of Baud Rate Settings by Machine Clock
Frequencies ........................................ 454
Main Frame Structure
Main Frame Structure ....................................... 132
Main Function
Main Function of DMAC .................................. 288
Main Functions of the Interrupt Controller.......... 246
Main Operations
Main Operations of DMAC ............................... 307
Manipulation
Logical Operations and Bit Manipulation ............. 34
Mapping
ICR Mapping ..................................................... 54
Mask
10-bit Slave Address Mask Register (ITMK) ...... 503
7-bit Slave Address Mask Register (ISMK) ........ 506
Interrupt Level Mask Register (ILM) ................... 41
Level Mask for Interrupts/NMI............................ 53
Slave Address Mask ......................................... 510
Master
LIN Master/Slave Communication Function ....... 474
LIN-UART as a Master Device ......................... 475
LIN-UART as LIN Master ................................ 465
Master/Slave Communication Function .............. 471
MB91461
Pin Assignment Diagram of the MB91461.............. 7
MD
Mode Pins (MD0 to MD3) .................................. 21
688
Memory
Memory Map............................................... 28, 46
Message
Acceptance Filter for Reception Messages ......... 393
Configuration of the Message Object ................. 371
Data Transmission/Reception to/from the Message
RAM ................................................. 389
Functions of the Message Object ....................... 371
List of the Message Handler Registers ............... 340
List of the Message Interface Registers .............. 338
Message Handler ............................................. 335
Message Handler Register ................................ 377
Message Handler Registers ............................... 342
Message Interface Registers .............................. 342
Message Object ............................................... 389
Message RAM................................................. 335
Message Reception by the FIFO Buffer.............. 397
Message Transmission...................................... 391
Reception Message Object Setting..................... 395
Reception Message Processing .......................... 396
Transmission Message Object Setting ................ 391
Updating a Transmission Message Object .......... 392
Message Handler Register
List of the Message Handler Registers ............... 340
Message Handler Register ................................ 377
Message Handler Registers ............................... 342
Message Interface Registers
List of the Message Interface Registers .............. 338
Message Interface Registers .............................. 342
Mode
Access Mode ..................................................... 64
Basic Mode ..................................................... 407
Bus Mode.......................................................... 64
Bus Mode 0 (Single Chip Mode) ......................... 65
Bus Mode 1 (Built-in ROM & External Bus Mode)
........................................................... 65
Bus Mode 2 (External ROM & External Bus Mode)
........................................................... 65
Caution on Operations during PLL Clock Mode
........................................................... 22
Clock Inversion and Start/Stop Bits in Mode 2
......................................................... 462
Combination of the Silent Mode and Loop-back
Mode. ................................................ 406
Communication Mode Setting ........................... 478
Continuous Mode............................................. 617
Loop-back Mode.............................................. 405
Mode Pins ......................................................... 66
Mode Pins (MD0 to MD3) .................................. 21
Mode Register (MODR) ..................................... 66
Notes on DMA Transfer in Sleep Mode ............. 325
Overview of Sleep Mode .................................. 145
Return from Standby Mode (Sleep/Stop) ............ 260
Serial Mode Register (SMR) ............................. 427
Setting the Test Mode....................................... 404
Silent Mode..................................................... 404
INDEX
Single Mode ............................................ 459, 617
Stop Mode....................................................... 618
Transfer Mode ................................................. 307
Using LIN in Operation Mode 3 ........................ 478
Wait Time after Return from the Stop Mode ......... 80
Mode Pins
Mode Pins ......................................................... 66
Mode Pins (MD0 to MD3) .................................. 21
Mode Register
Mode Register (MODR) ..................................... 66
Serial Mode Register (SMR) ............................. 427
Modes
Cache State in Various Operating Modes ........... 139
Operation Modes of LIN-UART........................ 415
Overview of the Operating Modes ....................... 64
MODR
Mode Register (MODR) ..................................... 66
Module
Block Diagram of Bit Search Module ................ 281
Block Diagram of Delayed Interrupt Module ...... 277
DICR (Delayed Interrupt Module Register) ........ 278
Overview of the Bit Search Module ................... 280
Overview of the Delayed Interrupt Module......... 276
Register List of Bit Search Module .................... 281
Register List of Delayed Interrupt Module.......... 277
Multiple Activation
Multiple Activation Using a Trigger from the Reload
Timer................................................. 590
Multiply & Divide Registers
Multiply & Divide Registers ............................... 43
N
NMI
Level Mask for Interrupts/NMI ........................... 53
NMI (Non Maskable Interrupt).......................... 259
NMI/Hold Suppression Level Interrupt
Processing .......................................... 321
Operation of User Interrupts and NMI.................. 59
Normal Access
Normal Access and Address/Data Multiplex
Access ............................................... 176
Note
Note on Debugger .............................................. 23
Notes on DMA Transfer in Sleep Mode ............. 325
Notes on Setting Registers ................................ 291
Notes on the PS Register..................................... 22
Notes on Using External Clock............................ 21
Notes on Using Hardware Watchdog Timer........ 162
Notes on Using the 16-bit Free-run Timer .......... 540
Notice
Notice ............................................................. 530
Number
Interrupt Number ............................................. 279
Number of Transfers and End of Transfer........... 308
O
Object
Configuration of the Message Object..................371
Functions of the Message Object........................371
Message Object ................................................389
Reception Message Object Setting .....................395
Transmission Message Object Setting.................391
Updating a Transmission Message Object ...........392
OCCP
Bit Configuration of the Compare Register
(OCCP0 to OCCP3).............................552
Functions of the Compare Register
(OCCP0 to OCCP3).............................552
Occurrence
Occurrence of an Address Error .........................323
OCS
Bit Configuration of the Control Register
(OCS01,OCS23)..................................553
One-Shot Operation
One-Shot Operation ..........................................585
Operating Modes
Cache State in Various Operating Modes ............139
Overview of the Operating Modes........................64
Operating States
Operating States of the Counter..........................530
Operation
16-bit Free-run Timer Operation ........................538
16-bit Input Capture Operation ..........................547
16-bit Output Compare Operation ......................556
16-bit Output Compare Operation Timing...........558
Arithmetic Operations .........................................33
Caution on Operations during PLL Clock
Mode....................................................22
Changing Operation Settings .............................478
Description of Operation without a Delay Slot.......50
Description of the Branch Operation
with a Delay Slot ...................................48
EIT Operation ....................................................59
Enabling Operations for All Channels.................318
Enabling PLL Operation......................................78
External Interrupt Operation ..............................270
Internal Clock Operation ...................................527
Interrupt Operation ...........................................587
Interval Timer Operation ...................................129
LIN-UART Operations .....................................458
Logical Operations and Bit Manipulation..............34
Main Operations of DMAC ...............................307
One-Shot Operation ..........................................585
Operation Enable Bit.........................................459
Operation Initialization Reset (RST).....................70
Operation Initialization Reset (RST) Release
Sequence ..............................................73
Operation Modes of LIN-UART ........................415
Operation of the INT Instruction ..........................60
Operation of the INTE Instruction ........................60
689
INDEX
Operation of the Interval Timer Function............ 128
Operation of the Output Pin Function ................. 529
Operation of the RETI Instruction ........................ 62
Operation of the Step Trace Trap ......................... 61
Operation of the Undefined Instruction
Exception ............................................. 61
Operation of User Interrupts and NMI .................. 59
Operation Procedure of External Interrupt .......... 270
Operation Setting ............................................. 478
Operation States of the Device........................... 121
Ordinary Reset Operation.................................... 76
PPG Operation ................................................. 582
PWM Operation ............................................... 583
Reception Operation ......................................... 461
Reload Operation ............................................. 312
Restrictions on the Operation with a Delay Slot..... 49
Synchronous Reset Operation.............................. 76
Transfer Count Register and Reload Operation
.......................................................... 316
Transmission Operation .................................... 461
Underflow Operation ........................................ 528
Using LIN in Operation Mode 3 ........................ 478
Wait Time after PLL Operation is Enabled ........... 79
Operation Enable Bit
Operation Enable Bit ........................................ 459
Operation Mode
Operation Modes of LIN-UART ........................ 415
Using LIN in Operation Mode 3 ........................ 478
Operational Flow
Operational Flow of Block Transfer ................... 328
Operational Flow of Burst Transfer .................... 329
Ordinary Reset Operation
Ordinary Reset Operation.................................... 76
Oscillation Stabilization Wait
Oscillation Stabilization Wait Factors................... 74
Selection of Oscillation Stabilization Wait
Time .................................................... 75
Oscillator
Crystal Oscillator Circuit .................................... 20
Other Instructions
Other Instructions............................................... 34
Others
Others ............................................................. 512
Output
16-bit Output Compare Operation ...................... 556
16-bit Output Compare Operation Timing .......... 558
About WDRESETX Pin Output......................... 161
All "L" or All "H" Output ................................. 588
Block Diagram of the Output Compare Unit ....... 550
Features of the Output Compare Unit ................. 550
Interrupts That DMAC Interrupt Control can
Output ................................................ 324
Operation of the Output Pin Function ................. 529
Output Compare Unit Registers ......................... 551
PPG Output Timing.......................................... 583
690
Output Compare
16-bit Output Compare Operation...................... 556
16-bit Output Compare Operation Timing .......... 558
Block Diagram of the Output Compare Unit ....... 550
Features of the Output Compare Unit................. 550
Output Compare Unit Registers......................... 551
Output Compare Unit Registers
Output Compare Unit Registers......................... 551
Output Pin
Operation of the Output Pin Function................. 529
Overview
I2C Interface Register Overview........................ 487
Overview ................................................ 132, 414
Overview of 16-bit Free-run Timer .................... 532
Overview of A/D Converter Registers................ 604
Overview of External Bus Interface
Registers ............................................ 167
Overview of Reset (Device Initialization)............. 69
Overview of the 16-bit Reload Timer (RLT)....... 518
Overview of the Bit Search Module ................... 280
Overview of the Branch Instructions .................... 47
Overview of the Delayed Interrupt Module......... 276
Overview of the Device State Control ................ 119
Overview of the DMAC ................................... 306
Overview of the DMAC Registers ..................... 289
Overview of the Input Capture .......................... 542
Overview of the Operating Modes ....................... 64
P
Parity
Parity.............................................................. 461
PC
Program Counter (PC) ........................................ 41
PCNH
Functions of the PCNH/PCNL Bits.................... 568
Structure of the Control Status Registers
(PCNH, PCNL) .................................. 568
PCNL
Functions of the PCNH/PCNL Bits.................... 568
Structure of the Control Status Registers
(PCNH, PCNL) .................................. 568
PCSR
Configuration of the PPG Cycle Setting Register
(PCSR) .............................................. 572
Functions of the PCSR ..................................... 572
PDR
Port Data Register (PDR).................................. 226
PDRD
Port Data Direct Read Register (PDRD)............. 227
PDUT
Configuration of the PPG Duty Setting Register
(PDUT).............................................. 573
Functions of the PDUT..................................... 573
INDEX
Peripheral Circuits
Transfer Stop Requests from Peripheral
Circuits .............................................. 323
Peripheral Clock
Peripheral Clock (CLKP).................................... 81
Pin
About WDRESETX Pin Output ........................ 161
Dedicated DSU4 (ICE) Connection Pin................ 24
Direct Access to LIN-UART Pins...................... 469
I/O Pins........................................................... 166
INITX Pin Input
(Setting Initialization Reset Pin) ............. 71
Mode Pins ......................................................... 66
Mode Pins (MD0 to MD3) .................................. 21
Operation of the Output Pin Function................. 529
Pin Assignment Diagram of the MB91461 ............. 7
Pin Descriptions................................................... 9
Pin Input Level ................................................ 242
Power Supply Pins ............................................. 20
Selection of Pin Input Level .............................. 242
Software Control by the CAN_TX Pin ............... 408
Treatment of Unused Pins ................................... 20
Pin Assignment
Pin Assignment Diagram of the MB91461 ............. 7
Pin Function
Operation of the Output Pin Function................. 529
PLL
Caution on Operations during PLL Clock
Mode ................................................... 22
Enabling PLL Operation ..................................... 78
PLL Multiply Rate ............................................. 78
PLLDIVM: PLL Divider M .............................. 108
PLLDIVN: PLL Divider N ............................... 110
Wait Time after PLL Operation is Enabled ........... 79
Wait Time after the PLL Multiply Rate is
Changed............................................... 79
PLL Clock Mode
Caution on Operations during PLL Clock
Mode ................................................... 22
PLLCTRL
PLLCTRL ....................................................... 113
PLLDIVG
PLLDIVG ....................................................... 111
PLLDIVM
PLLDIVM: PLL Divider M .............................. 108
PLLDIVN
PLLDIVN: PLL Divider N ............................... 110
PLLMULG
PLLMULG...................................................... 112
Port
Basic Block Diagram of the I/O Port.................. 222
General Specification of Ports ........................... 224
Port 01 ............................................................ 228
Port 05 ............................................................ 228
Port 06 ............................................................ 228
Port 07.............................................................228
Port 08.............................................................228
Port 09.............................................................228
Port 10.............................................................228
Port 11.............................................................228
Port 13.............................................................228
Port 14.............................................................228
Port 15.............................................................230
Port 16.............................................................231
Port 17.............................................................231
Port 18.............................................................232
Port 19.............................................................233
Port 20.............................................................234
Port 21.............................................................235
Port 22.............................................................236
Port 23.............................................................237
Port 24.............................................................238
Port 28.............................................................240
Port 29.............................................................241
Port Data Register (PDR) ..................................226
Port Pull-up and Pull-down Control Register .......244
Port Pull-up and Pull-down Enable Register ........243
Port Data Direct Read Register
Port Data Direct Read Register (PDRD)..............227
Port Data Register
Port Data Register (PDR) ..................................226
Port Pull-up and Pull-down Control Register
Port Pull-up and Pull-down Control Register .......244
Port Pull-up and Pull-down Enable Register
Port Pull-up and Pull-down Enable Register ........243
Power Supply Pins
Power Supply Pins..............................................20
Power-on
Wait Time after Power-on ...................................79
Power-up Sequence
Power-up Sequence for 3.3V and 5V Power
Supplies................................................21
PPG
Activating Multiple PPG Channels Using
Software .............................................589
Block Diagram of PPG......................................563
Configuration of the PPG Cycle Setting Register
(PCSR) ...............................................572
Configuration of the PPG Duty Setting Register
(PDUT) ..............................................573
Configuration of the PPG Timer Register
(PTMR) ..............................................574
PPG Operation .................................................582
PPG Output Timing ..........................................583
PPG Registers ..................................................565
PPG Cycle Setting Register
Configuration of the PPG Cycle Setting Register
(PCSR) ...............................................572
691
INDEX
PPG Duty Setting Register
Configuration of the PPG Duty Setting Register
(PDUT) .............................................. 573
PPG Timer Register
Configuration of the PPG Timer Register
(PTMR).............................................. 574
Precautions
Precautions for Use of the Interval Timer ........... 129
Prescaler Register
Prescaler Register............................................. 342
Preventing Latch-up
Preventing Latch-up ........................................... 20
Priority
Priority Among Channels.................................. 326
Priority Decision .............................................. 253
Priority of Accepting EITs .................................. 57
Reception Priority ............................................ 393
Transmission Priority........................................ 391
Procedure
Clock Switching Procedure ............................... 411
Communication Procedure ................................ 472
Operation Procedure of External Interrupt .......... 270
Procedure for Setting External Bus Interface....... 220
Processing
NMI/Hold Suppression Level Interrupt
Processing .......................................... 321
Reception Message Processing .......................... 396
Save and Restore Processing ............................. 286
Product Lineup
Product Lineup..................................................... 4
Program
Program Counter (PC) ........................................ 41
Program Status (PS) ........................................... 37
Programming
Basic Programming Model.................................. 35
PS
Notes on the PS Register..................................... 22
Program Status (PS) ........................................... 37
PS Register
Notes on the PS Register..................................... 22
PTMR
Configuration of the PPG Timer Register
(PTMR).............................................. 574
Functions of the PTMR..................................... 574
Pull-up and Pull-down
Port Pull-up and Pull-down Control Register....... 244
Port Pull-up and Pull-down Enable Register........ 243
Pull-up and Pull-down Control .......................... 243
Pull-up Control
Pull-up Control .................................................. 22
PWM
PWM Operation ............................................... 583
692
R
RAM
2-cycle Transfer (The Timing is the Same as for
Internal RAM → External I/O, RAM,
External I/O, RAM → Internal RAM.)
(TYP[3:0]=0000B, AWR=0008H)......... 217
Data Transmission/Reception to/from the Message
RAM ................................................. 389
Message RAM................................................. 335
RDR
Transmission/Reception Data Registers
(RDR/TDR) ....................................... 433
RDX/WRX
CSX → RDX/WR1X,WR0X Setup and RDX/
WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH) ........ 212
Setting of CSX → RDX/WR1X,WR0X Setup
(TYP[3:0]=0101B, AWR=100BH) ........ 216
Read
How to Read the I/O Map ................................. 641
Port Data Direct Read Register (PDRD)............. 227
Read → Write Timing
Read → Write Timing
(TYP[3:0]=0000B, AWR=0048H)......... 207
Reading
Reading from the FIFO Buffer .......................... 398
Real Time Clock Registers
Real Time Clock Registers................................ 592
Reception
Acceptance Filter for Reception Messages ......... 393
Data Frame Reception ...................................... 393
Data Transmission/Reception to/from the Message
RAM ................................................. 389
Message Reception by the FIFO Buffer.............. 397
Reception Interrupt .......................................... 444
Reception Interrupt Generation
and Flag Set Timing ............................ 447
Reception Message Object Setting..................... 395
Reception Message Processing .......................... 396
Reception Operation......................................... 461
Reception Priority ............................................ 393
Transmission/Reception Data Registers
(RDR/TDR) ....................................... 433
Reception Interrupt
Reception Interrupt .......................................... 444
Reception Interrupt Generation
and Flag Set Timing ............................ 447
Recommended Setting
Recommended Setting Value ............................ 614
Register
0-detection Data Register (BSD0)...................... 282
10-bit Slave Address Mask Register (ITMK) ...... 503
10-bit Slave Address Register (ITBA)................ 502
16-bit Free-run Timer Registers......................... 533
16-bit Reload Timer Registers........................... 519
INDEX
1-detection Data Register (BSD1)...................... 282
7-bit Slave Address Mask Register (ISMK) ........ 506
7-bit Slave Address Register (ISBA).................. 505
A/D Control Status Register 0 (ADCS0) ............ 610
A/D Control Status Register 1 (ADCS1) ............ 607
A/D Enable Register (ADER) ........................... 606
AD Bit in the Serial Control Register (SCR) ....... 479
Address Register Specification .......................... 314
Baud Rate/Reload Counter Register
(BGR)........................................ 441, 442
Bit Configuration of the 16-bit Reload Register
(TMRLR)........................................... 526
Bit Configuration of the 16-bit Timer Register
(TMR) ............................................... 525
Bit Configuration of the Compare Register
(OCCP0 to OCCP3) ............................ 552
Bit Configuration of the Control Register
(OCS01,OCS23) ................................. 553
Bit Configuration of the Control Status Register
(TMCSR) ........................................... 520
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Bit Configuration of the Input Capture Control
Register (ICS01,ICS23) ....................... 545
Bit Configuration of the Input Capture Register
(IPCP0 to IPCP3)................................ 544
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 251
Bus Control Register (IBCR) ............................ 492
Bus Status Register (IBSR) ............................... 488
Cache Size Register (ISIZE) ............................. 135
Changed Point Detection Data Register
(BSDC).............................................. 283
CLKR: Clock Source Control Register................. 95
Clock Control Register (ICCR) ......................... 500
Clock Prescaler Register ................................... 341
Condition Code Register (CCR) .......................... 38
Configuration of General Control Register 10
(GCN10) ............................................ 575
Configuration of the General Control Register 11
(GCN11) ............................................ 578
Configuration of the General Control Register 2
(GCN20,GCN21) ................................ 581
Configuration of the PPG Cycle Setting Register
(PCSR) .............................................. 572
Configuration of the PPG Duty Setting Register
(PDUT).............................................. 573
Configuration of the PPG Timer Register
(PTMR) ............................................. 574
Conversion Time Setting Register ..................... 613
CSCFG: Clock Source Configuration
Register.............................................. 103
CTBR: Time-base Counter Clear Register ............ 94
Data Direction Register (DDR) ......................... 226
Data Register (ADCR1, ADCR0) ...................... 612
Data Register (IDAR)....................................... 507
Details of External Interrupt Controller
Registers.............................................266
Details of the Interrupt Controller Registers ........250
Detection Result Register (BSRR)......................283
DICR (Delayed Interrupt Module Register).........278
DIVR0: Base Clock Division Setting
Register 0..............................................98
DIVR1: Base Clock Division Setting
Register 1............................................101
Extended Communication Control Register
(ECCR) ..............................................438
Extended Status/Control Register (ESCR)...........435
Functions of the Compare Register
(OCCP0 to OCCP3).............................552
General Control Registers..........................342, 343
General-purpose Registers ...................................36
Hardware Watchdog Timer Period Register ........159
Hardware Watchdog Timer Register...................158
Hour/Minute/Second Register ............................599
I2C Interface Register Overview ........................487
I2C Interface Registers ......................................483
Input Capture Registers .....................................543
Instruction Cache Control Register (ICHCR).......135
Interrupt Control Register (ICR) Bit Structure .......54
Interrupt Controller Registers.............................247
Interrupt Level Mask Register (ILM)....................41
LIN-UART Registers ........................................422
List of the External Interrupt Controller
Registers.............................................264
List of the General Control Registers ..................337
List of the Message Handler Registers ................340
List of the Message Interface Registers ...............338
Message Handler Register .................................377
Message Handler Registers................................342
Message Interface Registers...............................342
Mode Register (MODR)......................................66
Multiply & Divide Registers ................................43
Notes on Setting Registers .................................291
Notes on the PS Register .....................................22
Output Compare Unit Registers .........................551
Overview of A/D Converter Registers ................604
Overview of External Bus Interface
Registers.............................................167
Overview of the DMAC Registers......................289
Port Data Direct Read Register (PDRD)..............227
Port Data Register (PDR) ..................................226
Port Pull-up and Pull-down Control Register .......244
Port Pull-up and Pull-down Enable Register ........243
PPG Registers ..................................................565
Prescaler Register .............................................342
Real Time Clock Registers ................................592
Register Configuration
.................344, 347, 350, 351, 353, 355,
357, 359, 362, 367, 368, 369,
370, 378, 380, 382, 384, 386
Register Configuration of Area Configuration
Register (ACR0 to ACR3) ....................169
693
INDEX
Register Configuration of Area Wait Register
(AWR0 to AWR4) .............................. 175
Register Configuration of ASR0 to ASR4
(Area Select Register) .......................... 168
Register Configuration of Cache Enable Register
(CHER) .............................................. 185
Register Configuration of Chip Select Enable Register
(CSER) .............................................. 184
Register Configuration of
IOWR0 to IOWR2 .............................. 181
Register Configuration of Terminal and Timing
Control Register (TCR)........................ 186
Register Functions
......................... 344, 347, 350, 352, 354,
355, 357, 359, 362, 370,
379, 381, 383, 385, 386
Register Group................................................. 335
Register List of Bit Search Module .................... 281
Register List of Delayed Interrupt Module .......... 277
Register List of External Bus Interface ............... 166
Registers ......................................................... 604
Registers in the Interval Timer........................... 126
RSRR: Reset Source Register and Watchdog Timer
Control Register .................................... 85
Serial Control Register (SCR)............................ 424
Serial Mode Register (SMR) ............................. 427
Serial Status Register (SSR) .............................. 430
Setting of Temporary Stop
by Writing to the Control Register
(Set Independently for Each Channel or All
Channels Simultaneously) .................... 321
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH) ........................................... 615
STCR: Standby Control Register ......................... 88
Structure of the Control Status Registers
(PCNH, PCNL) ................................... 568
Sub-second Registers........................................ 597
System Condition Code Register (SCR) ............... 40
Table Base Register (TBR)............................ 42, 56
TBCR: Time-base Counter Control Register ......... 91
Timer Control Register
(WTCRH, WTCRL) ............................ 595
Timer Control Status Register (TCCS) ............... 535
Timer Data Register (TCDT)............................. 534
Transfer Count Register and Reload
Operation ........................................... 316
Transmission/Reception Data Registers
(RDR/TDR) ........................................ 433
WPR:Watchdog Reset Generation Postponement
Register ................................................ 97
Relation Ship
Relation Ship Between Data Bus Width and Control
Signal................................................. 190
694
Release
Operation Initialization Reset (RST) Release
Sequence.............................................. 73
Setting Initialization Reset (INIT) Release
Sequence.............................................. 73
Reload
16-bit Reload Timer Registers........................... 519
Baud Rate/Reload Counter Register
(BGR)........................................ 441, 442
Bit Configuration of the 16-bit Reload Register
(TMRLR)........................................... 526
Block Diagram of 16-bit Reload Timer .............. 518
Multiple Activation Using a Trigger from the Reload
Timer................................................. 590
Overview of the 16-bit Reload Timer (RLT)....... 518
Reload Operation ............................................. 312
Transfer Count Register and Reload
Operation ........................................... 316
Reload Counter
Baud Rate/Reload Counter Register
(BGR)........................................ 441, 442
Reload Register
Bit Configuration of the 16-bit Reload Register
(TMRLR)........................................... 526
Reload Timer
16-bit Reload Timer Registers........................... 519
Block Diagram of 16-bit Reload Timer .............. 518
Multiple Activation Using a Trigger from the Reload
Timer................................................. 590
Overview of the 16-bit Reload Timer (RLT)....... 518
Remote Frame
Remote Frame ................................................. 394
Request
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .................... 252
Example of Using the Hold Request Cancellation
Request Function (HRCL) ................... 261
External Interrupt Request Level ....................... 271
Hold Request Cancellation Request ................... 259
Internal Peripheral Request ............................... 309
Software Request ............................................. 309
Transfer Request Acceptance
and the Transfer .................................. 319
Transfer Stop Requests from Peripheral
Circuits .............................................. 323
Transmission Interrupt Request Generation
Timing............................................... 450
Reset
Hardware Watchdog Reset.................................. 72
INITX Pin Input
(Setting Initialization Reset Pin) ............. 71
Operation Initialization Reset (RST) .................... 70
Operation Initialization Reset (RST) Release
Sequence.............................................. 73
Ordinary Reset Operation ................................... 76
Overview of Reset (Device Initialization)............. 69
INDEX
Reset Timing for Watchdog Timer
Overflow............................................ 160
RSRR: Reset Source Register and Watchdog Timer
Control Register.................................... 85
Setting Initialization Reset (INIT)........................ 70
Setting Initialization Reset (INIT) Release
Sequence.............................................. 73
Synchronous Reset Operation.............................. 76
Watchdog Reset ................................................. 72
WPR:Watchdog Reset Generation Postponement
Register................................................ 97
Writing to the SRST Bit in STCR
(Software Reset) ................................... 71
Reset Operation
Ordinary Reset Operation ................................... 76
Synchronous Reset Operation.............................. 76
Reset Source Register
RSRR: Reset Source Register and Watchdog Timer
Control Register.................................... 85
Restore
Save and Restore Processing ............................. 286
Restrictions
Restrictions on a Little Endian Area................... 196
Restrictions on the Operation
with a Delay Slot .................................. 49
Result
Detection Result Register (BSRR) ..................... 283
RETI
Operation of the RETI Instruction........................ 62
Return
Return from Standby Mode (Sleep/Stop) ............ 260
Return Pointer (RP)............................................ 42
Wait Time after Return from the Stop Mode ......... 80
Return Pointer
Return Pointer (RP)............................................ 42
Returning
Returning from EIT............................................ 51
ROM
Bus Mode 1 (Built-in ROM &
External Bus Mode) .............................. 65
Bus Mode 2 (External ROM &
External Bus Mode) .............................. 65
RP
Return Pointer (RP)............................................ 42
RSRR
RSRR: Reset Source Register and Watchdog Timer
Control Register.................................... 85
RST
Operation Initialization Reset (RST) .................... 70
Operation Initialization Reset (RST) Release
Sequence.............................................. 73
S
Save
Save and Restore Processing..............................286
SCR
AD Bit in the Serial Control Register (SCR) .......479
Serial Control Register (SCR) ............................424
System Condition Code Register (SCR)................40
Selecting the Baud Rate
Selecting the Baud Rate for the LIN-UART ........451
Selecting Transfer Sequence
Selecting Transfer Sequence ..............................310
Selection
Selection of Clock ..............................................77
Selection of Oscillation Stabilization Wait
Time.....................................................75
Selection of Pin Input Level...............................242
Serial Control Register
AD Bit in the Serial Control Register (SCR) .......479
Serial Control Register (SCR) ............................424
Serial Mode Register
Serial Mode Register (SMR)..............................427
Serial Status Register
Serial Status Register (SSR) ..............................430
Setting
Changing Operation Settings .............................478
Communication Mode Setting............................478
Configuration of the PPG Cycle Setting Register
(PCSR) ...............................................572
Configuration of the PPG Duty Setting Register
(PDUT) ..............................................573
Conversion Time Setting Register ......................613
CSX → RDX/WR1X,WR0X Setup and RDX/
WR1X,WR0X → CSX Hold Setting
(TYP[3:0]=0000B, AWR=000BH).........212
CSX Delay Setting
(TYP[3:0]=0000B, AWR=000CH).........211
DIVR0: Base Clock Division Setting
Register 0..............................................98
DIVR1: Base Clock Division Setting
Register 1............................................101
Example of Setting ASR and ASZ[1:0]...............188
Examples of Baud Rate Settings by Machine Clock
Frequencies.........................................454
External Bus Setting ...........................................22
Function Settings ..............................................472
Initializing the Division Ratio Setting ...................83
INITX Pin Input
(Setting Initialization Reset Pin)..............71
Notes on Setting Registers .................................291
Operation Setting..............................................478
Procedure for Setting External Bus Interface .......220
Reception Message Object Setting .....................395
Recommended Setting Value .............................614
Setting Initialization Reset (INIT) ........................70
695
INDEX
Setting Initialization Reset (INIT) Release
Sequence .............................................. 73
Setting LIN Slave............................................. 478
Setting of CSX → RDX/WR1X,WR0X Setup
(TYP[3:0]=0101B, AWR=100BH) ........ 216
Setting of Temporary Stop
by Writing to the Control Register
(Set Independently for Each Channel or All
Channels Simultaneously) .................... 321
Setting the Division Ratio ................................... 83
Setting the Test Mode ....................................... 404
Start Channel Setting Register (ADSCH) and
End Channel Setting Register
(ADECH) ........................................... 615
Transmission Message Object Setting ................ 391
Wait Time after Setting Initialization ................... 79
Setting Procedures
Setting Procedures............................................ 141
Setting Register
DIVR0: