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Revised 24/7/13
‘Iris-SDL’
2D Graphics Engine
Hardware Manual
Fujitsu Semiconductor Europe GmbH
Version: 1.30
July 24, 2013
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Preface
Preface
Intention and Target Audience of this Document
This document describes and gives you detailed insight to the stated Fujitsu semiconductor product.
The Iris-SDL 2D Graphics Engine is an important component of the Titan device and incorporates
many new features.
This target audience of this document is engineers developing products which will use the Iris-SDL device. It describes the function and operation of the 2D Graphics Engine. Please read this document
carefully.
Trademarks
PrimeCell is a trademarks of ARM Limited.
System names and the product names which appear in this document are the trademarks of the respective company or organization.
Related Literature
This document refers to functionality described in official external (ARM) specifications. These are:
 AXI Read Masters:Please refer to [3] ARM® AMBA® AXI Protocol Specification v1.0.
 AXI Write Masters:Please refer to [3] ARM® AMBA® AXI Protocol Specification v1.0.
 AHB-Lite Masters:Please refer to [2] ARM® AMBA® Specification Rev 2.0.
 AXI Read Slaves:Please refer to [3] ARM® AMBA® AXI Protocol Specification v1.0.
 AXI Write Slaves:Please refer to [3] ARM® AMBA® AXI Protocol Specification v1.0.
 AHB-Lite Slaves:Please refer to [2] ARM® AMBA® Specification Rev 2.0.
 PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Please contact ARM Limited or check the respective website for these documents.
Fujitsu Semiconductor Europe GmbH
Document Revision History
Revised 24/7/13
Document Revision History
Version
Date
Editor
Comment
1.30
23.07.2013
R. v. Reitzenstein
Reset value for all Registers
GFXTCON_DIR_PINx_CTRL revised.
Register Overview table updated
Register Description for Registers GFXTCON_DIR_SPG0MaskOFF to
GFXTCON_DIR_SPG11MaskOFF added
1.20
24.07.2012
Andy von Treuberg
Changed description of ChanSel bitfield in
GFXTCON_DIR_PIN[0...12]_CTRL.
Units 0 and 12 have a different description to units 11:1.
1.10
18.06.2012
Andy von Treuberg
Increase internal VRAM size from 512K to 1M.
Corrected bus_clk speed from 128 MHz to 160 MHz
1.00
02.02.2012
Andy von Treuberg
First version
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Document Revision History
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Preface.....................................................................................................................................................1-2
Document Revision History...................................................................................................................1-1
Chapter 1: Iris-SDL (2D Graphics Engine) ............................................................................................1-1
1.1 Outline of Iris-SDL 2D Graphics Engine ..............................................................................................1-1
1.2 Features of the Iris-SDL 2D Graphics Engine .....................................................................................1-2
1.2.1 General Features ........................................................................................................................1-2
1.2.2 Display Output Features..............................................................................................................1-2
1.2.3 Blit Operation Features ...............................................................................................................1-3
1.2.4 Video Memory Features ..............................................................................................................1-3
1.2.5 AXI Interconnect Bus Matrix Features.........................................................................................1-3
1.2.6 Display Signature Features .........................................................................................................1-4
1.2.7 Command Sequencer Features ..................................................................................................1-4
1.2.8 Quad SPI Features......................................................................................................................1-4
1.3 Block Diagram of Iris-SDL ...................................................................................................................1-5
1.4 Iris-SDL Register Overview .................................................................................................................1-5
1.5 Memory layout of Iris-SDL Address Space..........................................................................................1-6
1.6 Iris-SDL System Events and Interrupt Mappings...............................................................................1-30
Chapter 2: Iris-SDL Programming Guide ..............................................................................................2-1
2.1 Basic Setup .........................................................................................................................................2-1
2.1.1 Hardware Reset ..........................................................................................................................2-1
2.1.2 Clock Settings .............................................................................................................................2-1
2.1.3 Register Lock/Unlock...................................................................................................................2-2
2.1.4 Bus Matrix Setup .........................................................................................................................2-3
2.1.5 Software Resets ..........................................................................................................................2-4
2.1.6 Interrupt Settings .........................................................................................................................2-4
2.2 Blit Operation.......................................................................................................................................2-5
2.2.1 Pipeline Configuration .................................................................................................................2-5
2.2.2 Components Configuration..........................................................................................................2-6
2.2.3 Blit Control Flow ..........................................................................................................................2-6
2.2.4 Extended Configurations .............................................................................................................2-7
2.2.5 Performance Measurement .........................................................................................................2-7
2.3 Display Operation ................................................................................................................................2-7
2.3.1 Clock Settings .............................................................................................................................2-8
2.3.2 Layer Configuration .....................................................................................................................2-8
2.3.3 Panel Configuration .....................................................................................................................2-9
2.3.4 Synchronization Techniques .......................................................................................................2-9
2.3.4.1 Single Display Buffer .............................................................................................................2-9
2.3.4.2 Dual Display Buffers..............................................................................................................2-9
2.3.4.3 Single Buffer with Blit During Blank.....................................................................................2-10
2.3.5 Control Flow ..............................................................................................................................2-10
2.3.6 Signature Check (Safety) ..........................................................................................................2-10
2.3.7 Setup Constraints ......................................................................................................................2-12
2.3.7.1 Operation Mode...................................................................................................................2-12
2.3.7.2 Rotated Mode......................................................................................................................2-12
2.3.7.3 Display Mode.......................................................................................................................2-13
2.3.7.4 Common Setup ...................................................................................................................2-13
2.3.7.5 General Recommendations.................................................................................................2-13
2.4 Command Sequencer Operation.......................................................................................................2-13
2.4.1 Command Lists .........................................................................................................................2-14
2.4.2 Event Synchronization...............................................................................................................2-14
2.5 External SPI Memories......................................................................................................................2-14
2.5.1 Clock Settings ...........................................................................................................................2-15
2.5.2 Device Setup .............................................................................................................................2-15
Chapter 3: Global Control Unit (GCTR) .................................................................................................3-1
3.1 Clock Generation, Distribution and Domains.......................................................................................3-1
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3.1.1 Pixel Clock Setup ........................................................................................................................3-4
3.2 Iris-SDL Interrupts ...............................................................................................................................3-6
3.2.1 Interrupt Control Flow ..................................................................................................................3-9
3.3 Iris-SDL Reset Controller...................................................................................................................3-10
Chapter 4: AXI Interconnect Bus (AIC)..................................................................................................4-1
4.1 Feature List..........................................................................................................................................4-2
4.1.1 AXI Interconnect Matrix Features ................................................................................................4-2
4.1.1.1 Configurable arbitration scheme ...........................................................................................4-2
4.1.1.2 Arbiting Scheme ....................................................................................................................4-2
4.1.1.3 Disabling Slave Modules .......................................................................................................4-3
4.1.1.4 AXI Interconnect Error Handling............................................................................................4-3
4.1.1.5 VRAM AXI Interface (U_VRAM0) ..........................................................................................4-3
Chapter 5: Pixel Engine (PIX) .................................................................................................................5-1
5.1 Pixel Engine Features .........................................................................................................................5-1
5.2 Pixel Engine Architecture ....................................................................................................................5-1
5.3 Checking the pipeline location of processing units..............................................................................5-2
5.4 Processing ‘kick’ signal........................................................................................................................5-3
5.5 Processing units enabled status..........................................................................................................5-3
5.6 Pixel Engine synchronization...............................................................................................................5-3
5.6.1 Synchronization procedure..........................................................................................................5-4
5.7 Handling separate Display and Blit Pipelines ......................................................................................5-6
5.8 Emptying the Pixel Engine for power down .........................................................................................5-9
5.9 New pipeline setup ..............................................................................................................................5-9
5.10 Relocating processing modules between the display and blit pipelines ............................................5-9
5.10.1 Removing a module from the display pipeline .....................................................................5-9
5.10.2 Removing a module from the blit pipeline ...............................................................................5-10
Chapter 6: Pixel Engine (PIX) Fetch Unit...............................................................................................6-1
6.1 Features of the Fetch Units .................................................................................................................6-2
6.2 Fetch Unit Input Data Format ..............................................................................................................6-2
6.3 Fetch Unit Co-ordinate System ...........................................................................................................6-3
6.4 Flexible AXI Interconnect Buffering .....................................................................................................6-3
6.5 Main Control Logic...............................................................................................................................6-3
6.6 Rasterizer for pixel fetching via the AXI Interconnect Bus...................................................................6-4
6.7 Color Conversion.................................................................................................................................6-4
6.8 Color Multiplication ..............................................................................................................................6-5
6.9 Optional: Run Length Decoding ..........................................................................................................6-5
6.10 Optional: Rotation with Nearest and Bilinear Filtering .......................................................................6-6
6.11 Fetch Unit Performance Considerations............................................................................................6-7
Chapter 7: Pixel Engine (PIX) CLUT Unit...............................................................................................7-1
7.1 Clut Unit Block Diagram ......................................................................................................................7-2
7.2 Neutral Mode Operation ......................................................................................................................7-2
7.3 LUT Mode Operation ...........................................................................................................................7-2
7.4 10 bit Index Mode Operation ...............................................................................................................7-3
7.5 RGBA Index Mode Operation..............................................................................................................7-3
7.6 Output Dithering ..................................................................................................................................7-3
7.7 Important Notes ...................................................................................................................................7-4
Chapter 8: Pixel Engine (PIX) Matrix......................................................................................................8-1
8.1 Matrix Block Diagram ..........................................................................................................................8-1
8.2 Neutral Mode Operation ......................................................................................................................8-1
8.3 Matrix Mode Operation ........................................................................................................................8-1
8.4 Pre multiplication Mode Operation ......................................................................................................8-2
Chapter 9: Pixel Engine (PIX) ROP ........................................................................................................9-1
9.1 ROP Interrupts.....................................................................................................................................9-1
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9.2 ROP Unit Restrictions..........................................................................................................................9-1
9.3 ROP Unit Processing Flow ..................................................................................................................9-2
Chapter 10: Pixel Engine (PIX) BlitBlend Unit ....................................................................................10-1
10.1 Shadowed Configuration .................................................................................................................10-1
10.2 Operation Modes .............................................................................................................................10-2
10.3 BlitBlend Interrupts ..........................................................................................................................10-2
Chapter 11: Pixel Engine (PIX) Layerblend .........................................................................................11-1
11.1 Features of the Layerblend Unit ......................................................................................................11-1
11.2 Layerblend Unit Functional Description...........................................................................................11-2
11.3 Blend mode .....................................................................................................................................11-3
11.4 Primary Transparent Blending Mode...............................................................................................11-4
11.5 Secondary Transparent Blending Mode ..........................................................................................11-4
11.6 Neutral Mode ...................................................................................................................................11-4
11.7 Interrupt signal generation...............................................................................................................11-4
Chapter 12: Pixel Engine (PIX) Store Unit ...........................................................................................12-1
12.1 Operation of the Store Unit..............................................................................................................12-1
12.2 Store unit Interrupt generation.........................................................................................................12-1
12.3 Fast fill mode ...................................................................................................................................12-2
12.4 Output Data Format.........................................................................................................................12-2
12.5 Store Unit Processing......................................................................................................................12-3
Chapter 13: Pixel Engine (PIX) Extdst .................................................................................................13-1
13.1 Extdst Block Diagram ......................................................................................................................13-1
13.2 Kick Signal Generation ....................................................................................................................13-1
13.3 Interrupt signal generation...............................................................................................................13-3
Chapter 14: Display Controller (DISP) .................................................................................................14-1
14.1 Display Controller Overview ............................................................................................................14-1
14.1.1 Timing Generator ....................................................................................................................14-1
14.1.2 Clock Domains and Concept ...................................................................................................14-3
14.1.3 FIFO and FIFO Control............................................................................................................14-3
14.1.4 Dither Unit ...............................................................................................................................14-4
14.1.5 Display Controller Generated Interrupts ..................................................................................14-4
14.1.6 Pixel Engine Synchronization ..................................................................................................14-4
14.1.7 Signature Error Handling in the Display Controller..................................................................14-5
14.1.8 Display Controller Output Signal Timing..................................................................................14-5
Chapter 15: Timing Controller (TCON) ................................................................................................15-1
15.1 Features of the Timing Controller Module .......................................................................................15-1
15.2 The Pixel Data Interface ................................................................................................................15-2
15.3 TCON Processing Flow and Operation Modes ...............................................................................15-3
15.3.1 TCON Operation Modes..........................................................................................................15-3
15.3.2 Resetting the TCON ................................................................................................................15-4
15.3.3 RSDS Bitmap Module (RBM) ..................................................................................................15-4
15.3.4 Inverting the RSDS channel order...........................................................................................15-8
15.3.5 TCON Timing Signal Generators (TSIG)...............................................................................15-10
15.3.5.1 Position Matching Method (First Stage Signal Forming) .................................................15-11
15.3.5.2 Sequence Matching Method (First Stage Signal Forming)..............................................15-12
15.3.5.3 Combining First Stage Sync Signals ...............................................................................15-13
15.3.5.4 Sync Signal Delay Adjustment ........................................................................................15-14
15.3.5.5 Clock Delay Adjustment ..................................................................................................15-14
15.3.5.6 Inversion Signal Generation ............................................................................................15-14
Chapter 16: Signature Unit (SIG)..........................................................................................................16-1
16.1 Features of the SIG unit ..................................................................................................................16-1
16.2 Evaluation and Mask Windows........................................................................................................16-2
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16.3 Signature A (CRC-32 Signature) .....................................................................................................16-3
16.4 Signature B (Sum of Color Values Signature) .................................................................................16-4
16.5 Programmable Evaluation Window (Position and Size) ..................................................................16-4
16.6 Automatic Monitoring and Interrupt .................................................................................................16-4
16.7 Self-Restoring Error Counter ...........................................................................................................16-5
16.8 Key Protection .................................................................................................................................16-5
16.9 Control Flow Interrupts ....................................................................................................................16-5
16.10 Programmable Input Picture Source Limitations ...........................................................................16-5
16.11 Signature Unit and Iris-SD Interrupts.............................................................................................16-5
16.12 Example Pseudo Code for Signature Generation .........................................................................16-6
Chapter 17: Command Sequencer (CMDSEQ)....................................................................................17-1
17.1 Features of the Command Sequencer unit......................................................................................17-1
17.2 Command Sequencer Process Flow ...............................................................................................17-1
17.3 Command Sequencer Status Register ............................................................................................17-2
17.4 Command Sequencer Watchdog Functionality ...............................................................................17-2
17.5 Command Sequencer Command Buffer .........................................................................................17-2
17.6 Command Sequencer Instruction Set..............................................................................................17-3
17.6.0.1 NOP - No Operation ..........................................................................................................17-4
17.6.0.2 CALL - Call to a command list...........................................................................................17-5
17.6.0.3 RET - Return from command list.......................................................................................17-6
17.6.0.4 WRITE - Write data to buffer .............................................................................................17-7
17.6.0.5 COPY - Copy buffer ..........................................................................................................17-8
17.6.0.6 SAVE - Save register values .............................................................................................17-9
17.6.0.7 RESTORE - Restore register values from memory.........................................................17-10
17.6.0.8 SYNC - Synchronize .......................................................................................................17-11
17.6.0.9 WDS - Watchdog Setup/Disable/Enable .........................................................................17-12
17.6.0.10 WDR - Watchdog reset .................................................................................................17-13
17.7 Initializing the Watchdog Timer .....................................................................................................17-14
17.8 SAVE and RESTORE....................................................................................................................17-14
17.9 Operation Mode.............................................................................................................................17-14
17.10 Restart after detecting an illegal instruction.................................................................................17-14
17.11 Overlapping buffers .....................................................................................................................17-14
Chapter 18: High Speed SPI Interface (SPI) ........................................................................................18-1
18.1 Features of HS_SPI.........................................................................................................................18-1
18.2 Block diagram of HS_SPI ................................................................................................................18-1
18.3 HS_SPI Operation ...........................................................................................................................18-2
18.3.1 Operation Modes .....................................................................................................................18-2
18.3.2 Clocking modes .......................................................................................................................18-3
18.3.3 Retimed clock ..........................................................................................................................18-6
18.3.4 Serial clock frequency .............................................................................................................18-6
18.3.5 SPI protocol .............................................................................................................................18-7
18.3.6 Shift direction...........................................................................................................................18-8
18.3.7 Safe synchronisation of internal data ....................................................................................18-10
18.3.8 Debug mode ..........................................................................................................................18-14
18.4 Direct mode ...................................................................................................................................18-14
18.4.1 Internal FIFOs .......................................................................................................................18-14
18.4.2 Service requests....................................................................................................................18-17
18.4.3 SPI transfers in master mode ................................................................................................18-19
18.4.4 SPI transfers in slave mode...................................................................................................18-21
18.5 Command sequencer mode ..........................................................................................................18-21
18.5.1 Memory mapping...................................................................................................................18-21
18.5.2 Initiation of command sequence............................................................................................18-24
18.5.3 AHB idle timeout....................................................................................................................18-25
18.5.4 Configuration of command sequence in CSR .......................................................................18-25
18.6 Address map of HS_SPI................................................................................................................18-28
18.6.1 Arrangement of HS_SPI address space in memory..............................................................18-28
18.7 Notes on using HS_SPI.................................................................................................................18-29
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18.7.1 General usage notes .............................................................................................................18-29
18.7.2 Steps in programming the HS_SPI module...........................................................................18-30
18.7.3 Using the HS_SPI in direct mode of operation ......................................................................18-31
18.7.4 Using the memory mapped memories...................................................................................18-37
18.7.5 Programmer’s flowchart.........................................................................................................18-38
18.7.6 Timing diagram for command sequencer ..............................................................................18-39
Chapter 19: Register Overview ............................................................................................................19-1
Chapter 20: Iris-SDL Register Descriptions........................................................................................20-1
20.1 Register Descriptions, Global Addresses ........................................................................................20-2
20.2 Iris-SDL Register Protection (Locking/Unlocking) ...........................................................................20-4
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Iris-SDL (2D Graphics Engine)
Revised 24/7/13
Chapter 1: Iris-SDL (2D Graphics Engine)
This chapter describes the functions and operation of the ‘Iris-SDL’ 2D Graphics Engine.
1.1
Outline of Iris-SDL 2D Graphics Engine
’Iris-SDL’ is the 2D graphics subsystem used in the ARM® Cortex™-R4 based Titan SoC (Systemon-Chip). Its main components are listed below:

GCTR – Iris-SDL Global Control.

AIC – Iris-SDL AXI Interconnect.

PIX – Pixel Engine (for blit operations and display pre-processing).

DISP – Display Controller.

TCON – Timing Controller.

SIG – Signature Unit.

CMDSEQ – Command Sequencer.

SPI – High-Speed SPI.

VRAM - AXI Interface for embedded video memory.

RAM256 - Large-scale, single-port SRAM (32K x 64-bit = 256 KB)
As the Iris-SDL 2D Graphics Engine provides a display interface, embedded video memory and
base level 2D acceleration features, it is ideal for automotive applications such as instrument clusters and dashboards in the performance mid-range as well as for industrial applications.
The two pixel processing pipelines (display/blit) are configurable and use several sub-components.
These can be hooked up to the processing flow, configured for use and re-arranged within the flows,
making the Iris-SDL Graphics Engine very versatile.
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1.2
Iris-SDL (2D Graphics Engine)
Features of the Iris-SDL 2D Graphics Engine
This chapter summarizes the features of the Iris-SDL 2D Graphics Engine.
1.2.1 General Features

Controller for external graphics display.

Accelerator for 2D block image transfer (blit) operations.

Embedded SRAM video memory.

Multilayer AXI bus matrix with external master and slave port.

Signature computation for display content (use: data integrity/safety requirements).

Command Sequencer for graphic operations.

Quad SPI (Serial Peripheral Interface) for external memory extensions.

Two processing pipelines (blit/display).

Maximum core system clock frequency: 128 MHz.
1.2.2 Display Output Features
1-2

Supports video modes with a pixel clock of max. 40 MHz.

1024 pixels maximum frame width and height.

Supports pixel data and clock output in RSDS and TTL mode.

Freely programmable waveforms with 12 pulse generators.

Configurable phase for display clock.

One background and 3 alpha blended foreground layers.

One dedicated alpha layer.

Packed buffer formats in memory with 1, 2, 4, 8, 16, 24 and 32 bpp.

Individual size for R, G, B and A component from 0 to 8 bits.

Configurable bit offset in pixel words for each component (color component shift)

Background layer can be run-length encoded.

Transparent color for foreground layers.

RGB lookup table for non-linear color correction (e.g. for gamma correction).

Dithering for displays with low color resolution.

Horizontal and vertical display flip.

90°, 180° and 270° display rotation.
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Iris-SDL (2D Graphics Engine)
Revised 24/7/13
1.2.3 Blit Operation Features

1024 pixels maximum frame width and height.

Packed buffer formats in memory with 1, 2, 4, 8, 16, 24 and 32 bpp.

Individual size for R, G, B and A component from 0 to 8 bits.

Individual bit offset in pixel word for each component.

Pre-multiplication of Alpha on RGB components.

Pre-multiplication of constant alpha on per-pixel alphas.

Pre-multiplication of RGB components by a constant factor.

Horizontal and vertical buffer flip.

Image rotation by any angle.

Image upscaling and downscaling.

Sub pixel precise image re-sampling (bilinear).

All blending modes of OpenGL 2.0 and support for most of the OpenVG 1.0 standard.

Raster operations (ROP2 and ROP3).

Indexed mode with color palette.

Programmable matrix for linear color transformations.

One source image can be split into two planes (e.g. separate buffer for alpha).

One source image can be run-length encoded.

Clip window for source images.

Blit performance at 128 MHz bus clock (32 bpp, uncompressed):
- 256 MPix/s for blit fill.
- 128 MPix/s for blit copy, blend and 90/180/270° rotation.
- 32 MPix/s for bilinear filtered rotation and scale.
1.2.4 Video Memory Features

1 MB embedded SRAM.
1.2.5 AXI Interconnect Bus Matrix Features

ARM PL301 High-Performance Bus Matrix.

2 read and write layers with 64-bit data bus each.

Programmable priority for master devices.

Least Recently Granted (LRG) arbitration for masters with same priority.

Access to each slave device can be disabled.

Direct access to the bus matrix by external master and slave port.

Monitor for error responses sent by any slave device (interrupt notification).
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Iris-SDL (2D Graphics Engine)
1.2.6 Display Signature Features

Signature computation for display output.

Method is color summation or CRC-32.

Reference signature to detect display failure (support for safety standards).

Programmable clip window for rectangular sub display area.

Per-pixel bit mask for any shaped display sub area (using the dedicated alpha layer).

Lock and unlock mechanism for configuration registers.
1.2.7 Command Sequencer Features

Autonomous processing of command sequences.

Read and write operations to whole Iris-SDL system address space (memory, configuration
and host system resources).

Synchronization to system events.

Direct mode (host writes directly into memory-mapped command FIFO).

Indirect mode (commands are read from memory).
1.2.8 Quad SPI Features
1-4

Up to 4 GB external flash memory.

Support for single, dual and quad bit modes.

Memory mapped access to slave devices.
Fujitsu Semiconductor Europe GmbH
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1.3
Revised 24/7/13
Block Diagram of Iris-SDL
Figure 1-1: Iris-SDL Block diagram
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Iris-SDL Register Overview
Please refer to “Register Overview” for a complete list.
Fujitsu Semiconductor Europe GmbH
1-5
Revised 24/7/13
1.5
Iris-SDL (2D Graphics Engine)
Memory layout of Iris-SDL Address Space
The Iris-SDL Graphics Engine has a 4GB address space (using 32-bit addresses).
The MEMBASE and REGBASE parameters referred to in the following sections are the base addresses of the memory space and register space respectively:
MEMBASE: 0x5000 0000
REGBASE: 0x8000 0000
Figure 1-2: Memory layout of Iris-SDL registers
Host System
IRIS Memories (512 MB)
MEMBASE
IRIS
System
Address
Space
(4 GB)
Host System
REGBASE
IRIS Configuration (512 KB)
Host System
The following table shows the mapping of internal functional components of Iris-SDL in the Iris-SDL
memory and configuration regions:
Table 1-1: Iris-SDL Global Address Map Overview
1-6
Target
Address Space
SPI Memory Space
MEMBASE + 00000000 ... MEMBASE + 0FFFFFFF
VRAM0
MEMBASE + 10000000 ... MEMBASE + 100FFFFFF
Reserved
MEMBASE + 10100000 ... MEMBASE + 101FFFFF
Global Control
REGBASE + 00000000 ... REGBASE + 00000FFF
SPI Register Space
REGBASE + 00001000 ... REGBASE + 000013FF
Reserved
REGBASE + 00001400 ... REGBASE + 00001FFF
Command Sequencer
REGBASE + 00002000 ... REGBASE + 00002FFF
Timing Controller
REGBASE + 00003000 ... REGBASE + 00003FFF
Display Controller
REGBASE + 00004000 ... REGBASE + 00004FFF
Signature Unit
REGBASE + 00005000 ... REGBASE + 00005FFF
Interconnect
REGBASE + 00006000 ... REGBASE + 00006FFF
reserved
REGBASE + 00007000 ... REGBASE + 00007FFF
Pixel Engine
REGBASE + 00008000 ... REGBASE + 0000FFFF
HPM Arbiter
REGBASE + 00010000 ... REGBASE + 00010FFF
reserved
REGBASE + 00011000 ... REGBASE + 0007FFFF
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
Table 1-1: Iris-SDL Global Address Map Overview
Target
Address Space
00000000 ... FFFFFFFF
except
MEMBASE + 00000000 ... MEMBASE + 1FFFFFFF
and except
REGBASE + 00000000 ... REGBASE + 0007FFFF
Main System
Table 1-2: Memory layout of Iris-SDL Configuration registers
Address
(REGBASE + ...)
+3
+2
+1
+0
block
0x00000000
GFXGCTR_LockUnlock
00000000 00000000 00000000 00000000
Global Control
0x00000004
GFXCTR_LockStatus
00000000 00000000 00000000 00000001
Global Control
0x00000008
GFXGCTR_IntStatus0
00000000 00000000 00000000 00000000
Global Control
0x0000000C
GFXGCTR_IntStatus1
00000000 00000000 00000000 00000000
Global Control
0x00000010
GFXGCTR_IntEnable0
00000000 00000000 00000000 00000000
Global Control
0x00000014
GFXGCTR_IntEnable1
00000000 00000000 00000000 00000000
Global Control
0x00000018
GFXGCTR_IntClear0
00000000 00000000 00000000 00000000
Global Control
0x0000001C
GFXGCTR_IntClear1
00000000 00000000 00000000 00000000
Global Control
0x00000020
GFXGCTR_IntPreset0
00000000 00000000 00000000 00000000
Global Control
0x00000024
GFXGCTR_IntPreset1
00000000 00000000 00000000 00000000
Global Control
0x00000028
GFXGCTR_IntMap0
00000000 00000000 00000000 00000000
Global Control
0x0000002C
GFXGCTR_IntMap1
00000000 00000000 00000000 00000000
Global Control
0x00000030
GFXGCTR_NmiStatus
00000000 00000000 00000000 00000000
Global Control
0x00000034
GFXGCTR_NmiClear
00000000 00000000 00000000 00000000
Global Control
0x00000038
GFXGCTR_NmiPreset
00000000 00000000 00000000 00000000
Global Control
0x0000003C
GFXGCTR_CsIntStatus0
00000000 00000000 00000000 00000000
Global Control
0x00000040
GFXGCTR_CsIntStatus1
00000000 00000000 00000000 00000000
Global Control
0x00000044
GFXGCTR_CsIntEnable0
00000000 00000000 00000000 00000000
Global Control
Fujitsu Semiconductor Europe GmbH
1-7
Revised 24/7/13
0x00000048
GFXGCTR_CsIntEnable1
00000000 00000000 00000000 00000000
Global Control
0x0000004C
GFXGCTR_CsIntClear0
00000000 00000000 00000000 00000000
Global Control
0x00000050
GFXGCTR_CsIntClear1
00000000 00000000 00000000 00000000
Global Control
0x00000054
GFXGCTR_CsIntPreset0
00000000 00000000 00000000 00000000
Global Control
0x00000058
GFXGCTR_CsIntPreset1
00000000 00000000 00000000 00000000
Global Control
0x0000005C
GFXGCTR_SwReset
00000000 00000000 00000000 00000000
Global Control
0x00000060
GFXGCTR_ClockAdjust
00000000 00000000 00000000 11111111
Global Control
0x00000064 ...
0x00000FFF
Reserved
0x00001000
GFXSPIn_MCTRL
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001004
GFXSPIn_PCC0
00000000 00000001 00000000 00000000
SPI Register
Space
0x00001008
GFXSPIn_PCC1
00000000 00000001 00000000 00000000
SPI Register
Space
0x0000100C
GFXSPIn_PCC2
00000000 00000001 00000000 00000000
SPI Register
Space
0x00001010
GFXSPIn_PCC3
00000000 00000001 00000000 00000000
SPI Register
Space
0x00001014
GFXSPIn_TXF
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001018
GFXSPIn_TXE
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000101C
GFXSPIn_TXC
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001020
GFXSPIn_RXF
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001024
GFXSPIn_RXE
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001028
GFXSPIn_RXC
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000102C
GFXSPIn_FAULTF
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001030
GFXSPIn_FAULTC
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001034
0x00001038
1-8
Iris-SDL (2D Graphics Engine)
read0
00000000 00000000
GFXSPIn_DMT
RP
00000000
GFXSPIn_DMP
SEL
00000000
Reserved
GFXSPIn_DMD
MAEN
00000000
GFXSPIn_DMC
FG
00000001
SPI Register
Space
GFXSPIn_DMS
TOP
00000000
GFXSPIn_DMS
TART
00000000
SPI Register
Space
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
0x0000103C
0x00001040
0x00001044
Revised 24/7/13
GFXSPIn_DMBCS
00000000 00000000
GFXSPIn_DMBCC
00000000 00000000
GFXSPIn_DMSTATUS
00000000 00000000 00000000 00000000
read0
00000000 00000000
GFXSPIn_RXBI
TCNT
SPI Register
Space
SPI Register
Space
GFXSPIn_TXBI
TCNT
SPI Register
Space
0x00001048
GFXSPIn_RXSHIFT
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000104C
GFXSPIn_FIFOCFG
00000000 00000000 00000000 01110111
SPI Register
Space
0x00001050
GFXSPIn_TXFIFO0
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001054
GFXSPIn_TXFIFO1
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001058
GFXSPIn_TXFIFO2
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000105C
GFXSPIn_TXFIFO3
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001060
GFXSPIn_TXFIFO4
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001064
GFXSPIn_TXFIFO5
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001068
GFXSPIn_TXFIFO6
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000106C
GFXSPIn_TXFIFO7
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001070
GFXSPIn_TXFIFO8
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001074
GFXSPIn_TXFIFO9
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001078
GFXSPIn_TXFIFO10
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000107C
GFXSPIn_TXFIFO11
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001080
GFXSPIn_TXFIFO12
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001084
GFXSPIn_TXFIFO13
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001088
GFXSPIn_TXFIFO14
00000000 00000000 00000000 00000000
SPI Register
Space
0x0000108C
GFXSPIn_TXFIFO15
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001090
GFXSPIn_RXFIFO0
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001094
GFXSPIn_RXFIFO1
00000000 00000000 00000000 00000000
SPI Register
Space
0x00001098
GFXSPIn_RXFIFO2
00000000 00000000 00000000 00000000
SPI Register
Space
Fujitsu Semiconductor Europe GmbH
1-9
Revised 24/7/13
0x0000109C
GFXSPIn_RXFIFO3
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010A0
GFXSPIn_RXFIFO4
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010A4
GFXSPIn_RXFIFO5
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010A8
GFXSPIn_RXFIFO6
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010AC
GFXSPIn_RXFIFO7
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010B0
GFXSPIn_RXFIFO8
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010B4
GFXSPIn_RXFIFO9
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010B8
GFXSPIn_RXFIFO10
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010BC
GFXSPIn_RXFIFO11
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010C0
GFXSPIn_RXFIFO12
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010C4
GFXSPIn_RXFIFO13
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010C8
GFXSPIn_RXFIFO14
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010CC
GFXSPIn_RXFIFO15
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010D0
GFXSPIn_CSCFG
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010D4
GFXSPIn_CSITIME
00000000 00000000 11111111 11111111
SPI Register
Space
0x000010D8
GFXSPIn_CSAEXT
00000000 00000000 00000000 00000000
SPI Register
Space
0x000010DC
GFXSPIn_RDCSDC1
00000000 00000000
GFXSPIn_RDCSDC0
00000000 00000000
SPI Register
Space
0x000010E0
GFXSPIn_RDCSDC3
00000000 00000000
GFXSPIn_RDCSDC2
00000000 00000000
SPI Register
Space
0x000010E4
GFXSPIn_RDCSDC5
00000000 00000000
GFXSPIn_RDCSDC4
00000000 00000000
SPI Register
Space
0x000010E8
GFXSPIn_RDCSDC7
00000000 00000000
GFXSPIn_RDCSDC6
00000000 00000000
SPI Register
Space
0x000010EC
GFXSPIn_WRCSDC1
00000000 00000000
GFXSPIn_WRCSDC0
00000000 00000000
SPI Register
Space
0x000010F0
GFXSPIn_WRCSDC3
00000000 00000000
GFXSPIn_WRCSDC2
00000000 00000000
SPI Register
Space
0x000010F4
GFXSPIn_WRCSDC5
00000000 00000000
GFXSPIn_WRCSDC4
00000000 00000000
SPI Register
Space
0x000010F8
GFXSPIn_WRCSDC7
00000000 00000000
GFXSPIn_WRCSDC6
00000000 00000000
SPI Register
Space
0x000010FC
1 - 10
Iris-SDL (2D Graphics Engine)
GFXSPIn_MID
00000000 00000000 00000000 00000001
SPI Register
Space
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00001100 ...
0x00001FFF
Reserved
Reserved
0x00002000
GFXCMD_HIF0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Command
Sequencer
0x00002004 ...
0x000020FB
GFXCMD_HIF1 ... HIF62
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Command
Sequencer
0x000020FF
GFXCMD_HIF63
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Command
Sequencer
0x00002100
GFXCMD_Status
01000000 00000000 00000000 10000000
Command
Sequencer
0x00002104
GFXCMD_Control
00000000 00000000 00000000 00000000
Command
Sequencer
0x00002108
GFXCMD_BufferAddress
00000000 00000000 00000000 00000000
Command
Sequencer
0x0000201C
GFXCMD_BufferSize
00000000 00000000 00000000 10000000
Command
Sequencer
0x00002110
GFXCMD_WatermarkControl
00000000 01100000 00000000 00100000
Command
Sequencer
0x00002114 ...
0x00002FFF
Reserved
Reserved
0x00003000
GFXTCON_DIR_SSqCnts0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timing
Controller
0x00003004 ...
0x000030FB
GFXTCON_DIR_SSqCnts1 ... DIR_SSqCnts62
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timing
Controller
0x000030FF
GFXTCON_DIR_SSqCnts63
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timing
Controller
0x00003103 ...
0x000033FC
Reserved
Reserved
0x00003400
GFXTCON_DIR_SWreset
00000000 00000000 00000000 00000001
Timing
Controller
0x00003404
GFXTCON_DIR_SPG0PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003408
GFXTCON_DIR_SPG0MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000340C
GFXTCON_DIR_SPG0PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003410
GFXTCON_DIR_SPG0MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003414
GFXTCON_DIR_SPG1PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003418
GFXTCON_DIR_SPG1MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000341C
GFXTCON_DIR_SPG1PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003420
GFXTCON_DIR_SPG1MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003424
GFXTCON_DIR_SPG2PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003428
GFXTCON_DIR_SPG2MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
Fujitsu Semiconductor Europe GmbH
1 - 11
Revised 24/7/13
1 - 12
Iris-SDL (2D Graphics Engine)
0x0000342C
GFXTCON_DIR_SPG2PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003430
GFXTCON_DIR_SPG2MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003434
GFXTCON_DIR_SPG3PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003438
GFXTCON_DIR_SPG3MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000343C
GFXTCON_DIR_SPG3PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003440
GFXTCON_DIR_SPG3MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003444
GFXTCON_DIR_SPG4PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003448
GFXTCON_DIR_SPG4MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000344C
GFXTCON_DIR_SPG4PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003450
GFXTCON_DIR_SPG4MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003454
GFXTCON_DIR_SPG5PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003458
GFXTCON_DIR_SPG5MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000345C
GFXTCON_DIR_SPG5PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003460
GFXTCON_DIR_SPG5MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003464
GFXTCON_DIR_SPG6PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003468
GFXTCON_DIR_SPG6MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000346C
GFXTCON_DIR_SPG6PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003470
GFXTCON_DIR_SPG6MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003474
GFXTCON_DIR_SPG7PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003478
GFXTCON_DIR_SPG7MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000347C
GFXTCON_DIR_SPG7PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003480
GFXTCON_DIR_SPG7MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003484
GFXTCON_DIR_SPG8PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003488
GFXTCON_DIR_SPG8MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000348C
GFXTCON_DIR_SPG8PosOff
00000000 00000000 00000000 00000000
Timing
Controller
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00003490
GFXTCON_DIR_SPG8MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x00003494
GFXTCON_DIR_SPG9PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x00003498
GFXTCON_DIR_SPG9MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x0000349C
GFXTCON_DIR_SPG9PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034A0
GFXTCON_DIR_SPG9MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034A4
GFXTCON_DIR_SPG10PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x000034A8
GFXTCON_DIR_SPG10MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x000034AC
GFXTCON_DIR_SPG10PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034B0
GFXTCON_DIR_SPG10MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034B4
GFXTCON_DIR_SPG11PosOn
00000000 00000000 00000000 00000000
Timing
Controller
0x000034B8
GFXTCON_DIR_SPG11MaskOn
00000000 00000000 00000000 00000000
Timing
Controller
0x000034BC
GFXTCON_DIR_SPG11PosOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034C0
GFXTCON_DIR_SPG11MaskOff
00000000 00000000 00000000 00000000
Timing
Controller
0x000034C4
GFXTCON_DIR_SSqCycle
00000000 00000000 00000000 00000000
Timing
Controller
0x000034C8
GFXTCON_DIR_SMx0Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034CC
GFXTCON_DIR_SMx0FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034D0
GFXTCON_DIR_SMx1Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034D4
GFXTCON_DIR_SMx1FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034D8
GFXTCON_DIR_SMx2Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034DC
GFXTCON_DIR_SMx2FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034E0
GFXTCON_DIR_SMx3Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034E4
GFXTCON_DIR_SMx3FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034E8
GFXTCON_DIR_SMx4Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034EC
GFXTCON_DIR_SMx4FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034F0
GFXTCON_DIR_SMx5Sigs
00000000 00000000 00000000 00000000
Timing
Controller
Fujitsu Semiconductor Europe GmbH
1 - 13
Revised 24/7/13
1 - 14
Iris-SDL (2D Graphics Engine)
0x000034F4
GFXTCON_DIR_SMx5FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x000034F8
GFXTCON_DIR_SMx6Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x000034FC
GFXTCON_DIR_SMx6FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x00003500
GFXTCON_DIR_SMx7Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x00003504
GFXTCON_DIR_SMx7FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x00003508
GFXTCON_DIR_SMx8Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x0000350C
GFXTCON_DIR_SMx8FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x00003510
GFXTCON_DIR_SMx9Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x00003514
GFXTCON_DIR_SMx9FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x00003518
GFXTCON_DIR_SMx10Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x0000351C
GFXTCON_DIR_SMx10FctTable
00000000 00000000 00000000 00000000
Timing
Controller
0x00003520
GFXTCON_DIR_SMx11Sigs
00000000 00000000 00000000 00000000
Timing
Controller
0x00003524
GFXTCON_DIR_SMx11FctTable
FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
Timing
Controller
0x00003528
GFXTCON_DIR_SSwitch
00000000 00000000 00000000 00000000
Timing
Controller
0x0000352C
GFXTCON_DIR_RBM_CTRL
00000000 00000000 00000000 00000001
Timing
Controller
0x00003530
Reserved
Timing
Controller
0x00003534
GFXTCON_DIR_PIN0_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003538
GFXTCON_DIR_PIN1_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x0000353C
GFXTCON_DIR_PIN2_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003540
GFXTCON_DIR_PIN3_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003544
GFXTCON_DIR_PIN4_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003548
GFXTCON_DIR_PIN5_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x0000354C
GFXTCON_DIR_PIN6_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003550
GFXTCON_DIR_PIN7_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00003554
GFXTCON_DIR_PIN8_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003558
GFXTCON_DIR_PIN9_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x0000355C
GFXTCON_DIR_PIN10_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003560
GFXTCON_DIR_PIN11_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003564
GFXTCON_DIR_PIN12_CTRL
00000000 00000000 00000000 00010000
Timing
Controller
0x00003568 ...
0x00003FFF
Reserved
Reserved
0x00004000
GFXDISP_DisplayEnable
00000000 00000000 00000000 00000000
Display
Controller
0x00004004
GFXDISP_DisplayResolution
00000000 00000000 00000000 00000000
Display
Controller
0x00004008
GFXDISP_DisplayActiveArea
00000000 00000000 00000000 00000000
Display
Controller
0x0000400C
GFXDISP_HorizontalSynchTimingConf
00000000 00000000 00000000 00000000
Display
Controller
0x00004010
GFXDISP_VerticalSynchTimingConf
00000000 00000000 00000000 00000000
Display
Controller
0x00004014
GFXDISP_DisplayConf
00000000 00000000 00000000 00000000
Display
Controller
0x00004018
GFXDISP_PixEngTrig
00000000 00000000 00000000 00000000
Display
Controller
0x0000401C
GFXDISP_DitherControl
00000000 00000000 00000000 00000001
Display
Controller
0x00004020
GFXDISP_Int0Trigger
00000000 00000000 00000000 00000000
Display
Controller
0x00004024
GFXDISP_Int1Trigger
00000000 00000000 00000000 00000000
Display
Controller
0x00004028
GFXDISP_Int2Trigger
00000000 00000000 00000000 00000000
Display
Controller
0x0000402C
GFXDISP_Debug
00000000 00000000 00000000 00000000
Display
Controller
0x00004FFB ...
0x00004FFF
Reserved
Reserved
0x00005000
GFXSIG_LockUnlock
00000000 00000000 00000000 00000000
Signature Unit
0x00005004
GFXSIG_SigLockStatus
00000000 00000000 00000000 00000001
Signature Unit
0x00005008
GFXSIG_SigSWreset
00000000 00000000 00000000 00000000
Signature Unit
0x0000500C
GFXSIG_SigCtrl
00000000 00000000 00000000 00000000
Signature Unit
0x00005010
GFXSIG_MaskHorizontalUpperLeft
00000000 00000000 00000000 00000000
Signature Unit
0x00005014
GFXSIG_MaskHorizontalLowerRight
00000000 00000000 00000000 00000000
Signature Unit
Fujitsu Semiconductor Europe GmbH
1 - 15
Revised 24/7/13
1 - 16
Iris-SDL (2D Graphics Engine)
0x00005018
GFXSIG_MaskVerticalUpperLeft
00000000 00000000 00000000 00000000
Signature Unit
0x0000501C
GFXSIG_MaskVerticalLowerRight
00000000 00000000 00000000 00000000
Signature Unit
0x00005020
GFXSIG_HorizontalUpperLeftW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005024
GFXSIG_HorizontalLowerRightW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005028
GFXSIG_VerticalUpperLeftW0
00000000 00000000 00000000 00000000
Signature Unit
0x0000502C
GFXSIG_VerticalLowerRightW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005030
GFXSIG_SignAReferenceRW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005034
GFXSIG_SignAReferenceGW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005038
GFXSIG_SignAReferenceBW0
00000000 00000000 00000000 00000000
Signature Unit
0x0000503C
GFXSIG_SignBReferenceRW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005040
GFXSIG_SignBReferenceGW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005044
GFXSIG_SignBReferenceBW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005048
GFXSIG_ThrBRW0
00000000 00000000 00000000 00000000
Signature Unit
0x0000504C
GFXSIG_ThrBGW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005050
GFXSIG_ThrBBW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005054
GFXSIG_ErrorThreshold
00000000 00001000 00000000 00000001
Signature Unit
0x00005058
GFXSIG_CtrlCfgW0
00000000 00000000 00000000 00000000
Signature Unit
0x0000505C
GFXSIG_TriggerW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005060
GFXSIG_IENW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005064
GFXSIG_InterruptStatusW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005068
GFXSIG_StatusW0
00000000 00000000 00000000 00000000
Signature Unit
0x0000506C
GFXSIG_Signature_error
00000000 00000000 00000000 00000000
Signature Unit
0x00005070
GFXSIG_SignatureARW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005074
GFXSIG_SignatureAGW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005078
GFXSIG_SignatureABW0
00000000 00000000 00000000 00000000
Signature Unit
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x0000507C
GFXSIG_SignatureBRW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005080
GFXSIG_SignatureBGW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005084
GFXSIG_SignatureBBW0
00000000 00000000 00000000 00000000
Signature Unit
0x00005088 ...
0x00005FFC
Reserved
Reserved
0x00006000
GFXAIC_Status
00000000 00000000 11111111 00000000
AXI Interconnect
Matrix
0x00006004
GFXAIC_Control
00000000 00000000 00000000 0000000X
AXI Interconnect
Matrix
0x00006008
GFXAIC_MonitorDisable
00000000 00000000 00000000 00000000
AXI Interconnect
Matrix
0x0000600C
GFXAIC_SlaveDisable
00000000 00000000 00000000 00000000
AXI Interconnect
Matrix
0x00006010 ...
0x00006FFF
Reserved
Reserved
0x00007000 ...
0x00007FFF
Reserved
Reserved
0x00008000
GFXPIX_fetch0_Status
00000000 00000000 00000000 0XXX000X
fetch0
0x00008004
Reserved
Reserved
0x00008008
GFXPIX_fetch0_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch0
0x0000800C
GFXPIX_fetch0_BaseAddress
00000000 00000000 00000000 00000000
fetch0
0x00008010
GFXPIX_fetch0_SourceBufferStride
00000000 00000000 00000000 00000000
fetch0
0x00008014
GFXPIX_fetch0_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch0
0x00008018
GFXPIX_fetch0_SourceBufferLength
00000000 00000000 00000000 00000000
fetch0
0x0000801C
GFXPIX_fetch0_FrameXOffset
00000000 00000000 00000000 00000000
fetch0
0x00008020
GFXPIX_fetch0_FrameYOffset
00000000 00000000 00000000 00000000
fetch0
0x00008024
GFXPIX_fetch0_FrameDimensions
00000000 00000000 00000000 00000000
fetch0
0x00008028..0x00
008034
Reserved
Reserved
0x00008038
GFXPIX_fetch0_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch0
0x0000803C
GFXPIX_fetch0_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch0
0x00008040
GFXPIX_fetch0_ColorComponentBits
00001000 00001000 00001000 00001000
fetch0
0x00008044
GFXPIX_fetch0_ColorComponentShift
00011000 00010000 00001000 00000000
fetch0
Fujitsu Semiconductor Europe GmbH
1 - 17
Revised 24/7/13
Iris-SDL (2D Graphics Engine)
0x00008048
GFXPIX_fetch0_ConstantColor
00000000 00000000 00000000 00000000
fetch0
0x0000804C
GFXPIX_fetch0_Control
0XXX0000 00000000 00000010 00001100
fetch0
0x00008050..0x00
0083
Reserved
Reserved
0x00008400
GFXPIX_fetch1_Status
00000000 00000000 00000000 0XXX000X
fetch1
0x00008404
Reserved
Reserved
0x00008408
GFXPIX_fetch1_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch1
0x0000840C
GFXPIX_fetch1_BaseAddress
00000000 00000000 00000000 00000000
fetch1
0x00008410
GFXPIX_fetch1_SourceBufferStride
00000000 00000000 00000000 00000000
fetch1
0x00008414
GFXPIX_fetch1_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch1
0x00008418
Reserved
Reserved
0x0000841C
GFXPIX_fetch1_FrameXOffset
00000000 00000000 00000000 00000000
fetch1
0x00008420
GFXPIX_fetch1_FrameYOffset
00000000 00000000 00000000 00000000
fetch1
0x00008424
GFXPIX_fetch1_FrameDimensions
00000000 00000000 00000000 00000000
fetch1
0x00008428..0x00
008434
Reserved
Reserved
0x00008438
GFXPIX_fetch1_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch1
0x0000843C
GFXPIX_fetch1_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch1
0x00008440
GFXPIX_fetch1_ColorComponentBits
00001000 00001000 00001000 00001000
fetch1
0x00008444
GFXPIX_fetch1_ColorComponentShift
00011000 00010000 00001000 00000000
fetch1
0x00008448
GFXPIX_fetch1_ConstantColor
00000000 00000000 00000000 00000000
fetch1
0x0000844C
GFXPIX_fetch1_Control
0XXX0000 00000000 00000010 00001100
fetch1
0x00008450..0x00
0087FC
Reserved
Reserved
0x00008800
GFXPIX_fetch2_Status
00000000 00000000 00000000 0XXX000X
fetch2
0x00008804
Reserved
Reserved
0x00008808
GFXPIX_fetch2_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch2
0x0000880C
GFXPIX_fetch2_BaseAddress
00000000 00000000 00000000 00000000
fetch2
1 - 18
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00008810
GFXPIX_fetch2_SourceBufferStride
00000000 00000000 00000000 00000000
fetch2
0x00008814
GFXPIX_fetch2_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch2
0x00008818
Reserved
Reserved
0x0000881C
GFXPIX_fetch2_FrameXOffset
00000000 00000000 00000000 00000000
fetch2
0x00008820
GFXPIX_fetch2_FrameYOffset
00000000 00000000 00000000 00000000
fetch2
0x00008824
GFXPIX_fetch2_FrameDimensions
00000000 00000000 00000000 00000000
fetch2
0x00008828
GFXPIX_fetch2_DeltaXX
00000000 00000000 00000000 00000000
fetch2
0x0000882C
GFXPIX_fetch2_DeltaXY
00000000 00000000 00000000 00000000
fetch2
0x00008830
GFXPIX_fetch2_DeltaYX
00000000 00000000 00000000 00000000
fetch2
0x00008834
GFXPIX_fetch2_DeltaYY
00000000 00000000 00000000 00000000
fetch2
0x00008838
GFXPIX_fetch2_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch2
0x0000883C
GFXPIX_fetch2_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch2
0x00008840
GFXPIX_fetch2_ColorComponentBits
00001000 00001000 00001000 00001000
fetch2
0x00008844
GFXPIX_fetch2_ColorComponentShift
00011000 00010000 00001000 00000000
fetch2
0x00008848
GFXPIX_fetch2_ConstantColor
00000000 00000000 00000000 00000000
fetch2
0x0000884C
GFXPIX_fetch2_Control
0XXX0000 00000000 00000010 00001100
fetch2
0x00008850..0x00
008BFC
0x00008C00
Reserved
GFXPIX_fetch3_Status
00000000 00000000 00000000 0XXX000X
Reserved
0x00008C04
Reserved
fetch3
Reserved
0x00008C08
GFXPIX_fetch3_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch3
0x00008C0C
GFXPIX_fetch3_BaseAddress
00000000 00000000 00000000 00000000
fetch3
0x00008C10
GFXPIX_fetch3_SourceBufferStride
00000000 00000000 00000000 00000000
fetch3
0x00008C14
GFXPIX_fetch3_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch3
0x00008C18
GFXPIX_fetch3_SourceBufferLength
00000000 00000000 00000000 00000000
fetch3
Fujitsu Semiconductor Europe GmbH
1 - 19
Revised 24/7/13
Iris-SDL (2D Graphics Engine)
0x00008C1C
GFXPIX_fetch3_FrameXOffset
00000000 00000000 00000000 00000000
fetch3
0x00008C20
GFXPIX_fetch3_FrameYOffset
00000000 00000000 00000000 00000000
fetch3
0x00008C24
GFXPIX_fetch3_FrameDimensions
00000000 00000000 00000000 00000000
fetch3
0x00008C28..0x0
0008C34
Reserved
Reserved
0x00008C38
GFXPIX_fetch3_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch3
0x00008C3C
GFXPIX_fetch3_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch3
0x00008C40
GFXPIX_fetch3_ColorComponentBits
00001000 00001000 00001000 00001000
fetch3
0x00008C44
GFXPIX_fetch3_ColorComponentShift
00011000 00010000 00001000 00000000
fetch3
0x00008C48
GFXPIX_fetch3_ConstantColor
00000000 00000000 00000000 00000000
fetch3
0x00008C4C
GFXPIX_fetch3_Control
0XXX0000 00000000 00000010 00001100
fetch3
0x00008C50..0x0
0008FFC
Reserved
Reserved
0x00009000
GFXPIX_fetch4_Status
00000000 00000000 00000000 0XXX000X
fetch4
0x00009004
Reserved
Reserved
0x00009008
GFXPIX_fetch4_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch4
0x0000900C
GFXPIX_fetch4_BaseAddress
00000000 00000000 00000000 00000000
fetch4
0x00009010
GFXPIX_fetch4_SourceBufferStride
00000000 00000000 00000000 00000000
fetch4
0x00009014
GFXPIX_fetch4_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch4
0x00009018
Reserved
Reserved
0x0000901C
GFXPIX_fetch4_FrameXOffset
00000000 00000000 00000000 00000000
fetch4
0x00009020
GFXPIX_fetch4_FrameYOffset
00000000 00000000 00000000 00000000
fetch4
0x00009024
GFXPIX_fetch4_FrameDimensions
00000000 00000000 00000000 00000000
fetch4
0x00009028..0x00
009034
Reserved
Reserved
0x00009038
GFXPIX_fetch4_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch4
0x0000903C
GFXPIX_fetch4_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch4
1 - 20
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00009040
GFXPIX_fetch4_ColorComponentBits
00001000 00001000 00001000 00001000
fetch4
0x00009044
GFXPIX_fetch4_ColorComponentShift
00011000 00010000 00001000 00000000
fetch4
0x00009048
GFXPIX_fetch4_ConstantColor
00000000 00000000 00000000 00000000
fetch4
0x0000904C
GFXPIX_fetch4_Control
0XXX0000 00000000 00000010 00001100
fetch4
0x00009050..0x00
0093FC
Reserved
Reserved
0x00009400
GFXPIX_fetch5_Status
00000000 00000000 00000000 0XXX000X
fetch5
0x00009404
Reserved
Reserved
0x00009408
GFXPIX_fetch5_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch5
0x0000940C
GFXPIX_fetch5_BaseAddress
00000000 00000000 00000000 00000000
fetch5
0x00009410
GFXPIX_fetch5_SourceBufferStride
00000000 00000000 00000000 00000000
fetch5
0x00009414
GFXPIX_fetch5_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch5
0x00009418
Reserved
Reserved
0x0000941C
GFXPIX_fetch5_FrameXOffset
00000000 00000000 00000000 00000000
fetch5
0x00009420
GFXPIX_fetch5_FrameYOffset
00000000 00000000 00000000 00000000
fetch5
0x00009424
GFXPIX_fetch5_FrameDimensions
00000000 00000000 00000000 00000000
fetch5
0x00009428..0x00
009434
Reserved
Reserved
0x00009438
GFXPIX_fetch5_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch5
0x0000943C
GFXPIX_fetch5_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch5
0x00009440
GFXPIX_fetch5_ColorComponentBits
00001000 00001000 00001000 00001000
fetch5
0x00009444
GFXPIX_fetch5_ColorComponentShift
00011000 00010000 00001000 00000000
fetch5
0x00009448
GFXPIX_fetch5_ConstantColor
00000000 00000000 00000000 00000000
fetch5
0x0000944C
GFXPIX_fetch5_Control
0XXX0000 00000000 00000010 00001100
fetch5
0x00009450..0x00
0097FC
Reserved
Reserved
0x00009800
GFXPIX_fetch6_Status
00000000 00000000 00000000 0XXX000X
fetch6
Fujitsu Semiconductor Europe GmbH
1 - 21
Revised 24/7/13
Iris-SDL (2D Graphics Engine)
0x00009804
Reserved
Reserved
0x00009808
GFXPIX_fetch6_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch6
0x0000980C
GFXPIX_fetch6_BaseAddress
00000000 00000000 00000000 00000000
fetch6
0x00009810
GFXPIX_fetch6_SourceBufferStride
00000000 00000000 00000000 00000000
fetch6
0x00009814
GFXPIX_fetch6_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch6
0x00009818
Reserved
Reserved
0x0000981C
GFXPIX_fetch6_FrameXOffset
00000000 00000000 00000000 00000000
fetch6
0x00009820
GFXPIX_fetch6_FrameYOffset
00000000 00000000 00000000 00000000
fetch6
0x00009824
GFXPIX_fetch6_FrameDimensions
00000000 00000000 00000000 00000000
fetch6
0x00009828..0x00
009834
Reserved
Reserved
0x00009838
GFXPIX_fetch6_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch6
0x0000983C
GFXPIX_fetch6_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch6
0x00009840
GFXPIX_fetch6_ColorComponentBits
00001000 00001000 00001000 00001000
fetch6
0x00009844
GFXPIX_fetch6_ColorComponentShift
00011000 00010000 00001000 00000000
fetch6
0x00009848
GFXPIX_fetch6_ConstantColor
00000000 00000000 00000000 00000000
fetch6
0x0000984C
GFXPIX_fetch6_Control
0XXX0000 00000000 00000010 00001100
fetch6
0x00009850..0x00
009BFC
Reserved
Reserved
0x00009C00
GFXPIX_fetch7_Status
00000000 00000000 00000000 0XXX000X
fetch7
0x00009C04
Reserved
Reserved
0x00009C08
GFXPIX_fetch7_BurstBufferManagement
00000100 00000100 000XXXXX XXXXXXXX
fetch7
0x00009C0C
GFXPIX_fetch7_BaseAddress
00000000 00000000 00000000 00000000
fetch7
0x00009C10
GFXPIX_fetch7_SourceBufferStride
00000000 00000000 00000000 00000000
fetch7
0x00009C14
GFXPIX_fetch7_SourceBufferAttributes
00000000 00000000 00000000 00000000
fetch7
0x00009C18
Reserved
Reserved
1 - 22
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x00009C1C
GFXPIX_fetch7_FrameXOffset
00000000 00000000 00000000 00000000
fetch7
0x00009C20
GFXPIX_fetch7_FrameYOffset
00000000 00000000 00000000 00000000
fetch7
0x00009C24
GFXPIX_fetch7_FrameDimensions
00000000 00000000 00000000 00000000
fetch7
0x00009C28..0x0
0009C34
Reserved
Reserved
0x00009C38
GFXPIX_fetch7_SkipWindowOffset
00000000 00000000 00000000 00000000
fetch7
0x00009C3C
GFXPIX_fetch7_SkipWindowDimensions
00000000 00000000 00000000 00000000
fetch7
0x00009C40
GFXPIX_fetch7_ColorComponentBits
00001000 00001000 00001000 00001000
fetch7
0x00009C44
GFXPIX_fetch7_ColorComponentShift
00011000 00010000 00001000 00000000
fetch7
0x00009C48
GFXPIX_fetch7_ConstantColor
00000000 00000000 00000000 00000000
fetch7
0x00009C4C
GFXPIX_fetch7_Control
0XXX0000 00000000 00000010 00001100
fetch7
0x00009C50..0x0
0009FFC
Reserved
Reserved
0x0000A000
GFXPIX_store0_Status
00000000 00000000 00000000 0XXX000X
store0
0x0000A004
GFXPIX_store0_LAST_CONTROL_WORD
00000000 00000000 00000000 00000000
store0
0x0000A008
GFXPIX_store0_BurstBufferManagement
00000100 00000000 000XXXXX 00000100
store0
0x0000A00C
GFXPIX_store0_BaseAddress
00000000 00000000 00000000 00000000
store0
0x0000A010
GFXPIX_store0_DestinationBufferStride
00000000 00000000 00000000 00000000
store0
0x0000A014..0x0
000A018
Reserved
Reserved
0x0000A01C
GFXPIX_store0_FrameXOffset
00000000 00000000 00000000 00000000
store0
0x0000A020
GFXPIX_store0_FrameYOffset
00000000 00000000 00000000 00000000
store0
0x0000A024..0x0
000A03C
Reserved
Reserved
0x0000A040
GFXPIX_store0_ColorComponentBits
00001000 00001000 00001000 00001000
store0
0x0000A044
GFXPIX_store0_ColorComponentShift
00011000 00010000 00001000 00000000
store0
0x0000A048
Reserved
Reserved
Fujitsu Semiconductor Europe GmbH
1 - 23
Revised 24/7/13
Iris-SDL (2D Graphics Engine)
0x0000A04C
GFXPIX_store0_Control
00000000 00000000 00000010 00001100
store0
0x0000A050
GFXPIX_store0_PerfCounter
00000000 00000000 00000000 00000000
store0
0x0000A054..0x0
000A3FC
Reserved
Reserved
0x0000A400
GFXPIX_hscaler0_Control
00000000 00000000 00000000 00000000
hscaler0
0x0000A404
GFXPIX_hscaler0_Setup1
00000000 00000000 10000000 00000000
hscaler0
0x0000A408
GFXPIX_hscaler0_Setup2
00000000 00000000 00000000 00000000
hscaler0
0x0000A40C..0x0
000A7FC
Reserved
Reserved
0x0000A800
GFXPIX_vscaler0_Control
00000000 00000000 00000000 00000000
vscaler0
0x0000A804
GFXPIX_vscaler0_Setup1
00000000 00000000 10000000 00000000
vscaler0
0x0000A808
GFXPIX_vscaler0_Setup2
00000000 00000000 00000000 00000000
vscaler0
0x0000A80C..0x0
000ABFC
Reserved
Reserved
0x0000AC00
GFXPIX_rop0_Control
00000000 00000000 00000000 00000000
rop0
0x0000AC04
GFXPIX_rop0_RasterOperationIndices
00000000 00000000 00000000 00000000
rop0
0x0000AC08
GFXPIX_rop0_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop0
0x0000AC0C
GFXPIX_rop0_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop0
0x0000AC10
GFXPIX_rop0_TERT_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop0
0x0000AC14..0x0
000AFFC
Reserved
Reserved
0x0000B000
GFXPIX_rop1_Control
00000000 00000000 00000000 00000000
rop1
0x0000B004
GFXPIX_rop1_RasterOperationIndices
00000000 00000000 00000000 00000000
rop1
0x0000B008
GFXPIX_rop1_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop1
0x0000B00C
GFXPIX_rop1_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop1
0x0000B010
GFXPIX_rop1_TERT_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
rop1
0x0000B014..0x0
000B3FC
Reserved
Reserved
1 - 24
Fujitsu Semiconductor Europe GmbH
Iris-SDL (2D Graphics Engine)
Revised 24/7/13
0x0000B400
GFXPIX_blitblend0_Control
00000000 00000000 00000000 00000000
blitblend0
0x0000B404
GFXPIX_blitblend0_ConstantColor
00000000 00000000 00000000 00000000
blitblend0
0x0000B408
GFXPIX_blitblend0_ColorRedBlendFunction
00000011 00000000 00000011 00000000
blitblend0
0x0000B40C
GFXPIX_blitblend0_ColorGreenBlendFunction
00000011 00000000 00000011 00000000
blitblend0
0x0000B410
GFXPIX_blitblend0_ColorBlueBlendFunction
00000011 00000000 00000011 00000000
blitblend0
0x0000B414
GFXPIX_blitblend0_AlphaBlendFunction
00000011 00000000 00000011 00000000
blitblend0
0x0000B418
GFXPIX_blitblend0_BlendMode1
10000000 00000110 10000000 00000110
blitblend0
0x0000B41C
GFXPIX_blitblend0_BlendMode2
10000000 00000110 10000000 00000110
blitblend0
0x0000B420
GFXPIX_blitblend0_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
blitblend0
0x0000B424
GFXPIX_blitblend0_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
blitblend0
0x0000B428
GFXPIX_blitblend0_Debug
00000000 00000000 00000000 00000000
blitblend0
0x0000B42C..0x0
000B7FC
Reserved
Reserved
0x0000B800
GFXPIX_layerblend0_CONTROL
00000000 00000000 00000000 00000000
layerblend0
0x0000B804
GFXPIX_layerblend0_POSITION
00000000 00000000 00000000 00000000
layerblend0
0x0000B808
GFXPIX_layerblend0_TRANS_COL
00000000 00000000 00000000 00000000
layerblend0
0x0000B80C
GFXPIX_layerblend0_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend0
0x0000B810
GFXPIX_layerblend0_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend0
0x0000B814..0x0
000BBFC
Reserved
Reserved
0x0000BC00
GFXPIX_layerblend1_CONTROL
00000000 00000000 00000000 00000000
layerblend1
0x0000BC04
GFXPIX_layerblend1_POSITION
00000000 00000000 00000000 00000000
layerblend1
0x0000BC08
GFXPIX_layerblend1_TRANS_COL
00000000 00000000 00000000 00000000
layerblend1
0x0000BC0C
GFXPIX_layerblend1_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend1
0x0000BC10
GFXPIX_layerblend1_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend1
Fujitsu Semiconductor Europe GmbH
1 - 25
Revised 24/7/13
Iris-SDL (2D Graphics Engine)
0x0000BC14..0x0
000BFFC
Reserved
Reserved
0x0000C000
GFXPIX_layerblend2_CONTROL
00000000 00000000 00000000 00000000
layerblend2
0x0000C004
GFXPIX_layerblend2_POSITION
00000000 00000000 00000000 00000000
layerblend2
0x0000C008
GFXPIX_layerblend2_TRANS_COL
00000000 00000000 00000000 00000000
layerblend2
0x0000C00C
GFXPIX_layerblend2_PRIM_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend2
0x0000C010
GFXPIX_layerblend2_SEC_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
layerblend2
0x0000C014..0x0
000C3FC
Reserved
Reserved
0x0000C400
GFXPIX_lut0_CONTROL
00000000 00000000 00000010 00000000
lut0
0x0000C404
GFXPIX_lut0_LAST_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
lut0
0x0000C408..0x0
000CBFC
Reserved
Reserved
0x0000CC00
GFXPIX_lut1_CONTROL
00000000 00000000 00000010 00000000
lut1
0x0000CC04
GFXPIX_lut1_LAST_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
lut1
0x0000CC08..0x0
000D3FC
Reserved
Reserved
0x0000D400
GFXPIX_matrix0_CONTROL
00000000 00000000 00000000 00000000
matrix0
0x0000D404
GFXPIX_matrix0_RED0
00000000 00000000 00000001 00000000
matrix0
0x0000D408
GFXPIX_matrix0_RED1
00000000 00000000 00000000 00000000
matrix0
0x0000D40C
GFXPIX_matrix0_GREEN0
00000001 00000000 00000000 00000000
matrix0
0x0000D410
GFXPIX_matrix0_GREEN1
00000000 00000000 00000000 00000000
matrix0
0x0000D414
GFXPIX_matrix0_BLUE0
00000000 00000000 00000000 00000000
matrix0
0x0000D418
GFXPIX_matrix0_BLUE1
00000000 00000000 00000001 00000000
matrix0
0x0000D41C
GFXPIX_matrix0_LAST_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
matrix0
0x0000D420..0x0
000D7FC
Reserved
Reserved
0x0000D800
GFXPIX_extdst0_CONTROL
00000000 00000000 00000000 00000000
extdst0
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0x0000D804
GFXPIX_extdst0_STATUS
00000000 00000000 00000000 00000XXX
extdst0
0x0000D808
GFXPIX_extdst0_CONTROL_WORD
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
extdst0
0x0000D80C
GFXPIX_extdst0_CUR_PIXEL_CNT
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
extdst0
0x0000D810
GFXPIX_extdst0_LAST_PIXEL_CNT
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
extdst0
0x0000D814..0x0
000DBFC
Reserved
Reserved
0x0000DC00
GFXPIX_pixelbus_fetch0_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC04
GFXPIX_pixelbus_fetch1_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC08
GFXPIX_pixelbus_fetch2_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC0C
GFXPIX_pixelbus_fetch3_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC10
GFXPIX_pixelbus_fetch4_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC14
GFXPIX_pixelbus_fetch5_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC18
GFXPIX_pixelbus_fetch6_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC1C
GFXPIX_pixelbus_fetch7_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC20
GFXPIX_pixelbus_store0_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC24
GFXPIX_pixelbus_hscaler0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC28
GFXPIX_pixelbus_vscaler0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC2C
GFXPIX_pixelbus_rop0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC30
GFXPIX_pixelbus_rop1_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC34
GFXPIX_pixelbus_blitblend0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC38
GFXPIX_pixelbus_layerblend0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC3C
GFXPIX_pixelbus_layerblend1_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC40
GFXPIX_pixelbus_layerblend2_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC44
GFXPIX_pixelbus_lut0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
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0x0000DC48
GFXPIX_pixelbus_lut1_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC4C
GFXPIX_pixelbus_matrix0_cfg
00XX0011 00000000 00000000 00000000
pixelbus
0x0000DC50
GFXPIX_pixelbus_extdst0_cfg
00XX0000 00000000 00000000 00000000
pixelbus
0x0000DC54
GFXPIX_pixelbus_STORE0_SYNC
00000000 00000000 00000000 00000010
pixelbus
0x0000DC58
GFXPIX_pixelbus_STORE0_SYNC_STAT
00000000 00000000 00000000 000XXXXX
pixelbus
0x0000DC5C
GFXPIX_pixelbus_EXTDST0_SYNC
00000000 00000000 00000000 00000010
pixelbus
0x0000DC60
GFXPIX_pixelbus_EXTDST0_SYNC_STAT
00000000 00000000 00000000 000XXXXX
pixelbus
0x0000DC64
GFXPIX_pixelbus_STORE0_CLK
00000000 00000000 00000000 10000000
pixelbus
0x0000DC68
GFXPIX_pixelbus_EXTDST0_CLK
00000000 00000000 00000000 10000000
pixelbus
0x0000DC6C..0x0
000FFFF
Reserved
Reserved
0x0000806C ...
0x0000FFFF
Reserved
Reserved
0x00010000 ...
0x00010404
Reserved
Reserved
0x00010408
GFXHPM_MSSARarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x0001040C
GFXHPM_MSSAWarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x00010410 ...
0x00010424
Reserved
Reserved
0x00010428
GFXHPM_Vram0ARarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x0001042C
GFXHPM_Vram0AWarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x00010430 ...
0x00010444
Reserved
Reserved
0x00010448
Reserved
Reserved
0x0001044C
Reserved
Reserved
0x00010450 ...
0x00010464
Reserved
Reserved
0x00010468
GFXHPM_AHBARarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x0001046C
GFXHPM_AHBAWarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x00010450 ...
0x00010484
Reserved
Reserved
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0x00010488
GFXHPM_HPMARarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x0001048C
GFXHPM_HPMAWarbitration
00000000 00000000 00000000 00000000
HPM (Arbiter)
0x00010490 ...
0x00010FFF
Reserved
Reserved
0x00011000 ...
0x0007FFFF
Reserved
Reserved
Table 1-3: Memory layout of Iris-SDL Memories
Address
(MEMBASE + ...)
+3
+2
+1
+0
block
0x00000000 ...
0x0FFFFFFF
SPI
SPI
0x10000000 ...
0x100FFFFF
VRAM0
VRAM0
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Iris-SDL (2D Graphics Engine)
Iris-SDL System Events and Interrupt Mappings
The Iris-SDL Graphics Engine has a series of defined events that are described in the following table. The table also shows the mapping of these to “Iris-SDL Interrupts” or “Command Sequencer
(CMDSEQ)” events.
Table 1-4: Iris-SDL System Events and Interrupts
Iris-SDL System Event
Mapping
(IntStatus[0/1]. bit)
Command
Sequencer
Event ID
From
Module
Description
pixeng_sync_extdst0
0.0
0
Pixel Engine
The reconfiguration
of the display path
in the Pixel Engine
has finished.
pixeng_sync_store0
0.1
1
Pixel Engine
The reconfiguration
of the blit path in the
Pixel Engine has
finished.
pixeng_store0_shd
0.2
2
Pixel Engine
Store Unit
Loading the shadow
configuration has
been completed.
pixeng_store0_rdy
0.3
3
Pixel Engine
Store Unit
Writing the result of
a blit operation into
memory has been
completed.
pixeng_store0_err
0.4
-
Pixel Engine
Store Unit
Received corrupt
input frame. This is
for hardware
debugging only.
pixeng_rop0_shd
0.5
4
Pixel Engine
ROP Unit
Loading the shadow
configuration has
been completed.
pixeng_rop1_shd
0.6
5
Pixel Engine
ROP Unit
Loading the shadow
configuration has
been completed.
pixeng_blitblend0_shd
0.7
6
Pixel Engine
BlitBlend
Loading the shadow
configuration has
been completed.
pixeng_layerblend0_shd
0.8
7
Pixel Engine
LayerBlend
Loading the shadow
configuration has
been completed.
pixeng_layerblend1_shd
0.9
8
Pixel Engine
LayerBlend
Loading the shadow
configuration has
been completed.
pixeng_layerblend2_shd
0.10
9
Pixel Engine
LayerBlend
Loading the shadow
configuration has
been completed.
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Table 1-4: Iris-SDL System Events and Interrupts
pixeng_extdst0_beg
0.11
10
Pixel Engine
ExtDst
Pixel Engine begins
sending a new
frame to the Display
Controller.
pixeng_extdst0_shd
0.12
11
Pixel Engine
ExtDst
Loading the shadow
configuration has
been completed.
pixeng_extdst0_rdy
0.13
12
Pixel Engine
ExtDst
Pixel Engine has
completed sending
a complete frame to
the Display
Controller.
pixeng_extdst0_err
0.14
-
Pixel Engine
ExtDst
One of several error
conditions has
occured. This is for
debugging purposes
only
cmd_watdog
0.15
-
Command
Sequencer
The watchdog
counter has expired.
cmd_fempty
0.16
-
Command
Sequencer
The command/data
buffer (FIFO) is
empty.
cmd_flwm
0.17
-
Command
Sequencer
The command/data
buffer (FIFO) has
reached the low
watermark.
cmd_fhwm
0.18
-
Command
Sequencer
The command/data
buffer (FIFO) has
reached the high
watermark.
cmd_ffull
0.19
-
Command
Sequencer
The command/data
buffer (FIFO) is full.
cmd_error
0.20
-
Command
Sequencer
Sequencer error or
illegal instruction
encountered.
cmd_idle
0.21
-
Command
Sequencer
Command
Sequencer is in idle
state.
disp_pInt0
0.22
13
Display
Controller
Reached
programmable
frame position 0.
disp_pInt1
0.23
14
Display
Controller
Reached
programmable
frame position 1.
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Table 1-4: Iris-SDL System Events and Interrupts
disp_pInt2
0.24
15
Display
Controller
Reached
programmable
frame position 2.
disp_bigInt
0.25
-
Display
Controller
Controller discarded
pixels from the
display FIFO. This is
typically in
consequence of a
FIFO underrun
condition
(disp_smallInt)
when the controller
must re-synchronize
to the pixel stream.
disp_smallInt
0.26
-
Display
Controller
Controller
generated black
display pixels
because of display
FIFO underrun. Use
this to detect
unstable display
processing.
aic_int
0.27
-
AXI
Interconnect
Detected an error
response from slave
device or address
decode error.
spi_tx_int (*)
0.28
16
High-Speed
SPI
TX interrupt for
HS-SPI direct
mode.
spi_rx_int (*)
0.29
17
High-Speed
SPI
RX interrupt for
HS-SPI direct
mode.
spi_fault_int (*)
0.30
-
High-Speed
SPI
Occurs on
protection violation
fault or with an
unmapped memory
access.
sig_cfg_cop
1.0
18
Signature
Unit
Loading the shadow
configuration has
been completed.
sig_result_valid
1.1
19
Signature
Unit
Signature
computation has
completed and the
result register is
valid.
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Table 1-4: Iris-SDL System Events and Interrupts
sig_error
1.2
20
Signature
Unit
Signature violation
(number of error
frames has
exceeded threshold
value).
This is also
available as a NMI
(non-maskable
interrupt) - see
below.
sw_int0
1.3
21
-
Can be triggered by
software only
(preset).
sw_int1
1.4
22
-
Can be triggered by
software only
(preset).
sw_int2
1.5
23
-
Can be triggered by
software only
(preset).
sw_int3
1.6
-
-
Can be triggered by
software only
(preset).
0
-
Signature
Unit
Signature violation
(number of error
frames has
exceeded threshold
value).
This is also
available as a
maskable interrupt see above.
NMI (Non-maskable interrupt):
sig_error
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Chapter 2: Iris-SDL Programming Guide
This chapter describes how to setup and run the Iris-SDL system from a programmer’s point of view.
All the required configuration and control registers are mapped into system address space. The address map is static and does not require any configuration.
The setup procedures described below assume that the hardware configuration is in the reset state.
The reset values for certain configuration bitfields are described in the register description tables of
the Iris-SDL sub components.
2.1
Basic Setup
2.1.1 Hardware Reset
The global Iris-SDL system reset must be controlled by the embodying system. Refer to the Titan
documentation.
2.1.2 Clock Settings
Iris-SDL generates internally needed clocks based on external signals delivered by the Titan device.
This must therefore be setup to generate a bus clock (always), a reference clock (only when display
operation is needed) and a peripheral clock (only required when external SPI devices are used).
Please refer to the Titan specification and the chapter ’Global Control Unit (GCTR)’ in this document
for details.
The Iris-SDL-internal bus clock frequency can be configured to less than the permitted maximum of
128 MHz for power saving purposes, however the frequency is critical to artifact-free display operation (see ’Clock Settings’) and sensitive to the performance of blit operations and access to internal
resources such as configuration registers and embedded video memory.
The reference clock is used to derive the display’s pixel clock. Its frequency should either be the
exact pixel clock frequency (typically the case when using an external clock source) or programmed
to the highest possible value (maximum 400 MHz) in order to achieve the most precise setup of the
pixel clock frequency with a divider circuitry.
NOTE After a reset, it is necessary to setup the pixel clock using a strict sequence of steps. If the
order of the steps is changed, it is possible that the system may become instable:
1) Release the Iris-SDL hardware reset (RESETN)
2) Turn on (glitch-free) the external clock source (REF_CLK)
3) Modify the clock adjust settings in the Global Control unit.
It is important that the clock settings in Iris-SDL are not changed from the reset values
before the external reference clock is active.
NOTE Please also note that the reset synchronization mechanism for the pixel clock domain
(pix_clk) is driven by pix_x2_clk, which is derived from ref_clk. This means that a reset will
not occur in the pixel clock domain until the reference clock is active. It is necessary to
restrict the pixel clock domain to 80MHz as it would otherwise be 400MHz, due to the time
required for the reset values for clock adjust to propagate into the pixel clock domain.
The peripheral clock is used to derive an external clock for SPI devices such as flash memories.
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2.1.3 Register Lock/Unlock
Access to specific configuration registers that handle safety-relevant features is locked after reset.
This applies to all non-maskable interrupt, software reset, pixel clock adjustment and signature settings.
By writing an unlock (or lock) key to The ’Lock/Unlock register (GFXGCTR_LockUnlock)’ (the SIG
unit has its own ’Signature Unit Lock/Unlock register (GFXSIG_LockUnlock)’, the protection status
can be changed (see the Global Control chapter ’Interrupt Status 0 register
(GFXGCTR_IntStatus0)’, LockStatus and the SIG chapter ’Signature Unit Lock/Unlock register
(GFXSIG_LockUnlock)’, SigLockStatus).
The keys are described here: ’Iris-SDL Register Protection (Locking/Unlocking)’.
Caution is needed in multi-threaded systems or when using interrupt handlers: Access to each of
the two GFXGCTR_LockUnlock registers should be exclusively controlled by one dedicated thread
or handler, otherwise coincident unlock/lock sequences could interfere with each other.
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2.1.4 Bus Matrix Setup
The AXI High-Performance Matrix allows the configuration of different priorities for master ports (see
chapter ’AXI Interconnect Bus (AIC)’).
For Iris-SDL it must be ensured that read access to display buffers has highest priority. The following
changes to the reset configuration are recommended (0 = highest priority):
Vram0
RSlot = 0
RPriority = 2
Main System (Read Access)
Vram0
WSlot = 0
WPriority = 2
Main System (Write Access)
Vram0
RSlot = 1
RPriority = 3
PixEng – Fetch#0 (Blit Buffer)
Vram0
RSlot = 2
RPriority = 3
PixEng – Fetch#1 (Blit Buffer)
Vram0
RSlot = 3
RPriority = 3
PixEng – Fetch#2 (Blit Buffer)
Vram0
RSlot = 4
RPriority = 0
PixEng – Fetch#3 (Display Buffer)
Vram0
RSlot = 5
RPriority = 0
PixEng – Fetch#4 (Display Buffer)
Vram0
RSlot = 6
RPriority = 0
PixEng – Fetch#5 (Display Buffer)
Vram0
RSlot = 7
RPriority = 0
PixEng – Fetch#6 (Display Buffer)
Vram0
RSlot = 8
RPriority = 0
PixEng – Fetch#7 (Display Buffer)
Vram0
WSlot = 9
WPriority = 3
PixEng – Store#0 (Blit Buffer)
Vram0
RSlot = 10
RPriority = 1
CmdSeq Read (Command FIFO)
Vram0
WSlot = 11
WPriority = 1
CmdSeq Write (Command FIFO)
Figure 2-3: Bus matrix setup
NOTE This applies to the default configuration of the Pixel Engine. When display layers are
disabled to be used in the blit path (’Extended Configurations’), then the priority of the
corresponding fetch units must be changed accordingly.
Priority changes to other slaves may be required, depending on the system setup.
If needed, a monitor for error responses on the AXI bus can be configured (see AXI Bus Matrix Registers; ’Error Monitor Status register (GFXAIC_Status)’, ’Error Monitor Control register
(GFXAIC_Control)’, ’Monitor Disable register (GFXAIC_MonitorDisable)’) and enabled as an interrupt source (see aic_int in table ’Iris-SDL System Events and Interrupt Mappings’).
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2.1.5 Software Resets
Certain sub components of Iris-SDL can be programmed to the reset state if not needed (see ’Software Reset register (GFXGCTR_SwReset)’ ) for power saving purposes. Before setting a sub component to reset, all the related AXI slave ports must be disabled to avoid undefined system behavior
(see ’Slave Disable register (GFXAIC_SlaveDisable)’).
Components
SwReset
SlaveDisable
Condition for reset
Display and Timing
Controller
disp_rstn
DispCtrl, Tcon
No display operation needed.
Signature Unit
sig_rstn
Signature
No reference check for display
signature needed.
Command Sequencer
csequ_rstn
CmdSeq
No autonomous processing of
command lists needed, all setup
and synchronization tasks are
done by the system’s CPU.
Pixel Engine
pixeng_rstn
PixEng
No display operation and no
graphics acceleration features
(blit operations) needed.
Video Memory
Interface
vram_rstn
Vram0
No embedded video memory
needed.
Table 2-5: Reset options for Iris-SDL sub components
These settings must not be changed during activity on the AXI bus - which must be ensured by software. We recommend that the setup is executed only in an initialization procedure, immediately after the global reset is being released and while Titan keeps access to Iris-SDL address space
disabled.
For more details about the Iris-SDL reset controller check the Titan documentation.
2.1.6 Interrupt Settings
Iris-SDL has an internal controller that can generate two different interrupt signals to the Titan system. All the hardware events available as listed in ’Iris-SDL Interrupts’ can be enabled or disabled
and mapped to either of these two interrupt lines (see ’Interrupt Enable 0 register
(GFXGCTR_IntEnable0)’, ’Interrupt Enable 1 register (GFXGCTR_IntEnable1)’, ’Interrupt Mapping
0 register (GFXGCTR_IntMap0)’ and ’Interrupt Mapping 1 register (GFXGCTR_IntMap1)’). These
can be used to create two different groups of events to be processed with different priorities by the
main Titan system.
In addition, one non-maskable interrupt signal (NMI) is available for signature violation events,
which are considered safety relevant.
The source event(s) for any of the interrupt lines can be read from status registers and must be reset
when processed by a software handler. All events can also be triggered by software using the preset
feature (’Interrupt Status 0 register (GFXGCTR_IntStatus0)’, ’Interrupt Status 1 register
(GFXGCTR_IntStatus1)’, ’NMI Status register (GFXGCTR_NmiStatus)’, ’Interrupt Clear 0 register
(GFXGCTR_IntClear0)’, ’Interrupt Clear 1 register (GFXGCTR_IntClear1)’, ’NMI Clear register
(GFXGCTR_NmiClear)’, ’Interrupt Preset 0 register (GFXGCTR_IntPreset0)’, ’Interrupt Preset 1
register (GFXGCTR_IntPreset1)’ and ’NMI Preset register (GFXGCTR_NmiPreset)’).
An exception from this mechanism applies to events from the High-Speed SPI. These must be additionally enabled and the status must be cleared in the SPI configuration.
For details about the Iris-SDL interrupt controller see ’Iris-SDL Interrupts’.
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Blit Operation
A blit operation (block-based image transfer) is a 2D graphics acceleration function which reads
source data from memory and writes resulting data back to memory at any system address location.
A single rectangular destination image is computed from one or several source images.
2.2.1 Pipeline Configuration
The number and sequence of pixel processing functions for a single blit is configurable and must be
configured in the Pixel Engine configuration. The following diagram illustrates possible data flow
paths. Each fetch unit corresponds to one source buffer in memory and any of them can be enabled
(but at least one). All pixel processing units in the path between fetch and store units can be programmed to neutral mode.
0HPRU\
)HWFK
5RW
)HWFK
5/'
)HWFK
/LJKW
/87
%DFNJU
)RUHJU
0DVN
5RS
0DWUL[
3L[(QJEOLWSDWK
'DWDSDWKVZLWFK
%OLW%OHQG
6WRUH
0HPRU\
Figure 2-4: Default blit path in Pixel Engine
The path is configured by programming the corresponding bitfield of the submodule’s pixelbus configuration register (null leaves the module disconnected) for each input port (see lut0_src_SEL,
rop0_prim_SEL, rop0_sec_SEL, rop0_aux_SEL, matrix0_src_SEL, blitblend0_prim_SEL,
blitblend0_sec_SEL, store_src_SEL).
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For example, see the Pixelbus Configuration for unit lut0 register (’Pixelbus Configuration for lut0
unit register (GFXPIX_lut0_cfg)’):
Table 2-6: lut0_SEL Bitfield
lut0_SEL
Used to read the lut0 module’s pixel processing path:
00
The lut0 module is not used
01
The lut0 module from the extdst0 processing path is selected
10
The lut0 module from the store0 processing path is selected
11
Reserved
2.2.2 Components Configuration
The next step is to configure the functionality of the submodules being used in the configured blit
path. This configuration defines objects and properties such as the source and destination buffer
format, size and location, color palettes, scale factors, blending functions etc. Please refer to the
respective chapter of the various submodules for details
The burst length used on the AXI bus is programmable for units with access to memory (fetch and
store units). The following values should be used for the best system performance:
SetBurstLength
SetNumBuffers
Fetch0, Fetch1
2
1 (if rotated sampling*)
4
8
Fetch2
4
1 (if rotated sampling*)
4
16
Store0
4
-
Table 2-7: Burst settings for Fetch and Store units
* ‘rotated sampling’ for Fetch0/1 means that FrameSwapDirections is enabled in order to achieve a
fixed 90 or 270 degree rotation. For Fetch2 it means that the DeltaXY and/or DeltaYX bitfields are
not null in order to perform a rotation by any angle.
2.2.3 Blit Control Flow
Once the data path and functionality have been configured, the blit operation is started by writing a
‘1’ to the Start bitfield of the ’Pixel Engine Store Unit Control register (GFXPIX_store0_Control)’.
Note, that the ShadowLoad field for all fetch units involved must have been programmed to ‘1’ for
this procedure to work, otherwise any configuration changes have no effect because the registers
involved are shadowed.
The end of operation can be detected by setting up an interrupt for the pixeng_store0_rdy event (see
’Iris-SDL System Events and Interrupt Mappings’), whereby ‘end’ means that the last destination
pixel has been written to memory. After this has been detected, the next blit operation can be configured.
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Pipline
configuration
Components
configuration
Start blit
operation
another
blit
Wait for blit
completed
done
As all configuration data is shadowed, it is alternatively possible to set up a new blit operation even
though the previous one is still operating. This can improve overall performance for a series of blit
operations significantly. To do this, the Pixel Engine synchronizer for the store0 unit must be initially
configured by programming the bitfield STORE0_MST_EN of the ’Pixelbus Store0 Sync register
(GFXPIX_STORE0_SYNC)’ to value store0 (10). Also during the pipeline configuration, the same
value must be applied to the <unit>_SHDW fields for all the submodules used in the blit path.
Once the blit operation is configured, the synchronizer has to be started first by writing a ‘1’ to
STORE0_START field before the blit is started as described above.
Then the ‘end of shadow load’ must be detected by setting up an interrupt for the pixeng_store0_shd
event (see ’Iris-SDL System Events and Interrupt Mappings’). After this, a new operation can be
configured.
Note that there is one exception from the mechanism above: The lookup table content (lut0 unit) is
not shadowed. If a modification is required, the software must wait for the blit complete
(pixeng_store0_rdy event).
2.2.4 Extended Configurations
Re-configuration of display layers into the blit path is not allowed, because the power consumption
can exceed the specified maximum power for Iris-SDL.
2.2.5 Performance Measurement
After a blit operation has been completed, the application software can determine the achieved performance by reading out the PerfResult bitfield of the Store0 Performance Counter register before
starting a new operation. The measured destination pixel rate for the recent blit is calculated using
the following formula:
pixel_rate = frame_width * frame_height * bus_clock_frequency / PerfResult
2.3
Display Operation
Display operation constantly drives an external LCD panel with pixel data read from display buffers
in local memory. It entails reading one or several images (layers), executing color processing (e.g.
layer blending and dithering), creating a horizontal and vertical blanking area as required by the panel and generating fully configurable timing signals needed to drive the connected panel. An optional
signature can be computed from the active display content and checked against a pre-computed
reference value to make the detection of corrupted display output possible (safety aspect).
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2.3.1 Clock Settings
When memory access and layer processing operate at bus clock frequency, the display controller
is driven with the pixel clock required by the externally connected panel.
The Iris-SDL Global Control Unit must be configured to provide the correct pixel clock and (optionally) RSDS bit clock signals for the Display and Timing Controller, which are derived from the reference clock as provided by the Titan system. For details see

The Titan specification.

’Clock Adjust register (GFXGCTR_ClockAdjust)’ in this document.

The Timing Controller chapter of this document.

The specification of the externally connected panel.
Also consider constraints to bus clock frequencies as documented in section ’Setup Constraints’.
2.3.2 Layer Configuration
The composition of the active display area is done with the Pixel Engine. The pipeline and components configuration is done in the same way as setting up the blit path as described in ’Pipeline Configuration’ and ’Components Configuration’. For functional details refer to the following chapters:

Pixel Engine

Pixel Engine (PixEng) CLUT

Pixel Engine (PixEng) Extdst

Pixel Engine (PixEng) Fetch

Pixel Engine (PixEng) Layerblend
Also see section ’Synchronization Techniques’ for synchronization related settings.
Memory
Fetch #3
(RLD)
Fetch #4
Fetch #5
Fetch #6
Fetch #7
(Light)
Backgr.
Foregr.
Foregr.
Foregr.
Mask
Layer
Blend #0
Rop
#1
Layer
Blend #1
internal
kick
Rop
#1
PixEng display path
Switchable unit
Layer
Blend #2
Rop
#1
Rop
#1
LUT #1
Signature
Unit
ExtDst
#0
Display
Controller
Timing
Controller
LCD Panel
external kick
Figure 2-5: Default display path in Pixel Engine
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The output of the Pixel Engine display path is generic RGBA 10-10-10-1 bit data for all pixels of the
active display area. Its configuration is independent of the properties of the connected panel. The
1-bit alpha channel can be used as a mask bit for signature computation (see ’Control Flow’).
2.3.3 Panel Configuration
The Display Controller and Timing Controller must be configured according to the requirements of
the external display. For details refer to the following chapters:

’Display Controller (DISP)’

’Timing Controller (TCON)’
and to the panel specification.
Please refer to the Titan documentation for details about the pinning of Iris-SDL TCON signals within
the context of the system.
2.3.4 Synchronization Techniques
Special care has to be taken when the display buffer content or the configuration of the display path
is changed during display operation in order to to avoid visible artifacts.
The following descriptions cover the three most common applications. For all of these, the Pixel Engine Synchronizer must be configured by setting the EXTDST0_MST_EN bitfield of the ’Pixelbus
Extdst0 Sync register (GFXPIX_EXTDST0_SYNC)’ to the value extdst0 (01). Also, during the pipeline configuration the same value must be applied to the <unit>_SHDW fields for all the submodules
used in the display path.
2.3.4.1
Single Display Buffer
The simplest setup is to use just a single display buffer, without any synchronization to the panel
timing. This saves video memory, however it does not allow you to monitor when a change to the
display buffer becomes visible on the screen and consequently this results in tearing and undefined
display content during rendering. A single display buffer should therefore only be used for static display content or for test purposes only.
For this method, the extdst0 unit must be programmed to continuous kick mode (see ’Pixel Engine
ExtDst Control register (GFXPIX_extdst0_CONTROL)’ - KICK_MODE field,
CONTINUOUS_NON_OVERLAP). A ‘kick’ in this context is a signal that triggers fetching the next
display frame from memory. With the setting described, this kick is generated whenever the previous frame has been completed by the Pixel Engine. Synchronization to the refresh rate of the panel
occurs implicitly by stalling the pixel pixel pipeline from the Display Controller, which operates at pixel clock frequency.
Changes to the configuration of the display path (such as blend modes etc.) can be done at any
time. They won’t have any effect before starting the extdst0 synchronizer (by writing a ‘1’ to
EXTDST0_START in the ’Pixelbus Extdst0 Sync register (GFXPIX_EXTDST0_SYNC)’). This loads
the shadow registers into the active configuration. This is automatically synchronized to the next
frame start in order to guarantee a consistent setup for each display frame.
2.3.4.2
Dual Display Buffers
This is the most common method for dynamic content as it guarantees tearing-free display operation. Two display buffers are used, one for the current frame (being displayed) and one for the next
frame (being rendered).
The configuration is the same as described in the previous section for single buffering. When the
software has finished rendering the next frame, it simply needs to swap the display buffer address
in the configuration of the fetch units in the display path and to start the extdst0 synchronizer.
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The synchronizer must then wait for a pixeng_extdst0_shd event (see ’Iris-SDL System Events and
Interrupt Mappings’) before starting to prepare the next frame in the other buffer. Note that by using
this method, the maximum frame rate being rendered is implicitly limited to the refresh rate of the
display.
2.3.4.3
Single Buffer with Blit During Blank
For applications that have excessive memory size requirements, an alternative is to use a single
display buffer and to change its content during the vertical blanking period of the display. This combines the advantages of both single buffering (low memory footprint) and dual buffering (display
quality) however it is critical with respect to the time duration for rendering a frame. If rendering has
not completed before the end of the vertical blanking interval, this may lead to artifacts.
In contrast to the previous methods, the extdst kick mode must be set to EXTERNAL. In this case,
the kick signal is generated by the Display Controller and it’s temporal position must be programmed
in relation to the total frame size (see ’Pixel Engine Trigger Point register (GFXDISP_PixEngTrig)’).
The kick signal position must be set very close to the first active pixel (end of vertical blank), however, with some degree of tolerance, required to gap the latency from the fetch units to the Display
Controller. If the tolerance is too low, the display FIFO may run empty, resulting in a single black
frame being displayed. If the tolerance is too high, the time available to render a new frame is decreased. Please see ’Common Setup’ for recommended values.
The software must be triggered to update the display buffer on the pixeng_extdst0_rdy event. For
the best possible performance, this should trigger an instruction list for the Command Sequencer
with blit operations ’Command Sequencer Operation’.
In order to detect rendering violations with respect to the vertical blanking interval, the software can
setup one of the programmable Display Controller interrupts (disp_pInt0/1/2). The frame position of
the corresponding event should match the position of the external kick signal as described above
(see GFXDISP_INT<n>Trigger registers). Rendering must be completed before this event in order
to avoid display artifacts.
2.3.5 Control Flow
To achieve clean display turn-on, first configure the pixel clocks, the Pixel Engine, Display Controller
and Timing Controller, then set DEN in the ’Display Controller Enable register
(GFXDISP_DisplayEnable)’ of the Display Controller (this will start driving the panel with black pixels) and finally turn on the display buffer fetching by setting KICK_MODE of the ExtDst unit (’Pixel
Engine ExtDst Control register (GFXPIX_extdst0_CONTROL)’), depending on the synchronization
method used.
For clean display turn-off, first set KICK_MODE to OFF, then wait for the disp_smallInt event (display FIFO underrun) and finally disable DEN.
These procedures are not mandatory, but prevent display of a corrupted frame during turn on/off
sequence and leave both the Pixel Engine’s display path and the Display Controller in the idle state.
2.3.6 Signature Check (Safety)
In order to detect corrupt display output, the software can pre-compute a signature value for specific
frames and setup the signature unit to compare this value against a signature computed in hardware
from the actual frames being displayed.
A signature violation can be detected with the Iris-SDL system event sig_error (see Iris-SDL Interrupts section). All events from the signature unit can be mapped to interrupts or Command Sequencer status bits in the Iris-SDL Global Control Unit. Register fields with interrupt functionality in the
SigUnit configuration are made obsolete by this!
Due to safety aspects, the sig_error event always activates the Iris-SDL non-maskable interrupt output (NMI).
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Also a sig_error immediately turns the display black when ’Interrupt Enable register
(GFXSIG_IENW0)’.IEnDiff is enabled. A black display can be re-activated by disabling IEnDiff or by
clearing ’Interrupt Status register (GFXSIG_InterruptStatusW0)’.IStsDiff. Note, that this mechanism
does not stop display operation, but only multiplexes black colors into the pixel stream. Since this
works without any software interaction, it allows to prevent displaying corrupt data, even if the CPU
hangs due to hardware or software failure.
The Signature Unit can select one of four sources to compute the signature (’Signature Unit General
Configuration register (GFXSIG_SigCtrl)’.SrcSel field), from which two are connected only in
Iris-SDL: 0 = raw pixel data (Display Controller input), 1 = dithered pixel data (Display Controller Output).
Signature computation can be restricted to a rectangular sub area of the screen by using the mask
window feature of the Signature Unit.
Alternatively it can be restricted to any combination of pixels by using the 1-bit alpha value as computed by the Pixel Engine for each pixel as a mask bit. Only pixels with alpha = 1 (opaque) are included into signature computation. Most typically this information is stored in a separate 1 bpp layer
(bit mask), but can also be derived from any per-pixel alpha value resulting from the blending stages
(see ALPHA_MODE in ’Pixel Engine ExtDst Control register (GFXPIX_extdst0_CONTROL)’). Note,
that this feature cannot be disabled in the SigUnit. If not needed, the 1-bit alpha should be programmed to constant 1 with ALPHA_MODE = ON.
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2.3.7 Setup Constraints
This section describes constraints for the Iris-SDL system that are required to guarantee stable display output. The setup procedure for three main applications is described:

Operation mode

Rotation mode

Display mode
Also considerations for other setups are given.
In general unstable display operation can be detected with the disp_smallInt event (see ’Iris-SDL
System Events and Interrupt Mappings’).
2.3.7.1
Operation Mode
In operation mode the following constraints for the usage of the Iris-SDL system exist:
Display path:

no 90° or 270° rotation (swap direction) for any layer is allowed.
Blit, Cmdseq path:

no limitation for the different buffer of the store/cmdseq units regarding memory location, etc
are given.

no limitation for the AXI burst length of the different AXI master (store, cmdseq, blit path fetch)
are given.
Host path:

host write access to the display memory can be done with maximum speed of the host.

no pipelined read from the host system or a maximum burst length of 4 for pipelined reads
from the host system

no stalling of the read data for a read from the main system is allowed. (because a stall from
the main system is not predicable and can not be taken into account)

no stalling of the write ready from the main system is allowed (because a stall from the main
system is not predicable and can not be taken into account)
Clock setup:

pixel clock frequency (pixclk) = depends on display (maximum 40MHz or 36MHz or 30MHz)

busclk clock frequencies = 128 MHz

pixel engine display throttling (register ’Extdst0 Unit Clock Throttling register
(GFXPIX_EXTDST0_CLK)’.EXTDST0_DIV) = 2 times the selected pixel clock frequency
(value can be calculated as 128*pixclk/busclk*2, e.g. for 40MHz pixel clock is
((128*40MHz)/128MHz)*2 = 80)
2.3.7.2
Rotated Mode
In this mode a maximum of one layer for the VRAM interface is rotated by 90° or 270° (swap direction). For the blit, cmdseq and host path the same restrictions as in the operation mode are given
plus

The maximum display clock frequency is 20 MHz (if no 24bpp mode is used)

The maximum display clock frequency is 13 MHz (for 24bpp mode)
Clock setup:
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
pixel clock frequency (pixclk) = depends on display (maximum 20MHz or 13 MHz)

busclk clock frequencies = 128 MHz

pixel engine display throttling (’Extdst0 Unit Clock Throttling register
(GFXPIX_EXTDST0_CLK)’.EXTDST0_DIV) = 2 times the selected pixel clock frequency
(value can be calculated as 128*pixclk/busclk*2, e.g. for 20MHz pixel clock is
((128*20MHz)/128MHz)*2 = 40)
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Display Mode
In the display mode the Iris-SDL system is setup in a way that a stable display is guaranteed with
the minimum required busclk (power save mode with minimum power).
For this setup no read or write access from other master than the display fetches to the display
VRAM interface is allowed. A display VRAM interface is the interface to a VRAM where at least one
display layer is stored.
Clock setup:
For the VRAM interface the bpp value of all connected display fetch units has to be summed up. If
a fetch unit uses 90° or 270° rotation (swap direction field set) a value of 128 (instead of the bpp
value) has to be used. The larger value of the two sums is used for the minimum busclk frequency
calculation:
If the larger_VRAM_sum < 64 then
minimum_busclk_frequency = pixclk_frequency * 1.5
display throttling = 128
else
minimum_busclk_frequency = pixclk_frequency * 1.5 * larger_VRAM_sum /
64
display throttling = 128 * 64 / larger_VRAM_sum
2.3.7.4
Common Setup
External kick signal position:
For a setup which uses the kick from the display controller (external kick) the kick signal has to be
programmed at least 100 pixels before frame start.
Arbiter setup:
All the fetch units of display have to be in the priority group with the highest priority. E.g. all display
fetch units are programmed to priority level 0 and all other AXI master have a priority level > 0. For
programming, see the ’Bus Matrix Setup’ section. If a fetch unit is switched between display and blit
pipeline the priority level must be adapted.
Fetch buffer setup:
For all display fetch units the burst length has to be programmed to 2 when the swap direction field
is set to ‘0’. When the swap direction field is set to ‘1’, the burst length should be programmed to 1.
The number of buffers should be set to the maximum number which is allowed for the selected burst
length.
Display setup:
2.3.7.5

A minimum of 16 pixel horizontal blanking is needed.

pixel clock frequency (pixclk) = depends on display (maximum 40MHz)

busclk clock frequencies = 128 MHz

pixel engine display throttling (’Extdst0 Unit Clock Throttling register
(GFXPIX_EXTDST0_CLK)’.EXTDST0_DIV) = 2 times the selected pixel clock frequency
(value can be calculated as 128*pixclk/busclk*2, e.g. for 40MHz pixel clock is
((128*40MHz)/128MHz)*2 = 80)
General Recommendations
If possible the burst length of all agents in the system should be reduced to 2 for better arbitration
in the AIX Interconnection Bus.
2.4
Command Sequencer Operation
The command sequencer can be used to automatically write configuration registers with synchronization points to Iris-SDL events. The configuration data has to be prepared at any memory location
along with a command list for the sequencer. This is typically used to process a sequence of blit
operations as described previously and has primarily three advantages over a direct control flow:
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
The main system’s CPU is freed from waiting for Iris-SDL events such as shadow load or blit
operation complete before continuing to prepare subsequent graphics operations. So the
software can be implemented without inefficient status polling techniques and without complex
synchronization structures based on interrupt handling.

The CPU does not need to directly write configuration registers but to memory only for most
data. Typically this has higher performance due to lower access latency and consequently
results in less processing time for the CPU. An additional optimization step could write data
into a local main system RAM for lowest possible CPU load and then transfer it via DMA into
Iris-SDL video memory.

Once configuration data for certain operations has been prepared by the CPU in memory, it
can be re-used any times for subsequent operations.
In summary the command sequencer acts as a co-processor specialized for graphics operations in
order to relax load situation for the main system processor and to simplify software architecture.
2.4.1 Command Lists
Required sequencer commands are primarily write/copy and sync instructions. They are used to
write configuration registers from data prepared in memory by the CPU and to stop processing until
a specific Iris-SDL system event is triggered.
Instructions are sequentially written into a command FIFO and immediately processed. This FIFO
is accessed through the software interface of the Command Sequencer (see HIF register). Physically the data is located in any system memory. For best performance the Iris-SDL video memory is
recommended. Address location and size of the FIFO is configurable (see ’Command Sequencer
Buffer Address register (GFXCMD_BufferAddress)’ and ’Command Sequencer Buffer Size register
(GFXCMD_BufferSize)’).
Instructions can also be sent to any other memory location and executed by writing a CALL command into the command FIFO (sub routines). Note however, that instruction processing is strictly
sequential. Flow control, such as loops or conditional branches is not supported.
For further details and additional instructions and features (such as FIFO fill state control and watchdog functionality) refer to the Command Sequencer chapter.
2.4.2 Event Synchronization
SYNC commands refer to a 24-bit system status. Each bit is mapped to a Iris-SDL system event as
documented in the Maskable Interrupts table. These events must be enabled for Command Sequencer use in the Iris-SDL Global Control Unit.
When enabled, the level sensitive status as seen by the Command Sequencer becomes active
when the event occurs or when software writes the preset bit. It stays active until the clear bit is written or the event disabled. Clearing the status should be done by the Command Sequencer itself with
an instruction subsequent to the SYNC. In this way the Sequencer acts as an event handler. No software interaction with the CPU is required.
Note that this mechanism is completely independent from setting up events for triggering main system interrupts. However, a single Iris-SDL event can be configured to additionally trigger a system
interrupt with a separate handler executed on the CPU when needed.
2.5
External SPI Memories
External memory devices, typically serial flash ROMs, can be connected to Iris-SDL through a quad
SPI interface. Once configured, the memory is mapped to system address space (see SPI memory
space) and can be accessed by any of the operations described in this chapter. Remember that the
maximum bandwidth is significantly lower compared to video RAM access.
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2.5.1 Clock Settings
The peripheral clock for the HS-SPI (from which the external SPI clock is derived) is provided by the
Titan system. Refer to the corresponding Hardware Manual specification.
2.5.2 Device Setup
The HS-SPI must be configured in master mode on SPI side and in indirect (= command sequencer)
mode on AXI side in order to allow memory mapped access.
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Chapter 3: Global Control Unit (GCTR)
The Global Control unit contains the clock generation and distribution system of the Iris-SDL graphics core. It controls clock gating for Iris-SDL submodules for power saving (note that Iris-SDL forms
Power Domain (PD5) in the context of the Titan device). The Global Control unit collects interrupts
from the Iris-SDL submodules and drives the interrupt lines of the Iris-SDL system. Furthermore it
generates reset signals for the Iris-SDL submodules, both for hardware and software reset. It contains test logic, e.g. clock multiplexers, to support scan testing.
3.1
Clock Generation, Distribution and Domains
For an overview of the clock generation and distribution of the Global Control Unit, please refer to
the block diagram below. Basically one can distinguish between the following domains:

Bus clock domain

Pixel clock domain

Peripheral clock domain
The bus clock domain operates the Pixel Engine, the Video RAM, the AXI Interconnect Bus, the
Command Sequencer and it clocks all the AHB configuration blocks of the Iris-SDL submodules.
The pixel clock domain supplies the Display Controller, Timing Controller and Signature Unit. The
input clock ref_clk, running at a frequency fref_clk , can be divided by a programmable divider using
divisors n = {2, 3, 4 ... 255}. This generates the clocks pix_clk and pix_del_clk which run at a frequency of fref_clk /(2*n) and the clock pix_x2_clk and pix_x2_del_clk which run at a frequency at
fref_clk /n. The clocks pix_del_clk and pix_x2_del_clk can have a programmable delay in steps of the
source clock ref_clk period. The Display Controller, Timing Controller (TCON) and Signature Unit
run at pix_clk. The clock pix_x2_clk signal, runs at twice the pix_clk clock frequency and is used to
supply the Timing Controller submodule (TCON). The delay clocks pix_del_clk and pix_x2_del_clk
are used to adjust setup or hold timings on the output ports of the display interface.
The maximum frequency of the bus clock (bus_clk) is 160 MHz. The maximum frequency of the reference clock (ref_clk) is 400 MHz.
NOTE After a reset, it is necessary to setup the pixel clock using a strict sequence of steps. If the
order of the steps is changed, it is possible that the system may become instable:
1) Release the Iris-SDL hardware reset (RESETN)
2) Turn on (glitch-free) the external clock source (REF_CLK)
3) Modify the clock adjust settings in the Global Control unit.
It is important that the clock settings in Iris-SDL are not changed from the reset values
before the external reference clock is active.
NOTE Please also note that the reset synchronization mechanism for the pixel clock domain
(pix_clk) is driven by pix_x2_clk, which is derived from ref_clk. This means that a reset will
not occur in the pixel clock domain until the refence clock is active. It is necessary to restrict
the pixel clock domain to 80MHz as it would otherwise be 400MHz, due to the time required
for the reset values for clock adjust to propagate into the pixel clock domain.
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Global Control Unit (GCTR)
co nfi g u nit
AHB
config
(A HB S lave)
bu s_ clk
config
pix_clk
pix_x2_clk
Clock
Division
ref_clk
pix_de l_clk
pix_ x2 _del_ clk
int0
in t[i-1:0]
int1
i
i nt_ ctrl
nmi
config
i ntcs[i- 1:0 ]
i
HRES ETn
bu s_ clk
vram_r stn
p eng_r stn
rst_ ctrl
csequ _rstn
p ix_ x1_ clk
sig_ rstn
re se tn
test_mode
co nfi g
di sp_ rstn
Figure 3-6: Global Control Block Diagram
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oSCLK_spi (100 MHz)
PER_CLK
100 MHz
Clock
divider
SPI
iSCLK_spi
100 MHz
Pixel
engine
VRAM_IF
BUS_CLK
160 MHz
AIC
pix_clk (40 MHz)
pix_x2_clk (80 MHz)
pix_del_clk (40 MHz)
REF_CLK
400 MHz
pix_del_x2_clk(80 MHz)
clkgen
SIG
DISP
TCON
CMD
globalctrl
data_a0/1_t con[12]
(using as clock pins)
IRIS
Balance cts (synchronous
clock domains)
asynchronous clock domains
Figure 3-7: Iris-SDL Clock Structure
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Global Control Unit (GCTR)
3.1.1 Pixel Clock Setup
The following diagram illustrates the clock signal paths and related bitfields of the “Clock Adjust register (GFXGCTR_ClockAdjust)” which influence the pixel clock setup.
Figure 3-8: Pixel Clock Generation
Basically, the pixel clock can be generated from the fast internal PLL clock (up to 400 MHz) or from
a (relatively slow) external clock (this is set in the Titan configuration).
If the PLL clock is used (bypass_x2_clk = 0), it is divided by the value programmed in the div_pix
bitfield of the GFXGCTR_ClockAdjust register. Please note the value of div_pix is related to twice
the pixel clock frequency, since the pixel clock itself is generated by a further fixed by-two division.
The pixel clock can be shifted in relation to the pixel data by programming the value shift_pix (same
register) in steps of the PLL clock cycle. Please note that the TCON must be configured accordingly
in order to select this clock as the pixel clock. Please refer to the chapter “Timing Controller (TCON)”
for details.
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If the external clock is used, it is used as the pixel clock without programmable clock division
(bypass_x2_clk = 1). Nevertheless, when using the TCON, the external clock must run at twice the
pixel clock frequency because a further by-two divider is established to create the pixel clock (set
bypass_clk = 0). If the TCON is bypassed, the external clock and the pixel clock run at the same
frequency (set bypass_clk = 1). Please check the table below for detailed register settings for the
pixel clock generation when running the described operating modes.
Table 3-8: Pixel Clock Setup
Register Bitfield
Use Case:
div_pix
bypass_clk
bypass_x2_clk
shift_pix
inv_clk
The in ternal
PLL clock is
used as the
pixel clock
source
Program to
the required
divider value
NBY (0x0)
NBY (0x0)
Program to the
required shift value
0x0
The TCON is
enabled, the
external clock
signal is used
as the pixel
clock source
Not used (set
to 0xFF)
NBY (0x0)
BY (0x1)
Not used (set to
0xFF)
0x0
The TCON is
bypassed, the
external clock
signal is used
as the pixel
clock source
Not used (set
to 0xFF)
BY (0x1)
BY (0x1)
Not used (set to
0xFF)
Set to 0x1 if
an inverted
pixel clock is
required, else
set to 0x0
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3.2
Global Control Unit (GCTR)
Iris-SDL Interrupts
The Iris-SDL Interrupt Controller collects interrupts generated by the Iris-SDL submodules. The interrupt lines of these submodules are synchronized to the bus_clk domain. By default, the submodule interrupt lines are pulse shaped. The interrupt pulse sets a corresponding bit in the Interrupt
Status Registers (“Interrupt Status 0 register (GFXGCTR_IntStatus0)”, “Interrupt Status 1 register
(GFXGCTR_IntStatus1)”). The logical AND of this bit of the Interrupt Status Registers and its corresponding enable bit in the Interrupt Enable Registers (“Interrupt Enable 0 register
(GFXGCTR_IntEnable0)”, “Interrupt Enable 1 register (GFXGCTR_IntEnable1)”) is mapped to either the int0 or int1 output pin. The mapping of the individual interrupt bits can be configured using
the “Interrupt Mapping 0 register (GFXGCTR_IntMap0)” and the “Interrupt Mapping 1 register
(GFXGCTR_IntMap1)”.
Writing to the “Interrupt Clear 0 register (GFXGCTR_IntClear0)” and to the “Interrupt Clear 1 register
(GFXGCTR_IntClear1)” clears the corresponding status bit in the GFXGCTR_IntStatus0,
GFXGCTR_IntStatus1 registers. It is also possible to preset these registers by writing to the corresponding bit position in the “Interrupt Preset 0 register (GFXGCTR_IntPreset0)”, and “Interrupt Preset 1 register (GFXGCTR_IntPreset1)” by software.
The HS-SPI submodule delivers level-shaped interrupts and is processed differently. Although the
corresponding bits in the GFXGCTR_IntStatus0 register reflect the status of the interrupt, the
GFXGCTR_IntEnable0 and GFXGCTR_IntMap0 registers must still be configured accordingly, because the clearing and presetting the HS-SPI bits is done within in the submodule itself.
As the Signature Unit is used to detect safety-critical error conditions in the display path, the
sig_IStsDiff interrupt is of special importance and is therefore mapped to a dedicated interrupt output, namely the non-maskable interrupt output (NMI). The sig_IStsDiff interrupt is handled like a
standard pulse-shaped interrupt with one exception; its enable bit is stuck at ‘1’ meaning that this bit
can not be disabled by software. A second status bit of the Signature Unit interrupt exists for applications that don’t use the NMI output of the Iris-SDL subsystem. In this way the Signature Unit interrupt sig_IStsDiff can also be mapped to the int0 or int1 outputs and in this case, the interrupt acts
like a standard pulse-shaped interrupt (including support of the enable bit).
In addition, the synchronized interrupt inputs are fed to a second register set for the Command Sequencer. This second register set includes:
3-6

the read-only Command Sequencer (CS) interrupt status registers (“Command Sequencer
Interrupt Status 0 register (GFXGCTR_CsIntStatus0)”, “Command Sequencer Interrupt Status
1 register (GFXGCTR_CsIntStatus1)”) which store the status of each interrupt bit

the CS Interrupt Preset Registers (“Command Sequencer Interrupt Preset 0 register
(GFXGCTR_CsIntPreset0)”, “Command Sequencer Interrupt Preset 1 register
(GFXGCTR_CsIntPreset1)” for presetting interrupt status

the CS Interrupt Clear Registers (“Command Sequencer Interrupt Clear 0 register
(GFXGCTR_CsIntClear0)”, “Command Sequencer Interrupt Clear 1 register
(GFXGCTR_CsIntClear1)” for clearing the interrupt status and

the CS Interrupt Enable registers (“Command Sequencer Interrupt Enable 0 register
(GFXGCTR_CsIntEnable0)”, “Command Sequencer Interrupt Enable 1 register
(GFXGCTR_CsIntEnable1)” for enabling the respective interrupt bit for the Command
Sequencer.
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Revised 24/7/13
Enable Register
HCLK
source
clock 0
Global Control Unit (GCTR)
int[1]
Syncr.
HCLK
source
clock 1
.
.
.
int[i-1]
int0
to Host
.
.
.
int1
sigint
HCLK
Syncr.
Mapping Register
NMI Status Reg.
Clear / Preset
Register
source
clock k
.
.
.
.
.
.
HCLK
source
clock k
Syncr.
Mapping Logic
Syncr.
Interrupt Status Register (ro)
int[0]
to Host
nmi
CS Int Clear /
Preset Register
CS Interrupt Status Register (ro)
CS Int Enable
Register
to Command
Sequencer
i
intcs[i-1:0]
.
.
.
Figure 3-9: Global Control Interrupt Diagram
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Revised 24/7/13
Global Control Unit (GCTR)
The interrupts are listed and described in the section “Iris-SDL System Events and Interrupt Mappings”.
Interrupts generated by the Iris-SDL Graphics Core are high active. Those which are set to '1' by the
respective Iris-SDL submodule must be cleared by writing to the respective register by software. Interrupt signals between Iris-SDL sub blocks and Global Control are either active with a rising edge
(pulse trigger) or at a high level (level sensitive) and can be synchronous to any of the clocks used
in Iris-SDL.
3-8
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Global Control Unit (GCTR)
Revised 24/7/13
3.2.1 Interrupt Control Flow
The interrupt control flow is visualized in the flow chart below.
First the clear register GFXGCTR_IntClear0/GFXGCTR_IntClear1 must be written to in order to
clear pending interrupts. Secondly, the required interrupt sources are enabled by writing the corresponding bits in the interrupt enable register GFXGCTR_IntEnable0/GFXGCTR_IntEnable1.
Start
Write IntClear =
32'hFFFFFFFF
Write IntEnable
Y
Interrupt ?
Process Interrupt
N
Figure 3-10: Global Control Flow Diagram
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Revised 24/7/13
3.3
Global Control Unit (GCTR)
Iris-SDL Reset Controller
The Iris-SDL Reset Controller is designed to take the internal timing requirements of its different
subcomponents into account and synchronizes their resets to their related clock domains.
AHB bu s
SW reset r egiste r
test_mode
sw_rstn
clk
test_mode
„1"
resetn
resetn
out_rstn
HRESE Tn
bus_clk
clk
test_mode
sw_rstn
resetn
Reset Sync Module
out_rstn
vram_rstn
clk
test_mode
sw_rstn
resetn
Reset Sync Module
out_rstn
pen g_rstn
clk
test_mode
sw_rstn
resetn
Reset Sync Module
out_rstn
cse qu_r stn
pix_clk
clk
test_mode
sw_rstn
resetn
Reset Sync Module
out_rstn
sig _rstn
clk
test_mode
sw_rstn
resetn
Reset Sync Module
out_rstn
disp_r stn
Reset Sync Module
Figure 3-11: Global Control Reset Generation
Due to an internal reset synchronizer mechanism, the internal reset signals for submodules are delayed by one to two target clock domain signals, as the following diagram indicates.
3 - 10
Fujitsu Semiconductor Europe GmbH
Global Control Unit (GCTR)
Revised 24/7/13
bus_clk
resetn
<ip>_clk
<ip>_rstn
enabled
asynchronously
disabled
synchronous to <ip>_clk
Figure 3-12: Internal Reset Signal Delay
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3 - 11
Revised 24/7/13
3 - 12
Global Control Unit (GCTR)
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AXI Interconnect Bus (AIC)
Revised 24/7/13
Chapter 4: AXI Interconnect Bus (AIC)
The AXI Interconnect Bus is the central module within Iris-SD responsible for the routing of data
paths from one submodule to another. Almost all the submodules within Iris-SD are connected to
the AXI Interconnect with one or more AMBA buses.
Master Ports
Interconnect
error_o
Monitor
AddressDecoder
MEMBASE,
REGBASE
HPM
ConfigurationRegisters
Slave Ports
Figure 4-13: AXI Interconnect Bus Block Diagram
Figure 4-14: High-Performance Matrix (HPM) Block Diagram
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Revised 24/7/13
4.1
AXI Interconnect Bus (AIC)
Feature List
The AXI Interconnect has the following features:

3 layer AXI Interconnect Matrix

Fully-decoded address map

Programmable priority for all master ports

LRG arbitration between masters with the same priority

Slave ports can be disabled

Read or write requests to a disabled slave or to an unmapped address respond with an AXI
decode error

Sync bridges are all synchronous

Interrupt is generated if the AXI Interconnect generates a decode error or any slave device
sends an error response. The Master ID of the first invalid access is latched and readable by
software. Note, that this has no impact on the bus protocol between a master and a slave.
4.1.1 AXI Interconnect Matrix Features
The AXI Interconnect module is a 3-layer ARM PL301 High-Performance Matrix for the interconnection of all AXI and AHB master and slave ports of Iris-SD components and the main system.
4.1.1.1
Configurable arbitration scheme
The arbitration schema is a combination of a fixed priority encoder and a LRG (Least Recently
Granted) system. The priority value of each master is programmable via the interconnect module.
Masters with the same priority form a ‘priority group’. As a result of arbitration, a master can move
within its priority group but cannot leave its group, and no new masters can join the group.
Arbitration is granted to the highest priority group from which a member is trying to win access, and
within that group, to the highest master at that time. When a master wins arbitration, it is relegated
to the bottom of its group to ensure that it cannot prevent other masters in its group from accessing
the slave.
4.1.1.2
Arbiting Scheme
The implemented arbitration scheme is a programmable Least Recently Granted (LRG) one.
Interface number
4-2
Description
0
Main system master (msm)
1
Pixel engine fetch #0 (pixf0)
2
Pixel engine fetch #1 (pixf1)
3
Pixel engine fetch #2 (pixf2)
4
Pixel engine fetch #3 (pixf3)
5
Pixel engine fetch #4 (pixf4)
6
Pixel engine fetch #5 (pixf5)
7
Pixel engine fetch #6 (pixf6)
8
Pixel engine fetch #7 (pixf7)
9
Pixel engine store unit (pixw)
10
Command sequender read (cmdr)
11
Command sequencer write (cmdw)
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AXI Interconnect Bus (AIC)
4.1.1.3
Revised 24/7/13
Disabling Slave Modules
Slave ports can be disabled by software by writing a ‘1’ to the corresponding bit of the “Slave Disable
register (GFXAIC_SlaveDisable)”.
Then all requests are processed by the ‘Default Slave” of the HPM module. The requester will receive a DECERR (decode error response) when accessing a disabled slave module.
4.1.1.4
AXI Interconnect Error Handling
When an ERROR response is detected, the ID of the initiator and the type of error (SLVERR or DECERR) are stored by the monitor module and an error interrupt is generated. The application software can tap this information by reading the content of the AXI Interconnect GFXAIC_Status
register. If more than one transfer incurs an error response, only the values of the first erroneous
transfer are stored. The monitor can be armed again by writing a ‘1’ to the Clear flag in the “Error
Monitor Control register (GFXAIC_Control)”.
NOTE This error handling does not affect the transfer of the error response back to the master.
4.1.1.5
VRAM AXI Interface (U_VRAM0)
The VRAM interface implemented has its own read and write AXI layer in the bus matrix and controls
four 256 KB SRAM units. From an application point of view, this results in a 1024KB video memory.
Internally, the memory bank is divided into two sub-banks for even and odd 64-bit word addresses.
As the SRAM types implemented can only operate at half the bus clock frequency, the theoretical
maximum bandwidth for each AXI channel of 1280 MB/s (64-bit @ 160 MHz) can actually drop to
50% in the event of consecutive even or odd address request sequences.
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4-4
AXI Interconnect Bus (AIC)
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Pixel Engine (PIX)
Revised 24/7/13
Chapter 5: Pixel Engine (PIX)
The Pixel Engine combines pixel processing units used for layer composition for the Display Controller and for block image transfer (blit) operations to a memory location.
5.1
Pixel Engine Features
The Pixel Engine has the following main features:
5.2

Flexible pixel processing unit instantiation in two pipelines (display/blit)

Configuration register with an AHB interface

Programmable clock gating with automatic mapping to the display and blit pipelines

Separate pipeline synchronizers

Interrupt signal routing
Pixel Engine Architecture
AXI fetch
AXI fetch
fetch0
fetch7
clk
reset_n
store0_reset_n
extdst0_reset_n
pixel_engine
configuration
AHB
clk enable
generation
processing
unit
busy register
pixel engine
synchronizer
extdst0
store0
pixelbus
pixel_engine
display
AXI store
Figure 5-15: Pixel Engine Block Diagram
In this diagram you can see that the pixelbus module multiplexes the inputs of the various pixel processing units, each of which has its own configuration register. The pixelbus itself is 10 bits wide.
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Revised 24/7/13
Pixel Engine (PIX)
Internally, the Pixel Engine has two configurable processing pipelines; one for the display path
(extdst0) and one for the blit path (store0). This is outlined in the following diagram.
Figure 5-16: Pixel Engine processing pipelines
5.3
Checking the pipeline location of processing units
The configuration registers of the various pipeline units (fetch, lut, rop etc). contain a ..._sel bitfield
which can be read to show the location of the respective unit in the current configuration (either in
the display or blit processing pipeline).
5-2
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Pixel Engine (PIX)
5.4
Revised 24/7/13
Processing ‘kick’ signal
The two pixel processing destinations exdst0 and store0 each issue a kick signal which is routed
through to the fetch units that are connected to the respective pipeline to start processing. The selection signal of each fetch unit defines which of the two kick signals is used.
5.5
Processing units enabled status
The Pixel Engine configuration covers the input ports of the processing units. These can be enabled/disabled using the respective register and this status is internally routed to the input of the two
processing pipelines. These, in turn, can use this signal to reconfigure the pipeline to a new setup.
5.6
Pixel Engine synchronization
Reconfiguring the Pixel Engine’s processing pipelines at runtime requires tightly controlled synchronization activities. These are handled by the Pixel Engine Synchronizer, which can reconfigure the
entire Pixel Engine or simply parts of it. To synchronize, this unit blocks the kick signals for the processing pipelines and waits until the selected pipeline is empty (see the STORE0_MST_EN,
STORE0_SLV_EN, EXTDST0_MST_EN, EXTDST0_SLV_EN bitfields in the STORE0_SYNC and
EXTDST0_SYNC registers). Once the pipelines are empty, the selected pipeline configuration registers (with the SHDW bitfields) are updated, the selected fetch units (with the SHDW bitfields) are
sent a command to issue a shadow update and the pending kick signals are reset. Iris-SDL incorporates two Pixel Engine synchronizers, one for each processing pipeline (display and blit).
Alternatively, the pipeline configuration registers can also be programmed directly if the SHDW bitfield does not exist in the corresponding configuration register.
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Revised 24/7/13
Pixel Engine (PIX)
5.6.1 Synchronization procedure
The synchronization procedure is started by defining which of the two processing pipelines (or both)
display (extdst0) / blit (store0) is to be synchronized. The software controlling the two pipelines must
ensure that purposeful register settings have been made and that - in the case of a pipeline reconfiguration which includes the relocation of a module (e.g. LUT) from one processing pipeline to the
other - that the Master/Slave roles of the two pipelines are correctly defined.
The initial situation is that the respective pipeline defines itself as Master whereas the Slave is set
to ‘disabled’ as indicated in the following table because the pipelines are fixed (i.e. the processing
modules are fixed in one or the other pipeline).
Table 5-9: Initial pipeline synchronization setup
BLIT
PIPELINE
(store0)
DISPLAY
PIPELINE
(extdst0)
Master:
extdst0
Master:
store0
Slave:
- disabled -
Slave:
- disabled -
In a second scenario, processing pipeline modules are relocated from one pipeline to the other. In
this case it is necessary to define the Slave role, because the synchronizer must ensure that the
slave pipeline is first emptied and then the master pipeline, before the shadow registers are updated, relocating the effected processing module.
Table 5-10: Synchronization setup when reconfiguring pipeline modules
DISPLAY
PIPELINE
(extdst0)
BLIT
PIPELINE
(store0)
Master:
extdst0
Master:
store0
Slave:
store0
Slave:
extdst0
Synchronization is setup and triggered using the STORE0_SYNC and EXTDST0_SYNC registers.
The Master/Slave role of the respective pipeline is defined using the STORE0_MST_EN,
STORE0_SLV_EN, EXTDST0_MST_EN and EXTDST0_SLV_EN bitfields. By writing to the
STORE0_START and/or EXRDST0_START bitfields, the synchronization is started. The synchronizer then first blocks the kick of the defined pipeline(s). When the pipeline is empty, the module
configuration registers are updated (shadow load) and then all pending kick events are sent.
If both pipelines need to be synchronized, then the synchronizer will first block the kick signal for the
defined slave pipeline and will wait until this is empty. After this, the kick signal for the master pipeline is blocked and when this pipeline is empty, the register updates are executed. When the update
is completed, all pending master and slave kick events are sent.
Each Pixel Engine configuration register has a ..._SHDW bitfield to select which of the two synchronizers (or both) updates it. This mechanism allows the software to control the display and blit paths
completely independently.
5-4
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Pixel Engine (PIX)
Revised 24/7/13
In addition to updating configuration registers, the shadow registers of all the processing modules
can be updated. In order to do this, the reload of the fetch units can be triggered by the pixel synchronizer. The registers of the individual fetch units also have a ..._SHDW bitfield (as do the configuration registers) which determines which (or both) of the pixel synchronizers will trigger a reload.
The respective pixel synchronizer is started by writing to the STORE0_START or
EXTDST0_START bitfield in the STORE0_SYNC or EXTDST0_SYNC registers. The
STORE0_SYNC_BUSY and EXTDST0_SYNC_BUSY bitfields of the STORE0_SYNC_STAT and
EXTDST0_SYNC_STAT registers can be polled to check if the respective pixel synchronizer is
busy. Alternatively, the pixel engine synchronizer interrupt can be used to check its status.
T0
T1
Synchronization Slave
(e.g. pixblit)
T2
valid
(generated in source)
kick
(generated in destination)
kick
(after synchronization)
Synchronization Master
(e.g. display controller)
valid
(generated in source)
kick
(generated in destination)
kick
(after synchronization)
T0: synchronization request from software, delay all further slave Pixel Bus kicks
T1: all slave Pixel Bus are empty, further kicks of master are delayed
T2: master Pixel Bus is empty, update Pixel Bus configuration register and trigger delayed kick
events
Figure 5-17: Synchronization Timing
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Revised 24/7/13
5.7
Pixel Engine (PIX)
Handling separate Display and Blit Pipelines
Display pipeline setup or (re)configuration:
When the display output is controlled by different software threads, they must be synchronized
(stopped) for this operation in the following way:

ensure that the shadow has been loaded for the display pipeline using the respective interrupt
signal (see Iris-SDL Interrupts section).

clear the shadow load IRQ flag for the extdst0 unit

program the respective pixelbus configuration registers

program the registers of the display modules

setup the extdst0 pixel synchronizer: (“Pixelbus Extdst0 Sync register
(GFXPIX_EXTDST0_SYNC)”)
EXTDST0_MST_EN = 1
EXTDST0_SLV_EN = 0
EXTDST0_START = 1
After the initial display pipeline setup, display processing has to be started:
Start sequence if a blit during vertical blank is needed (frame sync mode)

setup a kick event in the display engine register and start the display engine

start the display pipeline with KICK_MODE = 3 in the “Pixel Engine ExtDst Control register
(GFXPIX_extdst0_CONTROL)” (check for underflow errors in the display and for external kick
errors in extdst0 unit)
Start sequence if no blit during vertical blank is needed (free running mode)

start the display engine

start the display pipeline with KICK_MODE = 2 in the GFXPIX_extdst0_CONTROL register
(check for underflows error in the display)
(Re)configure display layers of the display pipeline
Parts of the pixel engine display pipeline can be combined into layers, which than can be controlled
by a separate software thread. Such layers include the display background or every display overlay
layer. Each layer has one fetch unit and ends if it reaches a non-primary input of a ROP or blend unit.
5-6
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Pixel Engine (PIX)
Revised 24/7/13
fetch
(background)
fetch
(overlay 0)
fetch
(overlay 1)
fetch
(overlay n)
processing
unit
processing
unit
processing
unit
processing
unit
p
s
processing
unit
p
s
processing
unit
p
s
processing
unit
processing
unit
Figure 5-18: Display layers of the display pipeline

check if a shadow is loaded for this display layer, use the shadow load IRQ flag of the
layerblendX unit (see Iris-SDL Interrupts section).

clear the shadow load IRQ flag of this display layer

enable the shadow update of the fetch unit of the desired layer (fetch<n>_SHDW = 1)
Blit pipeline setup or (re)configuration
The Blit pipeline is setup in the following way:

check if a shadow is loaded from a previous blit operation, check the shadow load IRQ flag of
the store0 unit (see Iris-SDL Interrupts section)

clear the shadow load IRQ flag of the store0 unit

program the ..._cfg registers with the new configuration

program the registers of the blit sub modules
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Revised 24/7/13
Pixel Engine (PIX)
The setup needs to be synchronized in order to avoid artifacts:

check that the frame started from the previous blit operation (frame command received IRQ
flag of the store0 unit, see Iris-SDL Interrupts section)

setup the store0 pixel synchronizer (in the “Pixelbus Store0 Sync register
(GFXPIX_STORE0_SYNC)”):
STORE0_MST_EN = 2
STORE0_SLV_EN = 0
STORE0_START = 1
The next blit operation could now directly be started, if required:

check that the frame started from the previous blit operation (frame command received IRQ
flag of store0 unit) (see Iris-SDL Interrupts section)

clear the frame command received IRQ flag of store0 unit

start the blit operation with STORE0_START (in the GFXPIX_STORE0_SYNC register)
Starting a Blit operation
The following steps are required (assuming that the correct configuration has already been setup):

check that the frame started from the previous blit operation (frame command received IRQ
flag of store0 unit) (see Iris-SDL INterrupts section)

clear the frame command received IRQ flag of store0 unit

start the blit operation with STORE0_START (in the GFXPIX_STORE0_SYNC register)
Executing a Blit operation during the next vertical blanking period
Important: if the display is not set up in frame sync mode, only a small (or no) vblanking time will
exist between two display frames.

check if a shadow is loaded from a previous blit operation (shadow load IRQ flag of the store0
unit (see Iris-SDL Interrupts section)

clear the shadow load IRQ flag of the store0 unit

program the ..._cfg registers with new configuration

program the blit sub module registers
In this way, the blit is synchronized to the display’s vertical blanking.

check that the frame started from the previous blit operation (frame command received an IRQ
flag from the store0 unit )

setup the pixel synchronizer (in the GFXPIX_STORE0_SYNC register):
STORE0_MST_EN = 1
STORE0_SLV_EN = 2
STORE0_START = 1
The blit operation is now started.
5-8

check that the frame started from the previous blit operation (frame command received an IRQ
flag from the store0 unit)

clear the frame command received IRQ flag of the store0 unit

start the blit operation with STORE0_START (in the GFXPIX_STORE0_SYNC register)
(if of any interest, poll to check whether that blit is empty before the display becomes active)
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Pixel Engine (PIX)
5.8
Revised 24/7/13
Emptying the Pixel Engine for power down
It is purposeful to empty the Pixel Engine properly before a power down sequence. This can be done
using the following sequence:

Stop the start of blit operations (GFXPIX_STORE0_SYNC.STORE0_START)

Disable display (GFXPIX_extdst0_CONTROL.KICK_MODE = 0)

Wait until GFXPIX_EXTDST0_SYNC_STAT.EXTDST0_KICK_CNT_extdst0 = 1

Wait until GFXPIX_store0_Status.StatusComplete = 1
The Pixel Engine is then empty and can be disabled.
5.9
New pipeline setup
It is assumed that after an initial setup the application will need to use a new setup for further pixel
processing. The starting conditions are that the pipelines are empty, there are no pending blit operations and display is not running.
To start a new setup, all the processing modules need to be disconnected from the original path
(means clearing all existing pixelbus selection configurations). Even if operations are not executed
the module may neither be connected to correct pipeline path nor disabled, because the hardware
maps the module clock depending on the configuration, which can generate several problems.

Empty the Pixel Engine

Remove the shadow of the Pixel Engine configuration registers (..._SHDW register = 0)

Set all the input selections in the Pixel Engine configuration registers to 0

Program the .._SHDW bitfields to reflect the pipeline that the respective modules belongs to
5.10 Relocating processing modules between the display and blit
pipelines
5.10.1 Removing a module from the display pipeline
To remove a module from the display pipeline, a new setup has to be created in which the effected
module is not used by any other display module.

Check if a shadow is loaded for the display pipeline (shadow load IRQ flag of the extdst0 unit)

Clear the shadow load IRQ flag of the extdst0 unit

Check if the extdst0 pixel synchronizer is ready (extdst0 pixel synchronizer IRQ flag)

Clear the extdst0 pixel synchronizer interrupt (irq0)

Program the .._cfg registers with the new configuration

Program the registers of the display modules

Setup the extdst0 pixel synchronizer (GFXPIX_EXTDST0_SYNC.EXTDST0_MST_EN = 1,
EXTDST0_SLV_EN = 0, EXTDST0_START = 1)

Check if the extdst0 pixel synchronizer is ready (extdst0 pixel synchronizer IRQ flag)

Update the ..._SHDW bitfield of the module
After this sequence the module can be used in the blit pipeline.
NOTE The display module shadow registers will be loaded with the next frame. If the display is not
running and the software wants to do a display reconfiguration, the standard configuration
sequence (without the check for a loaded shadow) has to be done first.
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Pixel Engine (PIX)
5.10.2 Removing a module from the blit pipeline
To remove a module from the blit pipeline, a new setup has to be created in which the effected module is not used by any other display module.

Check if a shadow is loaded from a previous blit operation (shadow load IRQ flag of the store0
unit)

Clear the shadow load IRQ flag of the store0 unit

Check if the store0 pixel synchronizer is ready (extdst0 pixel synchronizer IRQ flag)

Clear the store0 pixel synchronizer interrupt

Program the ..._cfg registers for the new configuration

Program the registers of the blit modules

Setup the store0 pixel synchronizer (EXTDST0_MST_EN = 2, EXTDST0_SLV_EN = 0,
EXTDST0_START = 1)

Check if the store0 pixel synchronizer is ready (extdst0 pixel synchronizer IRQ flag)

Update the ..._SHDW bitfield of the module
After this sequence the module can be used in the display pipeline.
NOTE The blit module shadow registers will be loaded with the next blit operation. If no blit is
executed and the software wants to reconfigure the blit pipeline with the standard
configuration sequence, the first shadow loaded check has to be removed.
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Pixel Engine (PIX) Fetch Unit
Revised 24/7/13
Chapter 6: Pixel Engine (PIX) Fetch Unit
A fetch unit is connected to the AXI interconnect bus and fetches frames of up to 1024*1024 pixels
to supply them to the pixel pipeline of the Pixel Engine.
There are three different types of fetch unit:

ROT (rotation)

RLD (runtime length decompression)

Light (streamlined unit)
The functional properties of the different types differ and can be queried via registers. The types are
indicated in parentheses under the name of the fetch unit in the diagrams that describe the pipeline
configuration, e.g. Fetch#2 (ROT) or Fetch #7 (Light).
Shadow Registers
Register Interface to
Config Unit
AXI interface for
memory access
Rasterizer
AXI interface
RLD
(optional)
Color
Conversion
Main
Control
Bi-Linear Filter
(optional)
Multiply Stage
kick_in
Pixel Pipeline to
PixEng Interconnect
Figure 6-19: Fetch unit block diagram and functional flow
After a fetch unit has received a kick signal, its rasterizer provides an address stream which is read
by the AXI interface (can be optionally decoded by an RLD type fetch unit in its internal Run Length
Decoding block). The input data is fed into the color conversion unit which converts the raw data into
pixels and passes these to the bilinear filter (which can perform bilinear filtering - ROT type fetch
units only). The multiply stage follows, where multiplications with constant color/alpha or an alpha
pre multiplication can be performed. Finally, the data is output to the Pixel Engine interconnect bus.
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6.1
6.2
Pixel Engine (PIX) Fetch Unit
Features of the Fetch Units

Flexible AXI buffering to adapt to different use cases. This is achieved using the “Pixel Engine
Fetch Burst Buffer Management register (GFXPIX_fetch<n>_BurstBufferManagement)”

Main Control Logic for pixel pipeline control words
- Shadow load control
- Flexible field bit generation

Rasterizer for fetching of pixels via AXI

Color conversion unit

Alpha constant multiply and Optional: color multiplication (check the “Pixel Engine Fetch
Control register (GFXPIX_fetch<n>_Control)”.

Optional: Run Length Decoding (check the Pixel Engine Fetch Control register
(GFXPIX_fetch<n>_Control)).

Optional: Rotation with nearest or bilinear filtering (check the Pixel Engine Fetch Control
register (GFXPIX_fetch<n>_Control)).
Fetch Unit Input Data Format
A fetch unit supports all pixel formats that are a power of two up to 32 bits or 24 bits width, with up
to 10 bits per color or 8 bits per alpha component. The following diagram shows you an example
and explains the term ‘color component shift’ which is used in to accommodate for different bit width
sizes of color components (e.g. RGB565 - see below) via the “Pixel Engine Fetch Color Component
Shift register (GFXPIX_fetch<n>_ColorComponentShift)”.
Table 6-11: Fetch Unit Input Data Format
RedBits
5
RedShift
0
GreenBits
6
GreenShift
6
BlueBits
5
BlueShift
11
Alphabits
0
AlphaShift
0
Total bits
16
Of course, every color component color shift plus the color bits value itself must be smaller than the
total number of bits per color (total bits). Please note, that if you specify any bits per color value to
zero, the fetch unit will replace it with the respective constant color component.
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Pixel Engine (PIX) Fetch Unit
6.3
Revised 24/7/13
Fetch Unit Co-ordinate System
The following diagram describes the co-ordinate system used by a fetch unit (useful for descriptions
further on in this chapter).
origin
X coordinate
(0,0)
pixel
origin
Y coordinate
(23,4)
6.4
example
(4,3)
pixel
center
(23.5,4.5)
Flexible AXI Interconnect Buffering
The AXI interface of a fetch unit supports a flexible buffering scheme. For example, if the AXI interface has a total of 16 buffers for AXI data words, it can arrange these to either support 4 bursts of
length 4, 8 bursts of length 2 or 16 bursts of length 1.
6.5
Main Control Logic
The fetch units’ Main Control logic can:

insert shadow load commands into the pixel pipeline at the start of a frame.

specify how the field bit is to be generated for the pixel pipeline: it can either be constant 0,
constant 1, or can toggle with a defined start value.
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6.6
Pixel Engine (PIX) Fetch Unit
Rasterizer for pixel fetching via the AXI Interconnect Bus
The rasterizer of a fetch unit can generate address patterns to fetch frames with a resolution of up
to 1024 x 1024 pixels from a source buffer (max. 1024 x 1024 pixels) via its AXI interface. It supports
positive as well as negative scanning directions and the swapping of the x and y directions to allow
rotations (if the fetch type is ROT, please use the Pixel Engine Fetch DeltaXX/YY registers fields to
emulate this behavior (GFXPIX_fetch<n>_Delta...). The rasterizer also supports a skip rectangle to
allow the masking of certain parts of the screen (refer to the “Pixel Engine Fetch Skip Window Offset
register (GFXPIX_fetch<n>_SkipWindowOffset)” and “Pixel Engine Fetch Skip Window Dimensions
register (GFXPIX_fetch<n>_SkipWindowDimensions)”. Masked areas are not fetched from the AXI
interface.
Frame
Source Buffer
Skip rectangle
Tile Pixels
Skip Pixels
Pixels read from buffer
Unused buffer pixels
The source for pixels (within the skip window/rectangle) that are skipped can be selected as either
a transparent black color or a software-specified constant color. Please note that the skip window
specified must be completely inside the source buffer. The start of rasterization is controlled externally via an input pin. If the rasterization is kicked again while a rasterization is already in progress,
the latter start will be delayed until the end of the frame.
Either a constant pixel color, or the pixel color from the source buffer pixel that is closest to the current position can be selected for pixels outside the source buffer. With the constant pixel color setting there is a further choice: either black pixels or the constant color specified in the register
interface. If a pixel is subject to TILE_PAD and the edge of the source buffer from where the pixel
color should be taken is a part of the skip window, then the skip settings will determine the color of
the resulting pixel.
NOTE Please note that if a skip window is specified with a width that is less than 2 times the burst
length/pixel size, it could be ignored
NOTE Func spec restrictions: If the skip window is specified less wide than 2 times burst
length/pixel size the skip window might not have any effect regarding axi bandwidth savings
6.7
Color Conversion
A fetch unit can perform color format conversion from any up to 32-bit wide color format into the internal 10-bit per color or 8-bit per alpha format used by the pixel pipeline of the Pixel Engine. Individual output color components can also be specified to be constant, if their input width is configured
to 0.
Please refer to the “Pixel Engine Fetch Color Component Bits register
(GFXPIX_fetch<n>_ColorComponentBits)” for details.
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Pixel Engine (PIX) Fetch Unit
6.8
Revised 24/7/13
Color Multiplication
After color conversion, a fetch unit can also perform the multiplication of the alpha value with a constant alpha value. If MULTIPLY is read back from the HasMultiply bitfield of the “Pixel Engine Fetch
Control register (GFXPIX_fetch<n>_Control)”, the RGB components can also be either premultiplied with the alpha channel or with a constant color.
The following diagram shows the multiplication circuit/flow, whereby the optional parts (MULTIPLY
is read back) are indicated with a darker shade.
AlphaMultiply
ConstantAlpha
0.8
add
MSB
1.8
MU
LT
0.8
AlphaIn
0.16
round and
truncate
0.8
0.8
AlphaOut
ColorMultiplySelect
add
MSB
ConstantRed
0.8
ColorMultiplyEnable
1.8
0.10
RedIn
MU
LT
0.18
round and
truncate
0.10
0.10
RedOut
0.10
ColorMultiplySelect
add
MSB
ConstantGreen
0.8
ColorMultiplyEnable
1.8
0.10
GreenIn
MU
LT
0.18
round and
truncate
0.10
0.10
GreenOut
0.10
ColorMultiplySelect
add
MSB
ConstantBlue
0.8
BlueIn
ColorMultiplyEnable
1.8
0.10
MU
LT
0.18
round and
truncate
0.10
0.10
BlueOut
0.10
6.9
Optional: Run Length Decoding
This feature is only available if RLD is read back from the FetchType bitfield of the Pixel Engine
Fetch Control register (GFXPIX_fetch<n>_Control).
A fetch unit can then perform run-length decoding of run-length encoded picture data (e.g. TGA™
similar format - please refer to Fujitsu’s MB87P2020A ‘Jasmine’ Hardware Manual). The source buffer width and height must correspond to the decoded width and height for the correct decoding of
the image. In addition, you must specify the number of 32-bit words (minus 1) that are necessary to
decode the entire frame window specified in the RLEWords bitfield of the Pixel Engine Fetch Source
Buffer Length register (GFXPIX_fetch<n>_SourceBufferLength). Please note that decoding is always executed from the source buffer origin. Specifying an insufficient or incorrect number of
RLEWords will inevitably result in a hang up of the fetch unit!
Please note that the skip window is ignored with RLD operations and that frames processed by the
RLD subunit must be entirely within the source buffer.
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Pixel Engine (PIX) Fetch Unit
6.10 Optional: Rotation with Nearest and Bilinear Filtering
This feature is only available if ROT is read back from the FetchType bitfield of the Pixel Engine
Fetch Control register (Control). The following diagram shows the various steps (configurable in the
Pixel Engine Fetch GFXPIX_fetch<n>_DeltaXX/DeltaXY/DeltaYX/DeltaYY registers).
DeltaYX
DeltaXX
DeltaXY
DeltaYY
Ver Step
Hor Step
4 pixels
(bilinear)
1 pixel
(nearest)
The Pixel Engine Fetch GFXPIX_fetch<n>_DeltaXX/DeltaXY/DeltaYX/DeltaYY registers use decimal places in order to be able to read the source buffer in arbitrary directions. Rotation operations
can be realized in this way. Two filter mode options are available to select the final pixel: Nearest
and Bilinear. The mode can be configured using the FilterMode bitfield of the respective Pixel Engine Fetch Control register (GFXPIX_fetch<n>_Control).
Please note that the two filter modes must be configured in a slightly different way: (please also refer
to the diagram below)

For nearest filtering you need to specify point B (center sample point of output pixel).

For bilinear mode you need to set the FrameOffset to point A of the first pixel (center sample
point of first output pixel minus 0.5 in both dimensions). Please also refer to the Pixel Engine
Fetch Frame X/Y Offset registers (“Pixel Engine Fetch Frame X Offset register
(GFXPIX_fetch<n>_FrameXOffset)”, “Pixel Engine Fetch Frame Y Offset register
(GFXPIX_fetch<n>_FrameYOffset)”).
(0,0)
Source buffer pixel
and coordinate system
A
B
Output pixel
(scaled and rotated)
Bilinear box filter
(size is always 1.0 x 1.0)
Deltas
Frame offset
(8,8)
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Pixel Engine (PIX) Fetch Unit
Revised 24/7/13
Please note that for a rotation type fetch unit (ROT), the register fields FrameSwapDirections, FrameXDirection and FrameYDirection do not exist and that the GFXPIX_fetch<n>_DeltaXX/DeltaXY/DeltaYX/DeltaYY registers have to be used to emulate their behavior.
Furthermore, do not use the skip window functionality when executing rotations.
6.11 Fetch Unit Performance Considerations
A fetch unit will deliver 1 pixel per cycle in normal operations or one pixel per 4 cycles with bilinear
filtering if the buffer size is large enough to hide the bus latency on the AXI interface and the buffer
is configured according to the requirements (e.g. 90-degree rotation performs best with many small
buffers, whereas a normal copy might benefit from having a few large buffers).
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6-8
Pixel Engine (PIX) Fetch Unit
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Pixel Engine (PIX) CLUT Unit
Revised 24/7/13
Chapter 7: Pixel Engine (PIX) CLUT Unit
A Color LUT (CLUT) can be used as a color lookup table or as a color index table.
When configured as a color lookup table, it can be used either to compensate the non-linearity of
color transmission or to adapt to the individual characteristics of a physical display panel by converting a logical color to a physical color that can be displayed on a monitor. A logical color (y) would –
in the perfect world – map to an identical physical output color (x) on a display. However, due to
physical transmission tolerances, this relationship is not completely linear. To correct deviations in
the linearity (gamma correction), the output colors in the CLUT are programmed with a corrective
offset factor (k), whereby k is dependant on the panel characteristics. This yields the CLUT function
y = x to the power of k.
A CLUT module can be programmed to act as a color index table. A picture can be reduced to a
maximum of 256 different colors for compression purposes. This means that each pixel of the image
only requires an index value stored in the memory to look up the color value to use.
From a hardware point of view, a CLUT is a simply block of fast RAM with 256 entries, each of which
is 10 bits wide (for each RGB component) which can be programmed by software.
A CLUT unit operates in one of four modes:

Neutral mode: The CLUT is not used and the incoming pixel is routed through directly to the
output (and expanded to 10 bits).

LUT mode: A 10 bit color value (8.2bit ) is looked up for the incoming 8 bit color value.

10 bit index mode: The incoming red color channel is used as an index value to address a
specific color in the CLUT's palette (max. 256 colors are therefore addressable). The LUT is
used for three 10 bit color values, whereby the incoming alpha is bypassed.

RGBA index mode: The incoming red color channel is used as an index value to address a
specific color in the CLUT's palette (max. 256 colors are therefore addressable). The LUT is
used for three 8 bit color values and a 6 bit alpha value.
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7.1
Pixel Engine (PIX) CLUT Unit
Clut Unit Block Diagram
dither
red[9:0]
red[7:0]
red clut
dither
green[9:0]
green clut
green[7:0]
mux
dither
blue[9:0]
blue clut
blue[7:0]
dither
alpha[9:0]
alpha[7:0]
expand
Figure 7-20: CLUT Block Diagram
7.2
Neutral Mode Operation
Incoming pixel data is routed directly to the output, whereby each color is expanded to 10 bits width.
Expansion is done by concatenating 2 msb to the lsb position:
Color_new[9:0] = ((Color<<2)&0x3FC) | ((Color>>6)&0x3);
7.3
LUT Mode Operation
In LUT mode, a 10 bit value is looked up in three different lookup RAMs for each color component
(R,G,B). The alpha value is bypassed.
alpha input value
alpha[7:0]
7-2
red clut [9:0]
red[9:0]
red color
input value
green clut [9:0]
green color
input value
green[9:0]
blue clut [9:0]
blue[9:0]
blue color
input value
output
pixel
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Pixel Engine (PIX) CLUT Unit
7.4
Revised 24/7/13
10 bit Index Mode Operation
In 10 bit indexed mode, a 10 bit value is looked up in the lookup table (using the same index) for
each color component (red, green and blue).
The index used for all the lookup memories is the red component value. The bit size of the red value
used as the index can be programmed. For example, if only 4 bits are used, the 4 msb of the incoming red value are used to address LUT entries 0 ... 16 and the incoming alpha value is bypassed.
7.5
alpha input value
red clu t [9:0]
al pha[7:0]
red[9:0]
i ndex
(red color
i nput value)
green clut [9:0]
i ndex
(red color
i nput value)
gre en[9:0]
blue clut [9:0]
bl ue[9:0]
i ndex
( red color
i nput value)
output
pixel
RGBA Index Mode Operation
In RGBA indexed mode an 8 bit value and for alpha a 6 bit value is looked up in the lookup table for
each color component (red, green and blue) using the same index.
The index used for all the lookup memories is the red component value. The bit size of the red value
used as the index can be programmed.
For example, if only 4 bits are used, the 4 msb of the incoming red value are used to address LUT
entries 0 ... 16.
red clut [9:0]
alpha[5:0]
inde x
(red color
inpu t va lue)
index
(red color
input valu e)
green clut [9:0]
red[7:0]
gre en [7:0]
blue clut [9:0]
b lue[7:0]
ind ex
(red color
inp ut value)
output
pixel
All values are expanded to 10 bits. Expansion is done by concatenating 2 msb to the lsb position.
Color_new[9:0] = ((Color<<2)&0x3FC) | ((Color>>6)&0x3);
Alpha_new[7:0] = ((Alpha<<2)&0xFC) | ((Alpha>>4)&0x3);
7.6
Output Dithering
The 10 bit output values generated in LUT mode or in 10 bit Index mode can be reduced to 8 bits
again by using ordered spatial dithering. The dithering mechanism uses a 2 x 2 ‘bayer’ matrix (see
also http://en.wikipedia.org/wiki/Ordered_dithering).
-2
0
1
-1
Depending on the lsb bit of the frame x and y co-ordinates, the corresponding value of the bayer
matrix is added to the color and alpha values. The result is checked for overflow, underflow and the
8 msb are used as the output value. The two lsb of the output are fixed to zero.
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Pixel Engine (PIX) CLUT Unit
If dithering is enabled for RGBA Index mode and Neutral mode, then only the expansion to 10 bits
is skipped.
7.7
Important Notes
It is recommended that a dither unit is enabled when the CLUT is enabled in order to avoid artefacts.
The CLUT offers spatial dithering, the Display Controller offers spatial and temporal dithering. If using multiple dithering units, enable these in sequence and consider the effects of chaining carefully.
The entire CLUT is - from a hardware point of view - a single port RAM with 256 entries. Writing to
this RAM entails stalling the pixel processing pipeline for one cycle, therefore if the CLUT is updated
during runtime, this should be taken into careful consideration. Furthermore, the CLUT memory is
clocked by the pixel clock signal. Therefore, the maximum data rate for reads/write from/to the CLUT
depends on the programmed clock frequency of the Pixel Engine. Likewise, if the CLUT is in clock
throttling mode or has no clock (e.g. not connected to the pipeline), accesses to the memory are not
possible.
If (for some reason) an access to the memory lasts longer than 256 HCLK cycles, the access will
be terminated by the hardware and a read will deliver undefined data (but an error response from
the register bus will not be delivered!).
The CLUT must be initialized by the application software during the initialization phase because the
CLUT does not have default values.
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Pixel Engine (PIX) Matrix
Revised 24/7/13
Chapter 8: Pixel Engine (PIX) Matrix
A color matrix unit (referred to simply as ‘matrix’ in this document) can be used to perform linear
color correction or conversions in the pixel processing pipeline. For example, a color conversion process could perform YUV to RGB color conversion. A matrix is fully programmable (coefficients for
the matrix and offset) and has a 3x3 matrix size (plus an offset) and operates in one of three modes:
8.1

Neutral mode: The matrix output is the same as the input, without any modifications

Matrix mode: The incoming RGB value is color-converted using the matrix

Pre multiplication mode: The incoming RGB color value is pre-multiplied with the incoming
alpha value
Matrix Block Diagram
Figure 8-21: Matrix Block Diagram
8.2
Neutral Mode Operation
In this mode both the color and alpha values are transferred to the output without modifications.
8.3
Matrix Mode Operation
When the matrix is active and in matrix mode, the processing matrices used are as shown below.
Every input color is multiplied with the matrix coefficient. The results are summed up and the sum
is rounded to the next 8bit value, checked for overflow, underflow and finally sent to the output.
The alpha value is bypassed without modifications.
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8.4
Pixel Engine (PIX) Matrix
Pre multiplication Mode Operation
When the matrix is active and in pre multiplication mode, the color value of the incoming pixel is multiplied with the alpha values.
First the incoming alpha value which is in the range 0..255 is extended to the range 0..256 by adding
the msb (bit[7]) of the alpha value to the alpha value. This new alpha value is than multiplied with
the color value.
As with matrix mode, the result is rounded to the next 8bit value, checked for overflow, underflow
and sent to the output.
The alpha value is bypassed without modification.
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Pixel Engine (PIX) ROP
Revised 24/7/13
Chapter 9: Pixel Engine (PIX) ROP
A Raster Operations unit (ROP) is connected to the Pixel Engine interconnect bus by three inputs
(primary, secondary and tertiary/auxiliary) and one output. It executes logical raster operations between its inputs and transmits the result to its output.
Pixel Pipelines from PixEng
Interconnect
Register Interface
to Config Unit
Primary input
Secondary input
Tertiary input
ROP Unit
Interrupt
Pixel Pipeline to PixEng
Interconnect
Figure 9-22: Raster Operations Unit
The ROP units contain shadow registers for all operation related configurations. The Pixel Engine
configuration determines how sub-units are interconnected and therefore implicitly, which inputs are
active. Any active input can submit a ‘shadow load’ command, however, the ROP unit will only process input supplied by the active input with the highest index - anything else is ignored.
A ROP unit can also be operated in ‘Neutral Mode’. Regardless of the number of active inputs (one,
two or three pixels are input), the output pixel is always the primary input pixel. This is why the primary input must always be active, whenever any of the inputs are active (see below).
9.1
ROP Interrupts
A ROP unit has one interrupt output that signals the completion of a shadow load. It is one pixel_clk
wide pulse.
9.2
ROP Unit Restrictions

The primary input must be active whenever any of the inputs are active.

If an input is not active, then the raster operation indices must be configured by software so
that the input pixels have no effect on the output (i.e. are effectively ignored).

For ROP3 operations, where one source buffer is run-length (RL) encoded and uses a clip
window, the corresponding FetchRLD unit must not be connected to the secondary input of the
ROP unit, but to the tertiary input. Otherwise there is no reliable way for the software to detect
the shadow load condition (because the second input of the ROP unit doesn’t have an
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Pixel Engine (PIX) ROP
interrupt and shadow load notification mechanism on its output [store unit]). This restriction can
cause problems in a system if the software wants to reconfigure the Blit Engine depending on
this (missing) notification.
9.3
ROP Unit Processing Flow
The Raster Operation unit performs the desired raster operation on the input data and forwards the
result to its output. The ‘Operation Index’ is an 8-bit value written to each of the four color components (R,G,B and A) of the “Pixel Engine ROP Raster Operation Indices register
(GFXPIX_rop<n>_RasterOperationIndices)” to determine the raster operation processing of the (up
to) three ROP unit inputs.
Example: Operation Index = 0xFA = 1111 0101 (binary)
Intended
Output
Tertiary
Input
Secondary
Input
Primary
Input
OpIndex
0
0
0
0
OpIndex...0
1
0
0
1
OpIndex...1
0
0
1
0
OpIndex...2
1
0
1
1
OpIndex...3
1
1
0
0
OpIndex...4
1
1
0
1
OpIndex...5
1
1
1
0
OpIndex...6
1
1
1
1
OpIndex...7
(0xFA)
Assume that we wish to have the result of a logical OR operation on the tertiary and primary inputs
(i.e. the secondary input is inactive/ignored).
If we OR the tertiary input:
1111 0000
with the primary input:
0101 0101
then the result is:
1111 0101
1111 0101 = 0xFA = the Operation Index to use (and the intended output)
In this example the secondary input is disabled, so the operation index should be set up so that the
following applies:
{ OpIndex[7:6], OpIndex[3:2] } = = { OpIndex[5:4], OpIndex[1:0] } ;
Please note that the operation index can be specified differently for each color component in the
“Pixel Engine ROP Raster Operation Indices register (GFXPIX_rop<n>_RasterOperationIndices)”.
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Pixel Engine (PIX) BlitBlend Unit
Revised 24/7/13
Chapter 10: Pixel Engine (PIX) BlitBlend Unit
A BlitBlend unit is connected to the Pixel Engine pipeline with a primary and a secondary input. It
has a single output. The unit is used to execute one of several blending operations on the two input
sources.
Pixel Pipelines from PixEng
Interconnect
Register Interface
to Config Unit
Primary input
Secondary input
BlitBlend
Unit
Interrupt
Pixel Pipeline to PixEng
Interconnect
Figure 10-23: BlitBlend Unit Block Diagram
A BlitBlend unit supports both OpenVG 1.0 and OpenGL 2.0 blending modes (please check the official OpenVG and OpenGL specifications for details) with one exception: a BlitBlend unit can not
perform pre multiplication with alpha or division to undo pre multiplication with alpha. The units’ data
path is set up to work on pre multiplied color values.
NOTE The OpenGL documentation refers to the primary input as the “Source” and the secondary
input is referred to as the “Destination”.
NOTE The OpenGL BlendFunction settings will have no effect when the OpenVG BlendModes are
used.
NOTE A constant color definition can be used for blitblending.
10.1 Shadowed Configuration
A BlitBlend unit contains shadow registers for all operation related configurations. Shadow loading
is automatically performed upon receipt of a ‘shadow load’ command from its highest active input.
In addition it is possible to enable constant shadow updating via the register interface (for debugging
purposes only) and to select the controller of the shadow update.
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Pixel Engine (PIX) BlitBlend Unit
10.2 Operation Modes
A BlitBlend unit has two modes of operation:

Neutral mode: all incoming commands and pixels are routed through directly to the output.

Normal operation mode: blitblending is performed on the inputs.
10.3 BlitBlend Interrupts
A BlitBlend unit has a single interrupt output signal. It indicates that a shadow register load has been
performed.
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Pixel Engine (PIX) Layerblend
Revised 24/7/13
Chapter 11: Pixel Engine (PIX) Layerblend
A layer blending unit (Layerblend) is used to blend or merge two video layers. The Layer blending
unit operates in one of four different modes:

Neutral mode: The primary input is used for output.

Blend mode: The Primary and Secondary inputs are blended according to the programmed
blending functions.

Primary transparency mode: The transparency color is used on the primary input.

Secondary transparency mode: The transparency color is used on the secondary input.
11.1 Features of the Layerblend Unit
The Layerblend unit has the following features:

Configurable transparent color for either the primary or secondary pixel input

Output frame geometry is defined by the primary input

Relative offset of input frames up to plus/minus max. resolution

Neutral mode

Generates interrupt signals
=
primary
ZERO
ONE
PRIM_ALPHA
ONE_MINUS_PRIM_ALPHA
SEC_ALPHA
ONE_MINUS_SEC_ALPHA
CONST_ALPHA
ONE_MINUS_CONST_ALPHA
X
primary
secondary
out
S
secondray
ZERO
ONE
PRIM_ALPHA
ONE_MINUS_PRIM_ALPHA
SEC_ALPHA
ONE_MINUS_SEC_ALPHA
CONST_ALPHA
ONE_MINUS_CONST_ALPHA
Transparency
color
OpenGL blend equation FUNC_ADD only
with blend factors ZERO, ONE, PRIM_ALPHA, ONE_MINUS_PRIM_ALPHA, SEC_ALPHA,
ONE_MINUS_SEC_ALPHA, CONST_ALPHA, ONE_MINUS_CONST_ALPHA
for RGB (source), RGB (destination), Alpha source and destination.
MODE

X
Figure 11-24: Layerblend Unit Block Diagram
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Pixel Engine (PIX) Layerblend
11.2 Layerblend Unit Functional Description
The LayerBlend unit has two inputs. A primary input, which is used as a background (and which defines the output geometry) and a secondary input (foreground) which is blended onto the frame of
the primary input. The XPOS and YPOS bitfields of the “Pixel Engine Layerblend Position register
(GFXPIX_layerblend<n>_POSITION)” define the position of the secondary input frame.
YPOS
XPOS
secondary input
primary input
Figure 11-25: Secondary layer position
The secondary input layer can also be partially or completely off-screen. In this case the entire off
-screen pixels are not used, but are read from the module input.
secondary input
primary input
secondary input
primary input
Figure 11-26: Secondary Layer Off Screen
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Pixel Engine (PIX) Layerblend
Revised 24/7/13
11.3 Blend mode
Each of the two input values (primary input and secondary input) can be multiplied with a programmable blending function. Eight different blending functions are supported for the primary and the
secondary inputs. Two different blending functions exist, one for color blending and one for alpha
blending.
The resulting blended color/alpha is defined as shown below.
Blending Function Name
Formula
ZERO
C/αblend =
0
* C/α in;
ONE
C/α blend =
1
* C/α in;
PRIM_ALPHA
C/α blend =
ONE_MINUS_PRIM_ALPHA
C/α blend = (1-αprim) * C/α in;
SEC_ALPHA
C/α blend =
ONE_MINUS_SEC_ALPHA
C/α blend = (1-αsec) * C/α in;
CONSTANT_ALPHA
C/α blend =
ONE_MINUS_CONSTANT_ALPHA
C/α blend = (1-αconst) * C/α in;
αprim * C/α in;
αsec
* C/α in;
αconst * C/α in;
If an alpha value is used for the multiplication, the range of the alpha value which is 0 ... 255 is increased to 0 ... 256 by adding the msb (bit[7]) to the original alpha value.
After the multiplication the two results are added. The final result is rounded off and clamped to the
8-bit output range.
primary
primary blend
function
X
S
secondary
secondary blend
function
X
Figure 11-27: Blending
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11.4 Primary Transparent Blending Mode
In this mode, the programmed transparency color is used for a comparison with the primary input
layer (background). The secondary layer is displayed in the overlapping area of the two layers when
the color of the primary layer matches the transparency color. The primary input is used in all other
cases.
+
secondary input
=
primary input
secondary input
primary input
Figure 11-28: Primary Transparent Mode, Transparency color = black
11.5 Secondary Transparent Blending Mode
In this mode, the programmed transparency color is used for a comparison with the secondary input
layer (foreground). The primary layer is displayed in the overlapping area of the two layers when the
color of the secondary layer matches the transparency color.
+
primary input
secondary input
=
secondary input
primary input
Figure 11-29: Secondary Transparent Mode, Transparency color = black
11.6 Neutral Mode
The primary input is routed to the output in this mode. The secondary input is fetched, but not used.
The secondary input is still used to update the shadow register. If the secondary input is disabled at
the Pixel Engine level, the layerblend module will use the primary input to update the shadow register.
11.7 Interrupt signal generation
An interrupt signal is generated when the shadow registers are updated. This interrupt can be used
by an application to detect when the next set of registers can be written.
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Pixel Engine (PIX) Store Unit
Revised 24/7/13
Chapter 12: Pixel Engine (PIX) Store Unit
A Store unit of the Pixel Engine is connected to the AXI Interconnect Bus and stores frames received
from the Pixel Engine pipeline (up to 1024 x 1024 pixels in size).
The features of a store unit also describe its possible applications:

Acts as a buffer to allow bursting over the AXI Interconnect interface (there are four buffers
with configurable sizes, also referred to as ‘managed buffers’)

Provides kick signals and generates interrupts

Rasterizer for address generation for the AXI Interface and dither unit (up to 1024 x 1024
pixels).

Color conversion unit with dithering

Provides a fast fill mode (64 bpp only)
Shadow
Registers
Register Interface to
Config Unit
Pixel Pipeline to
PixEng Interconnect
Rasterizer
Command Sync
Stage
Color
Conversion
irq[2:0]
Main
Control
kick_out
AXI Interface
AXI interface for
memory access
Figure 12-30: Store unit block diagram and functional flow
12.1 Operation of the Store Unit
A Store unit is able to provide ‘kick’ signals for fetch units (or other sources) to start operation. The
kick signal of a store unit can be triggered by software and is automatically delayed until a current
operation is executing if the store unit is not in idle mode.
12.2 Store unit Interrupt generation
The store unit is able to generate an interrupt if the ‘shadow load’ command has been received from
the pixel pipeline and has been executed. It can also generate an interrupt if the current operation
has been finished (all AXI acknowledges for writes have been received). For error detection it will
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Pixel Engine (PIX) Store Unit
also generate an interrupt if a new ‘start of frame’ command has been received from the pixel pipeline before the current operation has finished (frame is too short) or if a normal pixel is received
where the store unit expects a command word (frame too long).
12.3 Fast fill mode
A store unit can be set to 64 bits per pixel. In this mode, the store unit will first convert every pixel
from the pixel engine pipeline into a 32 bit data vector according to the “Pixel Engine Fetch Color
Component Bits register (GFXPIX_fetch<n>_ColorComponentBits)” and after that double every resulting 32 bit vector into one 64 bit vector. This is then written to the destination buffer.
12.4 Output Data Format
A store unit supports all pixel formats that are a power of two up to 64 bits or 24 bits width, with up
to 10 bits per color or 8 bits per alpha component.
NOTE The first pixel must be byte-aligned for pixel widths under 8bpp.
The following diagram shows you an example and explains the term ‘color component shift’ which
is used in to accommodate for different bit width sizes of color components (e.g. RGB565 - see below) via the “Pixel Engine Fetch Color Component Shift register
(GFXPIX_fetch<n>_ColorComponentShift)”.
Table 12-12: Output Data Format
RedBits
5
RedShift
0
GreenBits
6
GreenShift
6
BlueBits
5
BlueShift
11
Alphabits
0
AlphaShift
0
Total bits
16
Of course, every color component color shift plus the color bits value itself must be smaller than the
total number of bits per color (total bits). For 64 bit output pixels, the pixel engine pixel will be converted to a 32 bit pixel and then doubled.
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12.5 Store Unit Processing
When a store unit receives a software kick signal, its main control logic simply outputs the kick signal
to the Pixel Engine. This will eventually cause the fetch unit to send a ‘start of frame’ command word,
followed by pixels down the pipeline. When the command word has been received, it will be decoded
to get the width and height and (if specified) a shadow register load will be performed if required.
Next, the rasterizer will start generating the addresses and offsets (for dithering) for the incoming
pixels. Please note, that the rasterizer is pipelined and needs a few clock cycles to generate the first
address (the pixel pipeline will be stalled during this time). Afterwards the pixels will be converted
by the color conversion unit and the resulting data will be written to memory via the AXI interface.
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Pixel Engine (PIX) Store Unit
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Pixel Engine (PIX) Extdst
Revised 24/7/13
Chapter 13: Pixel Engine (PIX) Extdst
The external destination unit is an output interface of the Pixel Engine for an ARGB pixel steam with
a valid, busy handshake. This unit (extdst) can be used to connect a display controller to the Pixel
Engine and also generates the kick signal for one Pixel Engine pipeline.
13.1 Extdst Block Diagram
Figure 13-31: Extdst unit Block Diagram
13.2 Kick Signal Generation
The Extdst unit can generate kick signals for the Pixel Engine pipeline. This is done by writing to the
KICK register bitfield of the Pixel Engine ExtDst Control register (GFXPIX_extdst0_CONTROL). The
values that can be configured in the KICK_MODE bitfield are explained here.
OFF
Kick signals are not generated.
CONTINUOUS_NON_OVERLAP
The next kick signal will be generated after reception of the last pixel of the current frame.
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Pixel Engine (PIX) Extdst
valid pixel
kick
empty
running
empty
status
empty
SW enable
running
running
= frame control word
Figure 13-32: Continuous non overlapping kick
CONTINUOUS_OVERLAP
The next kick signal will be generated after recpetion of the control word of the current frame.
valid pixel
kick
SW enable
status
empty
running
running_retriggered
running
running_retriggered
running
running_retriggered
= frame control word
EXTERNAL
The rising edge of this external kick signal is detected and produces a kick pulse.
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13.3 Interrupt signal generation
The extdst module has several interrupt sources. Each interrupt source can be individually enabled
or disabled in the central interrupt controller.
Status interrupts

IRQ0: control word received
Used to detect the beginning of a frame.

IRQ1: control word with shadow update received
This interrupt can be used by the software to detect when the next set of registers can be
written.

IRQ2: finished interrupt
This interrupt signals when the pipeline is empty. This can be used by the software to detect
when a reconfiguration of the pipeline can be done safely.
Error interrupts
The extdst unit can detect several operation errors for debugging purposes. An interrupt can be generated if one of the following errors is detected (IRQ3). Status flags shows which error was detected.

external kick error
When an external kick signal is detected and the unit is in the “running_retriggered” status this
error flag will be set.

software kick error
When a software kick signal is detected and the unit is in the “running_retriggered” status this
error flag will be set.

count error
When a control word is received and the current pixel count do not match with the expected
pixel count this error flag will be set. This error flag is also set, when the current pixel count is
larger than the expected pixel count, without receiving a control word.
Please also refer to the “Pixel Engine ExtDst Status register (GFXPIX_extdst0_STATUS)” for information on monitoring the extdst unit.
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Pixel Engine (PIX) Extdst
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Display Controller (DISP)
Revised 24/7/13
Chapter 14: Display Controller (DISP)
14.1 Display Controller Overview
The Display Controller module generates all the required control signals for operating a display in
RGB mode using HSYNC and VSYNC as timing references. The pixel data provided by the Pixel
Engine is read by the Display Controller using a FIFO interface. The FIFO interface represents the
clock domain crossing border between the pixel clock domain and the display clock domain. The
pixel data that is received is output with respect to the programmed display timing, which is generated by the Timing Generator. If a display with a relatively low color resolution is used for the application, the visual impression can be improved by enabling the dithering unit which is in the pixel path
of the Display Controller.
Interrupts
Pixel Clock
Timing Generator
RGB
pixeng_clk
RDEN
RGB
Dithering
Unit
FIFO
to TCON
Pixel Clock
HS/VS/DE/CSYNC
CDC
from Pixel Engine
Kick (to PixEng)
Control
Signals
Control Register
AHB Bus
to Signature Unit
Figure 14-33: Display Controller Overview
14.1.1 Timing Generator
The Timing Generator creates all synchronization signals required by the Display Engine. The Timing Generator therefore generates the HSYNC, VSYNC, CSYNC and DE signals for the output RGB
interface. Furthermore the Timing Generator supplies the RDEN signal which controls pixel data
reads from the FIFO block. A synchronization signal (kick signal) is provided to the Pixel Engine for
every frame. This synchronisation signal starts the operation of the Pixel Engine for the next frame
to be displayed. The exact time when this synchronization signal is generated can be programmed
and is related to the base timing of the pixel counter and the line counter. In addition, the Timing
Generator generates the interrupt pulses whereby the position of the interrupt events is programmable in the same manner. The following diagram illustrates the frame timings provided by the Timing Generator.
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Display Controller (DISP)
HTP
HSP
HSW
VDP
VSP
VSW
VTR
HDP
Figure 14-34: Timing Generator Frame Timing Signals
Table 14-13: Frame Timing Signals
Parameter
Meaning
HTP
Horizontal Total Pixels
HSP
Horizontal Synchronization Pulse
HSW
Horizontal Synchronization Width
HDP
Horizontal Display period (active display area)
VTR
Vertical Total Resolution (lines)
VSP
Vertical Synchronization Pulse Position
VSW
Vertical Synchronization Pulse Width
VDP
Vertical Display Period (active display area)
The relationship of the parameters must adhere to the following rules:
4 ≤ HDP ≤ HSP < HSP + HSW ≤ HTP; HSW ≥ 1
4 ≤ VDP ≤ VSP < VSP + VSW ≤ VTR; VSW ≥ 1
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The table below shows example setups for typical display resolutions. The maximum display resolution supported is VGA 640x480 with a frame repetition rate of 60Hz.
Table 14-14: Typical display timings
Resolution
Division Rate
(assumed
clock is 400
MHz)
Pixel
Frequency
HDP
VDP
HTP
Horizontal
Frequency
VTR
Vertical
Frequency
320 x 240
1/63
6.35 MHz
320
240
424
15.75 MHz
263
59.90 Hz
400 x 240
1/47
8.51 MHz
400
240
530
15.82 MHz
263
60.15 Hz
480 x 240
1/40
10.0 MHz
480
240
636
15.67 MHz
263
59.60 Hz
640 x 480
1/16
25.0 MHz
640
480
800
31.25 MHz
525
59.52 Hz
14.1.2 Clock Domains and Concept
The Display Controller is clocked by the Pixel Clock whose frequency depends on the resolution and
frame rate of the display panel in use. A programmable clock divider in the Global Control unit is
used to generate the required pixel clock frequency (see “Clock Adjust register
(GFXGCTR_ClockAdjust)”). The pixel clock also drives the Pixel Engine (write side) FIFO interface.
14.1.3 FIFO and FIFO Control
WR_DATA
RD_DATA
32
WREN
FULL
PIXCLK
CDC
SYSCLK
Pixel data from the Pixel Engine is supplied to the Display Controller through an asynchronous FIFO
which serves to compensate delays between the two modules and effectively forms the clock domain crossing between the system clock and the pixel clock.
32
Async
FIFO
RDEN
EMPTY
Figure 14-35: FIFO data flow and Control
The picture above shows the connections of the FIFO interface. On the write side the pixel data is
connected by the 32bit wide WR_DATA bus. Each component of the RGB pixel is connected with
a resolution of 10 bits. The remaining two bits are used for control word indication and alpha indication. Alpha values are fed to the signature unit (SIG). WREN indicates a write request. FULL indicates that the FIFO is full. On the read side, the pixel data is read on the bus RD_DATA. The signal
RDEN indicates a read request; EMPTY indicates that the FIFO is empty.
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Display Controller (DISP)
The Pixel Engine sends 32 bit wide write data words to the Display Controller. It contains 3x10 bit
wide pixel data (RGB), one bit for alpha indication and one bit indicating that the data word has to
be interpreted as a control word.
14.1.4 Dither Unit
The Dither Unit is used in the display processing pipeline in order to improve the visual impression
of images displayed on a panel which has less color levels (bpc) than those contained in the original
picture data (e.g. original has 8 bits per color [bpc], whereas the panel has only 6 bpc). To achieve
this improvement, the dither unit modifies pixels so that the average color level of these pixels is
attained. The dither unit supports three operation modes:

Bypass mode
In bypass mode, the input data will be passed through to the output, dropping the 2 LSB of the
input data.

Spatial dithering mode
In spatial dithering mode, the intensities of neighboring pixels are modified so that their
combined intensities average out to the desired value. Using a 4x4 matrix (see table below),
the incoming pixel value will be filtered depending on the location of the pixel in a frame. The
pixel location is generated according to the horizontal and vertical synchronization signals.
Table 14-15: Ordered Dithering Matrix (4x4)

0
8
2
10
12
4
14
6
3
11
1
9
15
7
13
5
Temporal dithering mode
By alternating each pixel's color value rapidly between two approximate colors in the panel's
color space, a display panel which natively supports 6 bpc color can represent an 8 bpc image.
14.1.5 Display Controller Generated Interrupts
The display engine can issue three different interrupts on arbitrary positions of the generated frame
raster, both in the active area and in the blanking area. The coordinates of the interrupt triggers can
be programmed using the Trigger Point Coordinates for INT<n> register (GFXDISP_INT<n>Trigger) whereby <n> is 0, 1 or 2. An additional interrupt is provided to signal a ‘FIFO empty’ condition.
Furthermore the ‘interr’ interrupt is issued if a mismatch is detected between the programmed frame
size of the Display Controller and the number of pixels sent by the Pixel Engine.
14.1.6 Pixel Engine Synchronization
The Display Controller is able to send an internal synchronization signal (Pixel Engine kick signal)
to start Pixel Engine processing. When it is enabled (see “Pixel Engine Trigger Point register
(GFXDISP_PixEngTrig)”, the synchronization signal is generated at the programmed coordinates
(PESROW is the line number and PESCOL is the row number - both can lie within the active and
the blanking area of the frame), once per frame, for one pixel engine clock cycle.
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In order to program the Display Controller, it must be disabled first (DEN = 0), and then the trigger
coordinates for the kick signal PESROW and PESCOL must be programmed. Finally the Display
Controller can be enabled again (DEN = 1).
Start
Disable Display
Controller (DEN=0)
Write PESROW
Write PESCOL
Enable Display
Controller (DEN=1)
End
Figure 14-36: Control flow for programming the Pixel Engine kick signal
14.1.7 Signature Error Handling in the Display Controller
If a signature error is detected, the Display Controller issues black pixels for the duration of the time
in which the signature error flag is active. This is done to avoid the display of invalid (bad signature)
data. Note that the display synchronization signals remain unaffected by this behavior.
14.1.8 Display Controller Output Signal Timing
Basically the display panel interface signals comprise of DCLK, VSYNC, HSYNC, DE and RGB data. Some display panels also require a CSYNC (Composite SYNC) signal which is provided as well.
The figure below shows the timing relationship between the listed signals (accept CSYNC). All the
parameters (HDP, HSP, HTP, etc) can be programmed by software. The RGB data is output only
when DE is active – otherwise 0x00 is output on each color channel. In the example below DE is a
high-active signal and HSYNC and VSYNC are low-active signals.
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Display Controller (DISP)
DCLK
HDP
DE
HSP-HDP
RGB
0x0
D0
D1
...
...
Dn
0x0
Dn+1
Dn+2
...
...
Dk
0x0
HTP
HSW
HSYNC
VSYNC
Figure 14-37: Display Controller Output Signal Timing
Display Controller Interrupt Programming
The Display Controller has three interrupts (INT0, INT1 and INT2) which are programmable to arbitrary positions within the frame timing (both in the active and the blanking areas). These interrupts
are controlled by the Trigger Point registers (see GFXDISP_INT0Trigger, GFXDISP_INT1Trigger
and GFXDISP_INT2Trigger).
INTxROW
INTxCOL
Active Area
Interrupt
triggered
Blanking Area
Figure 14-38: Display Controller Interrupt Trigger Location definition
Special care must be taken when programming or reprogramming the trigger coordinates of the programmable interrupts. The flow chart below describes the sequence of necessary steps when
(re-)programming the interrupts. First the Display Controller must be disabled. The bit of the
GFXGCTR_IntEnable<n> register in the Interrupt Controller (Global Control) must be disabled and
the respective status register must be cleared by writing the GFXGCTR_IntClear<n> register in the
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Interrupt Controller (Global Control). The coordinates for triggering the respective interrupt signal of
the Display Controller (Int<n>Row, Int<n>Column whereby <n> = 0|1|2) must be written, after which
the respective enable signal INT<n>EN of this interrupt is switched on. Finally the Display Controller
(Global Control) is enabled again.
Write INTxROW
Write INTxCOL
Start
Enable Interrupt
(INTxEN=1)
Disable Display
Controller (DEN=0)
Write 0 to bit position
in IntEnable register in
Interrupt Controller
Write 1 to bit position
in IntEnable register in
Interrupt Controller
Enable Display
Controller (DEN=1)
Write 1 to bit position
in IntClear register in
Interrupt Controller
End
Figure 14-39: Display Controller Interrupt programming flow
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Timing Controller (TCON)
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Chapter 15: Timing Controller (TCON)
The Timing Controller module (TCON) is used to generate control and data signals to directly interface to the column and row drivers of a display panel. The freely programmable waveform of the
generated timing control signals allows the emulation of almost every timing controller IC (TCON IC)
commonly used in display panels. The pixel source RGB data can be transmitted either as single-ended TTL signals or as low voltage differential swing signals conforming to the RSDS™ standard (Reduced Swing Differential Signal).
The TCON module consists of three submodules; a Timing Signal Generator (TSIG) module, an RSDS™ bit mapping module (RBM) and an IO module for control of special RSDS™ or TTL capable
IO-cells.
CFG-BUS
CFG
TSIG
Data
PixelSource
RGB
TCON
LastColumn/Row
IOcells
Column-driver
Row-driver
FrameGenerator
DISP
Panel
Figure 15-40: Timing Controller (TCON) Overview
15.1 Features of the Timing Controller Module
RBM unit (RSDS Bit Mapping)

Conforms to the RSDS™ Standard 1.0 (from National Semiconductors, RSDS™ “Intra-Panel”
Interface Specification, Revision 1.0, May 2003)

Support for single bus (multidrop bus with single or double end termination)

Mapping for 6 bit color depth

Mapping for 8 bit color depth

Data and clock outputs can be flexibly assigned to the pool of available pins to ease board
design
TSIG (Timing Signal Generator)

Freely programmable waveforms

12 pulse generators (SPGs)

1 signal sequencer with max. 64 signal transitions

12 signal mixers with a programmable function table

Inversion control signal for transition minimizing (useful for TTL applications)
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Timing Controller (TCON)
I/O module

Controls combined TTL / RSDS I/O cells (used for RGB data and clock output)

Max. number of differential pins:
24 x data (12 diff. pairs)
2 x clock (1 diff. pair)

Programmable output clock phase shift 0 ... 360°

Adjustable drive current (2mA/4mA)
15.2 The Pixel Data Interface
The pixel data contains both active and blanking pixel data. The following timing diagram shows an
example video frame.
PixelClock
Last_column
PixelData RGB
P0
P1
P (nx-1)
P (nx)
P (nx+1)
P (N)
P (0,nextframe)
Figure 15-41: Video Frame
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Timing Controller (TCON)
Revised 24/7/13
15.3 TCON Processing Flow and Operation Modes
15.3.1 TCON Operation Modes
TC O N
IO s
D ata
RGB
data
“R G B S rc”
RBM
RGB
data
IN V
C TR
RSDS
/
TTL
D ata
IO control
PixelC lock
BitC lock
C lock
C ontrol
“Fram eG en”
TS IG
TTL
Figure 15-42: Timing Controller (TCON) Internal Structure
The TCON is operated in bypass or active mode (configured using the BYPASS bit in the RBM control register - see “RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL)”.

Bypass Mode:
In bypass mode, the RGB data from the RGB source is passed through the RBM submodule
unchanged. The additional timing signals (HSYNC, VSYNC, DE) from the frame generator are
sent to the TSIG output signals TSIG[0:2]. The RGB data and the timing signals have the
same latency.

Active Mode:
In active mode, the RGB data from the RGB source is passed through the RBM submodule
and changed before being output as either TTL or RSDS compliant signals.
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15.3.2 Resetting the TCON
The TCON is reset (synchronizing all internal states) by software using the reset register (see “Timing Controller Software Reset register (GFXTCON_DIR_SWreset)”). After a power on reset, the
TCON remains in the ‘software reset active’ state until de-asserted by internal logic, in sync with internal video synchronization signals, i.e. the last pixel of a video frame, including blanking signals.
For this reason, it is important (after configuring the TCON module) that the display controller sends
a valid video frame (HTP, VTR, HDP, VDP) to the TCON module. Otherwise RGB data and display
clock data will not be output.
Please note that the configuration registers of the TCON module are not effected by a software reset, only the internal states are reset.
15.3.3 RSDS Bitmap Module (RBM)
The RBM module essentially takes incoming RGB data, processes it (e.g. bit ordering) and outputs
the data mapped to RSDS/TTL channels.
Figure 15-43: RBM Module Functional Overview
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The following tables show the mapping of the RGB data to the respective RSDS/TTL channels.
Table 15-16: RSDS Bitmapping (8bpc)
RSDS 8bpc
Rising Edge
Falling Edge
Ch0
R0
R1
Ch1
R2
R3
Ch2
R4
R5
Ch3
R6
R7
Ch4
G0
G1
Ch5
G2
G3
Ch6
G4
G5
Ch7
G6
G7
Ch8
B0
B1
Ch9
B2
B3
Ch10
B4
B5
Ch11
B6
B7
Table 15-17: RSDS Bitmapping (6bpc)
RSDS 6bpc
Rising Edge
Falling Edge
Ch0
R2
R3
Ch1
R4
R5
Ch2
R6
R7
Ch3
G2
G3
Ch4
G4
G5
Ch5
G6
G7
Ch6
B2
B3
Ch7
B4
B5
Ch8
B6
B7
Ch9
0
0
Ch10
0
0
Ch11
0
0
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Timing Controller (TCON)
Table 15-18: TTL Bitmapping (8bpc)
15 - 6
TTL 8bpc
Rising Edge
Falling Edge
Ch0
R0
R0
Ch1
R1
R1
Ch2
R2
R2
Ch3
R3
R3
Ch4
R4
R4
Ch5
R5
R5
Ch6
R6
R6
Ch7
R7
R7
Ch8
G0
G0
Ch9
G1
G1
Ch10
G2
G2
Ch11
G3
G3
Ch12
G4
G4
Ch13
G5
G5
Ch14
G6
G6
Ch15
G7
G7
Ch16
B0
B0
Ch17
B1
B1
Ch18
B2
B2
Ch19
B3
B3
Ch20
B4
B4
Ch21
B5
B5
Ch22
B6
B6
Ch23
B7
B7
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Table 15-19: TTL Bitmapping (6bpc)
TTL 8bpc
Rising Edge
Falling Edge
Ch0
R2
R2
Ch1
R3
R3
Ch2
R4
R4
Ch3
R5
R5
Ch4
R6
R6
Ch5
R7
R7
Ch6
G2
G2
Ch7
G3
G3
Ch8
G4
G4
Ch9
G5
G5
Ch10
G6
G6
Ch11
G7
G7
Ch12
B2
B2
Ch13
B3
B3
Ch14
B4
B4
Ch15
B5
B5
Ch16
B6
B6
Ch17
B7
B7
Ch18
0
0
Ch19
0
0
Ch20
0
0
Ch21
0
0
Ch22
0
0
Ch23
0
0
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Timing Controller (TCON)
15.3.4 Inverting the RSDS channel order
The following register settings must be made in order to achieve RSDS channel order inversion per
color:
“RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL)”.BitOrder = 1
“RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL)”. Swapoddevenbit = 1
“RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL)”.IfcType = 01
This results in the following mappings.
Table 15-20: RSDS Bitmapping (8bpc) inverted
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RSDS 8bpc
Rising Edge
Falling Edge
Ch0
R6
R7
Ch1
R4
R5
Ch2
R2
R3
Ch3
R0
R1
Ch4
G6
G7
Ch5
G4
G5
Ch6
G2
G3
Ch7
G0
G1
Ch8
B6
B7
Ch9
B4
B5
Ch10
B2
B3
Ch11
B0
B1
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Timing Controller (TCON)
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Table 15-21: RSDS Bitmapping (6bpc) inverted
RSDS 6bpc
Rising Edge
Falling Edge
Ch0
R6
R7
Ch1
R4
R5
Ch2
R2
R3
Ch3
G6
G7
Ch4
G4
G5
Ch5
G2
G3
Ch6
B6
B7
Ch7
B4
B5
Ch8
B2
B3
Ch9
0
0
Ch10
0
0
Ch11
0
0
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Timing Controller (TCON)
15.3.5 TCON Timing Signal Generators (TSIG)
Sync signals are generated using a three-stage approach in order to achieve maximum flexibility.
In the first stage, signals are generated which carry positional timing information. Two methods are
used to create these signals, ‘Position Matching’ and ‘Sequence Matching’.
The second stage combines them to form more complex waveforms.
The third stage is used to create a programmable delay of half a pixel clock cycle.
TSIG
Stage 1
X coordinate
Y coordinate
Field flag
SPG 0
Stage 2
Stage 3
SM 0
Delay 0
SM 5
Delay 5
TSIG5
SM 6
Delay 6
TSIG6
SM 11
Delay
11
8
SPG 5
TSIG0
8
SynSeq
Const0
8
SPG 6
SPG 11
TSIG11
24
RGB
RGB
INV
control
INV(TSIG12)
SPG x = Sync Pulse Generator x
SM x = Sync Multiplexer x
Figure 15-44: TSIG Block Diagram
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Timing Controller (TCON)
Revised 24/7/13
15.3.5.1 Position Matching Method (First Stage Signal Forming)
One way to form the first stage signals is to use simple position matching to trigger an RS flip-flop
or a toggle flip-flop. This is done using an array of twelve identical Sync Pulse Generators (SPG’s).
The following diagram shows the working principle. Note that for progressive-only systems the ‘F’
bit (the odd-even frame flag) must always be set to ‘0’.
Figure 15-45: Position Matching Method
The coordinate space is generated by the display controller module (DISP). Therefore the allowed
range is:
0 ≤ X ≤ HTP (horizontal total pixels)
0 ≤ Y ≤ VTR (vertical total resolution)
TOGGLE_MODE = OFF:
The output of a sync pulse generator is set or reset if the current position equals the respective programmable position in all bits for which its don’t-care-vector (which is also programmable) contains
zeros. The Off matching is dominant, i.e. when both On and Off positions are matched at the same
time, the output of the sync pulse generator is reset.
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TOGGLE_MODE = ON:
The output of a sync pulse generator toggles if the current position equals the respective programmable position in all bits for which its don’t-care-vector (which is also programmable) contains zeros.
Toggle mode allows e.g. frame wise toggling signals. Set/Reset overrides toggle, and if both positions match and toggle, they cancel each other out.
15.3.5.2 Sequence Matching Method (First Stage Signal Forming)
A more sophisticated and powerful approach to creating first-stage signals is the use of a sequencer
RAM to match a whole sequence of positions. The following diagram shows the principle of operation. A sync sequencer (SyncSeq) follows an arbitrary sequence of timing positions and generates
an appropriate output signal. The length of the sequence as well as the contents of the RAM, consisting of the position and the assigned output value are programmable.
Figure 15-46: Sequencer Matching Method
Operation is as follows. To start, the address counter is reset to zero and the RAM outputs the first
position that matches and the output value for this position. If the comparator signals match, the
RAM address is incremented, the preset output value (bit 31) is propagated and the RAM then outputs the next position to match.
This match/address increment cycle continues until the programmed sequence length is reached.
If the last position is matched, the address counter is reset to zero again and the cycle starts again.
It is thus possible to generate arbitrarily complex waveforms with up to 64 edges (which is the maximum sequence length).
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Timing Controller (TCON)
Revised 24/7/13
15.3.5.3 Combining First Stage Sync Signals
As shown above, there are twelve sync pulse generator outputs and one sync sequencer output. To
create more complex waveforms, these signals can be combined in a second stage. Here, an array
of twelve sync mixers (SMx) is used to calculate Boolean functions of first-stage signals. Each sync
mixer can form any Boolean function on up to five inputs. The basic structure of one such mixer is
depicted in the following diagram.
Figure 15-47: Basic structure of a Sync Mixer
Basic structure of a Sync Mixer: Each of the five address lines of the 32 to 1 multiplexer can be individually selected from any of the first stage signals. The output is the result of a table look-up. The
individual function table registers (see “Sync Mixer [0...11] Function Table Selection register
(GFXTCON_DIR_SMx[0...11]FctTable)” contain the respective truth table of the Boolean function
calculated.
The concept of the sync mixers needs some explanation. In the first step a selection is made of the
signals to be combined. These are referred to then as SMX[0...11]SIGS_S[0 ... 4] or simply ‘S0…S4’
and form the address for the function table. This function table is used to look up the result of the
Boolean operation the five selected signals shall be subjected to.
An example may help understand the topic. Assuming the outputs of three Sync Pulse Generators
form a combined signal with a function, one would proceed as follows.
First, the Sync Mixer signals S0…S4 are assigned either to the Sync Pulse Generator outputs or to
constant zero by programming the respective multiplexers. The next step is to build the function’s
truth table, as shown below. As the intended function has only three inputs, only eight entries need
to be specified.
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Timing Controller (TCON)
Table 15-22: Function table for the Sync Mixer Example
Selected First Stage Signals
Desired Output
S4 =
Const 0
S3 =
Const 0
S2 = SPG1
S1 = SPG0
S0 = Sync
Seq’cer
SMX = f(S0 ... S4)
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
The combinations [S4 ... S0] = 10000 ... 11111 can never occur
because S4 and S3 are ‘wired to’ constant zero
Need not be
specified
It is recommended that S4…S0 are listed in the order of binary number representation. This makes
it possible to use the function result row directly as the register contents for the Sync Mixer function
table, i.e. the last row is interpreted as a binary 32 bit number with the LSB in the first row and the
MSB in the last. For the example this would be [xxxx xxxx xxxx xxxx xxxx xxxx 0000 1000] binary,
with x’s denoting arbitrarily set or reset bits, since these will never be read out of the function table.
15.3.5.4 Sync Signal Delay Adjustment
Before the outputs of the twelve Sync Mixers are routed to real device pins, they are fed through a
programmable delay stage. This means that the signals can either pass unmodified or they can be
delayed by half a pixel clock cycle. This delay can be individually set for each of the twelve Sync
Mixer output signals via the Sync Switch register (see “Sync Switch register
(GFXTCON_DIR_SSwitch)”).
15.3.5.5 Clock Delay Adjustment
The pix_x2_del_clk signal (see Global Control Block Diagram) is used for the output clock of the
Timing Controller. This clock is generated in the Iris-SD Global Control Unit. The phase adjustment
of this clock can be programmed within a broad range. This allows a flexible adjustment of the setup
and hold timing for the data and control signals of the Timing Controller.
15.3.5.6 Inversion Signal Generation
The purpose of the inversion signal (see “Sync Switch register (GFXTCON_DIR_SSwitch)”) is the
minimization of the total number of signal edge transitions on the RGB data bus. This improves EMI
performance, especially for TTL RGB signals.
The inversion signal is transmitted as an accompanying signal to the output RGB data signals.
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Timing Controller (TCON)
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How it works: the input data of time (n - 1) is compared to the data at time n. If more than the half of
the active RGB bits have a transition from low to high or vice versa, then the inversion functionality
toggles between HIGH and LOW.
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Timing Controller (TCON)
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Signature Unit (SIG)
Revised 24/7/13
Chapter 16: Signature Unit (SIG)
The Signature Generator unit (SIG) can calculate different types of checksums for each input frame
of pixel stream data (RGB) within a user-defined evaluation window (i.e. its size and position can be
programmed), whereby an additional, separate masking window can be used in conjunction to exclude specific areas of the evaluation window (in effect cutting out specific separate areas of interest).
R,G,B, LastRow, LastColumn
Src
sel
Window &
masking
Function
Checksum_A
Result,
shadowed
Interrupt
Generation
Int
Checksum_B
Config
Config,
shadowed
Result
Configuration Bus IF
Figure 16-48: Signature Unit Processing Flow
After the signature generation has been configured and then triggered, a set of signatures are generated. The hardware can then evaluate the correctness of the data by comparing the generated
signatures with the reference values.
16.1 Features of the SIG unit
The SIG unit has the following features:

Generation of 2 different RGB data signatures for each color component (Signature A: CRC-32
for color values + Signature B: Sum of color values)

Individual masking of escape sequence of pixels within a frame

Programmable evaluation window position and size

Programmable evaluation window mask

Automatic monitoring using reference signature registers

Configurable generation of pulse or level interrupts

Programmable picture source

Self-restoring error counter

Key protection to stop illegal access
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Signature Unit (SIG)
16.2 Evaluation and Mask Windows
(0,0)
HDP
HS(Lastcolumn)
Active pixels
Xupper left
Eval window
Xlower right
Blanking
VS(Last_row)
HTP
Figure 16-49: Example of an evaluation window
Mask Coordinate
1: MaskHorizontalUpperLeft , MaskVerticalUpperLeft
2: MaskHorizontalLowerRight , MaskVerticalLowerRight
Mask outside
Vmask_Mode = 10b
1
2
Mask inside
Hmask_Mode = 01b
Object
Evaluation Window
Signature computed Object
Figure 16-50: Example of a masking window on the evaluation window
A system can use such signatures e.g. to determine whether the displayed image is exactly identical
(or - using threshold values - almost identical i.e. within a specified tolerance) to the original image
data submitted. This is functionality is necessary for the display of safety-critical data and contributes functionality for the requirements of safety standards (e.g. Automotive Safety Integrity Level
ASIL).
Although the Iris-SD SIG unit can handle up to four input sources, only one of the first two (0,1) are
used.
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Signature Unit (SIG)
Source0
Pixel
Revised 24/7/13
RGB
CFG-BUS
FrameGenerator LastColumn
LastRow
Source3
Pixel
SIG
INT
RGB
Interrupt
Controller
FrameGenerator LastColumn
LastRow
Figure 16-51: SIG unit overview
16.3 Signature A (CRC-32 Signature)
A CRC-32 (32-bit cyclic redundancy check) value is generated for each color component (R,G,B) of
the RGB pixel data in the evaluation window (except if the pixel excluded using the mask window
functionality). This signature is generated for every frame. The CRC-32 algorithm used to generate
the signature is the same as defined in the CRC-32-IEEE 802.3 Ethernet Standard, except that the
last step is not applied, i.e. the resulting bit sequence is not complemented. Refer to the C++ code
below for details.
The default equation (‘polynome’ below) is:
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Start value: FFFF_FFFF
long crc32::crc32_input ( short data ) {
int i ;
long temp, polynome ;
bool lsb ;
polynome = 0x04C11DB7 ;
temp = current_value ;
for ( i = 7 ; i >= 0 ; i-- ) {
lsb = data & ( 1 << i ) ;
if ( ( temp & 0x80000000 ) != lsb ) {
temp = ( temp << 1 ) ^ polynome ;
} else {
temp = temp << 1 ;
}
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Signature Unit (SIG)
}
current_value = temp ;
return temp ;
}
crc32::crc32() {
current_value = 0xFFFFFFFF ;
}
crc32::~crc32() {}
long crc32::get_value() {
return current_value ;
}
void crc32::reinit() {
current_value = 0xFFFFFFFF ;
}
16.4 Signature B (Sum of Color Values Signature)
This signature is generated from the sum of pixel color values for each color component (R, G, B)
in the evaluation window area and is calculated for every frame.
16.5 Programmable Evaluation Window (Position and Size)
The position and size (upper left and lower right coordinates) of the evaluation window are programmable. The window coordinates use the coordinate system shown in Figure 16-49:.
16.6 Automatic Monitoring and Interrupt
A set of reference signature registers allows the monitoring of the calculated signatures. An interrupt
can be generated on the detection of any difference between the calculated signature and the reference value. For signature B the difference can be threshold-filtered to limit the interrupt load on
the micro controller.
The signature unit supports two kinds of interrupt generation:
16 - 4

Pulse interrupt (default)

Level interrupt (via configuration register)
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16.7 Self-Restoring Error Counter
If one of the active signature results is different to the corresponding reference value, then a counter
is incremented. If the (programmable) error counter threshold is reached, then an interrupt will be
generated. The same counter is reset to zero if the configured number of consecutive video frames
with correct signature values is received.
16.8 Key Protection
Iris-SD’s internal key protection logic can be used for prevent illegal accesses to the SIG unit. On
‘Power On/Reset’ the Signature Unit is in Lock mode and will not accept any accesses. Therefore,
an attempt to program the SIgnature Unit without unlocking it first will generate an error response
and the target register will remain unchanged.
16.9 Control Flow Interrupts
An interrupt can be generated at both the start and the end of the signature calculation process. The
start interrupt (CfgCop) indicates that the configuration parameters (e.g. window coordinates) have
been copied from the shadow registers and are now active for the current signature calculation. This
makes it possible to load the next configuration parameters into the (shadow) registers without disturbing the current calculation. The ResVal interrupt indicates that signature calculation has completed and that the result data can be read from the result shadow registers. These interrupts help
to control the flow of signature calculations for each incoming frame with different evaluation window
coordinates.
16.10Programmable Input Picture Source Limitations
The Signature Unit input data can be selected from two different sources. The inputs are subject to
the following limitations:

The maximum resolution for picture sources and windows is 4096 x 4096

The evaluation window position must be completely inside the picture source frame.

The source selection must be configured before the evaluation window coordinates are set it
and can not be changed during operation.

Interlaced input sources are not supported and de-interlaced sources are not subject to any
special processing. This means that reference values must be calculated by a software
application implementing the correct de-interlacing algorithm for such data.
16.11Signature Unit and Iris-SD Interrupts
Iris-SD has two interrupt modes:

Pulse interrupt mode (default)

Level interrupt mode
The mode can be selected using bit 31 of the “Evaluation Windows Control and Configuration register (GFXSIG_CtrlCfgW0)”
In pulse interrupt mode, interrupts can’t be masked. The Signature Unit will always generate an interrupt if the interrupt condition occurs.
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Signature Unit (SIG)
To use the Level interrupt mode, the corresponding bit of the “Interrupt Enable register
(GFXSIG_IENW0)” must be enabled respectively.
The Signature Unit unit has an active-high, combined interrupt output signal (an “OR” combination
of the 3 internal interrupt conditions). A separate output is additionally available for each interrupt
condition.
16.12Example Pseudo Code for Signature Generation
Signature Generation on every incoming frame
General Configuration phase: (control registers are not shadowed)
Enable mask mode
Write mask window
Enable Signature types
Enable interrupts (Level interrupt. Not necessary for pulse interrupt)
Configuration phase for calculation 0
Write Window 0 coordinates and signature references
Set Triggermode to one single generation
Trigger one generation by writing ‘1’ to the trigger field of TriggerW0
Wait for interrupt or poll IStsCfgCop, IStsResVal
On IStsCfgCop
Configuration phase for calculation of object n
Write Window n coordinates
Setup single TriggerMode
Trigger one generation by writing to the trigger field
On IStsResVal (no sig_error interrupt)
The calculated signatures are identical to signature references
On IStsDiff or sig_error interrupt
Read result registers Signature A, (B)
Process results
Cyclic Signature Generation every incoming frame
CYCLIC monitoring of one window:
General Configuration phase: (control registers are not shadowed)
Enable mask mode
Write mask window coordinates
Enable Signature types
Enable interrupts (Level interrupt. Not necessary for pulse interrupt)
Configuration phase for calculation 0
Write Window 0 coordinates and signature references
Setup cyclic TriggerMode
Trigger cyclic generation by writing ‘1’ to the trigger field of
TriggerW0
Wait for interrupt or poll IStsResVal
On IStsCfgCop
Configuration phase for calculation of object n
Write Window n coordinates
Setup single TriggerMode
Trigger cyclic (or one) generation by writing to the trigger field
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On IStsResVal (no sig_error interrupt)
The calculated Signatures are identical to signature references
On IStsDiff or sig_error interrupt
Read result registers Signature A, (B)
Process results
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Signature Unit (SIG)
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Command Sequencer (CMDSEQ)
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Chapter 17: Command Sequencer (CMDSEQ)
The Command Sequencer is used for parsing command lists, for the distribution of data to the addressed blocks and for synchronization on certain events. Command lists can be provided from the
host CPU or can be fetched directly from local memory.
17.1 Features of the Command Sequencer unit
The Command Sequencer has the following features:

Operation modes: Host writes data to command buffer (direct mode) or the Command
Sequencer reads data from local address space (indirect mode)

Command buffer with configurable hysteresis and an interrupt when a high watermark / low
watermark is reached

Programmable watchdog timer, issues an interrupt when expired and has a 16-bit pre-divider
to offer a sizeable measurement window

Synchronization: waits for various system status bits and external events
17.2 Command Sequencer Process Flow
After reset the Command Sequencer operates in direct mode i.e. the host CPU is responsible for
writing command list data to the command buffer via the configuration register space.
When it detects a CALL instruction, the Command Sequencer switches to indirect mode and starts
to fetch command list data from a specified address using its external memory read interface. The
Command Sequencer will revert to direct mode if it detects a RET instruction.
Command Sequencer
AHB [email protected] MHz
Configuration
Registers
Command
Buffer
Control
Core
AXI
Read
Agent
AXI [email protected] MHz
AXI
Write
Agent
AXI [email protected] MHz
Local Data Bus
System
Status
Watchdog
Figure 17-52: Command Sequencer overview
On receipt of command lists, these are sent to the instruction decoder. This unit synchronizes with
both the system status (via the status register interface) and the extraction of included data.
Data is written to the addressed unit (target) via the external memory write interface.
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Command Sequencer (CMDSEQ)
17.3 Command Sequencer Status Register
The Command Sequencer’s status input can be hooked up to to several Iris-SD system events. The
status input can therefore be used to synchronize a command stream with system states and
events, e.g. with the sync signals of the display controller.
17.4 Command Sequencer Watchdog Functionality
The Command Sequencer incorporates a watchdog timer to prevent a system hang-up.
The watchdog timer is configured and started using the WDS (Watchdog Setup - see ensuing command list) command in the command stream. If the parameters of the command are all ‘0’, then the
watchdog timer is disabled, otherwise the timing operation will be started using the specified values.
When the watchdog timer is enabled and running, an interrupt is generated if the watchdog counter
reaches zero when counting down.
The watchdog counter can be reset using the WDR (Watchdog Reset) command. This resets the
counter value (sets it back to the preset value - which is a parameter of the WDS command).
The watchdog unit incorporates a 16-bit pre-divider in order to offer extended flexibility with regard
to the size of a measurement window. At an operating frequency of 128 MHz, the counter granularity
varies between 7.81 ns and 512 µs. Therefore the overall measurement window is between 7.81 ns
and 38,17 h.
The watchdog pre-divider and counter registers are both implemented as down-counters with a preset (load) value. Otherwise it could happen that the counter has already passed the maximum value
when changing the configuration values.
CLK
predivider
0
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
count_p
counter
N
N-1
N-2
N-3
Figure 17-53: Command Sequencer Watchdog Counters
17.5 Command Sequencer Command Buffer
The Command Sequencer buffer is a FIFO that is used to hold commands and data when the Command Sequencer is operating in indirect mode.
The buffer can be located at any address of external memory space, whereby its location and size
must be specified in the “Command Sequencer Buffer Address register (GFXCMD_BufferAddress)”
and the “Command Sequencer Buffer Size register (GFXCMD_BufferSize)” within configuration
register space.
The command buffer itself is accessible at any address within the specified HIF address range of
the HIF register. The number of entries available can be read from the FIFOSpace field of the “Error
Monitor Status register (GFXAIC_Status)”.
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Command Sequencer (CMDSEQ)
Revised 24/7/13
Important Note about FIFO overflow
Before writing data to the FIFO, the host should first check that enough space is available by reading
the FIFOSpace bitfield of the GFXAIC_Status register or by using the high and low watermark interrupt mechanism. A FIFO high watermark interrupt (fifohwm_o) will be generated when the fill counter reaches the HighWM value and a FIFO low watermark interrupt (fifolwm_o) will be generated if
the fill counter reaches the LowWM value afterwards.
The HighWM value must be greater than the LowWM value.
The command buffer can be cleared by writing a ‘1’ to the Clear bit in the “Command Sequencer
Control register (GFXCMD_Control)”. This can also be used in an unexpected situation to restore
the Command Sequencer to a proper state in order to be able to start with the next command list.
Changing the command buffer address and size is only permitted when the buffer is empty and
when the Iris-SD 3D graphics core is in idle state. It is recommended that an application executes
a Clear afterwards to reset the read and write pointers to ‘0’.
17.6 Command Sequencer Instruction Set
This section describes the instructions that can be used in conjunction with the Command Sequencer. The instruction words components marked with ‘x’ below are not decoded. However, they should
be written as ‘0’ to avoid any unexpected behavior.
Undefined Instructions
If an undefined instruction code is detected, the Command Sequencer stops operation and indicates
the condition by setting an error_o status signal.
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Command Sequencer (CMDSEQ)
17.6.0.1 NOP - No Operation
This instruction performs ‘No Operation’ cycles. The number of delay cycles can be specified by the
operand.
Operation:
for (cnt = c24; cnt > 0; cnt = cnt – 1)
wait
Syntax:
NOP c24
Operands:
0 <= c24 < 16M
Opcode:
31
24
0 0 0 0 0 0 X X
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16
8
0
c24
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Command Sequencer (CMDSEQ)
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17.6.0.2 CALL - Call to a command list
Calls to a command list within the entire address space. The instruction switches the interpreter from
direct mode to indirect mode. Note that if the Command Sequencer is already in indirect mode, the
behavior of this instruction (and the following ones) is unpredictable!
Operation:
PC < addr
Mode < indirect mode
Syntax:
CALL addr
Operands:
0 <= addr < 4G
Opcode:
31
24
16
8
0
0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X
addr
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0 0
17 - 5
Revised 24/7/13
Command Sequencer (CMDSEQ)
17.6.0.3 RET - Return from command list
Returns from indirect mode and switches back to direct mode.
Operation:
Mode < direct mode
Syntax:
RET
Operands:
None
Opcode:
31
24
16
8
0
0 0 0 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X
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Command Sequencer (CMDSEQ)
Revised 24/7/13
17.6.0.4 WRITE - Write data to buffer
Write a list of data to a destination buffer. The destination buffer can either be specified using a fixed
(f = 1) pointer or an incremental (f = 0) address pointer.
Operation:
for (idx = 1, cnt = c24; cnt > 0; cnt = cnt - 1)
(dst) < data[idx++]
if (fixed == 0)
dst++
Syntax:
WRITE c24, dst, data, …
Operands:
1 <= c24 < 16M
0 <= dst < 4G
fixed = [0, 1]
data …
Opcode:
31
24
16
0 0 0 1 0 1 fix X
8
0
c24
dst
0 0
data[1]
.. .
data[c24]
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Command Sequencer (CMDSEQ)
17.6.0.5 COPY - Copy buffer
Copies data from a source buffer to destination buffer. The destination buffer address can either be
specified using a fixed (f =1) or incremental (f = 0) address pointer.
Operation:
for (cnt = c24; cnt > 0; cnt = cnt - 1)
(dst) < (src++)
if (f == 0)
dst++
Syntax:
COPY c24, src, dst
Operands:
1 <= c24 < 16M
0 <= dst < 4G
fixed = [0, 1]
0 <= src < 4G
Opcode:
31
24
16
0 0 0 0 1 0 fix X
17 - 8
8
0
c24
src
0 0
dst
0 0
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Command Sequencer (CMDSEQ)
Revised 24/7/13
17.6.0.6 SAVE - Save register values
This instruction saves register values to a destination buffer. The number of registers and the source
address are stored as well.
Operation:
(dst++) < c24
(dst++) < src
for (cnt = c24; cnt > 0; cnt = cnt - 1)
(dst++) < (src++)
Syntax:
SAVE c24, src, dst
Operands:
1 <= c24 < 16M
0 <= dst < 4G
0 <= src < 4G
Opcode:
31
24
16
0 0 0 1 1 0 X X
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8
0
c24
src
0 0
dst
0 0
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Revised 24/7/13
Command Sequencer (CMDSEQ)
17.6.0.7 RESTORE - Restore register values from memory
Restores register values from memory which have been previously stored using the SAVE command.
Operation:
cnt < (src++)
dst < (src++)
for ( ; cnt > 0; cnt = cnt - 1)
(dst++) < (src++)
Syntax:
RESTORE src
Operands:
0 <= src < 4G
Opcode:
31
24
16
8
0
0 0 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X
src
17 - 10
0 0
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Command Sequencer (CMDSEQ)
Revised 24/7/13
17.6.0.8 SYNC - Synchronize
This instruction stops processing the remaining command list until at least one of the system status/events set by the 32 bit mask parameter is detected.
Operation:
while ((SYSSTATUS ^ ~level) & mask == 0)
wait
Syntax:
SYNC level, mask
Operands:
0 <= level < 4G
0 <= mask < 4G
Opcode:
31
24
16
8
0
0 0 1 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X
level
mask
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Revised 24/7/13
Command Sequencer (CMDSEQ)
17.6.0.9 WDS - Watchdog Setup/Disable/Enable
This command configures the watchdog timer. If both the div and c28 parameters are zero, then the
watchdog time will be disabled, otherwise the timer will be started with the specified values.
Operation:
counter < c28
predivider < 2 ^ div
if (c28 == 0)
enable < 0
else
enable < 1
Syntax:
WDS div, c28
Operands:
0 <= div < 16
0 <= c28 < 256M
Opcode:
31
24
16
8
0
1 1 1 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X
div
17 - 12
c28
Fujitsu Semiconductor Europe GmbH
Command Sequencer (CMDSEQ)
Revised 24/7/13
17.6.0.10WDR - Watchdog reset
This instruction resets the watchdog timer. It must be executed within a limited time, given by the
watchdog load register and the divider value. The watchdog counter is reset to the value defined by
the div/c28 parameters of the WDS command.
Operation:
Watchdog timer restart
Syntax:
WDR
Operands:
None
Opcode:
31
24
16
8
0
1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X
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Revised 24/7/13
Command Sequencer (CMDSEQ)
17.7 Initializing the Watchdog Timer

Choose a pre divider value depending on the required measurement window.

Calculate the preset value of the watchdog counter for the maximum time period. This can be
done using this formula:
counter = Tmax * f / (2 ^ div)

To start the watchdog timer, send a WDS instruction with the calculated values.

Restart the watchdog timer by inserting a WDR command in the command stream

If the watchdog expires (WatchdogCounter = ‘0’), the watchdog_o output signal will be set to
‘1’.

The watchdog can be disabled by sending a WDS command with the div and c28 parameters
both set to ‘0’.
17.8 SAVE and RESTORE
The SAVE command is used to store data within a continuous address space. In this case, the destination source address (src) and the word count value (c24) are saved automatically. For this reason, when allocating memory for a destination buffer, set the size taking two additional words into
account.
Data can easily be restored using the RESTORE command.
17.9 Operation Mode
After a reset, the Command Sequencer defaults to the direct operating mode, i.e. commands must
be written to HIF register space by the host CPU.
If the system is up and command lists are available in memory, they can be executed by sending a
CALL instruction. The Command Sequencer then switches to indirect mode and fetches command
lists autonomously. If a RET command is received, the Command Sequencer switches back to direct operating mode and continues fetching commands from its command buffer (FIFO).
17.10Restart after detecting an illegal instruction
If the Command Sequencer detects an illegal instruction code, it stops execution and sets the Error
flag in the GFXAIC_Status register. The module can be restarted by writing a ‘1’ to the Clear bit in
the Control register. The command buffer will then be cleared and the Command Sequencer switches to direct operating mode.
17.11Overlapping buffers
If buffers overlap (permitted) e.g. executing a WRITE instruction to memory and then immediately
afterwards executing a COPY instruction of this data, the user has to ensure that all the data of the
WRITE instruction is stored in memory before starting the COPY instruction. This can be done by
inserting a SYNC instruction on CMDSEQ_FINISHED_WRITE (set the level and mask to
1000000H).
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High Speed SPI Interface (SPI)
Revised 24/7/13
Chapter 18: High Speed SPI Interface (SPI)
18.1 Features of HS_SPI
The HS_SPI module provides various operating modes for interfacing to serial peripheral devices
that use the de-facto standard SPI protocol. It also supports the new dual-bit and quad-bit SPI protocol. The following section lists the features of HS_SPI in detail:

Supports legacy, as well as the dual-bit and quad-bit modes of SPI operation

Supports up to four slave devices in master mode

Programmable transfer rate, active level of slave select signal, polarity and phase of the serial
clock per slave select

External serial flash and serial SRAM devices can be memory-mapped to the address space
of the host controller, in ’command sequencer’ mode 1

In ’command sequencer’ mode, memory accesses initiated by the host controller and the other
AHB masters are automatically converted to the serial memory read/write commands by
HS_SPI

’Direct’ mode allows HS_SPI to be used as a standard SPI through FIFO interface

Supports interfacing two devices through direct mode of operation
NOTE 1 ’Command sequencer mode’ is described in the Titan Hardware Manual. See also
“HS_SPI Module Control Register (GFXSPIn_MCTRL)”.
18.2 Block diagram of HS_SPI
The Figure 18-54: shows the internal block diagram of HS_SPI module.
Figure 18-54: Block diagram of HS_SPI
iSCLK
iPCLK
Clock
Mux
iHCLK
Clock to be divided
HS_SPI core logic
oSCLK
oSCLK_OEN
Address decoder
AHB
Slave
PPU and ECU
TX-FIFO
Command sequencer
Transaction
Sequence
comparator
generator
Idle timer
Address extender
SPI
FSM
iSSEL0
4
oSSEL3~0
4 oSSEL_OEN3~0
I/O PADs
CSR
set
RX-FIFO
DMA requests
DMA
acknowledgement
AHB
bus
Clock divider
Shift register
Interrupt
requests
To all blocks other
than SPI-core
4
iSDATA
4
oSDATA
Multi-bit SPI
interface
(external)
4 oSDATA_OEN
SPI
Core
HS_SPI Wrapper
HS_SPI register set
The operation of HS_SPI can be controlled and monitored through its Configuration and Status register (CSR) set (see “HS_SPI Module Control Register (GFXSPIn_MCTRL)” etc.)
SPI core and clock divider
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High Speed SPI Interface (SPI)
The SPI core is the protocol engine, which drives/samples the serial interface. The SPI communication related attributes (serial clock frequency, serial clock phase and polarity, etc.) are configured
in the CSR. On the host side, based on whether HS_SPI is operating in direct mode or in command
sequencer mode, the SPI core connects either with the FIFOs or with the command sequencer.
When operating as an SPI master, HS_SPI can initiate serial transfers with four SPI slaves, which
are connected to the four slave-select lines: SSEL0, SSEL1, SSEL2, and SSEL3. When operating
as an SPI slave, HS_SPI can respond to serial transfers initiated by the external SPI master, when
its SSEL0 pin is asserted. The internal clock divider is used to derive the serial clock output (SCLK),
which is used when HS_SPI acts as an SPI master. The ’clock mux’ multiplexes between the two
source clocks: AHB clock (i.e. iHCLK) and the peripheral clock (i.e. iPCLK) and selects one of them
as an input to the clock divider, depending on the configuration in CSR.
AHB interface and address decoding
The AHB masters can access the HS_SPI module through its AHB slave interface. The address decoder decodes the AHB address bus. If the access is for a register, the same is routed to the CSRs.
In command sequencer mode, if the AHB access is for a serial memory device, which is mapped
onto one of the four slave-select lines, then the memory address is passed on to the command sequencer.
TX-FIFO and RX-FIFO
HS_SPI internally has two FIFOs for temporary storage, one for the data to be transmitted and one
for the data to be received. Each FIFO is 16 locations deep and has a data width of 32 bits. The
FIFOs are used by HS_SPI in direct mode of operation.
Command Sequencer
The command sequencer maps the external serial memory devices on the address space of the
host controller. It consists of: ’transaction comparator’, ’address extender’, ’idle timer’, and ’sequence generator’.
Whenever there is an access to the memory-mapped serial memory device, the sequence generator initiates a serial transaction for accessing the external memory device. The address for the serial
memory device is generated by the ’address extender’ logic block. This actually concatenates some
of the bits from the AHB address bus with the HS_SPI address extension register. After a memory
read/write transaction on the serial interface is complete, the sequence generator responds to the
AHB master, cuts the serial clock but keeps asserting the corresponding slave select output, for a
period defined by the idle timer. Within the idle time out period, if the transaction comparator receives an access to the external serial memory, which has the address and the access-type (i.e.
read/write) same as the previous, then the sequence generator simply switches on the serial clock,
to access the next location of the serial memory.
Peripheral protection and error collection
The peripheral protection logic in HS_SPI protects the HS_SPI CSRs from the illegal AHB accesses, based on the access levels defined in the PPU module of the MCU. Occurrence of faults are
signalled by HS_SPI to the BECU, so that the BECU can collect the information about the transfer.
18.3 HS_SPI Operation
18.3.1 Operation Modes
HS_SPI can be configured in one of the two operating modes: direct mode and command sequencer mode (see CSEN in the “HS_SPI Module Control Register (GFXSPIn_MCTRL)”).
Direct mode
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High Speed SPI Interface (SPI)
Revised 24/7/13
In direct mode of operation the host controller can directly write the data to be transmitted into the
TX-FIFO. Similarly, the host controller can directly read the data received over the serial interface
from the RX-FIFO and from the shift register. The SPI core transfers the data to/from the FIFOs over
the serial interface. Based on the configuration in the CSR, in direct mode, HS_SPI can work either
as an SPI master or as an SPI slave.
Command Sequencer mode
In Command Sequencer mode, HS_SPI can act as an SPI master only. In this mode, HS_SPI maps
the external serial Flash or serial SRAM devices onto the address space of the MCU. Up to four serial memory devices can be mapped in this way, one on each of the four slave select outputs. If the
host controller (or any other AHB master) initiates an AHB transfer to access any of the mapped
serial memory device, the HS_SPI initiates serial transfer for the corresponding memory read or
write operation. Until the time HS_SPI accesses the external device, the AHB transfer is stalled.
18.3.2 Clocking modes
Based on the programmed values of the “HS_SPI Peripheral Communication Configuration Register 0~3 (GFXSPIn_PCC0~3)”.CPOL, CPHA and ACES bits, each peripheral can have up to eight
clocking modes. These bits, along with the RTM bits together decide the serial data input and output
timings of HS_SPI, with respect to the serial SPI clock. This is explained in the following table.
Mode
ACES
(active clock
edges are
same)
CPOL
(clock
polarity)
CPHA
(clock
phase)
Mode 0
0
0
0
Description
Output data is driven one half-cycle before the
first positive edge of the serial clock and on
subsequent negative edges.
Input data is sampled on positive edges of the
serial clock.
Mode 1
0
1
Output data is driven on positive edges of the
serial clock.
Input data is sampled on the negative edges of
the serial clock.
Mode 2
1
0
Output data is driven one half-cycle before the
first negative edge of the serial clock and on
subsequent positive edges.
Input data is sampled on the negative edges of
the serial clock.
Mode 3
1
1
Output data is driven on the negative edge of
the serial clock.
Input data is sampled on the positive edges.
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Revised 24/7/13
High Speed SPI Interface (SPI)
Mode
ACES
(active clock
edges are
same)
CPOL
(clock
polarity)
CPHA
(clock
phase)
Mode 4
1
0
0
Description
Output data is driven one half-cycle before the
first positive edge of the serial clock and on
subsequent negative edges.
Input data is sampled on negative edges of the
serial clock.
Mode 5
0
1
Output data is driven on positive edge of the
serial clock.
Input data is sampled one half-cycle after the
first negative edge of the serial clock and on the
subsequent positive edges of the serial clock.
Mode 6
1
0
Output data is driven one half-cycle before the
first negative edge of the serial clock and on
subsequent positive edges.
Input data is sampled on the positive edges of
the serial clock.
Mode 7
1
1
Output data is driven on the negative edge of
the serial clock.
Input data is sampled one half-cycle after the
first positive edge of the serial clock and on the
subsequent negative edges of the serial clock.
Table 18-23: Clocking Modes
Timing waveforms, indicating the serial data and the serial clock, along with the different combinations of “HS_SPI Peripheral Communication Configuration Register 0~3 (GFXSPIn_PCC0~3)”.ACES, CPOL and CPHA bits are depicted in Figure 18-55:.
As indicated in Figure 18-55:, when GFXSPIn_PCC0~3:ACES bit is set, the data driving and sampling points are separated by one complete clock period (as against the case in traditional
GFXSPIn_PCC0~3:ACES = 0 configuration, where the data driving and sampling points are separated only with a half-clock period). Thus, when GFXSPIn_PCC0~3:ACES is set, the transfer runs
for one extra clock cycle. On start of a transfer in receive mode, HS_SPI skips the sampling of data
on the first sampling point, and actually starts sampling the data from the next sampling point. This
skipping of the data on first sampling point is done in order to capture the correct serial data in retimed mode.
NOTE When GFXSPIn_PCC0~3:ACES is set, if transmission and reception are both enabled
simultaneously through the CSRs, then the extra clock cycle inserted at the start of the
reception has a side-effect of also transmitting some data for an extra clock cycle to the SPI
slave which is interfaced with HS_SPI master. Therefore, to avoid this extra data
transmission when GFXSPIn_PCC0~3:ACES is configured, the users shall disable the
transmission while reception is enabled.
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High Speed SPI Interface (SPI)
Revised 24/7/13
Figure 18-55: Clocking modes of the serial interface clock
Case (1): Launch/capture timings when GFXSPIn_PCC0~3.ACES is 0
1
Serial
clock
2
3
4
5 6
7
9 10 11 12 13 14 15 16
8
(CPOL = 0)
(CPOL = 1)
Slave select
Sampling points
CPHA = 1 Serial data
Invalid
D0
D4
D3
D2
D1
D5
D7
D6
Invalid
Sampling points
CPHA = 0 Serial data Invalid
D0
D4
D3
D2
D1
D5
Invalid
D7
D6
Case (2): Launch/capture timings when GFXSPIn_PCC0~3.ACES is 1
1
Serial
clock
2
3
4
5 6
7
9 10 11 12 13 14 15 16 17 18
8
(CPOL = 0)
(CPOL = 1)
Slave select
Sampling points
CPHA = 1 Serial data
Invalid
D0
D4
D3
D2
D1
D5
D7
D6
Invalid
Sampling points
CPHA = 0 Serial data Invalid
D0
D1
D2
D3
D4
D5
D6
D7
Invalid
As shown in the figure, when GFXSPIn_PCC0~3:ACES is set to 1, one extra clock cycle is required
for the serial data to be correctly captured by the remote device.
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High Speed SPI Interface (SPI)
18.3.3 Retimed clock
Some of the serial flash devices use SCLK frequencies of 80 MHz (and above), and they leave very
tight setup margins, for the serial data to be captured by HS_SPI. When HS_SPI is interfaced with
such memory devices, then data setup violations might occur at the registers, which are used to capture the serial data input. To capture the valid data read from such serial memories, the retimed
clock mode shall be used. Retimed clock mode can be set using the GFXSPIn_PCC0~3:RTM bit.
Figure 18-56: Retimed clock in HS_SPI
4
oSDATA
4 oSDATA_OEN
4
iSDATA
Multi-bit SPI
Interface
(External)
I/O PADs
iSCLK
(Retimed Clock)
D
Q
FF
oSCLK
oSCLK_OEN
Capture register(s)
iSSEL0
4 oSSEL3~0
4 oSSEL_OEN3~0
MCU core
HS_SPI module
Figure 18-56: shows how the retimed clock is generated in this module. The registers which are
used for capturing the serial data input are placed physically close to the I/O pads, in the host controller boundary. In retimed clock mode (i.e. when GFXSPIn_PCC0~3:RTM = 1), these registers are
sourced from the clock input which is looped back to the HS_SPI (from oSCLK to the I/O pad at the
peripheral of the host controller and back to the HS_SPI) i.e. iSCLK input is used for capturing the
input data. This is the retimed clock. This retiming technique is a cycle stealing technique, which
allows late arriving serial data signals (i.e. iSDATA[3:0]) to be sampled at a later point in time, by
intentionally introducing a skew on the clock.
18.3.4 Serial clock frequency
When HS_SPI is programmed to master mode, the SCLK clock is internally generated by dividing
either the AHB clock (iHCLK) or the Peripheral clock (iPCLK). The GFXSPIn_PCC0~3 registers
control the selection of the source clock for each of the four slave selects. The clock division ratio of
the resulting internal clock divider can also be programmed in these registers.
Figure 18-57: shows how the serial clock is generated. The GFXSPIn_PCC0~3:CDRS field decides
the clock division ratio. The frequency ’Fo’ of the clock generated by the clock divider is given by the
equation:
Fo = Fi / (2 x GFXSPIn_PCC0~3:CDRS)
Where Fi is the frequency of the source clock selected by the GFXSPIn_PCC0~3:CDSS field.
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High Speed SPI Interface (SPI)
Revised 24/7/13
If the GFXSPIn_PCC0~3:CDRS field is 0, the clock divider is bypassed, so that the frequency of
SCLK output is same as that of source clock. For a non-zero value of GFXSPIn_PCC0~3:CDRS
field, the output of clock divider (i.e. clock with frequency Fo) is the serial clock (i.e. SCLK).
Figure 18-57: Serial clock generation in master mode of operation
GFXSPIn_PCC0~3.CDRS
GFXSPIn_PCC0~3.CDSS
iPCLK
iHCLK
Source
Clock Clock
Mux
(Fi)
Source Clock
Selection
Clock
Divider
(Fo)
Clock
Serial Clock
Mux
(SCLK)
(Fi)
Divider
Bypass
18.3.5 SPI protocol
HS_SPI supports both, legacy SPI as well as the new dual-bit or quad-bit SPI protocol. While in direct mode of operation, the “HS_SPI Direct Mode Transfer Protocol Register
(GFXSPIn_DMTRP)”.TRP[1:0] bits decide whether HS_SPI uses legacy, the dual-bit or the quad-bit
protocol. While in command sequencer mode, the “HS_SPI Command Sequencer Configuration
Register (GFXSPIn_CSCFG)”.MBM bits decide whether the HS_SPI uses legacy, the dual-bit or the
quad-bit protocol. The dual-bit and quad-bit SPI protocol is used for interfacing with the newer generation serial flash memory devices.
Legacy SPI protocol
The legacy SPI protocol is a full-duplex protocol. When HS_SPI is configured in master mode with
legacy SPI protocol, the data can be received on a single wire (i.e. SDATA[1]) and simultaneously,
the data can also be transmitted on a single wire (i.e. SDATA[0]). When HS_SPI is configured in
slave mode with legacy SPI protocol, the data can be received on a single wire (i.e. SDATA[0]) and
simultaneously, the data can also be transmitted on a single wire (i.e. SDATA[1]). While legacy SPI
protocol is being used, the unused data lines (i.e. SDATA[2] and SDATA[3]) are tri-stated by
HS_SPI.
In direct mode, when GFXSPIn_DMTRP:TRP is configured for ‘TX-and-RX in legacy mode’, ‘TX-only in legacy mode’ or ‘RX-only in legacy mode’, the full-duplex legacy SPI protocol is used by
HS_SPI.
Dual bit protocol
In a dual-bit SPI protocol, two serial data lines (i.e. SDATA[1:0]) are used, in a half-duplex manner.
Data transmission and reception cannot happen simultaneously. While dual-bit SPI protocol is being
used, the unused data lines (i.e. SDATA[2] and SDATA[3]) are tri-stated by HS_SPI.
In direct mode, when GFXSPIn_DMTRP.TRP is configured for ‘TX-only in dual mode’, or ‘RX-only
in dual mode’, the dual-bit SPI protocol is used.
Quad bit protocol
In quad-bit SPI protocol, all four serial data lines (i.e. SDATA[3:0]) are used, in a half-duplex manner.
Data transmission and reception cannot happen simultaneously.
In direct mode, when GFXSPIn_DMTRP.TRP is configured for ‘TX-only in quad mode’ or ‘RX-only
in quad mode’, the quad-bit SPI protocol is used.
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High Speed SPI Interface (SPI)
18.3.6 Shift direction
The HS_SPI Peripheral Communication Configuration (GFXSPIn_PCC0~3) registers have a bit (i.e.
SDIR), which decides the direction in which the shift register is shifted.
When GFXSPIn_PCC0~3:SDIR is 0, most significant bit in the shift register is transmitted first and
the first received data is shifted into the least significant bit in the shift register. i.e. the shift register
is shifted left. When GFXSPIn_PCC0~3:SDIR is 1, least significant bit in the shift register is transmitted first and the first received data is shifted into the most significant bit in the shift register. i.e.
the shift register is shifted right. Irrespective of the value of the GFXSPIn_PCC0~3:SDIR bit, the
read/write accesses to the Data registers always have least significant bit of the data in bit 0.
Figure 18-58: and Figure 18-59: depict the direction in which the data in the shift register is shifted
to/from the serial data lines, in when either legacy, dual-bit or quad-bit SPI protocol is used. The
waveforms assume GFXSPIn_PCC0~3:CPOL = 0, GFXSPIn_PCC0~3:CPHA = 0 and “HS_SPI
FIFO Configuration Register (GFXSPIn_FIFOCFG)”.FWIDTH = 0. The figures depict that the transmit data is loaded into the shift register from the TX-FIFO. However, it shall be noted that the source
of transmit data could also be the other Data registers, like the “HS_SPI Read Command Sequence
Data/Control Register 0~7 (GFXSPIn_RDCSDC0~7)”.RDCSDATA or the “HS_SPI Write Command
Sequence Data/Control Register 0~7 (GFXSPIn_WRCSDC0~7)”.WRCSDATA.
Figure 18-58: Shift direction (assumptions: GFXSPIn_PCC0~3.CPOL = 0, GFXSPIn_PCC0~3.CPHA =
0, GFXSPIn_PCC0~3.SDIR = 0, GFXSPIn_FIFOCFG.FWIDTH = 0)
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High Speed SPI Interface (SPI)
Revised 24/7/13
TX-FIFO
RX-FIFO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
RX FIFO pop
TX FIFO push
MSB
LSB
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
Pop
Push
FIFO into shift register
Shift register into FIFO
LSB
MSB
Shift register
D7
D6
D5
D4
D3
D2
LSB
MSB
Shift register
D0
D1
D7
D6
Shift right (SDIR = 1)
1
2
3
D5
D4
D0
Shift right (SDIR = 1)
4
5 6
7
8
9 10 11 12 13 14 15 16
Serial clock
Slave select
SDATA[0] Invalid
Legacy
SPI
SDATA[1] Invalid
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SDATA[0] Invalid
Dual-bit
SDATA[1] Invalid
SPI
D0
D2
D4
D6
D0
D2
D4
D6
D1
D3
D5
D7
D1
D3
D5
D7
SDATA[0] Invalid
D0
D4
D0
D4
D0
D4
D0
D4
SDATA[1] Invalid
D1
D5
D1
D5
D1
D5
D1
D5
SDATA[2] Invalid
D2
D6
D2
D6
D2
D6
D2
D6
SDATA[3] Invalid
D3
D7
D3
D7
D3
D7
D3
D7
Quad-bit
SPI
Figure 18-59: Shift direction (assumptions: GFXSPIn_PCC0~3.CPOL = 0, GFXSPIn_PCC0~3.CPHA =
0, GFXSPIn_PCC0~3.SDIR = 1, GFXSPIn_FIFOCFG.FWIDTH = 0)
Fujitsu Semiconductor Europe GmbH
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Revised 24/7/13
High Speed SPI Interface (SPI)
TX-FIFO
RX-FIFO
LSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
RX FIFO pop
TX FIFO push
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Pop
Push
FIFO into shift register
Shift register into FIFO
LSB
MSB
Shift register
D7
D6
D5
D4
D3
D2
D1
LSB
MSB
Shift register
D0
D7
D6
D5
Shift Left (SDIR = 0)
1
2
3
D4
D3
D2
D1
D0
Shift Left (SDIR = 0)
4
5 6
7
8
9 10 11 12 13 14 15 16
Serial clock
Slave select
SDATA[0] Invalid
Legacy
SPI
SDATA[1] Invalid
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SDATA[0] Invalid
Dual-bit
SDATA[1] Invalid
SPI
D6
D4
D2
D0
D6
D4
D2
D0
D7
D5
D3
D1
D7
D5
D3
D1
SDATA[0] Invalid
D4
D0
D4
D0
D4
D0
D4
D0
SDATA[1] Invalid
D5
D1
D5
D1
D5
D1
D5
D1
SDATA[2] Invalid
D6
D2
D6
D2
D6
D2
D6
D2
SDATA[3] Invalid
D7
D3
D7
D3
D7
D3
D7
D3
Quad-bit
SPI
18.3.7 Safe synchronisation of internal data
While a serial transfer is in progress, HS_SPI has to internally move the data across the two clock
domains (AHB clock domain and the serial clock domain), using synchronizers which have their inherent latency.
Synchronisation in master mode
In certain cases when the synchronizer latency becomes a bottleneck in the serial transfer, the data
will not be synchronised properly. To avoid this situation, the software programmers must ensure
that the GFXSPIn_PCC0~3:SAFESYNC is set in such cases.
18 - 10
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
The exact conditions, when the setting of the GFXSPIn_PCC0~3:SAFESYNC bit is required, depend on the transfer protocol, the width of the shift register, and the ratio between the AHB clock
frequency (i.e. Fhclk) and the Serial clock frequency (Fsclk).
When GFXSPIn_PCC0~3:SAFESYNC bit is set, HS_SPI master halts the current serial transfer intermittently while it is internally synchronizing the data. The duration of this halt is 3 periods of the
serial clock. The serial interface is halted for the safe synchronisation of internal data only when the
following three conditions are satisfied:

HS_SPI is in master mode (i.e. GFXSPIn_DMCFG:MST= 1’b1 or GFXSPIn_MCTRL:CSEN =
1’b1)

GFXSPIn_PCC0~3:SAFESYNC bit is set to 1

‘Width of shift register is 8 bits and serial interface is configured for dual bit or quad bit mode’
or ‘Width of shift register is 16 bits and serial interface is configured for quad bit mode’
Thus, when the GFXSPIn_PCC0~3:SAFESYNC bit is set to 1, after the transfer of each data chunk,
the SPI core in HS_SPI on the fly decides whether to wait for safe synchronisation or not, depending
on the width of the shift register that is being used at that particualr instant. Merely setting the
GFXSPIn_PCC0~3:SAFESYNC bit does not imply that the SPI core would insert extra wait states
(for safe synchronisation) for every chunk of the data being transmitted. It inserts the extra wait
states if and only if the specific conditions related to the width of shift register and the SPI protocol
(i.e. legacy/dual/quad) in use are satisfied. This ensures that the achievable bandwidth of the serial
transfer is not severely hampered due to the time lost in safe synchronisation.
The term ‘Width of shift register‘, used above, with reference to GFXSPIn_PCC0~3:SAFESYNC bit
is explained in the following sub-sections.
In direct mode, generally the width of the shift register is decided by the width of the FIFOs, configured in GFXSPIn_FIFOCFG:FWIDTH. However, there are two special conditions that also need to
be considered:
a) If the GFXSPIn_FIFOCFG:TXCTRL bit in any of the TX-FIFO locations is set to 1, then the smallest width of the shift register used during the entire transfer is 1 byte. This smallest value of the shift
register width shall be used by HS_SPI while deciding whether safe synchronisation is required for
a transfer or not.
b) Specifically while using the Counter mode (i.e. “HS_SPI Direct Mode Byte Count Control Register
(GFXSPIn_DMBCC)” and “HS_SPI Direct Mode Byte Count Status Register (GFXSPIn_DMBCS)”)
for stopping the serial transfer, if the number of bytes to be transferred (programmed in
GFXSPIn_DMBCC register) is not divisible by the number of bytes configured in the FIFO width (i.e.
GFXSPIn_FIFOCFG:FWIDTH field), then the remainder of the division decides the smallest width
of the shift-register that is used during the transfer. As an example, if GFXSPIn_DMBCC:BCC is programmed with a value of 10 bytes and the GFXSPIn_FIFOCFG:FWIDTH is programmed with a value of 4 bytes, then the HS_SPI will perform the loading/unloading of the shift register in sets of 4
bytes, followed again by 4 bytes and the remaining chunk of 2 bytes is transferred before the transfer
ends. Thus, in this case the smallest width of the shift register used during the entire transfer is of 2
bytes (assuming that the GFXSPIn_FIFOCFG:TXCTRL bit in all TX-FIFO locations is 0). This smallest value of the shift register width shall be used by HS_SPI while deciding whether safe synchronisation is required for a transfer or not.
The following table shows the conditions when the GFXSPIn_PCC0~3:SAFESYNC bit shall be set
by the CPU to clock domain and the serial clock domain ‘1’ while HS_SPI is configured in direct
mode, master operation.
Fujitsu Semiconductor Europe GmbH
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Revised 24/7/13
High Speed SPI Interface (SPI)
Table 18-24: Criteria for setting the HSSPIn_PCC0~3:SAFESYNC bit in direct mode, master
operation
Mode
Direct mode,
master
GFXSPIn_PCC0~3:
SAFESYNC shall be
set to ‘1’, if:
Width of shift
register
Protocol
8 bits
Legacy
GFXSPIn_PCC0~3:SA
FESYNC is not required
Dual bit
Fsclk > (1/2) Fhclk
Quad bit
Fsclk > (1/5) Fhclk
Legacy
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Dual bit
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Quad bit
Fsclk > (1/2) Fhclk
Legacy
GFXSPIn_PCC0~3:
SAFESYNC is not
required
16 bits
24 bits
Dual bit
Maximum supported
SCLK frequency
Fsclk = Fhclk
Quad bit
32 bits
Legacy
Dual bit
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Quad bit
In command sequencer mode, while the command sequence is being transmitted, the width of the
shift register is 8 bits, and while the data is being written/read (to/from the serial memory), the width
of the shift register is equal to the AHB bus transfer size.
The following table precisely describes the conditions where setting the GFXSPIn_PCC0~3:SAFESYNC bit to ‘1’ is required while operating in command sequencer mode.
18 - 12
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
Table 18-25: Criteria for setting the SAFESYNCbit in Command Sequencer Mode
Mode of
operation
Command
sequencer
AHB transfer
size of the
memory-map
ped transfer
Protocol
8 bits
Legacy
16 bits
32 bits
GFXSPIn_PCC0~3:
SAFESYNC shall be
set to ‘1’, if:
Maximum supported
SCLK frequency
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Fsclk = Fhclk
Dual bit
Fsclk > (1/2) Fhclk
Quad bit
Fsclk > (1/6) Fhclk
Fsclk = (3/4) Fhclk
Legacy
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Fsclk = Fhclk
Dual bit
Fsclk > (1/2) Fhclk
Quad bit
Fsclk > (1/5) Fhclk
Legacy
GFXSPIn_PCC0~3:
SAFESYNC is not
required
Dual bit
Fsclk > (1/2) Fhclk
Quad bit
Fsclk > (1/5) Fhclk
Synchronisation in slave mode
While HS_SPI is configured in slave mode, the external SPI master must control the flow of the serial data, to avoid the loss of synchronisation.
Refer to Table 18-26 on page 14 It tabulates the maximum supported Fsclk values. While operating
in slave mode, if the serial clock frequency is more than the value depicted in Table 18-26 on
page 14, then data would be unpredictable. Therefore, in slave mode, the SPI master shall be configured to generate serial clock frequencies which is lesser than the maximum value of Fsclk shown
in Table 18-26 on page 14.
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Revised 24/7/13
High Speed SPI Interface (SPI)
Table 18-26: Maximum supported SCLK frequency in slave mode
Mode
Direct mode,
slave
Width of shift
register
Protocol
8 bits
Legacy
Dual bit
16 bits
24 bits
GFXSPIn_PCC0~3:
SAFESYNC value
Maximum supported
SCLK Frequency
Safe synchronisation is
not applicable in slave
mode.
Fsclk = Fhclk
Fsclk = (1/2) Fhclk
Quad bit
Fsclk = (1/5) Fhclk
Legacy
Fsclk = Fhclk
Dual bit
Fsclk = Fhclk
Quad bit
Fsclk = (1/2) Fhclk
Legacy
Fsclk = Fhclk
Dual bit
Quad bit
32 bits
Legacy
Dual bit
Quad bit
18.3.8 Debug mode
HS_SPI can be configured in debug mode, using the GFXSPIn_MCTRL:DEN bit.
If the iDEBUG input signal of HS_SPI is asserted when the HS_SPI is in debug mode and is working
as a master in direct mode of operation, then the serial interface is halted by stopping the activity on
the serial clock output of HS_SPI. The clock is stopped as long as the iDEBUG input is asserted and
the debug mode is enabled. While the serial interface is halted, the CSR registers of HS_SPI can
still be accessed normally by the AHB master.
The activity on the serial clock resumes either when the iDEBUG input is de-asserted or when the
debug mode is disabled in GFXSPIn_MCTRL:DEN bit.
18.4 Direct mode
In direct mode, the MCU (or the DMA engine) is responsible to directly control the serial transfer on
the serial interface. Direct mode of transfer can be enabled using the GFXSPIn_MCTRL:CSEN bit.
In direct mode of operation, HS_SPI uses its internal FIFOs, for temporary storage of the data to be
transmitted and the data received over the serial interface. This section describes the direct mode
of operation.
18.4.1 Internal FIFOs
HS_SPI internally has two FIFOs for temporary storage: one for the data to be transmitted and one
for the data to be received.
Based on whether the serial transfers in HS_SPI are configured as TX-only, RX-only or TX-and-RX
in the GFXSPIn_DMTRP:TRP field, only one or both FIFOs are used by HS_SPI. If HS_SPI is configured for TX-only operation the TX-FIFO is used. If HS_SPI is configured for RX-only operation,
the RX-FIFO is used. If HS_SPI is configured for TX-and-RX operation, then both FIFOs are used.
18 - 14
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
FIFO size
Each FIFO is 16-locations deep and has a data width of 32 bits. However, the software can configure the valid data width of the TX-FIFO and the RX-FIFO in GFXSPIn_FIFOCFG:FWIDTH.
The shift register in the SPI core is 32-bit wide. When the width of the FIFO is changed in the
GFXSPIn_FIFOCFG:FWIDTH field, the usable width of the shift register also changes accordingly.
For details refer to Figure 18-60:.
Figure 18-60: HS_SPI in direct mode
SPI Core
CSR
32
RX-FIFO
GFXSPIn_RXFIFO
SPI
Shift
register
32
GFXSPIn_TXFIFO
GFXSPIn_FIFOCFG.TXCTRL
Serial
Interface
33rd bit
TX-FIFO
In addition to the 32-bit of data width, each location in TX-FIFO has a 33rd control bit (known as
GFXSPIn_FIFOCFG:TXCTRL bit), which decides whether the data from the TX-FIFO is to be transmitted by the SPI core, or whether the serial data lines are to be tri-stated. If the
GFXSPIn_FIFOCFG:TXCTRL bit is set to ‘1‘, HS_SPI further decodes the bit 0 of the data in the
corresponding TX-FIFO location. All possibilities of the combinations of values of the
GFXSPIn_FIFOCFG:TXCTRL bit and the bit 0 of TX-FIFO data are tabulated in
Figure 18-60:.
Table 18-27: Tri-stating the serial data output lines during transmission
GFXSPIn_FIFOCF
G:TXCTRL
Bit 0 of
TX-FIFO
data
Description
0
Don’t care
Serial data output lines are not tri-stated while transmitting the
corresponding data.
1
0
Serial data output lines are tri-stated for 1 byte time. The data
from the corresponding TX-FIFO location is not transmitted.
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Revised 24/7/13
High Speed SPI Interface (SPI)
Table 18-27: Tri-stating the serial data output lines during transmission
GFXSPIn_FIFOCF
G:TXCTRL
Bit 0 of
TX-FIFO
data
Description
1
1
Irrespective of the shift direction configured in
GFXSPIn_PCC0~3:SDIR bits, the data transmission takes
place in the following order:
1. Data bits [7:4] from the corresponding TX-FIFO location are transmitted. Direction of transmission of
this data depends on configuration of
GFXSPIn_PCC0~3:SDIR bit.
2. SDATA output lines are tri-stated for 4-bit times.
For all practical reasons (e.g. while using the GFXSPIn_DMBCC:BCC feature or while referring to
Table 18-24:) the data in the TX-FIFO location for which the GFXSPIn_FIFOCFG:TXCTRL bit is set,
is considered to be 1-byte wide. The GFXSPIn_FIFOCFG:TXCTRL bit associated with the data
words in the TX-FIFO allows the software to generate the command sequences (using direct mode),
for interfacing with some quad-bit SPI memories available in the market, which need to tri-state the
serial data (i.e. SDATA) lines during the ‘dummy’ cycles or during the transmission of lower nibble
of the ‘mode bits’ of the command sequence.
FIFO accesses
Irrespective of the configured width of the FIFOs, only 32-bit word accesses are allowed to the
GFXSPIn_RXFIFO and GFXSPIn_TXFIFO registers.
A read access to the GFXSPIn_RXFIFO register in CSR directly pops out a word from the RX-FIFO.
If the RX-FIFO width was set to 8-bit, then the most-significant 24 bits read out from
GFXSPIn_RXFIFO register are logic 0. Similarly, when FIFO-width is set to 16-bit or 24 bits, the unused bits read-out from GFXSPIn_RXFIFO register are logic 0.
A write access to the GFXSPIn_TXFIFO register in CSR pushes a word of data and a
GFXSPIn_FIFOCFG.TXCTRL bit (see GFXSPIn_FIFOCFG.TXCTRL) into the TX-FIFO. However,
when HS_SI transmits the data on the serial lines, it uses only the least significant bits of the data
read from the GFXSPIn_TXFIFO register. The number of these least significant bits that are transmitted depend on the configured width of the TX-FIFO. The unused most significant bits are ignored
by HS_SPI.
Accessing the RX-data
The serial data received by HS_SPI on the SDATA lines is assembled in a shift register (in the SPI
core), before it is pushed into the RX-FIFO.
When a transfer completes (i.e. slave-select line is de asserted), the GFXSPIn_RXSHIFT register
is updated by with the assembled data and the GFXSPIn_RXBITCNT.RXBITCNT field is updated
with the number of bits valid in GFXSPIn_RXSHIFT register. When the GFXSPIn_TXF.TSSRS or
the GFXSPIn_RXF.RSSRS interrupt flag is set, the software can read the GFXSPIn_RXSHIFT and
GFXSPIn_RXBITCNT.RXBITCNT field, to get the RX data which is not yet pushed into the
RX-FIFO.
18 - 16
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
18.4.2 Service requests
When operating in direct mode, interrupt service requests to the MCU are triggered based on the
current fill levels of the TX-FIFO and the RX-FIFO, and their configured threshold values. Alternatively, the external DMA engine can be used for data transfers. HS_SPI has an interface with the
DMA engine in MCU, for transfers to/from its TX-FIFO and the RX-FIFO, when operating in direct
mode. Interrupt flags are also set when the current SPI transfer finishes.
Assertion of interrupt service requests based on FIFO levels
The fill levels of both FIFOs are accessible to the system through the GFXSPIn_DMSTATUS.TXFLEVEL and the GFXSPIn_DMSTATUS.RXFLEVEL fields. The interrupt service requests are generated by HS_SPI based on the FIFO fill levels and their threshold values configured by the MCU.
The ‘TX-FIFO Fill-level Less Than or Equal to Threshold’ (i.e. GFXSPIn_TXF.TFLETS) interrupt flag
is set, if the TX-FIFO fill level (i.e GFXSPIn_DMSTATUS.TXFLEVEL) is less than or equal to the
TX-FIFO threshold value configured in GFXSPIn_FIFOCFG.TXFTH.
The ‘RX-FIFO Fill-level More than Threshold’ (i.e. GFXSPIn_RXF.RFMTS) interrupt flag is set, if the
RX-FIFO fill level (i.e. GFXSPIn_DMSTATUS.RXFLEVEL) is more than the RX-FIFO threshold value configured in GFXSPIn_FIFOCFG.RXFTH.
If HS_SPI is configured for TX-only operation, the RX-FIFO is not used. If HS_SPI is configured for
RX-only operation, the TX-FIFO is not used.
Assertion of DMA service requests based on FIFO levels
HS_SPI supports block transfer mechanism of DMA engine. The DMA service requests are generated by HS_SPI, based on the FIFO fill levels and their threshold values configured by the MCU. To
keep track of the number of successful data transfers to/from the TX FIFO and/or the
RX FIFO, HS_SPI internally maintains two Down Counters: HS_SPI RX block counter and HS_SPI
TX block counter. Each of these counters is a 5-bit Down Counter, which is reloaded with the DMA
block size (for the respective channel) whenever the DMA service request for that channel is asserted. The counters are decremented with every successful read (or write) accesses to the RX FIFO
(or TX FIFO). In case of the RX FIFO accesses, the RX block counter is decremented only if the
access was from an AHB master other than the DAP controller. The block counters do not underflow
(i.e. the counter value remains 0 even if it is decremented while it is already 0).
Each DMA channel (read channel and write channel) has a dedicated DMA block size fault status
flag in the GFXSPIn_FAULTF register. A DMA block size fault is triggered if all of the following conditions are satisfied:

The DMA block counter is decremented (due to a valid AHB access) while it is already 0.
1. The DMA enable bit (HSPIn_DMDMAEN.RXDMAEN or HSPIn_DMDMAEN.TXDMAEN) for the
corresponding DMA channel is set to 1.
2. Module is enabled (i.e. GFXSPIn_MCTRL.MES = 1).
3. Module is operating in direct mode of operation (i.e. GFXSPIn_MCTRL.CSEN = 0).
The DMA read channel must be setup to perform a block transfer of ‘GFXSPIn_FIFOCFG.RXFTH
+ 1‘ transfers. The DMA write channel must be setup to perform a block transfer of
‘16 - GFXSPIn_FIFOCFG.TXFTH‘ transfers. These values are reloaded into the HS_SPI module’s
internal block counters, whenever the DMA read/write channel service request is asserted.
The DMA block counter is reset to ‘0‘ in either of the following conditions:

The corresponding DMA channel is disabled (in HSPI_DMDMAEN register).
1. Module is completely disabled (i.e. GFXSPIn_MCTRL.MES = 0).
2. Mode of operation is switched from direct mode to command sequencer mode.
The RX DMA service request (for DMA read channel) is asserted if all of the following conditions are
satisfied:
Fujitsu Semiconductor Europe GmbH
18 - 17
Revised 24/7/13

High Speed SPI Interface (SPI)
RX FIFO fill level (i.e. GFXSPIn_DMSTATUS.RXFLEVEL) is more than the RX-FIFO threshold
value configured in GFXSPIn_FIFOCFG.RXFTH. This condition is same as the
GFXSPIn_RXF.RFMTS bit.
1. HS_SPI RX block counter value is 0.
2. DMA read channel acknowledgement signal is de asserted by the DMA engine.
3. Previous service request for DMA read channel is not pending.
4. DMA read channel service request is enabled in the GFXSPIn_DMDMAEN.RXDMAEN bit,
AND
5. DMA read channel block size fault interrupt flag is not set
(i.e. GFXSPIn_FAULTF.DRCBFES = 0).
6. Module is enabled (i.e. GFXSPIn_MCTRL.MES = 1).
7. Module is in direct mode (i.e. GFXSPIn_MCTRL.CSEN = 0).
8. The configured transfer protocol (in GFXSPIn_DMTRP) is such that RX FIFO is used. e.g. If
HS_SPI is configured for TX-only operation, the RX-FIFO is not used and DMA read service
request is not asserted in such cases.
The RX DMA service request (for DMA read channel) is de asserted if any of the following condition
is satisfied:

DMA read channel service request has been acknowledged by the DMA engine.
1. DMA read channel service requests have been disabled
(i.e. GFXSPIn_DMDMAEN.RXDMAEN = 0).
2. Module is completely disabled (i.e. GFXSPIn_MCTRL.MES = 0).
3. Mode of operation is switched from direct mode to command sequencer mode.
The TX DMA service request (for DMA write channel) is asserted if all of the following conditions are
satisfied:

TX FIFO fill level (i.e. GFXSPIn_DMSTATUS.TXFLEVEL) is less than or equal to the threshold
value configured in GFXSPIn_FIFOCFG.TXFTH. This condition is same as the
GFXSPIn_TXF.TFLETS interrupt flag.
1. HS_SPI TX block counter value is 0.
2. DMA write channel acknowledgement signal is de asserted by the DMA engine.
3. Previous service request for DMA write channel is not pending.
4. DMA write channel service request is enabled in the GFXSPIn_DMDMAEN.TXDMAEN bit.
5. DMA write channel block size fault interrupt flag is not set
(i.e. GFXSPIn_FAULTF.DWCBSFS = 0).
6. Module is enabled (i.e. GFXSPIn_MCTRL.MES = 1).
7. Module is in direct mode (i.e. GFXSPIn_MCTRL.CSEN = 0).
8. The configured transfer protocol (in GFXSPIn_DMTRP) is such that TX FIFO is used. e.g. If
HS_SPI is configured for RX-only operation, the TX-FIFO is not used and DMA write service
request is not asserted in such cases.
The TX DMA service request (for DMA Write Channel) is de asserted if any of the following condition
is satisfied:

DMA write channel service request has been acknowledged by the DMA engine.
1. DMA write channel service requests have been disabled
(i.e. GFXSPIn_DMDMAEN.TXDMAEN = 0).
2. Module is completely disabled (i.e. GFXSPIn_MCTRL.MES = 0).
3. Mode of operation is switched from direct mode to command sequencer mode.
Assertion of service requests on end of transfer
18 - 18
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
While operating in direct mode, the HS_SPI also triggers interrupts, when the slave select line is de
asserted. The slave select deassertion event is routed onto two interrupt flags
GFXSPIn_TXF.TSSRS and GFXSPIn_RXF.RSSRS, which have separate interrupt clear and interrupt enable bits. The interrupt flags are routed onto separate interrupt signals. This is indicated in
Figure 18-61:.
Figure 18-61: Routing of the ‘slave select released’ interrupt event
AHB transaction:
write ‘1’ to
GFXSPIn_TXC.TSSRC
GFXSPIn_TXE.
TSSRE
Clear
TX interru
signal
GFXSPIn_TXF.TSSRS
Flag
Set
Slave select released
interrupt event
GFXSPIn_RXE.
RSSRE
Set
AHB transaction:
write ‘1’ to
GFXSPIn_RXC.RSSRC
GFXSPIn_RXF.RSSRS
RX interru
signal
Flag
Clear
18.4.3 SPI transfers in master mode
When HS_SPI is SPI master, it initiates the transfers onto one of the four SPI slave-select lines, selected by the GFXSPIn_DMPSEL.PSEL field.
Communication attributes of HS_SPI in master mode
Communication over the serial interface has several attributes, such as frequency, polarity and
phase of the serial interface clock, polarity of the slave select line, etc. These communication attributes are different for different SPI devices. When HS_SPI is working as a master in direct mode of
operation, it can be interfaced with upto four slaves, each with a different values of these attributes.
These device-specific communication attributes can be configured in the GFXSPIn_PCC0~3 registers in CSR.
Initiating the serial transfers
When HS_SPI is enabled (i.e. GFXSPIn_MCTRL.MEN = 1) and is working as a master (i.e.
GFXSPIn_DMCFG.MST = 1) in direct mode (i.e. GFXSPIn_MCTRL.CSEN = 0), serial transfers are
initiated by HS_SPI when the GFXSPIn_DMSTART.START bit is set to ‘1’.
If GFXSPIn_DMTRP.TRP is programmed such that transmission is enabled, and if the TX-FIFO is
empty when the GFXSPIn_DMSTART.START bit is set to "1"; then HS_SPI delays the initiation of
the serial transfer until the TX-FIFO is written by the software.
While HS_SPI has delayed the initiation of the serial transfer (until TX-FIFO is written by software):
a) If GFXSPIn_MCTRL.MEN bit is reset to "0" by software, then the disabling of the module will take
precedence over starting the next transfer.
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b) If counter mode is used for controlling the transfer length, then the GFXSPIn_DMBCS register
will be loaded with the value in GFXSPIn_DMBCC register only when the serial transfer is initiated
by HS_SPI. Until then, the GFXSPIn_DMBCS register will maintain its 0 value.
NOTE Once the GFXSPIn_DMSTART.START bit is set to ‘1’, it cannot be reset by the software.
The HS_SPI module resets the bit after it has started the serial transfer. Writing a ‘1’ to the
GFXSPIn_DMSTART.START bit while it is already set to ‘1’ has no effect on the bit. Writing
a ‘1’ to the GFXSPIn_DMSTART.START bit while it is ‘0’ and a serial transaction is already
in progress does not affect the ongoing transfer. A new serial transfer is initiated after the
current transfer completes.
Halting a transfer due to lack Of TX-DATA or due to lack of RX-FIFO space
As per the standard SPI protocol, an ongoing transfer can be halted by keeping the slave select asserted and by cutting the serial clock. HS_SPI automatically cuts the serial clock while it is waiting
for the TX-FIFO to be written or while it is waiting for the RX-FIFO to be read. Depending on whether
the HS_SPI master is operating as TX-only, RX-only or TX-and-RX, there are three scenarios in
which HS_SPI cuts the serial clock and halts a transfer:
TX-only mode
The serial clock is cut when the TX-FIFO is empty and the shift register is empty.
RX-only mode
The serial clock is cut when the RX-FIFO is full and when the shift register is full.
TX-and-RX mode
The serial clock is cut when:
a) The TX-FIFO and the shift registers are empty
b) RX-FIFO and the shift registers are full
When an ongoing transfer is halted (by cutting the serial clock) by HS_SPI due to unavailability of
FIFO resources, the corresponding slave-select line is kept asserted, indicating to the slave, that the
transfer has not finished. The halted transfers are automatically resumed by HS_SPI (by starting the
toggling of the serial clock) when the FIFO resources become available.
Controlling the transfer length
In master mode, the transfer length (i.e the de-assertion of the slave-select lines) can be controlled
in two ways:

Counter mode and

Software flow control mode
These modes can be selected in GFXSPIn_DMCFG.SSDC bit.
In counter mode, the MCU is supposed to initialize the GFXSPIn_DMBCC.BCC field with the number of bytes to be transferred over the serial interface, before the slave-select (i.e. SSEL) output is
de asserted. When the HS_SPI transfers are initiated, the HS_SPI counts the number of bytes that
are transferred and releases the slave-select signal after the number of bytes indicated in
GFXSPIn_DMBCC.BCC have been transferred.
In software flow control mode, the MCU controls the transfer length by using the
GFXSPIn_DMSTOP.STOP bit. Depending on whether the HS_SPI master is operating as TX-only,
RX-only or TX-and-RX, the deassertion of slave-select output is controlled in the following ways:
TX-only mode
The transfer is completed when the GFXSPIn_DMSTOP.STOP bit is set and all contents of
TX-FIFO are transmitted.
RX-only mode
The transfer is completed, when the GFXSPIn_DMSTOP.STOP bit is set and all bits in the shift register (used in SPI core for assembling the received serial data) are shifted in.
TX-and-RX mode
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The transfer is completed when the GFXSPIn_DMSTOP.STOP bit is set and all the contents of
TX-FIFO are transmitted.
18.4.4 SPI transfers in slave mode
When HS_SPI is configured as a slave (i.e. GFXSPIn_DMCFG.MST = 0), it responds to the transfers initiated by the external masters, when its slave-select input (i.e. SSEL0) is asserted.
Communication attributes of HS_SPI in slave mode
Communication over the serial interface has several attributes, such as polarity and phase of the
serial interface clock, polarity of the slave select line, etc. These communication attributes are different for different SPI devices. When HS_SPI is working as a slave in direct mode of operation, its
communication attributes can be configured in the GFXSPIn_PCC0 register in CSR.
While in slave mode, the serial clock (SCLK) is driven by the external master.
Lack Of FIFO resources while a serial transfer is ongoing
When HS_SPI acts as a slave, it has no control over the serial transfer. Therefore, it is the responsibility of the software, to monitor the GFXSPIn_TXF.TFLETS, GFXSPIn_TXF.TFMTS,
GFXSPIn_RXF.RFLETS, and the GFXSPIn_RXF.RFMTS interrupt flags and ensure the availability
of FIFO resources.
While HS_SPI is configured for transmission (i.e. TX-only or TX-and-RX configuration in
GFXSPIn_DMTRP.TRP field), if the TX-FIFO becomes empty, HS_SPI sets the
GFXSPIn_TXF.TFES interrupt flag. Even after the TX-FIFO becomes empty, it keeps reading the
data from the TX-FIFO (causing a TX-FIFO Underrun) and transmitting the data it gets from the
TX-FIFO on the serial data lines, as long as the slave select is asserted and the clock is toggling.
While HS_SPI is configured for reception (i.e. RX-only or TX-and-RX configuration in
GFXSPIn_DMTRP.TRP field), if the RX-FIFO becomes full, HS_SPI sets the GFXSPIn_RXF.RFFS
interrupt flag and keeps overwriting the serial data received on the SDATA lines in to the RX-FIFO.
Table 18.28-1
18.5 Command sequencer mode
In command sequencer mode, HS_SPI acts as an SPI master, for interfacing with the external serial
memory devices. Each of the four slave select lines can be used for mapping uniform type of ‘serial
flash’ or ‘serial SRAM’ devices. Memory accesses initiated by the MCU and other AHB masters on
the AHB bus are automatically converted to the serial memory read/write commands by HS_SPI.
This section describes the command sequencer mode of operation of HS_SPI.
18.5.1 Memory mapping
The command sequencer mode can be used for memory mapping of up to four serial Flash or serial
SRAM memory devices on the four slave select outputs of HS_SPI. All memory mapped devices
shall be of the same family.
In command sequencer mode, HS_SPI is allocated a memory space of 256 MBs, for mapping up to
four external memory devices. Each slave select can theoretically address a memory of up to
4 GB (i.e. 32-bit address bus) by using the address extension mechanism in command sequencer.
The address extension mechanism allows concatenation of the most significant bits from a 19-bit
Address Extension Register (i.e. GFXSPIn_CSAEXT register) with the few bits from the AHB address bus, to form a 32-bit address to be accessed on each slave select. This feature is explained
in detail in the subsequent sub sections of this chapter.
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High Speed SPI Interface (SPI)
Thus, the 256 MB of MCU address space is virtually mapped to 16 GB of external serial memory,
as shown in Figure 18-62:.
Figure 18-62: Mapping of memory devices on the slave select lines
MCU address map
HS_SPI memory base address
SSEL0
Up to 4 GB
SSEL1
256 MB
Up to 4 GB
For HS_SPI memory mapping
SSEL2
Up to 4 GB
HS_SPI CSR base address
1KB
For HS_SPI CSR
SSEL3
Up to 4 GB
Selection of slaves
The GFXSPIn_CSCFG.MSEL field indicates the size of the AHB address space associated with
each slave select line. Based on the value of GFXSPIn_CSCFG.MSEL field and the address placed
by the MCU (or the other AHB master, like the DMA controller) on the AHB address bus, HS_SPI
command sequencer decides which of the four slave select lines is asserted. For details refer to Figure 18-62:.
As an example, let us assume that the GFXSPIn_CSCFG.MSEL indicates that the AHB address
space associated with each slave select is of 8 KB. If the AHB address is between ‘HS_SPI memory
base address’ and ‘HS_SPI memory base address + 8 KB’, then slave select 0 is asserted. If the
AHB address is between ‘HS_SPI memory base address + 8 KB’ and ‘HS_SPI memory base address + 16 KB’, then slave select 1 is asserted, and so on. If the AHB address is beyond ‘HS_SPI
memory base address + 32 KB’, then the address is out of range and GFXSPIn_FAULTF.UMAFS
interrupt flag is set.
Generation of 32-bit memory address
The mapping of 256 MB of MCU address space to 4 GB of address space on a slave select line is
possible due to address extension mechanism. Every memory device can be visualized to be consisting of several memory banks. The size of each bank can be programmed in the
GFXSPIn_CSCFG.MSEL field. Each bank can be selected by changing the value in the
GFXSPIn_CSAEXT register. By reprogramming the GFXSPIn_CSAEXT register each time a new
bank in the selected slave is to be accessed, a memory device of upto 4 GB size can be addressed
through different banks.
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Refer to Figure 18-63:. It shows how each 4 GB device consists of 524288 banks when the
GFXSPIn_CSCFG.MSEL field is programmed to ‘0000’.
Figure 18-63: Addressing 4 GB devices on each slave select, through different banks
(GFXSPIn_CSCFG.MSEL = 0000)
GFXSPIn_CSAEXT.AEXT[31:13]
SSEL0 (4 GB)
19’b0000_0000_0000_0000_000
Bank # 000000
19’b0000_0000_0000_0000_001
Bank # 000001
19’b0000_0000_0000_0000_010
Bank # 000002
Bank # 000000
19’b0000_0000_0000_0000_011
Bank # 000003
Bank # 000001
SSEL1 (4 GB)
SSEL2 (4 GB)
Bank # 000002
Bank # 000000
Bank # 000003
Bank # 000001
Bank # 000002
Bank # 000003
SSEL3 (4 GB)
Bank # 000000
Bank # 000001
19’b1111_1111_1111_1111_100
Bank # 524284
19’b1111_1111_1111_1111_101
Bank # 524285
19’b1111_1111_1111_1111_110
Bank # 524286
Bank # 524284
19’b1111_1111_1111_1111_111
Bank # 524287
Bank # 524285
524288 Banks
of 8 KB Each
Bank # 524286
Bank # 524284
Bank # 524287
Bank # 524285
524288 Banks
of 8 KB Each
Bank # 524286
Bank # 000002
Bank # 000003
Bank # 524287
Bank # 524284
524288 Banks
of 8 KB Each
Bank # 524285
Bank # 524286
Bank # 524287
524288 Banks
of 8 KB Each
The least significant bits of the AHB address received by HS_SPI on the AHB bus are used as the
offset within the bank selected by the address extension bits.
The concatenation of the appropriate number of bits from the Address Extension Register with the
appropriate number of bits from the AHB address bus give the 32-bit address of the memory to be
accessed on the serial interface. Refer to Table 18.28-1
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Table 18-29: MCU address space to memory address mapping
GFXSPIn_CSCFG.
MSEL field
Size of a
memory bank
on each slave
select/size of
the AHB
address
range
associated
with each
slave select
0000
8 KB
0001
16 KB
0010
32 KB
AEXT[31:15]
HADDR[14:0]
0011
64 KB
AEXT[31:16]
HADDR[15:0]
0100
128 KB
AEXT[31:17]
HADDR[16:0]
0101
256 KB
AEXT[31:18]
HADDR[17:0]
0110
512 KB
AEXT[31:19]
HADDR[18:0]
0111
1MB
AEXT[31:20]
HADDR[19:0]
1000
2 MB
AEXT[31:21]
HADDR[20:0]
1001
4 MB
AEXT[31:22]
HADDR[21:0]
1010
8 MB
AEXT[31:23]
HADDR[22:0]
1011
16 MB
AEXT[31:24]
HADDR[23:0]
1100
32 MB
AEXT[31:25]
HADDR[24:0]
1101
64 MB
AEXT[31:26]
HADDR[25:0]
1110
128 MB
SSEL0 and SSEL1 only
AEXT[31:27]
HADDR[26:0]
1111
256 MB
SSEL0 only
AEXT[31:28]
HADDR[27:0]
Number of slave select
lines that can be
activated
SSEL0, SSEL1, SSEL2
and SSEL3
Number of bits
used from
GFXSPIn_CSA
EXT register,
for selection of
the memory
bank on a slave
select
Number of bits
used from AHB
address bus for
addressing the
memory
location within
a bank
AEXT[31:13]
HADDR[12:0]
AEXT[31:14]
HADDR[13:0]
Last two columns in Figure 18-62: indicate which bits from GFXSPIn_CSAEXT.AEXT and the AHB
address bus (i.e. HADDR) are concatenated, to get the final 32-bit address of the serial memory.
Although the final memory address generated in this way is a 32-bit address, it must be noted, that
the software can choose the number of bytes (from this 32-bit address) to be sent to the serial memory device during the address phase of a memory read/write command sequence.
18.5.2 Initiation of command sequence
Whenever the command sequencer receives an AHB read access for the memory mapped serial
device, it initiates a corresponding memory read command on one of the four slave select lines, assembles the data it has received, and responds with the memory read data.
Similarly, if it receives an AHB write access for the memory mapped serial device, it initiates a corresponding memory write command on one of the four slave select lines and transmits the data to
be written, serially on the SDATA lines.
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While the HS_SPI initiates a memory read command and receives the read data from the serial
memory device, the AHB slave port of HS_SPI inserts wait states on the AHB bus. Similarly, wait
states are also inserted for serial memory write sequences.
HS_SPI keeps track of the previous address and the AHB transfer type issued by the AHB master.
If the new transaction address is not contiguous or if there is switch in the command (from read to
write or vice-versa), then a new command is issued on the serial interface.
18.5.3 AHB idle timeout
After a serial device is accessed in the command sequencer mode, HS_SPI keeps asserting the
slave select line even if the serial transaction is over. Within the time period defined by
GFXSPIn_CSITIME.ITIME field, if a new AHB transaction is detected on AHB which has an address
contiguous with the previous transaction and which has the same command (i.e. read/write), then
the HS_SPI continues with the same serial transfer instead of initiating a new command sequence
phase on the serial device, thus reducing the access time. If there are subsequent AHB accesses
to a non-consecutive memory address during the idle time or if the command (i.e. read/write) changes, then even before the idle-timer expires, HS_SPI de-asserts the slave select (indicating the termination of the current transfer) and initiates the fresh transfer. If there are no subsequent AHB
accesses to the consecutive memory address during the idle time, then after the idle timer expires,
HS_SPI de-asserts the slave select, indicating the termination of the transfer.
Thus, the GFXSPIn_CSITIME.ITIME field is used to enhance the overall performance of the memory-mapped accesses by continuing the previous serial transaction for a configurable period.
The unit of the time period defined by GFXSPIn_CSITIME.ITIME field is the time period of AHB
clock input.
18.5.4 Configuration of command sequence in CSR
Command sequencer supports memory read accesses. Optionally, if serial SRAM devices are
memory mapped, the write accesses by command sequencer can be enabled by setting
GFXSPIn_CSCFG.SRAM = 1.
The sequence of command phases (i.e. instruction-phase, address-phase and data-phase) generated by HS_SPI in command sequencer mode, on the SDATA lines is configured by the software
(during initialization of HS_SPI) in the CSR.
Generation of memory read command sequence
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For memory read transactions, the sequence of command phases can be configured in the list of
eight registers: GFXSPIn_RDCSDC0, GFXSPIn_RDCSDC1, GFXSPIn_RDCSDC2,
GFXSPIn_RDCSDC3, GFXSPIn_RDCSDC4, GFXSPIn_RDCSDC5, GFXSPIn_RDCSDC6, and
GFXSPIn_RDCSDC7. Each of the eight registers in the list is parsed, starting from the
GFXSPIn_RDCSDC0, up to the GFXSPIn_RDCSDC7. Refer to Figure 18-64:.
Figure 18-64: Memory read command sequence list
Order of parsing by command sequencer
Read Command sequence list
in CSR
GFXSPIn_RDCSDC0
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC1
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC2
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC3
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC4
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC5
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC6
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC7
RDCSDATA [7:0]
DEC
The GFXSPIn_RDCSDCO.DEC bit in each of these registers indicates whether the data byte (i.e.
RDCSDATA[2:0]) must be decoded (as shown in Table 18-23:), or whether the data byte in RDCSDATA[7:0] must be transmitted as it is.
.
Table 18-30: Decoding of the read command sequence list
GFXSPIn_R
DCSDCO.D
EC
RDCSDATA
[2:0]
Description
0
Don’t care
Transmit RDCSDATA[07:00] as it is
1
000
Transmit address bits [07:00] of the serial memory to be accessed
1
001
Transmit address bits [15:08] of the serial memory to be accessed
1
010
Transmit address bits [23:16] of the serial memory to be accessed
1
011
Transmit address bits [31:24] of the serial memory to be accessed
1
100
Tri-state the SDATA output lines, for one byte-time
1
111
End of list
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The command sequencer switches to data-read cycles if it gets ‘end of list’ or after the
GFXSPIn_RDCSDC7 register, whichever occurs earlier. During data read cycles, the serial data on
SDATA lines is sampled and the assembled data is returned to the AHB master, in response to its
AHB read transaction.
Generation of memory write command sequence
Memory write command sequences can be initiated by the command sequencer only if they are enabled, in GFXSPIn_CSCFG.SRAM bit.
For memory write transactions, the sequence of command phases can be configured in the list of
eight registers: GFXSPIn_WRCSDC0, GFXSPIn_WRCSDC1, GFXSPIn_WRCSDC2,
GFXSPIn_WRCSDC3, GFXSPIn_WRCSDC4, GFXSPIn_WRCSDC5, GFXSPIn_WRCSDC6, and
GFXSPIn_WRCSDC7. Each of the eight registers in the list is parsed, starting from the
GFXSPIn_WRCSDC0, up to the GFXSPIn_WRCSDC7. Refer to Figure 18-65:.
Figure 18-65: Memory write command sequence list
Order of parsing by command sequencer
Write command sequence list
in CSR
GFXSPIn_WRCSDC0
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC1
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC2
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC3
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC4
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC5
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC6
WRCSDATA [7:0]
DEC
GFXSPIn_WRCSDC7
WRCSDATA [7:0]
DEC
The GFXSPIn_RDCSDCO.DEC bit in each of these registers indicates whether the data byte (i.e.
WRCSDATA[2:0]) must be decoded (as shown in Table 18-30 on page 26), or whether the data
byte in WRCSDATA[7:0] must be transmitted as it is.
.
Table 18-31: Decoding of the write command sequence list
Description
GFXSPIn_
RDCSDCO.
DEC
WRCSDATA [2:0]
0
Don’t care
Transmit WRCSDATA[07:00] as it is
1
000
Transmit address bits [07:00] of the serial memory to be accessed
1
001
Transmit address bits [15:08] of the serial memory to be accessed
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Table 18-31: Decoding of the write command sequence list
Description
GFXSPIn_
RDCSDCO.
DEC
WRCSDATA [2:0]
1
010
Transmit address bits [23:16] of the serial memory to be accessed
1
011
Transmit address bits [31:24] of the serial memory to be accessed
1
100
Tri-state the SDATA output lines, for one byte-time
1
101
Irrespective of the shift-direction configured in
GFXSPIn_PCC0~3.SDIR bit, the transmission takes place in the
following order:
1
111

Transmit RDCSDATA[07:04] as-it-is. Transmit
direction of this data will depend on the value of
GFXSPIn_PCC0~3.SDIR bit.

Tri-state the SDATA output lines for 4 Bit-Times.
End of list
The command sequencer switches to data-write cycles if it gets ‘end of list’ or after the
GFXSPIn_WRCSDC7 register, whichever occurs earlier. During data write cycles, the parallel data
from the AHB write data bus (i.e. HWDATA) is serially transmitted over the SDATA lines, as per the
configured SPI protocol.
18.6 Address map of HS_SPI
The HS_SPI module is allocated 256 MB of MCU’s address space for memory mapping of the external serial memory devices, using command sequencer mode. An additional 1 KB of MCU’s address space is reserved for mapping the internal Configuration and Status registers (i.e. CSRs) of
HS_SPI. The address area allocated to HS_SPI is discussed in this section.
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18.6.1 Arrangement of HS_SPI address space in memory
Figure 18-66: shows the allocation of HS_SPI address space in the MCU’s address space.
Figure 18-66: Address map of HS_SPI
MCU address map
HS_SPI memory base address
256 MB
For HS_SPI Memory Mapping
HS_SPI CSR base address
1 KB
For CSR of HS_SPI
Allocation for memory mapped devices
The 256 MB of memory space, starting from ‘HS_SPI memory base address’ is reserved for memory
mapping of the external serial devices onto the MCU’s address space.
This space is used in command sequencer mode.
Allocation for CSRs
The 1 KB of memory space, starting from ‘HS_SPI CSR base address’ is reserved for memory mapping of the Configuration and Status registers of HS_SPI on to the MCU’s address space.
Table 18.32-1
18.7 Notes on using HS_SPI
This section is the ‘programmer’s guide’, which lists the usage notes for programming the HS_SPI
module. Programmers are supposed to read these guidelines before programming the HS_SPI
module.
18.7.1 General usage notes

Any serial transaction related parameters and control bits (e.g. selection of the attributes in the
GFXSPIn_PCC0~3 registers, switching between direct mode of operation and the command
sequencer mode of operation, switching between the master and slave mode of operation, etc)
shall not be changed while a transaction is in progress. Any such changes shall be performed
only after HS_SPI module is disabled (GFXSPIn_MCTRL.MEN = 0) and the current serial
transfer has ended (i.e. GFXSPIn_TXF.TSSRS = 1 or GFXSPIn_RXF.RSSRS = 1). To ensure
that the HS_SPI module has finished all its transfers the software can read the
GFXSPIn_DMSTATUS.TXACTIVE and the GFXSPIn_DMSTATUS.RXACTIVE bits
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
For mimicking the transfer protocols of certain Serial Flash Memory devices (like the devices
from winbond) in direct mode of operation, it would be necessary to transfer initial set of bytes
in legacy mode and then transfer the remaining sets of data bytes using the dual-bit or quad-bit
mode. Thus, in such cases, it might be necessary to change the GFXSPIn_DMTRP register
while a serial transfer is in progress (i.e. while one of the slave select lines: SSEL0~3 is
asserted). When the software has to re-program the GFXSPIn_DMTRP register while a serial
transfer has already started, it can do so after halting the current serial transfer (as explained
in Section Halting a transfer due to lack Of TX-DATA or due to lack of RX-FIFO space in
Section 18.4)

However, it is recommended that while the serial transfer has halted, the GFXSPIn_DMTRP
shall not be reprogrammed for switching from "TX-only legacy" to "RX-only legacy" mode and
vice-versa. Instead of halting the serial transfer for switching the transfer protocol from
"TX-only legacy" to "RX-only legacy, the software can program the GFXSPIn_DMTRP for "TX
and RX legacy" mode before the start of transfer and then ignore the bytes in the data received
while reception is not applicable, or transmit dummy data when transmission is not applicable

When direct mode of operation is used, the software shall be responsible to take care that the
internal FIFOs of HS_SPI do not get overrun or underrun. In case the FIFOs get overrun or
underrun, the FIFO fill-levels (i.e. GFXSPIn_DMSTATUS.TXFLEVEL and
GFXSPIn_DMSTATUS.RXFLEVEL) are no longer pertinent and the software would have to
flush the FIFOs

The GFXSPIn_FIFOCFG.RXFLSH and GFXSPIn_FIFOCFG.TXFLSH bits shall be used by the
software to flush the corresponding FIFOs before using them for any serial transfer. Flushing a
FIFO ensures that they are not pre-loaded with any garbage data (possibly from the previous
transfer)

In direct mode, master operation, whenever the transfer ends, the data from the RX shift
register is pushed into the RX-FIFO; provided that the RX-FIFO is not full.
 If the RX FIFO is already full while a serial transfer is terminating, the serial transfer halts
and the remainder data remains in the RX shift register as long as HS_SPI is halted. As
soon as the RX FIFO is not full anymore, HS_SPI comes out of the halt state and the
remainder data from the RX shift register is pushed into the RX-FIFO before HS_SPI
releases the slave select line. The remainder data is pushed into the RX-FIFO irrespective
of whether the RX shift register is filled completely or partially
 Thus, in direct mode, master operation, remainder data never remains in the RX shift
register. The bit-count from the GFXSPIn_RXBITCNT register is always 0 and the received
data is always pushed into the RX-FIFO

18 - 30
In direct mode, slave operation, when the transfer stops, the last data received by HS_SPI,
which is not yet pushed into the RX-FIFO remains in the RX shift register. The software shall
read the remainder data from the GFXSPIn_RXSHIFT register and the bit-count from the
GFXSPIn_RXBITCNT register
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
18.7.2 Steps in programming the HS_SPI module
Figure 18-67: gives the general steps a programmer shall follow while using the HS_SPI module.
Figure 18-67: Programmer’s flowchart: general steps
System reset
1.
Read module ID
2.
Configure the peripheral
communication attributes
3.
Configure the mode-specific
options
4.
Enable the HS_SPI module
operation
5.
Keep monitoring the status
&
process the service requests
After the system reset, the software shall detect the module ID number of HS_SPI, by reading the
GFXSPIn_MID register. This would help it in identifying the attributes and capabilities supported by
the HS_SPI module.
1. The next step is to configure the attributes related to the peripheral communication with the serial device(s) connected with HS_SPI. In master mode, HS_SPI can be interfaced with up to four
serial devices. In slave mode, HS_SPI can respond to the serial transactions initiated by a single
master device. Serial communication related attributes like clock polarity, clock phase, transfer
frequency (i.e. clock division ratio and clock source selection bits), slave select polarity, etc.
shall be configured in the registers: GFXSPIn_PCC0, GFXSPIn_PCC1, GFXSPIn_PCC2, and
GFXSPIn_PCC3. It is very important that these attributes shall be the same as being used by
the remote serial device with which HS_SPI is serially interfaced. These configurations shall not
be modified while the HS_SPI module is active. In case the software has to re-program the values, the software shall first disable the HS_SPI module and wait until the current serial transfer
is finished.
2. HS_SPI can be configured either in direct mode, or in command sequencer mode through the
GFXSPIn_MCTRL.CSEN bit. Depending on which mode is to be used, the software shall configure the mode-specific registers. The registers specific to the direct mode are:
(GFXSPIn_TXF,
GFXSPIn_TXE,
GFXSPIn_TXC,
GFXSPIn_RXE,
GFXSPIn_RXF,
GFXSPIn_RXE,
GFXSPIn_RXC,
GFXSPIn_DMCFG,
GFXSPIn_DMSTATUS,
GFXSPIn_RXSHIFT,
GFXSPIn_TXFIFO0~15,
GFXSPIn_RXFIFO0~15,
and
GFXSPIn_FIFOCFG) and the registers specific to the command sequencer mode are:
(GFXSPIn_CSCFG, GFXSPIn_CSITIME, GFXSPIn_CSAEXT, GFXSPIn_RDCSDC0 GFXSPIn_RDCSDC7, and GFXSPIn_WRCSDC0 - GFXSPIn_WRCSDC7).
3. Only after all module-specific configurations are programmed, the HS_SPI module shall be enabled (by setting the GFXSPIn_MCTRL.MEN to 1).
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High Speed SPI Interface (SPI)
4. Once the HS_SPI module is enabled, its normal working begins. The software shall keep monitoring the status of the HS_SPI module using the various status bits. If the HS_SPI module is
configured for initiating the service requests, it would periodically trigger the service requests
(i.e. Interrupts and/or DMA requests). The software would service those requests, in order to
ensure the normal working of HS_SPI.
18.7.3 Using the HS_SPI in direct mode of operation
Master mode
Figure Figure 18-68: gives the general steps a programmer shall follow while using the HS_SPI
module as a master in direct mode of operation.
Figure 18-68: Programmer’s flowchart: HS_SPI as a master, in direct mode of operation
1.
Initialization
2.
Program the transfer protocol
3.
Program the HS_SPI in master mode
4.
Program the slave-select deassertion method
5.
Program the FIFO threshold levels
5.
Program the FIFO width
6.
Enable the interrupt/DMA service requests
7.
Enable the HS_SPI module operation
8.
Select the peripheral for communication
9.
Write the data to the TX-FIFO
10.
Trigger the start of serial transfer
11. Write data to TX-FIFO/read data from RX-FIFO
12.
Yes
SSDC = 1?
12.a1
Set the STOP bit,
wait for TSSRS/RSSRS
12.a2
If reception is enabled,
read RX-FIFO
If reception is enabled,
read RX-FIFO
Transfer count
is enough?
Done
12.a3
Yes
Done
18 - 32
No
Wait for GFXSPIn_DMBCS = 0 12.b1
12.b2
No
Launch recovery
Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
After the system reset, the software shall initialize the HS_SPI module by reading the
GFXSPIn_MID register and setting the peripheral communication related attributes in the
GFXSPIn_PCC0, GFXSPIn_PCC1n, GFXSPIn_PCC2n, and GFXSPIn_PCC3 registers. It is very
important that these attributes shall be the same as being used by the remote serial device with
which HS_SPI is serially interfaced. Ensure that the GFXSPIn_MCTRL.CSEN bit is reset to ‘0’.
1. The next step is to configure the transfer protocol (i.e. whether the HS_SPI serial transfers use
the legacy, dual-bit or the quad-bit SPI protocol and whether the HS_SPI would be used only
for transmission, or only for reception or for both: transmission and reception) in the
GFXSPIn_DMTRP.TRP field.
2. The next step is to set the GFXSPIn_DMCFG.MST bit, which decides whether HS_SPI is to be
used as a slave device or a master device.
3. Configure its GFXSPIn_DMCFG.SSDC field. This selects how the slave select output is to be
de asserted. If byte-counter mode is used, load the GFXSPIn_DMBCC.BCC field with the number of bytes to be serially transferred. If the software flow control is used, the software is responsible to set the GFXSPIn_DMSTOP.STOP bit after it has finished transmission/reception of the
desired data.
4. Configure the GFXSPIn_FIFOCFG register, to set the FIFO threshold levels. By programming
these levels, the assertion of the service requests can be controlled. Also configure the
GFXSPIn_FIFOCFG.FWIDTH field, to select the width of the FIFOs.
5. Configure the service requests. HS_SPI supports both: Interrupt and DMA service requests, for
the normal data read/write operations from/to the internal FIFOs. For normal operation, either
the interrupt requests or the DMA requests shall be enabled by the software. To enable the interrupt service requests for TX-FIFO write requests, please program the bits in the
GFXSPIn_TXE register. To enable the interrupt service requests for RX-FIFO read requests,
please program the bits in the GFXSPIn_RXE register. To enable the DMA read and/or DMA
write service requests, program either/both of the GFXSPIn_DMDMAEN.TXDMAEN and the
GFXSPIn_DMDMAEN.RXDMAEN bits. The DMA read channel must be setup to perform a
block transfer of "GFXSPIn_FIFOCFG.RXFTH + 1" transfers. The DMA write channel must be
setup to perform a block transfer of "16 - GFXSPIn_FIFOCFG.TXFTH" transfers.
6. This finishes the steps in initialization of HS_SPI for direct mode of operation. Set the
GFXSPIn_MCTRL.MEN bit, to enable the module.
7. Select the peripheral (in GFXSPIn_DMPSEL.PSEL field) on which HS_SPI shall initiate the
transfer.
8. If HS_SPI is configured for TX-only or TX-and-RX mode of operation (in
GFXSPIn_DMTRP.TRP field), then write the data to be transmitted in the TX-FIFO by performing write accesses to the GFXSPIn_TXFIFO0~15 register address. Before writing to the
GFXSPIn_TXFIFO0~15 register, modify the value of the GFXSPIn_FIFOCFG.TXCTRL field
appropriately. Generally (i.e when the data being written to the TX-FIFO is to be transmitted as
it is), the GFXSPIn_FIFOCFG.TXCTRL bit shall be reset to ‘0’. Only when HS_SPI is to be instructed to tri-state the serial data lines for a byte-time or for 4 bit-times, the
GFXSPIn_FIFOCFG.TXCTRL bit shall be set to ‘1’ and a GFXSPIn_TXFIFO0~15 write access
shall be performed.
9. When HS_SPI is configured as a master, setting the GFXSPIn_DMSTART.START bit triggers
the start of the serial transaction.
Once the serial transaction starts, if transmission is enabled in the GFXSPIn_DMTRP.TRP field, the
HS_SPI reads the TX-FIFO and loads the shift-register. The shift-register is shifted either left or right
(based on configuration in GFXSPIn_PCC0~3.SDIR field and the transmit data is shifted-out onto
the serial line(s). If HS_SPI is enabled for receive operation (in GFXSPIn_DMTRP.TRP field), the
HS_SPI assembles the received data by serially shifting the received data into the shift register. The
received data assembled in the shift register is shifted into the RX-FIFO.
1. Service requests are asserted by HS_SPI whenever the TX-FIFO level is below the threshold
or whenever the HS_SPI RX-FIFO level is above the threshold. The software shall read/write
the FIFOs, to ensure normal operation of HS_SPI. Once processed, the interrupt service requests shall be cleared by the software in the GFXSPIn_TXC or the GFXSPIn_RXC registers.
DMA service requests are automatically cleared by HS_SPI.
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High Speed SPI Interface (SPI)
2. For stopping the serial transfers, the software can use either of the two modes (configured in
GFXSPIn_DMCFG.SSDC bit) - software flow control mode or the byte counter mode.
In software flow control mode
12.a.i)
In software flow control mode, software waits till either of the GFXSPIn_TXF.TSSRS
or the GFXSPIn_RXF.RSSRS flag is set, indicating that the slave select is released.
12.a.ii)
If reception is enabled in GFXSPIn_DMTRP register, then the software fetches the
received data from the RX-FIFO.
12.a.iii)
If the number of byte of data transferred using the software flow control mode is not
enough, then the software launhces its own recovery.
In byte counter mode
12.b.i)
In byte counter mode, software waits till the GFXSPIn_DMBCS register value
becomes 0.
12.b.ii)
If reception is enabled in GFXSPIn_DMTRP register, then the software fetches the
received data from the RX-FIFO.
1. In the normal course of action, the software usually keeps repeating steps from 9 to 12, or it can
loop back to the initialization step.
2. To switch between the direct mode of operation to the command sequencer mode, or to re-program any of the parameters that directly affect the serial transfer, the software shall first stop
the current transfer and disable the HS_SPI module. Only after it is ensured that the HS_SPI
module has finished all its transfers (by reading the GFXSPIn_DMSTATUS.TXACTIVE and the
GFXSPIn_DMSTATUS.RXACTIVE bits), the software can reconfigure the module.
Slave mode
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Fujitsu Semiconductor Europe GmbH
High Speed SPI Interface (SPI)
Revised 24/7/13
Figure 18-69: gives the general steps a programmer shall follow while using the HS_SPI module as
a slave in direct mode of operation.
Figure 18-69: Programmer’s flowchart: HS_SPI as a slave, in direct mode of operation
1.
Initialization
2.
Program the transfer protocol
3.
Program the HS_SPI as a slave
4.
Program the FIFO threshold levels
4.
Program the FIFO width
5.
Enable the Interrupt/DMA service requests
6.
Enable the HS_SPI module operation
7.
Write the data to the TX-FIFO
8.
Wait for assertion of SSEL0
Write data to TX-FIFO/
read data from RX-FIFO
9., 10.
11.
SSEL0 is de asserted by master
12.
If reception is enabled,
read remaining data from RX-FIFO
No
13.
13.a
Bit count is
zero?
Yes
If reception is enabled,
read GFXSPIn_RXSHIFT
14.
No
Done
RXFIFO overflow/
TX-FIFO underflow?
Yes
Launch recovery
After the system reset, the software shall initialize the HS_SPI module by reading the
GFXSPIn_MID register and setting the peripheral communication related attributes in the
GFXSPIn_PCC0 register. It is very important that these attributes shall be the same as being used
by the remote serial device with which HS_SPI is serially interfaced. Ensure that the
GFXSPIn_MCTRL.CSEN bit is reset to ‘0’.
1. The next step is to configure the transfer protocol (i.e. whether the HS_SPI serial transfers use
the legacy, dual-bit or the quad-bit SPI protocol and whether the HS_SPI would be used only
for transmission, or only for reception or for both: transmission and reception) in the
GFXSPIn_DMTRP.TRP field.
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High Speed SPI Interface (SPI)
2. The next step is to program the GFXSPIn_DMCFG.MST bit, which decides whether HS_SPI n
is to be used as a slave device or a master device. If HS_SPI is to be used as a slave, it would
respond only on the serial transfers initiated by the external master, on it’s SSEL0 input. Therefore, when using HS_SPI in slave mode, only the peripheral communication attributes in
GFXSPIn_PCC0 register are used by HS_SPI.
3. Configure the GFXSPIn_FIFOCFG register, to set the FIFO threshold levels. By programming
these levels, the assertion of the service requests can be controlled. Also configure the
GFXSPIn_FIFOCFG.FWIDTH field, to select the width of the FIFOs.
4. Configure the service requests. HS_SPI supports both: Interrupt and DMA service requests, for
the normal data read/write operations from/to the internal FIFOs. For normal operation, either
the interrupt requests or the DMA requests shall be enabled by the software. To enable the interrupt service requests for TX-FIFO write requests, please program the bits in the
GFXSPIn_TXE register. To enable the interrupt service requests for RX-FIFO read requests,
please program the bits in the GFXSPIn_RXE register. To enable the DMA read and/or DMA
write service requests, program either/both of the GFXSPIn_DMDMAEN.TXDMAEN and the
GFXSPIn_DMDMAEN.RXDMAEN bits. The DMA read channel must be setup to perform a
block transfer of "GFXSPIn_FIFOCFG.RXFTH + 1" transfers. The DMA write channel must be
setup to perform a block transfer of "16 - GFXSPIn_FIFOCFG.TXFTH" transfers.
5. This finishes the steps in initialization of HS_SPI for direct mode of operation. Set the
GFXSPIn_MCTRL.MEN bit, to enable the module.
6. If HS_SPI is configured for TX-only or TX-and-RX mode of operation (in
GFXSPIn_DMTRP.TRP field), then write the data to be transmitted in the TX-FIFO by performing write accesses to the GFXSPIn_TXFIFO0~15 register address. Before writing to the
GFXSPIn_TXFIFO0~15 register, modify the value of the GFXSPIn_FIFOCFG.TXCTRL field
appropriately. Generally (i.e when the data being written to the TX-FIFO is to be transmitted as
it is), the GFXSPIn_FIFOCFG.TXCTRL bit shall be reset to ‘0’. Only when HS_SPI is to be instructed to tri-state the serial data lines for a byte-time or for 4-bit times, the
GFXSPIn_FIFOCFG.TXCTRL bit shall be set to ‘1’ and a GFXSPIn_TXFIFO0~15 write access
shall be performed.
7. When HS_SPI is configured as a slave, HS_SPI waits for the remote master to assert its SSEL0
input.
8. Once the serial transaction starts, if transmission is enabled in the GFXSPIn_DMTRP.TRP field,
the HS_SPI reads the TX-FIFO and loads the shift-register. The shift register is shifted either
left or right (based on configuration in GFXSPIn_PCC0~3.SDIR field and the transmit data is
shifted-out onto the serial line(s). If HS_SPI is enabled for receive operation (in
GFXSPIn_DMTRP.TRP field), the HS_SPI assembles the received data by serially shifting the
received data into the shift register. The received data assembled in the shift register is shifted
into the RX-FIFO.
9. Service requests are asserted by HS_SPI whenever the TX-FIFO level is below the threshold
or whenever the HS_SPI RX-FIFO level is above the threshold. The software shall read/write
the FIFOs, to ensure normal operation of HS_SPI. Once processed, the interrupt service requests shall be cleared by the software in the GFXSPIn_TXC or the GFXSPIn_RXC registers.
DMA service requests are automatically cleared by HS_SPI.
10. In case of slave operation, the remote master deasserts the slave select, to indicate end of the
transfer.
11. If reception is enabled, software shall read the received data from the RX-FIFO.
12. In slave mode of operation, when the transfer stops, the remainder data received by HS_SPI,
which is not yet pushed into the RX-FIFO remains in the RX shift register and the number of bits
valid in the RX shift register is indicated by the RX bit count register. Therefore, the software
shall read the GFXSPIn_RXBITCNT register, if reception is enabled.
13. If the value in GFXSPIn_RXBITCNT is non-zero, the software shall read the remainder data
from the GFXSPIn_RXSHIFT register.
14. In slave mode, the software shall take care that the RX-FIFO does not overflow and that the
TX-FIFO does not underrun. If the RX-FIFO overflows or the TX-FIFO underruns, the software
shall launch its recovery operation.
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High Speed SPI Interface (SPI)
Revised 24/7/13
15. In the normal course of action, the software usually keeps repeating steps from 8 to 14, or it can
loop back to the initialization step.
16. To switch between the direct mode of operation to the command sequencer mode ( note, that
in this case, switching to command sequencer mode also involves switching from slave mode
of operation to master-mode of operation), or to re-program any of the parameters that directly
affect the serial transfer, the software shall first stop the current transfer, disable the HS_SPI
module. Only after it is ensured that the HS_SPI module has finished all its transfers (by reading
the GFXSPIn_DMSTATUS.TXACTIVE and the GFXSPIn_DMSTATUS.RXACTIVE bits), the
software should reconfigure the module.
18.7.4 Using the memory mapped memories
Following usage rules shall be followed, when interfacing serial memories, for memory-mapped accesses in command sequencer mode.
Usage rules and notes

In command sequencer mode, all serial memory devices interfaced with HS_SPI shall be of
same family. Do not mix serial memory devices from different vendor families

If memory devices of same family, but with different memory sizes are to be interfaced, then
while deciding the suitable value of the GFXSPIn_CSCFG.MSEL field, the memory device with
maximum size must be considered. However, it shall be noted here, that the number of bytes
from the final memory address that will be transmitted by HS_SPI to the serial
memory-mapped device is programmed in the command sequence lists (in
GFXSPIn_RDCSDC0~7 and GFXSPIn_WRCSDC0~7 registers). Interfacing of one memory
device which requires 32-bit addressing and other memory device (also of same family, but)
which requires only 24-bit addressing in command sequencer mode is not possible. This is
because a memory device which has 24-bit addressing cannot be used with a bit-stuffed 32-bit
address - its address phase is of 3 cycles only

If a memory device only needs 21-bit addressing, and if the command sequence in HS_SPI is
configured to transmit a 24-bit address to the memory device, then the three most significant
bits [23:21] shall be bit-stuffed with 0s (using the GFXSPIn_CSAEXT register) by the software.
If the unused most significant bits are not reset to 0s, then the address pointers in the serial
memory devices interfaced with HS_SPI might wrap, causing unwanted results.

Serial SRAM devices support burst-operation only when they are configured to work in burst
mode. However, the command sequencer always assumes that the SRAM device is in burst
mode. Before enabling the command sequencer mode of HS_SPI, the software shall configure
the serial SRAM device (using direct mode of operation), for burst mode of operation

In command sequencer mode, it is not possible to change between the legacy, dual-bit or
quad-bit modes when a transfer has started. For this reason, for some of the new serial flash
devices - like the memory devices from winbond, the command sequencer can be enabled
only after the device has been initialized to work in the ‘continuous read mode’. The memory
device can be programmed in the continuous read mode, using the direct mode of operation of
HS_SPI.
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High Speed SPI Interface (SPI)
18.7.5 Programmer’s flowchart
Figure Figure 18-70: gives the general steps a programmer shall follow while using the HS_SPI for
memory mapping the serial memory devices onto the address space of MCU.
Figure 18-70: Programmer’s flowchart: memory mapping of serial memory devices
1.
Initialization of HS_SPI
2.
Initialization of the serial memory device(s)
(using direct mode)
3.
Switch to command sequencer mode
4.
Configure the transfer protocol
5.
Program whether memory-writes are allowed
6.
Configure the size of memory device
7.
Program the address extension bits
8.
Program the idle timeout period
9.
Program the read command sequence list
10.
Program the write command sequence list
(If memory-writes are enabled)
11.
Enable the HS_SPI module
Access the memories by performing
memory read/write accesses.
After the system reset, the software shall initialize the HS_SPI module by setting the peripheral communication related attributes in the GFXSPIn_PCC0, GFXSPIn_PCC1n, GFXSPIn_PCC2n, and
GFXSPIn_PCC3 registers. It is very important that these attributes shall be the same as being used
by the remote serial device with which HS_SPI is serially interfaced. When serial memory devices
are to be memory mapped using command sequencer mode, all memory devices shall be of same
family. Therefore, all four Peripheral Communication Configuration Registers (i.e
GFXSPIn_PCC0~3) shall have same configuration values.
1. The next step is to initialize the serial device that is to be memory mapped. The initialization is
device specific and it may include setting of some control/status bits in its register set. e.g. to
use a quad-SPI serial memory device, you might want to set the device in a high-performance
(i.e. quad mode). Consult the data sheet of the serial memory device to be interfaced. This initialization of the serial memory device shall be performed using direct mode of HS_SPI.
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Revised 24/7/13
2. After initializing the serial device (using direct mode of operation), re-program the HS_SPI module in the command sequencer mode. To switch from the direct mode of operation to the command sequencer mode, the software shall first stop the current transfer and disable the HS_SPI
module. Only after it is ensured that the HS_SPI module has finished all its transfers (by reading
the GFXSPIn_DMSTATUS.TXACTIVE and the GFXSPIn_DMSTATUS.RXACTIVE bits), the
software can reconfigure the module to command sequencer mode.
3. The next step is to configure the transfer protocol (i.e. whether the HS_SPI serial transfers use
the legacy, dual-bit or the quad-bit SPI protocol in the GFXSPIn_CSCFG.MBM field.
4. If serial SRAM devices are connected, you might want to enable the write accesses to these
memory-mapped devices, using the GFXSPIn_CSCFG.SRAM bit. If serial flash devices are
connected, do not enable the write accesses.
5. Program the GFXSPIn_CSCFG.MSEL field, with the size of the AHB address space which must
be used in selection of the memory device on which the serial transfer must be initiated. For
details of the Slave Selection logic refer to Section 18.5.
6. If the addresses generated for the memory-mapped accesses are to be virtually extended to
cover a memory range of virtually 16 GB, you might have to program the GFXSPIn_CSAEXT
register. For details of address generation refer to Section 18.5.
7. The GFXSPIn_CSITIME.ITIME field is used to enhance the overall performance of the memory-mapped accesses by continuing the previous serial transaction for a configurable period. If
there is an access (of same type: i.e. read/write) to the consecutive memory address, HS_SPI
proceeds with the same serial transfer (without having to issue a new command/address cycles), thus reducing the access time. Program the GFXSPIn_CSITIME.ITIME with appropriate
idle time-out value.
8. Program the list of Read Command Sequence Register (i.e. GFXSPIn_RDCSDC0,
GFXSPIn_RDCSDC1, GFXSPIn_RDCSDC2, GFXSPIn_RDCSDC3, GFXSPIn_RDCSDC4,
GFXSPIn_RDCSDC5, GFXSPIn_RDCSDC6, and GFXSPIn_RDCSDC7) with the sequence of
the memory read command for the memory device you have interfaced. Consult with the device-specific data sheet for details of the read command sequence.
9. If memory-write accesses are also enabled in GFXSPIn_CSCFG.SRAM bit, then you also need
to program the list of Write Command Sequence Register (i.e. GFXSPIn_WRCSDC0,
GFXSPIn_WRCSDC1,
GFXSPIn_WRCSDC2,
GFXSPIn_WRDCSDC3n,
GFXSPIn_WRCSDC4,
GFXSPIn_WRCSDC5,
GFXSPIn_WRCSDC6,
and GFXSPIn_WRCSDC7) with the sequence of the memory write command for the memory
device you have interfaced. Consult with the device-specific data sheet for details of the write
command sequence.
10. With this, you have configured the HS_SPI module for accessing the memory-mapped devices.
Enable the HS_SPI module (in GFXSPIn_MCTRL.MEN bit), so that it starts generating the
read/write sequences on the serial interface, by mapping the AHB accesses to the memory-mapped locations.
18.7.6 Timing diagram for command sequencer
Figure 18-71: illustrates with an example, how the command sequencer generates the serial memory read command sequence. Let us assume, that the read command sequence list is programmed
in GFXSPIn_RDCSDC0 through GFXSPIn_RDCS5 registers, as shown in the figure. The command
sequencer parses the list, starting from GFXSPIn_RDCS0 register, and executes the commands as
explained in Section 18.5.
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High Speed SPI Interface (SPI)
Figure 18-71: shows the corresponding timing diagram for a read command sequence, for a clocking mode of ‘0’.
Figure 18-71: Read command sequence illustration with timing diagram (mode-0)
Order of Parsing by Command Sequencer
Read command sequence list
in CSR
RDCSDATA [7:0]
DEC
GFXSPIn_RDCSDC0
(0000 1011)
0
Instruction: high-speed read
GFXSPIn_RDCSDC1
xxxx x010
1
Memory address [24:16]
GFXSPIn_RDCSDC2
xxxx x001
1
Memory address [15:08]
GFXSPIn_RDCSDC3
xxxx x000
1
Memory address [07:00]
GFXSPIn_RDCSDC4
xxxx x100
1
High-Z byte
GFXSPIn_RDCSDC5
xxxx x111
1
End of list
GFXSPIn_RDCSDC6
xxxx xxxx
x
Unused
GFXSPIn_RDCSDC7
xxxx xxxx
x
Unused
i.e. 0x0B
SS2CD
Delay
SSELx
0
1
2
3
4
5
6
7
C1
C0
A5
A4
A3
A2
A1
A0
8
9
10 11 12 13 14 15 16 17
SCLK
iSDATA [3:0]
Command Address Cycles (3-bytes)
cycle
Hi-Z Hi-Z H0
Dummy
cycle
L0
H1
L1
H2
L2
H3
L3 H4
Read-data Cycles (4-bytes)
I/O switches from output to input
(data is captured on falling edges of SCLK)
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Register Overview
Revised 24/7/13
Chapter 19: Register Overview
Lock/Unlock register (GFXGCTR_LockUnlock) ...................................................................................20 - 6
Lock Status register (GFXGCTR_LockStatus) .....................................................................................20 - 7
Interrupt Status 0 register (GFXGCTR_IntStatus0) ..............................................................................20 - 8
Interrupt Status 1 register (GFXGCTR_IntStatus1) ..............................................................................20 - 9
Interrupt Enable 0 register (GFXGCTR_IntEnable0) ..........................................................................20 - 10
Interrupt Enable 1 register (GFXGCTR_IntEnable1) ..........................................................................20 - 11
Interrupt Clear 0 register (GFXGCTR_IntClear0) ...............................................................................20 - 12
Interrupt Clear 1 register (GFXGCTR_IntClear1) ...............................................................................20 - 13
Interrupt Preset 0 register (GFXGCTR_IntPreset0) ...........................................................................20 - 14
Interrupt Preset 1 register (GFXGCTR_IntPreset1) ...........................................................................20 - 15
Interrupt Mapping 0 register (GFXGCTR_IntMap0) ...........................................................................20 - 16
Interrupt Mapping 1 register (GFXGCTR_IntMap1) ...........................................................................20 - 17
NMI Status register (GFXGCTR_NmiStatus) .....................................................................................20 - 18
NMI Clear register (GFXGCTR_NmiClear) ........................................................................................20 - 19
NMI Preset register (GFXGCTR_NmiPreset) .....................................................................................20 - 20
Command Sequencer Interrupt Status 0 register (GFXGCTR_CsIntStatus0) ...................................20 - 21
Command Sequencer Interrupt Status 1 register (GFXGCTR_CsIntStatus1) ...................................20 - 22
Command Sequencer Interrupt Enable 0 register (GFXGCTR_CsIntEnable0) .................................20 - 23
Command Sequencer Interrupt Enable 1 register (GFXGCTR_CsIntEnable1) .................................20 - 24
Command Sequencer Interrupt Clear 0 register (GFXGCTR_CsIntClear0) .......................................20 - 25
Command Sequencer Interrupt Clear 1 register (GFXGCTR_CsIntClear1) .......................................20 - 26
Command Sequencer Interrupt Preset 0 register (GFXGCTR_CsIntPreset0) ...................................20 - 27
Command Sequencer Interrupt Preset 1 register (GFXGCTR_CsIntPreset1) ...................................20 - 28
Software Reset register (GFXGCTR_SwReset) .................................................................................20 - 29
Clock Adjust register (GFXGCTR_ClockAdjust) .................................................................................20 - 30
Error Monitor Status register (GFXAIC_Status) .................................................................................20 - 32
Error Monitor Control register (GFXAIC_Control) ...............................................................................20 - 34
Monitor Disable register (GFXAIC_MonitorDisable) ...........................................................................20 - 35
Slave Disable register (GFXAIC_SlaveDisable) .................................................................................20 - 36
MSS A Read Arbitration register (GFXHPM_MSSARarbitration) .......................................................20 - 38
MSS A Write Arbitration register (GFXHPM_MSSAWarbitration) ......................................................20 - 39
VRAM0 A Read Arbitration register (GFXHPM_Vram0ARarbitration) ...............................................20 - 40
VRAM0 A Write Arbitration register (GFXHPM_Vram0AWarbitration) ...............................................20 - 41
AHB A Read Arbitration register (GFXHPM_AHBARarbitration) ........................................................20 - 42
AHB A Write Arbitration register (GFXHPM_AHBAWarbitration) .......................................................20 - 43
High-Performance Matrix A Read Arbitration register (GFXHPM_HPMARarbitration) ......................20 - 44
High-Performance Matrix A Write Arbitration register (GFXHPM_HPMAWarbitration) ......................20 - 45
Pixelbus Configuration for fetch0 unit register (GFXPIX_fetch0_cfg) .................................................20 - 46
Pixelbus Configuration for fetch1 unit register (GFXPIX_fetch1_cfg) .................................................20 - 47
Pixelbus Configuration for fetch2 unit register (GFXPIX_fetch2_cfg) .................................................20 - 48
Pixelbus Configuration for fetch3 unit register (GFXPIX_fetch3_cfg) .................................................20 - 49
Pixelbus Configuration for fetch4 unit register (GFXPIX_fetch4_cfg) .................................................20 - 50
Pixelbus Configuration for fetch5 unit register (GFXPIX_fetch5_cfg) .................................................20 - 51
Pixelbus Configuration for fetch6 unit register (GFXPIX_fetch6_cfg) .................................................20 - 52
Pixelbus Configuration for fetch7 unit register (GFXPIX_fetch7_cfg) .................................................20 - 53
Pixelbus Configuration for store0 unit register (GFXPIX_store0_cfg) ................................................20 - 54
Pixelbus Configuration for rop0 unit register (GFXPIX_rop0_cfg) ......................................................20 - 56
Pixelbus Configuration for rop1 unit register (GFXPIX_rop1_cfg) ......................................................20 - 58
Pixelbus Configuration for blitblend0 unit register (GFXPIX_blitblend0_cfg) .....................................20 - 60
Pixelbus Configuration for layerblend0 unit register (GFXPIX_layerblend0_cfg) ...............................20 - 62
Pixelbus Configuration for layerblend1 unit register (GFXPIX_layerblend1_cfg) ...............................20 - 64
Pixelbus Configuration for layerblend2 unit register (GFXPIX_layerblend2_cfg) ...............................20 - 66
Pixelbus Configuration for lut0 unit register (GFXPIX_lut0_cfg) .........................................................20 - 68
Pixelbus Configuration for lut1 unit register (GFXPIX_lut1_cfg) .........................................................20 - 70
Pixelbus Configuration for matrix0 unit register (GFXPIX_matrix0_cfg) .............................................20 - 72
Pixelbus Configuration for extdst0 unit register (GFXPIX_extdst0_cfg) .............................................20 - 74
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Register Overview
Pixelbus Store0 Sync register (GFXPIX_STORE0_SYNC) ...............................................................20 - 76
Pixelbus Store0 Sync Status register (GFXPIX_STORE0_SYNC_STAT) .........................................20 - 78
Pixelbus Extdst0 Sync register (GFXPIX_EXTDST0_SYNC) ............................................................20 - 80
Pixelbus Extdst0 Sync Status register (GFXPIX_EXTDST0_SYNC_STAT) ......................................20 - 82
Store0 Unit Clock Throttling register (GFXPIX_STORE0_CLK) .........................................................20 - 84
Extdst0 Unit Clock Throttling register (GFXPIX_EXTDST0_CLK) .....................................................20 - 85
Pixel Engine Blitblend Control register (GFXPIX_blend0_Control) ....................................................20 - 86
Pixel Engine Blitblend Constant Color register (GFXPIX_blend0_ConstantColor) ............................20 - 87
Pixel Engine Blitblend OpenGL Red Function register (GFXPIX_blend0_ColorRedBlendFunction) .20 - 88
Pixel Engine Blitblend OpenGL Green Function register (GFXPIX_blend0_ColorGreenBlendFunction) 20 91
Pixel Engine Blitblend OpenGL Blue Function register (GFXPIX_blend0_ColorBlueBlendFunction) 20 - 94
Pixel Engine Blitblend OpenGL Alpha Function register (GFXPIX_blend0_ColorAlphaBlendFunction) .20 97
Pixel Engine Blitblend OpenGL/VG Blending Modes register (GFXPIX_blend0_BlendMode1) .......20 - 100
Pixel Engine Blitblend OpenGL/VG Blending Modes register (GFXPIX_blend0_BlendMode2) .......20 - 103
Pixel Engine Blitblend Primary Control Word register (GFXPIX_blend0_PRIM_CONTROL_WORD) ....20 106
Pixel Engine Blitblend Secondary Control Word register (GFXPIX_blend0_SEC_CONTROL_WORD) .20 107
Pixel Engine CLUT Control register (GFXPIX_clut<n>_Control) ......................................................20 - 108
Pixel Engine CLUT LUT registers (GFXPIX_clut<n>_LUT[0 ... 255]) ..............................................20 - 110
Pixel Engine ExtDst Control register (GFXPIX_extdst0_CONTROL) ...............................................20 - 111
Pixel Engine ExtDst Status register (GFXPIX_extdst0_STATUS) ...................................................20 - 112
Pixel Engine ExtDst Control Word register (GFXPIX_extdst0_CONTROL_WORD) ........................20 - 113
Pixel Engine ExtDst Current Pixel register (GFXPIX_extdst0_CUR_PIXEL_CNT) ..........................20 - 114
Pixel Engine ExtDst Last Pixel register (GFXPIX_extdst0_LAST_PIXEL_CNT) ..............................20 - 115
Pixel Engine Fetch Status register (GFXPIX_fetch<n>_Status) .......................................................20 - 116
Pixel Engine Fetch Burst Buffer Management register (GFXPIX_fetch<n>_BurstBufferManagement) ..20 117
Pixel Engine Fetch Base Address register (GFXPIX_fetch<n>_BaseAddress) ...............................20 - 118
Pixel Engine Fetch Source Buffer Stride register (GFXPIX_fetch<n>_SourceBufferStride) ............20 - 119
Pixel Engine Fetch Source Buffer Attributes register (GFXPIX_fetch<n>_SourceBufferAttributes) .20 - 120
Pixel Engine Fetch Source Buffer Length register (GFXPIX_fetch<n>_SourceBufferLength) .........20 - 121
Pixel Engine Fetch Frame X Offset register (GFXPIX_fetch<n>_FrameXOffset) ............................20 - 122
Pixel Engine Fetch Frame Y Offset register (GFXPIX_fetch<n>_FrameYOffset) ............................20 - 123
Pixel Engine Fetch Frame Dimensions register (GFXPIX_fetch<n>_FrameDimensions) ................20 - 124
Pixel Engine Fetch DeltaXX register (GFXPIX_fetch<n>_DeltaXX) .................................................20 - 125
Pixel Engine Fetch DeltaXY register (GFXPIX_fetch<n>_DeltaXY) .................................................20 - 126
Pixel Engine Fetch DeltaYX register (GFXPIX_fetch<n>_DeltaYX) .................................................20 - 127
Pixel Engine Fetch DeltaYY register (GFXPIX_fetch<n>_DeltaYY) .................................................20 - 128
Pixel Engine Fetch Skip Window Offset register (GFXPIX_fetch<n>_SkipWindowOffset) ..............20 - 129
Pixel Engine Fetch Skip Window Dimensions register (GFXPIX_fetch<n>_SkipWindowDimensions) ...20 130
Pixel Engine Fetch Color Component Bits register (GFXPIX_fetch<n>_ColorComponentBits) .......20 - 131
Pixel Engine Fetch Color Component Shift register (GFXPIX_fetch<n>_ColorComponentShift) ....20 - 132
Pixel Engine Fetch Constant Color register (GFXPIX_fetch<n>_ConstantColor) ............................20 - 133
Pixel Engine Fetch Control register (GFXPIX_fetch<n>_Control) ....................................................20 - 134
Pixel Engine Layerblend Control register (GFXPIX_layerblend<n>_CONTROL) ............................20 - 137
Pixel Engine Layerblend Position register (GFXPIX_layerblend<n>_POSITION) ...........................20 - 140
Pixel Engine Layerblend Transparent Color register (GFXPIX_layerblend<n>_TRANS_COL) .......20 - 141
Pixel Engine Layerblend Primary Control Word register
(GFXPIX_layerblend<n>_PRIM_CONTROL_WORD) .....................................................................20 - 142
Pixel Engine Layerblend Primary Control Word register
(GFXPIX_layerblend<n>_SEC_CONTROL_WORD) .......................................................................20 - 143
Pixel Engine Color Matrix Control register (GFXPIX_matrix0_CONTROL) ......................................20 - 144
Pixel Engine Color Matrix RED0 register (GFXPIX_matrix0_RED0) ................................................20 - 145
Pixel Engine Color Matrix RED1 register (GFXPIX_matrix0_RED1) ................................................20 - 146
Pixel Engine Color Matrix GREEN0 register (GFXPIX_matrix0_GREEN0) .....................................20 - 147
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Register Overview
Revised 24/7/13
Pixel Engine Color Matrix GREEN1 register (GFXPIX_matrix0_GREEN1) .....................................20 - 148
Pixel Engine Color Matrix BLUE0 register (GFXPIX_matrix0_BLUE0) ............................................20 - 149
Pixel Engine Color Matrix BLUE1 register (GFXPIX_matrix0_BLUE1) ............................................20 - 150
Pixel Engine ROP Control register (GFXPIX_rop<n>_Control) ........................................................20 - 151
Pixel Engine ROP Raster Operation Indices register (GFXPIX_rop<n>_RasterOperationIndices) .20 - 152
Pixel Engine ROP Primary Control Word register (GFXPIX_rop<n>_PRIM_CONTROL_WORD) ..20 - 153
Pixel Engine ROP Secondary Control Word register (GFXPIX_rop<n>_SEC_CONTROL_WORD) 20 - 154
Pixel Engine ROP Tertiary Control Word register (GFXPIX_rop<n>_TERT_CONTROL_WORD) ..20 - 155
Pixel Engine Store Unit Status register (GFXPIX_store0_Status) ....................................................20 - 156
Pixel Engine Store Unit Last Control Word register (GFXPIX_store0_LAST_CONTROL_WORD) .20 - 157
Pixel Engine Store Unit Burst Buffer Management register (GFXPIX_store0_BurstBufferManagement) .20
- 158
Pixel Engine Store Unit Base Address register (GFXPIX_store0_BaseAddress) ............................20 - 159
Pixel Engine Store Unit Destination Buffer Stride register (GFXPIX_store0_DestinationBufferStride) ...20 160
Pixel Engine Store Unit Frame X Offset register (GFXPIX_store0_FrameXOffset) .........................20 - 161
Pixel Engine Store Unit Frame Y Offset register (GFXPIX_store0_FrameYOffset) .........................20 - 162
Pixel Engine Store Unit Color Component Bits register (GFXPIX_store0_ColorComponentBits) ....20 - 163
Pixel Engine Store Unit Color Component Shift register (GFXPIX_store0_ColorComponentShift) .20 - 164
Pixel Engine Store Unit Control register (GFXPIX_store0_Control) .................................................20 - 165
Pixel Engine Store Unit Performance Counter register (GFXPIX_store0_PerfCounter) ..................20 - 167
Signature Unit Lock/Unlock register (GFXSIG_LockUnlock) ............................................................20 - 168
Signature Unit Lock Status register (GFXSIG_SigLockStatus) ........................................................20 - 169
Signature Unit Software reset register (GFXSIG_SigSWreset) ........................................................20 - 170
Signature Unit General Configuration register (GFXSIG_SigCtrl) ....................................................20 - 171
Mask horizontal co-ordinates Upper left register (GFXSIG_MaskHorizontalUpperLeft) ..................20 - 173
Mask horizontal co-ordinates Lower Right register (GFXSIG_MaskHorizontalLowerRight) ............20 - 174
Mask vertical co-ordinates Upper left register (GFXSIG_MaskVerticalUpperLeft) ...........................20 - 175
Mask vertical co-ordinates Lower Right register (GFXSIG_MaskVerticalLowerRight) .....................20 - 176
Evaluation Window horizontal co-ordinates Upper left register (GFXSIG_HorizontalUpperLeftW0) 20 - 177
Evaluation Window horizontal co-ordinates Lower Right register (GFXSIG_HorizontalLowerRightW0) .20 178
Evaluation Window vertical co-ordinates Upper Left register (GFXSIG_VerticalUpperLeftW0) .......20 - 179
Evaluation Window vertical co-ordinates Lower Right register (GFXSIG_VerticalLowerRightW0) ..20 - 180
Signature A Reference Value Channel R register (GFXSIG_SignAReferenceRW0) .......................20 - 181
Signature A Reference Value Channel G register (GFXSIG_SignAReferenceGW0) ......................20 - 182
Signature A Reference Value Channel B register (GFXSIG_SignAReferenceBW0) .......................20 - 183
Signature B Reference Value Channel R register (GFXSIG_SignBReferenceRW0) .......................20 - 184
Signature B Reference Value Channel G register (GFXSIG_SignBReferenceGW0) ......................20 - 185
Signature B Reference Value Channel B register (GFXSIG_SignBReferenceBW0) .......................20 - 186
Threshold Signature B Channel R register (GFXSIG_ThrBRW0) ....................................................20 - 187
Threshold Signature B Channel G register (GFXSIG_ThrBGW0) ....................................................20 - 188
Threshold Signature B Channel B register (GFXSIG_ThrBBW0) ....................................................20 - 189
Error Counter Threshold register (GFXSIG_ErrorThreshold) ...........................................................20 - 190
Evaluation Windows Control and Configuration register (GFXSIG_CtrlCfgW0) ...............................20 - 191
Trigger register (GFXSIG_TriggerW0) .............................................................................................20 - 192
Interrupt Enable register (GFXSIG_IENW0) .....................................................................................20 - 193
Interrupt Status register (GFXSIG_InterruptStatusW0) ....................................................................20 - 194
Status register (GFXSIG_StatusW0) ................................................................................................20 - 195
Video Frame Signature Error Count register (GFXSIG_Signature_error) ........................................20 - 197
Signature A Result for Channel R register (GFXSIG_SignatureARW0) ...........................................20 - 198
Signature A Result for Channel G register (GFXSIG_SignatureAGW0) ..........................................20 - 199
Signature A Result for Channel B register (GFXSIG_SignatureABW0) ...........................................20 - 200
Signature B Result for Channel R register (GFXSIG_SignatureARW0) ...........................................20 - 201
Signature B Result for Channel G register (GFXSIG_SignatureBGW0) ..........................................20 - 202
Signature B Result for Channel B register (GFXSIG_SignatureBBW0) ...........................................20 - 203
Display Controller Enable register (GFXDISP_DisplayEnable) ........................................................20 - 204
Display Controller Resolution register (GFXDISP_DisplayResolution) ............................................20 - 205
Active Display Area Configuration register (GFXDISP_DisplayActiveArea) .....................................20 - 206
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Register Overview
Horizontal Synchronization Timing Configuration register (GFXDISP_HorizontalSynchTimingConf) .....20 207
Vertical Synchronization Timing Configuration register (GFXDISP_VerticalSynchTimingConf) ......20 - 208
Display Controller Miscellaneous Configuration register (GFXDISP_DisplayConf) .........................20 - 209
Pixel Engine Trigger Point register (GFXDISP_PixEngTrig) ............................................................20 - 210
Dither Unit Control register (GFXDISP_DitherControl) .....................................................................20 - 211
Trigger Point Coordinates for INT0 register (GFXDISP_INT0Trigger) .............................................20 - 213
Trigger Point Coordinates for INT1 register (GFXDISP_INT1Trigger) .............................................20 - 214
Trigger Point Coordinates for INT2 register (GFXDISP_INT2Trigger) .............................................20 - 215
Debug register (GFXDISP_Debug) ..................................................................................................20 - 216
Sequencer Position Definitions registers (GFXTCON_DIR_SSqCnts[0...63]) .................................20 - 217
Timing Controller Software Reset register (GFXTCON_DIR_SWreset) ...........................................20 - 218
Sequencer Pulse Generator [0...11] On Position register (GFXTCON_DIR_SPG[0...11]PosOn) ....20 - 219
Sequencer Pulse Generator [0...11] Mask Enable register (GFXTCON_DIR_SPG[0...11]MaskOn) 20 - 220
Sequencer Pulse Generator [0...11] Off Position register (GFXTCON_DIR_SPG[0...11]PosOff) ....20 - 221
Sequencer Pulse Generator [0...11] Mask Enable register (GFXTCON_DIR_SPG[0...11]MaskOff) 20 - 222
Sequencer Cycle Length register (GFXTCON_DIR_SSqCycle) ......................................................20 - 223
Sync Mixer [0...11] Signal Selection register (GFXTCON_DIR_SMx[0...11]Sigs) ............................20 - 224
Sync Mixer [0...11] Function Table Selection register (GFXTCON_DIR_SMx[0...11]FctTable) .......20 - 226
Sync Switch register (GFXTCON_DIR_SSwitch) .............................................................................20 - 227
RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL) .......................................................20 - 228
IO Module Internal Pad [0...11] Control register (GFXTCON_DIR_PINx[0...11]_CTRL) ..................20 - 230
Module Internal Pad 12 Control register (GFXTCON_DIR_PIN12_CTRL) ......................................20 - 233
Command Sequencer Command Input Buffer registers (GFXCMD_HIF[0:63]) ...............................20 - 236
Command Sequencer Status register (GFXCMD_Status) ...............................................................20 - 237
Command Sequencer Control register (GFXCMD_Control) ............................................................20 - 238
Command Sequencer Buffer Address register (GFXCMD_BufferAddress) .....................................20 - 239
Command Sequencer Buffer Size register (GFXCMD_BufferSize) .................................................20 - 240
Command Sequencer Watermark Control register (GFXCMD_WatermarkControl) ........................20 - 241
HS_SPI Module Control Register (GFXSPIn_MCTRL) ....................................................................20 - 242
HS_SPI Peripheral Communication Configuration Register 0~3 (GFXSPIn_PCC0~3) ...................20 - 244
HS_SPI TX Interrupt Flag Register (GFXSPIn_TXF) .......................................................................20 - 247
HS_SPI TX Interrupt Enable Register (GFXSPIn_TXE) ...................................................................20 - 249
HS_SPI TX Interrupt Clear Register (GFXSPIn_TXC) .....................................................................20 - 251
HS_SPI RX Interrupt Flag Register (GFXSPIn_RXF) ......................................................................20 - 253
HS_SPI RX Interrupt Enable Register (GFXSPIn_RXE) ..................................................................20 - 255
HS_SPI RX Interrupt Clear Register (GFXSPIn_RXC) ....................................................................20 - 257
HS_SPI Fault Interrupt Flag Register (GFXSPIn_FAULTF) .............................................................20 - 259
HS_SPI Fault Interrupt Clear Register (GFXSPIn_FAULTC) ...........................................................20 - 261
HS_SPI Direct Mode Configuration Register (GFXSPIn_DMCFG) ..................................................20 - 263
HS_SPI Direct Mode DMA Enable Register (GFXSPIn_DMDMAEN) ..............................................20 - 265
HS_SPI Direct Mode Start Register (GFXSPIn_DMSTART) ...........................................................20 - 266
HS_SPI Direct Mode Stop Register (GFXSPIn_DMSTOP) ..............................................................20 - 267
HS_SPI Direct Mode Peripheral Select Register (GFXSPIn_DMPSEL) ..........................................20 - 268
HS_SPI Direct Mode Transfer Protocol Register (GFXSPIn_DMTRP) ............................................20 - 269
HS_SPI Direct Mode Byte Count Control Register (GFXSPIn_DMBCC) .........................................20 - 270
HS_SPI Direct Mode Byte Count Status Register (GFXSPIn_DMBCS) ..........................................20 - 271
HS_SPI Direct Mode Status Register (GFXSPIn_DMSTATUS) ......................................................20 - 272
HS_SPI Transmit Bit Count Register (GFXSPIn_TXBITCNT) .........................................................20 - 273
HS_SPI Receive Bit Count Register (GFXSPIn_RXBITCNT) ..........................................................20 - 274
HS_SPI RX Shift Register (GFXSPIn_RXSHIFT) ............................................................................20 - 275
HS_SPI TX-FIFO Registers (GFXSPIn_TXFIFO0~15) ....................................................................20 - 276
HS_SPI RX-FIFO Registers (GFXSPIn_RXFIFO0~15) ...................................................................20 - 277
HS_SPI FIFO Configuration Register (GFXSPIn_FIFOCFG) ..........................................................20 - 279
HS_SPI Command Sequencer Configuration Register (GFXSPIn_CSCFG) ...................................20 - 281
HS_SPI Command Sequencer Idle Time Register (GFXSPIn_CSITIME) .......................................20 - 283
HS_SPI Command Sequencer Address Extension Register (GFXSPIn_CSAEXT) ........................20 - 284
HS_SPI Read Command Sequence Data/Control Register 0~7 (GFXSPIn_RDCSDC0~7) ............20 - 285
HS_SPI Write Command Sequence Data/Control Register 0~7 (GFXSPIn_WRCSDC0~7) ...........20 - 287
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Register Overview
Revised 24/7/13
HS_SPI Module ID Register (GFXSPIn_MID) ..................................................................................20 - 289
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Register Overview
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Iris-SDL Register Descriptions
Revised 24/7/13
Chapter 20: Iris-SDL Register Descriptions
If a specific submodule has more than one instance in the chip (e.g. a fetch unit) then a related register is referred to either specifically:
GFXPIX_fetch0_RegName
i.e. this register is only for the fetch0 unit, or generally:
GFXPIX_fetch<n>_RegName
i.e. this means for both fetch0 and fetch1 submodules. the <n> then refers to all the instances.
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Iris-SDL Register Descriptions
20.1 Register Descriptions, Global Addresses
Format of Register Description
The register descriptions in this manual use the format shown below to describe each bit(field).
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
<R/W>
< Field Name >
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
< Name of register >
< Reset value >
Meaning of items and sign
Name of Register
The name of the register as referred to in this document.
Please note that the names of some registers can be quite long and that the prefix may be omitted
for better readability (however, within the context of the description it will be clear which register or
bitfield is being referred to).
Bit number (31 ... 0]
Bit number shows bit position of the bit(field).
Field name
Field name shows bit name of the register.
R/W
R/W shows the read/write attribute of each bitfield:
 R: Read
 W: Write
 RWS: Read + Write, Shadowed bit(field)
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Iris-SDL Register Descriptions
Revised 24/7/13
Reset value
Reset value indicates the value of each bit field immediately after reset.
 0:Initial value is "0".
 1:Initial value is "1".
 X:Undefined.
Bit vectors are unsigned integers, if nothing else specified.
Please note, that access to an address other than those listed for the registers results in an error
response.
Global Address
For module base addresses refer to the global address map.
Register Address
For register addresses please refer to the “Register Overview” (which is hyperlinked in the PDF version
of this document).
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Iris-SDL Register Descriptions
20.2 Iris-SDL Register Protection (Locking/Unlocking)
The register interface of the Global Control Unit contains a protection mechanism. Before the register contents of specific registers of the Global Control Unit can be changed, the register interface
must first be unlocked. This is realized by writing a 32-bit unlock key into the “Lock/Unlock register
(GFXGCTR_LockUnlock)”. After the registers have been written, the register block can be re-protected by writing the lock key to the GFXGCTR_LockUnlock register. The register block is protected
after a reset. Writing to a protected register will incur an AHB error response.
The following keys are used to lock/unlock register access:
Action
Key to Use
Lock GFXGCTR_xxxx registers (listed below)
D15AB1E0
Unlock GFXGCTR_xxxx registers (listed below)
7E1ECA57
Lock GFXSIG_xxxx registers (all)
AB10C834
Unlock GFXSIG_xxxx registers (all)
A1ACC384
The following table lists which selected registers can be locked/unlocked.
Register Name
GFXGCTR_LockUnlock
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Protected by
Locking
Description
lock/unlock key Lock / Unlock Register.
GFXGCTR_LockStatus
no
Lock Status Register.
GFXGCTR_IntStatus0
no
Interrupt Status Register 0. Shows the status of
the interrupts (Read Only).
GFXGCTR_IntStatus1
no
Interrupt Status Register 1. Shows the status of
the interrupts (Read Only).
GFXGCTR_IntEnable0
no
Interrupt Enable Register 0 for interrupts bits.
GFXGCTR_IntEnable1
no
Interrupt Enable Register 1 for interrupts bits.
GFXGCTR_IntClear0
no
Interrupt Clear Register 0 for interrupt bits.
GFXGCTR_IntClear1
no
Interrupt Clear Register 1 for interrupt bits.
GFXGCTR_IntPreset0
no
Interrupt Preset Register 1 for interrupt bits.
GFXGCTR_IntPreset1
no
Interrupt Preset Register 1 for interrupt bits.
GFXGCTR_IntMap0
no
Interrupt Mapping Register 0 for interrupt bits.
GFXGCTR_IntMap1
no
Interrupt Mapping Register 1 for interrupt bits.
GFXGCTR_NmiStatus
yes
NMI Status Register. Shows the status of NMI
(Read Only).
GFXGCTR_NmiClear
yes
NMI Clear Register. Clears NMI.
GFXGCTR_NmiPreset
yes
NMI Preset Register. Presets NMI.
GFXGCTR_CsIntStatus0
no
Command Sequencer Interrupt Status Register 0.
Shows the status of the interrupts (Read Only).
GFXGCTR_CsIntStatus1
no
Command Sequencer Interrupt Status Register 1.
Shows the status of the interrupts (Read Only).
GFXGCTR_CsIntEnable0
no
Command Sequencer Interrupt Enable Register 0
for interrupts bits.
GFXGCTR_CsIntEnable1
no
Command Sequencer Interrupt Enable Register 1
for interrupts bits.
GFXGCTR_CsIntClear0
no
Command Sequencer Interrupt Clear Register 0
for interrupt bits.
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Iris-SDL Register Descriptions
Revised 24/7/13
GFXGCTR_CsIntClear1
no
Command Sequencer Interrupt Clear Register 1
for interrupt bits.
GFXGCTR_CsIntPreset0
no
Command Sequencer Interrupt Preset Register 1
for interrupt bits.
GFXGCTR_CsIntPreset1
no
Command Sequencer Interrupt Preset Register 1
for interrupt bits.
GFXGCTR_SwReset
yes
Software Reset Register.
GFXGCTR_ClockAdjust
yes
Clock Adjust Register.
GFXSIG_xxxx
yes
ALL GFXSIG_xxxx registers
Fujitsu Semiconductor Europe GmbH
20 - 5
Revised 24/7/13
20.3
Iris-SDL Register Descriptions
Lock/Unlock register (GFXGCTR_LockUnlock)
The Lock/Unlock register is a protection mechanism for selected configuration registers of the Iris-SDL
Global Control unit. A 32-bit unlock key must be written to this register before Global Control register
contents can be changed.
Figure 20-1: Lock/Unlock register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
12
0
0
13
0
11
14
0
0
15
0
16
0
W
Lock/Unlock
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
31
0
GFXGCTR_LockUnlock
Table 20-1: Lock/Unlock register bits
Bit position
Bit name
Description
[31:0]
GFXGCTR_L
ockUnlock
The register interface of the Global Control Unit contains a protection
mechanism. The register interface must be unlocked before specific
register contents of the Global Control Unit can be changed. This is done
by writing the 32-bit Global Control unlock key in the
GFXGCTR_LockUnlock register. After registers have been written to, the
register block can be re-protected by writing the 32-bit Global Control lock
key to the GFXGCTR_LockUnlock register. After reset, the register block
is protected.
An attempt to write to a locked (protected) register envokes an AHB error
response. See also:
20.28 Error Monitor Status register (GFXAIC_Status)
20.29 Error Monitor Control register (GFXAIC_Control)
20.30 Monitor Disable register (GFXAIC_MonitorDisable)
Note:
A seperate lock/unlock mechanism also exists for the Signature Unit
configuration registers (this is controlled by seperate registers).
20 - 6
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
20.4
Revised 24/7/13
Lock Status register (GFXGCTR_LockStatus)
The Lock Status register reads back the locked/unlocked status of the selected Global Control configuration registers.
Figure 20-2: Lock Status register
09
08
07
06
05
04
03
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
LockStatus
R
Description
Read back the locked/unlocked status of the selected Global Control
configuration registers from this bit.
0:
Unlocked
1:
Locked
Fujitsu Semiconductor Europe GmbH
20 - 7
1
0
Reserved
0
Table 20-2: Lock Status register bits
Bit position
00
10
0
01
11
0
LockStatus
12
0
0
13
0
02
14
0
0
15
0
16
17
22
0
Reserved
23
0
0
24
0
18
25
0
19
26
0
0
27
0
0
28
0
20
29
0
0
30
0
21
31
0
GFXGCTR_LockStatus
Revised 24/7/13
20.5
Iris-SDL Register Descriptions
Interrupt Status 0 register (GFXGCTR_IntStatus0)
The Interrupt Status 0 register shows the status of Iris-SDL interrupt signals.
Figure 20-3: Interrupt Status 0 register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
0
14
0
15
16
17
0
IntStatus0
18
23
0
19
24
0
0
25
0
0
26
0
20
27
0
0
28
0
21
29
0
22
30
0
0
R
0
0
0
0
Reserved
Reserved
31
GFXGCTR_IntStatus0
Table 20-3: Interrupt Status 0 register bits
Bit position
Bit name
31
Reserved
[30:0]
IntStatus0
20 - 8
Description
Each of the 31 read-only bits reflects the status of individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is inactive
1:
Interrupt is active
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
20.6
Revised 24/7/13
Interrupt Status 1 register (GFXGCTR_IntStatus1)
The Interrupt Status 1 register shows the status of Iris-SDL interrupt signals.
Figure 20-4: Interrupt Status 1 register
08
07
06
05
04
0
0
0
0
0
00
09
0
01
10
0
0
11
0
0
12
0
02
13
0
0
14
0
R
0
0
Resrved
0
0
0
03
15
0
IntStatus1
16
0
17
23
0
0
24
0
18
25
0
19
26
0
0
27
0
20
28
0
Reserved
29
0
21
30
0
22
31
0
GFXGCTR_IntStatus1
Table 20-4: Interrupt Status 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
IntStatus1
Description
Each of the 7 read-only bits reflects the status of individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is inactive
1:
Interrupt is active
Fujitsu Semiconductor Europe GmbH
20 - 9
Revised 24/7/13
20.7
Iris-SDL Register Descriptions
Interrupt Enable 0 register (GFXGCTR_IntEnable0)
The Interrupt Enable 0 register enables or disables Iris-SDL interrupt signals.
Figure 20-5: Interrupt Enable 0 register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
0
14
0
15
16
17
0
IntEnable0
18
23
0
19
24
0
0
25
0
0
26
0
20
27
0
0
28
0
21
29
0
22
30
0
0
RW
0
0
0
0
Reserved
Reserved
31
GFXGCTR_IntEnable0
Table 20-5: Interrupt Enable 0 register bits
Bit position
Bit name
31
Reserved
[30:0]
IntEnable0
20 - 10
Description
Each of the 31 read-write bits enables or disables individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is disabled
1:
Interrupt is enabled
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
20.8
Revised 24/7/13
Interrupt Enable 1 register (GFXGCTR_IntEnable1)
The Interrupt Enable 1 register enables or disables Iris-SDL interrupt signals.
Figure 20-6: Interrupt Enable 1 register
08
07
06
05
04
0
0
0
0
0
00
09
0
01
10
0
0
11
0
0
12
0
02
13
0
0
14
0
RW
0
0
Resrved
0
0
0
03
15
0
IntEnable1
16
0
17
23
0
0
24
0
18
25
0
19
26
0
0
27
0
20
28
0
Reserved
29
0
21
30
0
22
31
0
GFXGCTR_IntEnable1
Table 20-6: Interrupt Enable 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
IntEnable1
Description
Each of the 7 read-write bits enables or disables individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is disabled
1:
Interrupt is enabled
Fujitsu Semiconductor Europe GmbH
20 - 11
Revised 24/7/13
20.9
Iris-SDL Register Descriptions
Interrupt Clear 0 register (GFXGCTR_IntClear0)
The Interrupt Clear 0 register clears the Iris-SDL interrupt signal bits.
Figure 20-7: Interrupt Clear 0 register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
RW
Reserved
IntClear0
11
14
0
0
15
0
12
16
0
0
17
0
13
18
0
19
0
23
0
0
24
0
20
25
0
0
26
0
21
27
0
0
28
0
22
29
0
30
0
Reserved
31
0
GFXGCTR_IntClear0
Table 20-7: Interrupt Clear 0 register bits
Bit position
Bit name
[31:28]
Reserved
[27:0]
IntClear0
Description
Each of the 28 read-write bits clears an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
20 - 12
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.10 Interrupt Clear 1 register (GFXGCTR_IntClear1)
The Interrupt Clear 1 register clears the Iris-SDL interrupt signal bits.
Figure 20-8: Interrupt Clear 1 register
11
10
09
08
07
06
05
04
0
0
0
0
0
0
0
0
IntClear1
00
12
0
01
13
0
0
14
0
0
15
0
02
16
0
0
17
0
RW
0
0
Reserved
0
03
18
23
0
19
24
0
0
25
0
20
26
0
Reserved
27
0
0
28
0
21
29
0
0
30
0
22
31
0
GFXGCTR_IntClear1
Table 20-8: Interrupt Clear 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
IntClear1
Description
Each of the 7 read-write bits clears an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
Fujitsu Semiconductor Europe GmbH
20 - 13
Revised 24/7/13
Iris-SDL Register Descriptions
20.11 Interrupt Preset 0 register (GFXGCTR_IntPreset0)
The Interrupt Preset 0 register presets the Iris-SDL interrupt signal bits.
Figure 20-9: Interrupt Preset 0 register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
14
0
12
15
0
0
16
0
13
17
0
IntPreset0
18
0
19
0
23
0
0
24
0
20
25
0
0
26
0
21
27
0
0
28
0
22
29
0
30
0
0
RW
Reserved
Reserved
31
0
GFXGCTR_IntPreset0
Table 20-9: Interrupt Preset 0 register bits
Bit position
Bit name
[31:28]
Reserved
[27:0]
IntPreset0
Description
Each of the 28 read-write bits presets an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to preset the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
20 - 14
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.12 Interrupt Preset 1 register (GFXGCTR_IntPreset1)
The Interrupt Preset 1 register presets the Iris-SDL interrupt signal bits.
Figure 20-10: Interrupt Preset 1 register
09
08
07
06
05
04
0
0
0
0
0
0
00
10
0
01
11
0
0
12
0
0
13
0
02
14
0
0
15
0
0
RW
Reserved
0
03
16
0
IntPreset1
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
20
27
0
Reserved
28
0
0
29
0
21
30
0
0
31
0
GFXGCTR_IntPreset1
Table 20-10: Interrupt Preset 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
IntPreset1
Description
Each of the 7 read-write bits presets an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to preset the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
Fujitsu Semiconductor Europe GmbH
20 - 15
Revised 24/7/13
Iris-SDL Register Descriptions
20.13 Interrupt Mapping 0 register (GFXGCTR_IntMap0)
The Interrupt Mapping 0 register maps Iris-SDL interrupt signals to the interrupt 0 or interrupt 1 pin.
Figure 20-11: Interrupt Mapping 0 register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
0
14
0
IntMap0
0
0
0
RW
Reserved
0
15
16
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
Reserved
31
GFXGCTR_IntMap0
Table 20-11: Interrupt Mapping 0 register bits
Bit position
Bit name
31
Reserved
[30:0]
IntMap0
20 - 16
Description
Each of the 31 read-write bits maps individual interrupts to either the
interrupt 0 or interrupt 1 pin.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is mapped to the interrupt 0 pin.
1:
Interrupt is mapped to the interrupt 1 pin.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.14 Interrupt Mapping 1 register (GFXGCTR_IntMap1)
The Interrupt Mapping 1 register maps Iris-SDL interrupt signals to the interrupt 0 or interrupt 1 pin.
Figure 20-12: Interrupt Mapping 1 register
09
08
07
06
05
04
0
0
0
0
0
0
IntMap1
00
10
0
01
11
0
0
12
0
0
13
0
02
14
0
0
15
0
RW
0
0
Reserved
0
0
03
16
22
0
0
23
0
17
24
0
0
25
0
18
26
0
19
27
0
0
28
0
20
29
0
Reserved
30
0
21
31
0
GFXGCTR_IntMap1
Table 20-12: Interrupt Mapping 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
IntMap1
Description
Each of the 7 read-write bits maps individual interrupts to either the
interrupt 0 or interrupt 1 pin.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is mapped to the interrupt 0 pin.
1:
Interrupt is mapped to the interrupt 1 pin.
Fujitsu Semiconductor Europe GmbH
20 - 17
Revised 24/7/13
Iris-SDL Register Descriptions
20.15 NMI Status register (GFXGCTR_NmiStatus)
The NMI Status register shows the NMI (Non-Maskable Interrupt) status of Iris-SDL.
Figure 20-13: NMI Status register
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
NmiStatus
20 - 18
R
Description
The read-only bit reflects the NMI status of Iris-SDL.
Check also: Iris-SDL Interrupts section.
0:
NMI is inactive
1:
NMI is active
Fujitsu Semiconductor Europe GmbH
0
0
Reserved
0
Table 20-13: NMI Status register bits
Bit position
00
09
NmiStatus
10
0
12
0
0
13
0
11
14
0
0
15
0
16
17
22
0
Reserved
23
0
0
24
0
18
25
0
19
26
0
0
27
0
0
28
0
20
29
0
0
30
0
21
31
0
GFXGCTR_NmiStatus
Iris-SDL Register Descriptions
Revised 24/7/13
20.16 NMI Clear register (GFXGCTR_NmiClear)
The NMI Clear register clears the NMI (Non-Maskable Interrupt) status of Iris-SDL.
Figure 20-14: NMI Clear register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
NmiClear
NmiClear
RW
Description
The read-write bit is used to clear the NMI status of Iris-SDL.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the NMI.
Writing a 0 has no effect.
The read value of the bits is always 0.
Fujitsu Semiconductor Europe GmbH
20 - 19
0
0
Reserved
Table 20-14: NMI Clear register bits
Bit position
00
15
0
16
17
Reserved
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
31
0
GFXGCTR_NmiClear
Revised 24/7/13
Iris-SDL Register Descriptions
20.17 NMI Preset register (GFXGCTR_NmiPreset)
The NMI Preset register presets the NMI (Non-Maskable Interrupt) status of Iris-SDL.
Figure 20-15: NMI Preset register
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
NmiPreset
RW
Description
The read-write bit is used to preset the NMI status of Iris-SDL.
Check also: Iris-SDL Interrupts section.
Write a 1 to preset the NMI.
Writing a 0 has no effect.
The read value of the bits is always 0.
20 - 20
Fujitsu Semiconductor Europe GmbH
0
0
Table 20-15: NMI Preset register bits
Bit position
00
09
NmiPreset
10
0
12
0
0
13
0
11
14
0
0
15
0
16
17
Reserved
Reserved
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
31
0
GFXGCTR_NmiPreset
Iris-SDL Register Descriptions
Revised 24/7/13
20.18 Command Sequencer Interrupt Status 0 register
(GFXGCTR_CsIntStatus0)
The Command Sequencer Interrupt Status 0 register shows the status of the Command Sequencer interrupt signals.
Figure 20-16: Command Sequencer Interrupt Status 0 register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
17
0
16
18
0
CsIntStatus0
19
0
22
0
20
23
0
0
24
0
21
25
27
0
0
28
0
26
29
0
0
30
0
0
R
0
0
0
Reserved
Reserved
31
GFXGCTR_CsIntStatus0
Table 20-16: Command Sequencer Interrupt Status 0 register bits
Bit position
Bit name
31
Reserved
[30:0]
CsIntStatus0
Description
Each of the 31 read-only bits shows the status of the individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is inactive
1:
Interrupt is active
Fujitsu Semiconductor Europe GmbH
20 - 21
Revised 24/7/13
Iris-SDL Register Descriptions
20.19 Command Sequencer Interrupt Status 1 register
(GFXGCTR_CsIntStatus1)
The Command Sequencer Interrupt Status 1 register shows the status of the Command Sequencer interrupt signals.
Figure 20-17: Command Sequencer Interrupt Status 1 register
01
00
04
0
0
05
0
0
06
0
02
07
0
0
08
0
R
0
0
Reserved
0
0
03
09
CsIntStatus1
10
12
0
0
13
0
0
14
0
11
15
0
0
16
17
0
0
18
19
0
20
22
0
Reserved
23
0
21
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXGCTR_CsIntStatus1
Table 20-17: Command Sequencer Interrupt Status 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
CsIntStatus1
20 - 22
Description
Each of the 7 read-only bits shows the status of the individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is inactive
1:
Interrupt is active
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.20 Command Sequencer Interrupt Enable 0 register
(GFXGCTR_CsIntEnable0)
The Command Sequencer Interrupt Enable 0 register enables or disables the Command Sequencer interrupt signals.
Figure 20-18: Command Sequencer Interrupt Enable 0 register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
17
0
16
18
0
CsIntEnable0
19
0
22
0
20
23
0
0
24
0
21
25
27
0
0
28
0
26
29
0
0
30
0
0
R
0
0
0
Reserved
Reserved
31
GFXGCTR_CsIntEnable0
Table 20-18: Command Sequencer Interrupt Enable 0 register bits
Bit position
Bit name
31
Reserved
[30:0]
CsIntEnable0
Description
Each of the 31 read-write bits enables or disables the individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is disabled
1:
Interrupt is enabled
Fujitsu Semiconductor Europe GmbH
20 - 23
Revised 24/7/13
Iris-SDL Register Descriptions
20.21 Command Sequencer Interrupt Enable 1 register
(GFXGCTR_CsIntEnable1)
The Command Sequencer Interrupt Enable 1 register enables or disables the Command Sequencer interrupt signals.
Figure 20-19: Command Sequencer Interrupt Enable 1 register
01
00
04
0
0
05
0
0
06
0
02
07
0
0
08
0
RW
0
0
Reserved
0
0
03
09
CsIntEnable1
10
12
0
0
13
0
0
14
0
11
15
0
0
16
17
0
0
18
19
0
20
22
0
Reserved
23
0
21
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXGCTR_CsIntEnable1
Table 20-19: Command Sequencer Interrupt Enable 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
CsIntEnable1
20 - 24
Description
Each of the 7 read-write bits enables or disables the individual interrupts.
Check also: Iris-SDL Interrupts section.
0:
Interrupt is disabled
1:
Interrupt is enabled
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.22 Command Sequencer Interrupt Clear 0 register
(GFXGCTR_CsIntClear0)
The Command Sequencer Interrupt Clear 0 register clears the Command Sequencer interrupt signal
bits.
Figure 20-20: Command Sequencer Interrupt Clear 0 register
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
15
0
13
16
0
CsIntClear0
17
0
0
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
21
28
0
0
29
0
30
0
RW
Reserved
Reserved
31
0
GFXGCTR_CsIntClear0
Table 20-20: Command Sequencer Interrupt Clear 0 register bits
Bit position
Bit name
[31:28]
Reserved
[27:0]
CsIntClear0
Description
Each of the 28 read-write bits clears an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
Fujitsu Semiconductor Europe GmbH
20 - 25
Revised 24/7/13
Iris-SDL Register Descriptions
20.23 Command Sequencer Interrupt Clear 1 register
(GFXGCTR_CsIntClear1)
The Command Sequencer Interrupt Clear 1 register clears the Command Sequencer interrupt signal
bits.
Figure 20-21: Command Sequencer Interrupt Clear 1 register
01
00
0
04
0
0
05
0
02
06
0
0
07
0
0
RW
Reserved
0
03
08
0
CsIntClear1
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
0
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
20
27
0
Reserved
28
0
0
29
0
21
30
0
0
31
0
GFXGCTR_CsIntClear1
Table 20-21: Command Sequencer Interrupt Clear 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
CsIntClear1
Description
Each of the 7 read-write bits clears an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
20 - 26
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.24 Command Sequencer Interrupt Preset 0 register
(GFXGCTR_CsIntPreset0)
The Command Sequencer Interrupt Preset 0 register presets the Command Sequencer interrupt signal
bits.
Figure 20-22: Command Sequencer Interrupt Preset 0 register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
14
0
0
15
0
12
16
0
0
17
0
13
18
0
CsIntPreset0
19
0
0
20
22
0
0
23
0
21
24
0
0
25
0
27
0
26
28
0
0
29
0
30
0
RW
Reserved
Reserved
31
0
GFXCTR_CsInPreset0
Table 20-22: Command Sequencer Interrupt Preset 0 register bits
Bit position
Bit name
[31:28]
Reserved
[27:0]
CsIntPreset0
Description
Each of the 28 read-write bits presets an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
Fujitsu Semiconductor Europe GmbH
20 - 27
Revised 24/7/13
Iris-SDL Register Descriptions
20.25 Command Sequencer Interrupt Preset 1 register
(GFXGCTR_CsIntPreset1)
The Command Sequencer Interrupt Preset 1 register presets the Command Sequencer interrupt signal
bits.
Figure 20-23: Command Sequencer Interrupt Preset 1 register
01
00
0
0
04
0
02
05
0
0
06
0
RW
0
0
03
07
0
CsIntPreset1
08
0
12
0
09
13
0
10
14
0
0
15
0
0
16
0
11
17
0
0
18
19
0
20
Reserved
Reserved
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXCTR_CsInPreset1
Table 20-23: Command Sequencer Interrupt Preset 1 register bits
Bit position
Bit name
[31:7]
Reserved
[6:0]
CsIntPreset1
Description
Each of the 7 read-write bits presets an individual interrupt.
Check also: Iris-SDL Interrupts section.
Write a 1 to clear the respective interrupt bit.
Writing a 0 has no effect.
The read value of the bits is always 0.
20 - 28
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.26 Software Reset register (GFXGCTR_SwReset)
The Software Reset register resets individual core units of Iris-SDL.
Figure 20-24: Software Reset register
Bit name
[31:5]
Reserved
4
disp_rstn
3
2
1
0
sig_rstn
csequ_rstn
peng_rstn
vram_rstn
02
01
00
peng_rstn
vram_rstn
RW
RW
0
0
05
0
csequ_rstn
06
0
RW
07
0
0
08
0
03
09
0
sig_rstn
10
0
RW
11
0
0
12
0
04
13
0
disp_rstn
14
0
RW
15
0
0
0
Reserved
Bit position
0
16
0
17
18
19
0
Reserved
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXCTR_SwReset
Description
Software reset for the Display Controller and Timing Controller.
0 :
Write 0 to release the reset.
1 :
Write 1 to hold the unit in reset.
Software reset for the Signature Unit.
0 :
Write 0 to release the reset.
1 :
Write 1 to hold the unit in reset.
Software reset for the Command Sequencer.
0 :
Write 0 to release the reset.
1 :
Write 1 to hold the unit in reset.
Software reset for the Pixel Engine.
0 :
Write 0 to release the reset.
1 :
Write 1 to hold the unit in reset.
Software reset for the Video Memory.
0 :
Write 0 to release the reset.
1 :
Write 1 to hold the unit in reset.
Fujitsu Semiconductor Europe GmbH
20 - 29
Revised 24/7/13
Iris-SDL Register Descriptions
20.27 Clock Adjust register (GFXGCTR_ClockAdjust)
The Clock Adjust register configures various settings for the internal clock signals of Iris-SDL.
Figure 20-25: Clock Adjust register
01
00
1
div_pix
1
04
1
02
05
1
1
06
1
03
07
1
RW
Reserved
0
1
08
0
Reserved
09
10
0
0
11
0
12
13
bypass_clk
RW
14
bypass_x2_clk
RW
0
0
15
Reserved
Reserved
0
RW
0
0
0
17
0
16
18
shift_pix
19
22
0
0
23
0
Reserved
0
0
24
0
20
25
0
21
26
0
28
0
RW
0
27
29
0
Reserved
30
0
inv_clk
31
GFXCTR_ClockAdjust
Bit position
Bit name
Description
31
inv_clk
Writing a 1 to this bit inverts the pix_del_clk phase when bypass_clk is 01.
[30:24]
Reserved
[23:16]
shift_pix
15
Reserved
14
bypass_x2_clk
20 - 30
This bitfield configures the phase shift value for the pix_del_clk and
pix_x2_del_clk signals in units of source clock cycles when
bypass_x2_clk is 0.
The value must be smaller than the value for div_pix.
0
= no delay
1
= shift by 1 source clock cycle
...
...
255
= shift by 255 source clock cycles
Bypasses the programmable divider (div_pix) and programmable phase
shift (shift_pix).
0
NBY (No BYpass):
The pix_x2_clk and pix_x2_del_clk signals are
generated from the PLL clock using the programmable
divider (see div_pix!).
1
BY (Bypass):
ref_clk is used as the source for pix_x2_clk and
pix_x2_del_clk (for use with an external pixel clock only)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[13:12]
bypass_clk
[11:8]
Reserved
[7:0]
div_pix
Revised 24/7/13
Used to bypass the divider (/2) for the delayed pixel clock (phase shifted
= ..._del_) so that pix_del_x2_clk = pix_del_clk. Does the same for the
pix_x2_clk signal (not delayed)
00
NBY (No BYpass):
pix_clk = pix_x2_clk divided by 2
pix_del_clk = pix_x2_del_clk divided by 2
01
BY (Bypass):
pix_clk = pix_x2_clk
pix_del_clk = pix_x2_del_clk (but note inv_clk!)
10
Reserved
11
Reserved
This bitfield configures the divider value for the incoming pixel clock
source (ref_clk delivered by and configured in the host controller). This
effects all generated clock signals.
Fujitsu Semiconductor Europe GmbH
1
Divide by 1
2
Divide by 2
...
...
255
Divide by 256
256
Not allowed
20 - 31
Revised 24/7/13
Iris-SDL Register Descriptions
20.28 Error Monitor Status register (GFXAIC_Status)
The Error Monitor Status register provides an overview of the error status of various Iris-SDL units that
occur on the AXI Bus.
Figure 20-26: Error Monitor Status register
Bit name
[31:16]
Reserved
[15:8]
ID
[7:2]
20 - 32
01
0
Type
0
R
Reserved
R
00
02
05
0
0
06
0
03
07
0
0
08
1
04
09
1
0
10
1
ID
Reserved
11
12
1
Reserved
Bit position
1
13
14
1
1
17
0
15
18
0
1
19
0
16
20
0
0
21
22
0
0
23
0
24
Reserved
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXAIC_Status
Description
The ID of the requester that executed an erroneous request.
NONE
11111111
No error detected
MSM
00000000 Main System Master
(4 MSBs contain the requester ID of the main system. The
LSBs are always 0)
PIXF0
00000001 Pixel Engine fetch unit 0
PIXF1
00000010 Pixel Engine fetch unit 1
PIXF2
00000011 Pixel Engine fetch unit 2
PIXF3
00000100 Pixel Engine fetch unit 3
PIXF4
00000101 Pixel Engine fetch unit 4
PIXF5
00000110 Pixel Engine fetch unit 5
PIXF6
00000111 Pixel Engine fetch unit 6
PIXF7
00001000 Pixel Engine fetch unit 7
PIXW
00001001 Pixel Engine Write Unit
CMDR
00001010 Command Sequencer read port
CMDW
00001011 Command Sequencer write port
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[1:0]
Type
Revised 24/7/13
NONE
00 No error detected
SLVERR
10 Slave signalled error
DECERR
11 Decoder signalled error
Fujitsu Semiconductor Europe GmbH
20 - 33
Revised 24/7/13
Iris-SDL Register Descriptions
20.29 Error Monitor Control register (GFXAIC_Control)
The Error Monitor Control register clears the error status of Iris-SDL.
Figure 20-27: Error Monitor Control register
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Clear
X
W1C
Reserved
0
00
10
0
12
0
0
13
0
11
14
0
0
15
17
0
0
18
0
16
19
0
Reserved
20
24
0
0
25
0
21
26
0
0
27
0
22
28
0
23
29
0
0
30
0
0
31
0
GFXAIC_Control
Table 20-24: Error Monitor Control register bits
Bit position
Bit name
[31:1]
Reserved
0
Clear
20 - 34
Description
Write a 1 to clear the error flag and prime the system to check for the next
error.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.30 Monitor Disable register (GFXAIC_MonitorDisable)
The Monitor Disable register is used to disable the error monitoring function for specific requesters.
Figure 20-28: Monitor Disable register
10
09
08
07
06
05
04
03
02
01
00
Pixw
Pixf7
Pixf6
Pixf5
Pixf4
Pixf3
Pixf2
Pixf1
Pixf0
Msm
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
12
0
Cmdr
13
0
RW
14
0
RW
15
0
0
16
0
0
17
0
11
18
0
Cmdw
19
0
RW
20
0
Reserved
0
21
22
0
0
23
0
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXAIC_MonitorDisable
Bit position
Bit name
Description
[31:12]
reserved
11
Cmdw
Command Sequencer write port. Write a 1 here to disable error monitoring.
10
Cmdr
Command Sequencer read port. Write a 1 here to disable error monitoring.
9
Pixw
Pixel Engine store unit. Write a 1 here to disable error monitoring.
8
Pixf7
Pixel Engine fetch unit #7. Write a 1 here to disable error monitoring.
7
Pixf6
Pixel Engine fetch unit #6. Write a 1 here to disable error monitoring.
6
Pixf5
Pixel Engine fetch unit #5. Write a 1 here to disable error monitoring.
5
Pixf4
Pixel Engine fetch unit #4. Write a 1 here to disable error monitoring.
4
Pixf3
Pixel Engine fetch unit #3. Write a 1 here to disable error monitoring.
3
Pixf2
Pixel Engine fetch unit #2. Write a 1 here to disable error monitoring.
2
Pixf1
Pixel Engine fetch unit #1. Write a 1 here to disable error monitoring.
1
Pixf0
Pixel Engine fetch unit #0. Write a 1 here to disable error monitoring.
0
Msm
Main System Master. Write a 1 here to disable error monitoring.
Fujitsu Semiconductor Europe GmbH
20 - 35
Revised 24/7/13
Iris-SDL Register Descriptions
20.31 Slave Disable register (GFXAIC_SlaveDisable)
The Slave Disable register is used to disable specific slave units attached to the AXI Interconnect Bus
Figure 20-29: Slave Disable register
10
09
08
07
06
05
04
03
02
01
00
DispCtrl
Signature
Tcon
PixEng
CmdSeq
SpiCsr
SpiMem
Vram0
Reserved
Mss
RW
RW
RW
RW
RW
RW
RW
Reserved
RW
0
0
0
0
0
0
0
0
0
12
0
GlobalCtrl
13
0
RW
14
0
RW
15
0
0
16
0
0
17
0
11
18
0
Hpm
19
0
RW
20
0
Reserved
0
21
22
0
0
23
0
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXAIC_SlaveDisable
Bit position
Bit name
[31:12]
Reserved
11
Hpm
High Performance Matrix Arbiter configuration register space. Write a 1 here
to disable this slave. If a request is made to this slave after it has been
disabled, the default slave will issue an error response.
10
GlobalCtrl
Global Control configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
9
DispCtrl
Display Controller configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
8
Signature
Signature Unit configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
7
Tcon
Timing Controller configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
6
PixEng
Pixel Engine configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
5
CmdSeq
Command Sequencer configuration register space. Write a 1 here to disable
this slave. If a request is made to this slave after it has been disabled, the
default slave will issue an error response.
20 - 36
Description
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
4
SpiCsr
SPI configuration register space. Write a 1 here to disable this slave. If a
request is made to this slave after it has been disabled, the default slave will
issue an error response.
3
SpiMem
SPI memory space configuration register space. Write a 1 here to disable
this slave. If a request is made to this slave after it has been disabled, the
default slave will issue an error response.
2
Vram0
VRAM controller 0 configuration register space. Write a 1 here to disable this
slave. If a request is made to this slave after it has been disabled, the default
slave will issue an error response.
1
Reserved
Reserved.
0
Mss
Main System Slave configuration register space. Write a 1 here to disable
this slave. If a request is made to this slave after it has been disabled, the
default slave will issue an error response.
Fujitsu Semiconductor Europe GmbH
20 - 37
Revised 24/7/13
Iris-SDL Register Descriptions
20.32 MSS A Read Arbitration register (GFXHPM_MSSARarbitration)
The MSS A Read Arbitration register controls the AR channel read priority of the Iris-SDL master when
accessing main system resources. For details, please refer to ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-30: MSS A Read Arbitration register
01
00
0
RW
MSS_RMaster
0
04
0
02
05
0
0
06
0
03
07
0
RW
Bit position
Bit name
Description
[31:24]
MSS_RSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
MSS_RPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
MSS_RMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
20 - 38
0
08
0
12
0
09
13
0
10
14
0
0
15
0
0
16
0
11
17
0
0
18
0
0
RW
Reserved
Reserved
MSS_RPriority
19
0
22
0
20
23
0
0
24
0
21
25
0
0
26
28
0
0
29
0
27
30
0
MSS_RSlot
31
0
GFXHPM_MSSARarbitration
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.33 MSS A Write Arbitration register (GFXHPM_MSSAWarbitration)
The MSS A Write Arbitration register controls the AR channel write priority of the Iris-SDL master when
accessing main system resources. For details, please refer to ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-31: MSS A Write Arbitration register
00
RW
MSS_WMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
MSS_WSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
MSS_WPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
MSS_WMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
Fujitsu Semiconductor Europe GmbH
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
MSS_WPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
MSS_WSlot
31
0
GFXHPM_MSSAWarbitration
20 - 39
Revised 24/7/13
Iris-SDL Register Descriptions
20.34 VRAM0 A Read Arbitration register
(GFXHPM_Vram0ARarbitration)
The VRAM0 A Read Arbitration register controls the AR channel read priority of the main system or an
Iris-SDL master resource when accessing the VRAM0 memory interface. For details, please refer to
ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-32: VRAM0 A Read Arbitration register
00
RW
Vram0_RMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
Vram0_RSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
Vram0_RPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
Vram0_RMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
20 - 40
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
Vram0_RPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
Vram0_RSlot
31
0
GFXHPM_VRAM0ARarbitration
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.35 VRAM0 A Write Arbitration register
(GFXHPM_Vram0AWarbitration)
The VRAM0 A Write Arbitration register controls the AR channel write priority of the main system or an
Iris-SDL master resource when accessing the VRAM0 memory interface. For details, please refer to
ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-33: VRAM0 A Write Arbitration register
00
RW
Vram0_WMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
Vram0_WSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
Vram0_WPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
Vram0_WMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
Fujitsu Semiconductor Europe GmbH
0
10
12
0
0
13
0
0
14
0
11
15
0
0
16
0
0
0
RW
Reserved
Reserved
Vram0_WPriority
17
0
21
0
18
22
0
19
23
0
0
24
0
0
25
0
20
26
28
0
0
29
0
27
30
0
Vram0_WSlot
31
0
GFXHPM_Vram0AWarbitration
20 - 41
Revised 24/7/13
Iris-SDL Register Descriptions
20.36 AHB A Read Arbitration register (GFXHPM_AHBARarbitration)
The AHB A Read Arbitration register controls the AR channel read priority for access to Iris-SDL config
registers (with the exception of the arbitration config HPM PL301 registers themselves) by the main system and the HS-SPI memory map. For details, please refer to ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-34: AHB A Read Arbitration register
00
RW
AHB_RMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
AHB_RSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
AHB_RPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
AHB_RMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
20 - 42
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
AHB_RPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
AHB_RSlot
31
0
GFXHPM_AHBARarbitration
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.37 AHB A Write Arbitration register (GFXHPM_AHBAWarbitration)
The AHB A Write Arbitration register controls the AR channel write priority for access to Iris-SDL config
registers (with the exception of the arbitration config HPM PL301 registers themselves) by the main system and the HS-SPI memory map. For details, please refer to ARM Limited’s HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-35: AHB A Write Arbitration register
00
RW
AHB_WMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
AHB_WSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
AHB_WPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
AHB_WMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
Fujitsu Semiconductor Europe GmbH
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
AHB_WPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
AHB_WSlot
31
0
GFXHPM_AHBAWarbitration
20 - 43
Revised 24/7/13
Iris-SDL Register Descriptions
20.38 High-Performance Matrix A Read Arbitration register
(GFXHPM_HPMARarbitration)
The High-Performance Matrix A Read Arbitration register controls the collective AR channel read priority of external agents when accessing all Iris-SDL resources connected to the AHB bus (GCTR, SIG,
DISP, TCON, CMDSEQ, AIC, SPI, Pixel Engine Config). For details, please refer to ARM Limited’s
HPM specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-36: High-Performance Matrix A Read Arbitration register
00
RW
AHB_RMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
AHB_RSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
AHB_RPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
AHB_RMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
20 - 44
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
AHB_RPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
AHB_RSlot
31
0
GFXHPM_HPMARarbitration
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.39 High-Performance Matrix A Write Arbitration register
(GFXHPM_HPMAWarbitration)
The High-Performance Matrix A Write Arbitration register controls the collective AW channel write priority of external agents when accessing all Iris-SDL resources connected to the AHB bus (GCTR, SIG,
DISP, TCON, CMDSEQ, AIC, SPI, Pixel Engine Config). For details, please refer to ARM Limited’s HPM
specification: PrimeCell® High-Performance Matrix (PL301) Revision: r1p2
Figure 20-37: High-Performance Matrix A Write Arbitration register
00
RW
AHB_WMaster
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
RW
Bit position
Bit name
Description
[31:24]
AHB_WSlot
Interface number (when changing priority when writing)
See also “Arbiting Scheme”
[23:16]
Reserved
[15:8]
AHB_WPriority
Interface arbitration priority value (0 is highest, 255 lowest)
[7:0]
AHB_WMaster
Interface number (to get priority when reading)
See also “Arbiting Scheme”
Fujitsu Semiconductor Europe GmbH
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
RW
Reserved
Reserved
AHB_WPriority
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
0
26
28
0
0
29
0
27
30
0
AHB_WSlot
31
0
GFXHPM_HPMAWarbitration
20 - 45
Revised 24/7/13
Iris-SDL Register Descriptions
20.40 Pixelbus Configuration for fetch0 unit register
(GFXPIX_fetch0_cfg)
The Pixelbus Configuration for unit fetch0 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-38: Pixelbus Configuration for unit fetch0 register
Reserved
[29:28]
fetch0_SEL
fetch0_SHDW
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
11
13
0
0
14
0
12
15
19
0
0
20
0
16
21
0
0
22
0
17
23
0
[31:30]
20 - 46
0
24
0
Bit name
[25:0]
18
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
fetch0_SHDW
28
X
29
X
fetch0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch0_cfg
Description
Used to read the fetch0 module’s pixel processing path configuration:
00
The fetch0 module is not used
01
The fetch0 module from the extdst0 processing path is selected
10
The fetch0 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch0 module:
00
Disable: fetch0 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch0 automatically sends a reload flag for the modules
of the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch0 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch0 automatically sends a reload flag for the modules
of the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.41 Pixelbus Configuration for fetch1 unit register
(GFXPIX_fetch1_cfg)
The Pixelbus Configuration for unit fetch1 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-39: Pixelbus Configuration for unit fetch1 register
06
05
04
03
02
01
00
0
0
0
0
0
Reserved
Reserved
0
13
0
0
14
0
07
15
0
0
16
0
08
17
0
0
18
0
09
19
0
10
20
0
0
21
0
0
22
0
11
23
0
0
24
0
Bit name
[31:30]
Reserved
[29:28]
fetch1_SEL
[25:0]
12
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
fetch1_SHDW
28
X
29
X
fetch1_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch1_cfg
fetch1_SHDW
Description
Used to read the fetch1 module’s pixel processing path configuration:
00
The fetch1 module is not used
01
The fetch1 module from the extdst0 processing path is selected
10
The fetch1 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch1 module:
00
Disable: fetch1 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch1 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch1 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch1 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 47
Revised 24/7/13
Iris-SDL Register Descriptions
20.42 Pixelbus Configuration for fetch2 unit register
(GFXPIX_fetch2_cfg)
The Pixelbus Configuration for unit fetch2 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-40: Pixelbus Configuration for unit fetch2 register
Reserved
[29:28]
fetch2_SEL
fetch2_SHDW
05
04
03
02
01
00
0
0
0
0
0
0
Reserved
Reserved
06
13
0
0
14
0
0
15
0
07
16
0
0
17
0
08
18
0
0
19
0
09
20
0
10
21
0
0
22
0
0
23
0
[31:30]
20 - 48
11
24
0
Bit name
[25:0]
0
25
0
RW
R
Bit position
[27:26]
12
26
0
27
0
fetch2_SHDW
28
X
29
X
fetch2_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch2_cfg
Description
Used to read the fetch2 module’s pixel processing path configuration:
00
The fetch2 module is not used
01
The fetch2 module from the extdst0 processing path is selected
10
The fetch2 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch2 module:
00
Disable: fetch2 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch2 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch2 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch2 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.43 Pixelbus Configuration for fetch3 unit register
(GFXPIX_fetch3_cfg)
The Pixelbus Configuration for unit fetch3 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-41: Pixelbus Configuration for unit fetch3 register
06
05
04
03
02
01
00
0
0
0
0
0
Reserved
Reserved
0
13
0
0
14
0
07
15
0
0
16
0
08
17
0
0
18
0
09
19
0
10
20
0
0
21
0
0
22
0
11
23
0
0
24
0
Bit name
[31:30]
Reserved
[29:28]
fetch3_SEL
[25:0]
12
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
fetch3_SHDW
28
X
29
X
fetch3_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch3_cfg
fetch3_SHDW
Description
Used to read the fetch3 module’s pixel processing path configuration:
00
The fetch3 module is not used
01
The fetch3 module from the extdst0 processing path is selected
10
The fetch3 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch3 module:
00
Disable: fetch3 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch3 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch3 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch3 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 49
Revised 24/7/13
Iris-SDL Register Descriptions
20.44 Pixelbus Configuration for fetch4 unit register
(GFXPIX_fetch4_cfg)
The Pixelbus Configuration for unit fetch4 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-42: Pixelbus Configuration for unit fetch4 register
Reserved
[29:28]
fetch4_SEL
fetch4_SHDW
05
04
03
02
01
00
0
0
0
0
0
0
Reserved
Reserved
06
13
0
0
14
0
0
15
0
07
16
0
0
17
0
08
18
0
0
19
0
09
20
0
10
21
0
0
22
0
0
23
0
[31:30]
20 - 50
11
24
0
Bit name
[25:0]
0
25
0
RW
R
Bit position
[27:26]
12
26
0
27
0
fetch4_SHDW
28
X
29
X
fetch4_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch4_cfg
Description
Used to read the fetch4 module’s pixel processing path configuration:
00
The fetch4 module is not used
01
The fetch4 module from the extdst0 processing path is selected
10
The fetch4 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch4 module:
00
Disable: fetch4 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch4 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch4 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch4 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.45 Pixelbus Configuration for fetch5 unit register
(GFXPIX_fetch5_cfg)
The Pixelbus Configuration for unit fetch5 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-43: Pixelbus Configuration for unit fetch5 register
06
05
04
03
02
01
00
0
0
0
0
0
Reserved
Reserved
0
13
0
0
14
0
07
15
0
0
16
0
08
17
0
0
18
0
09
19
0
10
20
0
0
21
0
0
22
0
11
23
0
0
24
0
Bit name
[31:30]
Reserved
[29:28]
fetch5_SEL
[25:0]
12
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
fetch5_SHDW
28
X
29
X
fetch5_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch5_cfg
fetch5_SHDW
Description
Used to read the fetch5 module’s pixel processing path configuration:
00
The fetch5 module is not used
01
The fetch5 module from the extdst0 processing path is selected
10
The fetch5 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch5 module:
00
Disable: fetch5 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch5 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch5 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch5 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 51
Revised 24/7/13
Iris-SDL Register Descriptions
20.46 Pixelbus Configuration for fetch6 unit register
(GFXPIX_fetch6_cfg)
The Pixelbus Configuration for unit fetch6 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-44: Pixelbus Configuration for unit fetch6 register
Reserved
[29:28]
fetch6_SEL
fetch6_SHDW
05
04
03
02
01
00
0
0
0
0
0
0
Reserved
Reserved
06
13
0
0
14
0
0
15
0
07
16
0
0
17
0
08
18
0
0
19
0
09
20
0
10
21
0
0
22
0
0
23
0
[31:30]
20 - 52
11
24
0
Bit name
[25:0]
0
25
0
RW
R
Bit position
[27:26]
12
26
0
27
0
fetch6_SHDW
28
X
29
X
fetch6_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch6_cfg
Description
Used to read the fetch6 module’s pixel processing path configuration:
00
The fetch6 module is not used
01
The fetch6 module from the extdst0 processing path is selected
10
The fetch6 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch6 module:
00
Disable: fetch6 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch6 automatically sends a reload flag for the modules
of the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch6 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch6 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.47 Pixelbus Configuration for fetch7 unit register
(GFXPIX_fetch7_cfg)
The Pixelbus Configuration for unit fetch7 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline.
Figure 20-45: Pixelbus Configuration for unit fetch7 register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
11
13
0
0
14
0
12
15
0
0
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
Bit name
[31:30]
Reserved
[29:28]
fetch7_SEL
[25:0]
0
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
fetch7_SHDW
28
X
29
X
fetch7_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_fetch7_cfg
fetch7_SHDW
Description
Used to read the fetch7 module’s pixel processing path configuration:
00
The fetch7 module is not used
01
The fetch7 module from the extdst0 processing path is selected
10
The fetch7 module from the store0 processing path is selected
11
Reserved
Controls the shadow reload flag generation of the fetch7 module:
00
Disable: fetch7 does not automatically send a reload flag for the
modules of the pipeline
01
extdst0: fetch7 automatically sends a reload flag for the modules of
the pipeline connected to the extdst0 pixel engine synchronizer
10
store0: fetch7 automatically sends a reload flag for the modules of
the pipeline connected to the store0 pixel engine synchronizer
11
Enable: fetch7 automatically sends a reload flag for the modules of
the pipeline connected to either the extdst0 or the store0 pixel
engine synchronizer
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 53
Revised 24/7/13
Iris-SDL Register Descriptions
20.48 Pixelbus Configuration for store0 unit register
(GFXPIX_store0_cfg)
The Pixelbus Configuration for unit store0 register is used to read the pixel processing path of the unit
and to control its shadow reload flag in the pipeline. The register also selects the input source for the
store0 module.
Figure 20-46: Pixelbus Configuration for unit store0 register
Bit name
[31:30]
Reserved
[29:28]
store0_SEL
04
03
0
0
00
05
0
01
06
0
0
07
0
0
08
0
02
09
RWS
0
0
Reserved
Reserved
store0_src_SEL
10
0
16
0
0
17
0
11
18
0
0
19
0
12
20
0
0
21
0
13
22
0
14
23
0
0
24
0
0
25
0
RW
R
Bit position
20 - 54
15
26
0
27
0
store0_SHDW
28
X
29
X
store0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_store0_cfg
Description
Used to read the store0 module’s pixel processing path
configuration:
00
The store0 module is not used
01
The store0 module from the extdst0 processing path is
selected
10
The store0 module from the store0 processing path is
selected
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[27:26]
store0_SHDW
[25:5]
Reserved
[4:0]
store0_src_SEL
Revised 24/7/13
Controls the shadow reload flag generation of the store0 module:
00
Disable: store0 does not automatically send a reload flag
for the modules of the pipeline
01
extdst0: store0 automatically sends a reload flag for the
modules of the pipeline connected to the extdst0 pixel
engine synchronizer
10
store0: store0 automatically sends a reload flag for the
modules of the pipeline connected to the store0 pixel
engine synchronizer
11
Enable: store0 automatically sends a reload flag for the
modules of the pipeline connected to either the extdst0 or
the store0 pixel engine synchronizer
Selects the source for the src input to the store0 module:
(values not listed below are reserved and should not be used)
00000
Disable src input
01110
Selects bitblend0
Fujitsu Semiconductor Europe GmbH
20 - 55
Revised 24/7/13
Iris-SDL Register Descriptions
20.49 Pixelbus Configuration for rop0 unit register (GFXPIX_rop0_cfg)
The Pixelbus Configuration for unit rop0 register is used to read the pixel processing path of the unit and
to control its shadow profile. It also controls the rop0 clock and selects the input source for the rop0 module inputs.
Figure 20-47: Pixelbus Configuration for unit rop0 register
Reserved
[29:28]
rop0_SEL
rop0_SHDW
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
rop0_prim_SEL
05
07
0
06
08
0
0
RWS
0
0
09
10
0
11
12
0
0
Reserved
Reserved
rop0_sec_SEL
13
15
0
14
16
0
RWS
0
0
0
17
0
18
19
0
rop0_aux_SEL
20
0
Reserved
[31:30]
0
Reserved
Bit name
20 - 56
21
23
0
Bit position
[27:26]
22
24
RWS
RW
R
1
25
1
rop0_CLKEN
26
0
27
0
rop0_SHDW
28
X
29
X
rop0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_rop0_cfg
Description
Used to read the rop0 module’s pixel processing path:
00
The rop0 module is not used
01
The rop0 module from the extdst0 processing path is selected
10
The rop0 module from the store0 processing path is selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for rop0_cfg register (continous update of
the register)
01
extdst0: rop0_cfg register will be updated by the extdst0 pixel
engine synchronizer
10
store0: rop0_cfg register will be updated by the store0 pixel
engine synchronizer
11
Enable: rop0_cfg register will be updated by both the extsdt0
and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
rop0_CLKEN
[23:21]
Reserved
[20:16]
rop0_aux_SEL
[15:13]
Reserved
[12:8]
rop0_sec_SEL
[7:5]
Reserved
[4:0]
rop0_prim_SEL
Revised 24/7/13
Enables the rop0 clock (this setting has to be the same for all modules
of one processing pipeline)
00
Disable: clock for rop0 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for rop0 is without gating
Selects the source for the auxiliary input of the rop0 module.
00000
Disable
01010
Selects fetch2
01111
Selects lut0
Selects the source for the secondary input of the rop0 module.
00000
Disable
00010
Selects fetch1
Selects the source for the primary input of the rop0 module.
00000
Disable
01010
Selects fetch2
01111
Selects lut0
Fujitsu Semiconductor Europe GmbH
20 - 57
Revised 24/7/13
Iris-SDL Register Descriptions
20.50 Pixelbus Configuration for rop1 unit register (GFXPIX_rop1_cfg)
The Pixelbus Configuration for unit rop1 register is used to read the pixel processing path of the unit
and to control its shadow profile. It also controls the rop1 clock and selects the input source for the rop1
module inputs.
Figure 20-48: Pixelbus Configuration for unit rop1 register
Reserved
[29:28]
rop1_SEL
rop1_SHDW
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
rop1_prim_SEL
05
07
0
06
08
0
0
RWS
0
0
09
10
0
11
12
0
0
Reserved
Reserved
rop1_sec_SEL
13
15
0
14
16
0
RWS
0
0
0
17
0
18
19
0
rop1_aux_SEL
20
0
Reserved
[31:30]
0
Reserved
Bit name
20 - 58
21
23
0
Bit position
[27:26]
22
24
RWS
RW
R
1
25
1
rop1_CLKEN
26
0
27
0
rop1_SHDW
28
X
29
X
rop1_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_rop1_cfg
Description
Used to read the rop1 module’s pixel processing path:
00
The rop1 module is not used
01
The rop1 module from the extdst0 processing path is selected
10
The rop1 module from the store0 processing path is selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for rop1_cfg register (continous update of
the register)
01
extdst0: rop1_cfg register will be updated by the extdst0 pixel
engine synchronizer
10
store0: rop1_cfg register will be updated by the store0 pixel
engine synchronizer
11
Enable: rop1_cfg register will be updated by both the extsdt0
and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
rop1_CLKEN
[23:21]
Reserved
[20:16]
rop1_aux_SEL
[15:13]
Reserved
[12:8]
rop1_sec_SEL
[7:5]
Reserved
[4:0]
rop1_prim_SEL
Revised 24/7/13
Enables the rop1 clock (this setting has to be the same for all modules
of one processing pipeline)
00
Disable: clock for rop1 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for rop1 is without gating
Selects the source for the auxiliary input of the rop1 module.
00000
Disable
01010
Selects fetch2
01111
Selects lut0
Selects the source for the secondary input of the rop1 module.
00000
Disable
01000
Selects fetch7
Selects the source for the primary input of the rop1 module.
00000
Disable
00100
Selects fetch3
01111
Selects layerblend0
10000
Selects layerblend1
10001
Selects layerblend2
00101
Selects fetch4
00110
Selects fetch5
00111
Selects fetch6
Fujitsu Semiconductor Europe GmbH
20 - 59
Revised 24/7/13
Iris-SDL Register Descriptions
20.51 Pixelbus Configuration for blitblend0 unit register
(GFXPIX_blitblend0_cfg)
The Pixelbus Configuration for unit blitblend0 register is used to read the pixel processing path of the
unit and to control its shadow profile. It also controls the blitblend0 clock and selects the input source for
the blitblend0 module inputs.
Figure 20-49: Pixelbus Configuration for unit blitblend0 register
[31:30]
Reserved
[29:28]
blitblend0_SEL
blitblend0_SHDW
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
blitblend0_prim_SEL
05
07
0
06
08
0
0
RWS
0
0
09
10
12
0
0
13
0
11
14
0
0
0
Reserved
Reserved
blitblend0_sec_SEL
15
19
0
0
20
0
16
21
0
0
22
0
Bit name
20 - 60
17
23
0
Bit position
[27:26]
18
24
RWS
RW
R
1
25
1
blitblend0_CLKEN
26
0
27
0
blitblend0_SHDW
28
X
29
X
blitblend0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_blitblend0_cfg
Description
Used to read the blitblend0 module’s pixel processing path:
00
The blitblend0 module is not used
01
The blitblend0 module from the extdst0 processing path
is selected
10
The blitblend0 module from the store0 processing path is
selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for blitblend0_cfg register
(continuous update of the register)
01
extdst0: blitblend0_cfg register will be updated by the
extdst0 pixel engine synchronizer
10
store0: blitblend0_cfg register will be updated by the
store0 pixel engine synchronizer
11
Enable: blitblend0_cfg register will be updated by both
the extsdt0 and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
blitblend0_CLKEN
[23:13]
Reserved
[12:8]
blitblend0_sec_SEL
[7:5]
Reserved
[4:0]
blitblend0_prim_SEL
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Enables the blitblend0 clock (this setting has to be the same for all
modules of one processing pipeline)
00
Disable: clock for blitblend0 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for blitblend0 is without gating
Selects the source for the secondary input of the blitblend0
module.
00000
Disable
00011
Selects fetch2
10010
Selects lut0
Selects the source for the primary input of the blitblend0 module.
00000
Disable
10001
Selects layerblend2
01100
Selects rop0
10100
Selects matrix0
20 - 61
Revised 24/7/13
Iris-SDL Register Descriptions
20.52 Pixelbus Configuration for layerblend0 unit register
(GFXPIX_layerblend0_cfg)
The Pixelbus Configuration for unit layerblend0 register is used to read the pixel processing path of the
unit and to control its shadow profile. It also controls the layerblend0 clock and selects the input source
for the layerblend0 module inputs.
Figure 20-50: Pixelbus Configuration for unit layerblend0 register
[31:30]
Reserved
[29:28]
layerblend0_SEL
layerblend0_SH
DW
01
00
0
0
03
0
02
04
0
layerblend0_prim_SEL
05
RWS
0
0
Reserved
Reserved
06
07
0
0
RWS
0
0
0
08
0
12
0
09
13
0
10
14
0
0
15
0
11
16
0
Reserved
Reserved
layerblend0_sec_SEL
17
0
18
19
21
0
0
22
0
Bit name
20 - 62
20
23
0
Bit position
[27:26]
0
24
RWS
RW
R
1
25
1
layerblend0_CLKEN
26
0
27
0
layerblend0_SHDW
28
X
29
X
layerblend0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_layerblend0_cfg
Description
Used to read the layerblend0 module’s pixel processing path:
00
The layerblend0 module is not used
01
The layerblend0 module from the extdst0 processing path is
selected
10
The layerblend0 module from the store0 processing path is
selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for layerblend0_cfg register (continous
update of the register)
01
extdst0: layerblend0_cfg register will be updated by the
extdst0 pixel engine synchronizer
10
store0: layerblend0_cfg register will be updated by the store0
pixel engine synchronizer
11
Enable: layerblend0_cfg register will be updated by both the
extsdt0 and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
layerblend0_CLK
EN
[23:13]
Reserved
[12:8]
layerblend0_sec
_SEL
[7:5]
Reserved
[4:0]
layerblend0_prim
_SEL
Revised 24/7/13
Enables the layerblend0 clock (this setting has to be the same for all
modules of one processing pipeline)
00
Disable: clock for layerblend0 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for layerblend0 is without gating
Selects the source for the secondary input of the layerblend0 module.
00000
Disable
00101
Selects fetch4
01101
Selects rop1
Selects the source for the primary input of the layerblend0 module.
00000
Disable
10001
Selects fetch3
01100
Selects rop0
Fujitsu Semiconductor Europe GmbH
20 - 63
Revised 24/7/13
Iris-SDL Register Descriptions
20.53 Pixelbus Configuration for layerblend1 unit register
(GFXPIX_layerblend1_cfg)
The Pixelbus Configuration for unit layerblend1 register is used to read the pixel processing path of the
unit and to control its shadow profile. It also controls the layerblend1 clock and selects the input source
for the layerblend1 module inputs.
Figure 20-51: Pixelbus Configuration for unit layerblend1 register
[31:30]
Reserved
[29:28]
layerblend1_SEL
layerblend1_SH
DW
01
00
0
0
03
0
02
04
0
layerblend1_prim_SEL
05
RWS
0
0
Reserved
Reserved
06
07
0
0
RWS
0
0
08
0
12
0
09
13
0
10
14
0
0
15
0
11
16
0
layerblend1_sec_SEL
17
0
0
Reserved
Reserved
18
19
21
0
0
22
0
Bit name
20 - 64
20
23
0
Bit position
[27:26]
0
24
RWS
RW
R
1
25
1
layerblend1_CLKEN
26
0
27
0
layerblend1_SHDW
28
X
29
X
layerblend1_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_layerblend1_cfg
Description
Used to read the layerblend1 module’s pixel processing path:
00
The layerblend1 module is not used
01
The layerblend1 module from the extdst0 processing path is
selected
10
The layerblend1 module from the store0 processing path is
selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for layerblend1_cfg register (continous
update of the register)
01
extdst0: layerblend1_cfg register will be updated by the
extdst0 pixel engine synchronizer
10
store0: layerblend1_cfg register will be updated by the store0
pixel engine synchronizer
11
Enable: layerblend1_cfg register will be updated by both the
extsdt0 and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
layerblend1_CLK
EN
[23:13]
Reserved
[12:8]
layerblend1_sec
_SEL
[7:5]
Reserved
[4:0]
layerblend1_prim
_SEL
Revised 24/7/13
Enables the layerblend1 clock (this setting has to be the same for all
modules of one processing pipeline)
00
Disable: clock for layerblend1 is disabled
01
Automatic: clock is enabled if unit is used, frequency is defined
by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for layerblend1 is without gating
Selects the source for the secondary input of the layerblend1 module.
00000
Disable
00110
Selects fetch5
01101
Selects rop1
Selects the source for the primary input of the layerblend1 module.
00000
Disable
01111
Selects layerblend0
01100
Selects rop0
Fujitsu Semiconductor Europe GmbH
20 - 65
Revised 24/7/13
Iris-SDL Register Descriptions
20.54 Pixelbus Configuration for layerblend2 unit register
(GFXPIX_layerblend2_cfg)
The Pixelbus Configuration for unit layerblend2 register is used to read the pixel processing path of the
unit and to control its shadow profile. It also controls the layerblend2 clock and selects the input source
for the layerblend2 module inputs.
Figure 20-52: Pixelbus Configuration for unit layerblend2 register
[31:30]
Reserved
[29:28]
layerblend2_SEL
layerblend2_SHDW
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
layerblend2_prim_SEL
05
07
0
06
08
0
0
RWS
0
0
09
10
12
0
0
13
0
11
14
0
0
Reserved
Reserved
layerblend2_sec_SEL
15
0
19
0
16
20
0
0
21
0
17
22
0
Bit name
20 - 66
0
23
0
Bit position
[27:26]
18
24
RWS
RW
R
1
25
1
layerblend2_CLKEN
26
0
27
0
layerblend2_SHDW
28
X
29
X
layerblend2_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_layerblend2_cfg
Description
Used to read the layerblend2 module’s pixel processing path:
00
The layerblend2 module is not used
01
The layerblend2 module from the extdst0 processing
path is selected
10
The layerblend2 module from the store0 processing path
is selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for layerblend2_cfg register
(continous update of the register)
01
extdst0: layerblend2_cfg register will be updated by the
extdst0 pixel engine synchronizer
10
store0: layerblend2_cfg register will be updated by the
store0 pixel engine synchronizer
11
Enable: layerblend2_cfg register will be updated by both
the extsdt0 and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
layerblend1_CLKEN
[23:13]
Reserved
[12:8]
layerblend1_sec_SEL
[7:5]
Reserved
[4:0]
layerblend1_prim_SEL
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Enables the layerblend1 clock (this setting has to be the same for
all modules of one processing pipeline)
00
Disable: clock for layerblend1 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for layerblend1 is without gating
Selects the source for the secondary input of the layerblend1
module.
00000
Disable
00110
Selects fetch5
01101
Selects rop1
Selects the source for the primary input of the layerblend1
module.
00000
Disable
01111
Selects layerblend0
01100
Selects rop0
20 - 67
Revised 24/7/13
Iris-SDL Register Descriptions
20.55 Pixelbus Configuration for lut0 unit register (GFXPIX_lut0_cfg)
The Pixelbus Configuration for unit lut0 register is used to read the pixel processing path of the unit and
to control its shadow profile. It also controls the lut0 clock and selects the input source for the lut0 module.
Figure 20-53: Pixelbus Configuration for unit lut0 register
[31:30]
Reserved
[29:28]
lut0_SEL
lut0_SHDW
05
04
03
0
0
0
00
06
0
01
07
0
0
08
0
0
09
0
02
10
0
RWS
0
0
Reserved
Reserved
lut0_src_SEL
11
0
12
15
0
0
16
0
13
17
0
14
18
0
19
0
21
0
0
22
0
Bit name
20 - 68
20
23
0
RWS
Bit position
[27:26]
0
24
1
25
1
lut0_CLKEN
26
0
27
R
RW
lut0_SEL
lut0_SHDW
28
0
29
X
Reserved
0
X
30
0
Reserved
31
GFXPIX_lut0_cfg
Description
Used to read the lut0 module’s pixel processing path:
00
The lut0 module is not used
01
The lut0 module from the extdst0 processing path is selected
10
The lut0 module from the store0 processing path is selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for lut0_cfg register (continous update of
the register)
01
extdst0: lut0_cfg register will be updated by the extdst0 pixel
engine synchronizer
10
store0: lut0_cfg register will be updated by the store0 pixel
engine synchronizer
11
Enable: lut0_cfg register will be updated by both the extsdt0
and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
lut0_CLKEN
[23:5]
Reserved
[4:0]
lut0_src_SEL
Revised 24/7/13
Enables the lut0 clock (this setting has to be the same for all modules of
one processing pipeline)
00
Disable: clock for lut0 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for lut0 is without gating
Selects the source for the src input of the lut0 module.
00000
Disable
00001
Selects fetch0
Fujitsu Semiconductor Europe GmbH
20 - 69
Revised 24/7/13
Iris-SDL Register Descriptions
20.56 Pixelbus Configuration for lut1 unit register (GFXPIX_lut1_cfg)
The Pixelbus Configuration for unit lut1 register is used to read the pixel processing path of the unit and
to control its shadow profile. It also controls the lut1 clock and selects the input source for the lut1 module.
Figure 20-54: Pixelbus Configuration for unit lut1 register
[31:30]
Reserved
[29:28]
lut1_SEL
lut1_SHDW
05
04
03
0
0
0
00
06
0
01
07
0
0
08
0
0
09
0
02
10
0
RWS
0
0
Reserved
Reserved
lut1_src_SEL
11
12
0
0
13
15
0
14
16
0
0
17
18
0
19
0
21
0
0
22
0
Bit name
20 - 70
20
23
0
RWS
Bit position
[27:26]
0
24
1
25
1
lut1_CLKEN
26
0
27
R
RW
lut1_SEL
lut1_SHDW
28
0
29
X
Reserved
0
X
30
0
Reserved
31
GFXPIX_lut1_cfg
Description
Used to read the lut1 module’s pixel processing path:
00
The lut1 module is not used
01
The lut1 module from the extdst0 processing path is selected
10
The lut1 module from the store0 processing path is selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for lut1_cfg register (continous update of
the register)
01
extdst0: lut1_cfg register will be updated by the extdst0 pixel
engine synchronizer
10
store0: lut1_cfg register will be updated by the store0 pixel
engine synchronizer
11
Enable: lut1_cfg register will be updated by both the extsdt0
and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
lut1_CLKEN
[23:5]
Reserved
[4:0]
lut1_src_SEL
Revised 24/7/13
Enables the lut1 clock (this setting has to be the same for all modules of
one processing pipeline)
00
Disable: clock for lut1 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for lut1 is without gating
Selects the source for the src input of the lut1 module.
00000
Disable
00100
Selects fetch3
01111
Selects layerblend0
10000
Selects layerblend1
10001
Selects layerblend2
01101
Selects rop1
10100
Selects matrix0
Fujitsu Semiconductor Europe GmbH
20 - 71
Revised 24/7/13
Iris-SDL Register Descriptions
20.57 Pixelbus Configuration for matrix0 unit register
(GFXPIX_matrix0_cfg)
The Pixelbus Configuration for unit matrix0 register is used to read the pixel processing path of the unit
and to control its shadow profile. It also controls the matrix0 clock and selects the input source for the
matrix0 module.
Figure 20-55: Pixelbus Configuration for unit lut1 register
[31:30]
Reserved
[29:28]
matrix0_SEL
matrix0_SHDW
05
04
03
0
0
0
00
06
0
01
07
0
0
08
0
0
09
0
02
10
0
RWS
0
0
Reserved
Reserved
matrix0_src_SEL
11
12
0
0
13
15
0
14
16
0
0
17
18
0
19
0
21
0
0
22
0
Bit name
20 - 72
20
23
0
Bit position
[27:26]
0
24
RWS
RW
R
1
25
1
matrix0_CLKEN
26
0
27
0
matrix0_SHDW
28
X
29
X
matrix0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_matrix0_cfg
Description
Used to read the matrix0 module’s pixel processing path:
00
The matrix0 module is not used
01
The matrix0 module from the extdst0 processing path is
selected
10
The matrix0 module from the store0 processing path is
selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for matrix0_cfg register (continous
update of the register)
01
extdst0: matrix0_cfg register will be updated by the extdst0
pixel engine synchronizer
10
store0: matrix0_cfg register will be updated by the store0
pixel engine synchronizer
11
Enable: matrix0_cfg register will be updated by both the
extsdt0 and store0 pixel engine synchronizers
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[25:24]
matrix0_CLKEN
[23:5]
Reserved
[4:0]
matrix0_src_SEL
Revised 24/7/13
Enables the matrix0 clock (this setting has to be the same for all
modules of one processing pipeline)
00
Disable: clock for matrix0 is disabled
01
Automatic: clock is enabled if unit is used, frequency is
defined by the register setting for this pipeline (see
[pipeline_name]_CLK register)
10
Reserved
11
Full: clock for matrix0 is without gating
Selects the source for the src input of the matrix0 module.
00000
Disable
00100
Selects fetch3
01111
Selects layerblend0
10000
Selects layerblend1
10001
Selects layerblend2
01101
Selects rop1
01100
Selects rop0
Fujitsu Semiconductor Europe GmbH
20 - 73
Revised 24/7/13
Iris-SDL Register Descriptions
20.58 Pixelbus Configuration for extdst0 unit register
(GFXPIX_extdst0_cfg)
The Pixelbus Configuration for unit extdst0 register is used to read the pixel processing path of the unit
and to control its shadow profile. It also selects the input source for the extdst0 module.
Figure 20-56: Pixelbus Configuration for unit extdst0 register
Reserved
[29:28]
extdst0_SEL
extdst0_SHDW
04
03
0
0
00
05
0
01
06
0
0
07
0
0
08
0
02
09
0
RWS
0
0
Reserved
Reserved
extdst0_src_SEL
10
0
12
0
11
13
0
14
0
16
0
0
17
0
15
18
21
0
19
22
0
0
23
0
[31:30]
20 - 74
0
24
0
Bit name
[25:5]
20
25
0
RW
R
Bit position
[27:26]
0
26
0
27
0
extdst0_SHDW
28
X
29
X
extdst0_SEL
30
0
0
Reserved
Reserved
31
GFXPIX_extdst0_cfg
Description
Used to read the extdst0 module’s pixel processing path:
00
The extdst0 module is not used
01
The extdst0 module from the extdst0 processing path is
selected
10
The extdst0 module from the store0 processing path is
selected
11
Reserved
Controls the shadow update characteristics of this register:
00
Disable: no shadow for extdst0_cfg register (continous update
of the register)
01
extdst0: extdst0_cfg register will be updated by the extdst0
pixel engine synchronizer
10
store0: extdst0_cfg register will be updated by the store0 pixel
engine synchronizer
11
Enable: extdst0_cfg register will be updated by both the
extsdt0 and store0 pixel engine synchronizers
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[4:0]
extdst0_src_SEL
Revised 24/7/13
Selects the source for the src input of the extdst0 module.
0000
0
Disable
10011
Selects lut1
Fujitsu Semiconductor Europe GmbH
20 - 75
Revised 24/7/13
Iris-SDL Register Descriptions
20.59 Pixelbus Store0 Sync register (GFXPIX_STORE0_SYNC)
The Pixelbus Store0 Sync register activates and controls the processing pipelines (store0 and extdst0)
and configures the synchronization of the store0 pipeline with the Pixel Engine synchronizer.
Figure 20-57: Pixelbus Store0 Sync register
Bit name
[31:6]
Reserved
[5:4]
STORE0_MST_EN
[3:2]
1
20 - 76
STORE0_SLV_EN
STORE0_SYNC_R
ESET_N
These are the enable bits for the master pipeline:
00
The master pipelines are disabled.
01
extdst0 is enabled, store0 is disabled
10
store0 is enabled, extdst0 is disabled
11
Reserved
These are the enable bits for the slave pipeline:
00
The slave pipelines are disabled.
01
extdst0 is enabled, store0 is disabled
10
store0 is enabled, extdst0 is disabled
11
Reserved
Executes a software reset of the synchronization state machine and
forces a reload of configuration shadow registers:
0
Execute software reset and config shadow registers reload
1
Active state
Fujitsu Semiconductor Europe GmbH
00
W
0
Description
STORE0_START
01
RW
1
RW
RW
STORE0_SLV_EN
STORE0_SYNC_RESET_N
02
0
03
0
05
0
04
06
0
STORE0_MST_EN
07
0
Reserved
Bit position
0
08
11
0
0
12
0
0
13
0
09
14
0
10
15
0
0
16
0
17
0
20
0
0
21
0
18
22
0
0
23
0
19
24
Reserved
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_STORE0_SYNC
Iris-SDL Register Descriptions
0
STORE0_START
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Start synchronization with store0 pixel engine synchronizer:
0
No effect
1
Start synchronization
20 - 77
Revised 24/7/13
Iris-SDL Register Descriptions
20.60 Pixelbus Store0 Sync Status register
(GFXPIX_STORE0_SYNC_STAT)
The Pixelbus Store0 Sync Status register reads the status of the store0 processing pipeline.
Figure 20-58: Pixelbus Store0 Sync Status register
Bit name
[31:5]
Reserved
[4:3]
STORE0_KICK_C
NT_extdst0
[2:1]
20 - 78
STORE0_KICK_C
NT_store0
01
00
X
STORE0_SYNC_BUSY
R
R
R
STORE0_KICK_CNT_store0
X
02
04
X
X
05
0
03
06
0
0
0
Reserved
Bit position
X
07
STORE0_KICK_CNT_extdst0
08
11
0
0
12
0
0
13
0
09
14
0
10
15
0
0
16
0
17
20
0
0
21
0
0
22
0
18
23
0
19
24
Reserved
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_STORE0_SYNC_STAT
Description
Reads the status of the extdst0 pipeline:
00
EMPTY: The pipeline is empty with no pending kick
01
RUNNING: The pipeline is running
10
RUNNING_RETRIGGERED: The pipeline is running and the
next frame is already kicked
11
Reserved
Reads the status of the store0 pipeline:
00
EMPTY: The pipeline is empty with no pending kick
01
RUNNING: The pipeline is running
10
RUNNING_RETRIGGERED: The pipeline is running and the
next frame is already kicked
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
0
STORE0_SYNC_B
USY
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Reads the status of the store0 pixel engine synchronizer:
0
Not busy
1
Busy
20 - 79
Revised 24/7/13
Iris-SDL Register Descriptions
20.61 Pixelbus Extdst0 Sync register (GFXPIX_EXTDST0_SYNC)
The Pixelbus Extdst0 Sync register activates and controls the processing pipelines (store0 and extdst0)
and configures the synchronization of the extdst0 pipeline with the Pixel Engine synchronizer.
Figure 20-59: Pixelbus Extdst0 Sync register
Bit name
[31:6]
Reserved
[5:4]
EXTDST0_MST_EN
[3:2]
1
20 - 80
EXTDST0_SLV_EN
EXTDST0_SYNC_R
ESET_N
00
W
0
EXTDST0_START
01
RW
1
EXTDST0_SYNC_RESET_N
02
EXTDST0_SLV_EN
RW
RW
0
0
03
0
05
0
04
06
0
EXTDST0_MST_EN
07
0
Reserved
Bit position
0
08
0
11
0
09
12
0
10
13
0
0
14
0
0
15
0
19
0
16
20
0
17
21
0
0
22
0
0
23
0
18
24
Reserved
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_EXTDST0_SYNC
Description
These are the enable bits for the master pipeline:
00
The master pipelines are disabled.
01
extdst0 is enabled, store0 is disabled
10
store0 is enabled, extdst0 is disabled
11
Reserved
These are the enable bits for the slave pipeline:
00
The slave pipelines are disabled.
01
extdst0 is enabled, store0 is disabled
10
store0 is enabled, extdst0 is disabled
11
Reserved
Executes a software reset of the synchronization state machine and
forces a reload of configuration shadow registers:
0
Execute software reset and config shadow registers reload
1
Active state
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
0
EXTDST0_START
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Start synchronization with extdst0 pixel engine synchronizer:
0
No effect
1
Start synchronization
20 - 81
Revised 24/7/13
Iris-SDL Register Descriptions
20.62 Pixelbus Extdst0 Sync Status register
(GFXPIX_EXTDST0_SYNC_STAT)
The Pixelbus Extdst0 Sync Status register reads the status of the extdst0 processing pipeline.
Figure 20-60: Pixelbus Extdst0 Sync Status register
Bit name
[31:5]
Reserved
[4:3]
EXTDST0_KICK_C
NT_extdst0
[2:1]
20 - 82
EXTDST0_KICK_C
NT_store0
01
00
X
EXTDST0_SYNC_BUSY
R
R
R
EXTDST0_KICK_CNT_store0
X
02
04
X
X
05
0
03
06
0
0
0
Reserved
Bit position
X
07
EXTDST0_KICK_CNT_extdst0
08
11
0
0
12
0
0
13
0
09
14
0
10
15
0
0
16
0
17
20
0
0
21
0
0
22
0
18
23
0
19
24
Reserved
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_EXTDST0_SYNC_STAT
Description
Reads the status of the extdst0 pipeline:
00
EMPTY: The pipeline is empty with no pending kick
01
RUNNING: The pipeline is running
10
RUNNING_RETRIGGERED: The pipeline is running and the
next frame is already kicked
11
Reserved
Reads the status of the store0 pipeline:
00
EMPTY: The pipeline is empty with no pending kick
01
RUNNING: The pipeline is running
10
RUNNING_RETRIGGERED: The pipeline is running and the
next frame is already kicked
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
0
EXTDST0_SYNC_
BUSY
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Reads the status of the extdst0 pixel engine synchronizer:
0
Not busy
1
Busy
20 - 83
Revised 24/7/13
Iris-SDL Register Descriptions
20.63 Store0 Unit Clock Throttling register (GFXPIX_STORE0_CLK)
The Store0 Unit Clock Throttling register is used if the xxx_CLKEN bitfield of a unit (e.g. lut1_CLKEN)
is configured to use automatic mode. It disables the clock of the respective unit in the store0 pipeline or
configures its speed.
Figure 20-61: Store0 Unit Clock Throttling register
Bit name
[31:8]
Reserved
[7:0]
STORE0_DIV
01
00
0
04
0
0
05
0
02
06
0
03
07
1
0
08
0
RW
Reserved
Bit position
0
09
STORE0_DIV
10
12
0
0
13
0
0
14
0
11
15
0
0
16
17
0
0
18
20
0
19
21
0
0
22
0
0
23
0
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_STORE0_CLK
Description
This bitfield is used if the xxx_CLKEN bitfield of a unit (e.g.
lut1_CLKEN) is configured to use automatic mode. It disables the clock
of the respective unit in the store0 pipeline or configures its speed.
The set value is the dividing factor (the ratio is the decimal register
value divided by 128). Values above 128 are reserved.
00000000
OFF: The clock is disabled
...
Examples:
01h = 00000001 =
1/128 = max. speed * 0.0078125
10h = 00010000 =
16/128 = max. speed * 0.125
10000000
20 - 84
MAX: The clock runs at maximum speed (10000000bin =
80h = 128dec, 128/128 = 1, therefore ratio of 1:1 = max.
speed)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.64 Extdst0 Unit Clock Throttling register (GFXPIX_EXTDST0_CLK)
The Extdst0 Unit Clock Throttling register is used if the xxx_CLKEN bitfield of a unit (e.g. lut1_CLKEN)
is configured to use automatic mode. It disables the clock of the respective unit in the extdst0 pipeline
or configures its speed.
Figure 20-62: Extdst0 Unit Clock Throttling register
Bit name
[31:8]
Reserved
[7:0]
EXTDST0_DIV
05
04
0
0
00
06
0
01
07
1
0
08
0
0
09
0
02
10
0
0
11
0
03
12
0
RW
Reserved
Bit position
0
13
0
EXTDST0_DIV
14
0
20
0
15
21
0
0
22
0
16
23
0
17
24
0
0
25
0
0
26
0
18
27
0
0
28
0
19
29
0
0
30
0
Reserved
31
0
GFXPIX_EXTDST0_CLK
Description
This bitfield is used if the xxx_CLKEN bitfield of a unit (e.g. lut1_CLKEN)
is configured to use automatic mode. It disables the clock of the
respective unit in the extdst0 pipeline or configures its speed.
The set value is the dividing factor (the ratio is the decimal register value
divided by 128). Values above 128 are reserved.
00000000
OFF: The clock is disabled
...
Examples:
01h = 00000001 =
1/128 = max. speed * 0.0078125
10h = 00010000 =
16/128 = max. speed * 0.125
10000000
Fujitsu Semiconductor Europe GmbH
MAX: The clock runs at maximum speed (10000000bin =
80h = 128dec, 128/128 = 1, therefore ratio of 1:1 = max.
speed)
20 - 85
Revised 24/7/13
Iris-SDL Register Descriptions
20.65 Pixel Engine Blitblend Control register
(GFXPIX_blend0_Control)
The Pixel Engine Blitblend Control register is used to set the operation mode of a Pixel Engine’s Blitblend
module.
Figure 20-63: Pixel Engine Blitblend Control register
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Mode
Bit position
Bit name
Description
31
SHD_UPD
Overrides the standard shadow load mechanisms and constantly loads
shadows. Please note, that usage of this functionality is for debugging
purposes only and can cause unintended behavior of the blitblend unit
(such as corrupted data etc.)
[30:1]
Reserved
0
Mode
This bit sets the operation mode for the Pixel Engine’s Blitblend module.
0
Neutral Mode: routes pixels and commands from the
primary input directly to the output.
1
Normal Operation Mode (blitblending)
Fujitsu Semiconductor Europe GmbH
0
RWS
Table 20-25: Pixel Engine Blitblend Control register bits
20 - 86
00
10
0
12
0
0
13
0
11
14
0
0
15
0
Reserved
Reserved
0
RW
0
16
17
0
22
0
18
23
0
19
24
0
0
25
0
0
26
0
20
27
0
0
28
0
21
29
0
0
30
0
SHD_UPD
31
GFXPIX_blend0_Control
Iris-SDL Register Descriptions
Revised 24/7/13
20.66 Pixel Engine Blitblend Constant Color register
(GFXPIX_blend0_ConstantColor)
The Pixel Engine Blitblend ConstantColor register is used to define the components of a constant color
for blending operations.
Figure 20-64: Pixel Engine Blitblend ConstantColor register
01
00
0
0
04
0
02
05
0
0
06
0
03
07
0
0
08
0
RWS
RWS
ConstantColorBlue
ConstantColorAlpha
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
RWS
RWS
0
17
0
20
0
18
21
0
19
22
0
0
23
0
0
24
0
ConstantColorGreen
25
0
26
0
28
0
27
29
0
ConstantColorRed
30
0
0
31
0
GFXPIX_blend0_ConstantColor
Table 20-26: Pixel Engine Blitblend ConstantColor register
Bit position
Bit name
Description
[31:24]
ConstantColorRed
The 8 bits define the value of the red color component for the
constant color used for blitblending.
[23:16]
ConstantColorGreen
The 8 bits define the value of the green color component for the
constant color used for blitblending.
[15:8]
ConstantColorBlue
The 8 bits define the value of the blue color component for the
constant color used for blitblending.
[7:0]
ConstantColorAlpha
The 8 bits define the value of the alpha color component for the
constant color used for blitblending.
Fujitsu Semiconductor Europe GmbH
20 - 87
Revised 24/7/13
Iris-SDL Register Descriptions
20.67 Pixel Engine Blitblend OpenGL Red Function register
(GFXPIX_blend0_ColorRedBlendFunction)
The Pixel Engine Blitblend ColorRedBlendFunction register is used to define the Open GL blending
function for the red components of the blending operation.
Figure 20-65: Pixel Engine Blitblend Red Function register
06
05
04
03
02
01
00
0
0
0
0
0
0
0
07
08
0
RWS
0
0
RWS
BlendFuncColor
RedSrc
12
0
1
13
0
09
14
0
10
15
0
1
16
0
0
17
0
11
18
0
0
19
0
24
1
20
25
1
0
26
0
21
27
0
0
28
0
22
29
0
23
30
0
BlendFuncColor
RedDst
31
0
GFXPIX_blend0_ColorRedBlendFunction
Table 20-27: Pixel Engine Blitblend Red Function register
Bit position
20 - 88
Bit name
Description
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[31:16]
BlendFuncCol
orRedDst
Revised 24/7/13
Defines the Open GL blending function for the destination red component
of the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
20 - 89
Revised 24/7/13
[15:0]
20 - 90
Iris-SDL Register Descriptions
BlendFuncCol
orRedSrc
Defines the Open GL blending function for the source red component of
the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.68 Pixel Engine Blitblend OpenGL Green Function register
(GFXPIX_blend0_ColorGreenBlendFunction)
The Pixel Engine Blitblend ColorGreenBlendFunction register is used to define the Open GL blending
function for the green components of the blending operation.
Figure 20-66: Pixel Engine Blitblend Green Function register
01
00
0
08
1
0
09
1
02
10
0
0
11
0
03
12
0
0
13
0
04
14
0
0
15
0
05
16
0
06
17
0
0
18
0
0
19
0
07
20
0
0
RWS
0
0
RWS
BlendFuncColor
GreenSrc
21
0
22
23
26
0
24
27
0
BlendFuncColor
GreenDst
28
0
1
29
0
25
30
0
1
31
0
GFXPIX_blend0_ColorGreenBlendFunction
Table 20-28: Pixel Engine Blitblend Green Function register
Bit position
Bit name
Description
Fujitsu Semiconductor Europe GmbH
20 - 91
Revised 24/7/13
[31:16]
20 - 92
Iris-SDL Register Descriptions
BlendFuncCol
orGreenDst
Defines the Open GL blending function for the destination green
component of the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[15:0]
BlendFuncCol
orGreenSrc
Revised 24/7/13
Defines the Open GL blending function for the source green component of
the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
20 - 93
Revised 24/7/13
Iris-SDL Register Descriptions
20.69 Pixel Engine Blitblend OpenGL Blue Function register
(GFXPIX_blend0_ColorBlueBlendFunction)
The Pixel Engine Blitblend ColorBlueBlendFunction register is used to define the Open GL blending
function for the blue components of the blending operation.
Figure 20-67: Pixel Engine Blitblend Blue Function register
06
05
04
03
02
01
00
0
0
0
0
0
0
0
07
08
0
RWS
0
0
RWS
BlendFuncColor
BlueSrc
12
0
1
13
0
09
14
0
10
15
0
1
16
0
0
17
0
11
18
0
0
19
0
24
1
20
25
1
0
26
0
21
27
0
0
28
0
22
29
0
23
30
0
BlendFuncColor
BlueDst
31
0
GFXPIX_blend0_ColorBlueBlendFunction
Table 20-29: Pixel Engine Blitblend Blue Function register
Bit position
20 - 94
Bit name
Description
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[31:16]
BlendFuncCol
orBlueDst
Revised 24/7/13
Defines the Open GL blending function for the destination blue component
of the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
20 - 95
Revised 24/7/13
[15:0]
20 - 96
Iris-SDL Register Descriptions
BlendFuncCol
orBlueSrc
Defines the Open GL blending function for the source blue component of
the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.70 Pixel Engine Blitblend OpenGL Alpha Function register
(GFXPIX_blend0_ColorAlphaBlendFunction)
The Pixel Engine Blitblend ColorAlphaBlendFunction register is used to define the Open GL blending
function for the alpha components of the blending operation.
Figure 20-68: Pixel Engine Blitblend Alpha Function register
01
00
0
08
1
0
09
1
02
10
0
0
11
0
03
12
0
0
13
0
04
14
0
0
15
0
05
16
0
06
17
0
0
18
0
0
19
0
07
20
0
0
RWS
0
0
RWS
BlendFuncColor
AlphaSrc
21
0
22
23
26
0
24
27
0
BlendFuncColor
AlphaDst
28
0
1
29
0
25
30
0
1
31
0
GFXPIX_blend0_ColorAlphaBlendFunction
Table 20-30: Pixel Engine Blitblend Alpha Function register
Bit position
Bit name
Description
Fujitsu Semiconductor Europe GmbH
20 - 97
Revised 24/7/13
[31:16]
20 - 98
Iris-SDL Register Descriptions
BlendFuncCol
orAlphaDst
Defines the Open GL blending function for the destination alpha
component of the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[15:0]
BlendFuncCol
orAlphaSrc
Revised 24/7/13
Defines the Open GL blending function for the source alpha component of
the blending operation:
(see also: http://www.opengl.org/sdk/docs/man/xhtml/glBlendFunc.xml)
and http://wiki.delphigl.com/index.php/glBlendFunc
0H
GL_ZERO
1H
GL_ONE
300H
GL_SRC_COLOR
301H
GL_ONE_MINUS_SRC_COLOR
302H
GL_SRC_ALPHA
303H
GL_ONE_MINUS_SRC_ALPHA
304H
GL_DST_ALPHA
305H
GL_ONE_MINUS_DST_ALPHA
306H
GL_DST_COLOR
307H
GL_ONE_MINUS_DST_COLOR
308H
GL_SRC_ALPHA_SATURATE
8001H
GL_CONSTANT_COLOR
8002H
GL_ONE_MINUS_CONSTANT_COLOR
8003H
GL_CONSTANT_ALPHA
8004H
GL_ONE_MINUS_CONSTANT_ALPHA
Fujitsu Semiconductor Europe GmbH
20 - 99
Revised 24/7/13
Iris-SDL Register Descriptions
20.71 Pixel Engine Blitblend OpenGL/VG Blending Modes register
(GFXPIX_blend0_BlendMode1)
The Pixel Engine Blitblend BlendMode1 register is used to define the Open GL and Open VG blending
modes for the red and green components of the blending operation.
Figure 20-69: Pixel Engine Blitblend Open GL/VG Blending Modes register
06
05
04
03
02
01
00
0
0
0
1
1
0
RWS
BlendModeColorRed
0
08
0
07
09
RWS
0
0
10
12
0
0
13
0
0
14
0
11
15
1
0
16
0
19
0
17
20
0
1
21
0
18
22
0
1
23
0
24
0
BlendModeColorGreen
25
0
28
0
26
29
0
0
30
0
27
31
1
GFXPIX_blend0_BlendMode1
Table 20-31: Pixel Engine Blitblend Open GL/VG Blending Modes register
Bit position
20 - 100
Bit name
Description
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[31:16]
BlendModeColorGreen
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Defines the Open GL and Open VG blending function for the color
green component of the blending operation:
8006H
GL_FUNC_ADD
8007H
GL_MIN
8008H
GL_MAX
800AH
GL_FUNC_SUBTRACT
800BH
GL_FUNC_REVERSE_SUBTRACT
2000H
VG_BLEND_SRC
2001H
VG_BLEND_SRC_OVER
2002H
VG_BLEND_DST_OVER
2003H
VG_BLEND_SRC_IN
2004H
VG_BLEND_DST_IN
2005H
VG_BLEND_MULTIPLY
2006H
VG_BLEND_SCREEN
2007H
VG_BLEND_DARKEN
2008H
VG_BLEND_LIGHTEN
2009H
VG_BLEND_ADDITIVE
20 - 101
Revised 24/7/13
[15:0]
20 - 102
Iris-SDL Register Descriptions
BlendModeColorRed
Defines the Open GL and Open VG blending function for the color
red component of the blending operation:
8006H
GL_FUNC_ADD
8007H
GL_MIN
8008H
GL_MAX
800AH
GL_FUNC_SUBTRACT
800BH
GL_FUNC_REVERSE_SUBTRACT
2000H
VG_BLEND_SRC
2001H
VG_BLEND_SRC_OVER
2002H
VG_BLEND_DST_OVER
2003H
VG_BLEND_SRC_IN
2004H
VG_BLEND_DST_IN
2005H
VG_BLEND_MULTIPLY
2006H
VG_BLEND_SCREEN
2007H
VG_BLEND_DARKEN
2008H
VG_BLEND_LIGHTEN
2009H
VG_BLEND_ADDITIVE
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.72 Pixel Engine Blitblend OpenGL/VG Blending Modes register
(GFXPIX_blend0_BlendMode2)
The Pixel Engine Blitblend BlendMode2 register is used to define the Open GL and Open VG blending
modes for the blue and alpha components of the blending operation.
Figure 20-70: Pixel Engine Blitblend Open GL/VG Blending Modes register
RWS
RWS
BlendModeColorBlue
00
08
0
01
09
0
0
10
0
1
11
0
02
12
0
1
13
0
03
14
0
0
15
1
04
16
0
0
17
1
05
18
1
06
19
0
0
20
0
0
21
0
07
22
0
23
0
24
0
0
25
0
BlendModeColorAlpha
26
28
0
0
29
0
27
30
0
0
31
1
GFXPIX_blend0_BlendMode2
Table 20-32: Pixel Engine Blitblend Open GL/VG Blending Modes register
Bit
position
Bit name
Fujitsu Semiconductor Europe GmbH
Description
20 - 103
Revised 24/7/13
[31:16]
20 - 104
BlendModeColorAlpha
Iris-SDL Register Descriptions
Defines the Open GL and Open VG blending function for the alpha
component of the blending operation:
8006H
GL_FUNC_ADD
8007H
GL_MIN
8008H
GL_MAX
800AH
GL_FUNC_SUBTRACT
800BH
GL_FUNC_REVERSE_SUBTRACT
2000H
VG_BLEND_SRC
2001H
VG_BLEND_SRC_OVER
2002H
VG_BLEND_DST_OVER
2003H
VG_BLEND_SRC_IN
2004H
VG_BLEND_DST_IN
2005H
VG_BLEND_MULTIPLY
2006H
VG_BLEND_SCREEN
2007H
VG_BLEND_DARKEN
2008H
VG_BLEND_LIGHTEN
2009H
VG_BLEND_ADDITIVE
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[15:0]
BlendModeColorBlue
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Defines the Open GL and Open VG blending function for the color blue
component of the blending operation:
8006H
GL_FUNC_ADD
8007H
GL_MIN
8008H
GL_MAX
800AH
GL_FUNC_SUBTRACT
800BH
GL_FUNC_REVERSE_SUBTRACT
2000H
VG_BLEND_SRC
2001H
VG_BLEND_SRC_OVER
2002H
VG_BLEND_DST_OVER
2003H
VG_BLEND_SRC_IN
2004H
VG_BLEND_DST_IN
2005H
VG_BLEND_MULTIPLY
2006H
VG_BLEND_SCREEN
2007H
VG_BLEND_DARKEN
2008H
VG_BLEND_LIGHTEN
2009H
VG_BLEND_ADDITIVE
20 - 105
Revised 24/7/13
Iris-SDL Register Descriptions
20.73 Pixel Engine Blitblend Primary Control Word register
(GFXPIX_blend0_PRIM_CONTROL_WORD)
The Pixel Engine Blitblend Primary Control Word register is used to hold the value of the last control word
received on the primary input.
Figure 20-71: Pixel Engine Blitblend Primary Control Word register
10
09
08
07
06
05
04
03
02
01
00
X
X
X
X
X
X
X
X
X
X
X
12
X
11
13
X
14
X
16
X
X
17
X
15
18
X
X
19
X
R
P_VAL
20
X
22
X
21
23
X
X
24
X
27
X
25
28
X
X
29
X
26
30
X
X
31
X
GFXPIX_blend0_PRIM_CONTROL_WORD
Table 20-33: Pixel Engine Blitblend Primary Control Word register bits
Bit position
Bit name
Description
[31:1]
P_VAL
The value of the last control word received on the primary input.
If a 39 bit pixel channel is connected, the mapping is as follows:
P_VAL[31:0] = { data[37:22], data[19:12], data[9:2] }.
20 - 106
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.74 Pixel Engine Blitblend Secondary Control Word register
(GFXPIX_blend0_SEC_CONTROL_WORD)
The Pixel Engine Blitblend Primary Control Word register is used to hold the value of the last control
word received on the secondary input.
Figure 20-72: Pixel Engine Blitblend Secondary Control Word register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
X
X
17
X
15
18
X
X
19
X
X
R
S_VAL
20
22
X
X
23
X
21
24
X
X
25
X
28
X
26
29
X
X
30
X
27
31
X
GFXPIX_blend0_SEC_CONTROL_WORD
Table 20-34: Pixel Engine Blitblend Secondary Control Word register bits
Bit position
Bit name
Description
[31:1]
S_VAL
The value of the last control word received on the secondary input.
If a 39 bit pixel channel is connected, the mapping is as follows:
P_VAL[31:0] = { data[37:22], data[19:12], data[9:2] }.
Fujitsu Semiconductor Europe GmbH
20 - 107
Revised 24/7/13
Iris-SDL Register Descriptions
20.75 Pixel Engine CLUT Control register (GFXPIX_clut<n>_Control)
The Pixel Engine CLUT Control register is used to control the operations and modes of the Pixel Engine
Color Look-Up Table (CLUT).
Figure 20-73: Pixel Engine CLUT Control register
00
01
MODE
RWS
0
0
02
COL_8BIT
RWS
0
03
B_EN
RW
0
04
G_EN
RW
0
05
06
R_EN
RW
RWS
0
0
0
08
0
07
09
1
0
10
0
Reserved
Reserved
IDX_BITS
11
12
0
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
0
16
23
0
24
WRITE_TIMEOUT
RW1 C
RW1 C
0
0
25
26
0
READ_TIMEOUT
27
0
Reserved
Reserved
28
29
0
RW
0
0
30
0
SHD_UPD
31
GFXPIX_clu<n>t_Control
Table 20-35: Pixel Engine CLUT Control register bits
Bit position
Bit name
Description
31
SHD_UPD
Configures the shadow update mode.
0
NORMAL: The shadow registers are updated with
the pipeline control word
1
WRITE_THROUGH: The shadow registers are
updated constantly
[30:26]
Reserved
25
READ_TIMEOUT
If a timeout occurs when reading from the CLUT, this bit will read ‘1’.
To clear the ‘1’, write a ‘1’ to this bit.
24
WRITE_TIMEOUT
If a timeout occurs when writing to the CLUT, this bit will read ‘1’. To
clear the ‘1’, write a ‘1’ to this bit.
[23:10]
Reserved
[9:6]
IDX_BITS
Defines the number of bits for the index input. Default is 8 bits (i.e.
256 addressable table entries).
5
R_EN
Write enable control for red color component writes.
20 - 108
0
DISABLE: red color component writes are disabled.
1
ENABLE: red color component writes are enabled.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
4
3
2
[1:0]
G_EN
B_EN
COL_8BIT
MODE
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Write enable control for green color component writes.
0
DISABLE: green color component writes are
disabled.
1
ENABLE: green color component writes are
enabled.
Write enable control for blue color component writes.
0
DISABLE: blue color component writes are
disabled.
1
ENABLE: blue color component writes are enabled.
Dither enable control for the output color (R,G and B)
0
DISABLE: 10 bit output
1
ENABLE: 8 bit (dithered) output
Configures the operation mode for the CLUT.
00
NEUTRAL: Activate neutral mode (the CLUT is not
used and the incoming pixel is used for output)
01
LUT: Activate color look-up mode. For the incoming
8 bit color value, a 10 bit color value (8.2bit ) is
looked up.
10
INDEX_10BIT: Activate 10 bit color index table
mode. The incoming red color channel is used as an
index value to address a specific color in the CLUT's
palette (max. 256 colors are therefore addressable).
The LUT is used for three 10 bit color values. The
incoming alpha is bypassed
11
INDEX_RGBA: Activate RGBA color index table
mode. The incoming red color channel is used as an
index value to address a specific color in the CLUT's
palette (max. 256 colors are therefore addressable).
The LUT is used for three 8bit color values and a 6
bit alpha value.
20 - 109
Revised 24/7/13
Iris-SDL Register Descriptions
20.76 Pixel Engine CLUT LUT registers (GFXPIX_clut<n>_LUT[0 ...
255])
The Pixel Engine CLUT LUT registers are used to store the 256 look-up colors (indexed colors) used in
indexed color mode.
Figure 20-74: Pixel Engine CLUT LUT registers
01
00
X
RW
BLUE
X
05
X
02
06
X
X
07
X
03
08
X
X
09
X
04
10
X
RW
X
RW
X
11
X
12
15
X
X
16
X
13
17
X
14
18
X
X
19
X
X
20
X
RED
GREEN
21
X
25
X
22
26
X
23
27
X
X
28
X
X
29
X
Reserved
X
24
30
X
Reserved
31
GFXPIX_clut<n>_LUT[0 ... 255]
Table 20-36: Pixel Engine CLUT LUT registers
Bit position
Bit name
[31:30]
Reserved
[29:20]
RED
10 bits for the red color component of an indexed color.
[19:10]
GREEN
10 bits for the green color component of an indexed color.
[9:0]
BLUE
10 bits for the blue color component of an indexed color.
20 - 110
Description
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.77 Pixel Engine ExtDst Control register
(GFXPIX_extdst0_CONTROL)
The Pixel Engine ExtDst Control register is used to define the alpha component generation mode and
kick signal mode (or to trigger a kick signal) of the ExtDst unit.
Figure 20-75: Pixel Engine ExtDst Control register
05
0
KICK
0
W
RWS
0
00
06
0
01
07
0
KICK_MODE
08
0
RW
09
0
0
10
0
0
11
0
Reserved
02
12
0
0
13
0
03
14
0
04
15
0
ALPHA_MODE
16
17
0
0
18
19
0
Reserved
20
0
0
21
0
25
0
22
26
0
23
27
0
0
28
0
0
29
0
24
30
0
0
31
0
GFXPIX_extdst0_CONTROL
Table 20-37: Pixel Engine ExtDst Control register bits
Bit position
Bit name
[31:6]
Reserved
[5:3]
ALPHA_MODE
Description
Output alpha component generation mode. Values not listed below are
ignored. This can be used in the Signature Unit as a bitmask.
000
OFF: Alpha output is 0.
001
ON: Alpha output is 1.
010
OR: Alpha output is subject to logical OR operation.
011
AND: Alpha output is subject to logical AND operation.
100
MSBIT: Alpha output is the MSB of the input alpha value.
2
KICK
Writing a 1 forces a kick signal, independant of the KICK_MODE setting.
[1:0]
KICK_MODE
Defines the kick signal generation mode.
00
OFF: Kick signal is not generated
01
CONTINOUS_NON_OVERLAP: Kick signal is generated
after the last pixel has been received.
10
CONTINOUS_OVERLAP: Kick signal is generated after
the control word has been received.
11
EXTERNAL: Kick signal is generated by an external
source.
Fujitsu Semiconductor Europe GmbH
20 - 111
Revised 24/7/13
Iris-SDL Register Descriptions
20.78 Pixel Engine ExtDst Status register (GFXPIX_extdst0_STATUS)
The Pixel Engine ExtDst Status register is used to monitor the status of the ExtDst (External Destination)
unit.
Figure 20-76: Pixel Engine ExtDst Status register
EMPTY
R
X
00
01
03
X
KICK_CNT
04
X
R
05
X
X
06
X
X
07
X
Reserved
X
02
08
X
09
10
Reserved
12
X
X
13
X
11
14
X
X
15
X
16
E_KERR_STS
RW1C
0
17
SW_KERR_STS
RW1C
0
18
19
CNT_ERR_STS
RW1C
X
X
Reserved
0
X
21
X
20
22
X
23
26
X
X
27
X
X
28
X
24
29
X
25
30
X
Reserved
31
X
GFXPIX_extdst0_STATUS
Table 20-38: Pixel Engine ExtDst Status register
Bit position
Bit name
[31:19]
Reserved
18
CNT_ERR_STS
A pixel count error is signalled by a 1 in this bit. Write a 1 to clear the bit
again.
17
SW_KERR_STS
A 1 in this bit signals an error caused by the reception of a software kick
although a kick is already pending.
16
E_KERR_STS
A 1 in this bit signals an error caused by the reception of an external kick
although a kick is already pending.
[15:3]
Reserved
2
EMPTY
[1:0]
20 - 112
KICK_CNT
Description
Flags that the extdst block is empty (all pixels out).
0
Valid pixels are in the extdst block.
1
The extdst block is empty.
Signals that the pipeline is empty with no kick pending.
00
EMPTY: The pipeline is empty and a kick is not pending.
01
RUNNING: The pipeline is running.
10
RUNNING_RETRIGGERED: The pipeline is running
and the next frame has been kicked.
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.79 Pixel Engine ExtDst Control Word register
(GFXPIX_extdst0_CONTROL_WORD)
The Pixel Engine ExtDst Control Word register is used to hold the value of the last control word received
for the ExtDst (External Destination) unit.
Figure 20-77: Pixel Engine ExtDst Control Word register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
X
X
X
X
X
X
X
X
X
X
X
X
X
16
X
X
17
X
X
18
X
15
19
X
X
20
X
R
CW_VAL
21
22
X
23
X
26
X
X
27
X
24
28
X
X
29
X
25
30
X
X
31
X
GFXPIX_extdst0_CONTROL_WORD
Table 20-39: Pixel Engine ExtDst Control Word register bits
Bit position
Bit name
Description
[31:1]
CW_VAL
The value of the last control word received for the ExtDst (External
Destination) unit.
Fujitsu Semiconductor Europe GmbH
20 - 113
Revised 24/7/13
Iris-SDL Register Descriptions
20.80 Pixel Engine ExtDst Current Pixel register
(GFXPIX_extdst0_CUR_PIXEL_CNT)
The Pixel Engine ExtDst Current Pixel register is used to read the current pixel count (vertical lines and
horizontal pixels) of the frame currently running in the ExtDst unit.
Figure 20-78: Pixel Engine ExtDst Current Pixel register
07
06
05
04
03
02
01
00
X
X
X
X
X
X
X
X
12
X
08
13
X
R
R
C_XVAL
14
X
X
15
X
09
16
X
10
17
X
X
18
X
X
19
X
11
20
X
X
21
22
X
X
23
X
26
X
24
27
X
C_YVAL
28
X
X
29
X
25
30
X
X
31
X
GFXPIX_extdst0_CUR_PIXEL_CNT
Table 20-40: Pixel Engine ExtDst Current Pixel register bits
Bit position
Bit name
Description
[31:16]
C_YVAL
The value of the internal vertical line counter. The counter counts from
(maximum value - 1) to 0.
[15:0]
C_XVAL
The value of the internal horizontal pixel counter. The counter counts from
(maximum value - 1) to 0.
20 - 114
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.81 Pixel Engine ExtDst Last Pixel register
(GFXPIX_extdst0_LAST_PIXEL_CNT)
The Pixel Engine ExtDst Last Pixel register is used to read the pixel count between the last two control
words.
Figure 20-79: Pixel Engine ExtDst Last Pixel register
02
01
00
X
X
08
X
X
09
X
03
10
X
X
11
X
04
12
X
X
13
X
05
14
X
06
15
X
X
16
X
X
17
X
07
18
X
X
19
X
R
R
L_XVAL
20
X
24
X
21
25
X
X
26
X
22
27
X
23
28
X
X
29
X
X
30
X
L_YVAL
31
X
GFXPIX_extdst0_LAST_PIXEL_CNT
Table 20-41: Pixel Engine ExtDst Last Pixel register bits
Bit position
Bit name
Description
[31:16]
L_YVAL
The value of the vertical line counter.
[15:0]
L_XVAL
The value of the horizontal pixel counter.
Fujitsu Semiconductor Europe GmbH
20 - 115
Revised 24/7/13
Iris-SDL Register Descriptions
20.82 Pixel Engine Fetch Status register (GFXPIX_fetch<n>_Status)
The Pixel Engine Fetch Status register is used to monitor the status of a Fetch unit.
Figure 20-80: Pixel Engine Fetch Status register
Bit position
Bit name
[31:7]
Reserved
6
StatusComplete
A 1 indicates that the Fetch unit has completed all requested AXI bus
transfers.
5
StatusRequest
A 1 indicates that the Fetch unit is executing requests on the AXI bus
and waiting for an acknowledge.
4
StatusBuffersidle
A 1 indicates that the AXI interface buffers of the Fetch unit are idle.
[3:1]
Reserved
0
StatusBusy
20 - 116
00
01
StatusBusy
R
X
X
Table 20-42: Pixel Engine Fetch Status register bits
Description
A 1 indicates that the Fetch unit is busy.
Fujitsu Semiconductor Europe GmbH
X
02
03
Reserved
Reserved
X
04
StatusBuffersidl
R
X
05
StatursRequest
06
StatusComplete
R
07
X
R
08
X
X
09
X
Reserved
X
X
10
X
12
X
X
13
X
11
14
X
X
15
21
X
X
22
X
16
23
X
X
24
X
17
25
X
X
26
X
18
27
X
19
28
X
X
29
X
20
30
X
Reserved
31
X
GFXPIX_fetch<n>_Status
Iris-SDL Register Descriptions
Revised 24/7/13
20.83 Pixel Engine Fetch Burst Buffer Management register
(GFXPIX_fetch<n>_BurstBufferManagement)
The Pixel Engine Fetch Burst Buffer Management register is used to configure the AXI interface burst
buffers.
Figure 20-81: Pixel Engine Fetch Burst Buffer Management register
01
00
X
04
X
X
05
X
02
06
X
X
07
X
X
R
R
X
03
08
X
ManageBurstBu
ffers
09
10
11
X
X
12
X
X
Reserved
Reserved
BurstLengthFor
MaxBuffers
13
15
X
14
16
0
RWS
0
X
17
0
SetNumBuffers
18
21
0
19
22
0
1
23
0
RWS
1
0
24
0
20
25
0
27
0
26
28
0
SetBurstLength
29
X
30
X
X
Reserved
Reserved
31
GFXPIX_fetch<n>_BurstBufferManagement
Table 20-43: Pixel Engine Fetch Burst Buffer Management register bits
Bit position
Bit name
Description
[31:29]
Reserved
[28:24]
SetBurstLength
Set this to the burst length that should be used on the AXI interface.
Please note that SetNumBuffers * SetBurstLength has to be smaller or
equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that
bursts larger than 16 are not possible on the AXI interface.
Only a power of two value may be specified as the burst length.
[23:16]
SetNumBuffers
Set this to the number of bursts that should be buffered. Please note
that SetNumBuffers has to be smaller or equal to ManagedBurstBuffers
and SetNumBuffers * SetBurstLength has to be smaller or equal to
ManagedBurstBuffers * BurstLengthForMaxBuffers.
Must be either 4, 8 or 16.
[15:13]
Reserved
[12:8]
BurstLengthFor
MaxBuffers
The maximum Burst Length that can be used when
ManagedBurstBuffers burst buffers are used.
[7:0]
ManageBurstBuf
fers
The maximum number of burst buffers that can be administrated in the
AXI interface.
Fujitsu Semiconductor Europe GmbH
20 - 117
Revised 24/7/13
Iris-SDL Register Descriptions
20.84 Pixel Engine Fetch Base Address register
(GFXPIX_fetch<n>_BaseAddress)
The Pixel Engine Fetch Base Address register is used to set the byte aligned start address of the source
buffer for a fetch unit.
Figure 20-82: Pixel Engine Fetch Base Address register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
RWS
BaseAddress
21
22
0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXPIX_fetch<n>_BaseAddress
Table 20-44: Pixel Engine Fetch Base Address register bits
Bit position
Bit name
Description
[31:0]
BaseAddress
Byte aligned start address of the source buffer. For a pixel width of 32 bits
or RLD operations BaseAddress[1:0] has to be 0 and for a pixel width of
16 bit BaseAddress[0] has to be 0.
20 - 118
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.85 Pixel Engine Fetch Source Buffer Stride register
(GFXPIX_fetch<n>_SourceBufferStride)
The Pixel Engine Fetch Source Buffer Stride register is used to define the source buffer stride, used for
address generation.
Figure 20-83: Pixel Engine Fetch Source Buffer Stride register
09
08
07
06
0
0
0
0
RWS
Reserved
Strdie
00
10
0
01
11
0
0
12
0
0
13
0
02
14
0
0
15
0
03
16
0
0
17
0
04
18
0
0
19
0
05
20
0
0
21
22
0
0
23
0
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_fetch<n>_SourceBufferStride
Table 20-45: Pixel Engine Fetch Source Buffer Stride register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
Stride
Description
Source buffer stride in bytes minus one, used for address generation. For
a pixel width of 32 bits Stride has to be dividable by 4 and given minus one
and for a pixel width of 16 bit Stride has to be dividable by two and given
minus one.
Fujitsu Semiconductor Europe GmbH
20 - 119
Revised 24/7/13
Iris-SDL Register Descriptions
20.86 Pixel Engine Fetch Source Buffer Attributes register
(GFXPIX_fetch<n>_SourceBufferAttributes)
The Pixel Engine Fetch Source Buffer Attributes register is used to set the number of lines and the width
of the source buffer used for tiling.
Figure 20-84: Pixel Engine Fetch Source Buffer Attributes register
03
02
01
00
0
0
0
05
0
0
06
0
04
07
0
0
08
0
0
RWS
Reserved
Reserved
LineWidth
09
13
0
10
14
0
0
15
0
0
16
0
11
17
0
0
18
0
0
RWS
Reserved
12
19
0
22
0
20
23
0
0
24
0
21
25
0
LineCount
26
27
0
28
0
29
0
0
30
0
Reserved
31
0
GFXPIX_fetch<n>_SourceBufferAttributes
Table 20-46: Pixel Engine Fetch Source Buffer Attributes register bits
Bit position
Bit name
[31:12]
Reserved
[25:16]
LineCount
[15:10]
Reserved
[9:0]
LineWidth
20 - 120
Description
Number of lines of the source buffer minus one, needed for tiling.
Width of the source buffer in pixels minus one, needed for tiling.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.87 Pixel Engine Fetch Source Buffer Length register
(GFXPIX_fetch<n>_SourceBufferLength)
The Pixel Engine Fetch Source Buffer Length register is used to define the number of 32-bit words (minus 1) required to decode the RLE encoded source buffer.
Figure 20-85: Pixel Engine Fetch Source Buffer Length register
05
04
03
02
01
00
0
0
0
0
0
10
0
06
11
0
0
12
0
0
13
0
07
14
0
0
15
0
08
16
0
0
17
0
09
18
0
RLEWords
19
0
RWS
Reserved
0
0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
Reserved
31
0
GFXPIX_fetch<n>_SourceBufferLength
Table 20-47: Pixel Engine Fetch Source Buffer Length register bits
Bit position
Bit name
[31:21]
Reserved
[20:0]
RLEWords
Description
Number of 32-bit words minus one that are required to decode the run
length encoded source buffer. This field is only available in RLD type fetch
units.
Fujitsu Semiconductor Europe GmbH
20 - 121
Revised 24/7/13
Iris-SDL Register Descriptions
20.88 Pixel Engine Fetch Frame X Offset register
(GFXPIX_fetch<n>_FrameXOffset)
The Pixel Engine Fetch FrameXOffset register is used to determine the scan direction of a source buffer
and to define an X origin offset.
Figure 20-86: Pixel Engine Fetch Frame X Offset register
02
01
00
0
0
0
0
Reserved
Reserved
03
06
0
0
07
0
04
08
0
0
09
0
0
RWS
0
RWS
05
10
0
14
0
11
15
0
0
16
0
12
17
0
13
18
FrameXOffsetDec
imalPlaces
19
0
20
0
0
21
22
0
0
0
23
0
FrameXOffset
24
0
26
0
25
27
0
0
28
0
29
30
0
0
RWS
Reserved
Reserved
FrameXDirection
31
GFXPIX_fetch<n>_FrameXOffset
Table 20-48: Pixel Engine Fetch Frame X Offset register bits
Bit position
Bit name
Description
31
FrameXDirection
Changes X direction, settings this bit to one will cause scan
direction to be reversed. This field is not available in ROT type fetch
units.
[30:28]
Reserved
[27:16]
FrameXOffset
Frame X origin offset relative to the source buffer origin, given in
s11 two complements format.
[15:11]
FrameXOffsetDecim
alPlaces
Fractional bits of the X Offset. This field is only available in ROT
type fetch units.
[10:0]
Reserved
20 - 122
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.89 Pixel Engine Fetch Frame Y Offset register
(GFXPIX_fetch<n>_FrameYOffset)
The Pixel Engine Fetch FrameYOffset register is used to determine the scan direction of a source buffer
and to define an Y origin offset.
Figure 20-87: Pixel Engine Fetch Frame Y Offset register
02
01
00
0
0
0
Reserved
Reserved
0
06
0
03
07
0
0
08
0
04
09
0
0
10
0
RWS
0
RWS
05
11
14
0
0
15
0
12
16
0
0
17
0
13
18
FrameYOffsetDec
imalPlaces
19
0
20
0
0
21
22
0
0
0
23
0
FrameYOffset
24
0
26
0
25
27
0
0
28
0
29
30
0
0
RWS
Reserved
Reserved
FrameYDirection
31
GFXPIX_fetch<n>_FrameYOffset
Table 20-49: Pixel Engine Fetch Frame Y Offset register bits
Bit position
Bit name
Description
31
FrameYDirection
Changes Y direction, settings this bit to one will cause scan
direction to be reversed. This field is not available in ROT type fetch
units.
[30:28]
Reserved
[27:16]
FrameYOffset
Frame Y origin offset relative to the source buffer origin, given in
s11 two complements format.
[15:11]
FrameYOffsetDecim
alPlaces
Fractional bits of the Y Offset. This field is only available in ROT
type fetch units.
[10:0]
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 123
Revised 24/7/13
Iris-SDL Register Descriptions
20.90 Pixel Engine Fetch Frame Dimensions register
(GFXPIX_fetch<n>_FrameDimensions)
The Pixel Engine Fetch FrameDimensions register is used to determine the size of the frame and the
direction in which the rasterizer works in it.
Figure 20-88: Pixel Engine Fetch Frame Dimensionsregister
02
01
00
0
0
0
05
0
03
06
0
0
07
0
04
08
0
0
09
RWS
0
RWS
Reserved
Reserved
FrameWidth
10
13
0
0
14
0
0
15
0
11
16
0
0
17
0
12
18
21
0
19
22
0
0
23
0
0
24
0
20
25
0
0
26
0
FrameHeight
27
0
Reserved
Reserved
28
29
0
RWS
0
0
30
0
FrameSwapDirections
31
GFXPIX_fetch<n>_FrameDimensions
Table 20-50: Pixel Engine Fetch Frame Dimensions register bits
Bit position
Bit name
Description
31
FrameSwapDirections
Swaps X and Y directions, causes the rasterizer to first progress
in Y direction and once it reaches the end of the column
increment X by one and reset Y to FrameYOffset if set to one.
This field is not available in ROT type fetch units.
[30:26]
Reserved
[25:16]
FrameHeight
[15:10]
Reserved
[9:0]
FrameWidth
20 - 124
Frame height minus one
Frame width minus one
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.91 Pixel Engine Fetch DeltaXX register
(GFXPIX_fetch<n>_DeltaXX)
The Pixel Engine Fetch DeltaXX register is used to set the step size for a rotation operation of a ROT
type fetch unit.
Figure 20-89: Pixel Engine Fetch DeltaXX
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:23]
Reserved
[22:2]
DeltaXX
[1:0]
Reserved
Fujitsu Semiconductor Europe GmbH
Reserved
Description
Sets the DeltaXX stepsize for rotation operation, given in s6.14
twos complement notation. This field is only available in ROT
type fetch units.
20 - 125
0
0
RWS
Table 20-51: Pixel Engine Fetch DeltaXX register bits
Bit position
00
09
0
DeltaXX
Reserved
10
0
13
0
11
14
0
0
15
0
Reserved
0
12
16
19
0
0
20
0
17
21
0
0
22
0
18
23
0
0
24
25
0
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXPIX_fetch<n>_DeltaXX
Revised 24/7/13
Iris-SDL Register Descriptions
20.92 Pixel Engine Fetch DeltaXY register
(GFXPIX_fetch<n>_DeltaXY)
The Pixel Engine Fetch DeltaXY register is used to set the step size for a rotation operation of a ROT
type fetch unit.
Figure 20-90: Pixel Engine Fetch DeltaXY
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:23]
Reserved
[22:2]
DeltaXY
[1:0]
Reserved
20 - 126
Reserved
Description
Sets the DeltaXY stepsize for rotation operation, given in s6.14
twos complement notation. This field is only available in ROT
type fetch units.
Fujitsu Semiconductor Europe GmbH
0
0
RWS
Table 20-52: Pixel Engine Fetch DeltaXY register bits
Bit position
00
09
0
DeltaXY
Reserved
10
0
13
0
11
14
0
0
15
0
Reserved
0
12
16
19
0
0
20
0
17
21
0
0
22
0
18
23
0
0
24
25
0
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXPIX_fetch<n>_DeltaXY
Iris-SDL Register Descriptions
Revised 24/7/13
20.93 Pixel Engine Fetch DeltaYX register
(GFXPIX_fetch<n>_DeltaYX)
The Pixel Engine Fetch DeltaYX register is used to set the step size for a rotation operation of a ROT
type fetch unit.
Figure 20-91: Pixel Engine Fetch DeltaYX
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:23]
Reserved
[22:2]
DeltaYX
[1:0]
Reserved
Fujitsu Semiconductor Europe GmbH
Reserved
Description
Sets the DeltaYX stepsize for rotation operation, given in s6.14
twos complement notation. This field is only available in ROT
type fetch units.
20 - 127
0
0
RWS
Table 20-53: Pixel Engine Fetch DeltaYX register bits
Bit position
00
09
0
DeltaYX
Reserved
10
0
13
0
11
14
0
0
15
0
Reserved
0
12
16
19
0
0
20
0
17
21
0
0
22
0
18
23
0
0
24
25
0
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXPIX_fetch<n>_DeltaYX
Revised 24/7/13
Iris-SDL Register Descriptions
20.94 Pixel Engine Fetch DeltaYY register
(GFXPIX_fetch<n>_DeltaYY)
The Pixel Engine Fetch DeltaYY register is used to set the step size for a rotation operation of a ROT
type fetch unit.
Figure 20-92: Pixel Engine Fetch DeltaYY
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Reserved
0
RWS
0
00
09
0
DeltaYY
Reserved
10
0
13
0
11
14
0
0
15
0
Reserved
0
12
16
19
0
0
20
0
17
21
0
0
22
0
18
23
0
0
24
25
0
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXPIX_fetch<n>_DeltaYY
Table 20-54: Pixel Engine Fetch DeltaYY register bits
Bit position
Bit name
[31:23]
Reserved
[22:2]
DeltaYY
[1:0]
Reserved
20 - 128
Description
Sets the DeltaYY stepsize for rotation operation, given in s6.14
twos complement notation. This field is only available in ROT type
fetch units.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.95 Pixel Engine Fetch Skip Window Offset register
(GFXPIX_fetch<n>_SkipWindowOffset)
The Pixel Engine Fetch SkipWindowOffset register is used to set the X and Y offsets of the skip window.
Figure 20-93: Pixel Engine Fetch SkipWindowOffset
02
01
00
0
0
0
05
0
03
06
0
0
07
0
04
08
0
0
09
0
RWS
Reserved
Reserved
SkipWindowXOffset
10
0
13
0
11
14
0
0
15
0
12
16
0
RWS
Reserved
0
17
0
21
0
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
SkipWindowYOffset
28
0
29
0
0
30
0
Reserved
31
0
GFXPIX_fetch<n>_SkipWindowOffset
Table 20-55: Pixel Engine Fetch SkipWindowOffset register bits
Bit position
Bit name
[31:26]
Reserved
[25:16]
SkipWindowYOffset
[15:10]
Reserved
[9:0]
SkipWindowXOffset
Fujitsu Semiconductor Europe GmbH
Description
Skip window Y offset relative to the source buffer origin. Please
note that the skip window has to be completely inside the source
buffer.
Skip window X offset relative to the source buffer origin. Please
note that the skip window has to be completely inside the source
buffer.
20 - 129
Revised 24/7/13
Iris-SDL Register Descriptions
20.96 Pixel Engine Fetch Skip Window Dimensions register
(GFXPIX_fetch<n>_SkipWindowDimensions)
The Pixel Engine Fetch SkipWindowDimensions register is used to set the height and width of the skip
window.
Figure 20-94: Pixel Engine Fetch SkipWindowDimensions
02
01
00
0
0
0
05
0
03
06
0
0
07
0
04
08
0
0
09
0
RWS
Reserved
Reserved
SkipWindowWidth
10
13
0
0
14
0
0
15
0
11
16
0
0
17
0
RWS
Reserved
12
18
19
21
0
0
22
0
0
23
0
20
24
0
0
25
0
SkipWindowHeight
26
27
0
28
0
29
0
0
30
0
Reserved
31
0
GFXPIX_fetch<n>_SkipWindowDimensions
Table 20-56: Pixel Engine Fetch SkipWindowDimensions register bits
Bit position
Bit name
[31:26]
Reserved
[25:16]
SkipWindowHeight
[15:10]
Reserved
[9:0]
SkipWindowWidth
20 - 130
Description
Skip window height. Please note that the skip window has to be
completely inside the source buffer.
Skip window width. Please note that the skip window has to be
completely inside the source buffer.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.97 Pixel Engine Fetch Color Component Bits register
(GFXPIX_fetch<n>_ColorComponentBits)
The Pixel Engine Fetch ColorComponentBits register is used to define the size of the color components
of the source buffer.
Figure 20-95: Pixel Engine Fetch ColorComponentBits
01
00
0
02
0
0
03
1
RWS
RWS
Reserved
Reserved
ComponentBitsAlpha
04
06
0
0
07
0
05
08
0
0
09
10
0
Reserved
Reserved
ComponentBitsBlue
11
1
0
12
14
0
0
15
0
13
16
0
RWS
0
0
17
0
18
19
1
Reserved
Reserved
ComponentBitsGreen
20
22
0
0
23
0
21
24
0
0
RWS
Reserved
0
25
0
27
1
26
28
0
ComponentBitsRed
29
0
30
0
Reserved
31
0
GFXPIX_fetch<n>_ColorComponentBits
Table 20-57: Pixel Engine Fetch ColorComponentBits register bits
Bit position
Bit name
[31:28]
Reserved
[27:24]
ComponentBitsRed
[23:20]
Reserved
[19:16]
ComponentBitsGreen
[15:12]
Reserved
[11:8]
ComponentBitsBlue
[7:4]
Reserved
[3:0]
ComponentBitsAlpha
Fujitsu Semiconductor Europe GmbH
Description
The size of the red color component in the source buffer.
The size of the green color component in the source buffer.
The size of the blue color component in the source buffer.
The size of the alpha color component in the source buffer.
20 - 131
Revised 24/7/13
Iris-SDL Register Descriptions
20.98 Pixel Engine Fetch Color Component Shift register
(GFXPIX_fetch<n>_ColorComponentShift)
The Pixel Engine Fetch ColorComponentShift register is used to specify the offset of the first bit of a color
component (R,G,B,A) from the LSB of a pixel in the source buffer.
Figure 20-96: Pixel Engine Fetch ColorComponentShift
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
ComponentBitsAlpha
05
07
0
06
08
0
0
RWS
1
0
09
10
0
11
12
0
0
Reserved
Reserved
ComponentBitsBlue
13
15
0
14
16
0
RWS
0
0
17
0
19
0
18
20
1
0
Reserved
Reserved
ComponentBitsGreen
21
23
0
0
24
0
RWS
0
22
25
0
27
1
26
28
1
ComponentBitsRed
29
0
30
0
0
Reserved
Reserved
31
GFXPIX_fetch<n>_ColorComponentShift
Table 20-58: Pixel Engine Fetch ColorComponentShift register bits
Bit position
Bit name
[31:29]
Reserved
[28:24]
ComponentShiftRed
[23:21]
Reserved
[20:16]
ComponentShiftGreen
[15:13]
Reserved
[12:8]
ComponentShiftBlue
[7:5]
Reserved
[4:0]
ComponentShiftAlpha
Description
The offset of the red color component from the LSB of a pixel in
the source buffer. For example, an RGB565 pixel, the shift is 0.
The offset of the green color component from the LSB of a pixel
in the source buffer. For example, an RGB565 pixel, the shift is
6.
The offset of the blue color component from the LSB of a pixel in
the source buffer. For example, an RGB565 pixel, the shift is 11.
The offset of the alpha color component from the LSB of a pixel
in the source buffer. For example, an RGB565 pixel, the shift is
0.
Please refer to the Pixel Engine Store and Fetch unit descriptions for a diagram and details.
20 - 132
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.99 Pixel Engine Fetch Constant Color register
(GFXPIX_fetch<n>_ConstantColor)
The Pixel Engine Fetch ConstantColor register is used to set the constant colors used for tiling (fill constant), skip mode (constant) and color components whose bit width is 0.
Figure 20-97: Pixel Engine Fetch ConstantColor
01
00
0
0
04
0
02
05
0
0
06
0
03
07
0
0
08
0
RWS
RWS
ConstantColorBlue
ConstantColorAlpha
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
0
RWS
RWS
0
17
20
0
0
21
0
18
22
0
19
23
0
0
24
0
ConstantColorGreen
25
0
26
0
28
0
27
29
0
ConstantColorRed
30
0
0
31
0
GFXPIX_fetch<n>_ConstantColor
Table 20-59: Pixel Engine Fetch ConstantColor register bits
Bit position
Bit name
Description
[31:24]
ConstantColorRed
Defines the red color component value required for tiling mode
TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR and if
the red color component bit width is set to 0.
[23:16]
ConstantColorGreen
Defines the green color component value required for tiling mode
TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR and if
the green color component bit width is set to 0.
[15:9]
ConstantColorBlue
Defines the blue color component value required for tiling mode
TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR and if
the blue color component bit width is set to 0.
[7:0]
ConstantColorAlpha
Defines the alpha color component value required for tiling mode
TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR and if
the alpha color component bit width is set to 0.
Fujitsu Semiconductor Europe GmbH
20 - 133
Revised 24/7/13
Iris-SDL Register Descriptions
20.100Pixel Engine Fetch Control register (GFXPIX_fetch<n>_Control)
The Pixel Engine Fetch Control register is used to control and configure the functionality of the respective fetch unit.
Figure 20-98: Pixel Engine Fetch Control
03
02
01
00
ClockDisable
SWReset
Start
ShadowLoad
RW
RW
RW
1
0
0
04
0
RW
05
RWS
1
06
07
0
0
08
0
0
09
1
BitsPerPixel
10
0
11
Reserved
12
AlphaMultiply
RWS
0
Reserved
13
RWS
0
14
ColorMultiplySelect
ColorMultiplyEnable
RWS
0
Reserved
0
0
15
16
0
Reserved
17
Reserved
Reserved
0
0
RWS
0
0
0
18
19
20
DummySkipSelect
21
22
TileMode
RWS
23
Reserved
Reserved
0
0
24
RLDEnable
RWS
RWS
0
25
FilterMode
Reserved
Reserved
0
0
27
0
26
28
X
29
FetchType
R
30
HasMultiply
R
X
X
31
SHD_UPD
RWS
0
GFXPIX_fetch<n>_Control
Table 20-60: Pixel Engine Fetch Control register bits
Bit position
Bit name
Description
31
SHD_UPD
Overrides the standard shadow load mechanisms and constantly
loads shadows. Please note, that usage of this functionality is for
debugging purposes only and can cause unintended behavior of
the fetch unit (like corrupted data etc).
30
[29:28]
20 - 134
HasMultiply
FetchType
0
Neutral mode
1
Constant update mode
This read-only field can be used to determine if this fetch can
perform color multiplications.
0
MULTIPLY: The fetch unit has color multiplication
capabilities
1
NO_MULTIPLY: The fetch unit does not have color
multiplication capabilities
This field is used to read the fetch unit type.
00
SIMPLE: This fetch unit has no RLD or rotation
capabilities.
01
RLD: This fetch unit has RLD capabilities.
10
ROT: This fetch unit has rotation capabilities.
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[27:26]
Reserved
25
FilterMode
24
RLDEnable
23
Reserved
[22:21]
TileMode
20
DummySkipSelect
[19:15]
Reserved
15
Reserved
14
ColorMultiplySelect
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
This field is only available in ROT type fetch units.
It is used to switch between nearest and bilinear filtering modes.
0
NEAREST: Sets ‘nearest’ filtering mode.
1
BILINEAR: Sets ‘bilinear’ filtering mode.
This field is only available in RLD type fetch units.
Enables/Disables the Run Length Decompression (RLD)
feature. If the source buffer is run length encoded, enable this
field.
0
RLD is disabled
1
RLD is enabled
Selects the tile mode for pixels sampled outside the source
buffer.
Please note that the DummySkipSelect register setting takes
precedence if a pixel is subject to both tiling and is in the skip
window.
00
TILE_PAD: Uses the edge pixels of the source
image.
01
TILE_FILL_CONSTANT: If set when tiling, the
constant color set with register ConstantColor is
used.
10
TILE_FILL_ZERO: If set when tiling, black (all
color components = 0) is used.
11
Reserved
This bit selects which values is used for skipped pixels inside the
skip rectangle.
0
CONSTANTCOLOR: the constant color set with
the ConstantColor register is used.
1
ZERO: black (all color components = 0) is used.
This field is only available if the fetch unit has color multiplication
capabilities.
The bit select which multiplicator to use for color multiply.
0
ALPHA: use the alpha value.
1
CONSTANTCOLOR: use the constant color
defined in the ConstantColor register.
20 - 135
Revised 24/7/13
13
12
Iris-SDL Register Descriptions
ColorMultiplyEnable
AlphaMultiply
This field is only available if the fetch unit has color multiplication
capabilities.
Enables/disables the multiplication of color values after the
constant alpha multiplication stage.
0
Color multiply is disabled
1
Color multiply is enabled
This field is only available if the fetch unit has color multiplication
capabilities.
Enables/disables the multiplication of color values after the
constant alpha multiplication stage.
0
Alpha multiply is disabled
1
Alpha multiply is enabled
[11:10]
Reserved
Reserved
[9:4]
BitsPerPixel
Defines the pixel size in bits. This value must be a power of 2 or
24.
Other values are reserved and must not be used!
3
2
ClockDisable
SWReset
01
TOTALBITS_1: Pixel size is 1 bit per pixel.
10
TOTALBITS_2: Pixel size is 2 bits per pixel.
100
TOTALBITS_4: Pixel size is 4 bits per pixel.
1000
TOTALBITS_8: Pixel size is 8 bits per pixel.
10000
TOTALBITS_16: Pixel size is 16 bits per pixel.
11000
TOTALBITS_24: Pixel size is 24 bits per pixel.
100000
TOTALBITS_32: Pixel size is 32 bits per pixel.
Deactivates most of the internal clocks of the fetch unit. This
function can only be activated if SWReset bit of this register is
set to SW_RESET.
0
OPERATION: Normal operation.
1
POWERDOWN: The fetch unit clocks are
disabled.
This bit is used to execute a software reset of the fetch unit. A
software reset will not affect the shadow registers.
0
OPERATION: Normal operation.
1
SW_RESET: A software reset is executed.
1
Start
This bit is primarily intended for debugging purposes.
Writing a 1 to this bit starts processing.
0
ShadowLoad
Write a 1 to this bit if you want the fetch unit to perform a shadow
load with the next start of operation and set the RLD bit in the
start of frame control word. This bit is reset to 0 as soon as
ShadowLoad has been performed.
20 - 136
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.101Pixel Engine Layerblend Control register
(GFXPIX_layerblend<n>_CONTROL)
The Pixel Engine Layerblend Control register is used to configure a layer blending unit.
Figure 20-99: Pixel Engine Layerblend Control
01
0
MODE
RWS
0
RWS
0
00
02
0
03
04
0
PRIM_C_BLD_FUNC
05
0
RWS
SEC_C_BLD_FUNC
06
07
0
RWS
0
0
08
0
09
10
0
PRIM_A_BLD_FUNC
11
0
0
RWS
Reserved
0
RWS
12
13
0
SEC_A_BLD_FUNC
14
0
15
0
ALPHA
Reserved
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
Reserved
0
0
25
0
Reserved
26
28
0
0
29
0
RW
0
27
30
0
SHD_UPD
31
GFXPIX_layerblend<n>_CONTROL
Table 20-61: Pixel Engine Layerblend Control register bits
Bit position
Bit name
Description
31
SHD_UPD
Sets the shadow register update mode.
[30:24]
Reserved
[23:16]
ALPHA
[15:14]
Reserved
Fujitsu Semiconductor Europe GmbH
0
NORMAL: Shadow registers are updated with the
pipeline control word.
1
WRITE_THROUGH: The shadow registers are
constantly updated.
This bitfield defines the constant alpha value.
20 - 137
Revised 24/7/13
[13:11]
[10:8]
[7:5]
20 - 138
Iris-SDL Register Descriptions
SEC_A_BLD_FUNC
PRIM_A_BLD_FUNC
SEC_C_BLD_FUNC
This bitfield sets the secondary input blending function.
000
ZERO: Aout = Ain * 0
001
ONE: Aout = Ain * 1
010
PRIM_ALPHA: Aout = Ain * ALPHA_prim
011
ONE_MINUS_PRIM_ALPHA: Aout = Ain * (1 ALPHA_prim)
100
SEC_ALPHA: Aout = Ain * ALPHA_sec
101
ONE_MINUS_SEC_ALPHA: Aout = Ain * (1 ALPHA_sec)
110
CONST_ALPHA: Aout = Ain * ALPHA_const
111
ONE_MINUS_CONST_ALPHA: Aout = Ain * (1 ALPHA_const)
This bitfield sets the primary input blending function.
000
ZERO: Aout = Ain * 0
001
ONE: Aout = Ain * 1
010
PRIM_ALPHA: Aout = Ain * ALPHA_prim
011
ONE_MINUS_PRIM_ALPHA: Aout = Ain * (1 ALPHA_prim)
100
SEC_ALPHA: Aout = Ain * ALPHA_sec
101
ONE_MINUS_SEC_ALPHA: Aout = Ain * (1 ALPHA_sec)
110
CONST_ALPHA: Aout = Ain * ALPHA_const
111
ONE_MINUS_CONST_ALPHA: Aout = Ain * (1 ALPHA_const)
This bitfield sets the secondary input blending function.
000
ZERO: Cout = Cin * 0
001
ONE: Cout = Cin * 1
010
PRIM_ALPHA: Cout = Cin * ALPHA_prim
011
ONE_MINUS_PRIM_ALPHA: Cout = Cin * (1 ALPHA_prim)
100
SEC_ALPHA: Cout = Cin * ALPHA_sec
101
ONE_MINUS_SEC_ALPHA: Cout = Cin * (1 ALPHA_sec)
110
CONST_ALPHA: Cout = Cin * ALPHA_const
111
ONE_MINUS_CONST_ALPHA: Cout = Cin * (1 ALPHA_const)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[4:2]
[1:0]
PRIM_C_BLD_FUNC
MODE
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
This bitfield sets the primary input blending function.
000
ZERO: Cout = Cin * 0
001
ONE: Cout = Cin * 1
010
PRIM_ALPHA: Cout = Cin * ALPHA_prim
011
ONE_MINUS_PRIM_ALPHA: Cout = Cin * (1 ALPHA_prim)
100
SEC_ALPHA: Cout = Cin * ALPHA_sec
101
ONE_MINUS_SEC_ALPHA: Cout = Cin * (1 ALPHA_sec)
110
CONST_ALPHA: Cout = Cin * ALPHA_const
111
ONE_MINUS_CONST_ALPHA: Cout = Cin * (1 ALPHA_const)
Sets the layer blending mode.
00
NEUTRAL: The module is set to neutral mode,
output is the primary input.
01
BLEND: The module is set to blending mode.
10
PRIM_TRANSPARENT: Sets primary
(background) transparent mode.
11
SEC_TRANSPARENT: Sets secondary
(foreground) transparent mode.
20 - 139
Revised 24/7/13
Iris-SDL Register Descriptions
20.102Pixel Engine Layerblend Position register
(GFXPIX_layerblend<n>_POSITION)
The Pixel Engine Layerblend Control register is used to set the position of the secondary input frame.
Figure 20-100: Pixel Engine Layerblend Position
02
01
00
0
0
0
RWS
Reserved
XPOS
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
0
11
0
12
14
0
0
15
0
13
16
0
Reserved
17
0
YPOS
RWS
Reserved
0
18
19
0
0
20
0
22
0
21
23
0
0
24
26
0
0
27
0
25
28
0
0
29
0
30
0
Reserved
31
0
GFXPIX_layerblend<n>_POSITION
Table 20-62: Pixel Engine Layerblend Position register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
YPOS
[15:12]
Reserved
[11:0]
XPOS
20 - 140
Description
The vertical position, The first pixel is at 0.
Format: s11 (twos complement)
The horizontal position, The first pixel is at 0.
Format: s11 (twos complement)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.103Pixel Engine Layerblend Transparent Color register
(GFXPIX_layerblend<n>_TRANS_COL)
The Pixel Engine Layerblend Transparent Color register is used to define the color components of the
color used for transparency blending.
Figure 20-101: Pixel Engine Layerblend Transparent Color
00
RWS
RWS
BLUE
01
04
0
0
05
0
0
06
0
02
07
0
0
08
0
03
09
0
10
0
12
0
0
13
0
11
14
0
0
15
0
0
0
RWS
Reserved
RED
GREEN
16
20
0
0
21
0
17
22
0
0
23
0
18
24
0
19
25
0
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXPIX_layerblend<n>_TRANS_COL
Table 20-63: Pixel Engine Layerblend Transparent Color register bits
Bit position
Bit name
[31:24]
Reserved
[23:16]
RED
The red color component used for transparency blending.
[15:8]
GREEN
The green color component used for transparency blending.
[7:0]
BLUE
The blue color component used for transparency blending.
Fujitsu Semiconductor Europe GmbH
Description
20 - 141
Revised 24/7/13
Iris-SDL Register Descriptions
20.104Pixel Engine Layerblend Primary Control Word register
(GFXPIX_layerblend<n>_PRIM_CONTROL_WORD)
The Pixel Engine Layerblend Primary Control Word register is used to read the value of the last primary
control word received.
Figure 20-102: Pixel Engine Layerblend Primary Control Word
10
09
08
07
06
05
04
03
02
01
00
x
x
x
x
x
x
x
x
x
x
12
x
x
13
x
11
14
x
x
15
x
16
19
x
x
R
P_VAL
20
x
x
21
x
17
22
x
x
23
x
18
24
x
x
25
x
28
x
26
29
x
x
30
x
27
31
x
GFXPIX_layerblend<n>_PRIM_CONTROL_WORD
Table 20-64: Pixel Engine Layerblend Primary Control Word register bits
Bit position
Bit name
Description
[31:0]
P_VAL
The value of last received primary control word.
20 - 142
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.105Pixel Engine Layerblend Primary Control Word register
(GFXPIX_layerblend<n>_SEC_CONTROL_WORD)
The Pixel Engine Layerblend Secondary Control Word register is used to read the value of the last secondary control word received.
Figure 20-103: Pixel Engine Layerblend Secondary Control Word
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16
R
S_VAL
19
x
x
20
x
17
21
x
x
22
x
18
23
x
x
24
x
27
x
25
28
x
x
29
x
26
30
x
x
31
x
GFXPIX_layerblend<n>_SEC_CONTROL_WORD
Table 20-65: Pixel Engine Layerblend Secondary Control Word register bits
Bit position
Bit name
Description
[31:0]
S_VAL
The value of last received secondary control word.
Fujitsu Semiconductor Europe GmbH
20 - 143
Revised 24/7/13
Iris-SDL Register Descriptions
20.106Pixel Engine Color Matrix Control register
(GFXPIX_matrix0_CONTROL)
The Pixel Engine Color Matrix Control register is used to configure the color matrix unit.
Figure 20-104: Pixel Engine Color Matrix Control
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
MODE
RWS
Bit position
Bit name
Description
31
SHD_UPD
Sets the shadow register update mode.
Reserved
[1:0]
MODE
20 - 144
0
The shadow registers are updated with the
pipeline control word.
1
The shadow registers are constantly updated.
Sets the operation mode for the color matrix.
00
NEUTRAL: Sets the unit to neutral mode (the
matrix input is passed to the output without
modifications).
01
MATRIX: Sets the unit to matrix mode (the
incoming RGB value is color converted using the
matrix).
10
PREMUL: Sets the unit to (alpha)
pre-multiplication mode (the incoming RGB color
is pre multiplied with the incoming alpha value).
11
RSVD: Reserved.
Fujitsu Semiconductor Europe GmbH
0
0
0
Table 20-66: Pixel Engine Color Matrix Control register bits
[30:2]
00
10
0
12
0
11
13
0
0
14
0
15
Reserved
Reserved
RW
0
16
19
0
17
20
0
0
21
0
18
22
0
0
23
0
26
0
24
27
0
0
28
0
25
29
0
0
30
0
SHD_UPD
31
GFXPIX_matrix0_CONTROL
Iris-SDL Register Descriptions
Revised 24/7/13
20.107Pixel Engine Color Matrix RED0 register
(GFXPIX_matrix0_RED0)
The Pixel Engine Color Matrix RED0 register is used to define matrix values used for the calculation of
the red output value.
Figure 20-105: Pixel Engine Color Matrix RED0
02
01
00
0
0
A11
1
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
RWS
Reserved
0
05
11
0
14
0
12
15
0
0
16
0
RWS
0
13
17
0
A12
Reserved
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
Reserved
0
21
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_RED0
Table 20-67: Pixel Engine Color Matrix RED0 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
A12
[15:11]
Reserved
[10:0]
A11
Fujitsu Semiconductor Europe GmbH
Description
The value for the green input block (format: s2.8)
The value for the red input block (format: s2.8)
20 - 145
Revised 24/7/13
Iris-SDL Register Descriptions
20.108Pixel Engine Color Matrix RED1 register
(GFXPIX_matrix0_RED1)
The Pixel Engine Color Matrix RED1 register is used to define matrix values used for the calculation of
the red output value.
Figure 20-106: Pixel Engine Color Matrix RED1
02
01
00
0
0
A13
0
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
0
RWS
Reserved
0
05
11
14
0
0
15
0
12
16
0
RWS
0
13
17
0
C1
Reserved
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
Reserved
0
21
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_RED1
Table 20-68: Pixel Engine Color Matrix RED1 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
C1
[15:11]
Reserved
[10:0]
A13
20 - 146
Description
The value for the red output offset (format: s10)
The value for the blue input block (format: s2.8)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.109Pixel Engine Color Matrix GREEN0 register
(GFXPIX_matrix0_GREEN0)
The Pixel Engine Color Matrix GREEN0 register is used to define matrix values used for the calculation
of the green output value.
Figure 20-107: Pixel Engine Color Matrix GREEN0
02
01
00
0
0
A21
0
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
RWS
Reserved
0
05
11
0
14
0
12
15
0
0
16
0
RWS
0
13
17
0
A22
Reserved
18
19
0
1
20
22
0
0
23
0
Reserved
0
21
24
0
26
0
25
27
0
0
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_GREEN0
Table 20-69: Pixel Engine Color Matrix GREEN0 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
A22
[15:11]
Reserved
[10:0]
A21
Fujitsu Semiconductor Europe GmbH
Description
The value for the green input block (format: s2.8)
The value for the red input block (format: s2.8)
20 - 147
Revised 24/7/13
Iris-SDL Register Descriptions
20.110Pixel Engine Color Matrix GREEN1 register
(GFXPIX_matrix0_GREEN1)
The Pixel Engine Color Matrix GREEN1 register is used to define matrix values used for the calculation
of the green output value.
Figure 20-108: Pixel Engine Color Matrix GREEN1
02
01
00
0
0
A23
0
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
0
RWS
Reserved
0
05
11
14
0
0
15
0
12
16
0
RWS
0
13
17
0
C2
Reserved
18
19
0
1
20
22
0
0
23
0
Reserved
0
21
24
0
26
0
25
27
0
0
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_GREEN1
Table 20-70: Pixel Engine Color Matrix GREEN1 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
C2
[15:11]
Reserved
[10:0]
A23
20 - 148
Description
The value for the green output offset (format: s10)
The value for the blue input block (format: s2.8)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.111Pixel Engine Color Matrix BLUE0 register
(GFXPIX_matrix0_BLUE0)
The Pixel Engine Color Matrix BLUE0 register is used to define matrix values used for the calculation
of the blue output value.
Figure 20-109: Pixel Engine Color Matrix BLUE0
02
01
00
0
0
A31
0
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
RWS
Reserved
0
05
11
0
14
0
12
15
0
0
16
0
RWS
0
13
17
0
A32
Reserved
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
Reserved
0
21
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_BLUE0
Table 20-71: Pixel Engine Color Matrix BLUE0 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
A32
[15:11]
Reserved
[10:0]
A31
Fujitsu Semiconductor Europe GmbH
Description
The value for the green input block (format: s2.8)
The value for the red input block (format: s2.8)
20 - 149
Revised 24/7/13
Iris-SDL Register Descriptions
20.112Pixel Engine Color Matrix BLUE1 register
(GFXPIX_matrix0_BLUE1)
The Pixel Engine Color Matrix BLUE1 register is used to define matrix values used for the calculation of
the blue output value.
Figure 20-110: Pixel Engine Color Matrix BLUE1
02
01
00
0
0
A33
1
06
0
03
07
0
0
08
0
04
09
0
0
10
0
0
0
RWS
Reserved
0
05
11
14
0
0
15
0
12
16
0
RWS
0
13
17
0
C3
Reserved
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
Reserved
0
21
28
0
29
30
0
Reserved
31
0
GFXPIX_matrix0_BLUE1
Table 20-72: Pixel Engine Color Matrix BLUE1 register bits
Bit position
Bit name
[31:27]
Reserved
[26:16]
C3
[15:11]
Reserved
[10:0]
A33
20 - 150
Description
The value for the blue output offset (format: s10)
The value for the blue input block (format: s2.8)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.113Pixel Engine ROP Control register (GFXPIX_rop<n>_Control)
The Pixel Engine ROP Control register is used to configure a Raster Operations (ROP) unit of the Pixel
Engine.
Figure 20-111: Pixel Engine ROP Control
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
0
RWS
Reserved
Mode
00
12
Reserved
0
19
0
13
20
0
14
21
0
0
22
0
0
23
0
RW
0
15
24
0
16
25
0
0
26
0
17
27
0
0
28
0
18
29
0
0
30
0
SHD_UPD
31
GFXPIX_rop<n>_Control
Table 20-73: Pixel Engine ROP Control register bits
Bit position
Bit name
Description
31
SHD_UPD
This bit can be used to override the standard shadow load
mechanisms and to constantly load shadow register values.
Please note, that this functionality is for debugging purposes
only and can cause unintended behavior of the ROP unit (such
as corrupted data etc) if used otherwise.
[30:1]
Reserved
0
Mode
Fujitsu Semiconductor Europe GmbH
0
NORMAL: Normal operation mode.
1
UPDATE: Constantly update shadow registers.
Sets the operation mode of the ROP unit.
0
NEUTRAL: The ROP unit is set to neutral mode
(all incoming pixels and commands from the
primary input are routed directly to the unit’s
output).
1
OPERATION: The ROP is set to normal operation
mode.
20 - 151
Revised 24/7/13
Iris-SDL Register Descriptions
20.114Pixel Engine ROP Raster Operation Indices register
(GFXPIX_rop<n>_RasterOperationIndices)
The Pixel Engine ROP Raster Operation Indices register is used to set the indices used by each color
component for raster operations.
Figure 20-112: Pixel Engine ROP Raster Operation Indices
01
00
0
04
0
0
05
0
02
06
0
0
07
0
03
08
0
0
09
RWS
RWS
OpIndixBlue
OpIndixAlpha
10
12
0
0
13
0
0
14
0
11
15
0
0
RWS
RWS
0
0
16
0
20
0
17
21
0
0
22
0
18
23
0
19
24
0
0
25
0
OpIndixGreen
26
28
0
0
29
0
27
30
0
OpIndixRed
31
0
GFXPIX_rop<n>_RasterOperationIndices
Table 20-74: Pixel Engine ROP Raster Operation Indices register bits
Bit position
Bit name
Description
[31:24]
OpIndexRed
The index value for the red color component for raster
operations.
[23:16]
OpIndexGreen
The index value for the green color component for raster
operations.
[15:8]
OpIndexBlue
The index value for the blue color component for raster
operations.
[7:0]
OpIndexAlpha
The index value for the alpha color component for raster
operations.
20 - 152
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.115Pixel Engine ROP Primary Control Word register
(GFXPIX_rop<n>_PRIM_CONTROL_WORD)
The Pixel Engine ROP Primary Control Word register is used to read the value of the last primary control
word received.
Figure 20-113: Pixel Engine ROP Primary Control Word
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16
R
P_VAL
19
x
x
20
x
17
21
x
x
22
x
18
23
x
x
24
x
27
x
25
28
x
x
29
x
26
30
x
x
31
x
GFXPIX_rop<n>_PRIM_CONTROL_WORD
Table 20-75: Pixel Engine ROP Primary Control Word register bits
Bit position
Bit name
Description
[31:0]
P_VAL
The value of the last control word received on the primary input
can be read here. If a 39 bit pixel channel is connected, the
mapping is as follows: p_val[31:0] = { data[37:22], data[19:12],
data[9:2] }.
Fujitsu Semiconductor Europe GmbH
20 - 153
Revised 24/7/13
Iris-SDL Register Descriptions
20.116Pixel Engine ROP Secondary Control Word register
(GFXPIX_rop<n>_SEC_CONTROL_WORD)
The Pixel Engine ROP Secondary Control Word register is used to read the value of the last secondary
control word received.
Figure 20-114: Pixel Engine ROP Secondary Control Word
10
09
08
07
06
05
04
03
02
01
00
x
x
x
x
x
x
x
x
x
x
12
x
x
13
x
11
14
x
x
15
x
16
R
S_VAL
19
x
x
20
x
17
21
x
x
22
x
18
23
x
x
24
x
27
x
25
28
x
x
29
x
26
30
x
x
31
x
GFXPIX_rop<n>_SEC_CONTROL_WORD
Table 20-76: Pixel Engine ROP Secondary Control Word register bits
Bit position
Bit name
Description
[31:0]
S_VAL
The value of last control word received on the secondary input
can be read here. If a 39 bit pixel channel is connected, the
mapping is as follows: s_val[31:0] = { data[37:22], data[19:12],
data[9:2] }.
20 - 154
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.117Pixel Engine ROP Tertiary Control Word register
(GFXPIX_rop<n>_TERT_CONTROL_WORD)
The Pixel Engine ROP Tertiary Control Word register is used to read the value of the last tertiary control
word received.
Figure 20-115: Pixel Engine ROP Tertiary Control Word
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16
R
S_VAL
19
x
x
20
x
17
21
x
x
22
x
18
23
x
x
24
x
27
x
25
28
x
x
29
x
26
30
x
x
31
x
GFXPIX_rop<n>_TERT_CONTROL_WORD
Table 20-77: Pixel Engine ROP Tertiary Control Word register bits
Bit position
Bit name
Description
[31:0]
T_VAL
The value of last control word received on the tertiary input can
be read here. If a 39 bit pixel channel is connected, the mapping
is as follows: t_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
Fujitsu Semiconductor Europe GmbH
20 - 155
Revised 24/7/13
Iris-SDL Register Descriptions
20.118Pixel Engine Store Unit Status register (GFXPIX_store0_Status)
The Pixel Engine Store Unit Status register is used to read the status of a store unit in the Pixel Engine.
Figure 20-116: Pixel Engine Store Unit Status
Bit position
Bit name
[31:7]
Reserved
6
StatusComplete
The store unit has completed all requested AXI transfers.
5
StatusRequest
The store unit is requesting use of the AXI interface, waiting for
an acknowledge signal.
4
StatusBuffersidle
The AXI interface buffers are in idle state.
[3:1]
Reserved
0
StatusBusy
20 - 156
00
01
StatusBusy
R
0
0
Table 20-78: Pixel Engine Store Unit Status register bits
Description
The store unit is busy
Fujitsu Semiconductor Europe GmbH
X
02
03
Reserved
Reserved
0
04
StatusBuffersidle
R
X
05
StatusRequest
06
StatusComplete
R
07
0
R
08
0
X
09
0
0
Reserved
X
10
0
12
0
11
13
0
14
0
20
0
0
21
0
15
22
0
0
23
0
16
24
0
0
25
0
17
26
0
0
27
0
18
28
0
19
29
0
0
30
0
Reserved
31
0
GFXPIX_store0_Status
Iris-SDL Register Descriptions
Revised 24/7/13
20.119Pixel Engine Store Unit Last Control Word register
(GFXPIX_store0_LAST_CONTROL_WORD)
The Pixel Engine Store Unit Last Control Word register is used to read the value of the last control word
received.
Figure 20-117: Pixel Engine Store Unit Last Control Word
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R
L_VAL
19
0
0
20
0
17
21
0
0
22
0
18
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_store0_LAST_CONTROL_WORD
Table 20-79: Pixel Engine Store Unit Last Control Word register bits
Bit position
Bit name
Description
[31:0]
L_VAL
Shows the last control word received from the pixel engine. If a
39 bit pixel channel is connected, the mapping is as follows:
l_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
Fujitsu Semiconductor Europe GmbH
20 - 157
Revised 24/7/13
Iris-SDL Register Descriptions
20.120Pixel Engine Store Unit Burst Buffer Management register
(GFXPIX_store0_BurstBufferManagement)
The Pixel Engine Store Unit Burst Buffer Management register is used to configure the AXI interface
burst mode used by Pixel Engine store units.
Figure 20-118: Pixel Engine Store Unit Burst Buffer Management
01
00
0
0
04
0
02
05
0
1
06
0
03
07
0
X
R
R
X
0
08
X
ManagedBurstBuffers
09
10
12
X
X
13
0
11
14
0
0
Reserved
Reserved
MaxBurstLength
15
19
0
0
20
0
16
21
0
0
22
0
17
23
0
0
24
0
RWS
1
18
25
0
27
0
26
28
0
SetBurstLength
29
0
30
0
0
Reserved
Reserved
31
GFXPIX_store0_BurstBufferManagement
Table 20-80: Pixel Engine Store Unit Burst Buffer Management register bits
Bit position
Bit name
[31:29]
Reserved
[28:24]
SetBurstLength
[23:13]
Reserved
[12:8]
MaxBurstLength
This is the maximum burst length that can be configured.
[7:0]
ManagedBurstBuffers
This is the number of burst buffers on the AXI interface that are
managed. This is always 4.
20 - 158
Description
Set this to the burst length that should be used on the AXI
interface. Please note that SetBurstLength has to be smaller or
equal to MaxBurstLength. Only a power of two may be specified
as burst length. Please set this to at least 2 for 64bit pixels to
avoid performance loss.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.121Pixel Engine Store Unit Base Address register
(GFXPIX_store0_BaseAddress)
The Pixel Engine Store Unit Base Address register is used to define the byte-aligned start address of
the destination buffer for a store unit of the Pixel Engine.
Figure 20-119: Pixel Engine Store Unit Base Address
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
19
0
14
20
0
0
21
0
0
22
0
15
23
0
0
24
0
16
25
0
RWS
BaseAddress
26
0
0
27
0
17
28
0
0
29
0
18
30
0
0
31
0
GFXPIX_store0_BaseAddress
Table 20-81: Pixel Engine Store Unit Base Address register bits
Bit position
Bit name
Description
[31:0]
BaseAddress
This bitfield defines the byte-aligned start address of the
destination buffer. For 64 bit pixels BaseAddress[2:0] must be
set 0, for 32 bit pixels BaseAddress[1:0] must be set 0 and for 16
bit pixels BaseAddress[0] must be set 0.
Fujitsu Semiconductor Europe GmbH
20 - 159
Revised 24/7/13
Iris-SDL Register Descriptions
20.122Pixel Engine Store Unit Destination Buffer Stride register
(GFXPIX_store0_DestinationBufferStride)
The Pixel Engine Store Unit Destination Buffer Stride register is used to define the destination buffer
stride size used for address generation by a store unit.
Figure 20-120: Pixel Engine Store Unit Destination Buffer Stride
04
03
02
01
00
0
0
0
0
Stride
0
06
0
05
07
0
RWS
Reserved
0
0
08
0
12
0
09
13
0
10
14
0
0
15
0
0
16
0
11
17
0
0
18
19
0
0
20
0
22
0
21
23
0
0
24
0
Reserved
25
0
28
0
26
29
0
0
30
0
27
31
0
GFXPIX_store0_DestinationBufferStride
Table 20-82: Pixel Engine Store Unit Destination Buffer Stride register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
Stride
20 - 160
Description
This bitfield defines the destination buffer stride in bytes minus
one, used for address generation. For a pixel width of 64 bits
Stride has to be dividable by 8 and given minus one, for a pixel
width of 32 bits Stride has to be dividable by 4 and given minus
one and for a pixel width of 16 bit Stride has to be dividable by
two and given minus one.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.123Pixel Engine Store Unit Frame X Offset register
(GFXPIX_store0_FrameXOffset)
The Pixel Engine Store Unit Frame X Offset register is used to define a frame’s X offset relative to the
destination buffer origin.
Figure 20-121: Pixel Engine Store Unit Frame X Offset
02
01
00
0
0
0
Reserved
Reserved
03
08
0
0
09
0
04
10
0
0
11
0
05
12
0
06
13
0
0
14
0
0
15
0
07
16
0
RWS
Reserved
0
17
0
21
0
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
FrameXOffset
28
0
29
0
0
30
0
Reserved
31
0
GFXPIX_store0_FrameXOffset
Table 20-83: Pixel Engine Store Unit Frame X Offset register bits
Bit position
Bit name
[31:2]
Reserved
[25:16]
FrameXOffset
[15:0]
Reserved
Fujitsu Semiconductor Europe GmbH
Description
Frame X origin offset relative to the destination buffer origin.
20 - 161
Revised 24/7/13
Iris-SDL Register Descriptions
20.124Pixel Engine Store Unit Frame Y Offset register
(GFXPIX_store0_FrameYOffset)
The Pixel Engine Store Unit Frame Y Offset register is used to define a frame’s Y offset relative to the
destination buffer origin.
Figure 20-122: Pixel Engine Store Unit Frame Y Offset
06
05
04
03
02
01
00
0
0
0
0
0
0
0
Reserved
Reserved
07
08
0
RWS
Reserved
0
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
0
17
0
21
0
18
22
0
19
23
0
0
24
0
0
25
0
20
26
0
0
27
FrameYOffset
28
0
29
0
0
30
0
Reserved
31
0
GFXPIX_store0_FrameYOffset
Table 20-84: Pixel Engine Store Unit Frame Y Offset register bits
Bit position
Bit name
[31:2]
Reserved
[25:16]
FrameYOffset
[15:0]
Reserved
20 - 162
Description
Frame Y origin offset relative to the destination buffer origin.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.125Pixel Engine Store Unit Color Component Bits register
(GFXPIX_store0_ColorComponentBits)
The Pixel Engine Store Unit Color Component Bits register is used to define the size of the color components in the destination buffer used by a store unit.
Figure 20-123: Pixel Engine Store Unit Color Component Bits
01
00
0
02
0
0
03
1
RWS
RWS
Reserved
Reserved
ComponentBitsAlpha
04
06
0
0
07
0
05
08
0
0
09
10
0
Reserved
Reserved
ComponentBitsBlue
11
1
0
12
14
0
0
15
0
13
16
0
RWS
0
0
17
0
18
19
1
Reserved
Reserved
ComponentBitsGreen
20
22
0
0
23
0
21
24
0
0
1
RWS
Reserved
0
25
0
26
ComponentBitsRed
28
0
27
29
0
30
0
Reserved
31
0
GFXPIX_store0_ColorComponentBits
Table 20-85: Pixel Engine Store Unit Color Component Bits register bits
Bit position
Bit name
[31:28]
Reserved
[27:24]
ComponentBitsRed
[23:20]
Reserved
[19:16]
ComponentBitsGreen
[15:12]
Reserved
[11:8]
ComponentBitsBlue
[7:4]
Reserved
[3:0]
ComponentBitsAlpha
Fujitsu Semiconductor Europe GmbH
Description
Defines the number of bits used for the red color component.
Defines the number of bits used for the green color component.
Defines the number of bits used for the blue color component.
Defines the number of bits used for the alpha color component.
20 - 163
Revised 24/7/13
Iris-SDL Register Descriptions
20.126Pixel Engine Store Unit Color Component Shift register
(GFXPIX_store0_ColorComponentShift)
The Pixel Engine Store Unit Color Component Shift register is used to define a color component offset
in the destination buffer.
Figure 20-124: Pixel Engine Store Unit Color Component Shift
01
00
0
0
03
0
02
04
0
RWS
0
0
Reserved
Reserved
ComponentShiftAlpha
05
07
0
06
08
0
0
RWS
1
0
09
10
0
11
12
0
0
Reserved
Reserved
ComponentShiftBlue
13
15
0
14
16
0
RWS
0
0
17
0
19
0
18
20
1
0
Reserved
Reserved
ComponentShiftGreen
21
23
0
0
24
0
RWS
0
1
22
25
0
26
ComponentShiftRed
28
1
27
29
0
30
0
0
Reserved
Reserved
31
GFXPIX_store0_ColorComponentShift
Table 20-86: Pixel Engine Store Unit Color Component Shift register bits
Bit position
Bit name
[31:29]
Reserved
[28:24]
ComponentShiftRed
[23:21]
Reserved
[20:16]
ComponentShiftGreen
[15:13]
Reserved
[12:8]
ComponentShiftBlue
[7:5]
Reserved
[4:0]
ComponentShiftAlpha
20 - 164
Description
The offset of the red color component in the destination buffer.
The offset of the green color component in the destination buffer.
The offset of the blue color component in the destination buffer.
The offset of the alpha color component in the destination buffer.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.127Pixel Engine Store Unit Control register
(GFXPIX_store0_Control)
The Pixel Engine Store Unit Control register is used to configure a store unit of the Pixel Engine.
Figure 20-125: Pixel Engine Store Unit Control
01
00
Reserved
Start
Reserved
W
0
X
02
SWReset
RW
1
03
ClockDisable
04
0
RW
05
0
0
RWS
1
06
0
08
0
07
09
BitsPerPixel
10
1
11
Reserved
Reserved
0
0
12
ColorDitherEnable
RWS
0
0
13
14
15
0
AlphaDitherEnable
16
0
RWS
17
0
0
18
0
Reserved
Reserved
19
23
0
0
24
0
0
25
0
20
26
0
0
27
0
21
28
0
0
29
0
RW
0
22
30
0
SHD_UPD
31
GFXPIX_store0_Control
Table 20-87: Pixel Engine Store Unit Control register bits
Bit position
Bit name
Description
31
SHD_UPD
Used to override the standard shadow load mechanisms and
constantly load shadow registers. Please note, that usage of this
functionality is for debugging purposes only and can cause
unintended behavior of the store unit (such as corrupted data
etc).
[30:14]
Reserved
13
AlphaDitherEnable
12
ColorDitherEnable
Fujitsu Semiconductor Europe GmbH
0
NORMAL: Sets neutral mode.
1
UPDATE: Sets constant update mode.
Specifies whether dithering or LSB truncation should be used if
AlphaComponentBits is smaller than 8 for alpha.
0
LSBTRUNK: LSB truncation is used.
1
DITHER: uses dithering.
Specifies whether dithering or LSB truncation should be used if
ColorComponentBits is smaller than 10 for red, green or blue.
0
LSBTRUNK: LSB truncation is used.
1
DITHER: uses dithering.
20 - 165
Revised 24/7/13
[10:4]
3
2
Iris-SDL Register Descriptions
BitsPerPixel
ClockDisable
SWReset
1
Reserved
0
Start
20 - 166
Defines the pixel size in bits. This value must be a power of 2 or
24.
When 64 bit is selected, one 64bit output pixel will consist of one
pixel from the pixel engine pipeline, interpreted as 32bit and used
twice. Please set the bitfield SetBurstLength to at least 2 for 64bit
pixels, otherwise performance will suffer. Do not set an unlisted
value!
01
TOTALBITS_1: Pixel size is 1 bit per pixel.
10
TOTALBITS_2: Pixel size is 2 bits per pixel.
100
TOTALBITS_4: Pixel size is 4 bits per pixel.
1000
TOTALBITS_8: Pixel size is 8 bits per pixel.
10000
TOTALBITS_16: Pixel size is 16 bits per pixel.
11000
TOTALBITS_24: Pixel size is 24 bits per pixel.
100000
TOTALBITS_32: Pixel size is 32 bits per pixel.
1000000
TOTALBITS_64: Pixel size is 64 bits per pixel.
Deactivates most internal clocks of store unit. Can only be
activated if SWReset field is set to SW_RESET.
0
OPERATION: Normal operation.
1
POWERDOWN: The clocks are disabled.
Puts the store unit in software reset.
0
OPERATION: Normal operation.
1
SW_RESET: Executes a software reset of the
store unit.
Writing starts a blit operation (kick signal for all fetch units
configured for the blit path.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.128Pixel Engine Store Unit Performance Counter register
(GFXPIX_store0_PerfCounter)
The Pixel Engine Store unit performance counter register is used for measurement purposes.
Figure 20-126: Pixel Engine Store Unit Performance Counter register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
15
18
0
0
19
0
R
PerfResult
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXPIX_store0_PerfCounter
Table 20-88: Pixel Engine Store Unit Performance Counter register bits
Bit position
Bit name
Description
[31:0]
PerfResult
Returns the performance counter value. Please note that a software reset
during a frame can potentially produce invalid results in the first frame that
follows.
Fujitsu Semiconductor Europe GmbH
20 - 167
Revised 24/7/13
Iris-SDL Register Descriptions
20.129Signature Unit Lock/Unlock register (GFXSIG_LockUnlock)
The Signature Unit Lock/Unlock register is used to lock or unlock the Signature Unit by software control.
Figure 20-127: Signature Unit Lock/Unlock register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
W
LockUnlock
21
0
25
0
22
26
0
23
27
0
0
28
0
0
29
0
24
30
0
0
31
0
GFXSIG_LockUnlock
Table 20-89: Signature Unit Lock/Unlock register bits
Bit position
Bit name
Description
[31:0]
LockUnlock
Write the lock key to this register to lock the Signature Unit.
Write the unlock key to this register to unlock the Signature Unit.
20 - 168
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.130Signature Unit Lock Status register (GFXSIG_SigLockStatus)
The Signature Unit Lock Status register is used to check the locked/unlocked status of the Signature
Unit.
Figure 20-128: Signature Unit Lock Status register
13
12
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
0
R
1
0
Reserved
0
00
14
0
LockStatus
15
0
16
17
22
0
Reserved
23
0
0
24
0
18
25
0
19
26
0
0
27
0
0
28
0
20
29
0
0
30
0
21
31
0
GFXSIG_SigLockStatus
Table 20-90: Signature Unit Lock Statusregister bits
Bit position
Bit name
[31:1]
Reserved
0
LockStatus
Description
Read back the locked/unlocked status of the Signature Unit using this bit:
0:
Unlocked
1:
Locked
Fujitsu Semiconductor Europe GmbH
20 - 169
Revised 24/7/13
Iris-SDL Register Descriptions
20.131Signature Unit Software reset register (GFXSIG_SigSWreset)
The Signature Unit Software reset register is used to reset the Signature Unit by software control.
Figure 20-129: Signature Unit Software reset register
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
SWRes
RW
0
0
Reserved
0
00
10
0
12
0
0
13
0
11
14
0
0
15
17
0
0
18
0
16
19
0
Reserved
20
0
21
25
0
22
26
0
23
27
0
0
28
0
0
29
0
24
30
0
0
31
0
GFXSIG_SigSWreset
Table 20-91: Signature Unit Software reset register bits
Bit position
Bit name
[31:1]
Reserved
0
SWRes
20 - 170
Description
Write a 1 to this bitfield to reset the Signature Unit. Note that this register is
not shadowed.
0:
Default condition. Writing a 0 is ignored.
1:
Reset the Signature Unit. All components are reset except
the configuration registers.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.132Signature Unit General Configuration register (GFXSIG_SigCtrl)
The Signature Unit General Configuration register is used to configure the source and masking modes
of the Signature Unit.
Figure 20-130: Signature Unit General Configuration register
01
0
Bit name
[31:18]
Reserved
[17:16]
SrcSel
[15:10]
Reserved
[9:8]
Vmask_mode
[7:2]
Description
Selects the source of input data for the Signature Unit from one of two
sources.
00
Source 0 (display output before dithering)
01
Source 1 (display output after dithering)
10
Source 2 (Unused)
11
Source 3 (Unused)
Configures the masking mode for vertical coordinates:
00
No masking
01
Mask inside vertical coordinates
10
Mask outside vertical coordinates
11
Reserved
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 171
0
RW
Table 20-92: Signature Unit General Configuration register bits
Bit position
00
02
0
Reserved
Reserved
Hmask_mode
03
0
05
0
04
06
0
RW
Reserved
0
07
0
09
0
08
10
0
0
11
0
Vmask_mode
12
13
0
0
14
0
0
RW
Reserved
SrcSel
Reserved
15
17
0
0
18
0
16
19
0
0
20
0
21
22
25
0
23
26
0
0
27
0
0
28
0
24
29
0
0
30
0
Reserved
31
0
GFXSIG_SigCtrl
Revised 24/7/13
[1:0]
20 - 172
Iris-SDL Register Descriptions
Hmask_mode
Configures the masking mode for horizontal coordinates:
00
No masking
01
Mask inside horizontal coordinates
10
Mask outside horizontal coordinates
11
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.133Mask horizontal co-ordinates Upper left register
(GFXSIG_MaskHorizontalUpperLeft)
The Mask horizontal co-ordinates Upper Left register is used in the definition of a mask area for the Signature Unit. It defines the upper left x-axis position of a mask area.
Figure 20-131: Mask horizontal co-ordinates Upper Left register
02
01
00
0
0
06
0
0
07
0
03
08
0
0
09
0
04
10
0
0
11
0
05
12
0
MaskHorizontalUpperLeft
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
22
0
21
23
0
0
RW
Reserved
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_MaskHorizontalUpperLeft
Table 20-93: Mask horizontal co-ordinates Upper Left register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
MaskHorizont
alUpperLeft
Description
The value defines the x-axis position of the upper left corner of a mask
area in pixels from 0 to max. value 4095 (212 -1)
000011001000
Fujitsu Semiconductor Europe GmbH
(Example value) C8 = x position = 200
20 - 173
Revised 24/7/13
Iris-SDL Register Descriptions
20.134Mask horizontal co-ordinates Lower Right register
(GFXSIG_MaskHorizontalLowerRight)
The Mask horizontal co-ordinates Lower Right register is used in the definition of a mask area for the
Signature Unit. It defines the lower right x-axis position of a mask area.
Figure 20-132: Mask horizontal co-ordinates Lower Right register
05
04
03
02
01
00
0
0
0
0
0
06
MaskHorizontalLowerRight
0
0
07
0
12
0
08
13
0
0
14
0
09
15
0
10
16
0
0
17
0
0
18
0
11
19
0
0
20
0
22
0
21
23
0
0
RW
Reserved
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_MaskHorizontalLowerRight
Table 20-94: Mask horizontal co-ordinates Lower Right register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
MaskHorizont
alLowerRight
Description
The value defines the x-axis position of the lower right corner of a
horizontal mask area in pixels from 0 to max. value 4095 (212 -1)
000011001000
20 - 174
(Example value) C8 = x position = 200
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.135Mask vertical co-ordinates Upper left register
(GFXSIG_MaskVerticalUpperLeft)
The Mask vertical co-ordinates Upper Left register is used in the definition of a mask area for the Signature Unit. It defines the upper left y-axis position of a mask area.
Figure 20-133: Mask vertical co-ordinates Upper Left register
01
00
06
0
0
07
0
0
08
0
02
09
0
0
10
0
03
11
0
0
12
0
04
13
0
0
14
0
05
15
0
MaskVerticalUpperLeft
16
0
0
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
RW
Reserved
Reserved
31
0
GFXSIG_MaskVerticalUpperLeft
Table 20-95: Mask vertical co-ordinates Upper Left register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
MaskVertical
UpperLeft
Description
The value defines the y-axis position of the upper left corner of a mask area
in pixels from 0 to max. value 4095 (212 -1)
000011001000
Fujitsu Semiconductor Europe GmbH
(Example value) C8 = y position = 200
20 - 175
Revised 24/7/13
Iris-SDL Register Descriptions
20.136Mask vertical co-ordinates Lower Right register
(GFXSIG_MaskVerticalLowerRight)
The Mask vertical co-ordinates Lower Right register is used in the definition of a mask area for the Signature Unit. It defines the lower right y-axis position of a mask area.
Figure 20-134: Mask vertical co-ordinates Lower Right register
04
03
02
01
00
0
0
0
0
0
06
0
05
07
0
MaskVerticalLowerRight
08
0
0
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
0
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
RW
Reserved
Reserved
31
0
GFXSIG_MaskVerticalLowerRight
Table 20-96: Mask vertical co-ordinates Lower Right register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
MaskVerticalL
owerRight
Description
The value defines the y-axis position of the lower right corner of a mask
area in pixels from 0 to max. value 4095 (212 -1)
000011001000
20 - 176
(Example value) C8 = y position = 200
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.137Evaluation Window horizontal co-ordinates Upper left register
(GFXSIG_HorizontalUpperLeftW0)
The Evaluation Window horizontal co-ordinates Upper left register defines the upper left x-axis position
of the evaluation window for the Signature Unit.
Figure 20-135: Evaluation Window horizontal co-ordinates Upper Left register
02
01
00
0
0
06
0
0
07
0
03
08
0
0
09
0
04
10
0
0
11
0
05
12
0
HorizontalUpperLeftW0
13
0
14
0
16
0
0
17
0
15
18
0
0
19
0
22
0
20
23
0
0
24
0
21
25
0
0
RW
Reserved
Reserved
26
27
0
28
29
0
0
30
0
0
31
0
GFXSIG_HorizontalUpperLeftW0
Table 20-97: Evaluation Window horizontal co-ordinates Upper Left register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
HorizontalUpp
erLeftW0
Description
The value defines the x-axis position of the upper left corner of an
evaluation window in pixels from 0 to max. value 4095 (212 -1)
000011001000
Fujitsu Semiconductor Europe GmbH
(Example value) C8 = x position = 200
20 - 177
Revised 24/7/13
Iris-SDL Register Descriptions
20.138Evaluation Window horizontal co-ordinates Lower Right register
(GFXSIG_HorizontalLowerRightW0)
The Evaluation Window horizontal co-ordinates Lower Right register defines the lower right x-axis position of the evaluation window for the Signature Unit.
Figure 20-136: Evaluation Window horizontal co-ordinates Lower Right register
04
03
02
01
00
0
0
0
0
06
0
0
07
0
05
08
0
HorizontalLowerRightW0
09
0
0
10
0
12
0
11
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
22
0
21
23
0
0
RW
Reserved
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_HorizontalLowerRightW0
Table 20-98: Evaluation Window horizontal co-ordinates Lower Right register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
HorizontalLow
erRightW0
Description
The value defines the x-axis position of the lower right corner of an
evaluation window in pixels from 0 to max. value 4095 (212 -1)
000011001000
20 - 178
(Example value) C8 = x position = 200
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.139Evaluation Window vertical co-ordinates Upper Left register
(GFXSIG_VerticalUpperLeftW0)
The Evaluation Window vertical co-ordinates Upper Left register defines the upper left y-axis position of
the evaluation window for the Signature Unit.
Figure 20-137: Evaluation Window vertical co-ordinates Upper Left register
02
01
00
0
0
06
0
0
07
0
03
08
0
0
09
0
04
10
0
0
11
0
05
12
0
VerticalUpperLeftW0
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
22
0
21
23
0
0
RW
Reserved
Reserved
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_VerticalUpperLeftW0
Table 20-99: Evaluation Window vertical co-ordinates Upper Left register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
VerticalUpper
LeftW0
Description
The value defines the y-axis position of the upper left corner of an
evaluation window in pixels from 0 to max. value 4095 (212 -1)
000011001000
Fujitsu Semiconductor Europe GmbH
(Example value) C8 = y position = 200
20 - 179
Revised 24/7/13
Iris-SDL Register Descriptions
20.140Evaluation Window vertical co-ordinates Lower Right register
(GFXSIG_VerticalLowerRightW0)
The Evaluation Window vertical co-ordinates Lower Right register defines the lower right y-axis position
of the evaluation window for the Signature Unit.
Figure 20-138: Evaluation Window vertical co-ordinates Lower Right register
04
03
02
01
00
0
0
0
0
06
0
0
07
0
05
08
0
VerticalLowerRightW0
09
0
0
10
0
12
0
11
13
0
14
0
16
0
0
17
0
15
18
0
0
19
0
22
0
20
23
0
0
24
0
21
25
0
0
RW
Reserved
Reserved
26
27
0
28
29
0
0
30
0
0
31
0
GFXSIG_VerticalLowerRightW0
Table 20-100: Evaluation Window vertical co-ordinates Lower Right register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
VerticalLower
RightW0
Description
The value defines the y-axis position of the lower right corner of an
evaluation window in pixels from 0 to max. value 4095 (212 -1)
000011001000
20 - 180
(Example value) C8 = y position = 200
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.141Signature A Reference Value Channel R register
(GFXSIG_SignAReferenceRW0)
The Signature A Reference Value Channel R register defines the signature A reference value for the
red channel of the evaluation window for the Signature Unit.
Figure 20-139: Signature A Reference Value Channel R register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignAReferenceRW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignAReferenceRW0
Table 20-101: Signature A Reference Value Channel R register bits
Bit position
Bit name
Description
[31:0]
SignAReferen
ceRW0
The value defines the reference value for the red channel of an evaluation
window for signature A.
Fujitsu Semiconductor Europe GmbH
20 - 181
Revised 24/7/13
Iris-SDL Register Descriptions
20.142Signature A Reference Value Channel G register
(GFXSIG_SignAReferenceGW0)
The Signature A Reference Value Channel G register defines the signature A reference value for the
green channel of the evaluation window for the Signature Unit.
Figure 20-140: Signature A Reference Value Channel G register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignAReferenceGW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignAReferenceGW0
Table 20-102: Signature A Reference Value Channel G register bits
Bit position
Bit name
Description
[31:0]
SignAReferen
ceGW0
The value defines the reference value for the green channel of an
evaluation window for signature A.
20 - 182
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.143Signature A Reference Value Channel B register
(GFXSIG_SignAReferenceBW0)
The Signature A Reference Value Channel B register defines the signature A reference value for the
blue channel of the evaluation window for the Signature Unit.
Figure 20-141: Signature A Reference Value Channel B register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignAReferenceBW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignAReferenceBW0
Table 20-103: Signature A Reference Value Channel B register bits
Bit position
Bit name
Description
[31:0]
SignAReferen
ceBW0
The value defines the reference value for the blue channel of an
evaluation window for signature A.
Fujitsu Semiconductor Europe GmbH
20 - 183
Revised 24/7/13
Iris-SDL Register Descriptions
20.144Signature B Reference Value Channel R register
(GFXSIG_SignBReferenceRW0)
The Signature B Reference Value Channel R register defines the signature B reference value for the
red channel of the evaluation window for the Signature Unit.
Figure 20-142: Signature B Reference Value Channel R register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignBReferenceRW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignBReferenceRW0
Table 20-104: Signature B Reference Value Channel R register bits
Bit position
Bit name
Description
[31:0]
SignBReferen
ceRW0
The value defines the reference value for the red channel of an
evaluation window for signature B.
20 - 184
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.145Signature B Reference Value Channel G register
(GFXSIG_SignBReferenceGW0)
The Signature B Reference Value Channel G register defines the signature B reference value for the
green channel of the evaluation window for the Signature Unit.
Figure 20-143: Signature B Reference Value Channel G register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignGReferenceRW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignBReferenceGW0
Table 20-105: Signature B Reference Value Channel G register bits
Bit position
Bit name
Description
[31:0]
SignBReferen
ceGW0
The value defines the reference value for the green channel of an
evaluation window for signature B.
Fujitsu Semiconductor Europe GmbH
20 - 185
Revised 24/7/13
Iris-SDL Register Descriptions
20.146Signature B Reference Value Channel B register
(GFXSIG_SignBReferenceBW0)
The Signature B Reference Value Channel B register defines the signature B reference value for the
blue channel of the evaluation window for the Signature Unit.
Figure 20-144: Signature B Reference Value Channel B register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
0
16
0
0
17
0
15
18
0
0
19
0
RW
SignBReferenceBW0
20
0
22
0
21
23
0
0
24
0
27
0
25
28
0
0
29
0
26
30
0
0
31
0
GFXSIG_SignBReferenceBW0
Table 20-106: Signature B Reference Value Channel B register bits
Bit position
Bit name
Description
[31:0]
SignBReferen
ceBW0
The value defines the reference value for the blue channel of an
evaluation window for signature B.
20 - 186
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.147Threshold Signature B Channel R register (GFXSIG_ThrBRW0)
The Threshold Signature B Channel R register defines the signature B threshold value for the red channel of the evaluation window for the Signature Unit.
Figure 20-145: Threshold Signature B Channel R register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
0
18
0
15
19
0
0
20
0
RW
ThrBRW0
21
22
0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_ThrBRW0
Table 20-107: Threshold Signature B Channel R register bits
Bit position
Bit name
Description
[31:0]
ThrBRW0
The value defines the threshold value (maximum tolerance value) for the
red channel of an evaluation window for signature B.
Example value using a red rectangle 10 x 10 pixels as the reference
value:
10 x 10 x (255,0,0) = 25,500 = 0x639C =
00000000000000000110001110011100 (binary). This is the reference
value.
If the transmitted value is not equal to 25,500 but e.g. 25,490 due to
transmission errors, then this threshold value can be used to decide to
handle this situation as an error (fail) or not (pass).
Fujitsu Semiconductor Europe GmbH
20 - 187
Revised 24/7/13
Iris-SDL Register Descriptions
20.148Threshold Signature B Channel G register (GFXSIG_ThrBGW0)
The Threshold Signature B Channel G register defines the signature B threshold value for the green
channel of the evaluation window for the Signature Unit.
Figure 20-146: Threshold Signature B Channel G register
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
12
0
11
13
0
14
16
0
0
17
0
0
18
0
15
19
0
0
20
0
RW
ThrBGW0
21
22
0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_ThrBGW0
Table 20-108: Threshold Signature B Channel G register bits
Bit position
Bit name
Description
[31:0]
ThrBGW0
The value defines the threshold value (maximum tolerance value) for the
green channel of an evaluation window for signature B.
Example value using a green rectangle 10 x 10 pixels as the reference
value:
10 x 10 x (0,255,0) = 25,500 = 0x639C =
00000000000000000110001110011100 (binary). This is the reference
value.
If the transmitted value is not equal to 25,500 but e.g. 25,490 due to
transmission errors, then this threshold value can be used to decide to
handle this situation as an error (fail) or not (pass).
20 - 188
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.149Threshold Signature B Channel B register (GFXSIG_ThrBBW0)
The Threshold Signature B Channel B register defines the signature B threshold value for the blue channel of the evaluation window for the Signature Unit.
Figure 20-147: Threshold Signature B Channel B register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
0
18
0
15
19
0
0
20
0
RW
ThrBBW0
21
22
0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_ThrBBW0
Table 20-109: Threshold Signature B Channel B register bits
Bit position
Bit name
Description
[31:0]
ThrBBW0
The value defines the threshold value (maximum tolerance value) for the
blue channel of an evaluation window for signature B.
Example value using a blue rectangle 10 x 10 pixels as the reference
value:
10 x 10 x (0,0,255) = 25,500 = 0x639C =
00000000000000000110001110011100 (binary). This is the reference
value.
If the transmitted value is not equal to 25,500 but e.g. 25,490 due to
transmission errors, then this threshold value can be used to decide to
handle this situation as an error (fail) or not (pass).
Fujitsu Semiconductor Europe GmbH
20 - 189
Revised 24/7/13
Iris-SDL Register Descriptions
20.150Error Counter Threshold register (GFXSIG_ErrorThreshold)
The Error Counter Threshold register defines the threshold value for consecutive error-free video frames
which cause the Sig_error_count bitfield of the Signature_error register to be reset. The register is not
shadowed.
Figure 20-148: Error Counter Threshold register
01
00
1
RW
Reserved
ErrThres
0
04
0
02
05
0
0
06
0
03
07
0
0
08
0
Reserved
09
12
0
10
13
0
0
14
0
0
15
0
11
16
0
RW
Reserved
0
17
20
0
0
21
0
18
22
0
19
23
0
0
24
0
1
25
0
ErrThresReset
26
0
28
0
27
29
0
Reserved
30
0
0
31
0
GFXSIG_ErrorThreshold
Table 20-110: Error Counter Threshold register bits
Bit position
Bit name
[31:24]
Reserved
[23:16]
ErrThresReset
[15:8]
Reserved
[7:0]
ErrThres
20 - 190
Description
The number of consecutive error-free video frames which cause the
SIG_error_count bitfield of the Signature_error register to be reset:
00000000
No reset
00000001
1 error-free video frame
...
...
11111111
255 error-free video frames
The threshold of the error counter. If the Signature_error.Sig_error_count
bitfield value is equal to or higher than this value, then an interrupt is
generated.
00000000
256 errors
00000001
1 error
...
...
11111111
255 errors
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.151Evaluation Windows Control and Configuration register
(GFXSIG_CtrlCfgW0)
The Evaluation Windows Control and Configuration register controls/configures the evaluation window
for the Signature Unit. The register is shadowed bitwise.
Figure 20-149: Evaluation Windows Control and Configuration register
02
01
0
0
Bit name
[31:17]
Reserved
16
EnCoordW0
[15:9]
Reserved
8
EnSignB
[7:1]
Reserved
0
EnSignA
EnSignA
Description
Enables the evaluation window using the configured coordinates.
0
Disables the evaluation window
1
Enables the evaluation window
Shadowed bit. Enables the calculation of Signature B
0
Disables the Signature B calculation unit
1
Enables the Signature B calculation unit
Shadowed bit. Enables the calculation of Signature A
0
Disables the Signature A calculation unit
1
Enables the Signature A calculation unit
Fujitsu Semiconductor Europe GmbH
20 - 191
0
RW
Reserved
0
Table 20-111: Evaluation Windows Control and Configuration register bits
Bit position
00
03
0
05
0
RW
0
04
06
0
EnSignB
Reserved
07
09
0
0
10
0
Reserved
0
08
11
Reserved
0
13
0
RW
0
12
14
0
17
0
15
18
0
0
19
0
0
16
20
0
EnCoordW0
21
22
0
0
23
0
24
25
0
Reserved
Reserved
0
28
0
26
29
0
0
30
0
27
31
0
GFXSIG_CtrlCfgW0
Revised 24/7/13
Iris-SDL Register Descriptions
20.152Trigger register (GFXSIG_TriggerW0)
The Trigger register configures the trigger mode of the evaluation window signature generation and triggers the signature generation itself.
Figure 20-150: Trigger register
02
01
0
0
Bit name
[31:10]
Reserved
[9:8]
TrigMode
[7:1]
Reserved
0
Trigger
20 - 192
Trigger
Description
Configures the trigger mode of the evaluation window:
00
Start a one-off signature generation (also cancels
cyclic generation)
01
Start cyclic signature generation (also cancels
one-off generation)
10
Reserved
11
Reserved
Triggers the signature generation in the mode defined in the TrigMode
bitfield:
0
Disregarded
1
Triggers the signature generation
Fujitsu Semiconductor Europe GmbH
0
W
Reserved
0
Table 20-112: Trigger register bits
Bit position
00
03
05
0
0
06
0
04
07
0
Reserved
08
09
TrigMode
RW
Reserved
0
0
10
0
12
0
0
13
0
11
14
0
0
15
16
0
0
17
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
Reserved
31
0
GFXSIG_TriggerW0
Iris-SDL Register Descriptions
Revised 24/7/13
20.153Interrupt Enable register (GFXSIG_IENW0)
The Interrupt Enable register enables/disables a black display output in the event that the SIG unit traps
a signature error.
Figure 20-151: Interrupt Enable register
14
13
12
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IEnDiff
0
RW
Reserved
0
00
15
0
16
17
Reserved
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
31
0
GFXSIG_IENW0
Table 20-113: Interrupt Enable register bits
Bit position
Bit name
[31:1]
Reserved
0
IEnDiff
Description
Display output can be turned to black in the event that the SIG unit traps a
signature error. See also 20.154 Interrupt Status register
(GFXSIG_InterruptStatusW0).
0
Disables the signal
1
Enables the signal
Fujitsu Semiconductor Europe GmbH
20 - 193
Revised 24/7/13
Iris-SDL Register Descriptions
20.154Interrupt Status register (GFXSIG_InterruptStatusW0)
The Interrupt Status register signifies that a Signature Unit error has occurred.
Figure 20-152: Interrupt Status register
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
IStsDiff
RW
0
0
Reserved
0
00
10
0
12
0
0
13
0
11
14
0
0
15
0
16
17
0
Reserved
18
23
0
19
24
0
0
25
0
0
26
0
20
27
0
0
28
0
21
29
0
0
30
0
22
31
0
GFXSIG_InterruptStatusW0
Table 20-114: Interrupt Status register bits
Bit position
Bit name
[31:1]
Reserved
0
IStsDiff
20 - 194
Description
Indicates whether an signature error condition occurred. Condition: the
number of error frames (a difference between the current signature and the
reference value) is higher than the set threshold value (ErrThres bitfield of
the ErrorThreshold register).
0
The condition did not occur
1
The condition occurred. Write a ‘1’ again to clear this bitfield (the
clear has a higher priority than the set action). Condition: the
number of error frames (difference between the current signature
and the reference value) is higher than the value configured in
the ErrorThreshold register.
If IENW0.IEnDiff is enabled, then that bit directly controls the
black output for display. Writing a 1 here stops black display.
See also 20.153 Interrupt Enable register (GFXSIG_IENW0).
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.155Status register (GFXSIG_StatusW0)
The Status register delivers the results of the various signature comparisons. It also signals whether the
signature generation task is active or pending.
Figure 20-153: Status register
01
00
Active
Pendingg
R
R
0
0
02
0
Reserved
0
0
03
04
0
Reserved
05
06
0
07
Reserved
08
Diff_A_R
R
0
RWS
09
R
0
10
Diff_A_B
Diff_A_G
R
0
11
0
Reserved
0
0
12
0
13
14
0
Reserved
15
16
Diff_B_R
R
0
0
17
Diff_B_G
R
0
19
0
18
20
0
Diff_B_B
21
0
R
22
0
Reserved
0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
Reserved
31
0
GFXSIG_StatusW0
Table 20-115: Status register bits
Bit position
Bit name
[31:19]
Reserved
18
Diff_B_B
17
16
[15:11]
Diff_B_G
Diff_B_R
Description
Indicates whether the results of the comparison of the Signature B (valid) B
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Indicates whether the results of the comparison of the Signature B (valid) G
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Indicates whether the results of the comparison of the Signature B (valid) R
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 195
Revised 24/7/13
10
9
8
Iris-SDL Register Descriptions
Diff_A_R
Diff_A_R
Diff_A_R
[7:2]
Reserved
1
Active
0
20 - 196
Pending
Indicates whether the results of the comparison of the Signature A (valid) R
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Indicates whether the results of the comparison of the Signature A (valid) R
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Indicates whether the results of the comparison of the Signature A (valid) R
result with the reference value are equal or different:
0
The values are equal
1
The values are different
Indicates whether the generation of a signature is active:
0
The signature generation is not active.
1
The signature generation is active.
Indicates whether a signature generation task is pending:
0
Signature generation is not pending.
1
Signature generation is pending.
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.156Video Frame Signature Error Count register
(GFXSIG_Signature_error)
The Video Frame Signature Error Count register returns the number of video frames with signature errors.
Figure 20-154: Video Frame Signature Error Count register
01
00
0
06
0
0
07
0
02
08
0
0
09
0
03
10
0
0
11
0
04
12
0
0
13
0
05
14
0
Sig_error_count
15
0
0
16
0
17
0
22
0
18
23
0
19
24
0
0
25
0
0
26
0
20
27
0
0
28
0
21
29
0
0
30
0
R
Reserved
Reserved
31
0
GFXSIG_Signature_error
Table 20-116: Video Frame Signature Error Count register bits
Bit position
Bit name
[31:12]
Reserved
[11:0]
Sig_error_count
Description
Returns the number of video frames with signature errors. A signature
generation trigger (see TriggerW0 register) will reset this bitfield to 0.
0 ... 4096
Fujitsu Semiconductor Europe GmbH
The number of video frames with signature errors.
20 - 197
Revised 24/7/13
Iris-SDL Register Descriptions
20.157Signature A Result for Channel R register
(GFXSIG_SignatureARW0)
The Signature A Result for Channel R register returns the 32-bit signature generated by the Signature
A unit for the R channel.
Figure 20-155: Signature A Result for Channel R register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
12
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureARW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureARW0
Table 20-117: Signature A Result for Channel R register bits
Bit position
Bit name
Description
[31:0]
SignatureARW0
The 32-bit signature generated by the Signature A unit for the R
channel.
20 - 198
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.158Signature A Result for Channel G register
(GFXSIG_SignatureAGW0)
The Signature A Result for Channel G register returns the 32-bit signature generated by the Signature
A unit for the G channel.
Figure 20-156: Signature A Result for Channel G register
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureAGW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureAGW0
Table 20-118: Signature A Result for Channel G register bits
Bit position
Bit name
Description
[31:0]
SignatureAGW0
The 32-bit signature generated by the Signature A unit for the G
channel.
Fujitsu Semiconductor Europe GmbH
20 - 199
Revised 24/7/13
Iris-SDL Register Descriptions
20.159Signature A Result for Channel B register
(GFXSIG_SignatureABW0)
The Signature A Result for Channel B register returns the 32-bit signature generated by the Signature
A unit for the B channel.
Figure 20-157: Signature A Result for Channel B register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
12
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureABW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureABW0
Table 20-119: Signature A Result for Channel B register bits
Bit position
Bit name
Description
[31:0]
SignatureABW0
The 32-bit signature generated by the Signature A unit for the B
channel.
20 - 200
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.160Signature B Result for Channel R register
(GFXSIG_SignatureARW0)
The Signature B Result for Channel R register returns the 32-bit signature generated by the Signature
B unit for the R channel.
Figure 20-158: Signature B Result for Channel R register
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureBRW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureBRW0
Table 20-120: Signature B Result for Channel R register bits
Bit position
Bit name
Description
[31:0]
SignatureBRW0
The 32-bit signature generated by the Signature B unit for the R
channel.
Fujitsu Semiconductor Europe GmbH
20 - 201
Revised 24/7/13
Iris-SDL Register Descriptions
20.161Signature B Result for Channel G register
(GFXSIG_SignatureBGW0)
The Signature B Result for Channel G register returns the 32-bit signature generated by the Signature
B unit for the G channel.
Figure 20-159: Signature B Result for Channel G register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
12
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureBGW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureBGW0
Table 20-121: Signature B Result for Channel G register bits
Bit position
Bit name
Description
[31:0]
SignatureBGW0
The 32-bit signature generated by the Signature B unit for the G
channel.
20 - 202
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.162Signature B Result for Channel B register
(GFXSIG_SignatureBBW0)
The Signature B Result for Channel B register returns the 32-bit signature generated by the Signature
B unit for the B channel.
Figure 20-160: Signature B Result for Channel B register
12
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
0
22
R
SignatureBBW0
23
0
26
0
0
27
0
24
28
0
0
29
0
25
30
0
0
31
0
GFXSIG_SignatureBBW0
Table 20-122: Signature B Result for Channel B register bits
Bit position
Bit name
Description
[31:0]
SignatureBBW0
The 32-bit signature generated by the Signature B unit for the B
channel.
Fujitsu Semiconductor Europe GmbH
20 - 203
Revised 24/7/13
Iris-SDL Register Descriptions
20.163Display Controller Enable register (GFXDISP_DisplayEnable)
The Display Controller Enable register enables or disables the Display Controller.
Figure 20-161: Display Controller Enable register
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
DEN
20 - 204
DEN
RW
Description
Disables or Enables the Display Controller, allows its on/off status to
be read.
0
DISPLAYOFF: Disable Display Controller/Display Controller is
disabled.
1
DISPLAYON: Enable Display Controller/Display Controller is
enabled.
Fujitsu Semiconductor Europe GmbH
0
0
Reserved
Table 20-123: Display Controller Enable register bits
Bit position
00
10
0
12
0
0
13
0
11
14
0
0
15
0
16
17
Reserved
0
19
0
18
20
0
0
21
0
25
0
22
26
0
23
27
0
0
28
0
0
29
0
24
30
0
0
31
0
GFXDISP_DisplayEnable
Iris-SDL Register Descriptions
Revised 24/7/13
20.164Display Controller Resolution register
(GFXDISP_DisplayResolution)
The Display Controller Resolution register configures the display resolution (vertical lines and horizontal
pixel count) of the Display Controller.
Figure 20-162: Display Controller Resolution Configuration register
02
01
00
0
0
0
RW
Reserved
HTP
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
0
11
14
0
0
15
0
12
16
0
0
17
0
13
18
0
Reserved
19
0
VTR
RW
Reserved
0
20
22
0
0
23
0
21
24
0
0
25
0
27
0
26
28
0
0
29
0
30
0
Reserved
31
0
GFXDISP_DisplayResolution
Table 20-124: Display Controller Resolution Configuration register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
VTR
[15:12]
Reserved
[11:0]
HTP
Fujitsu Semiconductor Europe GmbH
Description
Specifies the Vertical Total Resolution (VTR) line count
Range 0 ... 4095
Specifies the Horizontal Total Pixel (HTP) count
Range 0 ... 4095
20 - 205
Revised 24/7/13
Iris-SDL Register Descriptions
20.165Active Display Area Configuration register
(GFXDISP_DisplayActiveArea)
The Active Display Area Configuration register configures the active display area (vertical and horizontal
display periods) of the Display Controller.
Figure 20-163: Active Display Area Configuration register
02
01
00
0
0
0
RW
Reserved
HDP
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
0
11
14
0
0
15
0
12
16
0
0
17
0
13
18
0
Reserved
19
0
VDP
RW
Reserved
0
20
0
22
0
21
23
0
0
24
26
0
0
27
0
25
28
0
0
29
0
30
0
Reserved
31
0
GFXDISP_DisplayActiveArea
Table 20-125: Active Display Area Configuration register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
VDP
[15:12]
Reserved
[11:0]
HDP
20 - 206
Description
Specifies the Vertical Display Period (VDP) in units of pixels
Range 0 ... 4095
Specifies the Horizontal Display Period (HDP) n units of pixels
Range 0 ... 4095
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.166Horizontal Synchronization Timing Configuration register
(GFXDISP_HorizontalSynchTimingConf)
The Horizontal Synchronization Timing Configuration register configures the horizontal synchronization
output timing of the Display Controller.
Figure 20-164: Horizontal Synchronization Timing Configuration register
02
01
00
0
0
0
RW
Reserved
HSP
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
0
11
14
0
0
15
0
12
16
0
0
17
0
13
18
0
Reserved
19
0
HSW
RW
Reserved
0
20
22
0
0
23
0
21
24
0
0
25
0
27
0
26
28
0
0
29
0
30
0
Reserved
31
0
GFXDISP_HorizontalSynchTimingConf
Table 20-126: Horizontal Synchronization Timing Configuration register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
HSW
[15:12]
Reserved
[11:0]
HSP
Fujitsu Semiconductor Europe GmbH
Description
Specifies the pulse width of the horizontal synchronization signal in
units of pixels
Range 0 ... 4095
Specifies the position of the horizontal synchronization signal in units
of pixels
Range 0 ... 4095
20 - 207
Revised 24/7/13
Iris-SDL Register Descriptions
20.167Vertical Synchronization Timing Configuration register
(GFXDISP_VerticalSynchTimingConf)
The Vertical Synchronization Timing Configuration register configures the vertical synchronization output timing of the Display Controller.
Figure 20-165: Vertical Synchronization Timing Configuration register
02
01
00
0
0
0
RW
Reserved
HSP
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
0
11
0
14
0
12
15
0
0
16
0
13
17
0
Reserved
18
0
HSW
0
RW
Reserved
0
19
0
22
0
20
23
0
0
24
0
21
25
0
0
26
0
28
0
27
29
0
30
0
Reserved
31
0
GFXDISP_VerticalSynchTimingConf
Table 20-127: Vertical Synchronization Timing Configuration register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
VSW
[15:12]
Reserved
[11:0]
VSP
20 - 208
Description
Specifies the pulse width of the vertical synchronization signal in units
of pixels
Range 0 ... 4095
Specifies the position of the vertical synchronization signal in units of
pixels
Range 0 ... 4095
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.168Display Controller Miscellaneous Configuration register
(GFXDISP_DisplayConf)
The Display Controller Miscellaneous Configuration register specifies the polarity of the HSYNC and
VSYNC synchronisation signals of the Display Controller.
Figure 20-166: Display Controller Miscellaneous Configuration register
13
12
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
POLSYNC
Fujitsu Semiconductor Europe GmbH
RW
Description
Specifies the polarity of the HSYNC and VSYNC synchronisation
signals:
0
Low active
1
High active
20 - 209
0
0
Reserved
0
Table 20-128: Display Controller Miscellaneous Configuration register bits
Bit position
00
14
0
POLSYNC
15
0
19
0
16
20
0
17
21
0
Reserved
22
0
0
23
0
18
24
0
0
25
0
28
0
26
29
0
0
30
0
27
31
0
GFXDISP_DisplayConf
Revised 24/7/13
Iris-SDL Register Descriptions
20.169Pixel Engine Trigger Point register (GFXDISP_PixEngTrig)
The Pixel Engine Trigger Point register specifies on which row and column of the display raster the Pixel
Engine synchronization signal is triggered.
Figure 20-167: Pixel Engine Trigger Point register
03
02
01
00
0
0
0
RW
Reserved
PESCOL
0
06
0
04
07
0
0
08
0
05
09
0
10
Reserved
0
14
0
0
15
0
11
16
0
0
17
0
12
18
0
0
19
0
13
20
0
RW
Reserved
0
21
0
22
PESROW
23
25
0
0
26
0
0
27
0
24
28
0
0
29
0
30
0
Reserved
31
0
GFXDISP_PixEngTrig
Table 20-129: Pixel Engine Trigger Point register bits
Bit position
Bit name
[31:28]
Reserved
[27:16]
PESROW
[15:12]
Reserved
[11:0]
PESCOL
20 - 210
Description
Specifies on which row of the display raster the synchronisation signal
(Pixel Engine kick signal) is triggered, whereby 0 < PESROW < HTP.
HTP = Horizontal Total Pixels.
Range 0 ... 4095
Specifies on which column of the display raster the synchronisation
signal (Pixel Engine kick signal) is triggered, whereby 0 < PESCOL <
VTR. VTR = Vertical Total Resolution.
Range 0 ... 4095
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.170Dither Unit Control register (GFXDISP_DitherControl)
The Dither Unit Control register is used to configure the dither unit.
Figure 20-168: Dither Unit Control register
01
00
dither_mode
dither_bypass
RW
RW
0
1
Reserved
RWS
0
03
0
02
04
0
05
dither_format
Reserved
RWS
0
RW
0
RW
09
0
06
10
0
0
11
0
0
0
12
0
07
13
0
Reserved
0
08
14
0
dither_align
15
21
0
0
22
0
16
23
0
0
24
0
17
25
0
0
26
0
18
27
0
19
28
0
0
29
0
20
30
0
Reserved
31
0
GFXDISP_DitherControl
Table 20-130: Dither Unit Control register bits
Bit position
Bit name
[31:9]
Reserved
8
dither_align
[7:6]
Reserved
[5:4]
dither_format
[3:2]
Reserved
1
dither_mode
Fujitsu Semiconductor Europe GmbH
Description
Specifies the dithered output byte alignment:
0
Bytes are right-aligned
1
Bytes are left-aligned
Specifies the RGB format of the dithered output:
00
888
01
777
10
666
11
656
Specifies the use of temporal or spatial dithering:
0
Temporal dithering is used
1
Spatial dithering is used
20 - 211
Revised 24/7/13
0
20 - 212
Iris-SDL Register Descriptions
dither_bypass
Enables or disables a bypass of the Dither Unit:
0
Disable the bypass
1
Enable the bypass
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.171Trigger Point Coordinates for INT0 register
(GFXDISP_INT0Trigger)
The Trigger Point Coordinates for INT0 register specifies on which row and column of the display raster
that the Display Controller INT0 signal is triggered and enables/disables the interrupt signal.
Figure 20-169: Trigger Point Coordinates for INT0 register
02
01
00
0
0
0
INT0COL
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
RW
Reserved
RW
0
11
0
Reserved
12
14
0
0
15
0
13
16
0
0
17
0
19
0
18
20
0
0
21
22
0
0
0
23
0
INT0ROW
24
0
26
0
25
27
0
0
28
0
29
30
Reserved
0
0
RW
Reserved
INT0EN
31
GFXDISP_INT0Trigger
Table 20-131: Trigger Point Coordinates for INT0 register bits
Bit position
Bit name
Description
31
INT0EN
Enables or disables the INT0 interrupt signal:
[30:28]
Reserved
[27:16]
INT0ROW
[15:12]
Reserved
[11:0]
INT0COL
Fujitsu Semiconductor Europe GmbH
0
DIS: the interrupt is disabled
1
ENA: the interrupt is enabled
Specifies on which row of the display raster that the INT0 signal is
triggered (whereby 0 < INT0ROW < HTP). HTP = Horizontal Total
Pixels.
Range 0 ... 4095
Specifies on which column of the display raster the INT0 signal is
triggered (0 < INT0COL < VTR). VTR = Vertical Total Resolution.
Range 0 ... 4095
20 - 213
Revised 24/7/13
Iris-SDL Register Descriptions
20.172Trigger Point Coordinates for INT1 register
(GFXDISP_INT1Trigger)
The Trigger Point Coordinates for INT1 register specifies on which row and column of the display raster
that the Display Controller INT1 signal is triggered and enables/disables the interrupt signal.
Figure 20-170: Trigger Point Coordinates for INT1 register
02
01
00
0
0
0
INT1COL
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
RW
Reserved
RW
0
11
0
Reserved
12
14
0
0
15
0
13
16
0
0
17
0
19
0
18
20
0
0
21
22
0
0
0
23
0
INT1ROW
24
0
26
0
25
27
0
0
28
0
29
30
Reserved
0
0
RW
Reserved
INT1EN
31
GFXDISP_INT1Trigger
Table 20-132: Trigger Point Coordinates for INT1 register bits
Bit position
Bit name
Description
31
INT1EN
Enables or disables the INT1 interrupt signal:
[30:28]
Reserved
[27:16]
INT1ROW
[15:12]
Reserved
[11:0]
INT1COL
20 - 214
0
DIS: the interrupt is disabled
1
ENA: the interrupt is enabled
Specifies on which row of the display raster that the INT1 signal is
triggered (whereby 0 < INT0ROW < HTP). HTP = Horizontal Total
Pixels.
Range 0 ... 4095
Specifies on which column of the display raster the INT1 signal is
triggered (0 < INT0COL < VTR). VTR = Vertical Total Resolution.
Range 0 ... 4095
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.173Trigger Point Coordinates for INT2 register
(GFXDISP_INT2Trigger)
The Trigger Point Coordinates for INT2 register specifies on which row and column of the display raster
that the Display Controller INT2 signal is triggered and enables/disables the interrupt signal.
Figure 20-171: Trigger Point Coordinates for INT2 register
02
01
00
0
0
0
INT2COL
03
06
0
0
07
0
04
08
0
0
09
0
05
10
0
RW
Reserved
RW
0
11
0
Reserved
12
14
0
0
15
0
13
16
0
0
17
0
19
0
18
20
0
0
21
22
0
0
0
23
0
INT2ROW
24
0
26
0
25
27
0
0
28
0
29
30
Reserved
0
0
RW
Reserved
INT2EN
31
GFXDISP_INT2Trigger
Table 20-133: Trigger Point Coordinates for INT2 register bits
Bit position
Bit name
Description
31
INT2EN
Enables or disables the INT2 interrupt signal:
[30:28]
Reserved
[27:16]
INT2ROW
[15:12]
Reserved
[11:0]
INT2COL
Fujitsu Semiconductor Europe GmbH
0
DIS: the interrupt is disabled
1
ENA: the interrupt is enabled
Specifies on which row of the display raster that the INT2 signal is
triggered (whereby 0 < INT0ROW < HTP). HTP = Horizontal Total
Pixels.
Range 0 ... 4095
Specifies on which column of the display raster the INT2 signal is
triggered (0 < INT0COL < VTR). VTR = Vertical Total Resolution.
Range 0 ... 4095
20 - 215
Revised 24/7/13
Iris-SDL Register Descriptions
20.174Debug register (GFXDISP_Debug)
The Debug register makes it possible to display a frame, even though it is expected to be distorted for
debugging purposes.
Figure 20-172: Debug register
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
Bit name
[31:1]
Reserved
0
ShowDistFrames
20 - 216
RW
Description
Display a frame, even though it is expected to be distorted for
debugging purposes (e.g. because the frame’s actual size does not
matched the programmed size):
0
Don’t show the frame
1
Show the frame
Fujitsu Semiconductor Europe GmbH
0
0
Table 20-134: Debug register bits
Bit position
00
09
ShowDistFrames
10
0
12
0
0
13
0
11
14
0
0
15
0
16
17
Reserved
Reserved
22
0
0
23
0
18
24
0
19
25
0
0
26
0
0
27
0
20
28
0
0
29
0
21
30
0
0
31
0
GFXDISP_Debug
Iris-SDL Register Descriptions
Revised 24/7/13
20.175Sequencer Position Definitions registers
(GFXTCON_DIR_SSqCnts[0...63])
The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold
their output value and assign the sequencer to an odd/even field. Only 32-bit (word) access is permitted.
Figure 20-173: Sequencer Position Definitions registers
04
03
02
01
00
X
X
X
X
X
RW
SSQCNTS_SEQY
X
08
X
05
09
X
06
10
X
X
11
X
X
12
X
RW
X
07
13
X
16
X
14
17
X
X
18
X
RW
X
15
19
X
SSQCNTS_FIELD
20
X
24
X
21
25
X
X
26
X
22
27
X
X
28
X
23
29
X
SSQCNTS_SEQX
30
X
X
RW
SSQCNTS_OUT
31
GFXTCON_DIR_SSqCnts[0...63]
Table 20-135: Sequencer Position Definitions registers bits
Bit position
Bit name
Description
31
SSQCNTS_OUT
This bit holds the value (0,1) to be output when the X/Y scan
position is reached.
[30:16]
SSQCNTS_SEQX
This bitfield defines the scan position on the X axis for sequencer
output
15
SSQCNTS_FIELD
This bit assigns the sequencer output to an odd or even field:
[14:0]
SSQCNTS_SEQY
Fujitsu Semiconductor Europe GmbH
0
Odd field
1
Even field
This bitfield defines the scan position on the Y axis for sequencer
output
20 - 217
Revised 24/7/13
Iris-SDL Register Descriptions
20.176Timing Controller Software Reset register
(GFXTCON_DIR_SWreset)
The Timing Controller Software Reset register is used to reset the Timing Controller under specific conditions.
Figure 20-174: Timing Controller Software Reset register
12
11
10
09
08
07
06
05
04
03
02
01
0
0
0
0
0
0
0
0
0
0
0
0
Bit name
[30:1]
Reserved
0
SWReset
20 - 218
SWReset
RW
Description
This bit is used to reset the Timing Controller by software. A
software reset is de asserted by internal logic. Please note that
specific conditions must be met before a reset can be initiated.
These are described further on in this documentation (TCON
chapter).
0
Reset is inactive (no effect)
1
Active Reset (i.e. the last pixel of a video frame was
not input to the TCON since the software reset was
last activated)
Fujitsu Semiconductor Europe GmbH
1
0
Reserved
Table 20-136: Timing Controller Software Reset register bits
Bit position
00
13
0
17
0
14
18
0
0
19
0
15
20
0
16
21
0
0
22
0
Reserved
23
26
0
24
27
0
0
28
0
0
29
0
25
30
0
0
31
0
GFXTCON_DIR_SWreset
Iris-SDL Register Descriptions
Revised 24/7/13
20.177Sequencer Pulse Generator [0...11] On Position register
(GFXTCON_DIR_SPG[0...11]PosOn)
The Sequencer Pulse Generator [0...11] On Position register is used to configure the operation mode
and X/Y scan positions for the SPG[0...11] unit’s On position.
Figure 20-175: Sequencer Pulse Generator [0...11] On Position register
03
02
01
00
0
0
0
0
0
RW
SPGSON_Y[0...11]
04
08
0
05
09
0
0
10
0
0
11
0
06
12
0
0
13
0
07
14
0
RW
0
0
15
16
18
0
SPGSON_FIELD[0...11]
19
0
0
20
0
17
21
0
0
22
0
24
SPGSON_X[0...11]
RW
RW
0
23
25
0
27
0
0
28
0
26
29
0
0
30
0
SPGSN_TOGGLE[0...11]
31
GFXTCON_DIR_SPG[0...11]PosOn
Table 20-137: Sequencer Pulse Generator [0...11] On Position register bits
Bit position
Bit name
Description
31
SPGSON_TOGGLE[0...11]
This bitfield enables/disables the SPG[0...11] unit’s On
position:
0
SPG[0...11] On position is disabled
1
SPG[0...11] Off position is enabled
[30:16]
SPGSON_X[0...11]
This bitfield defines the scan position on the X axis for
SPG[0...11]
15
SPGSON_FIELD[0...11]
This bit assigns the SPG[0...11] output to an odd or even
field:
[14:0]
SPGSON_Y[0...11]
Fujitsu Semiconductor Europe GmbH
0
Odd field
1
Even field
This bitfield defines the scan position on the Y axis for
SPG[0...11]
20 - 219
Revised 24/7/13
Iris-SDL Register Descriptions
20.178Sequencer Pulse Generator [0...11] Mask Enable register
(GFXTCON_DIR_SPG[0...11]MaskOn)
The Sequencer Pulse Generator [0...11] Mask Enable register is used to mask the enable bit of each of
the 12 SPGs.
Figure 20-176: Sequencer Pulse Generator [0...11] Mask Enable register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
12
18
0
0
19
0
13
20
0
0
21
0
14
22
0
0
23
0
15
24
0
SPGMKON[0...11]
25
27
0
0
28
0
26
29
0
0
30
0
RW
0
0
Reserved
Reserved
31
GFXTCON_DIR_SPG[0...11]MaskOn
Table 20-138: Sequencer Pulse Generator [0...11] Mask Enable register bits
Bit position
Bit name
31
Reserved
[30:0]
SPGMKON[0...11]
20 - 220
Description
This bit is used to mask the enable of the respective SPGs:
0
Include the respective bit in position matching
1
Do not include the respective in position matching
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.179Sequencer Pulse Generator [0...11] Off Position register
(GFXTCON_DIR_SPG[0...11]PosOff)
The Sequencer Pulse Generator [0...11] Off Position register is used to configure the operation mode
and X/Y scan positions for the SPG[0...11] unit’s Off position.
Figure 20-177: Sequencer Pulse Generator [0...11] Off Position register
03
02
01
00
0
0
0
04
0
05
0
RW
SPGSOFF_Y[0...11]
0
08
0
0
09
0
06
10
0
0
11
0
0
RW
0
07
12
16
0
0
17
0
13
18
0
14
19
0
0
20
0
0
15
21
0
SPGSOFF_FIELD[0...11]
22
0
24
SPGSOFF_X[0...11]
RW
RW
0
23
25
0
27
0
0
28
0
26
29
0
0
30
0
SPGSOFF_TOGGLE[0...11]
31
GFXTCON_DIR_SPG0PosOff
Table 20-139: Sequencer Pulse Generator [0...11] Off Position register bits
Bit position
Bit name
Description
31
SPGSOFF_TOGGLE[0...11]
This bitfield enables/disables the SPG[0...11] unit’s Off
position:
0
SPG[0...11] Off position is disabled
1
SPG[0...11] Off position is enabled
[30:16]
SPGSOFF_X[0...11]
This bitfield defines the scan position on the X axis for
SPG[0...11]
15
SPGSOFF_FIELD[0...11]
This bit assigns the respective SPG[0...11] outputs to an
odd or even field:
[14:0]
SPGSOFF_Y[0...11]
Fujitsu Semiconductor Europe GmbH
0
Odd field
1
Even field
This bitfield defines the scan position on the Y axis for
SPG[0...11]
20 - 221
Revised 24/7/13
Iris-SDL Register Descriptions
20.180Sequencer Pulse Generator [0...11] Mask Enable register
(GFXTCON_DIR_SPG[0...11]MaskOff)
The Sequencer Pulse Generator [0...11] Mask Enable register is used to mask the disable bit of each
of the 12 SPGs.
Figure 20-178: Sequencer Pulse Generator [0...11] Mask Enable register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
12
18
0
0
19
0
13
20
0
0
21
0
14
22
0
0
23
0
15
24
0
SPGMKOFF[0...11]
25
27
0
0
28
0
26
29
0
0
30
0
RW
0
0
Reserved
Reserved
31
GFXTCON_DIR_SPG[0...11]MaskOff
Table 20-140: Sequencer Pulse Generator [0...11] Mask Enable register bits
Bit position
Bit name
31
Reserved
[30:0]
SPGMKOFF[0...11]
20 - 222
Description
This bit is used to mask the disable of the respective SPGs:
0
Include the respective bit in position matching
1
Do not include the respective in position matching
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.181Sequencer Cycle Length register (GFXTCON_DIR_SSqCycle)
The Sequencer Cycle Length register is used to set the sequencer cycle length (value set here minus 1).
Figure 20-179: Sequencer Cycle Length register
10
09
08
07
06
05
04
0
0
0
0
0
0
0
00
11
0
01
12
0
0
13
0
0
14
0
02
15
0
0
16
0
03
17
0
SSQCYCLE
18
Reserved
RW
0
19
0
0
20
0
Reserved
21
0
25
0
22
26
0
0
27
0
23
28
0
24
29
0
0
30
0
0
31
0
GFXTCON_DIR_SSqCycle
Table 20-141: Sequencer Cycle Length register bits
Bit position
Bit name
[31:6]
Reserved
[5:0]
SSQCYCLE
Fujitsu Semiconductor Europe GmbH
Description
This bitfield sets the sequencer cycle length. The value set here -1
is the number of sequencer cycles The valid range is 0 ... 63.
20 - 223
Revised 24/7/13
Iris-SDL Register Descriptions
20.182Sync Mixer [0...11] Signal Selection register
(GFXTCON_DIR_SMx[0...11]Sigs)
The Sync Mixer [0...11] Signal Selection register is used to select the Sync Mixer [0...11] input signal
from one of five possible input paths (S0 ... S4), each of which can use different sources.
Figure 20-180: Sync Mixer [0...11] Signal Selection register
Bit name
[31:15]
Reserved
[14:12]
SMX[0...11]SIGS_S4
[11:9]
20 - 224
SMX[0...11]SIGS_S3
Description
Selects the input signal for the sync mixers:
000
Constant zero
001
Sync sequencer output
010 ...
111
Sync pulse generator 0 ... 5 output
Selects the input signal for the sync mixers:
000
Constant zero
001
Sync sequencer output
010 ...
111
Sync pulse generator 0 ... 5 output
Fujitsu Semiconductor Europe GmbH
0
0
RW
Table 20-142: Sync Mixer [0...11] Signal Selection register bits
Bit position
00
01
02
0
0
RW
SMX[0...11]SIGS_S0
03
0
04
05
0
0
RW
SMX[0...11]SIGS_S1
06
0
07
08
0
SMX[0...11]SIGS_S2
09
0
0
RW
RW
0
10
11
14
0
SMX[0...11]SIGS_S3
15
0
0
16
0
12
17
0
0
18
0
Reserved
0
13
19
0
SMX[0...11]SIGS_S4
20
24
0
21
25
0
0
26
0
0
27
0
22
28
0
0
29
0
23
30
0
Reserved
31
0
GFXTCON_DIR_SMx[0...11]Sigs
Iris-SDL Register Descriptions
[8:6]
[5:3]
[2:0]
SMX[0...11]SIGS_S2
SMX[0...11]SIGS_S1
SMX[0...11]SIGS_S0
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Selects the input signal for the sync mixers:
000
Constant zero
001
Sync sequencer output
010 ...
111
Sync pulse generator 0 ... 5 output
Selects the input signal for the sync mixers:
000
Constant zero
001
Sync sequencer output
010 ...
111
Sync pulse generator 0 ... 5 output
Selects the input signal for the sync mixers:
000
Constant zero
001
Sync sequencer output
010 ...
111
Sync pulse generator 0 ... 5 output
20 - 225
Revised 24/7/13
Iris-SDL Register Descriptions
20.183Sync Mixer [0...11] Function Table Selection register
(GFXTCON_DIR_SMx[0...11]FctTable)
The Sync Mixer [0...11] Function Table Selection register is used to select the function table used for
Sync Mixer [0...11] output.
Figure 20-181: Sync Mixer [0...11] Function Table Selection register
11
10
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
0
0
0
16
0
0
17
0
12
18
0
0
19
0
13
20
0
14
21
0
0
22
0
0
23
0
15
24
0
0
0
RW
SMXFCT[0...11]
25
0
0
26
28
0
0
29
0
27
30
0
31
GFXTCON_DIR_SMx[0...11]FctTable
Note:
Register GFXTCON_DIR_SM11FctTable, is an exception. In this case, the reset value is FFFFFFFFh
Table 20-143: Sync Mixer [0...11] Function Table Selection register bits
Bit position
Bit name
Description
[31:0]
SMXFCT[0...11]
The sync mixer output is the result of the function table:
[a] a = s4*24+s3*23+s2*22+s1*21+s0*20
Whereby:
a = bit number
s = result of sync mixer input selection
20 - 226
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.184Sync Switch register (GFXTCON_DIR_SSwitch)
The Sync Switch register is used to configure the TSIG output.
Figure 20-182: Sync Switch register
03
02
01
00
0
0
0
0
04
07
0
0
08
0
05
09
0
06
10
0
0
RW
RW
0
0
11
0
SSWITCH
12
InvCtrEn
Reserved
Reserved
0
0
16
0
13
17
0
0
18
0
14
19
RW
0
15
20
23
0
0
24
0
0
25
0
21
26
0
0
27
0
22
28
0
EnOptClk
29
0
30
0
0
Reserved
Reserved
31
GFXTCON_DIR_SSwitch
Table 20-144: Sync Switch register bits
Bit position
Bit name
[31:29]
Reserved
[28:16]
EnOptClk
[15:14]
Reserved
13
InvCtrEn
[12:0]
SSWITCH
Fujitsu Semiconductor Europe GmbH
Description
Enables the optional (delayed) sampling clock signal for each of the
respective TCON control signals:
0
Disable use of optional (delayed) clock
1
Enable use of optional (delayed) clock
This bit enables the inversion of the TSIG outputs:
0
Inversion is disabled
1
Inversion is enabled
The value written here configures the delay time of each of the
corresponding TSIG outputs, including the inversion control. For
example, bit 0 sets the delay for TSIG0 etc.
0
No delay
1
0.5 pixel clock delay
20 - 227
Revised 24/7/13
Iris-SDL Register Descriptions
20.185RSDS Bitmap Control register (GFXTCON_DIR_RBM_CTRL)
The RSDS Bitmap Control register is used to control the RSDS interface configuration (e.g. color component ordering, bit ordering, bits-per-colour and module enable/disable).
Figure 20-183: RSDS Bitmap Control register
Bit position
Bit name
[31:11]
Reserved
[10:8]
ColOrder
[7:6]
Reserved
5
BitOrder
20 - 228
Description
This bitfield configures the ordering of the incoming R,G and B
components:
000
RGB
001
BRG
010
GBR
011
RBG
100
GRB
101
BGR
110
Reserved
111
Reserved
Selects the ordering of the bits in the output:
0
Normal ordering (MSB 7 down to 0)
1
Inverted ordering (0 up to 7 MSB)
00
01
Bypass
RW
0
Table 20-145: RSDS Bitmap Control register bits
Fujitsu Semiconductor Europe GmbH
1
02
IfcType
RW
0
03
BitPerCol
RW
0
04
swapoddevenbit
RW
0
06
05
BitOrder
RW
0
Reserved
ColOrder
RW
0
0
07
10
0
Reserved
11
0
0
12
0
08
13
0
0
14
0
Reserved
0
09
15
16
0
0
17
22
0
0
23
0
18
24
0
0
25
0
19
26
0
20
27
0
0
28
0
0
29
0
21
30
0
Reserved
31
0
GFXTCON_DIR_RBM_CTRL
Iris-SDL Register Descriptions
4
3
[2:1]
0
swapoddevenbit
BitsPerCol
IfcType
ByPass
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
This bit is only available for ES2 versions of the chip (and higher). It
can be used to swap the odd and even bits required for RSDS
channel order inversion. For the ES1 version of this device, the
register is reserved.
0
No change
1
Swap bits 6 and 7, 4 and 5, 2 and 3, 0 and 1
This bit selects the number of bits used per colour:
0
6 bits per colour (2 LSBs are set to ‘0’)
1
8 bits per colour
Selects the interface protocol type:
00
TTL
01
RSDS
10
Reserved
11
Reserved
Enables/disables the RSDS Bitmap Control module bypass:
0
Disables bypass mode
1
Enables bypass mode, includes RGB data and TSIG
outputs
20 - 229
Revised 24/7/13
Iris-SDL Register Descriptions
20.186IO Module Internal Pad [0...11] Control register
(GFXTCON_DIR_PINx[0...11]_CTRL)
The IO Module Internal Pad 0 Control register is used to control the configuration of the internal IO pad
0 wired to the external pin. With the exception of the Mode, Boost and InOut bitfields, the fields of this
register are only effective if the TCON is not in bypass mode (DIR_RBM_CTRL.Bypass = 0).
Figure 20-184: IO Module Internal Pad [0...11] Control Register
01
0
Boost0
00
02
0
RW
0
03
04
Mode0
RW
1
Reserved
05
Polarity0
RW
0
Reserved
06
NPolarity0
RW
0
0
07
InOut0
RW
08
0
0
Reserved
0
09
0
10
11
0
Reserved
12
0
14
13
Delay0
RW
0
0
0
RW
Reserved
NDelay0
Reserved
15
16
0
ChanSel0
17
18
0
0
19
0
20
NChanSel0
RW
21
OptClkEn0
RW
0
0
22
23
0
NOptClkEn0
24
0
RW
25
0
0
Reserved
0
26
28
0
0
29
0
27
30
0
Reserved
31
0
GFXTCON_DIR_PIN0_CTRL
Table 20-146: IO Module Internal Pad [0...11] Control Register Bits
Bit position
Bit name
[31:23]
Reserved
22
NOptClkEn0
21
[20:19]
20 - 230
OptClkEn0
NChanSel0
Description
Configures the use of either the default clock or the optional
(delayed) sample clock for the respective IO N-pin
0
Use the default clock
1
Use the optional clock
Configures the use of either the default clock or the optional
(delayed) sample clock for the respective IO pin:
0
Use the default clock
1
Use the optional clock
The channel selection for the respective N pin of pad (i = 0)
in TTL mode:
00
Channel(i * 2 + 1)
01
Channel(i * 2)
10
Pixel clock
11
Constant zero
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[18:17]
ChanSel0
[16:15]
Reserved
14
NDelay0
13
Delay0
[12:8]
Reserved
7
InOut0
6
5
4
[3:2]
NPolarity0
Polarity0
Mode0
Revised 24/7/13
The channel selection for the respective pad (i = 0) in
RSDS/TTL mode:
00
In RSDS mode: Channel(i)
In TTL mode: Channel i * 2
01
In RSDS mode: Reserved
In TTL mode: INV (from the inversion control
function)
10
Pixel clock
11
Constant zero
Configures the delay of the respective N-pin:
0
No delay
1
Delay by half of the bit clock cycle (TTL mode
only!)
Configures the delay of the respective padcell:
0
No delay
1
Delay by half of the bit clock cycle (TTL mode
only)
Enables the input/output of the respective pin:
0
Input enabled
1
Output enabled
Configures the drive polarity of the respective N-pin::
0
Normal
In RSDS mode: no effect
1
Inverted
In RSDS mode: no effect
Configures the drive polarity of the respective padcell:
0
Normal
1
Inverted
Configures the drive mode of the respective padcell:
0
RSDS
1
TTL
Reserved
Fujitsu Semiconductor Europe GmbH
20 - 231
Revised 24/7/13
[1:0]
20 - 232
Iris-SDL Register Descriptions
Boost0
Configures the boost factor (drive current) for the
respective padcell. Note that bit 1 is ignored.
00
2mA
01
4mA
10
2mA
11
4mA
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.187Module Internal Pad 12 Control register
(GFXTCON_DIR_PIN12_CTRL)
The IO Module Internal Pad 12 Control register is used to control the configuration of the internal IO pads
12 wired to an external pin. With the exception of the Mode, Boost and InOut bitfields, the fields of this
register are only effective if the TCON is not in bypass mode (DIR_RBM_CTRL.Bypass = 0).
Figure 20-185: IO Module Internal Pad 12 Control register
01
0
Boost12
00
02
0
RW
0
03
04
Mode12
RW
1
Reserved
05
Polarity12
RW
0
Reserved
06
NPolarity12
RW
0
0
07
InOut12
RW
08
0
0
Reserved
0
09
0
10
11
0
Reserved
12
0
14
13
Delay12
RW
0
0
0
RW
Reserved
Reserved
NDelay12
15
16
0
ChanSel12
17
18
0
0
19
0
20
NChanSel12
RW
21
OptClkEn12
RW
0
0
22
NOptClkEn12
23
0
RW
24
0
0
0
Reserved
0
25
0
28
0
26
29
0
27
30
0
Reserved
31
0
GFXTCON_DIR_PIN12_CTRL
Table 20-147: IO Module Internal Pad 12 Control register bits
Bit position
Bit name
[31:23]
Reserved
22
NOptClkEn12
21
[20:19]
OptClkEn12
NChanSel12
Fujitsu Semiconductor Europe GmbH
Description
Configures the use of either the default clock or the optional
(delayed) sample clock for the respective IO N-pin
0
Use the default clock
1
Use the optional clock
Configures the use of either the default clock or the optional
(delayed) sample clock for the respective IO pin:
0
Use the default clock
1
Use the optional clock
The channel selection for the respective N pin of pad (i =
12) in TTL mode:
00
Constant zero
01
INV (from inversion control function)
10
Pixel clock
11
Constant zero
20 - 233
Revised 24/7/13
[18:17]
Iris-SDL Register Descriptions
ChanSel12
[16:15]
Reserved
14
NDelay12
13
Delay12
[12:8]
Reserved
7
InOut12
6
5
4
[3:2]
20 - 234
NPolarity12
Polarity12
Mode12
The channel selection for the respective pad (i = 12) in
RSDS/TTL mode:
00
In RSDS mode: Pixel clock
In TTL mode: Pixel clock
01
In RSDS mode: Channel(i - 1)
In TTL mode: Channel(i * 2 - 1)
10
In RSDS mode: Reserved
In TTL mode: INV (from inversion control
function)
11
Constant zero
Configures the delay of the respective N-pin:
0
No delay
1
Delay by half of the bit clock cycle (TTL mode
only!)
Configures the delay of the respective padcell:
0
No delay
1
Delay by half of the bit clock cycle (TTL mode
only)
Enables the input/output of the respective pin:
0
Input enabled
1
Output enabled
Configures the drive polarity of the respective N-pin::
0
Normal
In RSDS mode: no effect
1
Inverted
In RSDS mode: no effect
Configures the drive polarity of the respective padcell:
0
Normal
1
Inverted
Configures the drive mode of the respective padcell:
0
RSDS
1
TTL
Reserved
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
[1:0]
Boost12
Fujitsu Semiconductor Europe GmbH
Revised 24/7/13
Configures the boost factor (drive current) for the
respective padcell. Note that bit 1 is ignored.
00
2mA
01
4mA
10
2mA
11
4mA
20 - 235
Revised 24/7/13
Iris-SDL Register Descriptions
20.188Command Sequencer Command Input Buffer registers
(GFXCMD_HIF[0:63])
The 64 Command Sequencer Command Input Buffer registers consititute the FIFO storage for command instructions.
Figure 20-186: Command Sequencer Command Input Buffer registers
11
10
09
08
07
06
05
04
03
02
01
00
X
X
X
X
X
X
X
X
X
X
X
X
16
X
12
17
X
X
18
X
13
19
X
14
20
X
X
21
X
X
22
X
15
23
X
X
RW
CommandFIFO
24
X
X
25
X
28
X
26
29
X
X
30
X
27
31
X
GFXCMD_HIF[0:63]
Table 20-148: Command Sequencer Command Input Buffer registers bits
Bit position
Bit name
Description
[31:0]
CommandFIFO
Each of the 64 registers is used to store a command.
Reading always returns 0.
20 - 236
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.189Command Sequencer Status register (GFXCMD_Status)
The Command Sequencer status register provides read access to the status of various components of
the Command Sequencer.
Figure 20-187: Command Sequencer status register
03
02
01
00
0
0
0
0
09
0
04
10
0
05
11
0
0
12
0
0
13
0
06
14
0
0
15
0
07
16
0
1
17
0
0
R
Reserved
0
08
18
0
FIFOSpace
19
0
20
21
0
Reserved
22
0
24
R
0
23
25
FIFOFull
FIFOEmpty
R
0
0
26
FIFOWMState
R
0
0
27
28
Reserved
29
R
0
Reserved
30
Idle
Watchdog
R
1
0
31
Error
R
0
GFXCMD_Status
Table 20-149: Command Sequencer status register bits
Bit position
Bit name
Description
31
Error
A ‘1’ signals that execution of commands was stopped after
an illegal instruction was read:
30
Idle
A ‘1’ indicates that the Command Sequencer is in its idle
state.
29
Watchdog
A ‘1’ indicates that the watchdog counter has expired.
[28:27]
Reserved
26
FIFOWMState
A ‘1’ indicates that a watermark has been reached.
25
FIFOFull
A ‘1’ indicates that the Command FIFO is completely full.
24
FIFOEmpty
A ‘1’ indicates that the Command FIFO is completely empty.
[23:17]
Reserved
[16:0]
FIFOSpace
Fujitsu Semiconductor Europe GmbH
This bitfield indicates the available free space in the
command FIFO in entries.
The default value is 10000000 (80 hex, 128 decimal).
20 - 237
Revised 24/7/13
Iris-SDL Register Descriptions
20.190Command Sequencer Control register (GFXCMD_Control)
The Command Sequencer control register is used to clear the Command Sequencer FIFO (command/data buffer).
Figure 20-188: Command Sequencer control register
09
08
07
06
05
04
03
02
01
00
0
0
0
0
0
0
0
0
16
0
0
17
0
0
18
0
10
19
0
0
20
0
11
21
0
0
22
0
12
23
0
0
24
0
13
25
0
14
26
0
0
27
0
0
28
0
Reserved
0
W
0
15
29
0
Reserved
30
0
Clear
31
GFXCMD_Control
Table 20-150: Command Sequencer control register bits
Bit position
Bit name
Description
31
Clear
Write a ‘1’ to this bit to clear the Command Sequencer FIFO
(command/data buffer).
[30:0]
Reserved
20 - 238
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.191Command Sequencer Buffer Address register
(GFXCMD_BufferAddress)
The Command Sequencer Buffer Address register defines the base address of the Command FIFO
(command/data buffer) in memory.
Figure 20-189: Command Sequencer Buffer Address register
05
04
0
0
Reserved
Bit position
Bit name
Description
[31:2]
Addr
This bitfield holds the Command FIFO (command/data
buffer) base address (in the system memory space).
[30:0]
Reserved
Must be set to 0 (so that the address is 32-bit aligned)
20 - 239
0
RW
Table 20-151: Command Sequencer Buffer Address register bits
Fujitsu Semiconductor Europe GmbH
00
06
0
01
07
0
Reserved
08
0
0
09
0
02
10
0
0
11
0
03
12
0
0
13
17
0
14
18
0
0
19
0
0
20
0
15
21
0
16
22
0
0
23
0
0
24
Addr
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXCMD_BufferAddress
Revised 24/7/13
Iris-SDL Register Descriptions
20.192Command Sequencer Buffer Size register (GFXCMD_BufferSize)
The Command Sequencer Buffer Size register defines the size of the Command FIFO (command/data
buffer) in memory.
Figure 20-190: Command Sequencer Buffer Size register
RW
Reserved
Size
00
08
0
01
09
0
0
10
0
0
11
0
02
12
0
0
13
0
03
14
0
0
15
0
04
16
0
05
17
0
0
18
0
0
19
0
06
20
0
0
21
0
07
22
0
1
23
0
26
0
24
27
0
Reserved
28
0
25
29
0
0
30
0
0
31
0
GFXCMD_BufferSize
Table 20-152: Command Sequencer Buffer Size register bits
Bit position
Bit name
[31:16]
Reserved
[15:0]
Size
20 - 240
Description
Defines the size of the Command Sequencer FIFO
(command/data buffer) in DWORDs (32 bits)
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.193Command Sequencer Watermark Control register
(GFXCMD_WatermarkControl)
The Command Sequencer Watermark Control register configures the high and low thresholds of the
watermark control for the Command Sequencer.
Figure 20-191: Command Sequencer Watermark Control register
RW
RW
LowWM
00
08
0
01
09
0
0
10
0
0
11
0
02
12
0
0
13
0
03
14
0
0
15
0
04
16
0
05
17
0
0
18
0
1
19
0
06
20
0
0
21
1
07
22
1
0
23
0
24
HighWM
25
27
0
0
28
0
0
29
0
26
30
0
0
31
0
GFXCMD_WatermarkControl
Table 20-153: Command Sequencer Watermark Control register bits
Bit position
Bit name
Description
[31:16]
HighWM
Defines the high threshold value in buffer entries of the
watermark control of the Command Sequencer.
The default value is 1100000 (60 hex, 96 decimal)
[15:0]
LowWM
Defines the low threshold value in buffer entries of the
watermark control of the Command Sequencer.
The default value is 100000 (20 hex, 32 decimal)
Fujitsu Semiconductor Europe GmbH
20 - 241
Revised 24/7/13
Iris-SDL Register Descriptions
20.194HS_SPI Module Control Register (GFXSPIn_MCTRL)
The HS_SPI Module Control Register controls the HS_SPI module. It contains vital bits like the Module
Enable bit, the Command Sequencer Enable bit, and the Debug Enable bit. The software can enable/disable the module operation by using this register.
Figure 20-192: HS_SPI Module Control Register
read0
[7:5]
read0
4
MES
04
03
02
01
00
MES
CDSS
DEN
CSEN
MEN
RpWp
RpWp
RpWp
0
0
0
05
read0
Rp0
0
Rp
06
read0
Rp0
0
RpWp
07
read0
Rp0
0
0
08
read0
Rp0
0
0
09
read0
Rp0
0
12
read0
Rp0
0
10
13
read0
Rp0
0
read0
14
read0
Rp0
0
Rp0
15
read0
Rp0
0
0
16
read0
Rp0
0
11
17
read0
Rp0
0
read0
18
read0
Rp0
0
Rp0
19
read0
Rp0
0
0
20
read0
Rp0
0
21
22
read0
Rp0
0
[31:8]
read0
23
read0
Rp0
0
Bit name
Rp0
24
read0
Rp0
0
Bit position
0
25
read0
Rp0
0
27
read0
Rp0
0
26
28
read0
Rp0
0
read0
29
read0
Rp0
0
Rp0
30
read0
Rp0
0
0
31
read0
Rp0
0
GFXSPIn_MCTRL
Description
Module Enable Status (MES)
0: Module is completely disabled and it has entered the power saving
mode
1: Module is enabled
3
CDSS
Clock Division Source Select (CDSS)
When HS_SPI is in master mode, the internal clock divider can divide
either the AHB clock (i.e. iHCLK) or the peripheral clock (i.e. iPCLK).
The CDSS bit decides which clock is divided by the clock divider. This
field is not used in slave mode.
0: Clock divider divides the iHCLK
1: Clock divider divides the iPCLK
2
DEN
Debug Enable (DEN)
0: Debug mode is disabled
1: Debug mode is enabled
This bit takes effect only in direct mode of operation (i.e.
GFXSPIn_MCTRL:CSEN = 0), when HS_SPI is configured as a master
(i.e. GFXSPIn_DMCFG:MST = 1). Before programming this bit, the
software must ensure that the HS_SPI is working as a master in direct
mode of operation.
20 - 242
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
Bit position
Bit name
Description
1
CSEN
Command Sequencer Enable (CSEN)
0: Direct mode is enabled. Command sequencer is disabled
1: Command sequencer is enabled. Direct mode is disabled
Note: Refer to the device specific data sheet to check whether the
command sequencer mode is available in that particular device.
If command sequencer is not available in your device, the
CSEN bit is a read-only and its value is '0'.
0
MEN
Module Enable (MEN)
0: Module is disabled. HS_SPI module enters power saving mode. All
serial I/O signals are tri-stated by HS_SPI
1: Module is enabled
After configuring the HS_SPI, software must set this bit to '1', to enable
HS_SPI in operating mode.
When software resets this bit:
a) In direct mode: As a master, HS_SPI stops further SPI transfers after
the slave select is released (if it is already asserted). As a slave,
HS_SPI does not respond to any SPI transfers after the slave select is
released (if it is already asserted). After the slave select is released, it
internally enters a power saving mode, by gating the iHCLK and the
iPCLK clocks to some of its internal logic blocks.
b) In command sequencer mode: HS_SPI generates an unmapped
memory access fault interrupt, if any further AHB access to memory
mapped devices are received. It does not initiate any commands on
the serial interface. After the slave select has released, it internally
enters a power saving mode, by gating the iHCLK and the iPCLK
clocks to some of its internal logic blocks.
Fujitsu Semiconductor Europe GmbH
20 - 243
Revised 24/7/13
Iris-SDL Register Descriptions
20.195HS_SPI Peripheral Communication Configuration Register 0~3
(GFXSPIn_PCC0~3)
The HS_SPI Peripheral Communication Configuration Registers 0~3 control the attributes related to
the serial communication on slave select 0~3. The software must initialize these registers with the attributes that match the communication attributes of the serial peripheral that is to be interfaced on the
corresponding slave select line (0 ~ 3) of HS_SPI. While operating in master mode, each of the four
registers is used. While operating in slave mode, only the GFXSPIn_PCC0 register is used by HS_SPI.
Only GFXSPIn_PCC0 register is described here. Other registers (i.e. GFXSPIn_PCC1,
GFXSPIn_PCC2 and GFXSPIn_PCC3) have similar bit fields.
Figure 20-193: HS_SPI Peripheral Communication Configuration Register
08
07
06
05
04
03
02
01
00
read0
SDIR
SS2CD[1]
SS2CD[0]
SSPOL
RTM
ACES
CPOL
CPHA
Rp0
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
0
0
0
0
0
0
0
0
09
CDRS[0]
RpWp
0
0
10
CDRS[1]
12
CDRS[3]
RpWp
0
RpWp
13
CDRS[4]
RpWp
0
0
14
CDRS[5]
RpWp
0
11
15
CDRS[6]
RpWp
0
CDRS[2]
16
SAFESYNC
RpWp
1
RpWp
17
read0
Rp0
0
0
18
read0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
SAFESYNC
19
24
read0
Rp0
0
16
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
[23:17]
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:24]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_PCC0
Description
Safe Synchronisation for Peripheral 0 (SAFESYNC)
This bit is valid only when HS_SPI is configured as SPI master in
direct mode or in command sequencer mode.
0: Module operates normally. Pre-determined delay for safe
synchronisation of data is not added by HS_SPI during the
serial transfers
1: Module implements safe synchronisation of data while serial
communication with peripheral '0' is taking place
20 - 244
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
Bit position
Bit name
Description
[15:9]
CDRS[6:0]
Clock Division Ratio Select of Peripheral 0 (CDRS[6:0])
When HS_SPI is configured as SPI master in direct mode or in
command sequencer mode, this field decides the clock division
ratio of the internal clock divider. This field is not used when
HS_SPI is configured as SPI slave mode.
0: Clock divider is bypassed. SCLK is same as source clock,
selected by GFXSPIn_MCTRL:CDSS bit
1: Divide by 2
2: Divide by 4
3: Divide by 6
...
127: Divide by 254
In general, for a non-zero value of CDRS, the source clock
frequency (i.e. Fi) is divided by twice the CDRS value, to get the
derived clock frequency (i.e. Fo).
Fo = Fi/( 2 x CDRS )
The value of CDRS bit shall be chosen such that the resultant serial
clock frequency is not more than the frequency of the AHB clock.
8
read0
7
SDIR
Shift Direction of Peripheral 0 (SDIR)
This bit decides the bit transmission order within a field. SDIR bit
does not affect the position of the most significant bit and least
significant bit in the data registers. The read or write access to data
registers always have least significant bit in bit '0'.
0: Most significant bit is transmitted first
1: Least significant bit is transmitted first
[6:5]
SS2CD[1:0]
Slave-Select to Clock Delay of Peripheral 0 (SS2CD[1:0])
This bit is used only when HS_SPI is configured as SPI master in
direct mode or in command sequencer mode.
It defines a setup time for the slave device. By delaying the toggling
of SCLK, HS_SPI delays the data transmission (of slave) from the
chip select active edge by a multiple of SCLK cycles.
If GFXSPIn_PCC0~3: CPHA = 0, the delay between assertion of
slave select and first edge on the SCLK is given by:
( SS2CD + 0.5 ) number of clock periods of SCLK.
If GFXSPIn_PCC0~3: CPHA = 1, the delay between assertion of
slave select and first edge on the SCLK is given by:
( SS2CD ) number of clock periods of SCLK.
When the slave select becomes active, the slave has to prepare
data transfer within the delay time defined by SS2CD bits.
Fujitsu Semiconductor Europe GmbH
20 - 245
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
4
SSPOL
Slave Select Polarity of Peripheral 0 (SSPOL)
This bit is used to decide the polarity of the slave select (i.e. SSEL0)
signal.
0: SSEL0 is held high during default state. The signal is active
low
1: SSEL0 is held low during default state. The signal is active
high
3
RTM
Use Retimed Clock for Capturing the Data from Peripheral 0 (RTM)
This bit must be set to '1' if the serial device interfaced with HS_SPI
provides tight setup or hold margins to HS_SPI. This bit takes effect
only when HS_SPI is configured as SPI master in direct mode or in
command sequencer mode.
0: Do not use retimed clock for capturing the serial data
1: Use retimed clock for capturing the serial data
CPHA, CPOL, ACES, and RTM bits together decide the clocking
mode of HS_SPI serial interface.
2
ACES
Active Clock Edges are Same on Peripheral 0 (ACES)
This bit decides whether the active edges of the clock used for
launching of data and for capture of data are same, or otherwise.
This bit takes effect only when HS_SPI is configured as SPI master
in direct mode or in command sequencer mode.
0: Launching of data and capture of data is done on alternate (i.e.
opposite) edges of clock
1: Launching of data and capture of data is done on same edges
of clock
CPHA, CPOL, ACES, and RTM bits together decide the clocking
mode of HS_SPI serial interface.
1
CPOL
Clock Polarity of Peripheral 0 (CPOL)
0: SCLK is held low during its default state
1: SCLK is held high during its default state
CPHA, CPOL, ACES, and RTM bits together decide the clocking
mode of HS_SPI serial interface.
0
CPHA
Clock Phase of Peripheral 0 (CPHA)
0: Input data is sampled on odd numbered edges of serial clock
1: Input data is sampled on even numbered edges of serial clock
CPHA, CPOL, ACES, and RTM bits together decide the clocking
mode of HS_SPI serial interface.
20 - 246
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.196HS_SPI TX Interrupt Flag Register (GFXSPIn_TXF)
The HS_SPI TX Interrupt Flag Register indicates the status of the TX interrupt flags. These interrupt
flags are set in direct mode of operation only. Software can enable these interrupts and wait for their
assertion, or it can also use them in polling mode.
Figure 20-194: HS_SPI TX Interrupt Flag Register
[31:8]
read0
7
read0
6
TSSRS
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
TSSRS
TFMTS
TFLETS
TFUS
TFOS
TFES
TFFS
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp
Rp
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
23
read0
Rp0
0
Bit name
Rp0
24
read0
Rp0
0
Bit position
0
25
read0
Rp0
0
27
read0
Rp0
0
26
28
read0
Rp0
0
read0
29
read0
Rp0
0
Rp0
30
read0
Rp0
0
0
31
read0
Rp0
0
GFXSPIn_TXF
Description
Slave Select Released (TSSRS)
This interrupt flag indicates that the slave select line is released by the SPI
master.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TSSRE.
5
TFMTS
TX-FIFO Fill Level is More Than Threshold (TFMTS)
This interrupt flag is set with every AHB clock, if the TX-FIFO fill level is
more than the configured TX-FIFO threshold value.
i.e. GFXSPIn_DMSTATUS:TXFLEVEL is greater than
GFXSPIn_FIFOCFG:TXFTH.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFMTE.
4
TFLETS
TX-FIFO Fill Level is Less Than or Equal to Threshold (TFLETS)
This interrupt flag is set with every AHB clock, if the TX-FIFO fill level is
less than or equal to the configured TX-FIFO threshold value.
i.e. GFXSPIn_DMSTATUS:TXFLEVEL is less than or equal to
GFXSPIn_FIFOCFG:TXFTH.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFLETE.
Fujitsu Semiconductor Europe GmbH
20 - 247
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
3
TFUS
TX-FIFO Underrun (TFUS)
This interrupt flag indicates that the TX-FIFO is underrun.
The TX-FIFO underrun condition happens when TX-FIFO is read by the
SPI core while the TX-FIFO is empty. This condition may happen during
the slave mode of operation.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFUE.
2
TFOS
TX-FIFO Overrun (TFOS)
This interrupt flag indicates that the TX-FIFO is overrun.
The TX-FIFO overrun condition happens when GFXSPIn_TXFIFO0~15
register is written by the software while the TX-FIFO is full.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFOE.
1
TFES
TX-FIFO and Shift Register is Empty (TFES)
This interrupt flag is set with every AHB clock, if the TX-FIFO and the TX
shift register (in SPI core) are empty.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFEE.
0
TFFS
TX-FIFO Full (TFFS)
This interrupt flag is set with every AHB clock, if the TX-FIFO is full.
This interrupt flag triggers the TX interrupt signal, if it is enabled in
GFXSPIn_TXE:TFFE.
20 - 248
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.197HS_SPI TX Interrupt Enable Register (GFXSPIn_TXE)
The HS_SPI TX Interrupt Enable Register decides whether the interrupt flags in GFXSPIn_TXF register trigger the TX interrupt, or not.
The software must enable these flags to wait for the assertion of the TX interrupt signal.
Figure 20-195: HS_SPI TX Interrupt Enable Register
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
TSSRE
TFMTE
TFLETE
TFUE
TFOE
TFEE
TFFE
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
27
read0
Rp0
0
26
28
read0
Rp0
0
read0
29
read0
Rp0
0
Rp0
30
read0
Rp0
0
0
31
read0
Rp0
0
GFXSPIn_TXE
Bit position
Bit name
[31:8]
read0
7
read0
6
TSSRE
Description
Slave Select Released Interrupt Enable (TSSRE)
This bit decides whether the GFXSPIn_TXF:TSSRS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TSSRS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TSSRS interrupt flag triggers the TX interrupt
signal
5
TFMTE
TX-FIFO Fill Level is More Than Threshold Interrupt Enable (TFMTE)
This bit decides whether the GFXSPIn_TXF:TFMTS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFMTS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFMTS interrupt flag triggers the TX interrupt
signal
Fujitsu Semiconductor Europe GmbH
20 - 249
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
4
TFLETE
TX-FIFO Fill Level is Less Than or Equal To Threshold Interrupt Enable
(TFLETE)
This bit decides whether the GFXSPIn_TXF:TFLETS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFLETS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFLETS interrupt flag triggers the TX interrupt
signal
3
TFUE
TX-FIFO Underrun Interrupt Enable (TFUE)
This bit decides whether the GFXSPIn_TXF:TFUS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFUS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFUS interrupt flag triggers the TX interrupt signal
2
TFOE
TX-FIFO Overrun Interrupt Enable (TFOE)
This bit decides whether the GFXSPIn_TXF:TFOS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFOS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFOS interrupt flag triggers the TX interrupt signal
1
TFEE
TX-FIFO Empty Interrupt Enable (TFEE)
This bit decides whether the GFXSPIn_TXF:TFES interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFES interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFES interrupt flag triggers the TX interrupt signal
0
TFFE
TX-FIFO Full Interrupt Enable (TFFE)
This bit decides whether the GFXSPIn_TXF:TFFS interrupt flag is routed
on TX interrupt signal or not.
0: The GFXSPIn_TXF:TFFS interrupt flag does not trigger the TX
interrupt signal
1: The GFXSPIn_TXF:TFFS interrupt flag triggers the TX interrupt signal
20 - 250
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.198HS_SPI TX Interrupt Clear Register (GFXSPIn_TXC)
The HS_SPI TX Interrupt Clear Register is used to clear the interrupt flags set in the GFXSPIn_TXF
register. By writing ‘1’ to a bit in this register, the software can clear the corresponding flag in the
GFXSPIn_TXF register.
Figure 20-196: HS_SPI TX Interrupt Clear Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
TSSRC
TFMTC
TFLETC
TFUC
TFOC
TFEC
TFFC
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
TSSRC
19
24
read0
Rp0
0
6
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
7
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_TXC
Description
Slave Select Released Interrupt Clear (TSSRC)
This bit is used to clear the GFXSPIn_TXF:TSSRS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TSSRS interrupt flag
Read returns 0.
5
TFMTC
TX-FIFO Fill Level More Than Threshold Interrupt Clear (TFMTC)
This bit is used to clear the GFXSPIn_TXF:TFMTS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFMTS interrupt flag
Read returns 0.
4
TFLETC
TX-FIFO Fill Level Less Than or Equal to Threshold Interrupt Clear
(TFLETC)
This bit is used to clear the GFXSPIn_TXF:TFLETS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFLETS interrupt flag
Read returns 0.
Fujitsu Semiconductor Europe GmbH
20 - 251
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
3
TFUC
TX-FIFO Underrun Interrupt Clear (TFUC)
This bit is used to clear the GFXSPIn_TXF:TFUS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFUS interrupt flag
Read returns 0.
2
TFOC
TX-FIFO Overrun Interrupt Clear (TFOC)
This bit is used to clear the GFXSPIn_TXF:TFOS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFOS interrupt flag
Read returns 0.
1
TFEC
TX-FIFO Empty Interrupt Clear (TFEC)
This bit is used to clear the GFXSPIn_TXF:TFES interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFES interrupt flag
Read returns 0.
0
TFFC
TX-FIFO Full Interrupt Clear (TFFC)
This bit is used to clear the GFXSPIn_TXF:TFFS interrupt flag.
0: No effect
1: Clears the GFXSPIn_TXF:TFFS interrupt flag
Read returns 0.
20 - 252
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.199HS_SPI RX Interrupt Flag Register (GFXSPIn_RXF)
The HS_SPI RX Interrupt Flag register indicates the status of the RX interrupt flags. These interrupt
flags are set in direct mode of operation only. Software can enable these interrupts and wait for their
assertion, or it can also use them in polling mode.
Figure 20-197: HS_SPI RX Interrupt Flag Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
RSSRS
RFMTS
RFLETS
RFUS
RFOS
RFES
RFFS
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp
Rp
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
RSSRS
19
24
read0
Rp0
0
6
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
7
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_RXF
Description
Slave Select Released (RSSRS)
This interrupt flag indicates that the slave select line is released by
the SPI master.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RSSRE.
5
RFMTS
RX-FIFO Fill Level is More Than Threshold (RFMTS)
This interrupt flag is set with every AHB clock, if the RX-FIFO fill
level is more than the configured RX-FIFO threshold value.
i.e. GFXSPIn_DMSTATUS:RXFLEVEL is greater than
GFXSPIn_FIFOCFG:RXFT.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFMTE.
4
RFLETS
RX-FIFO Fill Level is Less Than or Equal to Threshold (RFLETS)
This interrupt flag is set with every AHB clock, if the RX-FIFO fill
level is less than or equal to the configured RX-FIFO threshold
value.
i.e. GFXSPIn_DMSTATUS:RXFLEVEL is less than or equal to
GFXSPIn_FIFOCFG:RXFTH.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFLETE.
Fujitsu Semiconductor Europe GmbH
20 - 253
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
3
RFUS
RX-FIFO Underrun (RFUS)
This interrupt flag indicates that the RX-FIFO is underrun.
The RX-FIFO Underrun condition happens when
GFXSPIn_RXFIFO0~15 register is read (by an AHB master other
than the DAP controller), while the RX-FIFO is empty.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFUE.
Note: This flag is not set when the DAP controller reads the
GFXSPIn_RXFIFO0~15 register while the RX-FIFO is
empty.
2
RFOS
RX-FIFO Overrun (RFOS)
This interrupt flag indicates that the RX-FIFO is overrun.
The RX-FIFO overrun condition happens when RX-FIFO is written
by the SPI-core while the RX-FIFO is full. This condition may
happen during the slave mode of operation.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFOE.
1
RFES
RX-FIFO Empty (RFES)
This interrupt flag is set with every AHB clock, if the RX-FIFO is
empty.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFEE.
0
RFFS
RX-FIFO Full (RFFS)
This interrupt flag is set with every AHB clock, if the RX-FIFO is full.
This interrupt flag triggers the RX interrupt signal, if it is enabled in
GFXSPIn_RXE:RFFE.
20 - 254
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.200HS_SPI RX Interrupt Enable Register (GFXSPIn_RXE)
The HS_SPI RX Interrupt Enable Register decides whether the interrupt flags in GFXSPIn_TXF register trigger the RX interrupt, or not. The software must enable these flags, if it wants to wait for the
assertion of the RX interrupt signal.
Figure 20-198: HS_SPI RX Interrupt Enable Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
RSSRE
RFMTE
RFLETE
RFUE
RFOE
RFEE
RFFE
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
RSSRE
19
24
read0
Rp0
0
6
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
7
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_RXE
Description
Slave Select Released Interrupt Enable (RSSRE)
This bit decides whether the GFXSPIn_RXF:RSSRS interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RSSRS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RSSRS interrupt flag triggers the RX
interrupt signal
5
RFMTE
RX-FIFO Fill Level is More Than Threshold Interrupt Enable
(RFMTE)
This bit decides whether the GFXSPIn_RXF:RFMTS interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFMTS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFMTS interrupt flag triggers the RX
interrupt signal
Fujitsu Semiconductor Europe GmbH
20 - 255
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
4
RFLETE
RX-FIFO Fill Level is Less Than or Equal To Threshold Interrupt
Enable (RFLETE)
This bit decides whether the GFXSPIn_RXF:RFLETS interrupt flag
is routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFLETS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFLETS interrupt flag triggers the RX
interrupt signal
3
RFUE
RX-FIFO Underrun Interrupt Enable (RFUE)
This bit decides whether the GFXSPIn_RXF:RFUS interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFUS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFUS interrupt flag triggers the RX
interrupt signal
2
RFOE
RX-FIFO Overrun Interrupt Enable (RFOE)
This bit decides whether the GFXSPIn_RXF:RFOS interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFOS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFOS interrupt flag triggers the RX
interrupt signal
1
RFEE
RX-FIFO Empty Interrupt Enable (RFEE)
This bit decides whether the GFXSPIn_RXF:RFES interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFES interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFES interrupt flag triggers the RX
interrupt signal
0
RFFE
RX-FIFO Full Interrupt Enable (RFFE)
This bit decides whether the GFXSPIn_RXF:RFFS interrupt flag is
routed on RX interrupt signal, or not.
0: The GFXSPIn_RXF:RFFS interrupt flag does not trigger the
RX interrupt signal
1: The GFXSPIn_RXF:RFFS interrupt flag triggers the RX
interrupt signal
20 - 256
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.201HS_SPI RX Interrupt Clear Register (GFXSPIn_RXC)
The HS_SPI RX Interrupt Clear Register is used to clear the Interrupt Flags set in the GFXSPIn_RXF
register. By writing a ‘1’ to a bit in this register, the software can clear the corresponding flag in the
GFXSPIn_RXF register.
Figure 20-199: HS_SPI RX Interrupt Clear Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
RSSRC
RFMTC
RFLETC
RFUC
RFOC
RFEC
RFFC
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
RSSRC
19
24
read0
Rp0
0
6
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
7
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_RXC
Description
Slave Select Released Interrupt Clear (RSSRC)
This bit is used to clear the GFXSPIn_RXF:RSSRS interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RSSRS interrupt flag
Read returns 0.
5
RFMTC
RX-FIFO Fill Level More Than Threshold Interrupt Clear (RFMTC)
This bit is used to clear the GFXSPIn_RXF:RFMTS interrupt flag.
0: No effect.
1: Clears the GFXSPIn_RXF:RFMTS interrupt flag
Read returns 0.
4
RFLETC
RX-FIFO Fill Level Less Than or Equal to Threshold Interrupt Clear
(RFLETC)
This bit is used to clear the GFXSPIn_RXF:RFLETS interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RFLETS interrupt flag
Read returns 0.
Fujitsu Semiconductor Europe GmbH
20 - 257
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
3
RFUC
RX-FIFO Underrun Interrupt Clear (RFUC)
This bit is used to clear the GFXSPIn_RXF:RFUS interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RFUS interrupt flag
Read returns 0.
2
RFOC
RX-FIFO Overrun Interrupt Clear (RFOC)
This bit is used to clear the GFXSPIn_RXF:RFOS interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RFOS interrupt flag
Read returns 0.
1
RFEC
RX-FIFO Empty Interrupt Clear (RFEC)
This bit is used to clear the GFXSPIn_RXF:RFES interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RFES interrupt flag
Read returns 0.
0
RFFC
RX-FIFO Full Interrupt Clear (RFFC)
This bit is used to clear the GFXSPIn_RXF:RFFS interrupt flag.
0: No effect
1: Clears the GFXSPIn_RXF:RFFS interrupt flag
Read returns 0.
20 - 258
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.202HS_SPI Fault Interrupt Flag Register (GFXSPIn_FAULTF)
The HS_SPI Fault Interrupt Flag Register indicates the status of the fault interrupt flags. The fault interrupt is non-maskable in HS_SPI. Once a fault occurs, the software needs to take a corrective action.
Figure 20-200: HS_SPI Fault Interrupt Flag Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
DRCBSFS
DWCBSFS
PVFS
WAFS
UMAFS
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
DRCBSFS
19
24
read0
Rp0
0
4
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
[7:5]
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_FAULTF
Description
DMA Read Channel Block Size Fault (DRCBSFS)
This interrupt flag indicates that the block size fault has occured on
DMA read channel.
The DMA Read Channel Block Size Fault occurs if the HS_SPI RX
block counter is 0 and there is a valid read access to the RX FIFO
(except from DAP controller).
This interrupt flag is non maskable in HS_SPI module.
3
DWCBSFS
DMA Write Channel Block Size Fault (DWCBSFS)
This interrupt flag indicates that the block size fault has occured on
DMA write channel.
The DMA Write Channel Block Size Fault occurs if the HS_SPI TX
block counter is 0 and there is a valid write access to the TX FIFO.
This interrupt flag is non maskable in HS_SPI module.
2
PVFS
Protection Violation Fault (PVFS)
This interrupt flag indicates that a PPU Protection Violation Fault
has occurred. This interrupt flag is non maskable in HS_SPI
module.
Fujitsu Semiconductor Europe GmbH
20 - 259
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
1
WAFS
Write Access Fault (WAFS)
This interrupt flag indicates that a write access fault has occurred.
This interrupt flag is non maskable in HS_SPI module.
This bit is set in command sequencer mode, if
GFXSPIn_CSCFG:SRAM = 0 and a AHB master performs a write
access to a memory location mapped onto the HS_SPI memory
area.
0
UMAFS
Unmapped Memory Access Fault (UMAFS)
This interrupt flag indicates that an Unmapped Memory Access
Fault has occurred. This interrupt flag is non maskable in HS_SPI
module.
This bit is set by HS_SPI when any of the following event occurs.
(a) In direct mode (i.e. GFXSPIn_MCTRL:CSEN = 0), an AHB
access within the 256 MB address range starting from the
HS_SPI base address is detected.
(b) In command sequencer mode
(i.e. GFXSPIn_MCTRL:CSEN = 1), an AHB access to a
memory device which is not enabled (in
GFXSPIn_CSCFG:SSEL0EN~SSEL3EN bits) is detected.
(c) In command sequencer mode
(i.e. GFXSPIn_MCTRL:CSEN = 1), an AHB access to a
memory location which is outside the memory range being
mapped onto the four slave selects (configured through the
GFXSPIn_CSCFG:MSEL field) is detected.
(d) While the module is disabled (i.e. GFXSPIn_MCTRL:MEN =
0), an AHB access to a mapped memory is detected.
20 - 260
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.203HS_SPI Fault Interrupt Clear Register (GFXSPIn_FAULTC)
The HS_SPI Fault Interrupt Clear Register is used to clear the interrupt flags set in the
GFXSPIn_FAULTF register. By writing ‘1’ to a bit in this register, the software can clear the corresponding flag in the GFXSPIn_FAULTF register.
Figure 20-201: HS_SPI Fault Interrupt Clear Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
DRCBSFC
DWCBSFC
PVFC
WAFC
UMAFC
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
Rp0Wp1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
DRCBSFC
19
24
read0
Rp0
0
4
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
[7:5]
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:8]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_FAULTC
Description
DMA Read Channel Block Size Fault Interrupt Clear (DRCBSFC)
This bit is used to clear the GFXSPIn_FAULTF:DRCBSFS interrupt
flag.
0: No effect
1: Clears the GFXSPIn_FAULTF:DRCBSFS interrupt flag
Read returns 0.
3
DWCBSFC
DMA Write Channel Block Size Fault Interrupt Clear (DWCBSFC)
This bit is used to clear the GFXSPIn_FAULTF:DWCBSFS interrupt
flag.
0: No effect
1: Clears the GFXSPIn_FAULTF:DWCBSFS interrupt flag
Read returns 0.
Fujitsu Semiconductor Europe GmbH
20 - 261
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
2
PVFC
Protection Violation Fault Interrupt Clear (PVFC)
This bit is used to clear the GFXSPIn_FAULTF:PVFS interrupt flag.
0: No effect
1: Clears the GFXSPIn_FAULTF:PVFS interrupt flag
Read returns 0.
1
WAFC
Write Access Fault Interrupt Clear (WAFC)
This bit is used to clear the GFXSPIn_FAULTF:WAFS interrupt flag.
0: No effect
1: Clears the GFXSPIn_FAULTF:WAFS interrupt flag
Read returns 0.
0
UMAFC
Unmapped Memory Access Fault Interrupt Clear (UMAFC)
This bit is used to clear the GFXSPIn_FAULTF:UMAFS interrupt
flag.
0: No effect
1: Clears the GFXSPIn_FAULTF:UMAFS interrupt flag
Read returns 0.
20 - 262
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.204HS_SPI Direct Mode Configuration Register (GFXSPIn_DMCFG)
The HS_SPI Direct Mode Configuration Register configures the following operational parameters of
HS_SPI:

The master or slave mode of operation

Software flow control or byte counter mode of slave select deassertion

Enabling the iMSTART input signal triggers for initiating a transfer
This register is used only when HS_SPI module is in direct mode
Figure 20-202: HS_SPI Direct Mode Configuration Register
GFXSPIn_DMCFG
read0
read0
MSTARTEN
SSDC
MST
Rp0
RpWp
RpWp
RpWp
00
Rp0
01
read0
02
Rp0
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
1
Bit position
Bit name
[7:3]
read0
2
MSTARTEN
Description
iMSTART Enable (MSTARTEN)
This bit is used only when HS_SPI acts as a master (i.e.
GFXSPIn_DMCFG:MST = 1) in direct mode (i.e.
GFXSPIn_MCTRL:CSEN = 0).
0: HS_SPI can initiate a transfer only when the software writes '1'
to GFXSPIn_DMSTART:START bit.
1: HS_SPI can initiate a transfer either when the software writes
'1' to GFXSPIn_DMSTART:START bit or when a positive edge
is detected on iMSTART input signal of HS_SPI
1
SSDC
Slave Select Deassertion Control (SSDC)
This bit is used only when HS_SPI acts as a master (i.e.
GFXSPIn_DMCFG:MST = 1).
The SSDC bit decides how the slave select is de asserted when
HS_SPI acts as a master.
0: Software flow control. GFXSPIn_DMSTOP:STOP bit is used to
decide when to deassert the slave select
1: Byte counter mode. GFXSPIn_DMBCC:BCC is used to decide
when to deassert the slave select
Fujitsu Semiconductor Europe GmbH
20 - 263
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
0
MST
Master Mode (MST)
0: HS_SPI is in slave mode
1: HS_SPI is in master mode
20 - 264
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.205HS_SPI Direct Mode DMA Enable Register
(GFXSPIn_DMDMAEN)
The HS_SPI direct mode DMA Enable Register can be used by the software, for enabling/disabling of
the DMA service requests generated by HS_SPI. This register is used only when HS_SPI module is in
direct mode.
Figure 20-203: HS_SPI Direct Mode DMA Enable Register
GFXSPIn_DMDMAEN
read0
read0
read0
TXDMAEN
RXDMAEN
Rp0
Rp0
RpWp
RpWp
00
Rp0
01
read0
02
Rp0
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:2]
read0
1
TXDMAEN
Description
TX DMA Enable (TXDMAEN)
0: TX DMA channel is disabled
1: TX DMA channel is enabled
0
RXDMAEN
RX DMA Enable (RXDMAEN)
0: RX DMA channel is disabled
1: RX DMA channel is enabled
Fujitsu Semiconductor Europe GmbH
20 - 265
Revised 24/7/13
Iris-SDL Register Descriptions
20.206HS_SPI Direct Mode Start Register (GFXSPIn_DMSTART)
The HS_SPI Direct Mode Start Register can be used by the software, for triggering the start of the serial transfer, if HS_SPI is working as a master. This bit can also be set by HS_SPI, if while
GFXSPIn_DMCFG:MSTARTEN bit is set and a positive transition is detected on the iMSTART input
signal. This register is used only when HS_SPI module is working as a master in direct mode.
Figure 20-204: HS_SPI Direct Mode Start Register
read0
read0
read0
Rp0
Rp0
Rp0
0
0
0
0
0
0
0
Bit position
Bit name
[7:1]
read0
0
START
RpWp1
read0
00
Rp0
01
read0
02
Rp0
03
read0
04
Rp0
05
read0
06
Rp0
07
START
GFXSPIn_DMSTART
0
Description
Start Transfer (START)
This field is used only when HS_SPI is master (i.e.
GFXSPIn_DMCFG:MST = 1).
0: No effect
1: Sets this bit
HS_SPI resets this bit to '0' when it starts the serial transfer. Writing
a '1' to this bit when the bit is already set to '1' has no effect on the
current serial transfer (if any).
HS_SPI sets this bit to '1' if it works as a master (i.e.
GFXSPIn_DMCFG:MST = 1) in direct mode (i.e.
GFXSPIn_MCTRL:CSEN = 0) and a positive edge is detected on
iMSTART input signal (while GFXSPIn_DMCFG:MSTARTEN is
set).
20 - 266
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.207HS_SPI Direct Mode Stop Register (GFXSPIn_DMSTOP)
The HS_SPI Direct Mode Stop Register can be used by the software, to stop the serial transfer, if software flow control mode is selected (i.e. if GFXSPIn_DMCFG:SSDC = 0). This register is used only
when HS_SPI module is working as a master, in direct mode. Once the STOP bit is set, the software
shall not clear this bit unless HS_SPI has stopped the current serial transfer (by de-asserting the slave
select output).
Figure 20-205: HS_SPI Direct Mode Stop Register
GFXSPIn_DMSTOP
read0
read0
read0
read0
STOP
Rp0
Rp0
Rp0
RpWp
00
Rp0
01
read0
02
Rp0
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:1]
read0
0
STOP
Description
Stop Bit (STOP)
This bit is used only when HS_SPI acts as a master (i.e.
GFXSPIn_DMCFG:MST = 1) and when GFXSPIn_DMCFG:SSDC
=.
This bit is used in software flow control mode for deassertion of the
slave select output.
0: HS_SPI does not de-assert the slave select output
1: Deassertion of slave select output by HS_SPI depends on
In TX-only mode: Stop is set and all contents in TX-FIFO are
transferred.
In RX-only mode: Stop is set and current filling of shift register is
complete.
In TX-and-RX mode: Stop is set and all contents in TX-FIFO are
transferred.
Fujitsu Semiconductor Europe GmbH
20 - 267
Revised 24/7/13
Iris-SDL Register Descriptions
20.208HS_SPI Direct Mode Peripheral Select Register
(GFXSPIn_DMPSEL)
The HS_SPI Direct Mode Peripheral Select Register can be used by the software for selection of one
of the four peripheral slave select lines for initiating the serial transfer in master mode. This register is
used only when HS_SPI module is in direct mode.
Figure 20-206: HS_SPI Direct Mode Peripheral Slave Select Register
GFXSPIn_DMPSEL
read0
read0
read0
PSEL[1]
PSEL[0]
Rp0
Rp0
RpWp
RpWp
00
Rp0
01
read0
02
Rp0
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:2]
read0
[1:0]
PSEL[1:0]
Description
Peripheral Select (PSEL[1:0])
This bit is used only when HS_SPI acts as a master (i.e.
GFXSPIn_DMCFG:MST = 1).
The PSEL bits decide which of the four slave select output lines in
SSEL3~0 is active for the current serial transfer.
00: Slave select 0
01: Slave select 1
10: Slave select 2
11: Slave select 3
20 - 268
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.209HS_SPI Direct Mode Transfer Protocol Register
(GFXSPIn_DMTRP)
The HS_SPI Direct Mode Transfer Protocol Register configures the transfer protocol of the serial transfer. This register is used only when HS_SPI module is in direct mode.
Figure 20-207: HS_SPI Direct Mode Transfer Protocol Register
GFXSPIn_DMTRP
read0
Rp0
RpWp
RpWp
RpWp
RpWp
TRP[0]
00
read0
TRP[1]
01
Rp0
TRP[2]
02
TRP[3]
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:4]
read0
[3:0]
TRP[3:0]
Description
Transfer Protocol (TRP[3:0])
Bits TRP[3:2] indicate the duplex configuration: Rx-only, Tx-only, or
both TX-and-RX.
Bits TRP[1:0] indicate whether the protocol used is: legacy, dual or
quad.
0000: TX-and-RX, in legacy mode
0100: RX only, in legacy mode
0101: RX only, in dual mode
0110: RX only, in quad mode
1000: TX only, in legacy mode
1001: TX only, in dual mode
1010: Tx only, in quad mode
All other combinations are reserved and they default to: TX-and-RX
in legacy mode.
Fujitsu Semiconductor Europe GmbH
20 - 269
Revised 24/7/13
Iris-SDL Register Descriptions
20.210HS_SPI Direct Mode Byte Count Control Register
(GFXSPIn_DMBCC)
The HS_SPI Direct Mode Byte Count Control Register configures the number of bytes that would be
transferred in the serial transfer, if byte counter mode of flow control is selected (i.e. if
GFXSPIn_DMCFG:SSDC = 1). This register is used only when HS_SPI module is configured to work
as a master, in direct mode of operation.
Figure 20-208: HS_SPI Direct Mode Byte Count Control Register
GFXSPIn_DMBCC
09
BCC[5]
BCC[4]
BCC[3]
BCC[2]
BCC[1]
BCC[0]
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
00
BCC[6]
01
RpWp
02
BCC[7]
03
RpWp
04
BCC[8]
05
RpWp
06
BCC[9]
07
RpWp
08
RpWp
BCC[10]
10
RpWp
BCC[11]
11
RpWp
BCC[12]
12
RpWp
BCC[13]
13
RpWp
BCC[14]
14
RpWp
BCC[15]
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit position
Bit name
Description
[15:0]
BCC[15:0]
Byte Count Control (BCC[15:0])
This field is used by HS_SPI only when HS_SPI acts as a master
(i.e. GFXSPIn_DMCFG:MST = 1) in direct mode and when
GFXSPIn_DMCFG:SSDC = 1.
BCC field must be programmed by the software with the number of
bytes to be transmitted or received or both.
The value in this field is loaded in a down counter at the start of a
transfer and the counter is decremented when a byte is serially
transferred. HS_SPI completes the transaction and deasserts the
slave select when this down counter reaches zero.
20 - 270
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.211HS_SPI Direct Mode Byte Count Status Register
(GFXSPIn_DMBCS)
The HS_SPI Direct Mode Byte Count Status Register is a read-only register, which can be used by the
software, to know how many bytes are yet to be transferred, in the current serial transfer. This register
is valid only when HS_SPI module is configured to work as a master, in direct mode of operation, and
if byte counter mode of flow control is selected (i.e. if GFXSPIn_DMCFG:SSDC = 1).
Figure 20-209: HS_SPI Direct Mode Byte Count Status Register
GFXSPIn_DMBCS
BCS[8]
BCS[7]
BCS[6]
BCS[5]
BCS[4]
BCS[3]
BCS[2]
BCS[1]
BCS[0]
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
00
Rp
01
BCS[9]
02
Rp
03
BCS[10]
04
Rp
05
BCS[11]
06
Rp
07
BCS[12]
08
Rp
09
BCS[13]
10
Rp
11
BCS[14]
12
Rp
13
BCS[15]
14
Rp
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit position
Bit name
Description
[15:0]
BCS[15:0]
Byte Count Status (BCS[15:0])
This read-only field is valid only when HS_SPI acts as a master (i.e.
GFXSPIn_DMCFG:MST = 1) in direct mode and when
GFXSPIn_DMCFG:SSDC = 1.
BCS field indicates the number of bytes in the current serial transfer,
that are not yet serially transmitted or received, or both.
Fujitsu Semiconductor Europe GmbH
20 - 271
Revised 24/7/13
Iris-SDL Register Descriptions
20.212HS_SPI Direct Mode Status Register (GFXSPIn_DMSTATUS)
The HS_SPI Direct Mode Status Register contains the status bits like whether the TX/RX path is active/idle
and the current fill-level of the TX/RX FIFOs.
This register is used only when HS_SPI module is configured in direct mode.
Figure 20-210: HS_SPI Direct Mode Status Register
08
07
06
05
04
03
02
01
00
RXFLEVEL[0]
read0
read0
read0
read0
read0
read0
TXACTIVE
RXACTIVE
Rp
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp
Rp
0
0
0
0
0
0
0
0
09
RXFLEVEL[1]
Rp
0
0
10
RXFLEVEL[2]
Rp
0
12
RXFLEVEL[4]
Rp
0
11
13
read0
Rp0
0
RXFLEVEL[3]
14
read0
Rp0
0
Rp
15
read0
0
0
16
TXFLEVEL[0]
Rp
Rp0
0
17
20
TXFLEVEL[4]
Rp
0
TXFLEVEL[1]
21
read0
Rp0
0
Rp
22
read0
Rp0
0
0
23
read0
Rp0
0
TXFLEVEL[4:0]
18
24
read0
Rp0
0
[20:16]
TXFLEVEL[2]
25
read0
Rp0
0
read0
Rp
26
read0
Rp0
0
[23:21]
0
27
read0
Rp0
0
read0
19
28
read0
Rp0
0
[31:24]
TXFLEVEL[3]
29
read0
Rp0
0
Bit name
Rp
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_DMSTATUS
Description
Current Fill Level of TX-FIFO (TXFLEVEL[4:0])
This field indicates the current fill level of the TX-FIFO.
[15:13]
read0
[12:8]
RXFLEVEL[4:0]
Current Fill Level of RX-FIFO (RXFLEVEL[4:0])
This field indicates the current fill level of the RX-FIFO.
[7:2]
read0
1
TXACTIVE
TX Active (TXACTIVE)
It indicates whether the transmission is in progress.
0: Serial transmission is not active
1: Serial transmission is active
0
RXACTIVE
RX Active (RXACTIVE)
It indicates whether the reception is in progress.
0: Serial reception is not active
1: Serial reception is active
20 - 272
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.213HS_SPI Transmit Bit Count Register (GFXSPIn_TXBITCNT)
After a serial transfer halts or ends, the HS_SPI Transmit Bit Count Register contains the number of
bits pending transmission from the TX Shift Register. This register is used only when HS_SPI module
is configured in direct mode.
Figure 20-211: HS_SPI Transmit Bit Count Register
GFXSPIn_TXBITCNT
TXBITCNT[4]
TXBITCNT[3]
TXBITCNT[2]
TXBITCNT[1]
TXBITCNT[0]
Rp
Rp
Rp
Rp
00
Rp
01
TXBITCNT[5]
02
Rp
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:6]
read0
[5:0]
TXBITCNT[5:0]
Description
TX Bit Count (TXBITCNT[5:0])
It indicates the number of bits pending transmission from the TX
Shift Register.
0: No bits are to be transmitted
1: 1-bit is to be transmitted
...
31: 31 bits are to be transmitted
32: 32 bits are to be transmitted
The GFXSPIn_TXBITCNT register is updated by HS_SPI when a
transfer halts (while HS_SPI is in master mode) or when a transfer
ends (i.e. slave select deassertion interrupt flag is de asserted).
Fujitsu Semiconductor Europe GmbH
20 - 273
Revised 24/7/13
Iris-SDL Register Descriptions
20.214HS_SPI Receive Bit Count Register (GFXSPIn_RXBITCNT)
After a serial transfer halts or ends, the HS_SPI Receive Bit Count Register contains the number of bits
received in the RX Shift Register, which are not pushed by HS_SPI into the RX FIFO. This register is
used only when HS_SPI module is configured in slave mode.
Figure 20-212: HS_SPI Receive Bit Count Register
GFXSPIn_RXBITCNT
RXBITCNT[4]
RXBITCNT[3]
RXBITCNT[2]
RXBITCNT[1]
RXBITCNT[0]
Rp
Rp
Rp
Rp
00
Rp
01
RXBITCNT[5]
02
Rp
03
read0
04
Rp0
05
read0
06
Rp0
07
0
0
0
0
0
0
0
0
Bit position
Bit name
[7:6]
read0
[5:0]
RXBITCNT[5:0]
Description
RX Bit Count (RXBITCNT[5:0])
It indicates the number of valid bits in the RX Shift Register.
0: No bits are valid
1: 1-bit is valid
...
31: 31 bits are valid
32: 32 bits are valid
'This register is used only in slave mode'.
In slave mode, when a transfer ends (i.e. slave select line is de
asserted), the GFXSPIn_RXSHIFT register is updated with the
assembled data and the GFXSPIn_RXBITCNT register is updated
with the number of bits valid in GFXSPIn_RXSHIFT register. The
software can read GFXSPIn_RXSHIFT and GFXSPIn_RXBITCNT
registers, to get RX data which is not yet pushed into the RX-FIFO.
20 - 274
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.215HS_SPI RX Shift Register (GFXSPIn_RXSHIFT)
The HS_SPI RX Shift Register is a read-only register. When a serial transfer in the direct mode halts or
ends, the data received by HS_SPI over the serial interface (which is not yet pushed into the RX-FIFO)
is stored in this register.
This register is used in slave mode only.
Figure 20-213: HS_SPI RX Shift Register
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
RXSHIFT[16]
RXSHIFT[15]
RXSHIFT[14]
RXSHIFT[13]
RXSHIFT[12]
RXSHIFT[11]
RXSHIFT[10]
RXSHIFT[9]
RXSHIFT[8]
RXSHIFT[7]
RXSHIFT[6]
RXSHIFT[5]
RXSHIFT[4]
RXSHIFT[3]
RXSHIFT[2]
RXSHIFT[1]
RXSHIFT[0]
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
RXSHIFT[20]
Rp
0
RXSHIFT[17]
21
RXSHIFT[21]
Rp
0
Rp
22
RXSHIFT[22]
Rp
0
0
23
RXSHIFT[23]
Rp
0
18
24
RXSHIFT[24]
Rp
0
RXSHIFT[18]
25
RXSHIFT[25]
Rp
0
Rp
26
RXSHIFT[26]
Rp
0
0
27
RXSHIFT[27]
Rp
0
19
28
RXSHIFT[28]
Rp
0
RXSHIFT[19]
29
RXSHIFT[29]
Rp
0
Rp
30
RXSHIFT[30]
Rp
0
0
31
RXSHIFT[31]
Rp
0
GFXSPIn_RXSHIFT
Bit position
Bit name
Description
[31:0]
RXSHIFT[31:0]
RX Shift Register (RXSHIFT[31:0])
'This register is used only in slave mode'.
In slave mode, when a transfer ends (i.e. slave select line is de
asserted), the GFXSPIn_RXSHIFT register is updated with the
assembled data and the GFXSPIn_RXBITCNT register is updated
with the number of bits valid in GFXSPIn_RXSHIFT register. The
software can read GFXSPIn_RXSHIFT and GFXSPIn_RXBITCNT
registers, to get RX data which is not yet pushed into the RX-FIFO.
Fujitsu Semiconductor Europe GmbH
20 - 275
Revised 24/7/13
Iris-SDL Register Descriptions
20.216HS_SPI TX-FIFO Registers (GFXSPIn_TXFIFO0~15)
The HS_SPI TX-FIFO Registers are used to push the data into the TX-FIFO. There are 16 such registers, all consecutively placed in the register map. Each of these 16 registers is identical in function. This
is because AHB protocol does not support burst transfers to same address. Only one register (i.e.
GFXSPIn_TXFIFO0) is explained here. Only 32-bit accesses are allowed to these registers. An 8-bit
or a 16-bit access to these registers trigger a protection violation fault. A write access to these registers
by the software pushes 33 bits into the TX-FIFO. The 33rd bit (i.e. the CTRL bit) is written with the value
in the GFXSPIn_FIFOCFG:TXCTRL bit.
Figure 20-214: HS_SPI TX-FIFO Register 0
07
06
05
04
03
02
01
00
TXDATA[6]
TXDATA[5]
TXDATA[4]
TXDATA[3]
TXDATA[2]
TXDATA[1]
TXDATA[0]
Rp0Wp
Rp0Wp
Rp0Wp
Rp0Wp
Rp0Wp
Rp0Wp
Rp0Wp
0
0
0
0
0
0
0
12
TXDATA[12]
Rp0Wp
0
08
13
TXDATA[13]
Rp0Wp
0
TXDATA[7]
14
TXDATA[14]
Rp0Wp
0
TXDATA[8]
15
TXDATA[15]
Rp0Wp
0
Rp0Wp
16
TXDATA[16]
Rp0Wp
0
Rp0Wp
17
TXDATA[17]
Rp0Wp
0
0
18
TXDATA[18]
Rp0Wp
0
0
19
TXDATA[19]
Rp0Wp
0
09
20
TXDATA[20]
Rp0Wp
0
TXDATA[9]
21
TXDATA[21]
Rp0Wp
0
Rp0Wp
22
TXDATA[22]
Rp0Wp
0
0
23
TXDATA[23]
Rp0Wp
0
10
24
TXDATA[24]
Rp0Wp
0
TXDATA[10]
25
TXDATA[25]
Rp0Wp
0
Rp0Wp
26
TXDATA[26]
Rp0Wp
0
0
27
TXDATA[27]
Rp0Wp
0
11
28
TXDATA[28]
Rp0Wp
0
TXDATA[11]
29
TXDATA[29]
Rp0Wp
0
Rp0Wp
30
TXDATA[30]
Rp0Wp
0
0
31
TXDATA[31]
Rp0Wp
0
GFXSPIn_TXFIFO0
Bit position
Bit name
Description
[31:0]
TXDATA[31:0]
TX-FIFO Register 0 (TXDATA[31:0])
Writing to this 32-bit register writes the data into the next location of
TX-FIFO and increments the TX-FIFO write pointer.
The 33rd bit (TXCTRL bit) of TX-FIFO word is written with the value
in GFXSPIn_FIFOCFG:TXCTRL field.
Irrespective of configured width of TX-FIFO, only 32-bit access to
this register is allowed. When the configured TX-FIFO width is less
than 32 bits, the unused most significant bits from the FIFO locations
are not transmitted by HS_SPI. e.g. if configured FIFO width is 8
bits, then only the bits TXDATA[7:0] are transmitted by HS_SPI and
the bits TXDATA[31:08] are unused. The software must not write any
valid data to be transmitted in those unused most significant bits.
A write access to this register while the TX-FIFO is full, pushes the
new data into the TX-FIFO and triggers a TX-FIFO overrun event.
When TX-FIFO overrun condition occurs, the integrity of the data
transmitted over the serial lines is not guaranteed. Before writing to
this register, the software must ensure that the TX-FIFO is not full, to
avoid an overrun.
20 - 276
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.217HS_SPI RX-FIFO Registers (GFXSPIn_RXFIFO0~15)
The HS_SPI RX-FIFO Registers are used to pop the data out of the RX-FIFO. There are 16 such registers, all consecutively placed in the register map. Each of these 16 registers is identical in function.
This is because AHB protocol does not support burst transfers to same address. Only one register (i.e.
GFXSPIn_RXFIFO0) is explained here.
Only 32-bit read accesses are allowed to these registers. An 8-bit or a 16-bit access to these registers
trigger a protection violation fault. By reading these register locations, the software can pop the data
out of the RX-FIFO.
Figure 20-215: HS_SPI RX-FIFO Register 0n
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
RXDATA[31]
RXDATA[30]
RXDATA[29]
RXDATA[28]
RXDATA[27]
RXDATA[26]
RXDATA[25]
RXDATA[24]
RXDATA[23]
RXDATA[22]
RXDATA[21]
RXDATA[20]
RXDATA[19]
RXDATA[18]
RXDATA[17]
RXDATA[16]
RXDATA[15]
RXDATA[14]
RXDATA[13]
RXDATA[12]
RXDATA[11]
RXDATA[10]
RXDATA[9]
RXDATA[8]
RXDATA[7]
RXDATA[6]
RXDATA[5]
RXDATA[4]
RXDATA[3]
RXDATA[2]
RXDATA[1]
RXDATA[0]
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GFXSPIn_RXFIFO0
Fujitsu Semiconductor Europe GmbH
20 - 277
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
[31:0]
RXDATA[31:0]
RX-FIFO Register 0 (RXDATA[31:0])
Reading this register returns a word of data from the RX-FIFO
location pointed by the RX-FIFO read pointer. After a read access to
this register, the RX-FIFO Read pointer is incremented provided that
the read cycle was initiated by the AHB master other than the
Debug Access Port (DAP) controller. If the DAP controller reads this
register, the RX-FIFO read pointer is not incremented.
A read access by a non-DAP AHB master to this register also has a
side effect of updating the RX-FIFO read pointer. Therefore,
non-DAP access in non-privileged mode can only be done with full
access rights (i.e. When iPPU_ACCESS is '1'), else Protection
Violation Fault is trigerred.
Irrespective of configured width of RX-FIFO, only 32-bit read access
to this register is allowed. When the configured FIFO width is less
than 32 bits, the unused most significant bits from the FIFO
locations contain invalid data. e.g. If configured FIFO width is 8 bits,
then only the bits RXDATA[7:0] are valid and the bits
RXDATA[31:08] return logic 0. The software must not use any data
from the unused most significant bits.
A read access to this register while the RX-FIFO is empty pops
invalid data out of the RX-FIFO. A RX-FIFO Underrun interrupt
(GFXSPIn_RXF:RFUS) event is triggered if the read cycle was
initiated by the AHB master other than the DAP controller. If the
DAP controller reads this register while the RX-FIFO is empty, the
GFXSPIn_RXF:RFUS flag is not set.
20 - 278
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.218HS_SPI FIFO Configuration Register (GFXSPIn_FIFOCFG)
The HS_SPI FIFO Configuration Register configures the operation of the TX-FIFO and the RX-FIFO.
The software can configure the FIFO threshold levels and the FIFO width.
The software can also flush the FIFOs using the TXFLSH and RXFLSH bits in this register.
Figure 20-216: HS_SPI FIFO Configuration Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
TXFLSH
RXFLSH
TXCTRL
FWIDTH[1]
FWIDTH[0]
TXFTH[3]
TXFTH[2]
TXFTH[1]
TXFTH[0]
RXFTH[3]
RXFTH[2]
RXFTH[1]
RXFTH[0]
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0Wp1
Rp0Wp1
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
TXFLSH
19
24
read0
Rp0
0
12
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
[15:13]
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:16]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_FIFOCFG
Description
TX-FIFO Flush (TXFLSH)
This register can be used by the software to flush the TX-FIFO.
0: No effect
1: Flushes the TX-FIFO
Read returns a 0.
11
RXFLSH
RX-FIFO Flush (RXFLSH)
This register can be used by the software to flush the RX-FIFO.
0: No effect
1: Flushes the RX-FIFO
Read returns a 0.
Fujitsu Semiconductor Europe GmbH
20 - 279
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
10
TXCTRL
TXCTRL bit to be written to TX-FIFO (TXCTRL)
When a write to GFXSPIn_TXFIFO0~15 register happens, 33rd bit
(TXCTRL bit) in TX-FIFO word takes this value.
The GFXSPIn_FIFOCFG:TXCTRL should be set by the software
only when the GFXSPIn_DMTRP:TRP field is programmed in any
one of the following modes:
a) TX only, in dual mode
b) TX only, in quad mode
If the GFXSPIn_DMTRP:TRP field is programmed in any mode
other than the two modes mentioned above, then the TXCTRL bit
shall be programmed to '0' by the software.
Before writing to the GFXSPIn_TXFIFO0~15 register, the software
must update this bit, depending on whether it wants the TXCTRL bit
in the next location in TX-FIFO to be set or reset.
[9:8]
FWIDTH[1:0]
FIFO Width (FWIDTH[1:0])
This register field indicates the FIFO Width. Depending on the
configured width of the FIFO, the usable size of the shift register in
the SPI core also changes.
00: TX-FIFO, RX-FIFO, and shift register is 8-bit wide
01: TX-FIFO, RX-FIFO, and shift register is 16-bit wide
10: TX-FIFO, RX-FIFO, and shift register is 24-bit wide
11: TX-FIFO, RX-FIFO, and shift register is 32-bit wide
[7:4]
TXFTH[3:0]
TX-FIFO Threshold Level (TXFTH[3:0])
Software must program this field with the threshold level of the
TX-FIFO.
[3:0]
RXFTH[3:0]
RX-FIFO Threshold Level (RXFTH[3:0])
Software must program this field with the threshold level of the
RX-FIFO.
20 - 280
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.219HS_SPI Command Sequencer Configuration Register
(GFXSPIn_CSCFG)
The HS_SPI Command Sequencer Configuration Register configures the command sequencer in
HS_SPI module.
This register must be programmed by the software before enabling the command sequencer mode. Attributes like transfer protocol, memory write enable/disable and size of memory device interfaced with
HS_SPI can be configured in this register.
Figure 20-217: HS_SPI Command Sequencer Configuration Register
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
SSEL2EN
SSEL1EN
SSEL0EN
read0
read0
read0
read0
read0
MBM[1]
MBM[0]
SRAM
RpWp
RpWp
RpWp
Rp0
Rp0
Rp0
Rp0
Rp0
RpWp
RpWp
RpWp
0
0
0
0
0
0
0
0
0
0
0
13
read0
Rp0
0
SSEL3EN
14
read0
Rp0
0
Rp0
15
read0
Rp0
0
RpWp
16
MSEL[0]
RpWp
0
0
17
MSEL[1]
RpWp
0
0
18
MSEL[2]
21
read0
Rp0
0
RpWp
22
read0
Rp0
0
0
23
read0
Rp0
0
MSEL[3:0]
19
24
read0
Rp0
0
[19:16]
20
25
read0
Rp0
0
read0
read0
26
read0
Rp0
0
[23:20]
MSEL[3]
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:24]
RpWp
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_CSCFG
Description
Memory Device Selection bits (MSEL[3:0])
This field indicates the range of the AHB address space associated
with each slave select line. It also indicates the size of each
memory banks in the selected device.
This field is used by command sequencer for two things:
(a) To select which of the four slave select output lines is to be
asserted for the memory mapped serial transfer and
(b) To select the size of each memory bank in the selected
memory device.
For more details see ‘command Sequencer Mode’.
[15:12]
read0
11
SSEL3EN
Slave Select 3 Enable (SSEL3EN)
0: Any access which fall in the memory range mapped on slave
select 3 cause an unmapped memory access fault
1: Access to the serial memory device mapped on slave select 3
is enabled
Fujitsu Semiconductor Europe GmbH
20 - 281
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
10
SSEL2EN
Slave Select 2 Enable (SSEL2EN)
0: Any access which fall in the memory range mapped on slave
select 2 cause an unmapped memory access fault
1: Access to the serial memory device mapped on slave select 2
is enabled
9
SSEL1EN
Slave Select 1 Enable (SSEL1EN)
0: Any access which fall in the memory range mapped on slave
select 1 cause an unmapped memory access fault
1: Access to the serial memory device mapped on slave select 1
is enabled
8
SSEL0EN
Slave Select 0 Enable (SSEL0EN)
0: Any access which fall in the memory range mapped on slave
select 0 cause an unmapped memory access fault
1: Access to the serial memory device mapped on slave select 0
is enabled
[7:3]
read0
[2:1]
MBM[1:0]
Multi Bit mode (MBM[1:0])
00: Memory devices access through the command sequencer
use the legacy SPI protocol. Read data is sampled on
SDATA[0]. Memory instruction, address, and other control
information is transmitted on SDATA[1]. Output enables of
other serial data lines are de-asserted
01: Memory devices access through the command sequencer
use the half-duplex Dual-bit SPI protocol. Read data is
sampled on SDATA[1:0]. Memory instruction, address, and
other control information is transmitted on SDATA[1:0]
10: Memory devices access through the command sequencer
use the quad-bit SPI protocol. Read data is sampled on
SDATA[3:0]. Memory instruction, address and other control
information is transmitted on SDATA[3:0]
11: Reserved
0
SRAM
Serial SRAM or Serial Flash Memory Type Select (SRAM)
This bit should be set only if serial SRAM devices are memory
mapped through HS_SPI.
0: Serial Flash memory devices are connected. Writes are
disabled
1: Serial SRAM memory devices are connected. Writes are
enabled
20 - 282
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Iris-SDL Register Descriptions
Revised 24/7/13
20.220HS_SPI Command Sequencer Idle Time Register
(GFXSPIn_CSITIME)
The HS_SPI Command Sequencer Idle Time Register configures the idle timeout period of command
sequencer in the HS_SPI module. The software must program this timeout value before enabling the
command sequencer mode.
Figure 20-218: HS_SPI Command Sequencer Idle Time Register
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
read0
ITIME[15]
ITIME[14]
ITIME[13]
ITIME[12]
ITIME[11]
ITIME[10]
ITIME[9]
ITIME[8]
ITIME[7]
ITIME[6]
ITIME[5]
ITIME[4]
ITIME[3]
ITIME[2]
ITIME[1]
ITIME[0]
Rp0
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
RpWp
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
17
read0
Rp0
0
0
18
read0
21
read0
Rp0
0
Rp0
22
read0
Rp0
0
0
23
read0
Rp0
0
19
24
read0
Rp0
0
20
25
read0
Rp0
0
ITIME[15:0]
read0
26
read0
Rp0
0
[15:0]
read0
27
read0
Rp0
0
read0
Rp0
28
read0
Rp0
0
[31:16]
Rp0
29
read0
Rp0
0
Bit name
0
30
read0
Rp0
0
Bit position
0
31
read0
Rp0
0
GFXSPIn_CSITIME
Description
Idle Time (ITIME[15:0])
This register is used by HS_SPI only in command sequencer mode
(i.e. GFXSPIn_MCTRL:CSEN = 1).
Once HS_SPI completes the required number of memory read or
write access on the serial interface, it keeps the slave select line
asserted. If no more access to the mapped serial memory device is
detected within the idle timeout period, then HS_SPI deasserts the
slave select line. This gives better performance, when the serial
memory access are of same type (i.e. if all are read access or all
are write access), the accessed locations are continuous and the
access occur within the predefined idle timeout interval. The idle
timeout interval is in terms of the AHB clock period.
Fujitsu Semiconductor Europe GmbH
20 - 283
Revised 24/7/13
Iris-SDL Register Descriptions
20.221HS_SPI Command Sequencer Address Extension Register
(GFXSPIn_CSAEXT)
The HS_SPI Command Sequencer Address Extension Register is used to extend the usable size of
memory mapped with the command sequencer.
The software must program this register if the address extension feature, to virtually access a serial
memory of upto 16 GB is required. If address extension is not to be used, the software must reset all
bits in this register to ‘0’.
Figure 20-219: HS_SPI Command Sequencer Address Extension Register
10
09
08
07
06
05
04
03
02
01
00
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
read0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
0
0
0
0
0
0
0
0
0
0
12
read0
Rp0
0
Rp0
13
AEXT[0]
RpWp
0
0
14
AEXT[1]
RpWp
0
11
15
AEXT[2]
RpWp
0
read0
16
AEXT[3]
RpWp
0
Rp0
17
AEXT[4]
RpWp
0
0
18
AEXT[5]
21
AEXT[8]
RpWp
0
RpWp
22
AEXT[9]
RpWp
0
0
23
RpWp
0
19
24
AEXT[11]
AEXT[10]
RpWp
0
20
25
AEXT[12]
RpWp
0
AEXT[6]
26
AEXT[13]
RpWp
0
AEXT[7]
27
AEXT[14]
RpWp
0
RpWp
28
AEXT[15]
RpWp
0
RpWp
29
AEXT[16]
RpWp
0
0
30
AEXT[17]
RpWp
0
0
31
AEXT[18]
RpWp
0
GFXSPIn_CSAEXT
Bit position
Bit name
Description
[31:13]
AEXT[18:0]
Address Extension Bits (AEXT[18:0])
This register is used by HS_SPI only in command sequencer mode
(i.e. GFXSPIn_MCTRL:CSEN = 1).
The GFXSPIn_CSAEXT register contains the 19 most significant
bits [31:13] of the memory address which is generated by the
command sequencer. The memory address generated by HS_SPI
on each slave select (while in command sequencer mode) is a
concatenation of the appropriate number of bits from the
GFXSPIn_CSAEXT register and from the AHB address bus. For
more details refer to ‘Command Sequencer Mode’.
If address extension is not to be used, the software should reset this
field to 0x0000000.
[12:0]
20 - 284
read0
Fujitsu Semiconductor Europe GmbH
Iris-SDL Register Descriptions
Revised 24/7/13
20.222HS_SPI Read Command Sequence Data/Control Register 0~7
(GFXSPIn_RDCSDC0~7)
The HS_SPI Read Command Sequence Data/Control Register 0~7 are a part of the list of eight Data/Control registers which configure the phases of the serial transaction generated by the command
sequencer for memory read operations. These registers are used only in command sequencer mode.
Only the GFXSPIn_RDCSDC0 register is explained here. Other registers have similar fields.
Figure 20-220: HS_SPI Read Command Sequence Data/Control Register 0
GFXSPIn_RDCSDC0
RDCSDATA[0]
read0
read0
read0
read0
read0
read0
read0
DEC
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
RpWp
00
RpWp
01
RDCSDATA[1]
02
RpWp
03
RDCSDATA[2]
04
RpWp
05
RDCSDATA[3]
06
RpWp
07
RDCSDATA[4]
08
RpWp
09
RDCSDATA[5]
10
RpWp
11
RDCSDATA[6]
12
RpWp
13
RDCSDATA[7]
14
RpWp
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Fujitsu Semiconductor Europe GmbH
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Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
[15:8]
RDCSDATA[7:0]
Command Sequencer Data or Control Byte for Memory-Read
transactions (RDCSDATA[7:0])
0:
When GFXSPIn_RDCSDC0:DEC bit is '0', the
RDCSDATA field contains the 8-bit data to be transmitted
on the serial interface
1:
When GFXSPIn_RDCSDC0:DEC bit is '1', the
RDCSDATA[2:0] field is decoded as follows
000: RDCSDATA[2:0] = 000: Transmit address bits [07:00] of
the serial memory address
001: RDCSDATA[2:0] = 001: Transmit address bits [15:08] of
the serial memory ad7dress
010: RDCSDATA[2:0] = 010: Transmit address bits [23:16] of
the serial memory address
011: RDCSDATA[2:0] = 011: Transmit address bits [31:24] of the
serial memory address
100: RDCSDATA[2:0] = 100: High-Z byte (i.e. SDATA[3:0]
signals are tri-stated for 1 byte time
101: RDCSDATA[2:0] = 101: High-Z nibble (i.e. Transmission of
RDCSDATA[7:4] is followed by tri-stating of SDATA output
for 1 nibble time
111: RDCSDATA[2:0] = 111: End of list
All other values of RDCSDATA[2:0] are reserved and must not be
used.
[7:1]
read0
0
DEC
Decode (DEC)
0: Transmit the GFXSPIn_RDCSDC0:RDCSDATA as it is
1: Decode the GFXSPIn_RDCSDC0:RDCSDATA[2:0] to decide
the further action
20 - 286
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Iris-SDL Register Descriptions
Revised 24/7/13
20.223HS_SPI Write Command Sequence Data/Control Register 0~7
(GFXSPIn_WRCSDC0~7)
The HS_SPI Write Command Sequence Data/Control Register 0~7 are a part of the list of eight Data/Control registers which configure the phases of the serial transaction generated by the command sequencer for memory write operations. These registers are used only in command sequencer mode.
Only the GFXSPIn_WRCSDC0 register is explained here. Other registers have similar fields.
Figure 20-221: HS_SPI Write Command Sequence Data/Control Register 0
GFXSPIn_WRCSDC0
WRCSDATA[0]
read0
read0
read0
read0
read0
read0
read0
DEC
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
Rp0
RpWp
00
RpWp
01
WRCSDATA[1]
02
RpWp
03
WRCSDATA[2]
04
RpWp
05
WRCSDATA[3]
06
RpWp
07
WRCSDATA[4]
08
RpWp
09
WRCSDATA[5]
10
RpWp
11
WRCSDATA[6]
12
RpWp
13
WRCSDATA[7]
14
RpWp
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Fujitsu Semiconductor Europe GmbH
20 - 287
Revised 24/7/13
Iris-SDL Register Descriptions
Bit position
Bit name
Description
[15:8]
WRCSDATA[7:0]
Command Sequencer Data or Control Byte for memory-write
transactions (WRCSDATA[7:0])
0:
When GFXSPIn_WRCSDC0:DEC bit is '0', the
WRCSDATA field contains the 8-bit data to be transmitted
on the serial interface
1:
When GFXSPIn_WRCSDC0:DEC bit is '1', the
WRCSDATA[2:0] field is decoded as follows
000: WRCSDATA[2:0] = 000: Transmit address bits [07:00] of
the serial memory address
001: WRCSDATA[2:0] = 001: Transmit address bits [15:08] of
the serial memory address
010: WRCSDATA[2:0] = 010: Transmit address bits [23:16] of
the serial memory address
011: WRCSDATA[2:0] = 011: Transmit address bits [31:24] of
the serial memory address
100: WRCSDATA[2:0] = 100: High-Z byte (i.e. SDATA[3:0]
signals are tri-stated for 1 byte time
101: WRCSDATA[2:0] = 101: High-Z nibble (i.e. transmission of
WRCSDATA[7:4] is followed by tri-stating of SDATA output
for 1 nibble time
111: WRCSDATA[2:0] = 111: End of list
All other values of WRCSDATA[2:0] are reserved and must not be
used.
[7:1]
read0
0
DEC
Decode (DEC)
0: Transmit the GFXSPIn_WRCSDC0:WRCSDATA as it is
1: Decode the GFXSPIn_WRCSDC0:WRCSDATA[2:0] to
decide the further action
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Iris-SDL Register Descriptions
Revised 24/7/13
20.224HS_SPI Module ID Register (GFXSPIn_MID)
This is a read-only register with a unique module identification number which identifies the version of
the HS_SPI module used in the MCU.
Refer to the device data sheet for the module identification number of the HS_SPI module in your device.
Figure 20-222: HS_SPI Module ID Register
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
MID[18]
MID[17]
MID[16]
MID[15]
MID[14]
MID[13]
MID[12]
MID[11]
MID[10]
MID[9]
MID[8]
MID[7]
MID[6]
MID[5]
MID[4]
MID[3]
MID[2]
MID[1]
MID[0]
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
Rp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
21
MID[21]
Rp
0
Rp
22
MID[22]
Rp
0
0
23
MID[23]
Rp
0
19
24
MID[24]
Rp
0
20
25
MID[25]
Rp
0
MID[19]
26
MID[26]
Rp
0
MID[20]
27
MID[27]
Rp
0
Rp
28
MID[28]
Rp
0
Rp
29
MID[29]
Rp
0
0
30
MID[30]
Rp
0
0
31
MID[31]
Rp
0
GFXSPIn_MID
Bit position
Bit name
Description
[31:0]
MID[31:0]
Module ID (MID[31:0])
This read-only register gives the unique module identification
number of HS_SPI module.
The unique module ID number identifies the version of the HS_SPI
module used in the MCU.
Note: For the module identification number of its HS_SPI refer to
the device specific data sheet for the module identification
number of its HS_SPI.
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Revised 24/7/13
20 - 290
Iris-SDL Register Descriptions
Fujitsu Semiconductor Europe GmbH
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