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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-00201-4E
2
F MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Readership
The F2MC-16LX series products are original 16-bit one-chip microcontrollers that support application
specific ICs (ASICs). They are suitable for use in various types of industrial equipment, office-automation
equipment, on-vehicle equipment, and other equipment that is required to operate at high speed in real-time
mode.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Configuration of this Manual
This manual contains the following 9 chapters and appendix.
CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION
INCLUDING IT
This chapter briefly describes the configuration of the F2MC-16LX CPU core, and presents a sample
configuration of a device incorporating it.
CHAPTER 2 MEMORY SPACE
This chapter describes the memory spaces of the F2MC-16LX CPU.
CHAPTER 3 DEDICATED REGISTERS
This chapter describes the dedicated registers of the F2MC-16LX CPU.
CHAPTER 4 GENERAL-PURPOSE REGISTERS
This chapter describes the general-purpose registers of the F2MC-16LX CPU.
CHAPTER 5 PREFIX CODES
The operation of an instruction can be modified by prefixing it with prefix code. This chapter explains
the prefix codes.
CHAPTER 6 INTERRUPT HANDLING
This chapter describes the F2MC-16LX interrupt handling functions and their operations.
CHAPTER 7 ADDRESSING
This chapter explains the addressing mode for each instruction of the F2MC-16LX.
CHAPTER 8 INSTRUCTION OVERVIEW
This chapter explains the meanings of items and symbols used in explanations in "CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS".
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
This chapter describes each execution instruction used in the assembler in a reference format.
APPENDIX
The appendix section includes lists of instructions used in the F2MC-16LX, as well as the related
instruction maps.
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■ Reference
The following manuals should be referred along with this manual:
• F2MC-16LX/16L/16/16H/16F Assembler Manual
• F2MC-16LX Model-Specific Hardware Manual
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©1998-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
Overview of the F2MC-16LX CPU Core ............................................................................................ 2
Sample Configuration of an F2MC-16LX Device ................................................................................ 3
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
GENERAL-PURPOSE REGISTERS .......................................................... 27
PREFIX CODES ......................................................................................... 31
Bank Select Prefix ............................................................................................................................
Common Register Bank Prefix (CMR) ..............................................................................................
Flag Change Inhibit Prefix Code (NCC) ............................................................................................
Constraints Related to the Prefix Codes ...........................................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.6
14
16
18
20
21
22
23
24
25
26
Register Banks in RAM ..................................................................................................................... 28
Calling General-purpose Registers in RAM ...................................................................................... 30
CHAPTER 5
5.1
5.2
5.3
5.4
DEDICATED REGISTERS ......................................................................... 13
Dedicated Register Types ................................................................................................................
Accumulator (A) ................................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) ............................................................
Processor Status (PS) ......................................................................................................................
Interrupt Level Mask (ILM) ...........................................................................................................
Register Bank Pointer (RP) .........................................................................................................
Condition Code Register (CCR) ..................................................................................................
Program Counter (PC) ......................................................................................................................
Direct Page Register (DPR) ..............................................................................................................
Bank Registers .................................................................................................................................
CHAPTER 4
4.1
4.2
MEMORY SPACE ........................................................................................ 5
CPU Memory Space ........................................................................................................................... 6
Linear Addressing Mode ..................................................................................................................... 7
Bank Addressing Mode ....................................................................................................................... 8
Memory Space Divided into Banks and Value in Each Bank Register ............................................. 10
Data Configuration of and Access to Multi-byte Data in Memory ..................................................... 11
CHAPTER 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.7
OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE
CONFIGURATION INCLUDING IT .............................................................. 1
32
34
35
36
INTERRUPT HANDLING ........................................................................... 39
Interrupt Handling .............................................................................................................................
Hardware Interrupt Operation Flow ..................................................................................................
Interrupt Handling Flowchart and Saving the Contents of Registers ................................................
Interrupt Vectors ...............................................................................................................................
Extended Intelligent I/O Service .......................................................................................................
Flowchart of Extended Iintelligent I/O Service Operation ............................................................
Flowchart of Extended Intelligent I/O Service Application Procedure .........................................
Interrupt Control Register (ICR) ........................................................................................................
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40
42
43
45
46
48
49
50
6.7
6.8
6.9
6.10
6.11
Meanings of the Bits of Interrupt Control Register (ICR) ..................................................................
Extended Intelligent I/O Service Descriptor (ISD) .............................................................................
Registers of Extended Intelligent I/O Service Descriptor ..................................................................
Exception Processing .......................................................................................................................
Interrupt Handling Program Example ...............................................................................................
CHAPTER 7
7.1
7.2
7.3
ADDRESSING ............................................................................................ 61
Effective Address Field ..................................................................................................................... 62
Direct Addressing ............................................................................................................................. 63
Indirect Addressing ........................................................................................................................... 65
CHAPTER 8
8.1
8.2
8.3
8.4
51
53
54
56
57
INSTRUCTION OVERVIEW ....................................................................... 69
Instruction Overview .........................................................................................................................
Symbols (Abbreviations) Used in Detailed Execution Instructions ...................................................
Effective Address Field .....................................................................................................................
Execution Cycles ..............................................................................................................................
CHAPTER 9
70
72
74
75
DETAILED EXECUTION INSTRUCTIONS ................................................ 79
9.1
Detailed Execution Instructions ........................................................................................................ 80
9.1.1
ADD (Add Byte Data of Destination and Source to Destination) ................................................. 81
9.1.2
ADDC (Add Byte Data of AL and AH with Carry to AL) ............................................................... 83
9.1.3
ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator) ......... 84
9.1.4
ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator) .... 86
9.1.5
ADDDC (Add Decimal Data of AL and AH with Carry to AL) ...................................................... 88
9.1.6
ADDL (Add Long Word Data of Destination and Source to Destination) ..................................... 89
9.1.7
ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer) ...................... 91
9.1.8
ADDW (Add Word Data of AL and AH to AL) .............................................................................. 92
9.1.9
ADDW (Add Word Data of Destination and Source to Destination) ............................................ 93
9.1.10 AND (And Byte Data of Destination and Source to Destination) ................................................. 95
9.1.11 AND (And Byte Data of Immediate Data and Condition Code Register) ..................................... 97
9.1.12 ANDL (And Long Word Data of Destination and Source to Destination) ..................................... 99
9.1.13 ANDW (And Word Data of AH and AL to AL) ............................................................................ 101
9.1.14 ANDW (And Word Data of Destination and Source to Destination) .......................................... 102
9.1.15 ASR (Arithmetic Shift Byte Data of Accumulator to Right) ........................................................ 104
9.1.16 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) ............................................ 106
9.1.17 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .................................................... 108
9.1.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .................................................... 110
9.1.19 BBcc (Branch if Bit Condition satisfied) ..................................................................................... 112
9.1.20 Bcc (Branch relative if Condition satisfied) ................................................................................ 114
9.1.21 CALL (Call Subroutine) .............................................................................................................. 116
9.1.22 CALLP (Call Physical Address) ................................................................................................. 118
9.1.23 CALLV (Call Vectored Subroutine) ............................................................................................ 120
9.1.24 CBNE (Compare Byte Data and Branch if not equal) ................................................................ 122
9.1.25 CLRB (Clear Bit) ........................................................................................................................ 124
9.1.26 CMP (Compare Byte Data of Destination and Source) ............................................................. 125
9.1.27 CMPL (Compare Long Word Data of Destination and Source) ................................................. 127
9.1.28 CMPW (Compare Word Data of Destination and Source) ........................................................ 129
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9.1.29
9.1.30
9.1.31
9.1.32
9.1.33
9.1.34
9.1.35
9.1.36
9.1.37
9.1.38
9.1.39
9.1.40
9.1.41
9.1.42
9.1.43
9.1.44
9.1.45
9.1.46
9.1.47
9.1.48
9.1.49
9.1.50
9.1.51
9.1.52
9.1.53
9.1.54
9.1.55
9.1.56
9.1.57
9.1.58
9.1.59
9.1.60
9.1.61
9.1.62
9.1.63
9.1.64
9.1.65
9.1.66
9.1.67
9.1.68
9.1.69
9.1.70
9.1.71
9.1.72
9.1.73
9.1.74
9.1.75
CWBNE (Compare Word Data and Branch if not Equal) ..........................................................
DBNZ (Decrement Byte Data and Branch if not zero) ...............................................................
DEC (Decrement Byte Data) .....................................................................................................
DECL (Decrement Long Word Data) .........................................................................................
DECW (Decrement Word Data) ................................................................................................
DIV (Divide Word Data by Byte Data) .......................................................................................
DIVW (Divide Long Word Data by Word Data) ..........................................................................
DIVU (Divide unsigned Word Data by unsigned Byte Data) ......................................................
DIVUW (Divide unsigned Long Word Data by unsigned Word Data) ........................................
DWBNZ (Decrement Word Data and Branch if not Zero) ..........................................................
EXT (Sign Extend from Byte Data to Word Data) ......................................................................
EXTW (Sign Extend from Word Data to Long Word Data) ........................................................
FILS (Fill String Byte) ................................................................................................................
FILSW (Fill String Word) ............................................................................................................
INC (Increment Byte Data (Address Specification)) ..................................................................
INCL (Increment Long Word Data) ............................................................................................
INCW (Increment Word Data) ...................................................................................................
INT (Software Interrupt) .............................................................................................................
INT (Software Interrupt (Vector Specification)) ..........................................................................
INT9 (Software Interrupt) ...........................................................................................................
INTP (Software Interrupt) ..........................................................................................................
JCTX (Jump Context) ................................................................................................................
JMP (Jump Destination Address) ..............................................................................................
JMPP (Jump Destination Physical Address) .............................................................................
LINK (Link and create new stack frame) ...................................................................................
LSL (Logical Shift Byte Data of Accumulator to Left) ................................................................
LSLL (Logical Shift Long Word Data of Accumulator to Left) ....................................................
LSLW (Logical Shift Word Data of Accumulator to Left) ............................................................
LSLW (Logical Shift Word Data of Accumulator to Left) ............................................................
LSR (Logical Shift Byte Data of Accumulator to Right) .............................................................
LSRL (Logical Shift Long Word Data of Accumulator to Right) .................................................
LSRW (Logical Shift Word Data of Accumulator to Right) .........................................................
LSRW (Logical Shift Word Data of Accumulator to Right) .........................................................
MOV (Move Byte Data from Source to Accumulator) ................................................................
MOV (Move Byte Data from Accumulator to Destination) .........................................................
MOV (Move Byte Immediate Data to Destination) .....................................................................
MOV (Move Byte Data from Source to Destination) ..................................................................
MOV (Move Byte Data from AH to Memory) .............................................................................
MOVB (Move Bit Data from Bit Address to Accumulator) .........................................................
MOVB (Move Bit Data from Accumulator to Bit Address) .........................................................
MOVEA (Move Effective Address to Destination) .....................................................................
MOVL (Move Long Word Data from Source to Accumulator) ...................................................
MOVL (Move Long Word Data from Accumulator to Destination) .............................................
MOVN (Move Immediate Nibble Data to Accumulator) .............................................................
MOVS (Move String Byte) .........................................................................................................
MOVSW (Move String Word) ....................................................................................................
MOVW (Move Word Data from Source to Accumulator) ...........................................................
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131
133
135
136
137
139
141
143
145
147
149
150
151
153
155
156
157
159
161
163
165
167
169
171
172
174
176
178
179
181
183
185
187
189
191
193
195
197
199
201
203
205
206
207
208
210
212
9.1.76
9.1.77
9.1.78
9.1.79
9.1.80
9.1.81
9.1.82
9.1.83
9.1.84
9.1.85
9.1.86
9.1.87
9.1.88
9.1.89
9.1.90
9.1.91
9.1.92
9.1.93
9.1.94
9.1.95
9.1.96
9.1.97
9.1.98
9.1.99
9.1.100
9.1.101
9.1.102
9.1.103
9.1.104
9.1.105
9.1.106
9.1.107
9.1.108
9.1.109
9.1.110
9.1.111
9.1.112
9.1.113
9.1.114
9.1.115
9.1.116
9.1.117
9.1.118
9.1.119
9.1.120
9.1.121
MOVW (Move Word Data from Accumulator to Destination) ..................................................... 214
MOVW (Move Immediate Word Data to Destination) ................................................................ 216
MOVW (Move Word Data from Source to Destination) ............................................................. 218
MOVW (Move Immediate Word Data to io) ............................................................................... 220
MOVW (Move Word Data from AH to Memory) ........................................................................ 221
MOVX (Move Byte Data with Sign Extension from Source to Accumulator) ............................. 222
MUL (Multiply Byte Data of Accumulator) .................................................................................. 224
MUL (Multiply Byte Data of Accumulator and Effective Address) .............................................. 225
MULW (Multiply Word Data of Accumulator) ............................................................................. 227
MULW (Multiply Word Data of Accumulator and Effective Address) ......................................... 228
MULU (Multiply Unsigned Byte Data of Accumulator) ............................................................... 230
MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address) ........................... 231
MULUW (Multiply Unsigned Word Data of Accumulator) .......................................................... 233
MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ...................... 234
NEG (Negate Byte Data of Destination) .................................................................................... 235
NEGW (Negate Word Data of Destination) ............................................................................... 237
NOP (No Operation) .................................................................................................................. 239
NOT (Not Byte Data of Destination) .......................................................................................... 240
NOTW (Not Word Data of Destination) ..................................................................................... 242
NRML (NORMALIZE Long Word) ............................................................................................. 243
OR (Or Byte Data of Destination and Source to Destination) .................................................... 245
OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)
.................................................................................................................................................... 247
ORL (Or Long Word Data of Destination and Source to Destination) ....................................... 249
ORW (Or Word Data of AH and AL to AL) ................................................................................ 251
ORW (Or Word Data of Destination and Source to Destination) ............................................... 252
POPW (Pop Word Data of Accumulator from Stack Memory) ................................................... 254
POPW (Pop Word Data of AH from Stack Memory) ................................................................. 256
POPW (Pop Word Data of Program Status from Stack Memory) .............................................. 258
POPW (Pop Registers from Stack Memory) ............................................................................. 260
PUSHW (Push Word Data of Inherent Register to Stack Memory) ........................................... 262
PUSHW (Push Registers to Stack Memory) ............................................................................. 264
RET (Return from Subroutine) ................................................................................................... 266
RETI (Return from Interrupt) ...................................................................................................... 268
RETP (Return from Physical Address) ...................................................................................... 270
ROLC (Rotate Byte Data of Accumulator with Carry to Left) ..................................................... 272
RORC (Rotate Byte Data of Accumulator with Carry to Right) .................................................. 274
SBBS (Set Bit and Branch if Bit Set) ......................................................................................... 276
SCEQ (Scan String Byte Until Equal) ........................................................................................ 278
SCWEQ (Scan String Word Until Equal) ................................................................................... 280
SETB (Set Bit) ........................................................................................................................... 282
SUB (Subtract Byte Data of Source from Destination to Destination) ....................................... 283
SUBC (Subtract Byte Data of AL from AH with Carry to AL) ..................................................... 285
SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator) 286
SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)
.................................................................................................................................................... 288
SUBDC (Subtract Decimal Data of AL from AH with Carry to AL) ............................................. 290
SUBL (Subtract Long Word Data of Source from Destination to Destination) ........................... 291
viii
9.1.122
9.1.123
9.1.124
9.1.125
9.1.126
9.1.127
9.1.128
9.1.129
9.1.130
9.1.131
9.1.132
9.1.133
9.1.134
9.1.135
SUBW (Subtract Word Data of Source from Destination to Destination) ..................................
SUBW (Subtract Word Data of AL from AH to AL) ....................................................................
SWAP (Swap Byte Data of Accumulator) ..................................................................................
SWAPW (Swap Word Data of Accumulator) .............................................................................
UNLINK (Unlink and Create New Stack Frame) ........................................................................
WBTc (Wait until Bit Condition Satisfied) ..................................................................................
XCH (Exchange Byte Data of Source to Destination) ...............................................................
XCHW (Exchange Word Data of Source to Destination) ...........................................................
XOR (Exclusive Or Byte Data of Destination and Source to Destination) .................................
XORL (Exclusive Or Long Word Data of Destination and Source to Destination) .....................
XORW (Exclusive Or Word Data of AH and AL to AL) ..............................................................
XORW (Exclusive Or Word Data of Destination and Source to Destination) ............................
ZEXT (Zero Extend from Byte Data to Word Data) ...................................................................
ZEXTW (Zero Extend from Word Data to Long Word Data) .....................................................
293
295
296
297
298
299
301
303
305
307
309
310
312
313
APPENDIX ......................................................................................................................... 315
APPENDIX A Explanation of Instruction Lists ............................................................................................
A.1 Items Used in Instruction Lists .......................................................................................................
A.2 Symbols Used in Instruction Lists ..................................................................................................
A.3 Effective Address Field ..................................................................................................................
A.4 Calculating the Number of Execution Cycles .................................................................................
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions) ...................................................................
B.1 Transfer Instructions ......................................................................................................................
B.2 Numeric Data Operation Instructions .............................................................................................
B.3 Logical Data Operation Instruction .................................................................................................
B.4 Shift Instruction ..............................................................................................................................
B.5 Branch Instructions ........................................................................................................................
B.6 Other Instructions ...........................................................................................................................
APPENDIX C F2MC-16LX Instruction Maps ...............................................................................................
C.1 Structure of the Instruction Map .....................................................................................................
C.2 Basic Page Map .............................................................................................................................
C.3 Bit Operation Instruction Map .........................................................................................................
C.4 Character String Operation Instruction Map ...................................................................................
C.5 2-byte Instruction Map ....................................................................................................................
C.6 ea-type Instruction Map ..................................................................................................................
C.7 MOVEA RWi, ea Instruction Map ...................................................................................................
C.8 MOV Ri, ea Instruction Map ...........................................................................................................
C.9 MOVW RWi, ea Instruction Map ....................................................................................................
C.10 MOV ea, Ri Instruction Map ...........................................................................................................
C.11 MOVW ea, RWi Instruction Map ....................................................................................................
C.12 XCH Ri, ea Instruction Map ............................................................................................................
C.13 XCHW RWi, ea Instruction Map .....................................................................................................
316
317
319
321
322
324
325
327
331
333
334
336
339
340
342
344
346
348
350
360
362
364
366
368
370
372
INDEX................................................................................................................................... 375
ix
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
Reviewed the explanation of the execution example.
-
Added the explanation of the execution example.
21
CHAPTER 3 DEDICATED REGISTERS
3.4.1 Interrupt Level Mask (ILM)
Changed the summary sentence.
Moved the configuration diagram of the interrupt level mask
(ILM).
22
CHAPTER 3 DEDICATED REGISTERS
3.4.2 Register Bank Pointer (RP)
Changed the summary sentence.
Moved the configuration diagram of the register bank pointer (RP).
23
CHAPTER 3 DEDICATED REGISTERS
3.4.3 Condition Code Register (CCR)
Changed the summary sentence.
Moved the configuration diagram of the condition code register
(CCR).
29
4.1 Register Banks in RAM
■ Register Banks in RAM
Corrected Table 4.1-2.
32
CHAPTER 5 PREFIX CODES
5.1 Bank Select Prefix
■ Bank Select Prefi❘
Moved the position of the "POPW PS".
50
CHAPTER 6 INTERRUPT HANDLING Corrected Figure 6.6-1.
6.6 Interrupt Control Register (ICR)
(Deleted the mark of the bit number of bit15 to bit8.)
■ Interrupt Control Register (ICR) Bit Corrected the access attribute of bit5 and bit4.
Configuration
(* → R/W *)
Corrected note.
(* : "1" is read by read operation. →
* : ICS1 and ICS0 are available only for write (W), and S1 and S0
are available only for read (R). )
51
CHAPTER 6 INTERRUPT HANDLING
6.7 Meanings of the Bits of Interrupt Control Register (ICR)
Corrected the title of the paragraph.
(■ Extended Intelligent I/O Service Channel Selection Bits
(bit15 to bit12 or bit7 to bit4: ICS0 to ICS3) →
■ Extended Intelligent I/O Service Channel Selection Bits
(bit7 to bit4: ICS0 to ICS3) )
55
CHAPTER 6 INTERRUPT HANDLING
6.9 Registers of Extended Intelligent I/O
Service Descriptor
■ Extended Intelligent I/O Service Status
Register (ISCS)
Corrected the "● bit1 (DIR): Specifies the data transfer direction."
(I/O register address pointer (IOA) →
Buffer address pointer (BAP))
(Buffer address pointer(BAP) →
I/O register address pointer (IOA))
56
CHAPTER 6 INTERRUPT HANDLING
6.10 Exception Processing
Corrected the "■ Exception Occurrence because of the Execution
of an Undefined Instruction".
(Lower bits of accumulator (AL) →
Lower word of accumulator (AL))
(Lower bits of accumulator (AH) →
Upper word of accumulator (AH))
xi
Page
57 to 60
66
Changes (For details, refer to main body.)
CHAPTER 6 INTERRUPT HANDLING
Added the 6.11 Interrupt Handling Program Example.
CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
■ Indirect Addressing
Corrected the "● Accumulator indirect (@A)".
(the lower bytes of the accumulator (AL) →
the low-order word of the accumulator (AL))
Corrected the "● Accumulator indirect branch address (@A)".
(the lower bytes of the accumulator (AL) →
the low-order word of the accumulator (AL))
82
CHAPTER 9 DETAILED EXECUTION Corrected the "● Example:".
INSTRUCTIONS
(the least significant byte data(46H) of A →
9.1.1 ADD (Add Byte Data of Destination
low-order byte data(46H) of AL)
and Source to Destination)
85
9.1.3 ADDC (Add Byte Data of
Corrected the "● Example:".
Accumulator and Effective Address with (the least significant byte data(46 ) of A →
H
Carry to Accumulator)
low-order byte data(46H) of AL)
87
9.1.4 ADDCW (Add Word Data of
Corrected the "● Example:".
Accumulator and Effective Address with (the low-order word data(2068 ) of A →
H
Carry to Accumulator)
word data(2068H) of AL)
91
9.1.7 ADDSP (Add Word Data of Stack Corrected the "● Operation:".
Pointer and Immediate Data to Stack (#imm8 → imm8)
Pointer)
(#imm16 → imm16)
94
9.1.9 ADDW (Add Word Data of
Destination and Source to Destination)
Corrected the "● Example:".
(the low-order word data (CD04H) of the accumulator →
word data (CD04H) of AL)
96
9.1.10 AND (And Byte Data of
Destination and Source to Destination)
Corrected the "● Example:".
(the least significant byte data (55H) of the accumulator →
low-order byte data (55H) of AL)
97
9.1.11 AND (And Byte Data of
Immediate Data and Condition Code
Register)
Corrected the "● Operation:".
(#imm8 → imm8)
103
9.1.14 ANDW (And Word Data of
Destination and Source to Destination)
Corrected the "● Example:".
(the low-order word data (5963H) of the accumulator →
word data (5963H) of AL)
105
9.1.15 ASR (Arithmetic Shift Byte Data of Corrected the "● Example:".
Accumulator to Right)
(the least significant byte data (96H) of A →
low-order byte data (96H) of AL)
109
9.1.17 ASRW (Arithmetic Shift Word
Data of Accumulator to Right)
Corrected the "● Example:".
(the low-order word data (A096H) of A →
word data (A096H) of AL)
111
9.1.18 ASRW (Arithmetic Shift Word
Data of Accumulator to Right)
Corrected the "● Example:".
(the low-order word data (A096H) of A →
word data (A096H) of AL)
xii
Page
Changes (For details, refer to main body.)
125
9.1.26 CMP (Compare Byte Data of
Destination and Source)
Corrected table of "● Number of bytes, Number of cycles, and
Correction value:".
(First operand : AH → A)
(Second operand : AL → −)
126
9.1.26 CMP (Compare Byte Data of
Destination and Source)
Corrected the "● Example:".
(the least significant byte data (22H) of A →
low-order byte data (22H) of AL)
129
9.1.28 CMPW (Compare Word Data of Corrected table of "● Number of bytes, Number of cycles, and
Destination and Source)
Correction value:".
(First operand : AH → A)
(Second operand : AL → −)
130
Corrected the "● Example:".
(the low-order word data (ABCDH) of A →
word data (ABCDH) of AL)
133
9.1.30 DBNZ (Decrement Byte Data and Corrected the title of the paragraph.
Branch if not zero)
(not "0") → not zero))
140
9.1.34 DIV (Divide Word Data by Byte Corrected the operand in the table of "● Number of bytes, Number
Data)
of cycles, and Correction value:".
Corrected figure of the "● Example:".
(00 31 → 00 15)
(EC D8 → 00 1D)
141
9.1.35 DIVW (Divide Long Word Data by Corrected the operand in the table of "● Number of bytes, Number
Word Data)
of cycles, and Correction value:".
144
9.1.36 DIVU (Divide unsigned Word
Data by unsigned Byte Data)
148
9.1.38 DWBNZ (Decrement Word Data Corrected figure of the "● Example:".
and Branch if not Zero)
(Z flag : 0 → 1)
149
9.1.39 EXT (Sign Extend from Byte Data Corrected the "● Example:".
to Word Data)
(the most significant bit of the least significant byte data ("80H")
Corrected the operand in the table of "● Number of bytes, Number
of cycles, and Correction value:".
for A →
the most significant bit of low-order byte data (80H) of AL)
150
9.1.40 EXTW (Sign Extend from Word Corrected the "● Example:".
Data to Long Word Data)
(the most significant bit of the low-order word data ("FF80H") for A
→
the most significant bit of word data (FF80H) of AL)
156
9.1.44 INCL (Increment Long Word
Data)
Corrected figure of the "● Example:".
(A → RL0)
160
9.1.46 INT (Software Interrupt)
Corrected figure of the "● Example:".
(SA → A (AH, AL))
162
9.1.47 INT (Software Interrupt (Vector Corrected figure of the "● Example:".
Specification))
(SA → A (AH, AL))
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Changes (For details, refer to main body.)
164
9.1.48 INT9 (Software Interrupt)
Corrected figure of the "● Example:".
(SA → A (AH, AL))
168
9.1.50 JCTX (Jump Context)
Corrected figure of the "● Example:".
(SA → A (AH, AL))
189
9.1.62 MOV (Move Byte Data from
Source to Accumulator)
Corrected the summary sentence.
bit16 to bit31 → AH
bit0 tobit15 → AL
191
9.1.63 MOV (Move Byte Data from
Accumulator to Destination)
Corrected the summary sentence.
(Transfer the least significant byte data of the accumulator (A) to
the address specified by the first operand. →
Transfer the low-order byte data of AL to the first operand. )
Corrected table of "● Number of bytes, Number of cycles, and
Correction value:".
(Second operand → First operand)
193
9.1.64 MOV (Move Byte Immediate data Corrected the summary sentence.
to Destination)
(the address specified by the first operand → the first operand)
Corrected the "● Operation:".
(#imm8 → imm8)
203
9.1.69 MOVEA (Move Effective Address Corrected the summary sentence.
to Destination)
(bit16 to bit31 → AH)
(bit0 to bit15 → AL)
207
9.1.72 MOVN (Move Immediate Nibble Corrected the summary sentence.
Data to Accumulator)
(bit16 to bit31 → AH)
(bit0 to bit15 → AL)
212
9.1.75 MOVW (Move Word Data from Corrected the summary sentence.
Source to Accumulator)
(bit16 to bit31 → AH)
(bit0 to bit15 → AL)
216
9.1.77 MOVW (Move Immediate Word Corrected the "● Operation:".
Data to Destination)
(#imm16 → imm16)
Corrected the "● CCR:".
(Deleted "and none of the flags is changed.".)
222
9.1.81 MOVX (Move Byte Data with
Sign Extension from Source to
Accumulator)
Corrected the summary sentence.
(bit16 to bit31 → AH)
(bit0 to bit15 → AL)
247
9.1.97 OR (Or Byte Data of Immediate
Data and Condition Code Register to
Condition Code Register)
Corrected the "● Operation:".
(#imm8 → imm8)
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154,
156-158,
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168, 170,
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304, 306,
308, 309,
311-313
CHAPTER 9 DETAILED EXECUTION
INSTRUCTIONS
Added the explanation of "● Example:".
90, 92,
101, 119,
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134, 148
CHAPTER 9 DETAILED EXECUTION
INSTRUCTIONS
Corrected the "● Example:".
The vertical lines marked in the left side of the page show the changes.
xv
xvi
CHAPTER 1
OVERVIEW OF
THE
2
F MC-16LX
CPU CORE
AND SAMPLE
CONFIGURATION
INCLUDING IT
This chapter briefly describes the configuration of the
F2MC-16LX CPU core, and presents a sample
configuration of a device incorporating it.
1.1 Overview of the F2MC-16LX CPU Core
1.2 Sample Configuration of an F2MC-16LX Device
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CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
2
1.1 Overview of the F2MC-16LX CPU Core
F MC-16LX Family
1.1
Overview of the F2MC-16LX CPU Core
The F2MC-16LX CPU core is an advanced 16-bit CPU designed for use in various types
of industrial equipment, office automation equipment, on-vehicle equipment, and other
equipment required to operate at high speed in real-time mode.
■ Overview of the F2MC-16LX CPU Core
The F2MC-16LX CPU core is an advanced 16-bit CPU designed for use in various types of industrial
equipment, office automation equipment, on-vehicle equipment, and other equipment required to operate at
high speed in real-time mode. The design of the F2MC-16LX instruction set is optimized for use in
controllers. The instructions can perform various types of control at high speed and at high efficiency. The
F2MC-16LX is a suitable CPU for processing 16-bit data. Some of its instructions can be used also for 32bit data processing, because its CPU incorporates a 32-bit accumulator. The memory space of the F2MC16LX can be expanded up to 16 Mbytes. Each location in the memory space can be accessed using either a
linear pointer or a bank method. The instruction set is based on the F2MC-8 A-T architecture, but has been
enhanced by adding instructions that support high-level language, extending the addressing mode,
improving the multiplication and division instructions, and augmenting bit manipulation.
■ Features of the F2MC-16LX CPU Core
● Minimum instruction execution time: 62.5 ns (with internal clock at 16 MHz)
● Memory space: Up to 16 Mbytes, accessible using either a linear or bank mode
● Instruction set optimized for use in controllers
• Cornucopia of data types: Bit, byte, word, and long word
• Extended addressing mode: 23 types
• High code efficiency
• Reinforcement of high-precision calculation (32-bit length) by means of a 32-bit accumulator
● Powerful interrupt functions
Interrupt priority levels: 8 levels (programmable)
● CPU-independent automatic transfer function
● Extended intelligent I/O service: Up to 16 channels
● Instruction supporting high-level language (C language) and multitasking
• Use of a system stack pointer
• Various pointers
• High symmetry of the instruction set
• Barrel shift instruction
● Increased execution speed: Use of a 4-byte queue for waiting of instructions
2
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CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
1.2 Sample Configuration of an F2MC-16LX Device
F2MC-16LX Family
1.2
Sample Configuration of an F2MC-16LX Device
Figure 1.2-1 shows a sample configuration of an F2MC-16LX device.
■ Sample Configuration of an F2MC-16LX Device
Figure 1.2-1 F2MC-16LX Device Sample Configuration
User pin section
Pin section peripheral to the CPU
Direct page
register
Timer/counter
Stack pointer
Register bank
pointer
Serial port
Program
counter
Processor
status
register
Bank register
F²MC-16LX CPU
F²MC-16LX bus
Accumulator
A/D converter
RAM (data area)
ROM
(program area)
ALU
Interrupt
controller
Clock generator
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CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
2
1.2 Sample Configuration of an F2MC-16LX Device
F MC-16LX Family
4
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CHAPTER 2
MEMORY SPACE
This chapter describes memory spaces in the F2MC16LX CPU.
2.1 CPU Memory Space
2.2 Linear Addressing Mode
2.3 Bank Addressing Mode
2.4 Memory Space Divided into Banks and Value in Each Bank Register
2.5 Data Configuration of and Access to Multi-byte Data in Memory
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CHAPTER 2 MEMORY SPACE
F2MC-16LX Family
2.1 CPU Memory Space
2.1
CPU Memory Space
All data, programs, and I/O areas managed in the CPU are allocated in its 16-Mbyte
memory space. The CPU can access these resources using an address on the 24-bit
address bus (see Figure 2.1-1 ).
The addressing mode can be classified either as a linear or bank mode. The linear
mode specifies an entire 24-bit address using a instruction. The bank mode specifies
the upper 8 bits of each address using a bank register, and the remaining 16-bit address
using an instruction.
■ CPU Memory Space
Figure 2.1-1 Example of Relationship between the F2MC-16LX System and Memory Map
Program
⎧ FFFFFFH
⎨
⎩
Program area
⎧ 810000H
⎪
⎪
⎨
⎪
⎪
⎩ 800000
Data area
FF8000H
F2MC-16LX
CPU
Data
Interrupt
H
Peripheral
circuit
General-purpose
port
[Device]
6
⎧ 0000C0H
⎨
⎩
⎧ 0000B0H
⎨
⎩
000020H
⎧
⎨
⎩ 000000
Interrupt controller
Peripheral circuit
General-purpose port
H
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CM44-00201-4E
CHAPTER 2 MEMORY SPACE
F2MC-16LX Family
2.2
Linear Addressing Mode
2.2 Linear Addressing Mode
The linear addressing mode specifies an entire 24-bit address using an instruction.
■ Linear Addressing Mode
The linear addressing mode specifies an entire 24-bit address using an instruction. The address mode of the
F2MC-16LX is determined according to the specification of the effective address or instruction code
(implied) of an instruction.
The linear addressing mode can operate in two different ways. In the first way, an operand of an instruction
directly specifies an entire 24-bit address. In the second way, the lower 24-bit of a 32-bit general-purpose
register is referred as an address (see Figure 2.1-1 ).
Figure 2.2-1 Examples of Generating an Address in the Linear Addressing Mode
Example 1: 24-bit Operand Specification in the Linear Addressing Mode
JMPP 123456H
Previous content of
program counter plus
program bank
17452DH
17
452D
Latest content of
program counter plus 12
program bank
3456
JMPP 123456H
123456H
Next instruction
Example 2: Indirect Addressing Based on 32-bit Register in the Linear Addressing Mode
MOV A @RL1+7
Previous content
of the AL
XXXX
090700H
3A
+7
240906F9
RL1
(Upper 8 bits are ignored.)
Latest content
of the AL
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003A
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CHAPTER 2 MEMORY SPACE
F2MC-16LX Family
2.3 Bank Addressing Mode
2.3
Bank Addressing Mode
The bank addressing mode specifies the upper 8 bits of an address using a bank
register for specific use, and the remaining 16 bits using an instruction.
■ Bank Addressing Mode
In the bank addressing mode, the 16-Mbyte memory space is divided into 256 banks of 64-Kbyte, the
corresponding bank for each space is specified by the following 4 bank registers.
● Program counter bank register (PCB)
A 64-Kbyte bank specified using the PCB register is called a program (PC) space. It is used to hold mainly
instruction codes, vector tables, and immediate data.
● Data bank register (DTB)
A 64-Kbyte bank specified using the DTB register is called a data (DT) space. It is used to hold mainly
readable/writable data and control/data registers for internal and external resources.
● User stack bank register (USB) and system stack bank register (SSB)
A 64-Kbyte bank specified using the USB or SSB register is called a stack (SP) space. It is accessed when
the execution of a push or pop instruction or interrupt handling is performed and which to be used, the USB
or SSB register, is determined according to the S flag in the condition code register to save register contents
and a stack access occurs.
● Additional data bank register (ADB)
A 64-Kbyte bank specified using the ADB register is called an additional (AD) space. It is used to hold
mainly data overflowing from the DT space.
Each instruction is assigned with one of the default spaces by each addressing listed in Table 2.3-1 to
improve instruction code efficiency.
Table 2.3-1 Default Spaces
Default space
8
Addressing
Program space
PC-indirect, program access, branch type
Data space
@A, addr16, dir, or addressing using @RW0, @RW1, @RW4, or @RW5
Stack space
Addressing using PUSHW, POPW, @RW3, @RW7, or @SP
Additional space
Addressing using @RW2 or @RW6
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CM44-00201-4E
CHAPTER 2 MEMORY SPACE
F2MC-16LX Family
2.3 Bank Addressing Mode
If a space other than a default space is used, an arbitrary bank space corresponding to a prefix code can be
accessed by specifying the prefix code before the instruction.
Table 2.3-2 lists bank select prefixes and the memory space selected using each prefix.
Table 2.3-2 Bank Selection Prefix
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the contents of the selected
stack flag
The DTB, USB, SSB, and ADB registers are initialized to 00H at a reset. The PCB register is initialized to
FFH at a reset. After a reset, the data, stack, and additional spaces are allocated in bank 00H (000000H to
00FFFFH), and the program space is allocated in bank FFH (FF0000H to FFFFFFH).
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CHAPTER 2 MEMORY SPACE
F2MC-16LX Family
Memory Space Divided into Banks and Value in Each Bank
Register
2.4 Memory Space Divided into Banks and Value in Each Bank Register
2.4
Figure 2.4-1 shows an example of a memory space divided into banks and a value in
each register bank.
■ Memory Space Divided into Banks and Values in Each Register Bank
Figure 2.4-1 Example of the Physical Addresses of Each Space
FFFFFFH
Program space
FF0000H
FFH
: PCB (program counter bank register)
B3H
: ADB (additional data bank register)
B3FFFFH
Additional space
Physical Address
B30000H
92FFFFH
User stack space
920000H
92H
: USB (user stack bank register)
68H
: DTB (data bank register)
4BH
: SSB (system stack bank register)
68FFFFH
Data space
680000H
4BFFFFH
System stack space
4B0000H
000000H
10
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CM44-00201-4E
CHAPTER 2 MEMORY SPACE
2.5 Data Configuration of and Access to Multi-byte Data in Memory
F2MC-16LX Family
2.5
Data Configuration of and Access to Multi-byte Data in
Memory
Multi-byte data is written to memory starting at the lowest address. If the multi-byte
data is 32-bit long, the lower 16 bits are written to memory first and then upper 16 bits.
■ Multi-byte Data Layout in a Memory Space
Multi-byte data is written to memory starting at the lowest address. If the multi-byte data is 32-bit length,
the lower 16 bits are written to memory first and then upper 16 bits.
If a reset signal is input immediately after the low-order data is written to memory, the high-order data may
not be written. To keep the data in integrity, it is necessary to input a reset signal after the high-order data
is written.
Figure 2.5-1 shows the layout of multi-byte data in memory. The lower 8 bits are placed at address n, the
next lower 8 bits are placed at address n + 1, and the next lower 8 bits are placed at address n + 2, and so
on.
Figure 2.5-1 Multi-byte Data Layout in Memory
MSB
01010101
H
LSB
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
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CHAPTER 2 MEMORY SPACE
2.5 Data Configuration of and Access to Multi-byte Data in Memory
F2MC-16LX Family
■ Access to Multi-byte Data
When multi-byte data is accessed, it is assumed that all parts of the multi-byte data are within a single bank.
To put it another way, an instruction accessing multi-byte data assumes that an address that follows address
FFFFH is 0000H in the same bank as for FFFFH.
Figure 2.5-2 shows an execution example of an instruction accessing multi-byte data.
Figure 2.5-2 Execution Example of an Instruction (MOVPW A, 080FFFFH) Accessing Multi-byte Data
Higher address
80FFFFH
AL before execution
??
??
AL after execution
23H 01H
01H
·
·
·
800000H
23H
Lower address
12
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CHAPTER 3
DEDICATED REGISTERS
The registers of the F2MC-16LX can be grouped into two
major categories: dedicated registers in the CPU and
general-purpose registers allocated in memory.
This chapter describes the dedicated registers. These
registers are the dedicated hardware in the CPU. Their
use is limited due to the architecture of the CPU.
3.1 Dedicated Register Types
3.2 Accumulator (A)
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.4 Processor Status (PS)
3.5 Program Counter (PC)
3.6 Direct Page Register (DPR)
3.7 Bank Registers
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.1 Dedicated Register Types
3.1
Dedicated Register Types
There are 11 dedicated registers.
• Accumulator (A=AH:AL)
• System stack pointer (SSP)
• Program counter (PC)
• Data bank register (DTB)
• System stack bank register (SSB)
• Direct page register (DPR)
•
•
•
•
•
User stack pointer (USP)
Processor status (PS)
Program counter bank register (PCB)
User stack bank register (USB)
Additional data bank register (ADB)
■ Dedicated Register Types
● Accumulator (A=AH:AL)
This is a set of two 16-bit accumulators. It can be used as a single 32-bit accumulator.
● User stack pointer (USP)
This is a 16-bit pointer indicating a user stack area.
● System stack pointer (SSP)
This is a 16-bit pointer indicating a system stack area.
● Processor status (PS)
This is a 16-bit register indicating the status of the system.
● Program counter (PC)
This is a 16-bit register to hold an address where the next instruction to be executed is stored.
● Program counter bank register (PCB)
This is an 8-bit register indicating the program space.
● Data bank register (DTB)
This is an 8-bit register indicating the data space.
● User stack bank register (USB)
This is an 8-bit register indicating the user stack space.
● System stack bank register (SSB)
This is an 8-bit register indicating the system stack space.
14
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CM44-00201-4E
CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.1 Dedicated Register Types
● Additional data bank register (ADB)
This is an 8-bit register indicating the additional space.
● Direct page register (DPR)
This is an 8-bit register indicating the direct page.
Figure 3.1-1 shows an image of the dedicated registers.
Figure 3.1-1 Dedicated Registers
AH
Accumulator
AL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bits
16 bits
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program counter bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
32 bits
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.2 Accumulator (A)
3.2
Accumulator (A)
The accumulator (A) consists of two 16-bit length operation registers (AH and AL), is
used for temporary storage of the results for an operation or of data to be transferred.
■ Accumulator (A)
The accumulator (A) consists of two 16-bit length operation registers (AH and AL), used for temporary
storage of the results for an operation or of data to be transferred.
To process 32-bit data, the AH and AL registers are concatenated (see Figure 3.2-1 ). To process 16-bit
data (used in word-unit processing) or 8-bit data (used in byte-unit processing), only the AL register is used
(see Figure 3.2-2 ). Various types of arithmetic and logical operations can be performed between data in
the accumulator (A) and data in memory or a register (such as Ri, RWi, or RLi).
Similarly to the F2MC-8, the F2MC-16LX automatically transfers data from the AL register to the AH
register, if it receives new data at the AL register and the new data is not larger than a word (data
preservation function). Use of this data preservation function and a function to perform arithmetic and
logical operations between the AL and AH registers makes various types of processing more efficient (see
Figure 3.2-2 ).
If data transferred to the AL register is not larger than a byte, the data is sign- or zero-extended to 16 bits
and it is stored in the AL register. The data in the AL register can be handled as either a word or a byte. If
a byte-unit arithmetic operation is performed on the AL register, the upper 8 bits of data that have been
previously set in the AL register are ignored and reset to all "0"s.
Figure 3.2-1 Example of Transferring 32-bit Data
MOVL A, @RW1+6
LSB
MSB
Previous content
of the A register
XXXXH
XXXXH
DTB
A6H
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
Latest content
of the A register
16
8F74H
2B52H
AH
AL
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CM44-00201-4E
CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.2 Accumulator (A)
Figure 3.2-2 Example of Transferring Data between the AL and AH Registers by Means of the Data
Preservation Function
MOVW A, @RW1+6
LSB
MSB
Previous content
of the A register
XXXXH
1234H
DTB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
A6H
+6
Latest content
of the A register
CM44-00201-4E
1234H
2B52H
AH
AL
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
User Stack Pointer (USP) and System Stack Pointer (SSP)
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.3
Both the user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers.
They are used to indicate a data save address or return address when a push, pop
instruction, or subroutine is executed.
Basically, a value to be set in a stack pointer must be an even address.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
Both the user stack pointer (USP) and system stack pointer (SSP) are a 16-bit register. They are used to
indicate a data save address or return address when a push, pop instruction, or subroutine is executed. The
USP and SSP registers are used by stack manipulation instructions in the same manner. If the stack flag (S)
in the condition code register (CCR) in the processor status (PS) register is "0", the USP register is active.
If the S flag is "1", the SSP register is active (see Figure 3.3-1 ). Because the S flag becomes "1" when an
interrupt is accepted, the SSP register is used to indicate a memory area to save register contents at an
interrupt. The SSP register is used by an interrupt routine for stack manipulation, while the USP register is
used by non-interrupt handling routines for stack manipulation. If it is unnecessary to divide the stack
space, only the SSP register should be used.
For the SSP register, the upper 8 bits of an address used for stack manipulation are indicated by the system
stack bank register (SSB). For the USP register, they are indicated by the user stack bank register (USB).
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
Figure 3.3-1 Relationships between Stack Manipulation Instruction and Stack Pointer
Example 1: PUSHW A executed when the S flag is "0"
MSB
AL A624H
S flag
After execution ➪
0
AL A624H
S flag
0
USB C6H
USP F328H
SSB 56H
SSP 1234H
USB C6H
USP F326H
SSB 56H
SSP 1234H
C6F326H
➪
Before execution ➪
LSB
XX
XX
The user stack is used
because the S flag is "0".
C6F326H A6H
24H
561232H
XX
XX
561232H
A6H
24H
Example 2: PUSHW A executed when the S flag is "1"
AL A624H
USB C6H
USP F328H
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F328H
S flag 1
SSB 56H
SSP 1232H
S flag
After execution ➪
CM44-00201-4E
1
➪
Before execution ➪
The system stack is used
because the S flag is "1".
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.4 Processor Status (PS)
3.4
Processor Status (PS)
The processor status (PS) register consists of bits for controlling the CPU and those for
indicating the status of the CPU. The PS register is divided into the following three
registers.
• Interrupt level mask (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor Status (PS)
The processor status (PS) register consists of bits for controlling the CPU and those for indicating the status
of the CPU.
• Interrupt level mask (ILM): Indicates the level of an interrupt to be accepted.
• Register bank pointer (RP): Indicates the start address of a register bank.
• Condition code register (CCR): Consists of various flags that are set or clear during instruction
execution or at an interrupt occurrence.
Figure 3.4-1 shows the structure of the processor status (PS) register.
Figure 3.4-1 Processor Status (PS) Register Structure
bit
PS
20
13 12
15
ILM
87
RP
0
CCR
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.4.1
Interrupt Level Mask (ILM)
3.4 Processor Status (PS)
The interrupt level mask (ILM) indicates the levels of interrupts acceptable to the CPU.
■ Interrupt Level Mask (ILM)
The following shows a configuration diagram of the interrupt level mask (ILM).
ILM
ILM2
ILM1
ILM0
(Initial value)→
0
0
0
The interrupt level mask (ILM) consists of 3 bits. It indicates the levels of interrupts acceptable to the
CPU. If an interrupt request whose level is higher than the level indicated using these 3 bits, the interrupt is
generated. Interrupt level 0 is the highest, and interrupt level 7 is the lowest (see Table 3.4-1 ).
For an interrupt to be accepted, its interrupt level value must be smaller than the value held in the ILM
register. When an interrupt is accepted, its interrupt level is set in the ILM register, thus prohibiting
interrupts on lower levels from being accepted. Because the ILM register is initialized to all "0"s at a reset,
the highest interrupt level is specified in the ILM register. It is possible to transfer 8-bit immediate data to
the ILM register, but only the lower 3 bits of the data can be used.
Table 3.4-1 Interrupt Levels Indicated in the Interrupt Level Mask (ILM)
CM44-00201-4E
ILM2
ILM1
ILM0
Level value
Levels of acceptable interrupts
0
0
0
0
Interrupt disabled
0
0
1
1
0
0
1
0
2
1 and below
0
1
1
3
2 and below
1
0
0
4
3 and below
1
0
1
5
4 and below
1
1
0
6
5 and below
1
1
1
7
6 and below
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.4 Processor Status (PS)
3.4.2
Register Bank Pointer (RP)
The register bank pointer (RP) indicates the address on RAM for a general-purpose
register.
■ Register Bank Pointer (RP)
The following shows a configuration diagram of the register bank pointer (RP).
RP
B4
B3
B2
B1
B0
(Initial value)→
0
0
0
0
0
The register bank pointer (RP) indicates the address of an internal RAM area where the general-purpose
registers exists. The start memory address of a register bank currently in use is represented using the
following conversion expression: [000180H + RP × 10H]. The RP register consists of 5 bits. It can hold
any value between 00H and 1FH. So the start memory address of the register bank can be set in the range
between 000180H and 00037FH. Therefore, the register bank can be allocated at memory locations in the
range between 000180H and 00037FH. If the internal RAM area used as an external area, however, it
cannot be used as general-purpose registers even if the register bank is within that range. It is possible to
transfer 8-bit immediate data to the RP register, but only the lower 5 bits of the data can be used.
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.4.3
Condition Code Register (CCR)
3.4 Processor Status (PS)
Each flag in the condition code register is reset or cleared due to the execution of an
instruction or the occurrence of an interrupt.
■ Condition Code Register (CCR)
The following shows a configuration diagram of the condition code register (CCR).
bit
CCR
(Initial value)→
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
0
1
–
–
–
–
–
-: Undefined
• I (Interrupt enable flag): If the I flag is "1", all non-software interrupts are acceptable. If the flag is "0",
they are disabled. The flag is cleared by a reset.
• S (Stack flag): If the S flag is "0", the user stack pointer (USP) is active as a pointer for stack
manipulation. If the flag is "1", the system stack pointer (SSP) is active. The flag is set
at a reset and when an interrupt is accepted.
• T (Sticky bit flag): If at least one bit read from the C flag is "1" when a logical shift right instruction or
an arithmetic shift right instruction is executed, this flag becomes "1". Otherwise,
the flag becomes "0". The flag becomes "0" also if the amount of shifting is "0".
• N (Negative flag): If the most significant bit of an arithmetic or logical operation result is "1", this flag
is set. If it is "0", this flag is cleared.
• Z (Zero flag): If the result of an arithmetic or logical operation is all "0"s, this flag is set. Otherwise, it
is cleared.
• V (Overflow flag): This flag is set if a digit overflow occurs in a signed value generated as the result of
an arithmetic or logical operation. Otherwise, the flag is cleared.
• C (Carry flag): This flag is set if an arithmetic or logical operation causes a carry from or a borrow to
the most-significant bit. Otherwise, the flag is cleared.
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.5 Program Counter (PC)
3.5
Program Counter (PC)
The program counter (PC) indicates the upper 16 bits of a memory address where the
next instruction to be executed by the CPU.
■ Program Counter (PC)
The program counter (PC) consists of 16 bits. It indicates the lower 16 bits of a memory address where the
next instruction to be executed by the CPU is (see Figure 3.5-1 ). The upper 8 bits of the memory address
are indicated in the program counter bank register (PCB). The content of the PC register is updated, when
a conditional branch or subroutine call instruction is executed, upon an interrupt occurrence, or at a reset.
The PC register is used also as a base pointer for reading an operand.
Figure 3.5-1 Program Counter (PC)
PCB
FEH
PC
ABCDH
FEABCDH
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Next instruction
to be executed
CM44-00201-4E
CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.6
Direct Page Register (DPR)
3.6 Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 (addr8 to addr15) of an operand
address for an instruction in direct addressing mode.
■ Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 (addr8 to addr15) of an operand address for an
instruction in direct addressing mode, as shown in Figure 3.6-1 . The DPR register is 8 bits long. It is
initialized to 01H at a reset. It can be read- and write-accessed by an instruction.
Figure 3.6-1 Physical Address Specified in Direct Addressing Mode
DPR register
DTB register
αααααααα
ββββββββ
MSB
24-bit
physical address
CM44-00201-4E
Direct address in an instruction
γγγγγγγγ
LSB
ααααααααββββββββγγγγγγγγ
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CHAPTER 3 DEDICATED REGISTERS
F2MC-16LX Family
3.7 Bank Registers
3.7
Bank Registers
The following 5 bank registers are available in the F2MC-16LX.
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
These registers indicate memory banks allocated for the program, data, user stack,
system stack, and additional spaces, respectively.
■ Bank Registers
All of these bank registers are 1 byte length. At a reset, the PCB register is initialized to FFH, and the other
registers, to 00H. The PCB register can be read-accessed, but not write-accessed. The other bank registers
can be both read- and write-accessed. The content of the PCB register is updated, when a JMPP, CALLP,
RETP, or RETI instruction for a branch anywhere in the 16-Mbyte space is executed or an interrupt occurs.
See "CHAPTER 2 MEMORY SPACE" for descriptions about the operation of each register.
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CM44-00201-4E
CHAPTER 4
GENERAL-PURPOSE
REGISTERS
The registers of the F2MC-16LX can be grouped into two
major categories: dedicated registers in the CPU and
general-purpose registers allocated in memory.
This chapter describes the general-purpose registers.
These registers are allocated in a RAM in address space
of the CPU. Similarly to the dedicated registers, the
general-purpose registers can be accessed without
specifying their address. However, the user can specify
the purpose for which they are used in the same manner
as for ordinary memory.
4.1 Register Banks in RAM
4.2 Calling General-purpose Registers in RAM
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
F2MC-16LX Family
4.1 Register Banks in RAM
4.1
Register Banks in RAM
Each register bank consists of 8 words (16 bytes). They can be used as generalpurpose registers (byte registers R0 to R7, word registers RW0 to RW7, and long word
registers RL0 to RL3) for performing various types of operations and specifying
pointers. RL0 to RL3 can be used also as a linear pointer to gain direct access to all
spaces in memory.
■ Register Banks in RAM
Table 4.1-1 lists the function of each register, and Table 4.1-2 shows relationships between the registers.
Table 4.1-1 Functions of Each Register
Register name
R0 to R7
28
Function
Used to hold an operand in various types of instructions.
Note: R0 is also used as a barrel shift counter and a counter of normarize
instruction.
RW0 to RW7
Used to hold a pointer.
Used to hold an operand in various types of instructions.
Note: RW0 is used also as a string instruction counter.
RL0 to RL3
Used to hold a long pointer.
Used to hold an operand in various types of instructions.
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
2
F MC-16LX Family
4.1 Register Banks in RAM
Table 4.1-2 Relationship between Registers
Address
Byte register
000180H + RP × 10H + 0
Long word register
RW0
000180H + RP × 10H + 1
RL0
000180H + RP × 10H + 2
RW1
000180H + RP × 10H + 3
000180H + RP × 10H + 4
RW2
000180H + RP × 10H + 5
RL1
000180H + RP × 10H + 6
RW3
000180H + RP × 10H + 7
000180H + RP × 10H + 8
R0
000180H + RP × 10H + 9
R1
000180H + RP × 10H + 10
R2
000180H + RP × 10H + 11
R3
000180H + RP × 10H + 12
R4
000180H + RP × 10H + 13
R5
000180H + RP × 10H + 14
R6
000180H + RP × 10H + 15
R7
CM44-00201-4E
Word register
RW4
RL2
RW5
RW6
RL3
RW7
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
F2MC-16LX Family
Calling General-purpose Registers in RAM
4.2 Calling General-purpose Registers in RAM
4.2
For general-purpose registers, the register bank pointer (RP) is used to specify where in
internal RAM between 000180H and 00037FH the register bank currently in use is
allocated.
■ Calling General-purpose Registers in RAM
The general-purpose registers are allocated in internal RAM between 000180H and 00037FH (in maximum
configuration). The register bank pointer (RP) is used to indicate where in internal RAM between 000180H
and 00037FH the register bank currently in use is allocated. Each bank contains the following 3 different
registers. These registers are not independent of one another. Instead, they have the relationships shown in
Figure 4.2-1 .
• R0 to R7:
8-bit general-purpose registers
• RW0 to RW7: 16-bit general-purpose registers
• RL0 to RL3: 32-bit general-purpose registers
Figure 4.2-1 General-purpose Registers
000180H + RP × 10H
Start address of a
general-purpose
register
16 bits
RW0
RW1
RW2
RW3
Lower order
Higher order
LSB
R1
R3
R5
R7
R0
R2
R4
R6
RW4
RW5
RW6
RW7
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
MSB
RL0
RL1
RL2
RL3
The relationships among the high- and low-order bytes in word registers (RW4 to RW7) and byte registers
(R0 to R7) are represented using the following expression:
RW (i + 4) = R (i × 2 + 1) × 256 + R (i × 2) [where i = 0 to 3]
The relationships among the high- and low-order word in long registers (RL0 to RL3) and word registers
(RW0 to RW7) are represented using the following expression:
RL (i) = RW (i × 2 + 1) × 65536 + RW (i × 2) [where i = 0 to 3]
For example, if the data in R1 and the data in R0 are arranged as high- and low-order bytes, respectively,
the resulting data equals the data (2 bytes) in RW4.
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CM44-00201-4E
CHAPTER 5
PREFIX CODES
The operation of an instruction can be modified by
prefixing it with prefix code. The following 3 types of
prefix codes are available.
• Bank select prefix
• Common register bank prefix
• Flag change inhibit prefix code
This chapter describes these prefixes.
5.1 Bank Select Prefix
5.2 Common Register Bank Prefix (CMR)
5.3 Flag Change Inhibit Prefix Code (NCC)
5.4 Constraints Related to the Prefix Codes
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CHAPTER 5 PREFIX CODES
5.1 Bank Select Prefix
5.1
F2MC-16LX Family
Bank Select Prefix
Placing a bank select prefix before an instruction enables selecting the memory space
accessed by the instruction regardless of what the current addressing mode is.
■ Bank Select Prefix
The memory space of data to be accessed is determined according to the addressing mode. Placing a bank
select prefix before an instruction enables to select the memory space accessed by the instruction regardless
of what the current addressing mode is. Table 5.1-1 lists the bank select prefixes and the memory space
selected according to each bank select prefix.
Table 5.1-1 Bank Select Prefixes
Bank select prefix
Memory space to be selected
PCB
Program counter space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the state of the stack flag
The following instructions have a different effect of prefix codes.
• Transfer instructions (I/O access)
MOV A,io
MOVW io,A
MOV io, A
MOV io,#imm8
MOVX A,io
MOVW A,io
MOVW io,#imm16
These instructions access the I/O space regardless of whether there is a prefix before them.
• Branch instruction
RETI
The system stack bank (SSB) is used regardless of whether there is a prefix before the branch instruction.
• Bit manipulation instructions (I/O access)
MOVB A,io:bp
MOVB io:bp,A
SETB io:bp
CLRB io:bp
BBC io:bp,rel
BBS io:bp,rel
WBTC
WBTS
The I/O space is accessed regardless of whether there is a prefix before those instructions.
• String manipulation instructions
MOVS
MOVSW
SCEQ
SCWEQ
FILS
FILSW
A bank register specified in the operand is used regardless of whether there is a prefix before these
instructions.
• Other types of control instructions (stack manipulation)
PUSHW
POPW
POPW PS
The system stack bank (SSB) or user stack bank (USB) is used depending on the state of the S flag,
regardless of whether there is a prefix before these instructions.
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CHAPTER 5 PREFIX CODES
F2MC-16LX Family
5.1 Bank Select Prefix
In the following cases, the prefix of an instruction affects not only that instruction but also an instruction
that follows it.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
The operations of these instructions are performed normally. The prefix of each of these instructions
affects not only the instructions but also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.2 Common Register Bank Prefix (CMR)
5.2
F2MC-16LX Family
Common Register Bank Prefix (CMR)
Placing a common register bank prefix (CMR) before an instruction accessing a register
bank enables to change that the instruction is to access only the registers in a common
bank (register bank selected when RP = 0) allocated between 000180H and 00018FH,
regardless of what the current value of the register bank pointer (RP) is.
■ Common Register Bank Prefix (CMR)
To make data exchange among tasks easier, it is necessary to use a method that can access a certain
specified register bank relatively easily no matter what value the RP register holds. To meet this
requirement, the F2MC-16LX has a register bank that can be used by all tasks in common. It is called a
common bank. The common bank is allocated in memory between address 000180H and 00018FH. It is
selected when the RP register contains a value of "0".
Placing the common register bank prefix (CMR) before an instruction accessing a register bank enables to
change that the instruction is to access only the registers in a common bank (register bank selected when
RP = 0) allocated between 000180H and 00018FH, regardless of what the current value of the register bank
pointer (RP) is.
The following instructions have a different effect of prefix codes.
• String instructions
MOVS
NOVSW
SCEQ
FILS
FILSW
If an interrupt is requested during execution of a string manipulation instruction attached with a prefix
code, the prefix becomes ineffective for the string manipulation instruction after a return is made from
the interrupt handling routine, possibly resulting in a malfunction. Do not place the CMR prefix before
these string manipulation instructions.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
The operations of these instructions are performed normally. The prefix of each of these instructions
affects not only the instructions but also an instruction that follows them.
• Other control instructions (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.3 Flag Change Inhibit Prefix Code (NCC)
F2MC-16LX Family
5.3
Flag Change Inhibit Prefix Code (NCC)
Placing the flag change inhibit prefix code (NCC) before an instruction inhibits flags
from changing during execution of the instruction.
■ Flag Change Inhibit Prefix Code (NCC)
The flag change inhibit prefix code (NCC) is used to suppress undesired changes to flags. Placing the NCC
prefix before an instruction inhibits flags from changing during execution of the instruction.
The following instructions have a different effect of prefix codes.
• Branch instructions
INT #vct8
INT9
INTP addr24
RETI
INT addr16
These instructions change the flags in the condition code register (CCR) regardless of whether there is a
prefix before them.
• String instructions
MOVE
MOVSW
SCEQ
SCWEQ
FILS
FISW
If an interrupt is requested during execution of a string manipulation instruction attached with a prefix
code, the prefix becomes ineffective for the string manipulation instruction after a return is made from
the interrupt handling routine, possibly resulting in a malfunction. Do not place the NCC prefix before
these string manipulation instructions.
• Another type of control instruction (task switching)
JCTX @A
This instruction changes the flags in the CCR register regardless of whether there is a prefix before it.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
These instructions change the flags in the CCR register regardless of whether there is a prefix before
them. The prefix of each of these instructions affects not only the instructions but also an instruction that
follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.4 Constraints Related to the Prefix Codes
5.4
F2MC-16LX Family
Constraints Related to the Prefix Codes
If a prefix code is placed before an instruction where interrupt and hold requests are
inhibited, the effect of the prefix code lasts until an instruction where neither an
interrupt nor hold request is inhibited appears for the first time, as shown in Figure 5.42.
If a prefix is followed by conflicting prefix codes, the last one is valid.
■ Relationships between Instructions Rejecting Interrupt Requests and Prefix Codes
The following 10 instructions/prefix codes reject interrupt and hold requests.
•
MOV ILM,#imm8
•
AND CCR,#imm8
•
OR CCR,#imm8
•
POPW PS
•
PCB
•
ADB
•
NCC
•
DTB
•
SPB
•
CMR
If an interrupt or hold request is issued during execution of any of the above instructions, the request is
accepted only after any instruction not listed above appears for the first time after that instruction and is
executed, as shown in Figure 5.4-1 .
Figure 5.4-1 Instructions Rejecting Interrupt and Hold Requests
Instructions rejecting interrupt and hold requests
••••••••
Interrupt request issued
(a)
•••
Interrupt accepted
(a):Ordinary instruction
If a prefix code is placed before an instruction rejecting interrupt and hold requests, its effect lasts until an
instruction other than instructions rejecting interrupt and hold requests appears for the first time after the
prefix code and is executed, as shown in Figure 5.4-2 .
Figure 5.4-2 Instructions Rejecting Interrupt and Hold Requests and Prefix Code
Instructions rejecting interrupt and hold requests
MOV A,FFH
NCC
CCR: XXX10XX
MOV ILM,#imm8
••••
ADD A,01H
CCR: XXX10XX
The NCC protects the
CCR from changing.
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CM44-00201-4E
CHAPTER 5 PREFIX CODES
F2MC-16LX Family
5.4 Constraints Related to the Prefix Codes
■ If Two or More Prefix Codes Appear in Succession
If a prefix is followed by conflicting prefix codes, the last one is valid (see Figure 5.4-3 ).
Figure 5.4-3 Consecutive Prefix Codes
Prefix codes
•••••
ADB
DTB
PCB
ADD A,01H
••••
The PCB prefix code is valid for this instruction.
The term "conflicting prefix codes" indicates PCB, ADB, DTB, and SPB in the above figure.
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CHAPTER 5 PREFIX CODES
5.4 Constraints Related to the Prefix Codes
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F2MC-16LX Family
CM44-00201-4E
CHAPTER 6
INTERRUPT HANDLING
This chapter describes the interrupt function and
operation.
6.1 Interrupt Handling
6.2 Hardware Interrupt Operation Flow
6.3 Interrupt Handling Flowchart and Saving the Contents of Registers
6.4 Interrupt Vectors
6.5 Extended Intelligent I/O Service
6.6 Interrupt Control Register (ICR)
6.7 Meanings of the Bits of Interrupt Control Register (ICR)
6.8 Extended Intelligent I/O Service Descriptor (ISD)
6.9 Registers of Extended Intelligent I/O Service Descriptor
6.10 Exception Processing
6.11 Interrupt Handling Program Example
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CHAPTER 6 INTERRUPT HANDLING
6.1 Interrupt Handling
6.1
F2MC-16LX Family
Interrupt Handling
In F2MC-16LX series, interrupt handling or extended intelligent I/O service is activated
by the interrupt request from an internal resource. For interrupt handling, the
processing appropriate to the interrupt request is performed by the interrupt handling
program. For extended intelligent I/O service, the data transfer between the requesting
internal resource and the memory is automatically performed. In addition, a function is
provided to stop the execution of the extended intelligent I/O service by the request
from the internal resource (such as built-in peripheral circuit).
■ Interrupt Handling
To permit an internal resource to make a hardware interrupt request to the CPU, an interrupt request flag
and an interrupt enable flag are required for that resource. The interrupt request flag is set by the
occurrence of an event specific to the internal resource. When the interrupt request flag indicates the
request being made and the interrupt enable flag is set to the enabled state, a hardware interrupt request is
issued from the internal resource.
In the case of the internal resource that requires the activation of the extended intelligent I/O service
accompanied by the occurrence of a hardware interrupt request, an extended intelligent I/O service enable
flag(ISE) is provided in the interrupt control register (ICR) in the interrupt controller associated with that
resource.
The occurrence of an interrupt request with the ISE flag set to "1" activates the extended intelligent I/O
service. If only normal hardware interrupt requests are intended, set the ISE flag to "0".
For interrupt requests by the execution of the INT instruction, which are software interrupts, no interrupt
request and enable flags are applied. Whenever the INT instruction is executed, an interrupt request occurs.
Any interrupt level of hardware interrupt request can be assigned to a given group regarding interrupt
request. Interrupt levels are specified by the interrupt level setting bits (IL0, IL1, and IL2) in the ICR
register in the interrupt controller. It is possible to specify eight interrupt level settings 0 to 7. Definition
of the interrupt levels is such that "0" is the highest and "6" is the lowest.
From a group set to interrupt level 7, no interrupt requests can be made. Hardware interrupt requests are
maskable (enabled/disabled) by the interrupt enable flag (I) in the condition code register (CCR) of the
processor status (PS) and the interrupt level mask (ILM).
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CHAPTER 6 INTERRUPT HANDLING
F2MC-16LX Family
6.1 Interrupt Handling
When an unmasked interrupt request occurs, the CPU takes the following actions:
(1) Saves the data (12 bytes) held by the following registers into the memory area indicated by the system
stack bank register (SSB) and the system stack pointer (SSP).
• Processor status (PS)
• Program counter (PC)
• Program counter bank register (PCB)
• Data bank register (DTB)
• Additional data bank register (ADB)
• Direct page register (DPR)
• Accumulator (A)
(2) Reads the interrupt vector in 3 bytes to PC and PCB.
(3) Updates the ILM register in the PS to the level setting value of the accepted interrupt request and sets
the S flag in the CCR register.
(4) Initiates the instruction execution, starting with the address indicated by the interrupt vector.
For the INT instruction, the ILM register is not updated and the interrupt enable flag (I) in the CCR register
is cleared. Subsequent interrupt requests are put to the pending state.
As a special case, hardware interrupt requests cannot be accepted during writing into an I/O area. This is
intended to avoid the CPU malfunction, which might otherwise be caused by the occurrence of an interrupt
request while the related data in the interrupt control registers for the resources are being rewritten.
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CHAPTER 6 INTERRUPT HANDLING
6.2 Hardware Interrupt Operation Flow
6.2
F2MC-16LX Family
Hardware Interrupt Operation Flow
Figure 6.2-1 shows the operation flow from the occurrence of a hardware interrupt
request until the interrupt request has been cleared and removed from within the
interrupt handling program.
■ Hardware Interrupt Operation Flow
Figure 6.2-1 From the Hardware Interrupt Occurrence to its Clearance
Register file
PS
Micro code
IR
F2MC-16 bus
ILM
I
Comparator
Check
(6)
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask
IR : Instruction register
(4)
(5)
F2MC-16LX CPU
(3)
AND
Source FF
(7)
(2)
(1)
Interrupt level IL
Enable FF
Level comparator
...
Peripheral
Interrupt
controller
Peripheral
(1) An interrupt source occurs within the peripheral.
(2) If the interrupt enable bit within the peripheral is referred and it indicates the interrupt enabled state, an
interrupt request is issued from the peripheral to the interrupt controller.
(3) The interrupt controller that has received that interrupt request determines the priority between the
requests made at the same time and transfers the interrupt level corresponding to the appropriate
interrupt to the CPU.
(4) The CPU compares the interrupt level requested by the interrupt controller with the IL bit held in the
processor status register.
(5) Only if the result of this comparison is that the interrupt level priority is higher than the current interrupt
handling level, the CPU checks the content of the interrupt enable flag (I) in the same processor status
register.
(6) Only if the result of the check in (5) is that the interrupt enable flag (I) is set in the interrupt enabled
state, the CPU sets the content of the IL bit to the requested level. Upon the completion of the ongoing
instruction execution, the CPU passes the control to the interrupt handling routine to initiate the
handling of that interrupt.
(7) When the software within the user’s interrupt handling routine clears the occurred interrupt cause as
mentioned in (1), this interrupt request process is terminated.
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CHAPTER 6 INTERRUPT HANDLING
6.3 Interrupt Handling Flowchart and Saving the Contents of Registers
F2MC-16LX Family
6.3
Interrupt Handling Flowchart and Saving the Contents of
Registers
Figure 6.3-1 shows the interrupt handling flowchart and Figure 6.3-2 shows how the
contents of the registers are saved with interrupt handling.
■ Interrupt Handling Flowchart
Figure 6.3-1 Interrupt Handling Flowchart
I:
ILM:
IF:
IE:
ISE:
IL:
S:
Interrupt enable flag
Interrupt level mask
Interrupt request by an internal resource
Interrupt enable flag for an internal resource
EI2OS enable flag
Interrupt request level of an internal resource
Stack flag
YES
I & IF & IE=1
AND
ILM > IL
NO
NO
YES
ISE=1
Fetch and decode next
instruction
Save the contents of PS, PC,
PCB, DTB, ADB, DPR, and A
into the SSP stack. Then, ILM=IL.
Perform extended intelligent
I/O service processing
YES
INT instruction
NO
Execute normal
instruction
NO
Stringprocessing
instruction repetition
completed
Save the contents of PS,
PC, PCB, DTB, ADB, DPR,
and A into the SSP stack.
Then, I = 0 and ILM = IL.
S←1
Fetch an interrupt vector
YES
Update PC
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CHAPTER 6 INTERRUPT HANDLING
6.3 Interrupt Handling Flowchart and Saving the Contents of Registers
F2MC-16LX Family
Figure 6.3-2 How the Contents of the Registers are Saved with Interrupt Handling
Word (16 bits)
MSB
LSB
H
← SSP (a value of SSP before the interrupt occurrence)
AH
AL
DPR
DTB
ADB
PCB
PC
PS
← SSP (a value of SSP after the interrupt occurrence)
L
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CHAPTER 6 INTERRUPT HANDLING
F2MC-16LX Family
6.4
Interrupt Vectors
6.4 Interrupt Vectors
Interrupt vectors are stored at addresses FFFC00H to FFFFFFH as shown in Table 6.4-1
Interrupt vectors share the same area for both hardware interrupt and software
interrupt.
■ Interrupt Vectors
Table 6.4-1 Interrupt Vectors
Interrupt
request
Vector address
L
Vector address
H
Vector address
bank
Mode register
INT0 *1
FFFFFCH
FFFFFDH
FFFFFEH
Not used
INT1 *1
FFFFF8H
FFFFF9H
FFFFFAH
Not used
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
INT7 *1
FFFFE0H
FFFFE1H
FFFFE2H
Not used
INT8 *2
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
INT10 *3
FFFFD4H
FFFFD5H
FFFFD6H
Not used
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
INT 254
FFFC00H
FFFC01H
FFFC02H
Not used
*1: Because the vector area for the CALLV instruction is also used as the vector area for INT #vct8 (#0 to #7) when the program counter
bank register (PCB) is FFH, care should be taken in using a vector for the CALLV instruction.
*2: It becomes a reset vector.
*3: It becomes a vector for exception processing.
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CHAPTER 6 INTERRUPT HANDLING
6.5 Extended Intelligent I/O Service
6.5
F2MC-16LX Family
Extended Intelligent I/O Service
The extended intelligent I/O service (EI2OS) is a function for automatic data transfer
between I/O and the memory. It enables the data transfer from/to I/O on a direct memory
access (DMA) basis, though this was performed by the interrupt handling program
before.
■ Overview of Extended Intelligent I/O Service
The extended intelligent I/O service is one type of hardware interrupt. This service achieves automatic data
transfer between I/O and the memory, enabling the data transfer from/to I/O on a DMA basis, though this
was formerly performed by the interrupt handling program. As compared with the method applied before
as part of interrupt handling, the following advantages are added:
• Because the part of the program coded for data transfer is no longer needed, the program size is reduced.
• It is unnecessary to save the contents of registers because the internal registers are not used for data
transfer, thus enhancing the transfer rate.
• Because the data transfer can be stopped according to the I/O status, unnecessary data transfer is
eliminated.
• Buffer addresses can be selected without the need of increments and update.
• I/O register addresses can be selected without the need of increments and update.
When the extended intelligent I/O service is terminated, it sets the end condition before the automatic
branch to the interrupt handling routine. This allows the user to know what the end condition was.
■ Structure of Extended Intelligent I/O Service
There are four functional entities below, which are related to the extended intelligent I/O service:
• Internal resource: Interrupt enable bit and interrupt request bit: Controls an interrupt request from a
resource.
• Interrupt controller: ICR: Assigns an interrupt level to each interrupt request, determines the priority
between the interrupts requested at the same time, and selects the operation
of EI2OS.
• CPU: I, ILM: Compares the requested interrupt level with the current level and verifies the interrupt
enabled state.
• RAM: Descriptor: Describes the transfer information of EI2OS.
Figure 6.5-1 shows the overview of extended intelligent I/O service.
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CHAPTER 6 INTERRUPT HANDLING
F2MC-16LX Family
6.5 Extended Intelligent I/O Service
Figure 6.5-1 Overview of Extended Intelligent I/O Service
Memory space
by IOA
Peripheral
I/O register
I/O register
CPU
Interrupt request
(3)
ISD
by ICS
(2)
(3)
(1)
Interrupt control
register
Interrupt controller
by BAP
(4)
Buffer
by DCT
(1) I/O requests data transfer.
(2) Interrupt controller selects the descriptor.
(3) Reads the transfer origin and destination from the descriptor.
(4) Data transfer between the I/O and the memory is performed.
Note:
Area that can be specified by the I/O register address pointer (IOA) is 000000H to 00FFFFH.
Area that can be specified by the buffer address pointer (BAP) is 000000H to 00FFFFH.
The maximum transfer count that can be specified by the data counter (DCT) is 65536.
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CHAPTER 6 INTERRUPT HANDLING
6.5 Extended Intelligent I/O Service
6.5.1
F2MC-16LX Family
Flowchart of Extended Iintelligent I/O Service Operation
Figure 6.5-2 shows the flowchart of extended intelligent I/O service operation.
■ Flowchart of Extended Intelligent I/O Service Operation
Figure 6.5-2 Extended Intelligent I/O Service Operation Flowchart
Interrupt request issued
from an internal resource
NO
ISE = 1
YES
Interrupt sequence
Read ISD/ISCS
End request
from the
resource
BAP: Buffer address pointer
IOA:
I/O register address pointer
ISD:
EI2OS descriptor
ISCS: EI2OS status
DCT: Data counter
ISE:
EI2OS enable bit
S1, S0: EI2OS end status
YES
SE = 1
NO
YES
DIR = 1
NO
Data indicated by IOA
↓ (Data transfer)
Memory indicated by BAP
YES
IF = 0
NO
The updated value
depends on BW.
Update IOA
YES
BF = 0
NO
Data indicated by BAP
↓ (Data transfer)
Data indicated by IOA
The updated value
depends on BW.
(−1)
Decrement DCT
DCT = 00
Update BAP
YES
NO
Set S1 and S0 to "00"
48
Set S1 and S0 to "01"
Set S1 and S0 to "11"
Clear the interrupt
request from the
resource
Clearing ISE to "0"
CPU operation recovery
Interrupt sequence
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CHAPTER 6 INTERRUPT HANDLING
6.5 Extended Intelligent I/O Service
F2MC-16LX Family
6.5.2
Flowchart of Extended Intelligent I/O Service Application
Procedure
Figure 6.5-3 shows the flowchart of extended intelligent I/O service (EI2OS) application
procedure.
■ Flowchart of Extended Intelligent I/O Service Application Procedure
Figure 6.5-3 Flowchart of Extended Intelligent I/O Service Application Procedure
Processing by CPU
Processing by EI2OS
EI2OS initialization
(Interrupt request) AND (ISE = 1)
Job execution
Reinitializing EI2OS
(Channel switch)
Normal termination
state
Data transfer
Count-out OR
Interrupt occurs by the end
request from a resource.
Processing the data in
the buffer
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CHAPTER 6 INTERRUPT HANDLING
6.6 Interrupt Control Register (ICR)
6.6
F2MC-16LX Family
Interrupt Control Register (ICR)
There are interrupt control registers (ICRs) in the interrupt controller. The number of
ICRs is equivalent to the number of all I/Os (internal resource I/Os) that have the
interrupt function.
■ Functions of Interrupt Control Registers (ICR0 to ICR15)
Each interrupt control register (ICR) has the following three functions:
• Sets the interrupt level of the associated internal resource.
• Selects either normal interrupt or extended intelligent I/O service to be executed for the interrupt request
from the associated internal resource.
• Selects the channel for extended intelligent I/O service.
Access to this register by read-modify-write instructions should not be performed, because it may cause
faulty operation.
■ Interrupt Control Register (ICR) Bit Configuration
Figure 6.6-1 shows the configuration of the bits of the interrupt control register (ICR).
Figure 6.6-1 Interrupt Control Register (ICR)
bit
7
6
ICS3
ICS2
W
W
5
4
ICS1/S1 ICS0/S0
R,W *
R,W *
3
2
1
0
ISE
IL2
IL1
IL0
R/W
R/W
R/W
R/W
00000111B when the
interrupt
control register (ICR) is reset.
* : ICS1 and ICS0 are available only for write (W), and S1 and S0 are available only for read (R).
Notes:
ICS3 to ICS0 are effective when the extended intelligent I/O service is activated. If the extended
intelligent I/O service is activated, set the ISE bit to "1". If not, set this bit to "0". Unless the
extended intelligent I/O service is activated, the settings of ICS3 to ICS0 may be omitted.
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CHAPTER 6 INTERRUPT HANDLING
6.7 Meanings of the Bits of Interrupt Control Register (ICR)
F2MC-16LX Family
6.7
Meanings of the Bits of Interrupt Control Register (ICR)
The meanings of the bits of the interrupt control register (ICR) are as follows:
• Extended intelligent I/O service channel selection bits (ICS0 to ICS3):
Any combination of these bits specifies a channel for extended intelligent I/O
service.
• Extended intelligent I/O service end status (S0, S1):
The combinations of S0 and S1 bits indicate the end conditions of the
extended intelligent I/O service.
• Extended intelligent I/O service enable bit (ISE):
This bit activates the extended intelligent I/O service.
• Interrupt level setting bits (IL0 to IL2):
Any combination of these bits sets an interrupt level.
■ Extended Intelligent I/O Service Channel Selection Bits (bit7 to bit4: ICS0 to ICS3)
These bits are used for write only and any combination of these bits specifies a channel for extended
intelligent I/O service. A value set by these bits determines the address in the memory of the extended
intelligent I/O service descriptor which is detailed later in this manual. All ICSs are initialized by reset.
Table 6.7-1 lists the correspondence between ICSs bits, the channel numbers, and descriptor addresses.
Table 6.7-1 Correspondence between ICS Bits, Channel Numbers, and Descriptor
Addresses
CM44-00201-4E
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
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CHAPTER 6 INTERRUPT HANDLING
6.7 Meanings of the Bits of Interrupt Control Register (ICR)
F2MC-16LX Family
■ Extended Intelligent I/O Service End Status (bit5, bit4: S0, S1)
These bits are used for read only. By checking a value set by these bits at the end of the extended
intelligent I/O service, you can know what the end condition was. After reset, any value becomes "00".
Table 6.7-2 shows the relationship between the S0 and S1 bit settings and the end conditions.
Table 6.7-2 Extended Intelligent I/O Service End Status Bits (S0 and S1) and End
Conditions
S1
S0
End condition
0
0
Reserved
0
1
End by count out
1
0
Reserved
1
1
End by the request from an internal resource
■ Extended Intelligent I/O Service Enable Bit (bit3: ISE)
This bit is read and write enabled. If an interrupt request occurs with this bit set to "1", the extended
intelligent I/O service is activated. If an interrupt request occurs with this bit set to "0", the interrupt
sequence is activated. Furthermore, when any end condition for the extended intelligent I/O service is met
(that is, S1 and S0 bits are other than "00"), the ISE bit is cleared. If the associated internal resource is not
provided with extended intelligent I/O service, the ISE bit must be set to "0" by software. The ISE bit is
initialized to "0" by reset.
■ Interrupt Level Setting Bits (bit2 to bit0: IL2 to IL0)
These bits are read and write enabled and any combination of these bits specifies an interrupt level of the
associated internal resource. The setting is initialized to level 7 (no interrupt) by reset. Table 6.7-3 shows
the relationship between the interrupt level setting bits and the interrupt levels.
Table 6.7-3 Interrupt Level Setting Bits and Associated Interrupt Levels
52
IL2
IL1
IL0
Level value
0
0
0
0 (Highest priority)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Lowest priority)
1
1
1
7 (No interrupt)
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CHAPTER 6 INTERRUPT HANDLING
6.8 Extended Intelligent I/O Service Descriptor (ISD)
F2MC-16LX Family
6.8
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor (ISD) is allocated to the area of 000100H
through 00017FH in the internal RAM. It consists of the followings:
•
•
•
•
Data counter
I/O register address pointer
Status data
Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 6.8-1 shows the configuration of the extended intelligent I/O service descriptor (ISD).
Figure 6.8-1 Configuration of Extended Intelligent I/O Service Descriptor
MSB
000100H + 8 × ICS
ISD start address
CM44-00201-4E
Upper 8 bits of data counter (DCTH)
Lower 8 bits of data counter (DCTL)
Upper 8 bits of I/O register address pointer (IOAH)
Lower 8 bits of I/O register address pointer (IOAL)
EI2OS status (ISCS)
Upper 8 bits of buffer address pointer (BAPH)
Medium 8 bits of buffer address pointer (BAPM)
Lower 8 bits of buffer address pointer (BAPL)
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LSB
H
L
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CHAPTER 6 INTERRUPT HANDLING
6.9 Registers of Extended Intelligent I/O Service Descriptor
6.9
F2MC-16LX Family
Registers of Extended Intelligent I/O Service Descriptor
The extended intelligent I/O service descriptor (ISD) consists of the following registers:
• Buffer address pointer (BAP)
• Extended intelligent I/O service status register (ISCS)
• I/O register address pointer (IOA)
• Data counter (DCT)
Note that these registers are undefined when reset.
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register that holds an address to be used in the next transfer by
extended intelligent I/O service. An independent buffer address pointer (BAP) exists for each extended
intelligent I/O service channel. Thus, data transfer on each extended intelligent I/O service channel is
possible between an arbitrary address among 16 Mbytes and I/O.
Note:
If the BF bit in the extended intelligent I/O service status register (ISCS) indicates "update enabled",
only the lower 16 bits of BAP (BAPM, BAPL) will change, but the upper 8 bits (BAPH) will not
change.
■ Extended Intelligent I/O Service Status Register (ISCS)
The extended intelligent I/O service status register (ISCS) is a register of 8-bit length. It indicates whether
the value is updated or fixed and incremental or decremental update is enabled regarding the buffer address
pointer and the I/O register address pointer. In addition, it indicates the data format (byte/word) for transfer
and the transfer direction. Figure 6.9-1 shows the configuration of the extended intelligent I/O service
status register (ISCS).
Figure 6.9-1 Configuration of Extended Intelligent I/O Service Status Register (ISCS)
bit
7
6
5
Reserved Reserved Reserved
4
3
2
1
0
IF
BW
BF
DIR
SE
: ISCS (undefined when reset)
Note: ISCS bit7 to bit5 must be coded with "0".
The contents of the bits of the ISCS register are as follows:
● bit4 (IF): Specifies whether the I/O register address pointer is updated or fixed.
• 0: The I/O register address pointer is updated after the data transfer.
• 1: The I/O register address pointer is not updated after the data transfer.
Note: Only increment is enabled.
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CHAPTER 6 INTERRUPT HANDLING
F2MC-16LX Family
6.9 Registers of Extended Intelligent I/O Service Descriptor
● bit3 (BW): Specifies the data length for transfer.
• 0: Byte
• 1: Word
● bit2 (BF): Indicates whether the buffer address pointer is updated or fixed.
• 0: The buffer address pointer is updated after the data transfer.
• 1: The buffer address pointer is not updated after the data transfer.
Note: If updated, only the lower 16 bits of the buffer address pointer will change. Only increment is
enabled.
● bit1 (DIR): Specifies the data transfer direction.
• 0: I/O register address pointer (IOA) → Buffer address pointer (BAP)
• 1: Buffer address pointer(BAP) → I/O register address pointer (IOA)
● bit0 (SE): Controls the termination of the extended intelligent I/O service by the request from an
internal resource.
• 0: Does not terminate the extended intelligent I/O service by the request from an internal resource.
• 1: Terminates the extended intelligent I/O service by the request from an internal resource.
■ I/O Register Address Pointer (IOA)
The I/O register address pointer (IOA) is a register of 16-bit length. It indicates the lower digits of the
address (A15 to A0) of the I/O register that transfers data between itself and the buffer. Upper positions of
the address (A23 to A16) are coded with 00H, and an arbitrary I/O address from 000000H to 00FFFFH can
be specified in the upper positions.
Figure 6.9-2 shows the configuration of the I/O register address pointer (IOA).
Figure 6.9-2 Configuration of I/O Register Address Pointer (IOA)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 : IOA (undefined when reset)
■ Data Counter (DCT)
The data counter (DCT) is a register of 16-bit length and holds the data count for transfer. Before each data
is transferred, this counter is decremented by one. When this counter value becomes 0000H, the extended
intelligent I/O service is terminated.
Figure 6.9-3 shows the configuration of the data counter.
Figure 6.9-3 Configuration of Data Counter (DCT)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 : DCT (undefined when reset)
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CHAPTER 6 INTERRUPT HANDLING
6.10 Exception Processing
6.10
F2MC-16LX Family
Exception Processing
Exception processing is basically the same as interrupts. Upon the detection of an
exceptional event on a boundary between instructions, exception processing is
performed apart from normal execution. Generally, exception processing occurs as a
result of an unexpected action. Thus, it is recommended to use the exception
processing feature only for debugging purposes or reactivating the software for
recovery in case of emergency.
■ Exception Occurrence because of the Execution of an Undefined Instruction
F2MC-16LX handles all codes that have not been defined in the instruction map as undefined instructions.
If an undefined instruction is executed, F2MC-16LX performs a processing similar to "INT10" which is a
software interrupt instruction. That is, the execution branches to a routine indicated by the interrupt
number 10 vector, after the contents of the following eight components are saved into the system stack:
• Lower word of accumulator (AL)
• Upper word of accumulator (AH)
• Direct page register (DPR)
• Data bank register (DTB)
• Additional data bank register (ADB)
• Program counter bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Then, F2MC-16LX clears the interrupt enable flag (I) and sets the stack flag (S). The value of PC saved
into the stack is that address of the location where the undefined instruction is stored. For 2-byte or longer
instruction codes, it is that address of the location where the code identified as being undefined is stored. It
is possible to make recovery by the RETI instruction, but the same exception recurs, so there is no point in
making such recovery.
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CHAPTER 6 INTERRUPT HANDLING
6.11
F2MC-16LX Family
6.11
Interrupt Handling Program Example
Interrupt Handling Program Example
The following shows an interrupt handling program example.
■ Interrupt Handling Program Example
● Processing specifications
The following shows an example of an interrupt program using external interrupt 0 (INT0).
● Coding example
DDR6
EQU
000016H
; Port 6 direction register
ENIR
EQU
00003CH
; Interrupt/DTP enable register
EIRR
EQU
00003DH
; Interrupt/DTP factor register
ELVR
EQU
00003EH
; Request level setting register
ICR03
EQU
0000B3H
; Interrupt control register 03
STACK
SSEG
RW
100
STACK_T
RW
STACK
ENDS
; Stack
1
;---------- Main program -----------------------------------------------------------CODE
CSEG ;
START:
MOV
RP, #0
; A general-purpose register uses the head bank
MOV
ILM, #07H
; Sets ILM in PS to level 7
MOV
A, #!STACK_T
; System stack setting
MOV
SSB, A
MOVW A, #STACK_T
; Stack pointer setting
MOVW SP, A
; Set to SSP because the S flag is set to "1"
MOV
DDR6, #00000000B
; Sets the P60/INT0 pin as the input.
OR
CCR, #40H
; Sets the I flag of CCR in PS to specify the interrupt
enable state
MOV
I:ICR03, #00H
; Sets the interrupt level to "0" (highest)
MOV
I:ELVR, #00000001B
; Sets INT0 to the "H" level request
MOV
I:EIRR, #00H
; Clears an INT0 interrupt factor
MOV
I:ENIR, #01H
; Enables the INT0 input
:
LOOP:
NOP
; Dummy loop
NOP
NOP
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CHAPTER 6 INTERRUPT HANDLING
6.11 Interrupt Handling Program Example
F2MC-16LX Family
NOP
BRA
LOOP
; Unconditional jump
;---------- Interrupt program -----------------------------------------------------------ED_INT1:
MOV
I:EIRR, #00H
; Disables the acceptance of a new INT0
NOP
NOP
NOP
NOP
NOP
NOP
RETI
CODE
; Returns from an interrupt
ENDS
;---------- Vector setting -----------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFB4H
DSL
ED_INT1
ORG
0FFDCH
DSL
START
DB
00H
; Sets a vector to interrupt #18 (12H)
; Reset vector setting
; Sets to the single chip mode
ENDS
END
START
● Processing specifications for program example of extended intelligent I/O service (EI2OS)
1. Detect the "H" level of the signal input to the INT0 pin, and start the extended intelligent I/O service
(EI2OS).
2. When the "H" level is input to the INT0 pin, EI2OS starts, and data of port 0 is transferred to address
3000H in memory.
3. The number of transferred data bytes is 100. After the 100-byte transfer has been completed, EI2OS
transfer processing terminates, and an interrupt occurs.
● Coding example
58
DDR6
EQU
000016H
; Port 6 direction register
ENIR
EQU
00003CH
; Interrupt/DTP enable register
EIRR
EQU
00003DH
; Interrupt/DTP factor register
ELVR
EQU
00003EH
; Request level setting register
ICR03
EQU
0000B3H
; Interrupt control register 03
BAPL
EQU
000100H
; Low order of buffer address pointer
BAPM
EQU
000101H
; Medium order of buffer address pointer
BAPH
EQU
000102H
; Upper order of buffer address pointer
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 6 INTERRUPT HANDLING
F2MC-16LX Family
6.11 Interrupt Handling Program Example
ISCS
EQU
000103H
; EI2OS status
IOAL
EQU
000104H
; Low order of I/O address pointer
IOAH
EQU
000105H
; Upper order of I/O address pointer
DCTL
EQU
000106H
; Low order of data counter
DCTH
EQU
000107H
; Upper order of data counter
ER0
EQU
EIRR:0
; Defines the external interrupt request flag bit
STACK
SSEG
; Stack
RW
100
STACK_T
RW
1
STACK
ENDS
;---------- Main program -----------------------------------------------------------CODE
CSEG
START:
AND
CCR, #0BFH
; Clears the I flag of CCR in PS to specify the interrupt
disable state
MOV
RP, #00
; Sets the register bank pointer
MOV
A, #!STACK_T
; System stack setting
MOV
SSB, A
MOVW A, #STACK_T
; Stack pointer setting
MOVW SP, A
; Set to SSP because the S flag is set to "1"
MOV
I:DDR6, #00000000B
; Sets the P60/INT0 pin as the input
MOV
BAPL, #00H
; Sets the buffer address (003000H)
MOV
BAPM, #30H
MOV
BAPH, #00H
MOV
ISCS, #00010001B
; Does not update the I/O address
Updates the byte transfer and the buffer address
; I/O → Transferred to buffer; ended by a peripheral
function in some cases
CM44-00201-4E
MOV
IOAL, #00H
; Sets the transfer source address (port 0:000000H)
MOV
IOAH, #00H
MOV
DCTL, #64H
MOV
DCTH, #00H
MOV
I:ICR00, #00001000B ; EI2OS ch.0, EI2OS enable, Interrupt level 0 (Highest)
MOV
I:ELVR, #00000001B
; Sets INT0 to the "H" level request
MOV
I:EIRR, #00H
; Clears an INT0 interrupt factor
MOV
I:ENIR, #01H
; Enables the INT0 input
MOV
ILM, #07H
; Sets ILM in PS to level 7
OR
CCR, #40H
; Sets the I flag of CCR in PS to specify the interrupt
enable state
; Sets the number of transferred bytes (100 bytes)
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CHAPTER 6 INTERRUPT HANDLING
6.11 Interrupt Handling Program Example
F2MC-16LX Family
:
LOOP:
BRA
LOOP
; Infinite loop
;---------- Interrupt program -----------------------------------------------------------WARI
CLRB
ER0
; Clears the interrupt/DTP request flag
:
User processing
; Check the factor that has caused EI2OS to terminate
; processing, buffer data processing, EI2OS resetting,
and other handling
:
RETI
CODE
ENDS
---------- Vector setting ------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFB4H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
; Reset vector setting
; Sets to the single chip mode
ENDS
END
60
; Sets a vector to interrupt #18 (12H)
START
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 7
ADDRESSING
This chapter describes addressing in each instructions.
Addressing specifies the data to be used and an address.
In F2MC-16LX, effective addressing or an used instruction
code determines the address format (absolute address
or relative address). When the address format is determined
by the instruction code itself, an address must be specified
in compliance with the used instruction code.
Some instructions enable several types of addressing to
be specified.
7.1 Effective Address Field
7.2 Direct Addressing
7.3 Indirect Addressing
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CHAPTER 7 ADDRESSING
7.1 Effective Address Field
7.1
F2MC-16LX Family
Effective Address Field
Table 7.1-1 lists the address formats that may be specified in the effective address field.
■ Effective Address Field
Table 7.1-1 Effective Address Field
Code
00
01
02
03
04
05
06
07
62
Coding
R0
R1
R2
R3
R4
R5
R6
R7
Address format
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
10
11
12
13
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
14
15
16
17
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
18
19
1A
1B
1C
1D
1E
1F
Default bank
Register direct
* : The general-purpose register names in the
Coding column correspond to the Byte,
Word, and Long-word types in sequence
from the left.
None
Register indirect
DTB
DTB
ADB
SPB
Register indirect with post-increment
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit displacement
DTB
DTB
ADB
SPB
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
DTB
DTB
PCB
DTB
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CM44-00201-4E
CHAPTER 7 ADDRESSING
F2MC-16LX Family
7.2
Direct Addressing
7.2 Direct Addressing
In direct addressing, a value, register, and address must be directly specified for the
operands.
■ Direct Addressing
● Immediate data (#imm)
Directly specify an operand value. There are four types of immediate data according to data length as
below:
• #imm4
• #imm8
• #imm16
• #imm32
● Register direct
Directly specify a register for the operand. Registers that can be specified are as below:
• General-purpose registers
(Byte):
R0, R1, R2, R3, R4, R5, R6, R7
(Word):
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
(Long word): RL0, RL1, RL2, RL3
• Dedicated registers
(Accumulator): A, AL
(Pointer):
SP *
(Bank):
PCB, DTB, USB, SSB, ADB
(Page):
DPR
(Control):
PS, CCR, RP, ILM
*: For SP, either user stack pointer (USP) or system stack pointer (SSP) is selected for use, according to
the value of the stack flag (S) in the condition code register (CCR). For branch instructions, program
counter (PC) is not described in the operand of the instruction, but it is automatically specified.
● Direct branch address (addr16)
Directly specify an address to which the execution will branch by means of displacement. The address
length with displacement is 16 bits and the address indicates the destination of the branch in the logical
space. This addressing is applied to an unconditional branch instruction and a subroutine call instruction.
bits 16 to 23 of the address are given by the program counter bank register (PCB).
● Physical direct branch address (addr24)
Directly specify a physical address to which the execution will branch by means of displacement. The data
length with displacement is 24 bits. This addressing is applied to an unconditional branch instruction, a
subroutine call instruction, and a software interrupt instruction.
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CHAPTER 7 ADDRESSING
7.2 Direct Addressing
F2MC-16LX Family
● I/O direct (io)
Directly specify a memory address in the operand by means of 8-bit displacement. Independently of the
respective values for data bank register (DTB) and direct page register (DPR), the I/O space with physical
addresses 000000H to 0000FFH is accessible. It is invalid to describe the bank select prefix to specify a
bank before an instruction using this addressing.
● Abbreviated direct address (dir)
Specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are given by the
direct page register (DPR). Bits 16 to 23 of the address are given by the data bank register (DTB).
● Direct address (addr16)
Specify lower 16 bits of a memory address in the operand. Bits 16 to 23 of the address are given by the
data bank register (DTB).
● I/O direct bit address (io:bp)
Directly specify a bit within the range of physical addresses 000000H to 0000FFH. Bit position is
represented by :bp. The higher number is the most significant bit and the lower number is the least
significant bit.
● Abbreviated direct bit address (dir:bp)
Directly specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are given
by the direct page register (DPR). Bits 16 to 23 of the address are given by the data bank register (DTB).
Bit position is represented by :bp. The higher number is the most significant bit and the lower number is
the least significant bit.
● Direct bit address (addr16:bp)
Directly specify an arbitrary bit within 64 Kbytes. Bits 16 to 23 of the address are given by the data bank
register (DTB). Bit position is represented by :bp. The higher number is the most significant bit and the
lower number is the least significant bit.
● Vector address (#vct)
The address to which the execution will branch is determined by the content of the vector that is specified
herein. The vector number data length may be either four bits or eight bits. This addressing is applied to a
subroutine call instruction and a software interrupt instruction.
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CM44-00201-4E
CHAPTER 7 ADDRESSING
F2MC-16LX Family
7.3
Indirect Addressing
7.3 Indirect Addressing
In indirect addressing, the data indicated by the operand you coded indirectly gives an
address.
■ Indirect Addressing
● Register indirect (@RWj j = 0 to 3)
The register indirect addressing is used to access a memory location whose address is specified by the
content of general-purpose register RWj. Bits 16 to 23 of the address are given by the data bank register
(DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the additional data bank register
(ADB) if RW2 is used.
● Register indirect with post-increment (@RWj+ j = 0 to 3)
This addressing is also used to access a memory location whose address is specified by the content of
general-purpose register RWj. After the execution of the operand operation, RWj is incremented by the
operand data length (1 for byte, 2 for word, and 4 for long word). Bits 16 to 23 of the address are given by
the data bank register (DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the additional
data bank register (ADB) if RW2 is used.
If the value resulting from post-increment indicates the address of the increment-specified register itself,
the value of this register is incremented when referred subsequently. Then, if a data write instruction is
issued to the register, the priority is given to the data write instruction, so that the register value, which
would otherwise be incremented, becomes the written data.
● Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)
This addressing is used to access a memory location whose address is specified by the displacement added
to the content of general-purpose register RWj. Displacement may be either byte or word and is added as a
signed value. Bits 16 to 23 of the address are given by the data bank register (DTB) if RW0, RW1, RW4,
and RW5 are used. Bits 16 to 23 are given by the SPB if RW3 and RW7 and by the additional data bank
register (ADB) if RW2 and RW6 are used.
● Long register indirect with displacement (@RLi+disp8 i = 0 to 3)
This addressing is used to access a memory location whose address is specified by the lower 24 bits that
result from the displacement added to the content of general-purpose register RLi. Displacement is eight
bits and added as a signed value.
● Program counter indirect with displacement (@PC+disp16)
This addressing is used to access a memory location whose address is specified by (address of instruction +
4 + disp16). Displacement is a word length. Bits 16 to 23 of the address are given by the program counter
bank register (PCB).
Note that respective operand addresses of the instructions listed next are not regarded as being (next
instruction address + disp16):
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CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
• DBNZ
F2MC-16LX Family
eam, rel
• DWBNQ eam, rel
• CBNE
eam, #imm8, rel
• CWBNE eam, #imml16, rel
• MOV
eam, #imm8
• MOVM
eam, #imm16
● Register indirect with base index (@RW0+RW7, @RW1+RW7)
This addressing is used to access a memory location whose address is specified by a value obtained by
adding the content of RW0 or RW1 to the content of general-purpose register RW7. Bits 16 to 23 of the
address are given by the data bank register (DTB).
● Program counter relative branch address (rel)
The address to which the execution will branch is determined by a value obtained by adding the 8-bit
displacement to the value of the program counter (PC). If the result of the addition exceeds 16 bits, the
bank register is not incremented or decremented and the part of excess is ignored. Consequently, the
address falls within the closed bank of 64 Kbytes. This addressing is applied to an unconditional or
conditional branch instruction. Bits 16 to 23 of the address are given by the program counter bank register
(PCB).
● Register List (rlst)
This addressing specifies a register subjected to push/pop for the stack (see Figure 7.3-1 ).
Figure 7.3-1 Configuration of Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
When the bit is "1", the associated register is selected. When the bit is "0",
the associated register is not selected.
● Accumulator indirect (@A)
This addressing is used to access a memory location whose address is specified by the 16-bit content of the
low-order word of the accumulator (AL). Bits 16 to 23 of the address are given by the data bank register
(DTB).
● Accumulator indirect branch address (@A)
The address to which the execution will branch is determined by the 16-bit content for the low-order word
of the accumulator (AL). This address indicates the destination of the branch within the bank space. Bits
16 to 23 of the address are given by the program counter bank register (PCB). In the case of the jump
context (JCTX) instruction, however, bits 16 to 23 of the address are given by the data bank register (DTB).
This addressing is applied to an unconditional branch instruction.
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CHAPTER 7 ADDRESSING
F2MC-16LX Family
7.3 Indirect Addressing
● Indirectly specified branch address (@ear)
The word data with the address specified by ear corresponds to the address to which the execution will
branch.
● Indirectly specified branch address (@eam)
The word data with the address specified by eam corresponds to the address to which the execution will
branch.
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CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
68
F2MC-16LX Family
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 8
INSTRUCTION OVERVIEW
This chapter provides explanation for the items
described in "CHAPTER 9 DETAILED EXECUTION
INSTRUCTIONS" and what the symbols used therein
stand for.
8.1 Instruction Overview
8.2 Symbols (Abbreviations) Used in Detailed Execution Instructions
8.3 Effective Address Field
8.4 Execution Cycles
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CHAPTER 8 INSTRUCTION OVERVIEW
8.1 Instruction Overview
8.1
F2MC-16LX Family
Instruction Overview
In "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS" the following items are
described for each instruction.
• Assembler format
• Execution cycles
• Operation
• Correction value
• CCR
• Example
• Byte count
■ Instruction Overview
In "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS" the following items are described for each
instruction.
● Assembler format
The format for coding each instruction into an assembler source program is presented.
• Upper case letters and symbols: Write them as they are into a source program.
• Lower case letters:
Rewrite them into a source program.
• Number after a lower case letter: Indicates a bit width in the instruction.
● Operation
The operation for registers and data by instruction execution is presented.
● CCR
The status of each flag (I, S, T, N, Z, V and C) of the condition code register (CCR) is presented.
• *: Denotes that the flag changes with the instruction execution.
• –: Denotes that the flag does not change.
• S: Denotes that the flag is set with the instruction execution.
• R: Denotes that the flag is clear with the instruction execution.
● Byte count
The byte count of the instruction (machine language) after assembled is presented.
● Execution cycles
The number of instruction execution cycles is presented.
For the meaning of the letter symbol used in the table, which is presented for description of execution
cycles, see Table 8.4-1 .
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CHAPTER 8 INSTRUCTION OVERVIEW
F2MC-16LX Family
8.1 Instruction Overview
● Correction value
A correction value used for calculating the number of instruction execution cycles is presented. For the
meanings of the letter symbols ((b), (c), and (d)) used in the table, which is presented for description of
correction values, see Table 8.4-2 . The number of instruction execution cycles is determined by the sum of
a value given in the column of execution cycles and a value given in the column of correction value.
● Example
An example of each instruction is presented.
All numeric values of the data given in any example are hexadecimal numbers. Any numeric value of the
data given in the operand represents a hexadecimal number with suffix (H).
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CHAPTER 8 INSTRUCTION OVERVIEW
8.2 Symbols (Abbreviations) Used in Detailed Execution Instructions
8.2
F2MC-16LX Family
Symbols (Abbreviations) Used in Detailed Execution
Instructions
Table 8.2-1 lists the symbols used in detailed execution instruction.
■ Symbols (abbreviations) Used in Detailed Execution Instructions
Table 8.2-1 Symbols (abbreviations) Used in Detailed Execution Instructions (1 / 2)
Coding
A
32-bit accumulator
The length of used bits varies depending on the instruction.
Byte:
Lower 8 bits of AL
Word:
16 bits of AL
Long word: 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
addr24
ad24 0-15
ad24 16-23
io
imm4
imm8
imm16
imm32
ext (imm8)
72
Meaning
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data resulting from the signed extension of 8-bit immediate data
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 8 INSTRUCTION OVERVIEW
F2MC-16LX Family
8.2 Symbols (Abbreviations) Used in Detailed Execution Instructions
Table 8.2-1 Symbols (abbreviations) Used in Detailed Execution Instructions (2 / 2)
Coding
disp8
disp16
bp
vct4
vct8
(
CM44-00201-4E
)b
Meaning
8-bit displacement
16-bit displacement
Bit offset value
Vector number (0 to 15)
Vector number (0 to 255)
Bit address
re1
Specifies a PC relative branch.
ear
eam
Effective addressing (codes 00H to 07H)
Effective addressing (codes 08H to 1FH)
r1st
Register list
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CHAPTER 8 INSTRUCTION OVERVIEW
8.3 Effective Address Field
8.3
F2MC-16LX Family
Effective Address Field
Table 8.3-1 lists the address formats that may be specified in the effective address field.
■ Effective Address Field
Table 8.3-1 Effective Address Field
Code
00
01
02
03
04
05
06
07
Coding
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Byte count of address
extension *
Register direct
* : The general-purpose register names in
the Coding column correspond to the
Byte, Word, and Long-word types in
sequence from the left.
-
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
0
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit displacement
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*: The byte count of address extension corresponds to "#" (byte count) shown in the instruction list and "+" shown in the byte count field of
each detailed instruction.
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CHAPTER 8 INSTRUCTION OVERVIEW
F2MC-16LX Family
8.4
Execution Cycles
8.4 Execution Cycles
The number of cycles required for the execution of an instruction (execution cycles) is
obtained by adding a "correction value", which is determined according to the
condition, to the number of "cycles" specific to each instruction. However, actual
instruction execution cycles may include the cycles required for reading the program in
addition to the sum of "cycles" and a "correction value".
■ Execution Cycles
The number of cycles required for the execution of an instruction is obtained by adding up the number of
"cycles" specific to each instruction, a "correction value", which is determined according to the condition,
and "cycles" required for program fetch.
When fetching a program stored in a memory connected to a 16-bit bus, such as built-in ROM, program
fetch is performed each time the instruction under execution passes over a 2-byte (word) boundary. If data
access interference occurs, it results in an increasing number of execution cycles.
When fetching a program stored in a memory connected to an 8-bit bus, which is an external data bus,
program fetch is performed per byte in the instruction under execution. If data access interference occurs,
it results in an increasing number of execution cycles.
During CPU intermittent operation, the access to a general-purpose register, built-in ROM, built-in RAM,
built-in I/O or external bus causes the CPU clock to make a halt for a certain time. This CPU halt time is
equivalent to the number of cycles specified by the CG1/CG0 bit of the low power consumption mode
control register. Therefore, the number of cycles required for the execution of an instruction during the
CPU intermittent operation should be calculated differently. That is, add "a correction value" determined
by "the number of times for access" × "cycles" for the CPU halt time to normal execution cycles.
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CHAPTER 8 INSTRUCTION OVERVIEW
8.4 Execution Cycles
F2MC-16LX Family
■ Calculating Execution Cycles
Table 8.4-1 , Table 8.4-2 , and Table 8.4-3 provide the referenced information which may help you to
calculate instruction execution cycles.
Table 8.4-1 Execution Cycles Specific to Each Addressing Method of an Effective Address
(a) *
Number of times of register access
specific to each addressing method
Code
Operand
00
to
07
08
to
0B
0C
to
0F
10
to
17
18
to
1B
1C
1D
1E
1F
Ri
RWi
RLi
Presented in the instruction list.
@RWj
2
1
@RWj +
4
2
@RWi + disp8
2
1
@RWj +
disp16
2
1
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Execution cycles specific to
each addressing method
Presented in the instruction list.
*: (a) is used in "~" (cycles) and "B" (correction value) in "APPENDIX B F2MC-16LX Instruction Lists (351
Instructions)" as well as "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Table 8.4-2 Correction Values for Cycles Used for Calculating Actual Execution Cycles
(b) * byte
Operand
Internal register
Internal memory even address
Internal memory odd address
External data bus 16-bit even
address
External data bus 16-bit odd
address
External data bus 8-bit
(c) * word
(d) * long
The
number of
cycles
The
number of
times of
access
The
number of
cycles
The
number of
times of
access
The
number of
cycles
The
number of
times of
access
+0
1
+0
1
+0
2
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
+1
1
+1
1
+2
2
+1
1
+4
2
+8
4
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used in "~" (cycles) and "B" (correction value) in "APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)"
as well as "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Note: For the application to external buses, the wait cycles for ready input and automatic ready must be added.
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CHAPTER 8 INSTRUCTION OVERVIEW
F2MC-16LX Family
8.4 Execution Cycles
Table 8.4-3 Correction Values for Cycles Used for Calculating Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
–
+2
External data bus 16-bit
–
+3
External data bus 8-bit
+3
–
Notes: • For the application to external buses, the wait cycles for ready input and automatic ready must
be added.
• Actually, all program fetches do not always cause the delay for the execution of an instruction.
Thus, these correction values should be used to calculate the required execution cycles in the
worst case.
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CHAPTER 8 INSTRUCTION OVERVIEW
8.4 Execution Cycles
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F2MC-16LX Family
CM44-00201-4E
CHAPTER 9
DETAILED EXECUTION
INSTRUCTIONS
This chapter explains each of the execution instructions
used by the assembler, in reference format. The
execution instructions are presented in alphabetical
order.
9.1 Detailed Execution Instructions
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1
F2MC-16LX Family
Detailed Execution Instructions
This section explains each of the execution instructions used by the assembler, in
reference format. The execution instructions are presented in alphabetical order.
■ Reading Detailed Execution Instructions
For an explanation of each of the items and symbols (abbreviations) used in the explanation of each
execution instruction, see "CHAPTER 8 INSTRUCTION OVERVIEW".
For an explanation of the alphabetical characters (a), (b), (c), and (d) used in an explanation (table) of
correction values and numbers of cycles, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.1
ADD (Add Byte Data of Destination and Source to
Destination)
Add the byte data specified by the second operand to the byte data specified by the first
operand and store the result in the first operand. If the first operand is the accumulator
(A), 00H are transferred to bits 8 to 15 of A.
■ ADD (Add Byte Data of Destination and Source to Destination)
● Assembler format:
ADD A,#imm8
ADD A,dir
ADD A,ear
ADD A,eam
ADD ear,A
ADD eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
[Byte addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
ear
eam
Second operand
#imm8
dir
ear
eam
A
A
Number of bytes
2
2
2
2+
2
2+
Number of cycles
2
3
3
4+(a)
3
5+(a)
Correction value
0
(b)
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
ADD A,0E021H
In this example, byte data (ABH) at address E021H is added to low-order byte data (46H) of AL.
A
AH
AL
×× ××
A0 46
CCR
×××××
A
AH
AL
×× ××
00 F1
CCR
A B
Memory
E021
Before execution
82
1 0 0 0
T N Z V C
T N Z V C
Memory
×
A B
E021
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.2
ADDC (Add Byte Data of AL and AH with Carry to AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C) together
and restore the result in AL. 00H are transferred to the high-order byte of AL.
■ ADDC (Add Byte Data of AL and AH with Carry to AL)
● Assembler format:
ADDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
[Byte addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ADDC A
In this example, low-order byte data (D4H) of AL and the C flag ("0") are added to low-order byte data
(05H) of AH.
A
AH
AL
05 05
00 D4
CCR
××××
A
0
AH
AL
05 05
00 D9
CCR
T N Z V C
Before execution
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×
1 0 0 0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.3
F2MC-16LX Family
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)
Add the least significant byte data of the accumulator (A), byte data at the effective
address, and carry flag (C) together and restore the result in the least significant byte of
A. 00H are transferred to bits 8 to 15 of A.
■ ADDC (Add Byte Data of Accumulator and Effective Address with Carry to
Accumulator)
● Assembler format:
ADDC
A, ear
ADDC
A, eam
●Operation:
(A) ← (A)+(ea)+(C)
[Byte addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Number of accesses
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ADDC
A, 0E035H
In this example, byte data (D5H) at address E035H and the C flag ("1") are added to low-order byte data
(46H) of AL.
A
AH
AL
×× ××
A0 46
CCR
××××
A
1
AH
AL
×× ××
00 2C
CCR
T N Z V C
Memory
D 5
0 0 0 1
T N Z V C
Memory
E035
Before execution
CM44-00201-4E
×
D 5
E035
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.4
F2MC-16LX Family
ADDCW (Add Word Data of Accumulator and Effective
Address with Carry to Accumulator)
Add the low-order word data (AL) of the accumulator (A), word data specified by the
second operand, and carry flag (C) together and restore the result in the low-order word
of A.
■ ADDCW (Add Word Data of Accumulator and Effective Address with Carry to
Accumulator)
● Assembler format:
ADDCW
A, ear
ADDCW
A, eam
● Operation:
(A) ← (A)+(ea)+(C)
[Word addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ADDCW A,@RW0+
In this example, word data (8952H) at address (E024H) specified in the second operand (@RW0+) and the
C flag ("1") are added to word data (2068H) of AL.
A
RW0
AH
AL
×× ××
20 68
CCR
E0 24
××××
A
1
RW0
AH
AL
×× ××
A9 BB
CCR
E0 26
T N Z V C
Memory
8
5
9
2
1 0 0 0
T N Z V C
Memory
E025
E024
Before execution
CM44-00201-4E
×
8
5
9
2
E025
E024
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.5
F2MC-16LX Family
ADDDC (Add Decimal Data of AL and AH with Carry to
AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C) together
in decimal and restore the result in the low-order byte of AL. 00H are transferred to the
high-order byte of AL.
■ ADDDC (Add Decimal Data of AL and AH with Carry to AL)
● Assembler format:
ADDDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
[Decimal addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Undefined
C:
Set when a carry has occurred as a result of the decimal operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
ADDDC A
In this example, low-order byte data (58H) of AH and the C flag ("0") are added to low-order byte data
(62H) of AL in decimal.
AH
A
××
AL
××
62
CCR
AH
58
××××
A
0
××
AL
62
CCR
T N Z V C
Before execution
88
00 20
×
0 0
×
1
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.6
ADDL (Add Long Word Data of Destination and Source to
Destination)
Add the long word data specified by the second operand to the long word data specified
by the first operand and restore the result in the first operand.
■ ADDL (Add Long Word Data of Destination and Source to Destination)
● Assembler format:
ADDL A,#imm32
ADDL A,ear
ADDL A,eam
● Operation:
(First operand) ← (First operand)+(Second operand)
[Long word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#imm32
ear
eam
Number of bytes
5
2
2+
Number of cycles
4
6
7+(a)
Correction value
0
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
ADDL A,0E077H
In this example, long word data (357F41ABH) at address E077H is added to long word data (85B7A073H)
of accumulator (A).
A
AH
AL
85 B7
A0 73
CCR
A
AH
AL
BB 36
E2 1E
×××××
CCR
Memory
Memory
5
F
1
B
E07A
E079
E078
E077
Before execution
90
1 0 0 0
T N Z V C
T N Z V C
3
7
4
A
×
3
7
4
A
5
F
1
B
E07A
E079
E078
E077
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.7
ADDSP (Add Word Data of Stack Pointer and Immediate
Data to Stack Pointer)
Add 16-bit immediate data or the value resulting from sign-extending 8-bit immediate
data to the word data pointed to by SP (stack pointer) and restore the result in SP. If the
addition result exceeds 16 bits, an underflow occurs.
CCR does not indicate whether an underflow has occurred.
■ ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer)
● Assembler format:
(1) ADDSP #imm8
(2) ADDSP #imm16
● Operation:
(1) (SP) ← (SP)+Sign-extended imm8
[Word addition]
(2) (SP) ← (SP)+imm16
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
#imm8
#imm16
Number of bytes
2
3
Number of cycles
3
3
Correction value
0
0
● Example:
ADDSP #89BAH
In this example, the 16-bit immediate data (89BAH) is added to SP. The addition result exceeds 16 bits,
resulting in an underflow.
SP
E2 A4
CCR
×0000
TNZVC
Before execution
CM44-00201-4E
SP
6C 5E
CCR
×0000
TNZVC
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.8
F2MC-16LX Family
ADDW (Add Word Data of AL and AH to AL)
Add the word data of AH and that of AL together and restore the result to AL.
■ ADDW (Add Word Data of AL and AH to AL)
● Assembler format:
ADDW A
● Operation:
(AL) ← (AH)+(AL)
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ADDW A
In this example, word data (83A2H) of AH is added to word data (7F23H) of AL. This results in an
overflow, so set the C flag.
A
AH
AL
83 A2
7F 23
CCR
×××××
A
AH
AL
83 A2
02 C5
CCR
92
0 0 0 1
T N Z V C
T N Z V C
Before execution
×
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.9
ADDW (Add Word Data of Destination and Source to
Destination)
Add the word data specified by the second operand to the word data specified by the
first operand and restore the result in the first operand.
■ ADDW (Add Word Data of Destination and Source to Destination)
● Assembler format:
ADDW A,#imm16
ADDW A,ear
ADDW A,eam
ADDW ear,A
ADDW eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
ADDW @RW0+1,A
In this example, word data (CD04H) of AL is added to word data (315DH) of address (E2A5H) specified in
the first operand (@RW0+1).
A
RW0
AH
AL
×× ××
CD 04
E2 A4
CCR
×××××
A
RW0
AH
AL
×× ××
CD 04
E2 A4
CCR
Memory
3 1
5 D
X X
1 0 0 0
Memory
E2A6
E2A5
E2A4
Before execution
94
×
T N Z V C
T N Z V C
F E
6 1
× ×
E2A6
E2A5
E2A4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.10
AND (And Byte Data of Destination and Source to
Destination)
Take the logical AND operation of the byte data specified by the first operand and the
byte data specified by the second operand and restore the result in the first operand.
■ AND (And Byte Data of Destination and Source to Destination)
● Assembler format:
AND A,#imm8
AND A,ear
AND A,eam
AND ear,A
AND eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
[Byte logical AND]
The logical AND operation of the byte data specified by the first operand and the byte data specified by the
second operand is taken on a bit-by-bit basis and the result is restored in the first operand.
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
AND 0052H,A
In this example, the logical AND operation of low-order byte data (55H) of AL is taken against byte data
(FAH) at address 0052H.
A
AH
AL
×× ××
00 55
CCR
×××××
A
AH
AL
×× ××
00 55
CCR
T N Z V C
Memory
F A
0 0 0
×
T N Z V C
Memory
0052
Before execution
96
×
5 0
0052
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.11
AND (And Byte Data of Immediate Data and Condition
Code Register)
Take the logical AND operation of the byte data of the condition code register (CCR) and
8-bit immediate data and restore the result in CCR.
In the logical AND operation, the most significant bit of the byte data is not taken into
consideration.
■ AND (And Byte Data of Immediate Data and Condition Code Register)
● Assembler format:
AND CCR,#imm8
● Operation:
(CCR) ← (CCR) and imm8
[Byte logical AND]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I
:
Stores bit 6 of the operation result.
S :
Stores bit 5 of the operation result.
T :
Stores bit 4 of the operation result.
N :
Stores bit 3 of the operation result.
Z :
Stores bit 2 of the operation result.
V :
Stores bit 1 of the operation result.
C :
Stores bit 0 of the operation result.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
0
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
AND CCR,#57H
In this example, the logical AND operation of immediate data (57H) is taken against CCR value
(0110101B).
A
CCR
AH
AL
×× ××
×× ××
I
0
S
1
T
1
N
0
Z
1
V
0
C
1
A
CCR
AH
AL
×× ××
×× ××
I
0
S
0
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
Before execution
98
Z
1
V
0
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
N
0
MSB
RP
LSB
× × × × ×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.12
ANDL (And Long Word Data of Destination and Source to
Destination)
Take the logical AND operation for the long word data of the accumulator (A) and that
specified by the second operand in a bit-by-bit basis and restore the result in A.
■ ANDL (And Long Word Data of Destination and Source to Destination)
● Assembler format:
ANDL A,ear
ANDL A,eam
● Operation:
(A) ← (A) and (Second operand)
[Long word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
ANDL A,0FFF0H
In this example, the logical AND operation of long word data (FF55AA00H) at address FFF0H is taken
against long word data (8252FEACH) of accumulator (A).
A
AH
82 52
AL
FE AC
CCR
A
AH
82 50
×××××
AL
AA 00
CCR
T N Z V C
F
5
A
0
FFF3
FFF2
FFF1
FFF0
Before execution
100
1 0 0
×
T N Z V C
Memory
Memory
F
5
A
0
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.13
ANDW (And Word Data of AH and AL to AL)
Take the logical AND operation of the word data of AH and that of AL and restore the
result in AL.
■ ANDW (And Word Data of AH and AL to AL)
● Assembler format:
ANDW A
● Operation:
(AL) ← (AH) and (AL)
[Word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ANDW A
In this example, the logical AND operation of word data (0426H) of AH is taken against word data
(AB98H) of AL.
A
AH
AL
04 26
AB 98
CCR
×××××
A
AH
AL
04 26
00 00
CCR
T N Z V C
Before execution
CM44-00201-4E
×
0 1 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.14
F2MC-16LX Family
ANDW (And Word Data of Destination and Source to
Destination)
Take the logical AND operation of the word data specified by the first operand and the
word data specified by the second operand and restore the reresult in the first operand.
■ ANDW (And Word Data of Destination and Source to Destination)
● Assembler format:
ANDW A,#imm16
ANDW A,ear
ANDW A,eam
ANDW ear,A
ANDW eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
[Word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ANDW 0E001H,A
In this example, the logical AND operation of word data (5963H) of AL is taken against word data (8342H)
at address 0E001H.
A
AH
AL
×× ××
59 63
CCR
×××××
A
AH
AL
×× ××
59 63
CCR
T N Z V C
E002
E001
Before execution
CM44-00201-4E
0 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
×
0 1
4 2
E002
E001
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.15
F2MC-16LX Family
ASR (Arithmetic Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) arithmetically to the right by
the number of bits specified by the second operand. The most significant bit of the
least significant byte data for A is not changed. The bit last shifted out from the least
significant bit is stored in the carry flag (C) of the condition code register (CCR).
■ ASR (Arithmetic Shift Byte Data of Accumulator to Right)
● Assembler format:
ASR A,R0
● Operation:
MSB
C
LSB
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
104
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ASR A,R0
In this example, low-order byte data (96H) of AL is arithmetically shifted to the right by the number of bits
(3) specified in R0.
AL
A
AL
×× ××
R0
××
03
CCR
AH
96
×××××
T N Z V C
Before execution
CM44-00201-4E
A
AL
×× ××
R0
××
03
F2
CCR 1 1 0
×
1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.16
F2MC-16LX Family
ASRL (Arithmetic Shift Long Word Data of Accumulator
to Right)
Shift the long word data of the accumulator (A) arithmetically to the right by the number
of bits specified by the second operand. The most significant bit of A is not changed.
The bit last shifted out from the least significant bit is stored in the carry flag (C) of the
condition code register (CCR).
■ ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)
● Assembler format:
ASRL A,R0
● Operation:
MSB
LSB
C
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
106
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ASRL A,R0
In this example, long word data (12345678H) of accumulator (A) is arithmetically shifted to the right by the
number of bits (2) specified in R0.
A
AH
AL
12 34
56 78
R0
CCR
0
2
× ×××0
T N Z V C
Before execution
CM44-00201-4E
A
AH
AL
04 8D
15 9E
R0
0
2
CCR 1 0 0 × 0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.17
F2MC-16LX Family
ASRW (Arithmetic Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by one
bit. The most significant bit of the low-order word data for A is not changed. The bit
shifted out from the least significant bit is stored in the carry flag (C).
■ ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Assembler format:
ASRW A
● Operation:
MSB
LSB
C
T
1
AL
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the old carry value is equal to "1" or the old T value is equal to "1", cleared
otherwise.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
108
Number of bytes:
1
Number of cycles:
2
Correction value:
0
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ASRW A
In this example, word data (A096H) of AL is arithmetically shifted to the right by one bit.
A
AH
AL
×× ××
A0 96
CCR 0
×××
A
1
AH
AL
×× ××
D0 4B
CCR 1 1 0
T N Z V C
Before execution
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×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.18
F2MC-16LX Family
ASRW (Arithmetic Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by the
number of bits specified by the second operand. The most significant bit of the loworder word data for A is not changed. The bit last shifted out from the least significant
bit is stored in the carry flag (C) of the condition code register (CCR).
■ ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Assembler format:
ASRW A,R0
● Operation:
MSB
LSB
C
T
1
AL
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
110
Number of bytes:
2
Number of states:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ASRW A,R0
In this example, word data (A096H) of AL is arithmetically shifted to the right by the number of bits (2)
specified in R0.
A
AH
AL
×× ××
A0 96
R0 0 2
CCR
××××
A
0
T N Z V C
Before execution
CM44-00201-4E
AH
AL
×× ××
E8 25
R0 0 2
CCR 0 1 0
×
1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.19
F2MC-16LX Family
BBcc (Branch if Bit Condition satisfied)
Cause a branch if the bit data specified by the first operand satisfies the condition.
Control is transferred to the address resulting from word-adding the sign-extended
data, specified by the second operand, to the address of the instruction following the
BBcc instruction.
■ BBcc (Branch if Bit Condition satisfied)
● Assembler format:
BBC <First operand>,rel
BBS <First operand>,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC) + <Number of bytes> + rel
[Word addition]
If the condition is not satisfied:
(PC) ← (PC)+<Number of bytes>
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:Unchanged
Z:
Set when the bit data is "0"; cleared when "1".
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
BBcc
BBC
BBS
Condition
Bit data = 0
Bit data = 1
First
operand
addr16:bp
dir:bp
io:bp
addr16:bp
dir:bp
io:bp
Number of
bytes
5
4
4
5
4
4
Number of
cycles *1
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 7
If a branch is
not taken: 6
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 7
If a branch is
not taken: 6
Correction
value *2
(b)
(b)
(b)
(b)
(b)
(b)
*1: “If a branch is taken” indicates the number of cycles assumed if a branch is taken. “If a branch is not taken” indicates
the number of cycles assumed if a branch is not taken.
*2: For the explanation of (b) in the table, see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
BBC 1234H:7,12H
In this example, a branch is caused because bit 7 in byte data (7FH) at address 1234H is set to "0" (when the
specified condition is satisfied).
PC
PC
E117
Memory
Memory
× ×
× ×
7 F
CM44-00201-4E
+ (12 + number of bytes 5)
E100
1234
: bit7 = 0
7 F
1234
× ×
× ×
Before execution
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.20
F2MC-16LX Family
Bcc (Branch relative if Condition satisfied)
Each instruction causes a branch if the condition determined for that instruction is
satisfied. Control is transferred to the address resulting from word-adding the signextended data, specified by the operand, to the address of the instruction following the
BBcc instruction.
■ Bcc (Branch relative if Condition satisfied)
● Assembler format:
BZ/BEQ rel
BNZ/BNE
rel
BC/BLO rel
BNC/BHS
rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+2+rel
[Word addition]
If the condition is not satisfied:
(PC) ← (PC)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 when branching is not performed, 4 otherwise.
Correction value:
0
Branch instruction and condition:
Bcc
BZ/
BEQ
BNZ/
BNE
BC/
BLO
BNC/
BHS
BN
BP
BV
BNV
BT
BNT
BRA
Condition
Z=1
Z=0
C=1
C=0
N=1
N=0
V=1
V=0
T=1
T=0
Always
satisfied
Bcc
BLT
BGE
BLE
BGT
BLS
BHI
Condition
V xor N = 1
V xor N = 0
(V xor N) or
Z=1
(V xor N) or
Z=0
C or Z = 1
C or Z = 0
● Example:
BHI 50H
In this example, a branch is caused because the C and Z flags in the condition code register (CCR) are set
to "0" (when the specified condition is satisfied).
PC
E 2
0 0
CCR 0 1 0 1 0
CM44-00201-4E
+(2+50)
C or Z = 0, then
PC
E 2
5 2
CCR 0 1 0 1 0
T N Z V C
T N Z V C
Before execution
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.21
F2MC-16LX Family
CALL (Call Subroutine)
Cause a branch to the address specified by the operand. By executing the RET
instruction in the subroutine to which control has been transferred, control returns to
the instruction following the CALL instruction.
■ CALL (Call Subroutine)
● Assembler format:
CALL @ear
CALL @eam
CALL addr16
● Operation:
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PC)+<Number of bytes>
(PC) ← <Operand>
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@ear
@eam
addr16
Number of bytes
2
2+
3
Number of cycles
6
7+(a)
6
Correction value
(c)
2×(c)
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
CALL @RW0
In this example, address (E55AH) of the next instruction is pushed to the stack specified by SP, and a
branch is caused to address (DC08H) indicated by the word data at address (F340H) specified in the
operand (@RW0).
PC
E5 58
RW0
F3 40
SP
01 24
PC
DC 08
RW0
F3 40
Memory
SP
01 22
Memory
D C
0 8
F341
F340
D C
0 8
F341
F340
× ×
× ×
× ×
0124
0123
0122
× ×
0124
0123
0122
Before execution
CM44-00201-4E
SP
SP
E 5
5 A
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.22
F2MC-16LX Family
CALLP (Call Physical Address)
Cause a branch to the physical address specified by the operand. The program bank
register (PCB) stores the most significant byte of the data specified by the operand. By
executing the RETP instruction in the subroutine to which control has been transferred,
control returns to the instruction following the CALLP instruction.
■ CALLP (Call physical Address)
● Assembler format:
CALLP @ear
CALLP @eam
CALLP addr24
● Operation:
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PCB)
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PC)+<Number of bytes>
[Zero extension]
(PCB) ← Physical address to branch to (High-order byte)
(PC) ← Physical address to branch to (Low-order word)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@ear
@eam
addr24
Number of bytes
2
2+
4
Number of cycles
10
11+(a)
10
Correction value
2×(c)
3×(c)+(b)
2×(c)
For the explanation of (a), (b), and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
CALLP 080711H
In this example, PCB and address (4349H) of the next instruction are pushed to the stack specified by USB
and SP, and a branch is caused to address 080711H. Set the most significant byte (08H) in the operand to
PCB.
PC
43 45
PCB
SP
F9 00
AD
USB
CCR
×
0
15
PC
07 11
PCB
SP
08
×××××
CCR
Memory
×
×
×
×
×
×
×
×
×
×
×
0
15
×××××
Memory
15F900
15F8FF
15F8FE
15F8FD
15F8FC
Before execution
CM44-00201-4E
USB
I S T N Z V C
I S T N Z V C
SP
F8 FC
× ×
SP
0
A
4
4
0
D
3
9
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.23
F2MC-16LX Family
CALLV (Call Vectored Subroutine)
Cause a branch to the address pointed to by the interrupt vector specified by the
operand. By executing the RET instruction in the subroutine to which control has been
transferred, control returns to the instruction following the CALLV instruction. The RET
instruction is the same as that used with the CALL instruction.
■ CALLV (Call Vectored Subroutine)
● Assembler format:
CALLV #vct4
● Operation:
(SP) ← (SP)–2
((SP)) ← (PC) + 1
[Word subtraction],
(PC) ← Vector address
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
7
Correction value:
2×(c)
Note: For the explanation of (c), see Table 8.4-2 .
Note:
When the value of the program counter bank register (PCB) is equal to FFH, the vector area is also
used as the vector area for INT #vct8 (#0 to #7). Caution must, therefore, be exercised when the
area is used. (See Table 9.1-1 .)
120
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
CALLV #15
In this example, address (F4A8H) of the next instruction is pushed to the stack specified by SP, and a
branch is caused to the address specified by the interrupt vector of #15.
PC
F4 A7
SP
01 02
PC
E1 54
Memory
SP
SP
01 00
Memory
E 1
5 4
FFE1
FFE0
E 1
5 4
FFE1
FFE0
× ×
× ×
× ×
0102
0101
0100
× ×
0102
0101
0100
Before execution
SP
F 4
A 8
After execution
Table 9.1-1 CALLV Vector List
Note:
CM44-00201-4E
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
XX is replaced by the value of the program counter bank register (PCB).
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.24
F2MC-16LX Family
CBNE (Compare Byte Data and Branch if not equal)
Perform byte comparison on the first and second operands (8-bit immediate data) and
cause a branch if the first and second operands are not equal. Control is transferred to
the address equal to the address of the instruction following the CBNE instruction plus
the word value resulting from sign-extending the third operand. A branch is not taken if
the first and second operands are equal.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the CBNE instruction + 4
+ disp16", not the "address of the location containing the machine instruction for the
instruction following the CBNE instruction 4 + disp16".
■ CBNE (Compare Byte Data and Branch if not equal)
● Assembler format:
CBNE A,#imm8,rel
CBNE ear,#imm8,rel
CBNE eam,#imm8,rel
● Operation:
(First operand)≠imm8
[Byte comparison] : (PC) ← (PC)+<Number of bytes>+rel
(First operand)=imm8
[Byte comparison] : (PC) ← (PC)+<Number of bytes>
● CCR:
122
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the compare operation result is "1", cleared otherwise.
Z:
Set when (First operand) = imm8, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared otherwise.
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Number of bytes, Number of cycles, and Correction value:
First operand
A
ear
eam *
Number of bytes
3
4
4+
If a branch is taken: 5
If a branch is not taken: 4
Number of cycles
Correction value
If a branch is taken: 13
If a branch is not taken: 12
0
If a branch is taken: 7+(a)
If a branch is not taken: 6+(a)
0
(b)
* : @Rwj+ addressing cannot be used in eam. If such code is executed, +4 is added to the contents of Rwj.
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
●Example:
CBNE
A, #0F4H,55H
In this example, comparison operation is performed on low-order byte data (F3H) of AL and 8-bit
immediate data (F4H). A branch is caused because the first and second operands are not equal.
A
AH
AL
×× ××
00 F3
PC
CCR
E3 10
F3H≠F4H
A
AH
AL
×× ××
00 F3
+(55H+Number of bytes: 3)
×××××
T N Z V C
Before execution
CM44-00201-4E
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PC
CCR
E3 68
×
1 0 0 1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.25
F2MC-16LX Family
CLRB (Clear Bit)
Clear the bit specified by bp to "0", in the memory location specified by the operand.
■ CLRB (Clear Bit)
● Assembler format:
CLRB dir:bp
CLRB io:bp
CLRB addr16:bp
● Operation:
(Operand) b ← 0
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
dir:bp
io:bp
addr16:bp
Number of bytes
3
3
4
Number of cycles
7
7
7
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
● Example:
CLRB 0AA55H:3
In this example, set bit 3 in data (FFH) at address AA55H to "0".
Memory
Memory
× ×
× ×
F F
124
AA55
F 7
AA55
× ×
× ×
Before execution
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.26
CMP (Compare Byte Data of Destination and Source)
Compare the byte data specified by the first operand with that specified by the second
operand and set the flag changes in the condition code register (CCR). The data
specified by the first operand and that by the second operand are not changed.
If only accumulator (A) is specified as the operand, the low-order byte data of AH is
compared with that of AL.
■ CMP (Compare Byte Data of Destination and Source)
● Assembler format:
(1)
CMP A,#imm8
CMP A,ear
(2)
CMP A,eam
CMP A
● Operation:
(1)
(First operand)–(Second operand)
[Byte comparison]
(2)
(AH)–(AL)
[Byte comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
Second operand
#imm8
ear
eam
−
Number of bytes
2
2
2+
1
Number of cycles
2
2
3+(a)
1
Correction value
0
0
(b)
0
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
CMP A,#7FH
In this example, comparison operation is performed on low-order byte data (22H) of AL and 8-bit
immediate data (7FH).
A
AH
AL
×× ××
A0 22
CCR
×××××
A
AH
AL
×× ××
A0 22
CCR
126
1 0 0 1
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.27
CMPL (Compare Long Word Data of Destination and
Source)
Compare the long word data specified by the first operand with that specified by the
second operand and set the result in the condition code register (CCR). The data
specified by the first operand and that specified by the second are not changed.
■ CMPL (Compare Long Word Data of Destination and Source)
● Assembler format:
CMPL A,#imm32
CMPL A,ear
CMPL A,eam
● Operation:
(First operand)–(Second operand)
[Long word comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#imm32
ear
eam
Number of bytes
5
2
2+
Number of cycles
3
6
7+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
CMPL A,#12345678H
In this example, comparison operation is performed on long word data (12345678H) of accumulator (A)
and 32-bit immediate data (12345678H).
A
AH
AL
12 34
56 78
CCR
×××××
A
AH
AL
12 34
56 78
CCR
128
0 1 0 0
T N Z V C
T N Z V C
Before execution
×
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.28
CMPW (Compare Word Data of Destination and Source)
Compare the word data specified by the first operand with that specified by the second
operand and set the result in the condition code register (CCR). The data specified by
the first operand and that specified by the second operand are not changed.
If only A is specified as the operand, the word data of AH is compared with that of AL.
■ CMPW (Compare Word Data of Destination and Source)
● Assembler format:
(1)
CMPW A,#imm16
CMPW A,ear
(2)
CMPW A,eam
CMPW A
● Operation:
(1)
(First operand)–(Second operand)
[Word comparison]
(2)
(AH)–(AL)
[Word comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
Second operand
#imm16
ear
eam
−
Number of bytes
3
2
2+
1
Number of cycles
2
2
3+(a)
1
Correction value
0
0
(c)
0
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
CMPW A,RW0
In this example, comparison operation is performed on word data (ABCDH) of AL and that (ABCCH) of
RW0.
A
AH
AL
×× ××
AB CD
RW0
CCR
AB CC
×××××
A
AH
AL
×× ××
AB CD
RW0
CCR
130
×
0 0 0 0
T N Z V C
T N Z V C
Before execution
AB CC
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.29
CWBNE (Compare Word Data and Branch if not Equal)
Perform word comparison on the first and second operands (16-bit immediate data) and
cause a branch if the first and second operands are not equal. Control is transferred to
the address equal to the address of the instruction following the CWBNE instruction
plus the word data resulting from sign-extending the third operand. A branch is not
taken if the first and second operands are equal.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the CWBNE instruction +
4 + disp16", not the "address of the location containing the machine instruction for the
instruction following the CWBNE instruction + disp16".
■ CWBNE (Compare Word Data and Branch if not Equal)
● Assembler format:
CWBNE A,#imm16,rel
CWBNE ear,#imm16,rel
CWBNE eam,#imm16,rel
● Operation:
(First operand)≠imm16
[Word comparison] :
(PC) ← (PC)+<Number of bytes>+rel
(First operand)=imm16
[Word comparison] :
(PC) ← (PC)+<Number of bytes>
● CCR:
CM44-00201-4E
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the comparison result is "1", cleared otherwise.
Z:
Set when (First operand) = imm16, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared otherwise.
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Number of bytes, Number of cycles, and Correction value:
First operand
A
ear
eam *
Number of bytes
4
5
5+
Number of cycles
If a branch is taken: 5
If a branch is not taken: 4
If a branch is taken: 8
If a branch is not taken: 7
If a branch is taken: 7+(a)
If a branch is not taken:
6+(a)
Correction value
0
0
(c)
*: @Rwj+ addressing cannot be used in eam. If such code is executed, +4 is added to the contents of Rwj.
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
CWBNE A,#0E5E5H,30H
In this example, comparison operation is performed on word data (5EE5H) of AL and the 16-bit immediate
data (E5E5H). A branch is caused because the first and second operands are not equal.
A
AH
AL
×× ××
5E E5
PC
CCR
D8 56
×××××
A
AH
AL
×× ××
5E E5
PC
CCR
132
×
0 0 0 0
T N Z V C
T N Z V C
Before execution
D8 8A
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.30
DBNZ (Decrement Byte Data and Branch if not zero)
Decrement the data specified by the first operand by one byte, and if the result is not
equal to zero, a branch is generated. Control is transferred to the address equal to the
address of the instruction following the DBNZ instruction plus the word data resulting
from sign-extending the data specified by the second operand. If the decrement result
is equal to zero, control is transferred to the next instruction.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the DBNZ instruction + 4 +
disp16", not the "address of the location containing the machine instruction for the
instruction following the DBNZ instruction + disp16".
■ DBNZ (Decrement Byte Data and Branch if not zero)
● Assembler format:
DBNZ ear,rel
DBNZ eam,rel
● Operation:
(ea) ← (ea)–1
[Byte subtraction]
if (ea) ≠ 0 : (PC) ← (PC)+<Number of bytes>+rel
if (ea) = 0 : (PC) ← (PC)+<Number of bytes>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Number of bytes
3
3+
Number of cycles
If a branch is taken: 7
If a branch is not taken: 6
If a branch is taken: 8+(a)
If a branch is not taken: 7+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
DBNZ @RW0+2,40H
In this example, one is subtracted from byte data (03H) at address (0122H) specified in the first operand
(@RW0+2). A branch is caused because the operation result is not "0".
PC
E3 58
PC
E3 9C
RW0
01 20
RW0
01 20
CCR 0 0 0 0 1
T N Z V C
CCR 0 0 1 0 1
T N Z V C
Memory
RW0+2
0
3
× ×
× ×
Memory
0122
0121
0120
Before execution
134
RW0+2
0
2
× ×
× ×
0122
0121
0120
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.31
DEC (Decrement Byte Data)
9.1 Detailed Execution Instructions
Decrement the byte data specified by the operand by one and store the result in the
operand.
■ DEC (Decrement Byte Data)
● Assembler format:
DEC ear
DEC eam
● Operation:
(ea) ← (ea)–1
[Byte subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
DEC R1
In this example, one is subtracted from byte data (80H) of R1.
R1
CCR
80
×××××
T N Z V C
Before execution
CM44-00201-4E
R1
CCR
7F
×
0 0 1
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.32
F2MC-16LX Family
DECL (Decrement Long Word Data)
Decrement the long word data specified by the operand by one and restore the result in
the operand.
■ DECL (Decrement Long Word Data)
● Assembler format:
DECL ear
DECL eam
● Operation:
(ea) ← (ea)–1
[Long word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
7
9+(a)
Correction value
0
2×(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
DECL RL0
In this example, one is subtracted from long word data (00001000H) of RL0.
RL0
0 0 0 0
10 00
CCR
×××××
RL0
00 00
CCR
T N Z V C
Before execution
136
0F FF
×
0 0 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.33
DECW (Decrement Word Data)
9.1 Detailed Execution Instructions
Decrement the word data specified by the operand by one and restore the result in the
operand.
■ DECW (Decrement Word Data)
● Assembler format:
DECW ear
DECW eam
● Operation:
(ea) ← (ea)–1
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
DECW @RW0+1000H
In this example, one is subtracted from word data (0001H) at address (7780H) specified in the operand
(@RW0+1000H).
67 80
RW0
CCR
RW0+1000H
×××××
CCR
×
0 0 1
×
T N Z V C
T N Z V C
Memory
Memory
0
0
0
1
× ×
7781
7780
777F
Before execution
138
67 80
RW0
RW0+1000H
0
0
0
0
× ×
7781
7780
777F
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1
F2MC-16LX Family
9.1.34
DIV (Divide Word Data by Byte Data)
Detailed Execution Instructions
Divide the word data specified by the first operand by the byte data specified by the
second operand and store the quotient (byte data) in the first operand and the
remainder (byte data) in the second operand. The operation assumes that the values
are signed ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of
AL and the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The
operation assumes that the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed. If an overflow occurs, the contents of
AL are destroyed.
■ DIV (Divide Word Data by Byte Data)
● Assembler format:
(1)
DIV A,ear
(2)
DIV A
DIV A,eam
● Operation:
(1)
word (A)/byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2)
word (AH)/byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
CM44-00201-4E
V:
Set when an overflow has occurred as a result of the operation or the divisor is zero,
cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
-
ear
eam
Number of bytes
2
2
2+
Number of cycles
Division by zero: 3
Overflow: 8 or 18
Normal termination: 18
Division by zero: 4
Overflow: 11 or 22
Normal termination: 23
Division by zero: 5+(a)
Overflow: 12+(a) or 23+(a)
Normal termination: 24+(a)
Correction value
0
0
*
*: (b) when division by zero or an overflow occurs; 2 × (b) when the instruction terminated normally.
For the explanation of (a) in the table and (b) in "*", see Table 8.4-1 and Table 8.4-2 .
● Example:
DIVA
In this example, word data (1357H) of AH is divided by byte data (AAH) of AL with a sign. Set the
quotient to AL and the remainder to AH.
A
AL
00 AA
AH
13 57
CCR
×××××
A
AH
00 15
CCR
140
×××
0 0
T N Z V C
T N Z V C
Before execution
AL
00 1D
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.35
DIVW (Divide Long Word Data by Word Data)
Divide the long word data specified by the first operand (A) by the word data specified
by the second operand and store the quotient (word data) in A and the remainder (word
data) in the second operand. The operation assumes that the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed. If an overflow occurs, the contents of
AL are destroyed.
■ DIVW (Divide Long Word Data by Word Data)
● Assembler format:
DIVW A,ear
DIVW A,eam
● Operation:
long word (A)/word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is zero,
cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Sign of the dividend
Plus
Minus
Plus
Minus
Number of bytes
2
2
2+
2+
Number of cycles
Correction value
Division by zero: 5+(a) Division by zero: 5+(a)
Division by zero: 4 Division by zero: 4
Overflow: 12+(a) or
Overflow: 12+(a) or
Overflow: 11 or 30 Overflow: 12 or 31
31+(a)
32+(a)
Normal termination: Normal termination:
Normal termination:
Normal termination:
31
32
32+(a)
33+(a)
0
0
*
*
*: (c) when division by zero or an overflow occurs; 2 × (c) when the instruction terminated normally.
For the explanation of (a) in the table and (c) in "*", see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
DIVW A,7254H
In this example, long word data (00001357H) of accumulator (A) is divided by word data (00AAH) at
address 7254H with a sign. Set the quotient to the word data of AL and the remainder to the word data at
address 7254H.
A
AH
AL
00 00
13 57
CCR
×××××
A
AL
00 1D
AH
00 00
CCR
×××
T N Z V C
T N Z V C
Memory
0 0
A A
Memory
7255
7254
Before execution
142
0 0
0 0
1 5
7255
7254
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.36
DIVU (Divide unsigned Word Data by unsigned Byte
Data)
Divide the word data specified by the first operand by the byte data specified by the
second operand and store the quotient (byte data) in the first operand and the
remainder (byte data) in the second operand. The operation assumes that the values
are unsigned ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of
AL and the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The
operation assumes that the values are unsigned ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it
had immediately before the instruction was executed.
■ DIVU (Divide unsigned Word Data by unsigned Byte Data)
● Assembler format:
(1)
DIVU A,ear
(2)
DIVU A
DIVU A,eam
● Operation:
(1)
word (A)/byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2)
word (AH)/byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
CM44-00201-4E
V:
Set when an overflow has occurred as a result of the operation or the divisor is zero,
cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
-
ear
eam
Number of bytes
1
2
2+
Division by zero: 3
Overflow: 7
Normal termination: 15
Number of cycles
Correction value
Division by zero: 4
Overflow: 8
Normal termination: 16
0
Division by zero: 6+(a)
Overflow: 9+(a)
Normal termination: 19+(a)
0
*
*: (b) when division by zero or an overflow occurs; 2 × (b) when the instruction terminated normally.
For the explanation of (a) in the table and (b) in "*", see Table 8.4-1 and Table 8.4-2 .
● Example:
DIVU A
In this example, word data (1357H) of AH is divided by the data (AAH) of AL without a sign. Set the
quotient to AL and the remainder to AH.
A
AH
13 57
AL
00 AA
CCR
×××××
A
AH
00 15
CCR
144
×××
0 0
T N Z V C
T N Z V C
Before execution
AL
00 1D
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.37
DIVUW (Divide unsigned Long Word Data by unsigned
Word Data)
Divide the long word data specified by the first operand (A) by the word data specified
by the second operand and store the quotient (word data) in A and the remainder (word
data) in the second operand. The operation assumes that the values are unsigned
ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it
had immediately before the instruction was executed.
■ DIVUW (Divide unsigned Long Word Data by unsigned Word Data)
● Assembler format:
DIVUW A,ear
DIVUW A,eam
● Operation:
long word (A)/word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is zero,
cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
Correction value
Division by zero: 4
Overflow: 7
Normal termination: 22
0
Division by zero: 6+(a)
Overflow: 8+(a)
Normal termination: 26+(a)
*
*: (c) when division by zero or an overflow occurs; 2 × (c) when the instruction terminated normally.
For the explanation of (a) in the table and (c) in "*", see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
DIVUW A,7254H
In this example, long word data (00001357H) of accumulator (A) is divided by word data (00AAH) at
address 7254H without a sign. Set the quotient to AL and the remainder to address 7254H.
A
AH
AL
00 00
13 57
CCR
×××××
A
AH
AL
00 00
00 1D
CCR
Memory
0 0
A A
0 0
Memory
7255
7254
Before execution
146
×××
T N Z V C
T N Z V C
0 0
1 5
7255
7254
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.38
DWBNZ (Decrement Word Data and Branch if not Zero)
Decrement the data specified by the first operand by one word, and if the result is not
equal to zero, cause a branch. Control is transferred to the address equal to the
address of the instruction following the DWBNZ instruction plus the word data resulting
from sign-extending the data specified by the second operand. If the decrement result
is equal to zero, control is transferred to the instruction following the DWBNZ
instruction.
When the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the DWBNZ instruction + 4 +
disp16", not the "address of the location containing the machine instruction for the
instruction following the DWBNZ instruction + disp16".
■ DWBNZ (Decrement Word Data and Branch if not Zero)
● Assembler format:
DWBNZ ear,rel
DWBNZ eam,rel
● Operation:
(First operand) ← (First operand)–1
[Word subtraction]
When (First operand)≠0, (PC) ← (PC)+<Number of bytes>+second operand
(PC) ← (PC)+<Number of bytes>
● CCR:
CM44-00201-4E
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Second operand
rel
rel
Number of bytes
3
3+
If a branch is taken: 7
If a branch is not taken: 6
Number of cycles
Correction value
If a branch is taken: 8+(a)
If a branch is not taken: 7+(a)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
DWBNZ RW0,30H
In this example, one is subtracted from word data (0001H) of RW0. A branch is not caused because the
operation result is "0".
PC
F8 20
PC
F8 23
RW0
00 01
RW0
00 00
CCR
×××××
T N Z V C
Before execution
148
CCR
×
0 1 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.39
EXT (Sign Extend from Byte Data to Word Data)
Extend the least significant byte data of A to word data as a signed binary number.
■ EXT (Sign Extend from Byte Data to Word Data)
● Assembler format:
EXT
● Operation:
When bit 7 of A=0, bits 8 to 15 of A ← 00H
When bit 7 of A≠0, bits 8 to 15 of A ← FFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
EXT
In this example, the high-order byte (bits 8 to 15) of AL is extend with FFH because the most significant bit
of low-order byte data (80H) of AL is "1".
AH
A
AL
×× ××
CCR
××
80
×××××
A
AH
AL
×× ××
FF 80
CCR
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1 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.40
F2MC-16LX Family
EXTW (Sign Extend from Word Data to Long Word Data)
Extend the low-order word data of A to long word data as a signed binary number.
■ EXTW (Sign Extend from Word Data to Long Word Data)
● Assembler format:
EXTW
● Operation:
When bit15 of A=0, bits 16 to 31 of A ← 0000H
When bit15 of A≠0, bits 16 to 31 of A ← FFFFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
EXTW
In this example, AH (bits 16 to 31 of A) is extend with FFFFH because the most significant bit of word data
(FF80H) of AL is "1".
A
AH
AL
×× ××
FF 80
CCR
×××××
A
AH
AL
FF FF
FF 80
CCR
150
1 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.41
FILS (Fill String Byte)
9.1 Detailed Execution Instructions
Transfer the contents of AL to the RW0-byte area that starts from the address whose
high-order eight bits are specified by the bank register specified by <bank> and whose
low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended. After the
interrupt has been handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank>
is omitted, DTB is assumed.
■ FILS (Fill String Byte)
● Assembler format:
FILS [I] [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL)
[Byte transfer], (AH) ← (AH)+1,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6×(RW0)+6
Correction value:
(b)×(RW0)
For the explanation of (b), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
FILS
In this example, low-order byte data (E5H) of AL is transferred from address (94BC00H) specified by DTB
and AH to the number of bytes (0100H) specified in RW0.
AH
BC 00
A
RW0
AL
00 E5
01 00
DTB
CCR
94
A
AH
BD 00
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
AH
1 0
94BC02
94BC01
94BC00
94BD00
94BCFF
94BCFE
E 5
E 5
...
...
...
...
94BD00
94BCFF
94BCFE
Before execution
152
94
Memory
× ×
× ×
× ×
AH
DTB
T N Z V C
Memory
× ×
× ×
× ×
AL
00 E5
E 5
E 5
E 5
94BC02
94BC01
94BC00
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.42
FILSW (Fill String Word)
9.1 Detailed Execution Instructions
Transfer the contents of AL to the RW0-word area that starts from the address whose
high-order eight bits are specified by the bank register specified by <bank> and whose
low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended. After the
interrupt has been handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank>
is omitted, DTB is assumed.
■ FILSW (Fill String Word)
● Assembler format:
FILSW [I] [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL)
[Word transfer], (AH) ← (AH)+2,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes: 2
Number of cycles: 6×(RW0)+6
Correction value: (c)×(RW0)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
FILSW ADB
In this example, word data (E55EH) of AL is transferred from address (49ABFEH) specified by ADB and
AH to the number of words (0080H) specified in RW0.
A
AH
AB FE
RW0
00 80
AL
E5 5E
ADB
CCR
49
A
AH
AC FE
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
× ×
AH
0 0
49AC00
49ABFF
49ABFE
49ACFF
49ACFE
49ACFD
E 5
...
...
...
...
49ACFF
49ACFE
49ACFD
Before execution
154
49
Memory
× ×
× ×
× ×
AH
ADB
T N Z V C
Memory
× ×
× ×
× ×
AL
E5 5E
5 E
E 5
5 E
49AC00
49ABFF
49ABFE
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.43
INC (Increment Byte Data (Address Specification))
Increment the byte data specified by the operand by one and restore the result in the
operand.
■ INC (Increment Byte Data (Address Specification))
● Assembler format:
INC ear
INC eam
● Operation:
(Operand) ← (Operand)+1
[Byte increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
INC R0
In this example, one is added to byte data (FFH) of R0.
R0
CCR
FF
×××××
T N Z V C
Before execution
CM44-00201-4E
00
R0
CCR
×
0 1 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.44
F2MC-16LX Family
INCL (Increment Long Word Data)
Increment the long word data specified by the operand by one and restore the result in
the operand.
■ INCL (Increment Long Word Data)
● Assembler format:
INCL ear
INCL eam
● Operation:
(Operand) ← (Operand)+1
[Long word increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
7
9+(a)
Correction value
0
2×(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
INCL RL0
In this example, one is added to long word data (7FFFFFFFH) of RL0.
RL0
7F FF
FF FF
CCR
×××××
RL0
80 00
CCR
156
×
1 0 1
×
T N Z V C
T N Z V C
Before execution
00 00
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.45
INCW (Increment Word Data)
9.1 Detailed Execution Instructions
Increment the word data specified by the operand by one and restore the result in the
operand.
■ INCW (Increment Word Data)
● Assembler format:
INCW ear
INCW eam
● Operation:
(Operand) ← (Operand)+1
[Word increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
INCW @RW0+
In this example, one is added to word data (0101H) at address (0354H) specified in the operand (@RW0+).
03 54
RW0
CCR
×××××
CCR
0 0 0
×
T N Z V C
Memory
Memory
0
0
1
1
0357
0356
0355
0354
Before execution
158
×
T N Z V C
× ×
× ×
RW0
03 56
RW0
RW0
× ×
× ×
0
0
1
2
0357
0356
0355
0354
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.46
INT (Software Interrupt)
9.1 Detailed Execution Instructions
Cause a branch to the interrupt handling routine at the specified address in the bank
0FFH. By executing the RETI instruction in the interrupt handling routine to which
control has been transferred, control returns to the instruction following this
instruction.
■ INT (Software Interrupt)
● Assembler format:
INT addr16
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as the
high-order byte and ADB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+3), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← 0FFH, (PC) ← addr16
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
3
Number of cycles:
16
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
INT 020F2H
In this example, a branch is caused to the interrupt handling routine at address FF20F2H. Set FFH to PCB.
A
AH
FF EE
DTB
99
DPR
BB
ILM
03
SSB
03
AL
DD CC
PCB
PC
88
77 66
ADB
CCR
AA
RP
I S T N Z V C
10
0 0 0 0 1 0 1
SSP
80 00
A
AH
FF EE
DTB
99
DPR
BB
ILM
03
SSB
03
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
160
PCB
PC
FF
20 F2
ADB
CCR
AA
I S T N Z V C
RP
0 1 0 0 1 0 1
10
SSP
7F F4
Memory
Memory
SSP
AL
DD CC
SSP
F
E
D
C
B
A
9
8
7
6
7
8
F
E
D
C
B
A
9
8
7
9
0
5
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.47
INT (Software Interrupt (Vector Specification))
Cause a branch to the interrupt handling routine pointed to by the interrupt vector
specified by the operand.
■ INT (Software Interrupt (Vector Specification))
● Assembler format:
INT #vct8
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as the
high-order byte and ADB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+2), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
(PC) ← Vector address (Low-order word)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
20
Correction value:
8×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
INT #11
In this example, a branch is caused to the interrupt handling routine specified by the interrupt vector of #11.
A
AH
AL
FF EE
DD CC
DTB
99
DPR
BB
ILM
02
SSB
03
PCB
PC
88
77 66
ADB
CCR
AA
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
A
AH
AL
FF EE
DD CC
DTB
99
DPR
BB
ILM
02
SSB
03
Memory
Memory
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
F
E
D
C
B
A
9
8
7
6
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
162
PCB
PC
89
E7 95
ADB
CCR
AA
RP
I S T N Z V C
15
0 1 0 0 1 0 1
SSP
7F F4
SSP
F
E
D
C
B
A
9
8
7
8
5
5
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.48
INT9 (Software Interrupt)
9.1 Detailed Execution Instructions
Cause a branch to the interrupt handling routine pointed to by the vector.
By executing the RETI instruction in the interrupt handling routine to which control has
been transferred, control returns to the instruction following this instruction.
■ INT9 (Software Interrupt)
● Assembler format:
INT9
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as the
high-order byte and ADB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+1), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
← Vector address (Low-order word)
(PC)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
20
Correction value:
8×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
INT9
In this example, a branch is caused to the interrupt handling routine specified by the interrupt vector of #9.
A
AH
11 22
DTB
77
DPR
55
ILM
02
SSB
03
AL
33 44
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
A
AH
11 22
DTB
77
DPR
55
ILM
02
SSB
03
PCB
PC
89
E7 95
ADB
CCR
66
RP
I S T N Z V C
15
0 1 0 0 1 0 1
SSP
7F F4
Memory
Memory
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
1
2
3
4
5
6
7
8
9
A
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
164
AL
33 44
SSP
1
2
3
4
5
6
7
8
9
B
5
5
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.49
INTP (Software Interrupt)
9.1 Detailed Execution Instructions
Cause a branch to the interrupt handling routine at the 24-bit physical address specified
by the operand. Any address in the entire 16MB space can be specified.
By executing the RETI instruction in the interrupt handling routine to which control has
been transferred, control returns to the instruction following this instruction.
■ INTP (Software Interrupt)
● Assembler format:
INTP addr24
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR: High-order byte, ADB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB: High-order byte, PCB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+4), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Most significant byte of addr24,
(PC) ← Low-order word of addr24
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
4
Number of cycles:
17
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
INTP 0C8F220H
In this example, a branch is caused to the interrupt handling routine at address C8F220. Set C8H to the
program counter bank register (PCB).
A
AH
11 22
DTB
77
DPR
55
ILM
03
SSB
03
AL
33 44
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
10
0 0 0 0 1 0 1
SSP
80 00
A
AH
11 22
DTB
77
DPR
55
ILM
03
SSB
03
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
166
PCB
PC
C8
F2 20
ADB
CCR
66
I S T N Z V C
RP
0 1 0 0 1 0 1
10
SSP
7F F4
Memory
Memory
SSP
AL
33 44
SSP
1
2
3
4
5
6
7
8
9
A
7
8
1
2
3
4
5
6
7
8
9
E
0
5
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.50
JCTX (Jump Context)
9.1 Detailed Execution Instructions
Restore register contents or an address saved in memory.
■ JCTX (Jump Context)
● Assembler format:
JCTX @A
● Operation:
(temp)
← (AL)
(PS)
← ((temp)) : (temp) ← (temp)+2
(PC)
← ((temp)) : (temp) ← (temp)+2
(DTB), (PCB)
← ((temp)) : (temp) ← (temp)+2
(DPR), (ADB)
← ((temp)) : (temp) ← (temp)+2
(AL)
← ((temp)) : (temp) ← (temp)+2
(AH)
← ((temp))
● CCR:
I
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
:
Stores bit 6 of the address indicated by AL.
S :
Stores bit 5 of the address indicated by AL.
T :
Stores bit 4 of the address indicated by AL.
N :
Stores bit 3 of the address indicated by AL.
Z :
Stores bit 2 of the address indicated by AL.
V :
Stores bit 1 of the address indicated by AL.
C :
Stores bit 0 of the address indicated by AL.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
14
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
JCTX @A
In this example, a context is returned from address (09E020H) specified by DTB and AL.
AH
A
AL
E0 20
×× ××
A
DTB
09
DPR
PCB
PC
××
×× ××
××
××
ILM
RP
××
×× × × × × × × ×
ADB
CCR
I S T N Z V C
AL
B
5
2
0
8
E
0
0
8
1
6
A
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
Before execution
168
DTB
80
DPR
08
ILM
07
AL
02 50
PCB
50
ADB
CE
RP
16
PC
88 01
CCR
I S T N Z V C
0 0 0 1 0 1 0
Memory
Memory
C
7
0
5
0
C
8
5
8
0
F
8
AH
CB 75
C
7
0
5
0
C
8
5
8
0
F
8
B
5
2
0
8
E
0
0
8
1
6
A
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.51
JMP (Jump Destination Address)
9.1 Detailed Execution Instructions
Read the word data from the address specified by the operand and cause a branch to
the address specified by the word data.
■ JMP (Jump Destination Address)
● Assembler format:
JMP @A
JMP addr16
JMP @ear
JMP @eam
● Operation:
(PC) ← (Operand)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@A
@ear
@eam
addr16
Number of bytes
1
2
2+
3
Number of cycles
2
3
4+(a)
3
Correction value
0
0
(c)
0
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
JMP @@RW0+2
In this example, a branch is caused to address (DB80H) specified by the word data at address (A0A2H)
specified in the operand (@RW0+2).
PC
E0 00
PC
DB 80
RW0
A0 A0
RW0
A0 A0
Memory
RW0+2
D
8
B
0
× ×
× ×
Memory
A0A3
A0A2
A0A1
A0A0
Before execution
170
RW0+2
D
8
B
0
× ×
× ×
A0A3
A0A2
A0A1
A0A0
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.52
JMPP (Jump Destination Physical Address)
If the operand is addr24, this instruction causes a branch to the physical address
specified by addr24.
If the operand is @ea, the instruction causes a branch to the physical address specified
by the contents of the operand.
■ JMPP (Jump Destination Physical Address)
● Assembler format:
(1)
JMPP addr24
(2)
JMPP @ear
JMPP @eam
● Operation:
(1):
(2):
(PC)
← Low-order word of addr24
(PCB)
← Most significant byte of addr24
(PC)
← (ea)
[Word transfer]
(PCB)
← (ea+2)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
addr24
@ear
@eam
Number of bytes
4
2
2+
Number of cycles
4
5
6+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
JMPP 0FFC850H
In this example, a branch is caused to FFC850H. Set FFH to PCB.
PC
12 48
PCB 3 4
Before execution
CM44-00201-4E
PC
C8 50
PCB F F
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.53
F2MC-16LX Family
LINK (Link and create new stack frame)
Store the current value of the frame pointer (RW3) in a stack and set a new frame
pointer. This allows an area for a new local variable to be reserved. This instruction is
used before a function is called.
■ LINK (Link and create new stack frame)
● Assembler format:
LINK #imm8
● Operation:
(SP) ← (SP)–2 ; ((SP)) ← (RW3) ; (RW3) ← (SP) ; (SP) ← (SP)–imm8
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
172
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
LINK #20H
In this example, RW3 is pushed to the stack specified by SP. Then 8-bit immediate data (20H) is subtracted
from the SP value (E020H).
SP
RW3
E0 22
A0 46
SP
RW3
Memory
SP
× ×
E0 20
Memory
A
4
E022
SP
Before execution
CM44-00201-4E
E0 00
0
6
E020
× ×
E000
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.54
F2MC-16LX Family
LSL (Logical Shift Byte Data of Accumulator to Left)
Shift the least significant byte data of the accumulator (A) to the left by the number of
bits specified by the second operand. The least significant bit of A is set to "0". The bit
last shifted out from the most significant bit of the least significant byte data for A is
stored in the carry flag (C).
■ LSL (Logical Shift Byte Data of Accumulator to Left)
● Assembler format:
LSL A,R0
● Operation:
C
A
MSB
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
174
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0 ; otherwise, 5 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
LSL A,R0
In this example, low-order byte data (FEH) of AL is shifted to the left by the number of bits (2) specified in
R0.
AH
A
AL
×× FF
×× ××
R0
CCR
02
×××××
T N Z V C
Before execution
CM44-00201-4E
AH
A
×× ××
R0
AL
×× FC
02
1 0 ××
T N Z V C
After execution
CCR
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.55
F2MC-16LX Family
LSLL (Logical Shift Long Word Data of Accumulator to
Left)
Shift the long word data of the accumulator (A) to the left by the number of bits
specified by the second operand. The least significant bit of A is set to "0". The bit last
shifted out from the most significant bit is stored in the carry flag (C).
■ LSLL (Logical Shift Long Word Data of Accumulator to Left)
● Assembler format:
LSLL A,R0
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
176
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
LSLL A,R0
In this example, long word data (33333333H) of accumulator (A) is shifted to the left by the number of bits
(2) specified in R0.
A
AH
33 33
AL
33 33
R0
CCR
A
AH
CC CC
02
×××××
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
CC CC
×
R0
02
1 0
×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.56
F2MC-16LX Family
LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by one bit. The least
significant bit of A is set to "0". The bit shifted out from the most significant bit of the
low-order word data for A is stored in the carry flag (C).
■ LSLW (Logical Shift Word Data of Accumulator to Left)
● Assembler format:
LSLW A/SHLW A
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
LSLW A
In this example, word data (AA55H) of AL is shifted to the left by one bit.
AH
A
AL
AA 55
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
Before execution
178
AL
55 AA
×
0 0
×
1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.57
LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by the number of bits
specified by the second operand. The least significant bit of A is set to "0". The bit last
shifted out from the most significant bit of the low-order word data for A is stored in the
carry flag (C).
■ LSLW (Logical Shift Word Data of Accumulator to Left)
● Assembler format:
LSLW A,R0
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
LSLW A,R0
In this example, word data (AA55H) of AL is shifted to the left by the number of bits (4) specified in R0.
A
AH
AL
×× ××
AA 55
R0
CCR
A
AH
AL
×× ××
A5 50
04
×××××
R0
CCR
T N Z V C
Before execution
180
×
1 0
04
×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.58
LSR (Logical Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) to the right by the number of
bits specified by the second operand. The most significant bit of the least significant
byte for A is set to "0". The bit last shifted out from the least significant bit is stored in
the carry flag (C).
■ LSR (Logical Shift Byte Data of Accumulator to Right)
● Assembler format:
LSR A,R0
● Operation:
A
MSB
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
LSR A,R0
In this example, low-order byte data (FFH) of AL is shifted to the right by the number of bits (5) specified
in R0.
AH
A
AL
×× FF
×× ××
R0
CCR
05
×××××
AH
A
×× ××
R0
182
05
CCR 1 1 0
T N Z V C
Before execution
AL
×× 07
×
1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.59
LSRL (Logical Shift Long Word Data of Accumulator to
Right)
Shift the long word data of the accumulator (A) to the right by the number of bits
specified by the second operand. The most significant bit of A is set to "0". The bit last
shifted out from the least significant bit of A is stored in the carry flag (C).
■ LSRL (Logical Shift Long Word Data of Accumulator to Right)
● Assembler format:
LSRL A,R0
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
LSRL A,R0
In this example, long word data (33333333H) of accumulator (A) is shifted to the right by the number of
bits (16) specified in R0.
A
AH
33 33
AL
33 33
R0
CCR
A
AH
00 00
10
×××××
R0
CCR 1 0 0
T N Z V C
Before execution
184
AL
33 33
10
×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.60
LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by one bit. The most
significant bit of the low-order word data for A is set to "0". The least significant bit is
stored in the carry flag (C).
■ LSRW (Logical Shift Word Data of Accumulator to Right)
● Assembler format:
LSRW A/SHRW A
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
R
*
–
*
I and S:
Unchanged
T:
Stores the OR of the shifted-out data from the carry and the old T flag value.
N:
Cleared
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
LSRW A
In this example, word data (AAAAH) of AL is shift to the right by one bit.
AH
A
×× ××
AL
AA AA
CCR 1
×××
AH
A
0
×× ××
CCR 1 0 0
T N Z V C
Before execution
186
AL
55 55
×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.61
LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by the number of bits
specified by the second operand. The most significant bit of the low-order word data
for A is set to "0". The bit last shifted out from the least significant bit is stored in the
carry flag (C).
■ LSRW (Logical Shift Word Data of Accumulator to Right)
● Assembler format:
LSRW A,R0
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
LSRW A,R0
In this example, word data (AAAAH) of AL is shifted to the right by the number of bits (12) specified in
R0.
AH
A
AL
×× ××
AH
AA AA
R0
CCR
A
AL
×× ××
0C
×××××
R0
CCR 1 0 0
T N Z V C
Before execution
188
00 0A
0C
×
1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.62
MOV (Move Byte Data from Source to Accumulator)
The AL value is transferred to AH. After this, 00H is transferred to the high-order byte of
AL, and byte data in the second operand is transferred to the low-order byte of AL.
No data is transferred to AH if the second operand is set to @A.
■ MOV (Move Byte Data from Source to Accumulator)
● Assembler format:
MOV A,#imm8
MOV A,Ri
MOV A,@A
MOV A,dir
MOV A,@RLi + disp8
MOV A,addr16
MOV A,io
MOV A,brg1
MOV A,eam
MOV A,ear
● Operation:
(A) ← (Second operand)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#imm8
@A
@RLi+disp8
io
addr16
Ri
dir
ear
eam
brg1
Number of bytes
2
2
3
2
3
1
2
2
2+
2
Number of cycles
2
3
10
3
4
2
3
2
3+(a)
*
Correction value
0
(b)
(b)
(b)
(b)
0
(b)
0
(b)
0
*: One cycle for the program counter bank register (PCB), additional data bank register (ADB), system stack bank
register (SSB), and user stack bank register (USB). Two cycles for the data bank register (DTB) and direct page
register (DPR).
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOV A,0092H
In this example, word data (A046H) of AL is transferred to AH, and then byte data (71H) at address 0092H
is transferred to AL.
AH
A
AL
A0 46
×× ××
CCR
×××××
A
AH
A0 46
AL
00 71
×
CCR
7 1
Memory
0092
Before execution
190
××
T N Z V C
T N Z V C
Memory
0 0
7 1
0092
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.63
MOV (Move Byte Data from Accumulator to Destination)
Transfer the low-order byte data of AL to the first operand.
■ MOV (Move Byte Data from Accumulator to Destination)
● Assembler format:
MOV dir,A
MOV Ri,A
MOV @RLi+disp8,A
MOV io,A
MOV addr16,A
MOV brg2,A
MOV ear,A
MOV eam,A
● Operation:
(First operand) ← (A)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
dir
@RLi+disp8
addr16
io
Ri
ear
eam
brg2
Number of bytes
2
3
3
2
1
2
2+
2
Number of cycles
3
10
4
3
2
2
3+(a)
1
Correction value
(b)
(b)
(b)
(b)
0
0
(b)
0
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOV R1,A
In this example, low-order byte data (32H) of AL is transferred to R1.
AH
A
×× ××
CCR
×××××
AL
49 32
R1
××
T N Z V C
AH
A
CCR
×× ××
×
0 0
××
R1
32
T N Z V C
Before execution
192
AL
49 32
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After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.64
MOV (Move Byte Immediate Data to Destination)
Transfer the 8-bit immediate data specified in the second operand to the first operand.
When the first operand is @PC + disp16, the data is transferred to the "address of the
location containing the machine instruction for the MOV instruction + 4 + rel", not the
"address of the location containing the machine instruction for the instruction following
the MOV instruction + rel".
■ MOV (Move Byte Immediate Data to Destination)
● Assembler format:
MOV RP,#imm8
MOV ILM,#imm8
MOV io,#imm8
MOV dir,#imm8
MOV ear,#imm8
MOV eam,#imm8
● Operation:
(First operand) ← imm8
● CCR:
If the data is transferred to a generalpurpose registers (R0 to R7) or bank
register
CM44-00201-4E
If the data is transferred to a register other
than the general-purpose registers (R0 to
R7) and the bank register
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T:
Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, N is set when the MSB of the
transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, Z is set when the transferred data
is zero, cleared otherwise.
V and C:
Unchanged
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Number of bytes, Number of cycles, and Correction value:
First operand
RP
ILM
dir
io
ear
eam
Second operand
#imm8
#imm8
#imm8
#imm8
#imm8
#imm8
Number of bytes
2
2
3
3
3
3+
Number of cycles
2
2
5
5
2
4+(a)
Correction value
0
0
(b)
(b)
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOV 009FH,#22H
In this example, 8-bit immediate data (22H) is transferred to address 009FH in bytes.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
AL
×× ××
×× ××
CCR
T N Z V C
T N Z V C
Memory
Memory
7 1
009F
Before execution
194
×××××
2 2
009F
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.65
MOV (Move Byte Data from Source to Destination)
Transfer the byte data specified by the second operand to the first operand.
MOV Ri, #imm8, described below, is an instruction contained in the basic page map (see
C.1 Table C-1 ), with code different from that contained in MOV ear, #imm8.
■ MOV (Move Byte Data from Source to Destination)
● Assembler format:
MOV Ri,#imm8
MOV Ri,ear
MOV Ri,eam
MOV ear,Ri
MOV eam,Ri
● Operation:
(First operand) ← (Second operand)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
Ri
Ri
Ri
ear
eam
Second operand
#imm8
ear
eam
Ri
Ri
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
4
5+(a)
Correction value
0
0
(b)
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOV R3,@RW0
In this example, byte data (71H) at address (E001H) specified in the second operand (@RW0) is transferred
to R3.
RW0
R3
××
E0 01
CCR
Memory
7 1
×××××
T N Z V C
E001
Before execution
196
RW0
R3
71
E0 01
CCR
Memory
7 1
××
0 0 ×
T N Z V C
E001
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.66
MOV (Move Byte Data from AH to Memory)
Transfer the low-order byte data of AH to the memory location specified by the contents
of AL.
■ MOV (Move Byte Data from AH to Memory)
● Assembler format:
MOV @AL,AH
● Operation:
((AL)) ← (AH)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
(b)
For the explanation of (b), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOV @AL,AH
In this example, low-order byte data (22H) of AH is transferred to address (E084H) specified in the word
data of AL.
A
AH
01 22
AL
E0 84
CCR
×××××
A
AH
01 22
CCR
0 0
××
Memory
Memory
E084
Before execution
198
×
T N Z V C
T N Z V C
7 1
AL
E0 84
2 2
E084
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.67
MOVB (Move Bit Data from Bit Address to Accumulator)
Transfer 00H to bits 8 to 15 of the accumulator (A). 00H is transferred to bits 0 to 7 of A
if the bit of the address specified by the second operand is equal to "0" and FFH is
transferred if the bit is equal to "1".
■ MOVB (Move Bit Data from Bit Address to Accumulator)
● Assembler format:
MOVB A,addr16:bp
MOVB A,dir:bp
MOVB A,io:bp
● Operation:
If (Second operand)=0 : (A) ← 00H
[Byte transfer]
If (Second operand)=1 : (A) ← FFH
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the transferred bit is "1", cleared when "0".
Z:
Set when the transferred bit is "0", cleared when "1".
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
addr16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
5
5
4
Correction value
(b)
(b)
(b)
For the explanation of (b) in the table, see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOVB A,32H:3
In this example, 00FFH is set to AL because bit 3 of byte data (7FH) at address 32H is set to "1".
A
AH
AL
×× ××
×× ××
CCR
×××××
AH
A
×× ××
CCR
1 0
××
Memory
Memory
× ×
200
×
T N Z V C
T N Z V C
7 F
AL
00 FF
× ×
0032
7 F
0032
× ×
× ×
Before execution
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.68
MOVB (Move Bit Data from Accumulator to Bit Address)
Transfer bit data "0" to the bit address specified by the first operand if the least
significant byte data of the accumulator (A) is 00H.
Bit data "1" is transferred to the bit address specified by the first operand if the least
significant byte data of A is not 00H.
■ MOVB (Move Bit Data from Accumulator to Bit Address)
● Assembler format:
MOVB addr16:bp,A
MOVB dir:bp,A
MOVB io:bp,A
● Operation:
If the byte data of (A) is 00H :
(First operand) b=0
[Bit transfer]
If the byte data of (A) is not 00H : (First operand) b=1
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the byte data for A is "1", cleared otherwise.
Z:
Set when the byte data of A is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
addr16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
7
7
6
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOVB 765FH: 7,A
In this example, bit 7 at address 765FH is set to "1" because the low-order byte data of AL is not set to 00H.
AH
A
AL
×× 01
×× ××
CCR
×××××
AH
A
×× ××
CCR
Memory
Memory
× ×
× ×
202
765F
×
0 0
××
T N Z V C
T N Z V C
7 F
AL
×× 01
F F
× ×
× ×
Before execution
After execution
FUJITSU MICROELECTRONICS LIMITED
765F
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.69
MOVEA (Move Effective Address to Destination)
Transfer the value specified by the second operand (effective address) to the first
operand. If a general-purpose register is specified by the second operand, the address
of the general-purpose register is transferred.
If the first operand is set to accumulator (A), the AL value, which is set before the
address transfer is performed, is transferred to AH.
■ MOVEA (Move Effective Address to Destination)
● Assembler format:
MOVEA <destination>,ear
MOVEA <destination>,eam
● Operation:
First operand ← ea
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
1
1+(a)
3
2+(a)
Correction value
0
0
0
0
For the explanation of (a) in the table, see Table 8.4-1 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MOVEA RW2,@RW0+2
In this example, address value (006BH) specified in the second operand (@RW0+2) is transferred to RW2.
RW0
00 69
RW0
00 69
RW2
×× ××
RW2
00 6B
CCR
×××××
T N Z V C
Before execution
204
CCR
×××××
T N Z V C
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.70
MOVL (Move Long Word Data from Source to
Accumulator)
Transfer the long word data specified by the second operand to the accumulator (A).
■ MOVL (Move Long Word Data from Source to Accumulator)
● Assembler format:
MOVL A,#imm32
MOVL A,ear
MOVL A,eam
● Operation:
(A) ← (Second operand)
[Long word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#imm32
ear
eam
Number of bytes
5
2
2+
Number of cycles
3
4
5+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOVL A,#0053FF64H
In this example, 32-bit immediate data (0053FF64H) is transferred to accumulator (A) as long word data.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
00 53
CCR
CM44-00201-4E
×
0 0
××
T N Z V C
T N Z V C
Before execution
AL
FF 64
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.71
F2MC-16LX Family
MOVL (Move Long Word Data from Accumulator to
Destination)
Transfer the long word data of the accumulator (A) to the first operand.
■ MOVL (Move Long Word Data from Accumulator to Destination)
● Assembler format:
MOVL ear,A
MOVL eam,A
● Operation:
(First operand) ← (A)
[Long word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Number of bytes
2
2+
Number of cycles
4
5+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOVL RL1,A
In this example, long word data (0197A024H) of accumulator (A) is transferred to RL1.
A
AH
01 97
AL
A0 24
A
AH
01 97
AL
A0 24
RL1
×× ××
×× ××
RL1
01 97
A0 24
CCR
×××××
CCR
206
0 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.72
MOVN (Move Immediate Nibble Data to Accumulator)
The AL value is transferred to AH. After this, 000H is transferred to bits 4 to 15 of AL,
and the nibble data specified in the second operand is transferred to bits 0 to 3 of AL.
■ MOVN (Move Immediate Nibble Data to Accumulator)
● Assembler format:
MOVN A,#imm4
● Operation:
(A) ← imm4
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T:
Unchanged
N:
Cleared
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
MOVN A,#0FH
In this example, word data (6207H) of AL is transferred to AH, and then byte data (0FH) with the 4-bit
immediate data (FH) zero-extended is transferred to AL.
AH
A
×× ××
CCR
AL
62 07
×××××
A
AH
62 07
AL
00 0F
CCR
CM44-00201-4E
0 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.73
F2MC-16LX Family
MOVS (Move String Byte)
Transfer byte data from the address specified by AL in the space specified by <source
bank> to the address specified by AH in the space specified by <destination bank>. The
transfer is repeated the number of times specified by RW0, with the addresses being
changed each time. The transfer is not performed if RW0 is equal to zero. Four types of
registers PCB, DTB, ADB, and SPB can be used as <destination bank> and <source
bank>. By default, DTB is assumed.
The addresses can be either incremented or decremented. By default, the addresses
are incremented.
If an interrupt occurs during the transfer, the transfer is suspended to handle the
interrupt. The transfer is resumed after the interrupt has been handled.
■ MOVS (Move String Byte)
● Assembler format:
MOVSI
[<destination bank>] [,<source bank>] (When the addresses are incremented)
MOVSD [<destination bank>] [,<source bank>] (When the addresses are decremented)
● Operation:
The following is repeated until RW0 becomes equal to "0":
((AH)) ← ((AL))
[Byte transfer]
(AH) ← (AH)±1, (AL) ← (AL)±1
[+ if MOVSWI, – if MOVSWD]
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 if (RW0) is equal to zero; otherwise, 4+8×(RW0)
Correction value:
2×(b)×(RW0)
For the explanation of (b), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVSI ADB,PCB
In this example, byte data from address (FF0000H) specified by PCB and AL is transferred to address
(018000H) specified by ADB and AH.
A
RW0
AH
80 00
AL
00 00
00 03
CCR
×××××
A
AH
80 03
RW0
00 00
AL
00 03
CCR
T N Z V C
PCB
FF
ADB
T N Z V C
PCB
01
FF
ADB
01
Memory
Memory
C
D
E
F
FF0003
FF0002
FF0001
FF0000
AL
AL
F
F
F
F
F
F
F
F
C
D
E
F
FF0003
FF0002
FF0001
FF0000
×
×
×
×
018003
018002
018001
018000
AH
× ×
AH
×
×
×
×
018003
018002
018001
018000
Before execution
CM44-00201-4E
×××××
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F D
F E
F F
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.74
F2MC-16LX Family
MOVSW (Move String Word)
Transfer word data from the address specified by AL in the space specified by <source
bank> to the address specified by AH in the space specified by <destination bank>. The
transfer is repeated the number of times specified by RW0, with the addresses being
changed each time. The transfer is not performed if RW0 is equal to zero. Four types of
registers PCB, DTB, ADB, and SPB can be used as <destination bank> and <source
bank>. By default, DTB is assumed.
The addresses can be either incremented or decremented. By default, the addresses
are incremented.
If an interrupt occurs during the transfer, the transfer is suspended to handle the
interrupt. The transfer is resumed after the interrupt has been handled.
■ MOVSW (Move String Word)
● Assembler format:
MOVSWI
[<destination bank>] [,<source bank>] (When the addresses are incremented)
MOVSWD
[<destination bank>] [,<source bank>] (When the addresses are decremented)
● Operation:
The following is repeated until RW0 becomes equal to "0":
((AH)) ← ((AL))
[Byte transfer]
(AH) ← (AH)±2, (AL) ← (AL)±2
[+ if MOVSWI, – for MOVSWD]
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 if (RW0) is equal to "0"; otherwise, 4 + 8×(RW0)
Correction value:
2×(c)×(RW0)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVSW,ADB
In this example, the word data from address (38A000H) specified by ADB and AL is transferred to address
(CD0000H) specified by DTB and AH.
A
AH
00 00
RW0
00 03
AL
A0 00
CCR
×××××
A
AH
00 06
RW0
00 00
AL
A0 06
CCR
T N Z V C
T N Z V C
DTB
CD
ADB
DTB
38
CD
ADB
AH
×
×
×
×
×
×
38
Memory
Memory
×
×
×
×
×
×
×××××
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
AH
2
4
3
3
4
4
6
2
6
1
D
6
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
AL
AL
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
Before execution
CM44-00201-4E
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.75
F2MC-16LX Family
MOVW (Move Word Data from Source to Accumulator)
The AL value is transferred to AH. After this, the word data in the second operand is
transferred to AL. No data is transferred to AH if the second operand is set to @A.
■ MOVW (Move Word Data from Source to Accumulator)
● Assembler format:
MOVW A,#imm16
MOVW A,@RWi+disp8
MOVW A,@A
MOVW A,addr16
MOVW A,@RLi+disp8
MOVW A,RWi
MOVW A,SP
MOVW A,dir
MOVW A,io
MOVW A,ear
MOVW A,eam
● Operation:
(A) ← (Second operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#imm16
@A
@RLi+disp8
SP
io
@RWi+disp8
addr16
RWi
dir
ear
eam
Number of bytes
3
2
3
1
2
2
3
1
2
2
2+
Number of cycles
2
3
10
1
3
5
4
2
3
2
3+(a)
Correction value
0
(c)
(c)
0
(c)
(c)
(c)
0
(c)
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVW A,0F9A0H
In this example, word data (4901H) of AL is transferred to AH, and then word data (AE86H) at address
F9A0H is transferred to AL.
AH
A
×× ××
CCR
AL
49 01
×××××
A
AH
49 01
CCR
T N Z V C
Memory
A E
8 6
×
1 0
××
T N Z V C
Memory
F9A1
F9A0
Before execution
CM44-00201-4E
AL
AE 86
A E
8 6
F9A1
F9A0
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.76
F2MC-16LX Family
MOVW (Move Word Data from Accumulator to
Destination)
Transfer the low-order word data of the accumulator (A) to the first operand.
■ MOVW (Move Word Data from Accumulator to Destination)
● Assembler format:
MOVW @RLi+disp8,A
MOVW addr16,A
MOVW SP,A
MOVW RWi,A
MOVW io,A
MOVW dir,A
MOVW @RWi+disp8,A
MOVW ear,A
MOVW eam,A
● Operation:
(First operand) ← (A)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
dir
@RLi+disp8
addr16
SP
io
@RWi+disp8
RWi
ear
eam
Number of bytes
2
3
3
1
2
2
1
2
2+
Number of cycles
3
10
4
1
3
5
2
2
3+(a)
Correction value
(c)
(c)
(c)
0
(c)
(c)
0
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVW RW0,A
In this example, word data (0000H) of AL is transferred to RW0.
AH
A
×× ××
RW0
CCR
AL
00 00
×× ××
×××××
AH
A
×× ××
RW0
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
00 00
00 00
×
0 1
××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.77
F2MC-16LX Family
MOVW (Move Immediate Word Data to Destination)
This instruction transfers the 16-bit immediate data to the first operand.
When the first operand is @PC + disp16, the transfer destination address is the address
where the machine instruction of the MOVW instruction is stored + 4 + disp16. Note
that this is not the address where the machine instruction of the instruction subsequent
to the MOVW instruction is stored+disp16.
■ MOVW (Move Immediate Word Data to Destination)
● Assembler format:
MOVW ear,#imm16
MOVW eam,#imm16
● Operation:
(First operand) ← imm16
● CCR:
If the data is transferred to a generalpurpose register (RW0 to RW7)
If the data is transferred to a register
other than the general-purpose registers
(RW0 to RW7)
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T:
Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, N is set when the MSB of the
transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, Z is set when the transferred data
is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:]
First operand
ear
eam
Number of bytes
4
4+
Number of cycles
2
4+(a)
Correction value
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVW RW0,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to RW0.
CCR
×××××
CCR
T N Z V C
RW0
×× ××
Before execution
CM44-00201-4E
RW0
×
0 0
××
T N Z V C
23 43
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.78
F2MC-16LX Family
MOVW (Move Word Data from Source to Destination)
Transfer the word data specified by the second operand to the first operand.
■ MOVW (Move Word Data from Source to Destination)
● Assembler format:
MOVW RWi,#imm16
MOVW ear,RWi
MOVW eam,RWi
MOVW RWi,ear
MOVW RWi,eam
● Operation:
(First operand) ← (Second operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
RWi
RWi
RWi
ear
eam
Second operand
#imm16
ear
eam
RWi
RWi
Number of bytes
3
2
2+
2
2+
Number of cycles
2
4
5+(a)
3
4+(a)
Correction value
0
0
(c)
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVW RW1,RW0
In this example, word data (004AH) of RW0 is transferred to RW1.
A
AH
AL
×× ××
×× ××
AH
A
AL
×× ××
RW0
00 4A
RW0
00 4A
RW1
×× ××
RW1
00 4A
CCR
×××××
CCR
T N Z V C
Before execution
CM44-00201-4E
×× ××
×
0 0
××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.79
F2MC-16LX Family
MOVW (Move Immediate Word Data to io)
Transfer 16-bit immediate data to the I/O area specified by the first operand.
■ MOVW (Move Immediate Word Data to io)
● Assembler format:
MOVW io,#imm16
● Operation:
(First operand) ← imm16
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
4
Number of cycles:
5
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
MOVW 24H,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to address 24H in the I/O area as word
data.
CCR
×××××
CCR
T N Z V C
×
×
×
×
× ×
000025
000024
2 3
4 3
000025
000024
× ×
Before execution
220
T N Z V C
Memory
Memory
×
×
×
×
×××××
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.80
MOVW (Move Word Data from AH to Memory)
Transfer the word data of AH to the memory location specified by the contents of AL.
■ MOVW (Move Word Data from AH to Memory)
● Assembler format:
MOVW @AL,AH
● Operation:
((AL)) ← (AH)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
MOVW @AL,AH
In this example, word data (00CBH) of AH is transferred to address (FEFFH) specified in AL.
A
AH
00 CB
AL
FE FF
CCR
×××××
A
AH
00 CB
CCR
T N Z V C
Memory
X X
0 0
FEFF
Before execution
CM44-00201-4E
×
1 0
××
T N Z V C
Memory
7 1
AL
FE FF
C B
FEFF
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.81
F2MC-16LX Family
MOVX (Move Byte Data with Sign Extension from Source
to Accumulator)
The AL value is transferred to AH. After this, the word data, for which the byte data in
the second operand is sign-extended, is transferred to AL. No data is transferred to AH
if the second operand is set to @A.
■ MOVX (Move Byte Data with Sign Extension from Source to Accumulator)
● Assembler format:
MOVX A,#imm8
MOVX A,@RWi+disp8
MOVX A,@A
MOVX A,addr16
MOVX A,@RLi+disp8
MOVX A,Ri
MOVX A,dir
MOVX A,io
MOVX A,ear
MOVX A,eam
● Operation:
(A) ← (Second operand)
[Byte transfer with sign extension]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#imm8
@A
@RLi+disp8
dir
io
@RWi+disp8 addr16
Ri
ear
eam
Number of bytes
2
2
3
2
2
2
3
2
2
2+
Number of cycles
2
3
10
3
3
5
4
2
2
3+(a)
Correction value
0
(b)
(b)
(b)
(b)
(b)
(b)
0
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MOVX A,0E001H
In this example, word data (FF86H), for which byte data (86H) at address E001H is sign-extended, is
transferred to AL.
AH
A
AL
A0 46
×× ××
CCR
×××××
A
AH
A0 46
CCR
T N Z V C
Memory
8 6
×
1 0
××
T N Z V C
Memory
E001
Before execution
CM44-00201-4E
AL
FF 86
8 6
E001
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.82
F2MC-16LX Family
MUL (Multiply Byte Data of Accumulator)
This instruction multiplies the low-order byte data of AH by that of AL as signed binary
numbers, then returns the result to AL of the accumulator (A).
■ MUL (Multiply Byte Data of Accumulator)
● Assembler format:
MUL A
● Operation:
word (A) ← byte (AH)×byte (AL)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 if byte (AH) is equal to zero; 12 if byte (AH) is not equal to zero and the result is
positive; 13 if the result is negative.
Correction value:
0
● Example:
MUL A
In this example, low-order byte data (FAH) of AH is multiplied by low-order byte data (11H) of AL with a
sign. Set word data (FF9AH) to AL as the multiplication result.
A
AH
AL
00 FA
00 11
CCR
×××××
T N Z V C
Before execution
224
A
AH
AL
00 FA
FF 9A
CCR
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.83
MUL (Multiply Byte Data of Accumulator and Effective
Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second
operand as signed binary numbers and restore the result in bits 0 to 15 of A.
■ MUL (Multiply Byte Data of Accumulator and Effective Address)
● Assembler format:
MUL A,ear
MUL A,eam
● Operation:
word (A) ← byte (A) × byte (ea)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if byte (ear) is equal to zero; 13 if byte (ear) is not equal to zero and the result is positive; 14 if the result is
negative.
*2: 5 + (a) if byte (eam) is equal to zero; 14 + (a) if byte (eam) is not equal to zero and the result is positive; 15 + (a) if
the result is negative.
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MUL A,R7
In this example, low-order byte data (85H) of AL is multiplied by byte data (A5H) in R7 with a sign. Set
word data (2B89H) to AL as the multiplication result.
A
AH
AL
×× ××
00 85
R7
CCR
A
AH
AL
×× ××
2B B9
A5
×××××
R7
CCR
T N Z V C
Before execution
226
A5
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.84
MULW (Multiply Word Data of Accumulator)
Multiply the word data of AH and AL as signed binary numbers, and restore the result to
accumulator (A) as long word data.
■ MULW (Multiply Word Data of Accumulator)
● Assembler format:
MULW A
● Operation:
long (A) ← word (AH)×word (AL)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 if word (AH) is equal to zero; 16 if word (AH) is not equal to zero and the result is
positive; 19 if the result is negative.
Correction value:
0
● Example:
MULW A
In this example, word data (AD01H) of AH is multiplied by word data (05EDH) of AL with a sign. Set the
multiplication result to accumulator (A) as long word data.
A
AH
AL
AD 01
05 ED
CCR
×××××
A
AH
AL
FE 14
2E ED
CCR
T N Z V C
Before execution
CM44-00201-4E
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.85
F2MC-16LX Family
MULW (Multiply Word Data of Accumulator and Effective
Address)
Multiply the word data in accumulator (A) and second operand as signed binary
numbers, and restore the result to accumulator (A) as long word data.
■ MULW (Multiply Word Data of Accumulator and Effective Address)
● Assembler format:
MULW A,ear
MULW A,eam
● Operation:
long (A) ← word (A)×word (Second operand)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if Word (ear) is equal to zero; 17 if Word (ear) is not equal to zero and the result is positive; 20 if the result is
negative.
*2: 5 + (a) if Word (eam) is equal to zero; 18 + (a) if Word (eam) is not equal to zero and the result is positive; 21 + (a)
if the result is negative.
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
MULW A,RW5
In this example, word data (8342H) of AL is multiplied by word data (4314H) in RW5 with a sign. Set the
multiplication result to accumulator (A) as long word data.
A
AH
AL
×× ××
83 42
RW5
CCR
43 14
×××××
A
AH
AL
DF 50
87 28
RW5
CCR
T N Z V C
Before execution
CM44-00201-4E
43 14
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.86
F2MC-16LX Family
MULU (Multiply Unsigned Byte Data of Accumulator)
Multiply the low-order byte data of AH by the low-order byte data of AL as unsigned
binary numbers and restore the result in the AL of the accumulator (A).
■ MULU (Multiply Unsigned Byte Data of Accumulator)
● Assembler format:
MULU A
● Operation:
word (A) ← byte (AH)×byte (AL)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3 if byte (AH) is equal to zero; 7 if byte (AH) is not equal to zero.
Correction value:
0
● Example:
MULU A
In this example, low-order byte data (FAH) of AH is multiplied by low-order byte data (11H) of AL without
a sign. Set word data (109AH) to AL as the multiplication result.
A
AH
00 FA
AL
00 11
CCR
×××××
A
AH
00 FA
CCR
T N Z V C
Before execution
230
AL
10 9A
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.87
MULU (Multiply Unsigned Byte Data of Accumulator and
Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second
operand as unsigned binary numbers and restore the result in bits 0 to 15 of A.
■ MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address)
● Assembler format:
MULU A, ear
MULU A, eam
● Operation:
word (A) ← byte (A) × byte (Second operand)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if byte (ear) is equal to zero; 8 if byte (ear) is not equal to zero.
*2: 5 + (a) if byte (eam) is equal to zero; 9 + (a) if not equal to zero.
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
MULU A, R7
In this example, low-order byte data (85H) of AL is multiplied by byte data (A5H) in R7 without a sign. Set
word data (55B9H) to AL as the multiplication result.
AH
A
AL
00 85
×× ××
R7
CCR
AH
A
×× ××
A5
×××××
R7
CCR
T N Z V C
Before execution
232
AL
55 B9
A5
×××××
T N Z V C
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.88
MULUW (Multiply Unsigned Word Data of Accumulator)
Multiply the word data of AH and AL as unsigned binary numbers, and restore the result
to accumulator (A) as long word data.
■ MULUW (Multiply Unsigned Word Data of Accumulator)
● Assembler format:
MULUW A
● Operation:
long (A) ← word (AH)×word (AL)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3 if word (AH) is equal to zero; 11 if word (AH) is not equal to zero.
Correction value:
0
● Example:
MULUW A
In this example, word data (AD01H) of AH is multiplied by word data (05EDH) of AL without a sign. Set
the multiplication result to accumulator (A) as long word data.
A
AH
AD 01
AL
05 ED
CCR
×××××
A
AH
04 01
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
2E ED
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.89
F2MC-16LX Family
MULUW (Multiply Unsigned Word Data of Accumulator
and Effective Address)
Multiply the word data in accumulator (A) and second operand as unsigned binary
numbers, and restore the result to accumulator (A) as long word data.
■ MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address)
● Assembler format:
MULUW A, ear
MULUW A, eam
● Operation:
long (A) ← word (A)×word (Second operand)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(c)
*1: 4 if word (ear) is equal to zero; 12 if word (ear) is not equal to zero.
*2: 5 + (a) if word (eam) is zero; 13 + (a) if word (eam) is not equal to zero.
For the explanation of (c) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
● Example:
MULUW A, RW5
In this example, word data (8342H) of AL is multiplied by word data (4314H) in RW5 without a sign. Set
the multiplication result to accumulator (A) as long word data.
AH
A
RW5
×× ××
43 14
AL
83 42
CCR
×××××
AH
22 64
A
RW5
43 14
T N Z V C
Before execution
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AL
87 28
CCR
×××××
T N Z V C
After execution
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.90
NEG (Negate Byte Data of Destination)
Take the 2's complement of the byte data specified by the operand and restore the
result in the operand. If the operand is the accumulator (A), the value resulting from
sign-extending the operation result is transferred to bits 8 to 15 of A.
■ NEG (Negate Byte Data of Destination)
● Assembler format:
NEG A
NEG ear
NEG eam
● Operation:
(Operand) ← 0–(Operand)
[Byte operation]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
NEG R0
In this example, the two's complement of byte data (59H) in R0 is obtained.
R0
CCR
59
×××××
T N Z V C
Before execution
236
R0
CCR
×
A7
1 0 0 1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.91
NEGW (Negate Word Data of Destination)
Take the 2's complement of the word data specified by the operand and restore the
result in the operand.
■ NEGW (Negate Word Data of Destination)
● Assembler format:
NEGW A
NEGW ear
NEGW eam
● Operation:
(Operand) ← 0–(Operand)
[Word operation]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
NEGW A
In this example, the two's complement of word data (AB98H) of AL is obtained.
A
AH
AL
×× ××
AB 98
CCR
×××××
A
AH
AL
×× ××
54 68
CCR
T N Z V C
Before execution
238
×
0 0 0 1
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.92
NOP (No Operation)
9.1 Detailed Execution Instructions
Perform no operation.
■ NOP (No Operation)
● Assembler format:
NOP
● Operation:
No operation is performed.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
NOP
The NOP instruction performs no operations.
A
AH
AL
×× ××
×× ××
PC
A
F0 00
CCR
AH
AL
×× ××
×× ××
PC
×××××
CCR
T N Z V C
× ×
0 0
Memory
F001
F000
Before execution
CM44-00201-4E
×××××
T N Z V C
Memory
PC
F0 01
PC
× ×
0 0
F001
F000
After execution
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9.1 Detailed Execution Instructions
9.1.93
F2MC-16LX Family
NOT (Not Byte Data of Destination)
Take the logical NOT of the byte data specified by the operand and restore the result in
the operand.
■ NOT (Not Byte Data of Destination)
● Assembler format:
NOT A
NOT ear
NOT eam
● Operation:
(Operand) ← not (Operand)
[Byte logical NOT]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
NOT 0071H
In this example, byte data (FFH) at address 0071H is inverted for each bit.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
AL
×× ××
×× ××
CCR
T N Z V C
0071
Before execution
CM44-00201-4E
0 1 0
×
T N Z V C
Memory
Memory
F F
×
0 0
0071
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.94
F2MC-16LX Family
NOTW (Not Word Data of Destination)
Take the logical NOT of the word data specified by the operand and restore the result in
the operand.
■ NOTW (Not Word Data of Destination)
● Assembler format:
NOTW A
NOTW ear
NOTW eam
● Operation:
(Operand) ← not (Operand)
[Word logical NOT]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
NOTW RW3
In this example, word data (258BH) of RW3 is inverted for each bit.
RW3
CCR
25 8B
×××××
T N Z V C
Before execution
242
RW3
CCR
DA 74
×
1 0 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1.95
NRML (NORMALIZE Long Word)
9.1 Detailed Execution Instructions
Shift the long word data of the accumulator (A) to the left until the most significant bit of
A becomes "1", if the long word data is not zero. R0 is set to the number of shifts
required and the zero flag (Z) is cleared.
If the long word data of the accumulator (A) is zero, R0 is set to 00H and the zero flag (Z)
is set.
■ NRML (NORMALIZE Long Word)
● Assembler format:
NRML A,R0
● Operation:
If A≠0:
The long word data is shifted to the left until the most significant bit of A becomes "1".
(R0) ← Number of shifts required, Z ← 0
If A=0:
(R0) ← 00H, Z ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:
Unchanged
Z:
Set when A is equal to zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
4 when the accumulator is equal to zero; otherwise, 6 + (Number of shifts required)
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
NRML A,R0
In this example, long word data (00008361H) of accumulator (A) is shifted to the left by 16 bits. Set the
number of shifted bits (10H) to R0.
A
AH
00 00
AL
83 61
R0
CCR
A
AH
83 61
34
×××××
R0
CCR
T N Z V C
Before execution
244
AL
00 00
××
10
0
××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.96
OR (Or Byte Data of Destination and Source to
Destination)
Take the logical OR of the byte data specified by the first operand and the byte data
specified by the second operand and restore the result in the first operand.
■ OR (Or Byte Data of Destination and Source to Destination)
● Assembler format:
OR A,#imm8
OR A,ear
OR A,eam
OR ear,A
OR eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
[Byte logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
OR 0052H,A
In this example, the logical OR of the byte data at address 0052H and low-order byte data (37H) of AL are
taken.
AH
A
AL
00 37
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
0052
Before execution
246
×
1 0 0
×
T N Z V C
Memory
Memory
F A
AL
00 37
F F
0052
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.97
OR (Or Byte Data of Immediate Data and Condition Code
Register to Condition Code Register)
Take the logical OR of the byte data in the condition code register (CCR) and specified
8-bit immediate data and restore the result in the condition code register (CCR).
Bit 7 of the immediate data is ignored because the condition code register (CCR) is 7
bits long.
■ OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code
Register)
● Assembler format:
OR CCR,#imm8
● Operation:
(CCR) ← (CCR) or imm8
[Byte logical OR]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
0
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
OR CCR,#57H
In this example, the logical OR of CCR and bits 6 to 0 of 8-bit immediate data (57H) are taken.
A
CCR
AH
AL
×× ××
×× ××
I
0
S
1
T
1
N
0
Z
1
V
0
C
1
A
CCR
AH
AL
×× ××
×× ××
I
1
S
1
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
Before execution
248
Z
1
V
1
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
N
0
MSB
RP
LSB
× × × × ×
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.98
ORL (Or Long Word Data of Destination and Source to
Destination)
Take the logical OR of the long word data for the accumulator (A) and that specified by
the second operand and restore the result in A.
■ ORL (Or Long Word Data of Destination and Source to Destination)
● Assembler format:
ORL A,ear
ORL A,eam
● Operation:
(A) ← (A) or (Second operand)
[Long word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
ORL A,0FFF0H
In this example, the logical OR of long word data (725DF05CH) of accumulator (A) and long word data
(FF55AA00H) at address FFF0 are taken.
A
AH
AL
72 5D
F0 5C
CCR
A
AH
AL
FF 5D
FA 5C
×××××
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
1 0 0
×
T N Z V C
Memory
FFF3
FFF2
FFF1
FFF0
Before execution
250
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.99
ORW (Or Word Data of AH and AL to AL)
Take the logical OR of the word data for AH and that for AL and restore the result in AL.
■ ORW (Or Word Data of AH and AL to AL)
● Assembler format:
ORW A
● Operation:
(AL) ← (AH) or (AL)
[Word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ORW A
In this example, the logical OR of word data (AB98H) of AL and word data (0426H) of AH are taken.
A
AH
04 26
AL
AB 98
CCR
×××××
A
AH
04 26
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
AF BE
×
1 0 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.100
F2MC-16LX Family
ORW (Or Word Data of Destination and Source to
Destination)
Take the logical OR of the word data specified by the first operand and the word data
specified by the second operand and restore the result in the first operand.
■ ORW (Or Word Data of Destination and Source to Destination)
● Assembler format:
ORW A,#imm16
ORW A,ear
ORW A,eam
ORW ear,A
ORW eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
[Word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ORW 0E001H,A
In this example, the logical OR of word data (4283H) at address E001 and word data (5963H) of AL are
taken.
A
AH
AL
×× ××
59 63
CCR
×××××
A
AH
AL
×× ××
59 63
CCR
T N Z V C
E002
E001
Before execution
CM44-00201-4E
1 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
×
D B
6 3
E002
E001
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.101
F2MC-16LX Family
POPW (Pop Word Data of Accumulator from Stack
Memory)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the
word data of the memory location pointed to by the stack pointer (SP) is transferred to
bits 0 to 15 of A. After the data is transferred, 0002H is word-added to the value of SP
(word data).
■ POPW (Pop Word Data of Accumulator from Stack Memory)
● Assembler format:
POPW A
● Operation:
(A) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
POPW A
In this example, word data (1635H) of AL is transferred to AH, and then word data (10ACH) at address
(0120H) specified by SP is transferred to AL. Add 2 to SP.
A
AH
04 22
AL
16 35
SP
01 20
CCR
A
×××××
AH
16 35
AL
10 AC
SP
01 22
CCR
T N Z V C
T N Z V C
Memory
Memory
SP
1 0
A C
0122
0121
0120
Before execution
CM44-00201-4E
×××××
SP
1 0
A C
0122
0121
0120
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.102
F2MC-16LX Family
POPW (Pop Word Data of AH from Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to AH.
Then, 0002H is word-added to the value of SP (word data).
■ POPW (Pop Word Data of AH from Stack Memory)
● Assembler format:
POPW AH
● Operation:
(AH) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
POPW AH
In this example, word data (4314H) at address (0120H) specified by SP is transferred to AH. Add 2 to SP.
AH
A
AL
04 22
16 35
SP
CCR
AH
A
01 20
AL
43 14
SP
×××××
CCR
T N Z V C
SP
×××××
Memory
0122
0121
0120
Before execution
CM44-00201-4E
01 22
T N Z V C
Memory
4 3
1 4
16 35
SP
4 3
1 4
0122
0121
0120
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.103
F2MC-16LX Family
POPW (Pop Word Data of Program Status from Stack
Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to the
processor status (PS). Bit 7 of the word data is ignored. Then, 0002H is word-added to
the value of SP (word data).
■ POPW (Pop Word Data of Program Status from Stack Memory)
● Assembler format:
POPW PS
● Operation:
(PS) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
The values of the corresponding bits for the stack memory are transferred.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
4
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
POPW PS
In this example, word data (4314H) at address (0120H) specified by SP is transferred to PS. Add 2 to SP.
SP
I
CCR
S
T
N
Z
V
SP
C
× × × × × × ×
MSB
ILM2 ILM1 ILM0
ILM
01 20
× × ×
RP
CCR
LSB
× × × × ×
4 3
1 4
0
1
0
T
1
N Z V C
0 1 0 0
MSB
LSB
RP 0 0 0 1 1
Memory
0122
0121
0120
Before execution
CM44-00201-4E
S
0
ILM2 ILM1 ILM0
ILM
Memory
SP
I
0
01 22
SP
4 3
1 4
0122
0121
0120
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.104
F2MC-16LX Family
POPW (Pop Registers from Stack Memory)
Transfer the data pointed to by the stack pointer (SP) to the multiple general-purpose
word registers specified by the register list (rlst).
In assembler representation, register names are enumerated as a register list. After
assembly, the register list turns into byte data.
■ POPW (Pop Registers from Stack Memory)
● Assembler format:
POPW rlst
● Operation:
(RWx) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
7 + 3 × (Number of transfers) + 2 × (Largest number in the transferred registers)
7 if rlst=0
Correction value:
(Number of transfers)×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
POPW (RW0,RW4)
In this example, RW0 and RW4 are popped from the stack specified by SP.
SP
34 FA
××
××
××
××
××
××
××
××
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Memory
SP
0
0
0
0
4
3
2
1
××
××
××
××
××
××
××
××
34FE
34FD
34FC
34FB
34FA
Before execution
CM44-00201-4E
SP
34 FE
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
02
01
××
××
××
××
××
××
04
03
××
××
××
××
××
××
Memory
0
0
0
0
4
3
2
1
34FE
34FD
34FC
34FB
34FA
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.105
F2MC-16LX Family
PUSHW (Push Word Data of Inherent Register to Stack
Memory)
Decrement the value of the stack pointer (SP) by two words and transfer the word data
of the register to the memory location pointed to by the resulting SP value.
■ PUSHW (Push Word Data of Inherent Register to Stack Memory)
● Assembler format:
PUSHW A
PUSHW AH
PUSHW PS
● Operation:
(SP) ← (SP)–2
[Word subtraction]
((SP)) ← (Operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
AH
PS
Number of bytes
1
1
1
Number of cycles
4
4
4
Correction value
(c)
(c)
(c)
For the explanation of (c) in the table, see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
PUSHW A
In this example, 2 is subtracted from SP, and the word data of AL to address (0120H) specified by SP is
transferred.
A
45 A4
A
45 A4
SP
01 22
SP
01 20
CCR
×××××
CCR
T N Z V C
T N Z V C
Memory
Memory
SP
× ×
× ×
0122
0121
0120
Before execution
CM44-00201-4E
×××××
SP
4 5
A 4
0122
0121
0120
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.106
F2MC-16LX Family
PUSHW (Push Registers to Stack Memory)
Transfer the contents of the multiple general-purpose word registers specified by the
register list (rlst) to the memory location pointed to by the stack pointer (SP).
In assembler representation, register names are enumerated as a register list. After
assembly, the register list turns into byte data.
■ PUSHW (Push Registers to Stack Memory)
● Assembler format:
PUSHW rlst
● Operation:
(SP) ← (SP)–2
[Word subtraction]
((SP))← (RWx)
[Word transfer]
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
29 + 3 × (Number of transfers) – 3 × (8 – Smallest number of the transferred registers)
8 if rlst = 0
Correction value:
(Number of transfers)×(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
PUSHW (RW1,RW3)
In this example, RW3 and RW1 to the stack specified by SP are pushed.
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
34 FE
×× ××
3 5
A 4
×× ××
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
×
×
×
×
×
×
×
×
×
×
×
×
34FE
34FD
34FC
34FB
34FA
Before execution
CM44-00201-4E
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
34 FA
×× ××
3 5
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
SP
A 4
×× ××
6
F
3
A
D
0
5
4
×
×
×
×
34FE
34FD
34FC
34FB
34FA
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.107
F2MC-16LX Family
RET (Return from Subroutine)
Cause a branch to the address pointed to by the stack pointer (SP). If this instruction is
used in combination with a subroutine call instruction (CALL, CALLV), control returns to
the instruction following the subroutine call instruction after the branch operation is
completed.
■ RET (Return from Subroutine)
● Assembler format:
RET
● Operation:
(PC) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
4
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
RET
In this example, word data (FC22H) at address (0062H) specified by SP is set to PC. Add 2 to SP.
SP
00 62
SP
00 64
PC
F0 02
PC
FC 22
Memory
SP
F C
2 2
Memory
0064
0063
0062
Before execution
CM44-00201-4E
SP
F C
2 2
0064
0063
0062
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.108
F2MC-16LX Family
RETI (Return from Interrupt)
This instruction returns the data in the memory that is indicated by (SSP) to PS to
detect interrupt requests performed using IF or ILM.
When the next interrupt request is received, the procedure branches to the detected
interruption vector. If no next interrupt is received, the procedure will return from the
interruption process.
■ RETI (Return from Interrupt)
● Assembler format:
RETI
● Operation:
(1)
If the next interrupt is accepted
(PS)
←
((SSP))
(S)
←
1, (PCB), (PC) ← Interrupt vector address
(ILM)
←
Accepted interrupt level
DTB, PCB, DPR, ADB, AL, and AH are not restored.
(2)
If control is returned from the next interrupt
(PS)
←
((SSP)), (SSP)
←
(SSP)+2;
(PC)
←
((SSP)), (SSP)
←
(SSP)+2;
(DTB),(PCB)
←
((SSP)), (SSP)
←
(SSP)+2;
(DPR),(ADB)
←
((SSP)), (SSP)
←
(SSP)+2;
(AL)
←
((SSP)), (SSP)
←
(SSP)+2;
(AH)
←
((SSP)), (SSP)
←
(SSP)+2
● CCR
(1) If the next interrupt is accepted
268
(2) If control is returned from the next interrupt
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
*
S
*
*
*
*
*
*
*
*
*
*
*
*
I: Restored to the saved I value.
I:
Restored to the saved I value.
S: Set
S: Restored to the saved S value.
T: Restored to the saved T value.
T: Restored to the saved T value.
N: Restored to the saved N value.
N: Restored to the saved N value.
Z: Restored to the saved Z value.
Z: Restored to the saved Z value.
V: Restored to the saved V value.
V: Restored to the saved V value.
C: Restored to the saved C value.
C: Restored to the saved C value.
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
15 if the next interrupt is accepted; 17 if control is returned from the next interrupt
Correction value:
3 × (b) + 2 × (c) if the next interrupt is accepted; 6 × (c) if control is returned from the
next interrupt
For the explanation of (b) and (c), see Table 8.4-2 .
● Example:
RETI (if control is returned from the interrupt)
In this example, the word data from address (037FF4H) specified by SSB and SP are transferred to each
register. Add 2 to SP each time data is transferred to a register.
AH
A
AL
××××
××××
A
DTB
PCB
PC
××
××
×× ××
DPR
ADB
××
××
CCR
ILM
RP
I S T N Z V C
××
××
× ×× × × × ×
SSB
03
AH
FFFE
DTB
99
DPR
BB
ILM
03
SSP
7F F4
SSP
F
E
D
C
B
A
9
8
7
6
1
0
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
CM44-00201-4E
PCB
88
ADB
AA
RP
01
SSB
03
PC
77 66
CCR
I S T N Z V C
0 0 0 0 0 0 0
SSP
80 00
Memory
Memory
F
E
D
C
B
A
9
8
7
6
6
8
AL
DDCC
SSP
F
E
D
C
B
A
9
8
7
6
6
8
F
E
D
C
B
A
9
8
7
6
1
0
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.109
F2MC-16LX Family
RETP (Return from Physical Address)
Cause a branch to the physical address pointed to by the stack pointer (SP). If this
instruction is used in combination with the CALLP instruction, control returns to the
instruction following the CALLP instruction after the branch operation is completed.
■ RETP (Return from Physical Address)
● Assembler format:
RETP
● Operation:
(PC) ← ((SP)), (SP) ← (SP)+2
[Word addition]
(PCB) ← ((SP))
[Word addition]
[Byte transfer], (SP) ← (SP)+2
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
6
Correction value:
(d)
For the explanation of (d), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
RETP
In this example, PC and PCB from the stack specified by USB and SP are popped, and are branched to
address AD4345H.
PC
22 FC
PCB
CCR
SP
F8 FC
08
×
USB
0
PC
43 45
15
SP
PCB
×××××
AD
×
CCR
I S T N Z V C
SP
0
A
4
4
0
D
3
5
0
15
×××××
Memory
15F900
15F8FF
15F8FE
15F8FD
15F8FC
Before execution
CM44-00201-4E
USB
I S T N Z V C
Memory
× ×
F9 00
SP
× ×
0
A
4
4
0
D
3
5
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.110
F2MC-16LX Family
ROLC (Rotate Byte Data of Accumulator with Carry to
Left)
Rotate or shift the byte data specified by the operand to the left by one bit, including the
carry flag (C). The most significant bit of the operand is placed in the carry flag (c).
■ ROLC (Rotate Byte Data of Accumulator with Carry to Left)
● Assembler format:
ROLC A
ROLC ear
ROLC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
2
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
ROLC A
In this example, rotate low-order byte data (32H) of AL and the C flag ("0") are rotated to the left.
AH
A
AL
×× ××
CCR
××
AH
32
××××
A
0
AL
×× ××
CCR
T N Z V C
Before execution
CM44-00201-4E
××
×
64
0 0
×
0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.111
F2MC-16LX Family
RORC (Rotate Byte Data of Accumulator with Carry to
Right)
Rotate or shift the byte data specified by the operand to the right by one bit, including
the carry flag (C). The least significant bit of the operand is placed in the carry flag (c).
■ RORC (Rotate Byte Data of Accumulator with Carry to Right)
● Assembler format:
RORC A
RORC ear
RORC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
2
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
RORC A
In this example, low-order byte data (32H) of AL and the C flag ("0") are rotated to the right.
AH
A
AL
32
×× ××
××
××××
0
T N Z V C
Before execution
CCR
CM44-00201-4E
AH
A
×× ××
CCR
AL
19
××
×
0 0 ×0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.112
F2MC-16LX Family
SBBS (Set Bit and Branch if Bit Set)
Cause a branch if the bit data specified by the first operand is "1". Control is
transferred to the address resulting from word-adding the value resulting from signextending the second operand to the address of the instruction following the SBBS
instruction.
After the instruction has been executed, the bit specified by the first operand is set to
"1".
■ SBBS (Set Bit and Branch if Bit Set)
● Assembler format:
SBBS addr16:bp,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+<Number of bytes>+rel
[Word addition], (addr16:bp) ← 1
If the condition is not satisfied:
(PC) ← (PC)+<Number of bytes>
[Word addition], (addr16:bp) ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:
Unchanged
Z:
Set when the bit data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
5
Number of cycles:
9 if the condition is not satisfied; 10 if the condition is satisfied
Correction value:
2×(b)
For the explanation of (b), see Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
SBBS 1234H:5,20H
In this example, bit 7 is set to "1" because bit 7 in byte data (7FH) at address 1234H is set to "1", and then is
branched (when the specified condition is satisfied).
PC
E1 00
E1 25
Memory
Memory
× ×
× ×
7 F
CM44-00201-4E
PC
1234
7 F
1234
× ×
× ×
Before execution
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.113
F2MC-16LX Family
SCEQ (Scan String Byte Until Equal)
Compare the byte data specified by AH in the space specified by <bank> with the data
of AL. The address is incremented/decremented and RW0 is decremented until the byte
data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By
default, DTB is assumed. The address can be either incremented or decremented. By
default, the address is incremented.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is
resumed.
■ SCEQ (Scan String Byte Until Equal)
● Assembler format:
SCEQ [<bank>] SCEQI [<bank>] (When the address is incremented)
SCEQD [<bank>] (When the address is decremented)
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Byte comparison]:
(AH) ← (AH)±1
(RW0) ← (RW0)–1
● CCR:
278
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
N is set when the MSB of the last compare operation result is "1", cleared otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
Z is set when a match with the contents of AL is found; cleared when the instruction
terminates with RW0 being set to zero.
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
V is set when an overflow has occurred as a result of the last compare operation;
cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
V is set when a borrow has occurred as a result of the last compare operation; cleared
otherwise.
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 when RW0 is zero, 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the
data in the AL register matches the byte data specified by the AH register in the space
that is specified by bank
Correction value:
(Number of times the operation was repeated)×(b)
For the explanation of (b), see Table 8.4-2 .
● Example:
SCEQ
In this example, byte data (54H) at address (031580H) specified by DTB and AH are compared with loworder byte data (46H) of AL. Both of them match with byte data (46H) at address 031585H.
AH
15 80
A
RW0
AL
00 46
01 00
DTB
CCR
03
A
RW0
AH
15 86
AL
00 46
00 FA
×××××
CCR
T N Z V C
Memory
AH
4
4
4
4
4
5
6
8
9
D
E
4
031586
031585
031584
031583
031582
031581
031580
Before execution
CM44-00201-4E
DTB
03
×××××
T N Z V C
AH
Memory
4
4
4
4
4
5
6
8
9
D
E
4
131586
031585
031584
031583
031582
031581
031580
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.114
F2MC-16LX Family
SCWEQ (Scan String Word Until Equal)
Compare the word data specified by AH in the space specified by <bank> with the data
of AL. The address is incremented/decremented and RW0 is decremented until the
word data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By
default, DTB is assumed. The address can be either incremented or decremented. By
default, the address is incremented.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is
resumed.
■ SCWEQ (Scan String Word until Equal)
● Assembler format:
SCWEQ [<bank>] SCWEQI [<bank>] (When the address is incremented)
SCWEQD [<bank>] (When the address is decremented)
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Word comparison]:
(AH) ← (AH)±2
(RW0) ← (RW0)–1
● CCR:
280
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
N is set when the MSB of the last compare operation result is "1", cleared otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
Z is set when a match with the contents of AL is found; cleared when the instruction
terminates with RW0 being set to zero.
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
V is set when an overflow has occurred as a result of the last compare operation;
cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not zero,
V is set when a borrow has occurred as a result of the last compare operation; cleared
otherwise.
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 when RW0 is zero, 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the
data in the AL register matches the byte data specified by the AH register in the space
that is specified by bank
Correction value:
(Number of times the operation was repeated) × (c)
For the explanation of (c), see Table 8.4-2 .
● Example:
SCWEQ
In this example, word data (E1E0H) at address (DEC000H) specified by DTB and AH are compared with
word data (00FFH) of AL. RW0 is set to "0", and processing is terminated.
A
AH
C0 00
RW0
00 03
AL
00 FF
DTB
CCR
DE
A
AH
C0 06
RW0
00 00
×××××
AL
00 FF
DTB
CCR
T N Z V C
AH
6
5
4
3
2
1
0
Memory
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
Before execution
CM44-00201-4E
1 0 0 1
T N Z V C
Memory
E
E
E
E
E
E
E
×
DE
AH
E
E
E
E
E
E
E
6
5
4
3
2
1
0
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.115
F2MC-16LX Family
SETB (Set Bit)
Set the contents of the bit address specified by the operand to "1".
■ SETB (Set Bit)
● Assembler format:
SETB addr16:bp
SETB dir:bp
SETB io:bp
● Operation:
(Operand) b ← 1
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
addr16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
7
7
7
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
● Example:
SETB 0AA55H:4
In this example, bit 4 in data (FFH) at address AA55H is set to "1".
CCR
00000
TNZVC
Memory
CCR
× ×
6 F
282
00000
TNZVC
Memory
× ×
AA55
7 F
AA55
× ×
× ×
Before execution
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.116 SUB (Subtract Byte Data of Source from Destination to
Destination)
Subtract the byte data specified by the second operand from the byte data specified by
the first operand and restore the result in the first operand. If the first operand is A, 00H
is transferred to bits 8 to 15 of A.
■ SUB (Subtract Byte Data of Source from Destination to Destination)
● Assembler format:
SUB A,#imm8
SUB A,dir
SUB A,ear
SUB A,eam
SUB ear,A
SUB eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
[Byte subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
ear
eam
Second operand
#imm8
dir
ear
eam
A
A
Number of bytes
2
2
2
2+
2
2+
Number of cycles
2
5
3
4+(a)
3
5+(a)
Correction value
0
(b)
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
SUB A,#22H
In this example, 8-bit immediate data (22H) is subtracted from low-order byte data (01H) of AL.
AH
A
AL
49 01
×× ××
CCR
×××××
AH
A
×× ××
CCR
284
×
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 DF
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.117 SUBC (Subtract Byte Data of AL from AH with Carry to
AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order byte
data of AH and restore the result in AL. 00H is transferred to bits 8 to 15 of the
accumulator (A).
■ SUBC (Subtract Byte Data of AL from AH with Carry to AL)
● Assembler format:
SUBC A
● Operation:
(AL) ← (AH)–(AL)–(C)
[Byte subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SUBC A
In this example, low-order byte data (D4H) of AL and the C flag ("1") are subtracted from low-order byte
data (05H) of AH. The subtraction result (30H) is set to the low-order bytes of AL.
A
AH
05 05
AL
00 D4
CCR
×××××
A
AH
05 05
CCR
CM44-00201-4E
×
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 30
After execution
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9.1 Detailed Execution Instructions
9.1.118
F2MC-16LX Family
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
Subtract the byte data specified by the second operand and the carry flag (C) from the
byte data of the accumulator (A) and restore the result in A. 00H is transferred to bits 8
to 15 of A.
■ SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to
Accumulator)
● Assembler format:
SUBC A,ear
SUBC A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
[Byte subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
286
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
SUBC A,R1
In this example, byte data (54H) of R1 and the C flag ("0") are subtracted from low-order byte data (35H) of
AL.
AH
A
×× ××
AL
00 35
R1
CCR
AH
A
×× ××
54
××××
0
R1
CCR
CM44-00201-4E
×
54
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 E1
After execution
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9.1 Detailed Execution Instructions
9.1.119
F2MC-16LX Family
SUBCW (Subtract Word Data of Effective Address from
Accumulator with Carry to Accumulator)
Subtract the word data specified by the second operand and the carry flag (C) from the
low-order word data of the accumulator (A) and restore the result in A.
■ SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to
Accumulator)
● Assembler format:
SUBCW A,ear
SUBCW A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
[Word subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
288
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
SUBCW A,0E024H
In this example, word data (A95BH) at address E024H and the C flag ("1") are subtracted from word data
(7558H) of AL.
AH
A
AL
75 58
×× ××
CCR
××××
AH
A
1
×× ××
CCR
A 9
5 B
1 0 0 1
Memory
E025
E024
Before execution
CM44-00201-4E
×
T N Z V C
T N Z V C
Memory
AL
CB FC
A 9
5 B
E025
E024
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.120
F2MC-16LX Family
SUBDC (Subtract Decimal Data of AL from AH with Carry to
AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order byte
data of AH and restore the result in AL. 00H is transferred to bits 8 to 15 of A.
■ SUBDC (Subtract Decimal Data of AL from AH with Carry to AL)
● Assembler format:
SUBDC A
● Operation:
(AL) ← (AH)–(AL)–(C)
[Decimal subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Undefined
C:
Set when a borrow has occurred as a result of the decimal operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
SUBDC A
In this example, byte data (86H) of AL and the C flag ("0") are subtracted from byte data (86H) of AH in
decimal.
A
AH
86
AL
86
××
××
CCR
××××
A
0
AH
86
××
CCR
290
×
0 1 0 0
T N Z V C
T N Z V C
Before execution
AL
00 00
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.121 SUBL (Subtract Long Word Data of Source from
Destination to Destination)
Subtract the long word data specified by the second operand from the long word data of
the accumulator (A) and restore the result in A.
■ SUBL (Subtract Long Word Data of Source from Destination to Destination)
● Assembler format:
SUBL A,#imm32
SUBL A,ear
SUBL A,eam
● Operation:
(First operand) ← (First operand)–(Second operand)
[Long word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#imm32
ear
eam
Number of bytes
5
2
2+
Number of cycles
4
6
7+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
SUBL A,0FD12H
In this example, long word data (525F31BDH) at address FD12H is subtracted from long word data
(34B3F201H) of accumulator (A).
A
AH
AL
34 B3
F2 01
CCR
A
AH
AL
E2 54
C0 44
×××××
CCR
5
5
3
B
2
F
1
D
Memory
FD16
FD15
FD14
FD13
FD12
Before execution
292
1 0 0 1
T N Z V C
T N Z V C
Memory
×
5
5
3
B
2
F
1
D
FD16
FD15
FD14
FD13
FD12
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.122 SUBW (Subtract Word Data of Source from Destination to
Destination)
Subtract the word data specified by the second operand from the word data specified by
the first operand and restore the result in the first operand.
■ SUBW (Subtract Word Data of Source from Destination to Destination)
● Assembler format:
SUBW A,#imm16
SUBW A,ear
SUBW A,eam
SUBW ear,A
SUBW eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
SUBW @RW0+,A
In this example, word data (3104H) of AL is subtracted from word data (5DABH) of address (E2A4H)
specified in the first operand (@RW0+).
A
AH
AL
×× ××
31 04
RW0
E2 A4
CCR
×××××
A
AH
AL
×× ××
31 04
RW0
CCR
T N Z V C
E2A5
E2A4
Before execution
294
×
0 0 0 0
T N Z V C
Memory
Memory
5 D
A B
E2 A6
2 C
A 7
E2A5
E2A4
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.123 SUBW (Subtract Word Data of AL from AH to AL)
Subtract the word data of AL from the word data of AH and restore the result to AL.
■ SUBW (Subtract Word Data of AL from AH to AL)
● Assembler format:
SUBW A
● Operation:
(AL) ← (AH)–(AL)
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SUBW A
In this example, word data (1019H) of AL is subtracted from word data (83A2H) of AH. The subtraction
result (7389H) is set to AL.
A
AH
AL
83 A2
10 19
CCR
×××××
A
AH
AL
83 A2
73 89
CCR
T N Z V C
Before execution
CM44-00201-4E
×
0 0 1 0
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.124
F2MC-16LX Family
SWAP (Swap Byte Data of Accumulator)
Swap the high- and low-order bytes of the word data for the accumulator (A) with each
other.
■ SWAP (Swap Byte Data of Accumulator)
● Assembler format:
SWAP
● Operation:
(A) 0 to 7 ↔ (A) 8 to 15
[Byte swapping]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
SWAP
In this example, the high-order byte data (06H) of AL and low-order byte data (90H) of AL are exchanged.
AH
A
×× ××
CCR
AL
AH
AL
06 90
×× ××
90 06
×××××
A
CCR
T N Z V C
Before execution
296
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.125 SWAPW (Swap Word Data of Accumulator)
Swap the high- and low-order words of the long word data for the accumulator (A) with
each other.
■ SWAPW (Swap Word Data of Accumulator)
● Assembler format:
SWAPW
● Operation:
Bits 0 to 15 of A ↔ Bits 16 to 31 of A
[Word swapping]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SWAPW
In this example, word data (1986H) of AH and word data (9861H) of AL are exchanged.
A
AH
19 86
AL
98 61
CCR
×××××
A
AH
98 61
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
19 86
×××××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.126
F2MC-16LX Family
UNLINK (Unlink and Create New Stack Frame)
Restore an old frame pointer from a stack.
■ UNLINK (Unlink and Create New Stack Frame)
● Assembler format:
UNLINK
● Operation:
(SP) ← (RW3), (RW3) ← ((SP)), (SP) ← (SP)+2
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
5
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
UNLINK
In this example, word data (E020H) of RW3 to SP is transferred, and RW3 from the stack specified by SP
is popped.
SP
E0 00
SP
E0 20
RW3
A 0
4 6
A0 46
RW3
Memory
E0 22
Memory
E020
SP
× ×
A 0
4 6
SP
× ×
E000
Before execution
298
E022
E021
E020
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.127 WBTc (Wait until Bit Condition Satisfied)
This instruction keeps reading data from the bit address specified by the operand until
that data satisfies the conditions. Once the data at the specified bit address satisfies
the conditions, control is transferred to the instruction subsequent to the WBTc
instruction.
■ WBTc (Wait until Bit Condition Satisfied)
● Assembler format:
WBTC io:bp
WBTS io:bp
● Operation:
Data is read from the bit address specified by io:bp until the data satisfies the condition. If the data from
the bit address satisfies the condition, control is transferred to the next instruction.
Interrupts are acceptable while the read operation is repeated with the condition not satisfied. If an
interrupt is generated in this state, the RETI instruction causes control to return to the WBTc instruction,
not to the instruction following the WBTc instruction.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Instruction
WBTC
WBTS
Condition
Bit data=0
Bit data=1
Number of bytes
3
3
Number of cycles
Undefined
Undefined
Correction value
CM44-00201-4E
Until the condition is satisfied Until the condition is satisfied
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
WBTS 34H:7
In this example, the process is halted until bit 7 in the byte data at address 34H is set to "1".
PC
E1 00
Memory
Peripheral
register
× ×
7 F
× ×
0034H
Before execution
300
Data is read from address 34H until bit 7 is set to "1"
(because of resource operation, for example).
When bit 7 becomes "1", execute the next instruction.
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.128 XCH (Exchange Byte Data of Source to Destination)
Exchange the byte data specified by the first operand with that specified by the second
operand.
If the first operand is A, the high-order byte of AL is set to 00H.
■ XCH (Exchange Byte Data of Source to Destination)
● Assembler format:
XCH A,ear
XCH A,eam
XCH Ri,ear
XCH Ri,eam
● Operation:
(First operand) ↔ (Second operand)
[Byte exchange]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Ri
Ri
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
4
5+(a)
7
9+(a)
Correction value
0
2×(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
XCH R4,@RW0+
In this example, byte data (F1H) of R4 and byte data (22H) at address (0060H) specified in the second
operand (@RW0+) are exchanged.
RW0
00 60
R4
CCR
RW0
F1
R4
×××××
CCR
T N Z V C
2 2
×××××
Memory
0061
0060
Before execution
302
22
T N Z V C
Memory
RW0
00 61
RW0
F 1
0061
0060
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.129 XCHW (Exchange Word Data of Source to Destination)
Exchange the word data specified by the first operand with that specified by the second
operand.
■ XCHW (Exchange Word Data of Source to Destination)
● Assembler format:
XCHW A,ear
XCHW A,eam
XCHW RWi,ear
XCHW RWi,eam
● Operation:
(First operand) ↔ (Second operand)
[Word exchange]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
4
5+(a)
7
9+(a)
Correction value
0
2×(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
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9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
XCHW A,@RW0
In this example, word data (24B4H) of AL and word data (2D58H) at address (E001H) specified in the
second operand (@RW0) are exchanged.
A
AH
AL
×× ××
34 B4
RW0
E0 01
CCR
A
×××××
AH
AL
×× ××
2D 58
RW0
E0 01
CCR
T N Z V C
T N Z V C
Memory
Memory
RW0
2 D
5 8
E002
E001
Before execution
304
×××××
RW0
3 4
B 4
E002
E001
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.130 XOR (Exclusive Or Byte Data of Destination and Source
to Destination)
Take the logical exclusive OR of the byte data specified by the first operand and the
byte data specified by the second operand and restore the result in the first operand.
■ XOR (Exclusive Or Byte Data of Destination and Source to Destination)
● Assembler format:
XOR A,#imm8
XOR A,ear
XOR A,eam
XOR ear,A
XOR eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
[Byte logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
XOR 0052H,A
In this example, the logical exclusive OR of byte data (FAH) at address 0052 and low-order byte data (55H)
of AL is taken.
AH
A
AL
00 55
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
Before execution
306
×
1 0 0
×
T N Z V C
Memory
Memory
F A
AL
00 55
000052
A F
000052
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.131 XORL (Exclusive Or Long Word Data of Destination and
Source to Destination)
Take the logical exclusive OR of the long word data for the accumulator (A) and that
specified by the second operand and restore the result in A.
■ XORL (Exclusive Or Long Word Data of Destination and Source to Destination)
● Assembler format:
XORL A,ear
XORL A,eam
● Operation:
(A) ← (A) xor (Second operand)
[Long word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
● Example:
XORL A,0FFF0H
In this example, the logical exclusive OR of long word data (8252FEACH) of accumulator (A) and long
word data (FF55AA00H) at address FFF0 is taken.
A
AH
AL
82 52
FE AC
CCR
A
AH
AL
7D 07
54 AC
×××××
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
0 0 0
×
T N Z V C
Memory
FFF3
FFF2
FFF1
FFF0
Before execution
308
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.132 XORW (Exclusive Or Word Data of AH and AL to AL)
Take the logical exclusive OR for the word data of AH and that of AL and restore the
result in AL.
■ XORW (Exclusive Or Word Data of AH and AL to AL)
● Assembler format:
XORW A
● Operation:
(AL) ← (AH) xor (AL)
[Word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
XORW A
In this example, the logical exclusive OR of word data (AB98H) of AL and word data (0426H) of AH is
taken.
A
AH
04 26
AL
AB 98
CCR
×××××
A
AH
04 26
CCR
T N Z V C
Before execution
CM44-00201-4E
AL
AF BE
×
1 0 0
×
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.133
F2MC-16LX Family
XORW (Exclusive Or Word Data of Destination and
Source to Destination)
Take the logical exclusive OR of the word data specified by the first operand and the
word data specified by the second operand and restore the result in the first operand.
■ XORW (Exclusive Or Word Data of Destination and Source to Destination)
● Assembler format:
XORW A,#imm16
XORW A,ear
XORW A,eam
XORW ear,A
XORW eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
[Word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
310
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
F2MC-16LX Family
9.1 Detailed Execution Instructions
● Example:
XORW 0E001H,A
In this example, the logical exclusive OR of word data (8342H) at address E001 and word data (5963H) of
AL is taken.
A
AH
AL
×× ××
59 63
CCR
×××××
AH
A
AL
×× ××
CCR
T N Z V C
E002
E001
Before execution
CM44-00201-4E
×
1 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
59 63
D A
2 1
E002
E001
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
9.1.134
F2MC-16LX Family
ZEXT (Zero Extend from Byte Data to Word Data)
Transfer 00H to bits 8 to 15 of the accumulator (A).
■ ZEXT (Zero Extend from Byte Data to Word Data)
● Assembler format:
ZEXT
● Operation:
Bits 8 to 15 of A ← 00H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T:
Unchanged
N:
Cleared
Z:
Set when the zero-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
ZEXT
In this example, the low-order byte of AL is set to 00H.
AH
A
AL
×× ××
××
CCR
80
×××××
A
AH
AL
×× ××
00 80
CCR
T N Z V C
Before execution
312
×
0 0
××
T N Z V C
After execution
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CM44-00201-4E
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
F2MC-16LX Family
9.1.135 ZEXTW (Zero Extend from Word Data to Long Word Data)
Transfer 0000H to bits 16 to 31 of the accumulator (A).
■ ZEXTW (Zero Extend from Word Data to Long Word Data)
● Assembler format:
ZEXTW
● Operation:
Bits 16 to 31 of A ← 0000H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, andT:
Unchanged
N:
Cleared
Z:
Set when the zero-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
ZEXTW
In this example, AH is set to 0000H.
A
AH
AL
×× ××
FF 80
CCR
×××××
A
AH
AL
00 00
FF 80
CCR
T N Z V C
Before execution
CM44-00201-4E
×
0 0
××
T N Z V C
After execution
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CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1 Detailed Execution Instructions
314
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F2MC-16LX Family
CM44-00201-4E
APPENDIX
This appendix includes lists and maps of instructions
for the F2MC-16LX.
APPENDIX A Explanation of Instruction Lists
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
APPENDIX C F2MC-16LX Instruction Maps
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APPENDIX
APPENDIX A
Explanation of Instruction Lists
F2MC-16LX Family
APPENDIX A Explanation of Instruction Lists
This section explains items and symbols used in each instruction list included in
Appendix B.
A.1 Items Used in Instruction Lists
A.2 Symbols Used in Instruction Lists
A.3 Effective Address Field
A.4 Calculating the Number of Execution Cycles
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A.1
APPENDIX A
APPENDIX
Explanation of Instruction Lists
Items Used in Instruction Lists
Table A-1explains the items used in the instruction lists.
■ Explanation of the Items Used in the Instruction Lists
Table A-1 Explanation of the Items Used in the Instruction Lists (1 / 2)
Item
Mnemonic
Description
Upper-case letters and symbols: Described as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table A-4for details about meanings of letters in items.
RG
B
Operation
Indicates the register access count during execution of instruction.
Used to calculate compensation values for CPU intermittent operation.
Indicates the compensation value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is the compensation
value summed with the value in the "~" column.
Indicates operation of instruction.
LH
Indicates special operations involving bits 15 through 08 of the accumulator.
Z: Transfers "0".
X: Sign-extended transfer through sign extension.
- : Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH.
- : No transfer
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH using sign extension AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack),
T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
- : No change
S: Set by execution of instruction.
R: Reset by execution of instruction.
Z
V
C
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APPENDIX
APPENDIX A
F2MC-16LX Family
Explanation of Instruction Lists
Table A-1 Explanation of the Items Used in the Instruction Lists (2 / 2)
Item
Description
RMW
Indicates whether the instruction is a read-modify-write instruction (a single
instruction that reads data from memory, etc., processes the data, and then writes
the result to memory.).
*: Instruction is a read-modify-write instruction.
-: Instruction is not a read-modify-write instruction.
Note:
A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
■ Number of Execution Cycles
The number of cycles required to execute instructions (number of execution cycles) is the summation of the
number of cycles of each instruction, the compensation value determined by conditions, and the number of
cycles required to fetch programs. If, however, a program stored in memory that is connected to a 16-bit
bus such as internal ROMs is to be fetched, program fetch is executed every time instructions being
executed exceed the two byte (one word) boundary. Therefore, interference with data access will increase
the number of execution cycles. Since program fetch is executed for each byte of instructions being
executed when a program stored on the memory connected to an external 8-bit bus is fetched, data access
interference will increase the number of execution cycles.
When access is made to general-purpose registers, built-in ROMs, built-in RAMs, built-in I/O units, or
external buses during CPU intermittent operation, the CPU clock suspends its operation for the number of
cycles that is specified by the CG0/CG1 bit of the low-power-consumption-mode control register. Therefore,
to obtain the number of cycles required to execute instructions during CPU intermittent operation, add
these compensation values (the number of accesses multiplied by the number of cycled suspended) to the
number of normal execution cycles.
350
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CM44-00201-4E
F2MC-16LX Family
A.2
APPENDIX A
APPENDIX
Explanation of Instruction Lists
Symbols Used in Instruction Lists
Table A-2explains the symbols used in the instruction lists.
■ Explanation of the Symbols Used in the Instruction Lists
Table A-2 Explanation of the Symbols Used in the Instruction Lists (1 / 2)
Symbol
A
CM44-00201-4E
Explanation
32 bit accumulator
The bit length used is different for each instruction.
Byte: Lower 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL and AH
AH
Upper 16 bits of A
AL
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of address 24
ad24 16-23
Bit16 to bit23 of address 24
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351
APPENDIX
APPENDIX A
F2MC-16LX Family
Explanation of Instruction Lists
Table A-2 Explanation of the Symbols Used in the Instruction Lists (2 / 2)
Symbol
io
I/O area (000000H to 0000FFH)
imm4
4-bit immediate data
imm8
8-bit immediate data
imm16
16-bit immediate data
imm32
32-bit immediate data
ext (imm8)
16-bit data signed and extended from 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
352
Explanation
Bit offset value
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
Branch specification relative to PC
ear
Effective addressing (codes 00H to 07H)
eam
Effective addressing (codes 08H to 1FH)
rlst
Register list
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
A.3
APPENDIX A
APPENDIX
Explanation of Instruction Lists
Effective Address Field
Table A-3lists address formats used in the effective address field.
■ Effective Address Field
Table A-3 Effective Address Field
Code
00
01
02
03
04
05
06
07
08
09
0A
Notation
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RL0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Number of bytes
of address
expansion part*
Register direct
* : The general-purpose register names in the
Coding column correspond to the Byte,
Word, and Long-word types in sequence
from the left.
-
Register indirect
0
0B
@RW3
0C
@RW0+
0D
@RW1+
Register indirect with post-incrementing
0
0E
@RW2+
0F
@RW3+
10
@RW0+disp8
11
@RW1+disp8
12
@RW2+disp8
13
@RW3+disp8
Register indirect with 8-bit displacement
1
14
@RW4+disp8
15
@RW5+disp8
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
* : The number of bytes of the address expansion part is shown in the "#" (number of bytes) column or the figure
before "+" in the expression of bytes in the instruction details.
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APPENDIX
APPENDIX A
A.4
F2MC-16LX Family
Calculating the Number of Execution Cycles
Explanation of Instruction Lists
Table A-4, Table A-5, and Table A-6show the method of calculating the number of
execution cycles of instructions.
■ Calculating the Number of Execution Cycles
Table A-4 Number of Execution Cycles for Designating Each Effective Address
Code
Operand
(a)*
Number of execution cycles
for each form of addressing
Number of accesses for
each form of addressing
Listed in Table of Instructions
Listed in Table of Instructions
00
to
07
Ri
Rwi
RLi
08
to
0B
@RWj
2
1
0C
to
0F
@RWj+
4
2
10
to
17
@RWi+disp8
2
1
18
to
1B
@RWj+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
* : (a) is used in "~" (number of cycles), "B" (compensation value) (both in "APPENDIX B F2MC-16LX Instruction
Lists (351 Instructions)", and in "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
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CM44-00201-4E
F2MC-16LX Family
APPENDIX
Explanation of Instruction Lists
APPENDIX A
Table A-5 Compensation Values for Calculating the Number of Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycles
Access
count
Cycles
Access
count
Cycles
Access
count
Internal register
+0
1
+0
1
+0
2
Internal register even
address
+0
1
+0
1
+0
2
Internal register odd
address
+0
1
+2
2
+4
4
Even address on external
data bus (16-bits)
+1
1
+1
1
+2
2
Odd address on external
data bus (16-bits)
+1
1
+4
2
+8
4
External data bus
(8-bit)
+1
1
+4
2
+8
4
* : (b), (c), and (d) are used in "~" (number of cycles), "B" (compensation value) (both in "APPENDIX B F2MC16LX Instruction Lists (351 Instructions)", and in "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Note:
If external data buses are used, add the number of cycles that are weighted with ready input and
automatic ready.
Table A-6 Compensation Values for Calculating The Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus (16-bit)
-
+3
External data bus (8-bit)
+3
-
Notes:
• If external data buses are used, add the number of cycles that are weighted with ready input and
automatic ready.
• Since all cases of program fetch do not delay the execution of instructions, use this compensation
value to calculate the worst case value.
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APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
This appendix lists the instructions used in assembler.
For items and symbols for each instruction list, see "APPENDIX A Explanation of
Instruction Lists".
B.1 Transfer Instructions
B.2 Numeric Data Operation Instructions
B.3 Logical Data Operation Instruction
B.4 Shift Instruction
B.5 Branch Instructions
B.6 Other Instructions
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F2MC-16LX Family
B.1
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Transfer Instructions
Table B-1and Table B-2lists the transfer instructions of the F2MC-16LX.
• Transfer instruction (Byte): 41 instructions in Table B-1
• Transfer instruction (Word/Long-word): 38 instructions in Table B-1
■ Transfer Instructions
Table B-1 Transfer Instruction (Byte): 41 Instructions
Mnemonic
#
~
RG
B
MOV
A,dir
2
3
0
(b)
MOV
A,addr16
3
4
0
(b)
MOV
A,Ri
1
2
1
0
MOV
A,ear
2
2
1
0
MOV
A,eam
2+
3 + (a)
0
(b)
MOV
A,io
2
3
0
(b)
MOV
A,#imm8
2
2
0
0
MOV
A,@A
2
3
0
(b)
MOV
A,@RLi+disp8
3
10
2
(b)
MOVN
A,#imm4
1
1
0
0
MOVX
A,dir
2
3
0
(b)
MOVX
A,addr16
3
4
0
(b)
MOVX
A,Ri
2
2
1
0
MOVX
A,ear
2
2
1
0
MOVX
A,eam
2+
3 + (a)
0
(b)
MOVX
A,io
2
3
0
(b)
MOVX
A,#imm8
2
2
0
0
MOVX
A,@A
2
3
0
(b)
MOVX
A,@RWi+disp8
2
5
1
(b)
MOVX
A,@RLi+disp8
3
10
2
(b)
MOV
dir,A
2
3
0
(b)
MOV
addr16,A
3
4
0
(b)
MOV
Ri,A
1
2
1
0
MOV
ear,A
2
2
1
0
MOV
eam,A
2+
3 + (a)
0
(b)
MOV
io,A
2
3
0
(b)
MOV
@RLi+disp8,A
3
10
2
(b)
MOV
Ri,ear
2
3
2
0
MOV
Ri,eam
2+
4 + (a)
1
(b)
MOV
ear,Ri
2
4
2
0
MOV
eam,Ri
2+
5 + (a)
1
(b)
MOV
Ri,#imm8
2
2
1
0
MOV
io,#imm8
3
5
0
(b)
MOV
dir,#imm8
3
5
0
(b)
MOV
ear,#imm8
3
2
1
0
MOV
eam,#imm8
3+
4 + (a)
0
(b)
MOV
@AL,AH
2
3
0
(b)
XCH
A,ear
2
4
2
0
XCH
A,eam
2+
5 + (a)
0
2 × (b)
XCH
Ri,ear
2
7
4
0
XCH
Ri,eam
2+
9 + (a)
2
2 × (b)
Note: See Table A-4and Table A-5for information on (a) and (b) in the table.
CM44-00201-4E
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← (imm8)
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
FUJITSU MICROELECTRONICS LIMITED
357
APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Table B-2 Transfer Instruction (Word/Long-word): 38 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
MOVW
A,dir
2
3
0
(c)
word (A) ← (dir)
MOVW
A,addr16
3
4
0
(c)
word (A) ← (addr16)
MOVW
A,SP
1
1
0
0
word (A) ← (SP)
MOVW
A,RWi
1
2
1
0
word (A) ← (RWi)
MOVW
A,ear
2
2
1
0
word (A) ← (ear)
MOVW
A,eam
2+
3 + (a)
0
(c)
word (A) ← (eam)
MOVW
A,io
2
3
0
(c)
word (A) ← (io)
MOVW
A,@A
2
3
0
(c)
word (A) ← ((A))
MOVW
A,#imm16
3
2
2
0
word (A) ← imm16
MOVW
A,@RWi+disp8
2
5
1
(c)
word (A) ← ((RWi)+disp8)
MOVW
A,@RLi+disp8
3
10
2
(c)
word (A) ← ((RLi)+disp8)
MOVW
dir,A
2
3
0
(c)
word (dir) ← (A)
MOVW
addr16,A
3
4
0
(c)
word (addr16) ← (A)
MOVW
SP,A
1
1
0
0
word (SP) ← (A)
MOVW
RWi,A
1
2
1
0
word (RWi) ← (A)
MOVW
ear,A
2
2
1
0
word (ear) ← (A)
MOVW
eam,A
2+
3 + (a)
0
(c)
word (eam) ← (A)
MOVW
io,A
2
3
0
(c)
word (io) ← (A)
MOVW
@RWi+disp8,A
2
5
1
(c)
word ((RWi)+disp8) ← (A)
MOVW
@RLi+disp8,A
3
10
2
(c)
word ((RLi)+disp8) ← (A)
MOVW
RWi,ear
2
3
2
0
word (RWi) ← (ear)
MOVW
Rwi,eam
2+
4 + (a)
1
(c)
word (RWi) ← (eam)
MOVW
ear,Rwi
2
4
2
0
word (ear) ← (RWi)
MOVW
eam,Rwi
2+
5 + (a)
1
(c)
word (eam) ← (RWi)
MOVW
RWi,#imm16
3
2
1
0
word (RWi) ← imm16
MOVW
io,#imm16
4
5
0
(c)
word (io) ← imm16
MOVW
ear,#imm16
4
2
1
0
word (ear) ← imm16
MOVW
eam,#imm16
4+
4 + (a)
0
(c)
word (eam) ← imm16
MOVW
@AL,AH
2
3
0
(c)
word ((A)) ← (AH)
XCHW
A,ear
2
4
2
0
word (A) ↔ (ear)
XCHW
A,eam
2+
5 + (a)
0
2 × (c)
word (A) ↔ (eam)
XCHW
RWi, ear
2
7
4
0
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
XCHW
RWi, eam
2+
9 + (a)
2
2 × (c)
MOVL
A,ear
2
4
2
0
long (A) ← (ear)
MOVL
A,eam
2+
5 + (a)
0
(d)
long (A) ← (eam)
MOVL
A,#imm32
5
3
0
0
long (A) ← imm32
MOVL
ear,A
2
4
2
0
long (ear1) ← (A)
MOVL
eam,A
2+
5 + (a)
0
(d)
long(eam1) ← (A)
Note: See Table A-4and Table A-5for information on (a), (c) and (d) in the table.
358
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
B.2
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Numeric Data Operation Instructions
The numeric data operation instructions of the F2MC-16L are listed in the following five
tables:
• Table B-3for addition and subtraction (Byte/Word/Long-word) : 42 instructions
• Table B-4for increment and decrement (Byte/Word/Long-word) : 12 instructions
• Table B-5for compare (Byte/Word/Long-word) : 11 instructions
• Table B-6for unsigned multiplication and division : 11 instructions (Word/Long-word)
• Table B-7for signed multiplication and division : 11 instructions (Word/Long-word)
■ Numeric Data Operation Instructions
Table B-3 Addition and Subtraction (Byte/Word/Long-word): 42 Instructions
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
A
1
2
0
0
ADDW
A,ear
2
3
1
0
ADDW
A,eam
2+
4+(a)
0
(c)
ADDW
A,#imm16
3
2
0
0
ADDW
ear,A
2
3
2
0
ADDW
eam,A
2+
5+(a)
0
2 × (c)
ADDCW A,ear
2
3
1
0
ADDCW A,eam
2+
4+(a)
0
(c)
SUBW
A
1
2
0
0
SUBW
A,ear
2
3
1
0
SUBW
A,eam
2+
4+(a)
0
(c)
SUBW
A,#imm16
3
2
0
0
SUBW
ear,A
2
3
2
0
SUBW
eam,A
2+
5+(a)
0
2 × (c)
SUBCW A,ear
2
3
1
0
SUBCW A,eam
2+
4+(a)
0
(c)
ADDL
A,ear
2
6
2
0
ADDL
A,eam
2+
7+(a)
0
(d)
ADDL
A,#imm32
5
4
0
0
SUBL
A,ear
2
6
2
0
SUBL
A,eam
2+
7+(a)
0
(d)
SUBL
A,#imm32
5
4
0
0
Note: See Table A-4and Table A-5for information on (a) to (d) in the table.
CM44-00201-4E
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
FUJITSU MICROELECTRONICS LIMITED
359
APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Table B-4 Increment and Decrement (Byte/Word/Long-word): 12 Instructions
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note: See Table A-4and Table A-5for information on (a) to (d) in the table.
Table B-5 Compare (Byte/Word/Long-word): 11 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note: See Table A-4and Table A-5for information on (a) to (d) in the table.
360
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Table B-6 Unsigned Multiplication and Division: 11 Instructions (Word/Long-word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL)
Remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A)
Remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A)
Remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A)
Remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A)
Remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3 for zero-divide, 7 for overflow, 15 for normal
*2: 4 for zero-divide, 8 for overflow, 16 for normal
*3: 6 + (a) for zero-divide, 9 + (a) for overflow, 19 + (a) for normal
*4: 4 for zero-divide, 7 for overflow, 22 for normal
*5: 6 + (a) for zero-divide, 8 + (a) for overflow, 26 + (a) for normal
*6: (b) for zero-divide or overflow, 2 × (b) for normal
*7: (c) for zero-divide or overflow, 2 × (c) for normal
*8: 3 when byte (AH) is 0, 7 when byte (AH) is not 0
*9: 4 when byte (ear) is 0, 8 when byte (ear) is not 0
*10: 5 + (a) when byte (eam) is 0, 9 + (a) when byte (eam) is not 0
*11: 3 when word (AH) is 0, 11 when word (AH) is not 0
*12: 4 when word (ear) is 0, 12 when word (ear) is not 0
*13: 5 + (a) when word (eam) is 0, 13 + (a) when word (eam) is not 0
Note: See Table A-4and Table A-5for information on (a), (b) and (c) in the table.
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
361
APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Table B-7 Signed Multiplication and Division: 11 Instructions (Word/Long-word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL)
Remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A)
Remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A)
Remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A)
Remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A)
Remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3 for zero-divide, 8 or 18 for overflow, 18 for normal
4 for zero-divide, 11 or 22 for overflow, 23 for normal
5 + (a) for zero-divide, 12 + (a) or 23 + (a) for overflow, 24 + (a) for normal
If the dividend is positive: 4 for zero-divide, 12 or 30 for overflow, 31 for normal
If the dividend is negative: 4 for zero-divide, 12 or 31 for overflow, 32 for normal
*5: If the dividend is positive: 5 + (a) for zero-divide, 12 + (a) or 31 + (a) for overflow, 32 + (a) for normal
If the dividend is negative: 5 + (a) for zero-divide, 12 + (a) or 32 + (a) for overflow, 33 + (a) for normal
*6: (b) for zero-divide or overflow, 2 x (b) for normal
*7: (c) for zero-divide or overflow, 2 x (c) for normal
*8: 3 when byte (AH) is 0, 12 when the result is positive, 13 when the result is negative
*9: 4 when byte (ear) is 0, 13 when the result is positive, 14 when the result is negative
*10: 5 + (a) when byte (eam) is 0, 14 + (a) when the result is positive, 15 + (a) when the result is negative
*11: 3 when word (AH) is 0, 16 when the result is positive, 19 when the result is negative
*12: 4 when word (ear) is 0, 17 when the result is positive, 20 when the result is negative
*13: 5 + (a) when word (eam) is 0, 18 + (a) when the result is positive, 21 + (a) when the result is negative
Notes:
• There are two numbers of execution cycles when overflow occurs during execution of the DIV and DIVW instructions, depending on the number of execution cycles is
detected before or after operation.
• The content of AL is corrupted when overflow occurs during execution of the DIV and DIVW instructions.
• See Table A-4and Table A-5for information on (a), (b) and (c) in the table.
362
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
B.3
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Logical Data Operation Instruction
The logical data operation instructions of the F2MC-16L are listed in the following four
tables:
• Table B-8for logic 1 (Byte/Word): 39 instructions
• Table B-9for logic 2 (Long): 6 instructions
• Table B-10for sign inversion (Byte/Word): 6 instructions
• Table B-11for normalize instructions (Long): 1 instruction
■ Logical Operation Instruction
Table B-8 Logic 1 (Byte/Word): 39 Instructions (1 / 2)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
eam,A
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
363
APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Table B-8 Logic 1 (Byte/Word): 39 Instructions (2 / 2)
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
XORW
Mnemonic
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
RMW
Note: See Table A-4and Table A-5for information on (a), (b) and (c) in the table.
Table B-9 Logic 2 (Long): 6 Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
Operation
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note: See Table A-4and Table A-5for information on (a) and (d) in the table.
Table B-10 Sign Inversion (Byte/Word): 6 Instructions
Mnemonic
NEG
A
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
1
2
0
0
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
Note: See Table A-4and Table A-5for information on (a), ( b) and (c) in the table.
Table B-11 Normalize Instruction (Long): 1 Instruction
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift to the first bit which is set to 1
formerly placed
byte (R0) ← Number of shifts at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
Note: See Table A-4and Table A-5for information on (a), ( b) and (c) in the table.
364
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
B.4
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Shift Instruction
Table B-12lists 18 shift instructions of F2MC-16L.
■ Shift Instruction
Table B-12 Shift Instructions (Byte/Word/Long-word): 18 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
Mnemonic
A
2
2
0
0
byte (A) ← Right rotate with carry
Operation
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotate with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotate with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
*
-
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, R0)
-
-
-
-
*
*
*
-
*
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note: See Table A-4and Table A-5for information on (a) and (b) in the table.
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
365
APPENDIX
APPENDIX B
B.5
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Branch Instructions
The branch instructions of the F2MC-16L are listed in the following two tables:
• Table B-13for branch 1: 31 instructions
• Table B-14for branch 2: 19 instructions
■ Branch Instruction
Table B-13 Branch 1: 31 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
Mnemonic
rel
2
*1
0
0
Branch on (Z) = 1
Operation
-
-
-
-
-
-
-
-
-
-
BNZ/BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear)0-15, (PCB) ← (ear)16-23
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam)0-15, (PCB) ← (eam)16-23
-
-
-
-
-
-
-
-
-
-
word (PC) ← addr0-15, (PCB) ← addr16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when branch is made, 6 when branch is not made
*2: 3 × (c) + (b)
*3: Read the branched address (word)
*4: W: Save to stack (word), R: Read the branched address (word)
*5: Save to stack (word)
*6: W: Save to stack (long), R: Read the branched address (long)
*7: Save to stack (long)
Note: See Table A-4and Table A-5 for information on (a) to (d) in the table.
366
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Table B-14 Branch 2: 19 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
Branch on byte (ear) = (ear) - 1, (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
-
*
*
*
-
*
-
-
-
-
-
*
*
*
-
-
2 × (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
Branch on word (ear) = (ear) - 1, (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
At the entrance of function, save old frame pointers im
stack, set up new frame pointers, reserve area for local
pointers.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
At the exit of function, recover the old frame pointers from
the stack.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when branch is made, 4 when branch is not made
*2: 13 when branch is made, 12 when branch is not made
*3: 7 + (a) when branch is made, 6 + (a) when branch is not made
*4: 8 when branch is made, 7 when branch is not made
*5: 7 when branch is made, 6 when branch is not made
*6: 8 + (a) when branch is made, 7 + (a) when branch is not made
*7: 3 × (b) + 2 × (c) when the sequence is branched to the next interrupt request, 6 × (c) when returned from the current interruption
*8: 15 when the sequence is branched to the next interrupt request, 17 when returned from the current interruption
*9: Do not use the RWj + addressing mode for the CBNE/CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long)
Note: See Table A-4and Table A-5for information on (a) to (d) in the table.
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
367
APPENDIX
APPENDIX B
B.6
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Other Instructions
Other instructions of the F2MC-16L are listed in the following four tables:
• Table B-15for other control systems (Byte/Word/Long-word) : 28 instructions
• Table B-16for bit operation instructions: 21 instructions
• Table B-17for accumulator operation instructions (Byte/Word): 6 instructions
• Table B-18for string instructions: 10 instructions
■ Other Instructions
Table B-15 Other Control Systems (Byte/Word/Long-word): 28 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
PUSHW
Mnemonic
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
Operation
-
-
-
-
-
-
-
-
-
RMW
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP)
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switching instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag unchange setting
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix for common register banks
-
-
-
-
-
-
-
-
-
-
*1: 1 for PCB, ADB, SSB, USB, and SPB 2 for DTB and DPR
*2: 7 + 3 × (number of POP operations) + 2 × (number of the last register that operates POP), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (number of PUSH operations) - 3 × (number of the last register that operates PUSH), 8 when RLST = 0 (no transfer register)
*4: (number of POP operations) × c, or (number of PUSH operations) × c
*5: (number of POP operations), or (number of PUSH operations)
Note: See Table A-4and Table A-5for information on (a) and (c) in the table.
368
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
APPENDIX B
APPENDIX
F2MC-16LX Instruction Lists (351 Instructions)
Table B-16 Bit Operation Instruction: 21 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1, bit = 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when branch is made, 7 when branch is not made
*2: 7 when branch is made, 6 when branch is not made
*3: 10 when the condition is met, 9 when the condition is not met
*4: Undefined count
*5: Until the condition is met
Note: See Table A-5for information on (b) in the table.
Table B-17 Accumulator Operation Instruction (Byte/Word): 6 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte signed extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word signed extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
CM44-00201-4E
Operation
FUJITSU MICROELECTRONICS LIMITED
369
APPENDIX
APPENDIX B
F2MC-16LX Instruction Lists (351 Instructions)
F2MC-16LX Family
Table B-18 String Instruction : 10 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the data in the AL register matches the byte data specified by the AH register in the space that
is specified by bank
*2: 5 when RW0 is 0, 4 + 8 × (RW0) for otherwise
*3: (b) × (RW0) + (b) × (RW0):To access different areas for sources and destinations, calculate item (b) separately each other.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0):To access different areas for sources and destinations, calculate item (c) separately each other.
*7: (c) × n
*8: (b) × (RW0)
Notes: • m: RW0 value (counter value), n: Number of loops
•
370
See Table A-5for information on (b) and (c) in the table.
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
APPENDIX C
APPENDIX
F2MC-16LX Instruction Maps
APPENDIX C F2MC-16LX Instruction Maps
This appendix describes F2MC-16LX instruction maps.
C.1 Structure of the Instruction Map
C.2 Basic Page Map
C.3 Bit Operation Instruction Map
C.4 Character String Operation Instruction Map
C.5 2-byte Instruction Map
C.6 ea-type Instruction Map
C.7 MOVEA RWi, ea Instruction Map
C.8 MOV Ri, ea Instruction Map
C.9 MOVW RWi, ea Instruction Map
C.10 MOV ea, Ri Instruction Map
C.11 MOVW ea, RWi Instruction Map
C.12 XCH Ri, ea Instruction Map
C.13 XCHW RWi, ea Instruction Map
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
371
APPENDIX
APPENDIX C
C.1
F2MC-16LX Instruction Maps
F2MC-16LX Family
Structure of the Instruction Map
Since the instruction code of the F2MC-16LX consists of one- and two-byte instructions,
the instruction map consists of more than one page that can be used for one- and twobyte instructions.
■ Structure of the Instruction Map
Figure C-1shows the structure of the instruction map.
Figure C-1 Structure of the Instruction Map
Basic page map
Bit operation
instruction
Character string
operation
instruction
2-byte
instructions
: First byte
ea-type
instruction × 9
: Second byte
The instruction code is described on the basic page map for one-byte instructions (such as the NOP
instruction). For two-byte instructions (such as the MOVS instruction), see the basic page map to find the
name of the map that describes the second byte of the instruction code to be referenced next.
Figure C-2shows the relationship between actual instruction codes and instruction maps.
372
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
F2MC-16LX Family
APPENDIX C
APPENDIX
F2MC-16LX Instruction Maps
Figure C-2 Relationship Between Actual Instruction Codes and Instruction Maps
May not exist for
some instruction.
Instruction
code
The length varies
depending on
instructions.
First byte
Second byte
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*:
Extended page map is a generic name for bit operation instruction, character string
operation instruction, 2-byte instruction, and ea-type instruction. More than one extended
page map exists for each type of instruction.
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
373
APPENDIX
APPENDIX C
C.2
F2MC-16LX Instruction Maps
F2MC-16LX Family
Basic Page Map
Table C-1shows the basic page map.
374
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
JCTX
@A
NEG
LINK
SPB
ADB
DTB
PCB
FUJITSU MICROELECTRONICS LIMITED
SWAPW
ADDSP
#imm16
ASRW
+E A
LSRW
+F A
+D
EXTW
LSLW
+C A
ZEXTW
CMPL
A,
#imm32
NEGW
+B A
MULUW
A
XORW
A
ORW
A
ANDW
A
CMPW
A
CBNE
A,
#imm8, rel
MOVW
dir,
A
MOVW
A,
dir
MOVW
SP,
A
MOVW
A,
SP
MOVX
A,
dir
MOV
dir,
#imm8
MOVX
A,
#imm8
MOV
A,
#imm8
MOV
dir,
A
MOV
A,
dir
40
NOTW
A
XORW
A,
#imm16
ORW
A,
#imm16
ANDW
A,
#imm16
CMPW
A,
#imm16
PUSHW
rlst
PUSHW
PS
PUSHW
AH
PUSHW
A
MOVL
A,
#imm32
CWBNE
MOVW
A,
A,
#imm16, rel #imm16
SUBW
A,
#imm16
ADDW
A,
#imm16
NOT
A
XOR
A,
#imm8
OR
A,
#imm8
AND
A,
#imm8
CMP
A,
#imm8
SUBC
A
SUB
A,
#imm8
ADD
A,
#imm8
30
POPW
rlst
POPW
PS
POPW
AH
POPW
A
MOVW
addr16,
A
MOVW
A,
addr16
MOVW
io,
A
MOVW
A,
io
MOVX
A,
addr16
MOVW
io,
#imm16
MOVX
A,
io
MOV
io,
#imm8
MOV
addr16,
A
MOV
A,
addr16
MOV
io,
A
MOV
A,
io
50
ea
instruction
instruction
instruction
XCHW RWi, ea
instruction
instruction
2-byte
instruction
XCH Ri, ea
String operation
instruction
MOVW ea, RWi
MOV ea, Ri
instruction
MOVW RWi, ea
instruction
MOVW
A,
RW7
MOVW
A,
RW6
MOVW
A,
RW5
MOVW
A,
RW4
MOVW
A,
RW3
MOVW
RW7,
A
MOVW
RW6,
A
MOVW
RW5,
A
MOVW
RW4,
A
MOVW
RW3,
A
MOVW
RW2,
A
MOVW
A,
RW2
MOV Ri, ea
instruction
A,
RW1
MOVW
RW1,
A
MOVEA RWi, ea MOVW
MOV
R7,
A
MOV
R6,
A
MOV
R5,
A
MOV
R4,
A
MOV
R3,
A
MOV
R2,
A
MOV
R1,
A
MOV
R0,
A
90
MOVW
RW0,
A
MOV
A,
R7
MOV
A,
R6
MOV
A,
R5
MOV
A,
R4
MOV
A,
R3
MOV
A,
R2
MOV
A,
R1
MOV
A,
R0
80
MOVW
A,
RW0
instruction 9
ea
instruction 8
ea
instruction 7
ea
instruction 6
ea
instruction 5
ea
instruction 4
ea
instruction 3
ea
instruction 2
ea
instruction 1
70
Bit operation
RETI
INTP
addr24
INT
addr16
INT
#vct8
RET
RETP
CALLP
addr24
CALL
addr16
JMPP
addr24
JMP
addr16
JMP
@A
BRA
rel
60
MOVW
RW7,
#imm16
MOVW
RW6,
#imm16
MOVW
RW5,
#imm16
MOVW
RW4,
#imm16
MOVW
RW3,
#imm16
MOVW
RW2,
#imm16
MOVW
RW1,
#imm16
MOVW
RW0,
#imm16
MOV
R7,
#imm8
MOV
R6,
#imm8
MOV
R5,
#imm8
MOV
R4,
#imm8
MOV
R3,
#imm8
MOV
R2,
#imm8
MOV
R1,
#imm8
MOV
R0,
#imm8
A0
MOVN
A,
#imm4
D0
MOVN
A,
#imm4
A
@RW7+disp8
#imm4
@RW7+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW6+disp8
MOVW
@RW6+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW5+disp8
MOVW
@RW5+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW4+disp8
MOVW
@RW4+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW3+disp8
MOVW
@RW3+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW2+disp8
MOVW
@RW2+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW1+disp8
MOVW
@RW1+disp8, A,
MOVN
#imm4
MOVW
A,
MOVW
A
MOVN
@RW0+disp8, A,
MOVW
@RW0+disp8
MOVN
A,
@RW7+disp8 #imm4
MOVX
A
MOVN
A,
@RW6+disp8 #imm4
MOVX
A
MOVN
A,
@RW5+disp8 #imm4
MOVX
A
@RW4+disp8
MOVX
A
MOVN
A,
@RW3+disp8 #imm4
MOVX
A
MOVN
A,
@RW2+disp8 #imm4
MOVX
A
MOVN
A,
@RW1+disp8 #imm4
MOVX
A
@RW0+disp8
MOVX
A
C0
MOVW
A,
MOVX
A,
R7
MOVX
A,
R6
MOVX
A,
R5
MOVX
A,
R4
MOVX
A,
R3
MOVX
A,
R2
MOVX
A,
R1
MOVX
A,
R0
B0
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
E0
BHI
rel
BLS
rel
BGT
rel
BLE
rel
BGE
rel
BLT
rel
BNT
rel
BT
rel
BNV
rel
BV
rel
BP
rel
BN
rel
BNC/BHS
rel
BC/BLO
rel
BNZ/BNE
rel
BZ/BEQ
rel
F0
APPENDIX C
INTE
MOV
ILM,
#imm8
SUBW
A
ADDW
A
ADDL
A,
#imm32
SUBL
A,
#imm32
MULU
A
DIVU
A
OR
CCR,
#imm8
AND
CCR,
#imm8
CMP
A
ADDC
A
SUB
A,
dir
ADD
A,
dir
20
ADDSP
#imm8
SWAP
ZEXT
MOV
+A RP,
#imm8
+9
UNLINK
+8 #imm8
+7
+6
+5
+4
+3 A
EXT
SUBDC
A
NCC
CMR
10
ADDDC
INT9
NOP
+2 A
+1
+0
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ Basic Page Map
Table C-1 Basic Page Map
375
APPENDIX
APPENDIX C
C.3
F2MC-16LX Instruction Maps
F2MC-16LX Family
Bit Operation Instruction Map
Table C-2shows the bit operation instruction map.
376
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
dir:bp,
A
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
FUJITSU MICROELECTRONICS LIMITED
MOVB
MOVB
MOVB
MOVB
MOVB
dir:bp
+F A,
dir:bp
+E A,
dir:bp
+D A,
dir:bp
+C A,
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
30
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
40
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
50
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
60
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
70
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
80
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
A0
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
90
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
B0
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
C0
D0
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
E0
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
F0
APPENDIX C
dir:bp
+B A,
dir:bp
+A A,
dir:bp
+9 A,
dir:bp
+8 A,
io:bp
+7 A,
io:bp
+6 A,
io:bp
+5 A,
io:bp
+4 A,
io:bp
+3 A,
io:bp
+2 A,
io:bp
MOVB
dir:bp,
A
MOVB
ip:bp,
A
+1 A,
io:bp
+0 A,
MOVB
20
MOVB
ip:bp,
A
10
MOVB
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ Bit Operation Instruction Map
Table C-2 Bit Operation Instruction Map (First Byte = 6CH)
377
APPENDIX
APPENDIX C
C.4
F2MC-16LX Instruction Maps
F2MC-16LX Family
Character String Operation Instruction Map
Table C-2 Character String Operation Instruction Map
Table C-3shows the character string operation instruction map.
378
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
MOVSWD
SPB,
DTB
MOVSWD
SPB,
ADB
MOVSWI
SPB,
DTB
MOVSWI
SPB,
ADB
MOVSD
PCB,
DTB
CM44-00201-4E
MOVSD
PCB,
ADB
MOVSD
PCB,
SPB
MOVSD
DTB,
PCB
MOVSD
DTB,
DTB
MOVSD
DTB,
ADB
MOVSD
DTB,
SPB
MOVSD
ADB,
PCB
MOVSD
ADB,
DTB
MOVSD
ADB,
ADB
MOVSD
ADB,
SPB
MOVSD
SPB,
PCB
MOVSD
SPB,
DTB
MOVSD
SPB,
ADB
MOVSD
SPB,
SPB
MOVSI
PCB,
ADB
MOVSI
PCB,
SPB
MOVSI
DTB,
PCB
MOVSI
DTB,
DTB
MOVSI
DTB,
ADB
MOVSI
DTB,
SPB
MOVSI
ADB,
PCB
MOVSI
ADB,
DTB
MOVSI
ADB,
ADB
MOVSI
ADB,
SPB
FUJITSU MICROELECTRONICS LIMITED
MOVSI
SPB,
PCB
MOVSI
SPB,
DTB
MOVSI
SPB,
ADB
MOVSI
SPB,
SPB
MOVSWI
SPB,
SPB
MOVSWD
SPB,
SPB
MOVSWD
SPB,
PCB
MOVSWD
ADB,
SPB
MOVSWD
ADB,
ADB
MOVSWD
ADB,
DTB
MOVSWD
ADB,
PCB
MOVSWD
DTB,
SPB
MOVSWD
DTB,
ADB
40
50
60
70
SCEQI
SPB
SCEQI
ADB
SCEQI
DTB
SCEQI
PCB
80
SCEQD
SPB
SCEQD
ADB
SCEQD
DTB
SCEQD
PCB
90
SCWEQI
SPB
SCWEQI
ADB
SCWEQI
DTB
SCWEQI
PCB
A0
SCWEQD
SPB
SCWEQD
ADB
SCWEQD
DTB
SCWEQD
PCB
B0
FILSI
SPB
FILSI
ADB
FILSI
DTB
FILSI
PCB
C0
D0
FILSWI
SPB
FILSWI
ADB
FILSWI
DTB
FILSWI
PCB
E0
F0
APPENDIX C
MOVSWI
SPB,
PCB
MOVSWI
ADB,
SPB
MOVSWI
ADB,
ADB
MOVSWI
ADB,
DTB
MOVSWI
ADB,
PCB
MOVSWI
DTB,
SPB
MOVSWI
DTB,
ADB
MOVSWD
DTB,
DTB
MOVSWD
DTB,
PCB
MOVSWI
DTB,
PCB
MOVSWI
DTB,
DTB
MOVSWD
PCB,
SPB
MOVSWD
PCB,
ADB
MOVSWD
PCB,
DTB
MOVSWI
PCB,
SPB
MOVSWI
PCB,
ADB
MOVSWI
PCB,
DTB
MOVSWD
PCB,
PCB
MOVSI
PCB,
DTB
MOVSWI
PCB,
PCB
MOVSD
PCB,
PCB
30
MOVSI
PCB,
PCB
20
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ Character String Operation Instruction Map
Table C-3 Character String Operation Instruction Map (First Byte = 6EH)
379
APPENDIX
APPENDIX C
C.5
F2MC-16LX Instruction Maps
F2MC-16LX Family
2-byte Instruction Map
Table C-4shows the 2-byte instruction map.
380
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
MOV
DTB,
A
MOV
ADB,
A
MOV
SSB,
A
MOV
USB,
A
MOV
DPR,
A
MOV
@AL,
AH
MOVX
A,
@A
RORC
A
LSLL
A,
R0
MOVW
@AL,
AH
ASRL
A,
R0
LSRL
A,
R0
MOV
A,
ADB
MOV
A,
SSB
MOV
A,
USB
MOV
A,
DPR
MOV
A,
@A
MOV
A,
PCB
ROLC
A
LSLW
A,
R0
MOVW
A,
@A
ASRW
A,
R0
LSRW
A,
R0
10
MOV
A,
DTB
00
MOV
30
MOV
40
CM44-00201-4E
MOV
MOV
MOV
MOV
MOV
MOV
FUJITSU MICROELECTRONICS LIMITED
LSR
A,
R0
ASR
A,
R0
MOVW
MOVW
MOVW
MOVW
@RL3+disp8, A,
@RL3+disp8
A
MOVW
@RL2+disp8, A,
@RL2+disp8
A
MOVW
@RL1+disp8, A,
@RL1+disp8
A
50
60
DIV
A
MULW
A
MUL
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX C
NRML
A,
R0
LSL
A,
R0
MOVW
@RL0+disp8, A,
@RL0+disp8
A
MOVW
@RL3+disp8, A,
@RL3+disp8 A
@RL3+disp8
MOVX
A,
@RL2+disp8, A,
@RL2+disp8 A
@RL2+disp8
MOVX
A,
@RL1+disp8, A,
@RL1+disp8 A
@RL1+disp8
MOVX
A,
@RL0+disp8, A,
@RL0+disp8 A
@RL0+disp8
MOVX
A,
20
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ 2-byte Instruction Map
Table C-4 2-byte Instruction Map (First Byte = 6FH)
381
APPENDIX
APPENDIX C
C.6
F2MC-16LX Instruction Maps
F2MC-16LX Family
ea-type Instruction Map
ea-type instruction maps (first byte = 70H to first byte = 78H) are shown in the following
nine tables:
• Table C-5for ea-type instruction (1) (first byte = 70H)
• Table C-6for ea-type instruction (2) (first byte = 71H)
• Table C-7for ea-type instruction (3) (first byte = 72H)
• Table C-8for ea-type instruction (4) (first byte = 73H)
• Table C-9for ea-type instruction (5) (first byte = 74H)
• Table C-10for ea-type instruction (6) (first byte = 75H)
• Table C-11for ea-type instruction (7) (first byte = 76H)
• Table C-12for ea-type instruction (8) (first byte = 77H)
• Table C-13for ea-type instruction (9) (first byte = 78H)
382
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
20
SUBL
A,
@RW1+disp8 RL0
ADDL
A,
SUBL
A,
@RW2+disp8 RL1
ADDL
A,
SUBL
A,
@RW3+disp8 RL1
ADDL
A,
SUBL
A,
@RW4+disp8 RL2
ADDL
A,
SUBL
A,
@RW5+disp8 RL2
ADDL
A,
SUBL
A,
@RW6+disp8 RL3
ADDL
A,
SUBL
A,
@RW7+disp8 RL3
ADDL
A,
SUBL
A,
@RW0+disp16 @RW0
ADDL
A,
SUBL
A,
@RW1+disp16 @RW1
ADDL
A,
SUBL
A,
@RW2+disp16 @RW2
ADDL
A,
SUBL
A,
@RW3+disp16 @RW3
ADDL
A,
SUBL
A,
@RW0+RW7 @RW0+
ADDL
A,
SUBL
A,
@RW1+RW7 @RW1+
ADDL
A,
SUBL
A,
@PC+disp16 @RW2+
ADDL
A,
addr16
ADDL
+2 A,
RL1
ADDL
+3 A,
RL1
ADDL
+4 A,
RL2
ADDL
+5 A,
RL2
ADDL
+6 A,
RL3
ADDL
+7 A,
RL3
ADDL
+8 A,
@RW0
ADDL
+9 A,
@RW1
ADDL
+A A,
@RW2
ADDL
+B A,
@RW3
ADDL
+C A,
@RW0+
ADDL
+D A,
@RW1+
ADDL
+E A,
@RW2+
ADDL
+F A,
@RW3+
CWBNE
RW0,
40
CWBNE
RW1,
CWBNE
RW2,
CWBNE
RW3,
CWBNE
RW4,
CWBNE
RW5,
CWBNE
RW6,
CWBNE
RW7,
CWBNE
@RW0,
CWBNE
@RW1,
CWBNE
@RW2,
FUJITSU MICROELECTRONICS LIMITED
CWBNE
@RW3,
SUBL
A,
addr16
Use
prohibited
Use
prohibited
@PC+disp16
SUBL
A,
Use
prohibited
@RW1+RW7
SUBL
A,
Use
prohibited
@RW0+RW7
SUBL
A,
@RW3+disp16 #imm16, rel
SUBL
A,
@RW2+disp16 #imm16, rel
SUBL
A,
@RW1+disp16 #imm16, rel
SUBL
A,
@RW0+disp16 #imm16, rel
SUBL
A,
@RW7+disp8 #imm16, rel
SUBL
A,
@RW6+disp8 #imm16, rel
SUBL
A,
@RW5+disp8 #imm16, rel
SUBL
A,
@RW4+disp8 #imm16, rel
SUBL
A,
@RW3+disp8 #imm16, rel
SUBL
A,
@RW2+disp8 #imm16, rel
SUBL
A,
@RW1+disp8 #imm16, rel
SUBL
A,
@RW0+disp8 #imm16, rel
SUBL
A,
30
CMPL
60
80
#imm16, rel
CWBNE
addr16,
CMPL
A,
@RW3+
CMPL
A,
addr16
ANDL
A,
@RW3+
ANDL
A,
@PC+disp16 @RW2+
CMPL
A,
CWBNE
CMPL
@PC+disp16, A,
#imm16, rel
@RW2+
ANDL
A,
@RW1+RW7 @RW1+
CWBNE
CMPL
A,
ANDL
A,
@RW0+RW7 @RW0+
CMPL
@RW1+RW7, A,
#imm16, rel
@RW1+
CMPL
A,
CWBNE
CMPL
@RW0+RW7, A,
#imm16, rel
@RW0+
ANDL
A,
@RW3+disp16 @RW3
CMPL
A,
ANDL
A,
@RW2+disp16 @RW2
CMPL
A,
ANDL
A,
@RW1+disp16 @RW1
CMPL
A,
ANDL
A,
@RW0+disp16 @RW0
CMPL
A,
ANDL
A,
@RW7+disp8 RL3
CMPL
A,
ANDL
A,
@RW6+disp8 RL3
CMPL
A,
ANDL
A,
@RW5+disp8 RL2
CMPL
A,
ANDL
A,
@RW4+disp8 RL2
CMPL
A,
ANDL
A,
@RW3+disp8 RL1
CMPL
A,
ANDL
A,
@RW2+disp8 RL1
CMPL
A,
ANDL
A,
@RW1+disp8 RL0
CMPL
A,
ANDL
A,
@RW0+disp8 RL0
CMPL
A,
70
CMPL
@RW3+disp16, A,
#imm16, rel
@RW3
CWBNE
CMPL
@RW2+disp16, A,
#imm16, rel
@RW2
CWBNE
CMPL
@RW1+disp16, A,
#imm16, rel
@RW1
CWBNE
CMPL
@RW0+disp16, A,
#imm16, rel
@RW0
CWBNE
CMPL
@RW7+disp8, A,
#imm16, rel
RL3
CWBNE
CMPL
@RW6+disp8, A,
#imm16, rel
RL3
CWBNE
CMPL
@RW5+disp8, A,
#imm16, rel
RL2
CWBNE
CMPL
@RW4+disp8, A,
#imm16, rel
RL2
CWBNE
CMPL
@RW3+disp8, A,
#imm16, rel
RL1
CWBNE
CMPL
@RW2+disp8, A,
#imm16, rel
RL1
CWBNE
CMPL
@RW1+disp8, A,
#imm16, rel
RL0
CWBNE
@RW0+disp8, A,
#imm16, rel
RL0
CWBNE
50
A0
C0
XORL
A,
@RW3+disp16 @RW3
ORL
A,
XORL
A,
@RW2+disp16 @RW2
ORL
A,
XORL
A,
@RW1+disp16 @RW1
ORL
A,
XORL
A,
@RW0+disp16 @RW0
ORL
A,
XORL
A,
@RW7+disp8 RL3
ORL
A,
XORL
A,
@RW6+disp8 RL3
ORL
A,
XORL
A,
@RW5+disp8 RL2
ORL
A,
XORL
A,
@RW4+disp8 RL2
ORL
A,
XORL
A,
@RW3+disp8 RL1
ORL
A,
XORL
A,
@RW2+disp8 RL1
ORL
A,
XORL
A,
@RW1+disp8 RL0
ORL
A,
XORL
A,
@RW0+disp8 RL0
ORL
A,
B0
ANDL
A,
addr16
ORL
ORL
A,
A,
@RW3+ addr16
XORL
A,
@RW3+
ORL
XORL
ORL
A,
A,
A,
@PC+disp16 @RW2+ @PC+disp16 @RW2+
ANDL
A,
ORL
XORL
ORL
A,
A,
A,
@RW1+RW7 @RW1+ @RW1+RW7 @RW1+
ANDL
A,
ORL
XORL
ORL
A,
A,
A,
@RW0+RW7 @RW0+ @RW0+RW7 @RW0+
ANDL
A,
ORL
A,
@RW3+disp16 @RW3
ANDL
A,
ORL
A,
@RW2+disp16 @RW2
ANDL
A,
ORL
A,
@RW1+disp16 @RW1
ANDL
A,
ORL
A,
@RW0+disp16 @RW0
ANDL
A,
ORL
A,
@RW7+disp8 RL3
ANDL
A,
ORL
A,
@RW6+disp8 RL3
ANDL
A,
ORL
A,
@RW5+disp8 RL2
ANDL
A,
ORL
A,
@RW4+disp8 RL2
ANDL
A,
ORL
A,
@RW3+disp8 RL1
ANDL
A,
ORL
A,
@RW2+disp8 RL1
ANDL
A,
ORL
A,
@RW1+disp8 RL0
ANDL
A,
ORL
A,
@RW0+disp8 RL0
ANDL
A,
90
E0
XORL
A,
addr16
Use
prohibited
Use
prohibited
@PC+disp16
XORL
A,
Use
prohibited
@RW1+RW7
XORL
A,
Use
prohibited
@RW0+RW7
XORL
A,
CBNE
@RW3,
@RW3+disp16 #imm8, rel
XORL
A,
CBNE
@RW2,
@RW2+disp16 #imm8, rel
XORL
A,
CBNE
@RW1,
@RW1+disp16 #imm8, rel
XORL
A,
CBNE
@RW0,
@RW0+disp16 #imm8, rel
XORL
A,
CBNE
R7,
@RW7+disp8 #imm8, rel
XORL
A,
CBNE
R6,
@RW6+disp8 #imm8, rel
XORL
A,
CBNE
R5,
@RW5+disp8 #imm8, rel
XORL
A,
CBNE
R4,
@RW4+disp8 #imm8, rel
XORL
A,
CBNE
R3,
@RW3+disp8 #imm8, rel
XORL
A,
CBNE
R2,
@RW2+disp8 #imm8, rel
XORL
A,
CBNE
R1,
@RW1+disp8 #imm8, rel
XORL
A,
CBNE
R0,
@RW0+disp8 #imm8, rel
XORL
A,
D0
CBNE
addr16,
#imm8, rel
#imm8, rel
@PC+disp16,
CBNE
#imm8, rel
@RW1+RW7,
CBNE
#imm8, rel
@RW0+RW7,
CBNE
#imm8, rel
@RW3+disp16,
CBNE
#imm8, rel
@RW2+disp16,
CBNE
#imm8, rel
@RW1+disp16,
CBNE
#imm8, rel
@RW0+disp16,
CBNE
#imm8, rel
@RW7+disp8,
CBNE
#imm8, rel
@RW6+disp8,
CBNE
#imm8, rel
@RW5+disp8,
CBNE
#imm8, rel
@RW4+disp8,
CBNE
#imm8, rel
@RW3+disp8,
CBNE
#imm8, rel
@RW2+disp8,
CBNE
#imm8, rel
@RW1+disp8,
CBNE
#imm8, rel
@RW0+disp8,
CBNE
F0
APPENDIX C
SUBL
A,
@RW3+
ADDL
A,
SUBL
A,
@RW0+disp8 RL0
ADDL
A,
10
ADDL
+1 A,
RL0
RL0
+0 A,
ADDL
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ ea-type Instruction Map
Table C-5 ea-byte Instruction (1) (First Byte = 70H)
383
384
JMPP
CALLP
@@RW2+disp8 @RL1
JMPP
JMPP
+2 @RL1
JMPP
+3 @RL1
FUJITSU MICROELECTRONICS LIMITED
CALLP
INCL
@@RW0+RW7 @@RW0+ @@RW0+RW7 @RW0+
DECL
DECL
DECL
DECL
@RW3+
INCL
addr16
JMPP
JMPP
+F @@RW3+ @addr16
INCL
@RW3+
DECL
@PC+disp16 @RW2+
CALLP
CALLP
@@RW3+ @addr16
INCL
DECL
@RW1+RW7 @RW1+
INCL
@RW0+RW7 @RW0+
INCL
DECL
@RW3+disp16 @RW3
INCL
DECL
@RW2+disp16 @RW2
INCL
DECL
@RW1+disp16 @RW1
INCL
@RW0+disp16 @RW0
INCL
DECL
@RW7+disp8 RL3
INCL
DECL
@RW6+disp8 RL3
INCL
DECL
@RW5+disp8 RL2
INCL
@RW4+disp8 RL2
INCL
DECL
@RW3+disp8 RL1
INCL
DECL
@RW2+disp8 RL1
INCL
DECL
@RW1+disp8 RL0
INCL
JMPP
JMPP
CALLP
CALLP
INCL
+E @@RW2+ @@PC+disp16 @@RW2+ @@PC+disp16 @RW2+
JMPP
JMPP
CALLP
CALLP
INCL
+D @@RW1+ @@RW1+RW7 @@RW1+ @@RW1+RW7 @RW1+
+C @@RW0+
CALLP
JMPP
JMPP
+B @@RW3
INCL
@@RW2+disp16 @RW2
CALLP
JMPP
CALLP
@@RW2+disp16 @@RW2
DECL
60
@RW0+disp8 RL0
INCL
50
RL0
MOVL
RL2
MOVL
@RW0
MOVL
@RW0+
DECL
addr16
MOVL
A,
@RW3+
MOVL
@PC+disp16 A,
@RW2+
DECL
MOVL
@RW1+RW7 A,
@RW1+
DECL
@RW0+RW7 A,
DECL
MOVL
@RW3+disp16 A,
@RW3
DECL
MOVL
@RW2+disp16 A,
@RW2
DECL
MOVL
@RW1+disp16 A,
@RW1
DECL
@RW0+disp16 A,
DECL
MOVL
@RW7+disp8 A,
RL3
DECL
MOVL
@RW6+disp8 A,
RL3
DECL
MOVL
@RW5+disp8 A,
RL2
DECL
@RW4+disp8 A,
DECL
MOVL
@RW3+disp8 A,
RL1
DECL
MOVL
@RW2+disp8 A,
RL1
DECL
MOVL
@RW1+disp8 A,
RL0
DECL
80
MOVL
@RW0+disp8 A,
DECL
70
A0
MOV
MOV
R1,
#imm8
MOV
MOV
@RW3+disp8, R3,
A
#imm8
MOVEA
@RW7+disp8, A,
#imm8
RW7
MOV
@RW7+disp8, R7,
A
#imm8
MOVL
A,
addr16
MOVL
@RW3+,
A
MOVL
@RW2+,
@PC+disp16 A
MOVL
A,
MOVL
@RW1+,
@RW1+RW7 A
MOVL
A,
MOVL
@RW0+,
@RW0+RW7 A
MOVL
A,
MOVL
addr16,
A
MOV
@RW3+,
#imm8
MOV
@PC+disp16, @RW2+,
A
#imm8
MOVL
@RW0+
MOV
addr16,
#imm8
MOVEA
A,
@RW3+
MOVEA
@PC+disp16, A,
#imm8
@RW2+
MOV
MOVEA
@RW1+RW7, A,
#imm8
@RW1+
MOV
#imm8
#imm8
MOV
@RW1+RW7, @RW1+,
A
#imm8
MOVL
A
MOVEA
@RW0+RW7, A,
MOV
MOVEA
@RW3+disp16, A,
#imm8
@RW3
MOV
MOVEA
@RW2+disp16, A,
#imm8
@RW2
MOV
@RW0+RW7, @RW0+,
MOVL
MOV
MOV
@RW3+disp16, @RW3,
A
#imm8
MOVL
MOVL
MOV
@RW2+disp16, @RW2,
A
#imm8
MOVL
A,
@RW3,
@RW3+disp16 A
MOVL
@RW0
MOVEA
@RW1+disp16, A,
#imm8
@RW1
MOV
#imm8
MOVL
MOV
@RW1+disp16, @RW1,
A
#imm8
#imm8
A
MOV
@RW0+disp16, A,
@RW0+disp16, @RW0,
MOVL
MOVL
MOVEA
MOVEA
@RW6+disp8, A,
#imm8
RW6
MOV
MOV
MOV
@RW6+disp8, R6,
A
#imm8
MOVL
MOV
MOVEA
@RW5+disp8, A,
#imm8
RW5
RW4
MOV
MOVL
MOV
@RW5+disp8, R5,
A
#imm8
#imm8
#imm8
MOVEA
A
MOV
@RW4+disp8, A,
@RW4+disp8, R4,
MOVL
MOVL
MOV
MOVEA
@RW2+disp8, A,
#imm8
RW2
MOVEA
@RW3+disp8, A,
#imm8
RW3
MOV
MOVL
MOV
@RW2+disp8, R2,
A
#imm8
A
@RW1+disp8,
MOVEA
@RW1+disp8, A,
#imm8
RW1
RW0
#imm8
#imm8
MOVL
E0
MOVEA
A
MOV
D0
@RW0+disp8, A,
MOV
C0
@RW0+disp8, R0,
MOVL
B0
MOVL
@RW2,
@RW2+disp16 A
MOVL
A,
MOVL
@RW1,
@RW1+disp16 A
MOVL
A,
MOVL
@RW0,
@RW0+disp16 A
MOVL
A,
MOVL
RL3,
@RW7+disp8 A
MOVL
A,
MOVL
RL3,
@RW6+disp8 A
MOVL
A,
MOVL
RL2,
@RW5+disp8 A
MOVL
A,
MOVL
RL2,
@RW4+disp8 A
MOVL
A,
MOVL
RL1,
@RW3+disp8 A
MOVL
A,
MOVL
RL1,
@RW2+disp8 A
MOVL
A,
MOVL
RL0,
@RW1+disp8 A
MOVL
A,
MOVL
RL0,
@RW0+disp8 A
MOVL
A,
90
MOVEA
A,
addr16
@PC+disp16
MOVEA
A,
@RW1+RW7
MOVEA
A,
@RW0+RW7
MOVEA
A,
@RW3+disp16
MOVEA
A,
@RW2+disp16
MOVEA
A,
@RW1+disp16
MOVEA
A,
@RW0+disp16
MOVEA
A,
@RW7+disp8
MOVEA
A,
@RW6+disp8
MOVEA
A,
@RW5+disp8
MOVEA
A,
@RW4+disp8
MOVEA
A,
@RW3+disp8
MOVEA
A,
@RW2+disp8
MOVEA
A,
@RW1+disp8
MOVEA
A,
@RW0+disp8
MOVEA
A,
F0
F2MC-16LX Instruction Maps
JMPP
JMPP
JMPP
+A @@RW2
INCL
@@RW1+disp16 @RW1
CALLP
INCL
@@RW3+disp16 @RW3
CALLP
@@RW1+disp16 @@RW1
CALLP
JMPP
JMPP
+9 @@RW1
INCL
@@RW0+disp16 @RW0
CALLP
@@RW3+disp16 @@RW3
@@RW0+disp16 @@RW0
+8 @@RW0
CALLP
CALLP
INCL
@@RW6+disp8 RL3
CALLP
JMPP
JMPP
JMPP
+7 @RL3
JMPP
CALLP
@@RW6+disp8 @RL3
INCL
@@RW5+disp8 RL2
CALLP
INCL
@@RW7+disp8 RL3
JMPP
JMPP
+6 @RL3
INCL
@@RW4+disp8 RL2
CALLP
INCL
@@RW3+disp8 RL1
CALLP
INCL
@@RW2+disp8 RL1
CALLP
INCL
@@RW1+disp8 RL0
CALLP
CALLP
CALLP
@@RW5+disp8 @RL2
INCL
40
@@RW0+disp8 RL0
CALLP
30
CALLP
@@RW7+disp8 @RL3
JMPP
CALLP
JMPP
+5 @RL2
JMPP
@@RW4+disp8 @RL2
+4 @RL2
JMPP
CALLP
@@RW1+disp8 @RL0
CALLP
@@RW3+disp8 @RL1
JMPP
JMPP
+1 @RL0
CALLP
20
@@RW0+disp8 @RL0
JMPP
10
+0 @RL0
JMPP
00
APPENDIX
APPENDIX C
F2MC-16LX Family
Table C-6 ea-type Instruction (2) (First Byte = 71H)
CM44-00201-4E
CM44-00201-4E
RORC
@RW1+disp8 R1
ROLC
RORC
@RW2+disp8 R2
ROLC
ROLC
+2 R2
ROLC
+3 R3
ROLC
RORC
@RW5+disp8 R5
ROLC
ROLC
+5 R5
ROLC
+6 R6
RORC
@RW7+disp8 R7
ROLC
RORC
@RW0+disp16 @RW0
ROLC
RORC
@RW1+disp16 @RW1
ROLC
RORC
@RW2+disp16 @RW2
ROLC
RORC
@RW3+disp16 @RW3
ROLC
RORC
@RW0+RW7 @RW0+
ROLC
RORC
@RW1+RW7 @RW1+
ROLC
RORC
@PC+disp16 @RW2+
ROLC
addr16
ROLC
+8 @RW0
ROLC
+9 @RW1
ROLC
+A @RW2
ROLC
+B @RW3
ROLC
+C @RW0+
ROLC
+D @RW1+
ROLC
+E @RW2+
ROLC
+F @RW3+
INC
INC
R6
40
FUJITSU MICROELECTRONICS LIMITED
RORC
addr16
INC
@RW3+
INC
@PC+disp16 @RW2+
RORC
INC
@RW1+RW7 @RW1+
RORC
INC
@RW0+RW7 @RW0+
RORC
INC
@RW3+disp16 @RW3
RORC
INC
@RW2+disp16 @RW2
RORC
INC
@RW1+disp16 @RW1
RORC
INC
@RW0+disp16 @RW0
RORC
INC
@RW7+disp8 R7
RORC
@RW6+disp8
RORC
INC
@RW5+disp8 R5
RORC
INC
@RW4+disp8 R4
RORC
INC
@RW3+disp8 R3
RORC
INC
@RW2+disp8 R2
RORC
INC
@RW1+disp8 R1
RORC
@RW0+disp8 R0
RORC
30
INC
INC
addr16
DEC
@RW3+
DEC
@PC+disp16 @RW2+
INC
DEC
@RW1+RW7 @RW1+
INC
DEC
@RW0+RW7 @RW0+
INC
DEC
@RW3+disp16 @RW3
INC
DEC
@RW2+disp16 @RW2
INC
DEC
@RW1+disp16 @RW1
INC
DEC
@RW0+disp16 @RW0
INC
DEC
@RW7+disp8 R7
INC
DEC
@RW6+disp8 R6
INC
DEC
@RW5+disp8 R5
INC
DEC
@RW4+disp8 R4
INC
DEC
@RW3+disp8 R3
INC
DEC
@RW2+disp8 R2
INC
DEC
@RW1+disp8 R1
INC
60
DEC
@RW0+disp8 R0
50
R0
DEC
addr16
MOV
A,
@RW3+
MOV
@PC+disp16 A,
@RW2+
DEC
MOV
@RW1+RW7 A,
@RW1+
DEC
MOV
@RW0+RW7 A,
@RW0+
DEC
MOV
@RW3+disp16 A,
@RW3
DEC
MOV
@RW2+disp16 A,
@RW2
DEC
MOV
@RW1+disp16 A,
@RW1
DEC
MOV
@RW0+disp16 A,
@RW0
DEC
MOV
@RW7+disp8 A,
R7
DEC
MOV
@RW6+disp8 A,
R6
DEC
MOV
@RW5+disp8 A,
R5
DEC
MOV
@RW4+disp8 A,
R4
DEC
MOV
@RW3+disp8 A,
R3
DEC
MOV
@RW2+disp8 A,
R2
DEC
MOV
@RW1+disp8 A,
R1
DEC
80
MOV
@RW0+disp8 A,
DEC
70
A0
MOV
A,
addr16
MOV
@RW3+,
A
MOV
@RW2+,
@PC+disp16 A
MOV
A,
MOV
@RW1+,
@RW1+RW7 A
MOV
A,
MOV
@RW0+,
@RW0+RW7 A
MOV
A,
MOV
@RW3,
@RW3+disp16 A
MOV
A,
MOV
@RW2,
@RW2+disp16 A
MOV
A,
MOV
@RW1,
@RW1+disp16 A
MOV
A,
MOV
@RW0,
@RW0+disp16 A
MOV
A,
MOV
R7,
@RW7+disp8 A
MOV
A,
MOV
R6,
@RW6+disp8 A
MOV
A,
MOV
R5,
@RW5+disp8 A
MOV
A,
MOV
R4,
@RW4+disp8 A
MOV
A,
MOV
R3,
@RW3+disp8 A
MOV
A,
MOV
R2,
@RW2+disp8 A
MOV
A,
MOV
R1,
@RW1+disp8 A
MOV
A,
MOV
R0,
@RW0+disp8 A
MOV
A,
90
MOVX
A,
MOVX
MOVX
A,
XCH
A,
@RW2+disp8 R2
MOVX
A,
XCH
A,
@RW3+disp8 R3
MOVX
A,
XCH
A,
@RW4+disp8 R4
MOVX
A,
XCH
A,
@RW5+disp8 R5
MOVX
A,
XCH
A,
@RW6+disp8 R6
MOVX
A,
XCH
A,
@RW7+disp8 R7
MOVX
A,
XCH
A,
@RW0+disp16 @RW0
MOVX
A,
MOVX
@RW2+disp8, A,
A
R2
MOVX
@RW3+disp8, A,
A
R3
MOVX
@RW4+disp8, A,
A
R4
MOVX
@RW5+disp8, A,
A
R5
MOVX
@RW6+disp8, A,
A
R6
MOVX
@RW7+disp8, A,
A
R7
MOVX
@RW0+disp16, A,
A
@RW0
MOVX
@RW1+disp16, A,
A
@RW1
MOV
addr16,
A
MOVX
A,
@RW3+
MOVX
@PC+disp16, A,
A
@RW2+
MOV
MOVX
@RW1+RW7, A,
A
@RW1+
MOV
MOVX
@RW0+RW7, A,
A
@RW0+
MOV
MOVX
@RW3+disp16, A,
A
@RW3
MOV
MOVX
@RW2+disp16, A,
A
@RW2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
A,
addr16
XCH
A,
@RW3+
XCH
A,
@PC+disp16 @RW2+
MOVX
A,
XCH
A,
@RW1+RW7 @RW1+
MOVX
A,
XCH
A,
@RW0+RW7 @RW0+
MOVX
A,
XCH
A,
@RW3+disp16 @RW3
MOVX
A,
XCH
A,
@RW2+disp16 @RW2
MOVX
A,
XCH
A,
@RW1+disp16 @RW1
XCH
A,
@RW1+disp8 R1
R0
MOVX
A,
MOV
MOVX
@RW1+disp8, A,
A
R1
A
E0
XCH
A,
@RW0+disp8 R0
D0
C0
@RW0+disp8, A,
MOV
B0
XCH
A,
addr16
@PC+disp16
XCH
A,
@RW1+RW7
XCH
A,
@RW0+RW7
XCH
A,
@RW3+disp16
XCH
A,
@RW2+disp16
XCH
A,
@RW1+disp16
XCH
A,
@RW0+disp16
XCH
A,
@RW7+disp8
XCH
A,
@RW6+disp8
XCH
A,
@RW5+disp8
XCH
A,
@RW4+disp8
XCH
A,
@RW3+disp8
XCH
A,
@RW2+disp8
XCH
A,
@RW1+disp8
XCH
A,
@RW0+disp8
XCH
A,
F0
APPENDIX C
RORC
@RW3+
ROLC
ROLC
+7 R7
@RW6+disp8
RORC
@RW4+disp8 R4
RORC
R6
ROLC
ROLC
+4 R4
RORC
@RW3+disp8 R3
ROLC
RORC
ROLC
+1 R1
ROLC
@RW0+disp8 R0
ROLC
20
+0 R0
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
Table C-7 ea-type Instruction (3) (First Byte = 72H)
385
386
CALL
@@RW1+disp8 @RW1
JMP
CALL
@@RW2+disp8 @RW2
JMP
JMP
+2 @RW2
JMP
+3 @RW3
FUJITSU MICROELECTRONICS LIMITED
CALL
@@RW4+disp8 @RW4
JMP
CALL
@@RW5+disp8 @RW5
JMP
CALL
@@RW6+disp8 @RW6
JMP
CALL
@@RW7+disp8 @RW7
JMP
CALL
@@RW0+disp16 @@RW0
JMP
CALL
@@RW1+disp16 @@RW1
JMP
CALL
@@RW2+disp16 @@RW2
JMP
JMP
+5 @RW5
JMP
+6 @RW6
JMP
+7 @RW7
JMP
+8 @@RW0
JMP
+9 @@RW1
JMP
+A @@RW2
JMP
+B @@RW3
INCW
40
INCW
@@RW0+RW7 @RW0+
INCW
@@RW1+RW7 @RW1+
JMP
JMP
CALL
+D @@RW1+ @@RW1+RW7 @@RW1
+
DECW
60
DECW
DECW
@RW0+
DECW
@RW3+
@RW3+
@RW2+
INCW
addr16
DECW
addr16
MOVW
A,
INCW
@RW3+
CALL
@addr16
CALL
@@RW3
+
@PC+disp16 @RW2+
JMP
JMP
+F @@RW3+ @addr16
@RW1+
MOVW
@PC+disp16 A,
DECW
MOVW
@RW1+RW7 A,
DECW
MOVW
@RW0+RW7 A,
DECW
MOVW
@RW3+disp16 A,
@RW3
DECW
MOVW
@RW2+disp16 A,
@RW2
DECW
MOVW
@RW1+disp16 A,
@RW1
DECW
MOVW
@RW0+disp16 A,
@RW0
DECW
MOVW
@RW7+disp8 A,
RW7
DECW
MOVW
@RW6+disp8 A,
RW6
DECW
MOVW
@RW5+disp8 A,
RW5
DECW
MOVW
@RW4+disp8 A,
RW4
DECW
MOVW
@RW3+disp8 A,
RW3
DECW
MOVW
@RW2+disp8 A,
RW2
DECW
INCW
@@PC+disp16 @RW2+
DECW
RW0
MOVW
@RW1+disp8 A,
RW1
DECW
80
MOVW
@RW0+disp8 A,
DECW
70
CALL
INCW
@RW1+RW7 @RW1+
INCW
@RW0+RW7 @RW0+
INCW
DECW
@RW3+disp16 @RW3
INCW
DECW
@RW2+disp16 @RW2
INCW
DECW
@RW1+disp16 @RW1
INCW
DECW
@RW0+disp16 @RW0
INCW
DECW
@RW7+disp8 RW7
INCW
DECW
@RW6+disp8 RW6
INCW
DECW
@RW5+disp8 RW5
INCW
DECW
@RW4+disp8 RW4
INCW
DECW
@RW3+disp8 RW3
INCW
DECW
@RW2+disp8 RW2
INCW
DECW
@RW1+disp8 RW1
INCW
@RW0+disp8 RW0
INCW
50
JMP
JMP
CALL
+E @@RW2+ @@PC+disp16 @@RW2
+
CALL
CALL
INCW
@@RW3+disp16 @RW3
CALL
INCW
@@RW2+disp16 @RW2
CALL
INCW
@@RW1+disp16 @RW1
CALL
INCW
@@RW0+disp16 @RW0
CALL
INCW
@@RW7+disp8 RW7
CALL
INCW
@@RW6+disp8 RW6
CALL
INCW
@@RW5+disp8 RW5
CALL
INCW
@@RW4+disp8 RW4
CALL
INCW
@@RW3+disp8 RW3
CALL
INCW
@@RW2+disp8 RW2
CALL
INCW
@@RW1+disp8 RW1
CALL
@@RW0+disp8 RW0
CALL
30
A0
MOVW
@RW0,
A
MOVW
A,
addr16
MOVW
@RW3+,
A
MOVW
@RW2+,
@PC+disp16 A
MOVW
A,
MOVW
@RW1+,
@RW1+RW7 A
MOVW
A,
MOVW
@RW0+,
@RW0+RW7 A
MOVW
A,
MOVW
@RW3,
@RW3+disp16 A
MOVW
A,
MOVW
@RW2,
@RW2+disp16 A
MOVW
A,
MOVW
@RW1,
@RW1+disp16 A
MOVW
A,
@RW0+disp16
MOVW
A,
MOVW
RW7,
@RW7+disp8 A
MOVW
A,
MOVW
RW6,
@RW6+disp8 A
MOVW
A,
MOVW
RW5,
@RW5+disp8 A
MOVW
A,
MOVW
RW4,
@RW4+disp8 A
MOVW
A,
MOVW
RW3,
@RW3+disp8 A
MOVW
A,
MOVW
RW2,
@RW2+disp8 A
MOVW
A,
MOVW
RW1,
@RW1+disp8 A
MOVW
A,
MOVW
RW0,
@RW0+disp8 A
MOVW
A,
90
XCHW
@RW7+disp8, A,
#imm16
RW7
XCHW
@RW0+disp16, A,
#imm16
@RW0
XCHW
@RW1+disp16, A,
#imm16
@RW1
MOVW
@RW0+disp16, @RW0,
A
#imm16
MOVW
@RW1+disp16, @RW1,
A
#imm16
MOVW
addr16,
A
MOVW
@RW3+,
#imm16
MOVW
@PC+disp16, @RW2+,
A
#imm16
MOVW
MOVW
@RW1+RW7, @RW1+,
A
#imm16
MOVW
MOVW
@RW0+RW7, @RW0+,
A
#imm16
MOVW
MOVW
@RW3+disp16, @RW3,
A
#imm16
MOVW
MOVW
@RW2+disp16, @RW2,
A
#imm16
MOVW
MOVW
MOVW
MOVW
addr16,
#imm16
XCHW
A,
@RW3+
XCHW
@PC+disp16, A,
#imm16
@RW2+
MOVW
XCHW
@RW1+RW7, A,
@RW1+
#imm16
MOVW
XCHW
@RW0+RW7, A,
#imm16
@RW0+
MOVW
XCHW
@RW3+disp16, A,
#imm16
@RW3
MOVW
XCHW
@RW2+disp16, A,
#imm16
@RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
@RW7+disp8, RW7,
A
#imm16
XCHW
A,
RW5
XCHW
A,
RW4
XCHW
A,
RW3
XCHW
A,
RW2
XCHW
A,
RW1
XCHW
@RW6+disp8, A,
#imm16
RW6
#imm16
@RW5+disp8,
MOVW
#imm16
@RW4+disp8,
MOVW
#imm16
@RW3+disp8,
MOVW
#imm16
@RW2+disp8,
MOVW
#imm16
@RW1+disp8,
MOVW
#imm16
XCHW
A,
RW0
E0
MOVW
MOVW
RW5,
#imm16
MOVW
RW4,
#imm16
MOVW
RW3,
#imm16
MOVW
RW2,
#imm16
MOVW
RW1,
#imm16
MOVW
MOVW
RW0,
#imm16
@RW0+disp8,
D0
C0
MOVW
@RW6+disp8, RW6,
A
#imm16
A
@RW5+disp8,
MOVW
A
@RW4+disp8,
MOVW
A
@RW3+disp8,
MOVW
A
@RW2+disp8,
MOVW
A
@RW1+disp8,
MOVW
A
@RW0+disp8,
MOVW
B0
XCHW
A,
addr16
@PC+disp16
XCHW
A,
@RW1+RW7
XCHW
A,
@RW0+RW7
XCHW
A,
@RW3+disp16
XCHW
A,
@RW2+disp16
XCHW
A,
@RW1+disp16
XCHW
A,
@RW0+disp16
XCHW
A,
@RW7+disp8
XCHW
A,
@RW6+disp8
XCHW
A,
@RW5+disp8
XCHW
A,
@RW4+disp8
XCHW
A,
@RW3+disp8
XCHW
A,
@RW2+disp8
XCHW
A,
@RW1+disp8
XCHW
A,
@RW0+disp8
XCHW
A,
F0
F2MC-16LX Instruction Maps
JMP
JMP
CALL
+C @@RW0+ @@RW0+RW7 @@RW0
+
CALL
@@RW3+disp16 @@RW3
JMP
JMP
+4 @RW4
CALL
@@RW3+disp8 @RW3
JMP
JMP
+1 @RW1
CALL
20
@@RW0+disp8 @RW0
JMP
10
+0 @RW0
JMP
00
APPENDIX
APPENDIX C
F2MC-16LX Family
Table C-8 ea-type Instruction (4) (First Byte = 73H)
CM44-00201-4E
CM44-00201-4E
20
SUB
A,
@RW1+disp8 R1
ADD
A,
SUB
A,
@RW2+disp8 R2
ADD
A,
SUB
A,
@RW3+disp8 R3
ADD
A,
SUB
A,
@RW4+disp8 R4
ADD
A,
SUB
A,
@RW5+disp8 R5
ADD
A,
SUB
A,
@RW6+disp8 R6
ADD
A,
SUB
A,
@RW7+disp8 R7
ADD
A,
SUB
A,
@RW0+disp16 @RW0
ADD
A,
SUB
A,
@RW1+disp16 @RW1
ADD
A,
SUB
A,
@RW2+disp16 @RW2
ADD
A,
SUB
A,
@RW3+disp16 @RW3
ADD
A,
SUB
A,
@RW0+RW7 @RW0+
ADD
A,
SUB
A,
@RW1+RW7 @RW1+
ADD
A,
SUB
A,
@PC+disp16 @RW2+
ADD
A,
addr16
ADD
+2 A,
R2
ADD
+3 A,
R3
ADD
+4 A,
R4
ADD
+5 A,
R5
ADD
+6 A,
R6
ADD
+7 A,
R7
ADD
+8 A,
@RW0
ADD
+9 A,
@RW1
ADD
+A A,
@RW2
ADD
+B A,
@RW3
ADD
+C A,
@RW0+
ADD
+D A,
@RW1+
ADD
+E A,
@RW2+
ADD
+F A,
@RW3+
40
FUJITSU MICROELECTRONICS LIMITED
SUB
A,
addr16
ADDC
A,
@RW3+
ADDC
A,
@PC+disp16 @RW2+
SUB
A,
ADDC
A,
@RW1+RW7 @RW1+
SUB
A,
ADDC
A,
@RW0+RW7 @RW0+
SUB
A,
ADDC
A,
@RW3+disp16 @RW3
SUB
A,
ADDC
A,
@RW2+disp16 @RW2
SUB
A,
ADDC
A,
@RW1+disp16 @RW1
SUB
A,
ADDC
A,
@RW0+disp16 @RW0
SUB
A,
ADDC
A,
@RW7+disp8 R7
SUB
A,
ADDC
A,
@RW6+disp8 R6
SUB
A,
ADDC
A,
@RW5+disp8 R5
SUB
A,
ADDC
A,
@RW4+disp8 R4
SUB
A,
ADDC
A,
@RW3+disp8 R3
SUB
A,
ADDC
A,
@RW2+disp8 R2
SUB
A,
ADDC
A,
@RW1+disp8 R1
SUB
A,
ADDC
A,
@RW0+disp8 R0
SUB
A,
30
60
ADDC
A,
addr16
CMP
A,
@RW3+
CMP
A,
@PC+disp16 @RW2+
ADDC
A,
CMP
A,
@RW1+RW7 @RW1+
ADDC
A,
CMP
A,
@RW0+RW7 @RW0+
ADDC
A,
CMP
A,
@RW3+disp16 @RW3
ADDC
A,
CMP
A,
@RW2+disp16 @RW2
ADDC
A,
CMP
A,
@RW1+disp16 @RW1
ADDC
A,
CMP
A,
@RW0+disp16 @RW0
ADDC
A,
CMP
A,
@RW7+disp8 R7
ADDC
A,
CMP
A,
@RW6+disp8 R6
ADDC
A,
CMP
A,
@RW5+disp8 R5
ADDC
A,
CMP
A,
@RW4+disp8 R4
ADDC
A,
CMP
A,
@RW3+disp8 R3
ADDC
A,
CMP
A,
@RW2+disp8 R2
ADDC
A,
CMP
A,
@RW1+disp8 R1
ADDC
A,
CMP
A,
@RW0+disp8 R0
ADDC
A,
50
80
CMP
A,
addr16
AND
A,
@RW3+
AND
A,
@PC+disp16 @RW2+
CMP
A,
AND
A,
@RW1+RW7 @RW1+
CMP
A,
AND
A,
@RW0+RW7 @RW0+
CMP
A,
AND
A,
@RW3+disp16 @RW3
CMP
A,
AND
A,
@RW2+disp16 @RW2
CMP
A,
AND
A,
@RW1+disp16 @RW1
CMP
A,
AND
A,
@RW0+disp16 @RW0
CMP
A,
AND
A,
@RW7+disp8 R7
CMP
A,
AND
A,
@RW6+disp8 R6
CMP
A,
AND
A,
@RW5+disp8 R5
CMP
A,
AND
A,
@RW4+disp8 R4
CMP
A,
AND
A,
@RW3+disp8 R3
CMP
A,
AND
A,
@RW2+disp8 R2
CMP
A,
AND
A,
@RW1+disp8 R1
CMP
A,
AND
A,
@RW0+disp8 R0
CMP
A,
70
A0
AND
A,
addr16
OR
A,
@RW3+
OR
A,
@PC+disp16 @RW2+
AND
A,
OR
A,
@RW1+RW7 @RW1+
AND
A,
OR
A,
@RW0+RW7 @RW0+
AND
A,
OR
A,
@RW3+disp16 @RW3
AND
A,
OR
A,
@RW2+disp16 @RW2
AND
A,
OR
A,
@RW1+disp16 @RW1
AND
A,
OR
A,
@RW0+disp16 @RW0
AND
A,
OR
A,
@RW7+disp8 R7
AND
A,
OR
A,
@RW6+disp8 R6
AND
A,
OR
A,
@RW5+disp8 R5
AND
A,
OR
A,
@RW4+disp8 R4
AND
A,
OR
A,
@RW3+disp8 R3
AND
A,
OR
A,
@RW2+disp8 R2
AND
A,
OR
A,
@RW1+disp8 R1
AND
A,
OR
A,
@RW0+disp8 R0
AND
A,
90
C0
OR
A,
addr16
XOR
A,
@RW3+
XOR
A,
@PC+disp16 @RW2+
OR
A,
XOR
A,
@RW1+RW7 @RW1+
OR
A,
XOR
A,
@RW0+RW7 @RW0+
OR
A,
XOR
A,
@RW3+disp16 @RW3
OR
A,
XOR
A,
@RW2+disp16 @RW2
OR
A,
XOR
A,
@RW1+disp16 @RW1
OR
A,
XOR
A,
@RW0+disp16 @RW0
OR
A,
XOR
A,
@RW7+disp8 R7
OR
A,
XOR
A,
@RW6+disp8 R6
OR
A,
XOR
A,
@RW5+disp8 R5
OR
A,
XOR
A,
@RW4+disp8 R4
OR
A,
XOR
A,
@RW3+disp8 R3
OR
A,
XOR
A,
@RW2+disp8 R2
OR
A,
XOR
A,
@RW1+disp8 R1
OR
A,
XOR
A,
@RW0+disp8 R0
OR
A,
B0
E0
DBNZ
R1,
rel
XOR
A,
addr16
DBNZ
@RW3+,
rel
DBNZ
@RW2+,
@PC+disp16 rel
XOR
A,
DBNZ
@RW1+,
@RW1+RW7 rel
XOR
A,
DBNZ
@RW0+,
@RW0+RW7 rel
XOR
A,
DBNZ
@RW3,
@RW3+disp16 rel
XOR
A,
DBNZ
@RW2,
@RW2+disp16 rel
XOR
A,
DBNZ
@RW1,
@RW1+disp16 rel
XOR
A,
DBNZ
@RW0,
@RW0+disp16 rel
XOR
A,
DBNZ
R7,
@RW7+disp8 rel
XOR
A,
DBNZ
R6,
@RW6+disp8 rel
XOR
A,
DBNZ
R5,
@RW5+disp8 rel
XOR
A,
DBNZ
R4,
@RW4+disp8 rel
XOR
A,
DBNZ
R3,
@RW3+disp8 rel
XOR
A,
DBNZ
R2,
@RW2+disp8 rel
XOR
A,
@RW1+disp8
XOR
A,
DBNZ
R0,
@RW0+disp8 rel
XOR
A,
D0
DBNZ
addr16,
rel
rel
@PC+disp16,
DBNZ
rel
@RW1+RW7,
DBNZ
rel
@RW0+RW7,
DBNZ
rel
@RW3+disp16,
DBNZ
rel
@RW2+disp16,
DBNZ
rel
@RW1+disp16,
DBNZ
rel
@RW0+disp16,
DBNZ
rel
@RW7+disp8,
DBNZ
rel
@RW6+disp8,
DBNZ
rel
@RW5+disp8,
DBNZ
rel
@RW4+disp8,
DBNZ
rel
@RW3+disp8,
DBNZ
rel
@RW2+disp8,
DBNZ
rel
@RW1+disp8,
DBNZ
rel
@RW0+disp8,
DBNZ
F0
APPENDIX C
SUB
A,
@RW3+
ADD
A,
SUB
A,
@RW0+disp8 R0
ADD
A,
10
ADD
+1 A,
R1
R0
+0 A,
ADD
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
Table C-9 ea-type Instruction (5) (First Byte = 74H)
387
388
FUJITSU MICROELECTRONICS LIMITED
SUB
SUBC
@RW3+disp8, A,
A
R3
SUB
SUBC
@RW4+disp8, A,
A
R4
SUB
SUBC
@RW5+disp8, A,
A
R5
SUB
SUBC
@RW6+disp8, A,
A
R6
SUB
SUBC
@RW7+disp8, A,
A
R7
SUB
SUBC
@RW0+disp16, A,
A
@RW0
SUBC
@RW1+disp16, A,
A
@RW1
SUB
@RW3+disp8, R3,
A
A
ADD
SUB
@RW4+disp8, R4,
A
A
ADD
SUB
@RW5+disp8, R5,
A
A
ADD
SUB
@RW6+disp8, R6,
A
A
ADD
SUB
@RW7+disp8, R7,
A
A
ADD
SUB
@RW0+disp16, @RW0,
A
A
ADD
SUB
@RW1+disp16, @RW1,
A
A
ADD
SUB
@RW2+disp16, @RW2,
A
A
SUB
@RW3+disp16, @RW3,
A
A
ADD
+3 R3,
A
ADD
+4 R4,
A
ADD
+5 R5,
A
ADD
+6 R6,
A
ADD
+7 R7,
A
ADD
+8 @RW0,
A
ADD
+9 @RW1,
A
ADD
+A @RW2,
A
ADD
+B @RW3,
A
SUB
@PC+disp16, @RW2+,
A
A
ADD
addr16,
A
ADD
+F @RW3+,
A
SUB
@RW3+,
A
ADD
ADD
+E @RW2+,
A
@RW0+
SUB
addr16,
A
SUBC
A,
@RW3+
SUBC
@PC+disp16, A,
A
@RW2+
SUB
SUBC
@RW1+RW7, A,
A
@RW1+
SUB
A
A
SUB
@RW1+RW7, @RW1+,
A
A
ADD
A
SUBC
@RW0+RW7, A,
SUB
SUBC
@RW3+disp16, A,
A
@RW3
SUB
SUBC
@RW2+disp16, A,
A
@RW2
SUB
@RW0+RW7, @RW0+,
ADD
ADD
+D @RW1+,
A
A
+C @RW0+,
ADD
SUB
SUBC
@RW2+disp8, A,
A
R2
SUB
@RW2+disp8, R2,
A
A
SUBC
A,
addr16
@PC+disp16
SUBC
A,
@RW1+RW7
SUBC
A,
@RW0+RW7
SUBC
A,
@RW3+disp16
SUBC
A,
@RW2+disp16
SUBC
A,
@RW1+disp16
SUBC
A,
@RW0+disp16
SUBC
A,
@RW7+disp8
SUBC
A,
@RW6+disp8
SUBC
A,
@RW5+disp8
SUBC
A,
@RW4+disp8
SUBC
A,
@RW3+disp8
SUBC
A,
@RW2+disp8
SUBC
A,
@RW1+disp8
SUBC
A,
@RW0+disp8
SUBC
A,
50
AND
R0,
A
80
NEG
@RW3+
NEG
@RW2+
NEG
@RW1+
NEG
NEG
@RW0+
A
NEG
addr16
AND
@RW3+,
A
AND
@PC+disp16 @RW2+,
A
NEG
AND
@RW1+RW7 @RW1+,
A
NEG
@RW0+RW7 @RW0+,
AND
AND
@RW3+disp16 @RW3,
A
NEG
AND
@RW2+disp16 @RW2,
A
NEG
AND
@RW1+disp16 @RW1,
A
NEG
AND
@RW0+disp16 @RW0,
A
NEG
AND
@RW7+disp8 R7,
A
NEG
AND
@RW6+disp8 R6,
A
NEG
AND
@RW5+disp8 R5,
A
NEG
AND
@RW4+disp8 R4,
A
NEG
AND
@RW3+disp8 R3,
A
NEG
AND
@RW2+disp8 R2,
A
NEG
AND
@RW1+disp8 R1,
A
NEG
@RW0+disp8
NEG
70
NEG
@RW3
NEG
@RW2
NEG
@RW1
NEG
@RW0
NEG
R7
NEG
R6
NEG
R5
NEG
R4
NEG
R3
NEG
R2
NEG
R1
NEG
R0
60
OR
A
A0
OR
A
AND
addr16,
A
OR
@RW3+,
A
OR
@PC+disp16, @RW2+,
A
A
AND
OR
@RW1+RW7, @RW1+,
A
A
AND
A
@RW0+RW7, @RW0+,
AND
OR
@RW3+disp16, @RW3,
A
A
AND
OR
@RW2+disp16, @RW2,
A
A
AND
OR
@RW1+disp16, @RW1,
A
A
AND
OR
@RW0+disp16, @RW0,
A
A
AND
OR
@RW7+disp8, R7,
A
A
AND
OR
@RW6+disp8, R6,
A
A
AND
OR
@RW5+disp8, R5,
A
A
AND
OR
@RW4+disp8, R4,
A
A
AND
OR
@RW3+disp8, R3,
A
A
AND
OR
@RW2+disp8, R2,
A
A
AND
OR
@RW1+disp8, R1,
A
A
AND
A
@RW0+disp8, R0,
AND
90
OR
A
XOR
A
OR
addr16,
A
XOR
@RW3+,
A
XOR
@PC+disp16, @RW2+,
A
A
OR
XOR
@RW1+RW7, @RW1+,
A
A
OR
A
@RW0+RW7, @RW0+,
OR
XOR
@RW3+disp16, @RW3,
A
A
OR
XOR
@RW2+disp16, @RW2,
A
A
OR
XOR
@RW1+disp16, @RW1,
A
A
OR
XOR
@RW0+disp16, @RW0,
A
A
OR
XOR
@RW7+disp8, R7,
A
A
OR
XOR
@RW6+disp8, R6,
A
A
OR
XOR
@RW5+disp8, R5,
A
A
OR
XOR
@RW4+disp8, R4,
A
A
OR
XOR
@RW3+disp8, R3,
A
A
OR
XOR
@RW2+disp8, R2,
A
A
OR
XOR
@RW1+disp8, R1,
A
A
OR
A
C0
XOR
@RW0+disp8, R0,
B0
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
XOR
addr16,
A
A
NOT
@RW3+
@PC+disp16, @RW2+
XOR
A
@RW1+RW7, @RW1+
XOR
A
@RW0+RW7, @RW0+
XOR
A
@RW3+disp16, @RW3
XOR
A
@RW2+disp16, @RW2
XOR
A
@RW1+disp16, @RW1
XOR
A
@RW0+disp16, @RW0
XOR
A
@RW7+disp8, R7
XOR
A
@RW6+disp8, R6
XOR
A
@RW5+disp8, R5
XOR
A
@RW4+disp8, R4
XOR
A
@RW3+disp8, R3
XOR
A
@RW2+disp8, R2
XOR
A
@RW1+disp8, R1
XOR
A
E0
NOT
@RW0+disp8, R0
XOR
D0
NOT
addr16
@PC+disp16
NOT
@RW1+RW7
NOT
@RW0+RW7
NOT
@RW3+disp16
NOT
@RW2+disp16
NOT
@RW1+disp16
NOT
@RW0+disp16
NOT
@RW7+disp8
NOT
@RW6+disp8
NOT
@RW5+disp8
NOT
@RW4+disp8
NOT
@RW3+disp8
NOT
@RW2+disp8
NOT
@RW1+disp8
NOT
@RW0+disp8
NOT
F0
F2MC-16LX Instruction Maps
ADD
SUB
ADD
ADD
+2 R2,
A
SUB
SUBC
@RW1+disp8, A,
A
R1
ADD
SUB
SUB
@RW1+disp8, R1,
A
A
R0
A
ADD
A
40
SUBC
A
SUB
30
@RW0+disp8, A,
SUB
20
@RW0+disp8, R0,
ADD
10
ADD
+1 R1,
A
A
+0 R0,
ADD
00
APPENDIX
APPENDIX C
F2MC-16LX Family
Table C-10 ea-type Instruction (6) (First Byte = 75H)
CM44-00201-4E
CM44-00201-4E
SUBW
A,
@RW1+disp8 RW1
ADDW
A,
SUBW
A,
@RW2+disp8 RW2
ADDW
A,
SUBW
A,
@RW3+disp8 RW3
ADDW
A,
SUBW
A,
@RW4+disp8 RW4
ADDW
A,
SUBW
A,
@RW5+disp8 RW5
ADDW
A,
SUBW
A,
@RW6+disp8 RW6
ADDW
A,
SUBW
A,
@RW7+disp8 RW7
ADDW
A,
ADDW
A,
ADDW
+2 A,
RW2
ADDW
+3 A,
RW3
ADDW
+4 A,
RW4
ADDW
+5 A,
RW5
ADDW
+6 A,
RW6
ADDW
+7 A,
RW7
ADDW
+8 A,
@RW0
ADDW
SUBW
A,
@RW2+disp16 @RW2
ADDW
A,
SUBW
A,
@RW3+disp16 @RW3
ADDW
A,
SUBW
A,
@RW0+RW7 @RW0+
ADDW
A,
SUBW
A,
@RW1+RW7 @RW1+
ADDW
A,
SUBW
A,
@PC+disp16 @RW2+
ADDW
A,
addr16
ADDW
+A A,
@RW2
ADDW
+B A,
@RW3
ADDW
+C A,
@RW0+
ADDW
+D A,
@RW1+
ADDW
+E A,
@RW2+
ADDW
+F A,
@RW3+
40
FUJITSU MICROELECTRONICS LIMITED
SUBW
A,
addr16
ADDCW
A,
@RW3+
ADDCW
A,
@PC+disp16 @RW2+
SUBW
A,
ADDCW
A,
@RW1+RW7 @RW1+
SUBW
A,
ADDCW
A,
@RW0+RW7 @RW0+
SUBW
A,
ADDCW
A,
@RW3+disp16 @RW3
SUBW
A,
ADDCW
A,
@RW2+disp16 @RW2
SUBW
A,
ADDCW
A,
@RW1+disp16 @RW1
SUBW
A,
ADDCW
A,
@RW0+disp16 @RW0
SUBW
A,
ADDCW
A,
@RW7+disp8 RW7
SUBW
A,
ADDCW
A,
@RW6+disp8 RW6
SUBW
A,
ADDCW
A,
@RW5+disp8 RW5
SUBW
A,
ADDCW
A,
@RW4+disp8 RW4
SUBW
A,
ADDCW
A,
@RW3+disp8 RW3
SUBW
A,
ADDCW
A,
@RW2+disp8 RW2
SUBW
A,
ADDCW
A,
@RW1+disp8 RW1
SUBW
A,
ADDCW
A,
@RW0+disp8 RW0
SUBW
A,
30
60
ADDCW
A,
addr16
CMPW
A,
@RW3+
CMPW
A,
@PC+disp16 @RW2+
ADDCW
A,
CMPW
A,
@RW1+RW7 @RW1+
ADDCW
A,
CMPW
A,
@RW0+RW7 @RW0+
ADDCW
A,
CMPW
A,
@RW3+disp16 @RW3
ADDCW
A,
CMPW
A,
@RW2+disp16 @RW2
ADDCW
A,
CMPW
A,
@RW1+disp16 @RW1
ADDCW
A,
CMPW
A,
@RW0+disp16 @RW0
ADDCW
A,
CMPW
A,
@RW7+disp8 RW7
ADDCW
A,
CMPW
A,
@RW6+disp8 RW6
ADDCW
A,
CMPW
A,
@RW5+disp8 RW5
ADDCW
A,
CMPW
A,
@RW4+disp8 RW4
ADDCW
A,
CMPW
A,
@RW3+disp8 RW3
ADDCW
A,
CMPW
A,
@RW2+disp8 RW2
ADDCW
A,
CMPW
A,
@RW1+disp8 RW1
ADDCW
A,
CMPW
A,
@RW0+disp8 RW0
ADDCW
A,
50
80
CMPW
A,
addr16
ANDW
A,
@RW3+
ANDW
A,
@PC+disp16 @RW2+
CMPW
A,
ANDW
A,
@RW1+RW7 @RW1+
CMPW
A,
ANDW
A,
@RW0+RW7 @RW0+
CMPW
A,
ANDW
A,
@RW3+disp16 @RW3
CMPW
A,
ANDW
A,
@RW2+disp16 @RW2
CMPW
A,
ANDW
A,
@RW1+disp16 @RW1
CMPW
A,
ANDW
A,
@RW0+disp16 @RW0
CMPW
A,
ANDW
A,
@RW7+disp8 RW7
CMPW
A,
ANDW
A,
@RW6+disp8 RW6
CMPW
A,
ANDW
A,
@RW5+disp8 RW5
CMPW
A,
ANDW
A,
@RW4+disp8 RW4
CMPW
A,
ANDW
A,
@RW3+disp8 RW3
CMPW
A,
ANDW
A,
@RW2+disp8 RW2
CMPW
A,
ANDW
A,
@RW1+disp8 RW1
CMPW
A,
ANDW
A,
@RW0+disp8 RW0
CMPW
A,
70
A0
ANDW
A,
addr16
ORW
A,
@RW3+
ORW
A,
@PC+disp16 @RW2+
ANDW
A,
ORW
A,
@RW1+RW7 @RW1+
ANDW
A,
ORW
A,
@RW0+RW7 @RW0+
ANDW
A,
ORW
A,
@RW3+disp16 @RW3
ANDW
A,
ORW
A,
@RW2+disp16 @RW2
ANDW
A,
ORW
A,
@RW1+disp16 @RW1
ANDW
A,
ORW
A,
@RW0+disp16 @RW0
ANDW
A,
ORW
A,
@RW7+disp8 RW7
ANDW
A,
ORW
A,
@RW6+disp8 RW6
ANDW
A,
ORW
A,
@RW5+disp8 RW5
ANDW
A,
ORW
A,
@RW4+disp8 RW4
ANDW
A,
ORW
A,
@RW3+disp8 RW3
ANDW
A,
ORW
A,
@RW2+disp8 RW2
ANDW
A,
ORW
A,
@RW1+disp8 RW1
ANDW
A,
ORW
A,
@RW0+disp8 RW0
ANDW
A,
90
C0
ORW
A,
addr16
XORW
A,
@RW3+
XORW
A,
@PC+disp16 @RW2+
ORW
A,
XORW
A,
@RW1+RW7 @RW1+
ORW
A,
XORW
A,
@RW0+RW7 @RW0+
ORW
A,
XORW
A,
@RW3+disp16 @RW3
ORW
A,
XORW
A,
@RW2+disp16 @RW2
ORW
A,
XORW
A,
@RW1+disp16 @RW1
ORW
A,
XORW
A,
@RW0+disp16 @RW0
ORW
A,
XORW
A,
@RW7+disp8 RW7
ORW
A,
XORW
A,
@RW6+disp8 RW6
ORW
A,
XORW
A,
@RW5+disp8 RW5
ORW
A,
XORW
A,
@RW4+disp8 RW4
ORW
A,
XORW
A,
@RW3+disp8 RW3
ORW
A,
XORW
A,
@RW2+disp8 RW2
ORW
A,
XORW
A,
@RW1+disp8 RW1
ORW
A,
XORW
A,
@RW0+disp8 RW0
ORW
A,
B0
E0
XORW
A,
addr16
DWBNZ
@RW3+,
rel
DWBNZ
@RW2+,
@PC+disp16 rel
XORW
A,
DWBNZ
@RW1+,
@RW1+RW7 rel
XORW
A,
DWBNZ
@RW0+,
@RW0+RW7 rel
XORW
A,
DWBNZ
@RW3,
@RW3+disp16 rel
XORW
A,
DWBNZ
@RW2,
@RW2+disp16 rel
XORW
A,
DWBNZ
@RW1,
@RW1+disp16 rel
XORW
A,
DWBNZ
@RW0,
@RW0+disp16 rel
XORW
A,
DWBNZ
RW7,
@RW7+disp8 rel
XORW
A,
DWBNZ
RW6,
@RW6+disp8 rel
XORW
A,
DWBNZ
RW5,
@RW5+disp8 rel
XORW
A,
DWBNZ
RW4,
@RW4+disp8 rel
XORW
A,
DWBNZ
RW3,
@RW3+disp8 rel
XORW
A,
DWBNZ
RW2,
@RW2+disp8 rel
XORW
A,
DWBNZ
RW1,
@RW1+disp8 rel
XORW
A,
DWBNZ
RW0,
@RW0+disp8 rel
XORW
A,
D0
DWBNZ
addr16,
rel
rel
@PC+disp16,
DWBNZ
rel
@RW1+RW7,
DWBNZ
rel
@RW0+RW7,
DWBNZ
rel
@RW3+disp16,
DWBNZ
rel
@RW2+disp16,
DWBNZ
rel
@RW1+disp16,
DWBNZ
@RW0+disp16,
rel
DWBNZ
rel
@RW7+disp8,
DWBNZ
rel
@RW6+disp8,
DWBNZ
rel
@RW5+disp8,
DWBNZ
rel
@RW4+disp8,
DWBNZ
rel
@RW3+disp8,
DWBNZ
rel
@RW2+disp8,
DWBNZ
rel
@RW1+disp8,
DWBNZ
rel
@RW0+disp8,
DWBNZ
F0
APPENDIX C
SUBW
A,
@RW3+
ADDW
A,
@RW1
+9 A,
SUBW
A,
@RW1+disp16 @RW1
SUBW
A,
@RW0+disp16 @RW0
ADDW
A,
ADDW
+1 A,
RW1
RW0
20
SUBW
A,
@RW0+disp8 RW0
ADDW
A,
ADDW
+0 A,
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
Table C-11 ea-type Instruction (7) (First Byte = 76H)
389
390
SUBW
@RW2+disp8, RW2,
A
A
ADDW
ADDW
+3 RW3,
A
ADDW
FUJITSU MICROELECTRONICS LIMITED
SUBW
@RW3+disp16, @RW3,
A
A
ADDW
+B @RW3,
A
ADDW
ADDW
SUBW
@PC+disp16, @RW2+,
A
A
ADDW
addr16,
A
ADDW
+E @RW2+,
A
ADDW
+F @RW3+,
A
SUBW
@RW3+,
A
SUBW
@RW1+RW7, @RW1+,
A
A
ADDW
A
@RW0+RW7,
ADDW
+D @RW1+,
A
A
+C @RW0+,
SUBW
@RW0+,
A
SUBW
@RW2+disp16, @RW2,
A
A
SUBCW
A,
@RW0+
SUBW
addr16,
A
SUBCW
A,
@RW3+
SUBCW
@PC+disp16, A,
A
@RW2+
SUBW
SUBCW
@RW1+RW7, A,
A
@RW1+
SUBW
A
@RW0+RW7,
SUBW
SUBCW
@RW3+disp16, A,
A
@RW3
SUBW
SUBCW
@RW2+disp16, A,
A
@RW2
SUBW
SUBCW
@RW1+disp16, A,
A
@RW1
@RW0
SUBCW
A,
addr16
@PC+disp16
SUBCW
A,
@RW1+RW7
SUBCW
A,
@RW0+RW7
SUBCW
A,
@RW3+disp16
SUBCW
A,
@RW2+disp16
SUBCW
A,
@RW1+disp16
SUBCW
A,
@RW0+disp16
SUBCW
A,
@RW7+disp8
SUBCW
A,
@RW6+disp8
SUBCW
A,
@RW5+disp8
SUBCW
A,
@RW4+disp8
SUBCW
A,
@RW3+disp8
SUBCW
A,
@RW2+disp8
SUBCW
A,
@RW1+disp8
SUBCW
A,
@RW0+disp8
SUBCW
A,
50
ANDW
RW0,
A
80
ANDW
RW4,
A
ANDW
A
NEGW
@RW3+
NEGW
@RW2+
NEGW
@RW1+
NEGW
addr16
@PC+disp16
NEGW
@RW1+RW7
NEGW
ANDW
@RW3+,
A
ANDW
@RW2+,
A
ANDW
@RW1+,
A
ANDW
@RW0+,
A
NEGW
NEGW
@RW0+
@RW0+RW7
ANDW
@RW3+disp16 @RW3,
A
NEGW
ANDW
@RW2+disp16 @RW2,
A
NEGW
ANDW
@RW1+disp16 @RW1,
A
NEGW
@RW0+disp16 @RW0,
NEGW
ANDW
@RW7+disp8 RW7,
A
NEGW
ANDW
@RW6+disp8 RW6,
A
NEGW
ANDW
@RW5+disp8 RW5,
A
NEGW
@RW4+disp8
NEGW
ANDW
@RW3+disp8 RW3,
A
NEGW
ANDW
@RW2+disp8 RW2,
A
NEGW
ANDW
@RW1+disp8 RW1,
A
NEGW
@RW0+disp8
NEGW
70
NEGW
@RW3
NEGW
@RW2
NEGW
@RW1
NEGW
@RW0
NEGW
RW7
NEGW
RW6
NEGW
RW5
NEGW
RW4
NEGW
RW3
NEGW
RW2
NEGW
RW1
NEGW
RW0
60
ORW
A0
A
ORW
A
ORW
A
ORW
@RW0+,
A
ANDW
addr16,
A
ORW
@RW3+,
A
ORW
@PC+disp16, @RW2+,
A
A
ANDW
ORW
@RW1+RW7, @RW1+,
A
A
ANDW
A
@RW0+RW7,
ANDW
ORW
@RW3+disp16, @RW3,
A
A
ANDW
ORW
@RW2+disp16, @RW2,
A
A
ANDW
ORW
@RW1+disp16, @RW1,
A
A
ANDW
A
@RW0+disp16, @RW0,
ANDW
ORW
@RW7+disp8, RW7,
A
A
ANDW
ORW
@RW6+disp8, RW6,
A
A
ANDW
ORW
@RW5+disp8, RW5,
A
A
ANDW
A
@RW4+disp8, RW4,
ANDW
ORW
@RW3+disp8, RW3,
A
A
ANDW
ORW
@RW2+disp8, RW2,
A
A
ANDW
ORW
@RW1+disp8, RW1,
A
A
ANDW
A
@RW0+disp8, RW0,
ANDW
90
XORW
C0
A
XORW
A
XORW
A
XORW
@RW0+,
A
ORW
addr16,
A
XORW
@RW3+,
A
XORW
@PC+disp16, @RW2+,
A
A
ORW
XORW
@RW1+RW7, @RW1+,
A
A
ORW
A
@RW0+RW7,
ORW
XORW
@RW3+disp16, @RW3,
A
A
ORW
XORW
@RW2+disp16, @RW2,
A
A
ORW
XORW
@RW1+disp16, @RW1,
A
A
ORW
A
@RW0+disp16, @RW0,
ORW
XORW
@RW7+disp8, RW7,
A
A
ORW
XORW
@RW6+disp8, RW6,
A
A
ORW
XORW
@RW5+disp8, RW5,
A
A
ORW
A
@RW4+disp8, RW4,
ORW
XORW
@RW3+disp8, RW3,
A
A
ORW
XORW
@RW2+disp8, RW2,
A
A
ORW
XORW
@RW1+disp8, RW1,
A
A
ORW
A
@RW0+disp8, RW0,
ORW
B0
NOTW
E0
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
XORW
addr16,
A
A
@PC+disp16,
XORW
A
@RW1+RW7,
XORW
A
@RW0+RW7,
XORW
A
NOTW
NOTW
@RW3+
NOTW
@RW2+
NOTW
@RW1+
NOTW
@RW0+
@RW3+disp16, @RW3
XORW
A
@RW2+disp16, @RW2
XORW
A
@RW1+disp16, @RW1
XORW
A
@RW0+disp16, @RW0
XORW
A
@RW7+disp8, RW7
XORW
A
@RW6+disp8, RW6
XORW
A
@RW5+disp8, RW5
XORW
A
@RW4+disp8, RW4
XORW
A
@RW3+disp8, RW3
XORW
A
@RW2+disp8, RW2
XORW
A
@RW1+disp8, RW1
XORW
A
@RW0+disp8, RW0
XORW
D0
NOTW
addr16
@PC+disp16
NOTW
@RW1+RW7
NOTW
@RW0+RW7
NOTW
@RW3+disp16
NOTW
@RW2+disp16
NOTW
@RW1+disp16
NOTW
@RW0+disp16
NOTW
@RW7+disp8
NOTW
@RW6+disp8
NOTW
@RW5+disp8
NOTW
@RW4+disp8
NOTW
@RW3+disp8
NOTW
@RW2+disp8
NOTW
@RW1+disp8
NOTW
@RW0+disp8
NOTW
F0
F2MC-16LX Instruction Maps
ADDW
ADDW
ADDW
+A @RW2,
A
ADDW
SUBW
@RW1+disp16, @RW1,
A
A
SUBW
A
ADDW
A
A
ADDW
+9 @RW1,
A
A
@RW0+disp16, A,
SUBCW
SUBW
@RW0+disp16, @RW0,
SUBW
ADDW
ADDW
ADDW
+7 RW7,
A
SUBCW
@RW6+disp8, A,
A
RW6
SUBW
SUBCW
@RW7+disp8, A,
A
RW7
SUBW
@RW6+disp8, RW6,
A
A
SUBW
ADDW
ADDW
+6 RW6,
A
RW4
SUBCW
@RW5+disp8, A,
A
RW5
SUBW
SUBW
@RW7+disp8, RW7,
A
A
SUBW
@RW5+disp8, RW5,
A
A
A
ADDW
+8 @RW0,
SUBCW
A
SUBW
A
SUBW
SUBCW
@RW3+disp8, A,
A
RW3
SUBW
SUBCW
@RW2+disp8, A,
A
RW2
SUBW
@RW4+disp8, A,
ADDW
RW0
SUBCW
@RW1+disp8, A,
A
RW1
SUBW
@RW4+disp8, RW4,
ADDW
+5 RW5,
A
A
+4 RW4,
ADDW
ADDW
ADDW
+2 RW2,
A
SUBW
@RW3+disp8, RW3,
A
A
SUBW
@RW1+disp8, RW1,
A
A
A
ADDW
40
SUBCW
A
SUBW
A
ADDW
+1 RW1,
A
A
SUBW
30
@RW0+disp8, A,
ADDW
20
@RW0+disp8, RW0,
ADDW
+0 RW0,
10
00
APPENDIX
APPENDIX C
F2MC-16LX Family
Table C-12 ea-type Instruction (8) (First Byte = 77H)
CM44-00201-4E
CM44-00201-4E
MULU
A,
MULUW
A,
@RW2+disp8 RW2
MULU
A,
MULU
+2 A,
R2
MULU
+3 A,
R3
MULU
A,
MULUW
A,
@RW6+disp8 RW6
MULU
A,
MULU
A,
MULU
+6 A,
R6
MULU
+7 A,
R7
MULU
FUJITSU MICROELECTRONICS LIMITED
MULU
A,
MULUW
A,
@RW3+disp16 @RW3
MULU
A,
@RW0+RW7
MULU
+B A,
@RW3
MULU
@RW0+
@PC+disp16
MULU
A,
addr16
MULU
+F A,
@RW3+
MULU
A,
@RW1+RW7
MULU
+E A,
@RW2+
MULU
+D A,
@RW1+
MULUW
A,
@RW3+
MULUW
A,
@RW2+
MULUW
A,
@RW1+
MULUW
A,
@RW2+disp16 @RW2
MULUW
A,
@RW0+
MULU
A,
MULU
+A A,
@RW2
MULU
A,
MULUW
A,
@RW1+disp16 @RW1
40
MULUW
A,
addr16
@PC+disp16
MULUW
A,
@RW1+RW7
MULUW
A,
@RW0+RW7
MULUW
A,
MUL
A,
@RW3+
MUL
A,
@RW2+
MUL
A,
@RW1+
MUL
A,
@RW0+
MUL
A,
@RW3+disp16 @RW3
MULUW
A,
MUL
A,
@RW2+disp16 @RW2
MULUW
A,
MUL
A,
@RW1+disp16 @RW1
MULUW
A,
MUL
A,
@RW0+disp16 @RW0
MULUW
A,
MUL
A,
@RW7+disp8 R7
MULUW
A,
MUL
A,
@RW6+disp8 R6
MULUW
A,
MUL
A,
@RW5+disp8 R5
MULUW
A,
MUL
A,
@RW4+disp8 R4
MULUW
A,
MUL
A,
@RW3+disp8 R3
MULUW
A,
MUL
A,
@RW2+disp8 R2
MULUW
A,
MUL
A,
@RW1+disp8 R1
MULUW
A,
MUL
A,
@RW0+disp8 R0
MULUW
A,
30
60
MUL
A,
addr16
@PC+disp16
MUL
A,
@RW1+RW7
MUL
A,
@RW0+RW7
MUL
A,
MULW
A,
@RW3+
MULW
A,
@RW2+
MULW
A,
@RW1+
MULW
A,
@RW0+
MULW
A,
@RW3+disp16 @RW3
MUL
A,
MULW
A,
@RW2+disp16 @RW2
MUL
A,
MULW
A,
@RW1+disp16 @RW1
MUL
A,
MULW
A,
@RW0+disp16 @RW0
MUL
A,
MULW
A,
@RW7+disp8 RW7
MUL
A,
MULW
A,
@RW6+disp8 RW6
MUL
A,
MULW
A,
@RW5+disp8 RW5
MUL
A,
MULW
A,
@RW4+disp8 RW4
MUL
A,
MULW
A,
@RW3+disp8 RW3
MUL
A,
MULW
A,
@RW2+disp8 RW2
MUL
A,
MULW
A,
@RW1+disp8 RW1
MUL
A,
MULW
A,
@RW0+disp8 RW0
MUL
A,
50
80
MULW
A,
addr16
@PC+disp16
MULW
A,
@RW1+RW7
MULW
A,
@RW0+RW7
MULW
A,
DIVU
A,
@RW3+
DIVU
A,
@RW2+
DIVU
A,
@RW1+
DIVU
A,
@RW0+
DIVU
A,
@RW3+disp16 @RW3
MULW
A,
DIVU
A,
@RW2+disp16 @RW2
MULW
A,
DIVU
A,
@RW1+disp16 @RW1
MULW
A,
DIVU
A,
@RW0+disp16 @RW0
MULW
A,
DIVU
A,
@RW7+disp8 R7
MULW
A,
DIVU
A,
@RW6+disp8 R6
MULW
A,
DIVU
A,
@RW5+disp8 R5
MULW
A,
DIVU
A,
@RW4+disp8 R4
MULW
A,
DIVU
A,
@RW3+disp8 R3
MULW
A,
DIVU
A,
@RW2+disp8 R2
MULW
A,
DIVU
A,
@RW1+disp8 R1
MULW
A,
DIVU
A,
@RW0+disp8 R0
MULW
A,
70
A0
DIVU
A,
addr16
@PC+disp16
DIVU
A,
@RW1+RW7
DIVU
A,
@RW0+RW7
DIVU
A,
DIVUW
A,
@RW3+
DIVUW
A,
@RW2+
DIVUW
A,
@RW1+
DIVUW
A,
@RW0+
DIVUW
A,
@RW3+disp16 @RW3
DIVU
A,
DIVUW
A,
@RW2+disp16 @RW2
DIVU
A,
DIVUW
A,
@RW1+disp16 @RW1
DIVU
A,
DIVUW
A,
@RW0+disp16 @RW0
DIVU
A,
DIVUW
A,
@RW7+disp8 RW7
DIVU
A,
DIVUW
A,
@RW6+disp8 RW6
DIVU
A,
DIVUW
A,
@RW5+disp8 RW5
DIVU
A,
DIVUW
A,
@RW4+disp8 RW4
DIVU
A,
DIVUW
A,
@RW3+disp8 RW3
DIVU
A,
DIVUW
A,
@RW2+disp8 RW2
DIVU
A,
DIVUW
A,
@RW1+disp8 RW1
DIVU
A,
DIVUW
A,
@RW0+disp8 RW0
DIVU
A,
90
C0
DIVUW
A,
addr16
@PC+disp16
DIVUW
A,
@RW1+RW7
DIVUW
A,
@RW0+RW7
DIVUW
A,
DIV
A,
@RW3+
DIV
A,
@RW2+
DIV
A,
@RW1+
DIV
A,
@RW0+
DIV
A,
@RW3+disp16 @RW3
DIVUW
A,
DIV
A,
@RW2+disp16 @RW2
DIVUW
A,
DIV
A,
@RW1+disp16 @RW1
DIVUW
A,
DIV
A,
@RW0+disp16 @RW0
DIVUW
A,
DIV
A,
@RW7+disp8 R7
DIVUW
A,
DIV
A,
@RW6+disp8 R6
DIVUW
A,
DIV
A,
@RW5+disp8 R5
DIVUW
A,
DIV
A,
@RW4+disp8 R4
DIVUW
A,
DIV
A,
@RW3+disp8 R3
DIVUW
A,
DIV
A,
@RW2+disp8 R2
DIVUW
A,
DIV
A,
@RW1+disp8 R1
DIVUW
A,
DIV
A,
@RW0+disp8 R0
DIVUW
A,
B0
E0
DIV
A,
addr16
@PC+disp16
DIV
A,
@RW1+RW7
DIV
A,
@RW0+RW7
DIV
A,
DIVW
A,
@RW3+
DIVW
A,
@RW2+
DIVW
A,
@RW1+
DIVW
A,
@RW0+
DIVW
A,
@RW3+disp16 @RW3
DIV
A,
DIVW
A,
@RW2+disp16 @RW2
DIV
A,
DIVW
A,
@RW1+disp16 @RW1
DIV
A,
DIVW
A,
@RW0+disp16 @RW0
DIV
A,
DIVW
A,
@RW7+disp8 RW7
DIV
A,
DIVW
A,
@RW6+disp8 RW6
DIV
A,
DIVW
A,
@RW5+disp8 RW5
DIV
A,
DIVW
A,
@RW4+disp8 RW4
DIV
A,
DIVW
A,
@RW3+disp8 RW3
DIV
A,
DIVW
A,
@RW2+disp8 RW2
DIV
A,
DIVW
A,
@RW1+disp8 RW1
DIV
A,
DIVW
A,
@RW0+disp8 RW0
DIV
A,
D0
DIVW
A,
addr16
@PC+disp16
DIVW
A,
@RW1+RW7
DIVW
A,
@RW0+RW7
DIVW
A,
@RW3+disp16
DIVW
A,
@RW2+disp16
DIVW
A,
@RW1+disp16
DIVW
A,
@RW0+disp16
DIVW
A,
@RW7+disp8
DIVW
A,
@RW6+disp8
DIVW
A,
@RW5+disp8
DIVW
A,
@RW4+disp8
DIVW
A,
@RW3+disp8
DIVW
A,
@RW2+disp8
DIVW
A,
@RW1+disp8
DIVW
A,
@RW0+disp8
DIVW
A,
F0
APPENDIX C
+C A,
MULU
A,
MULUW
A,
@RW0+disp16 @RW0
MULU
+9 A,
@RW1
@RW0
+8 A,
MULUW
A,
@RW5+disp8 RW5
MULUW
A,
@RW7+disp8 RW7
MULU
A,
MULUW
A,
@RW4+disp8 RW4
MULU
A,
MULU
+5 A,
R5
R4
+4 A,
MULU
MULUW
A,
@RW1+disp8 RW1
MULUW
A,
@RW3+disp8 RW3
MULU
A,
MULU
+1 A,
R1
R0
20
MULUW
A,
@RW0+disp8 RW0
MULU
A,
MULU
+0 A,
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
Table C-13 ea-type Instruction (9) (First Byte = 78H)
391
APPENDIX
APPENDIX C
C.7
F2MC-16LX Instruction Maps
F2MC-16LX Family
MOVEA RWi, ea Instruction Map
Table C-14lists MOVEA RWi, ea instruction map.
392
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
20
FUJITSU MICROELECTRONICS LIMITED
MOVEA
RW0,
MOVEA
RW1,
@RW3+disp8 RW3
MOVEA
RW0,
MOVEA
RW1,
@RW4+disp8 RW4
MOVEA
RW0,
MOVEA
RW1,
@RW5+disp8 RW5
MOVEA
RW0,
MOVEA
RW1,
@RW6+disp8 RW6
MOVEA
RW0,
MOVEA
RW1,
@RW7+disp8 RW7
MOVEA
RW0,
MOVEA
RW1,
@RW0+disp16 @RW0
MOVEA
RW0,
MOVEA
RW1,
@RW1+disp16 @RW1
MOVEA
RW0,
MOVEA
RW1,
@RW2+disp16 @RW2
MOVEA
RW0,
MOVEA
RW1,
@RW3+disp16 @RW3
MOVEA
RW0,
MOVEA
+3 RW0,
RW3
MOVEA
+4 RW0,
RW4
MOVEA
+5 RW0,
RW5
MOVEA
+6 RW0,
RW6
MOVEA
+7 RW0,
RW7
MOVEA
+8 RW0,
@RW0
MOVEA
+9 RW0,
@RW1
MOVEA
+A RW0,
@RW2
MOVEA
+B RW0,
@RW3
MOVEA
+C RW0,
@RW0+
@PC+disp16
MOVEA
RW0,
addr16
MOVEA
+F RW0,
@RW3+
MOVEA
RW0,
MOVEA
+E RW0,
@RW2+
@RW1+RW7
MOVEA
RW0,
MOVEA
RW1,
@RW3+
MOVEA
RW1,
@RW2+
MOVEA
RW1,
@RW1+
MOVEA
RW1,
@RW2+disp8 RW2
@RW0+RW7
MOVEA
RW0,
MOVEA
+2 RW0,
RW2
40
MOVEA
RW1,
addr16
@PC+disp16
MOVEA
RW1,
@RW1+RW7
MOVEA
RW1,
@RW0+RW7
MOVEA
RW1,
MOVEA
RW2,
@RW3+
MOVEA
RW2,
@RW2+
MOVEA
RW2,
@RW1+
MOVEA
RW2,
@RW0+
MOVEA
RW2,
@RW3+disp16 @RW3
MOVEA
RW1,
MOVEA
RW2,
@RW2+disp16 @RW2
MOVEA
RW1,
MOVEA
RW2,
@RW1+disp16 @RW1
MOVEA
RW1,
MOVEA
RW2,
@RW0+disp16 @RW0
MOVEA
RW1,
MOVEA
RW2,
@RW7+disp8 RW7
MOVEA
RW1,
MOVEA
RW2,
@RW6+disp8 RW6
MOVEA
RW1,
MOVEA
RW2,
@RW5+disp8 RW5
MOVEA
RW1,
MOVEA
RW2,
@RW4+disp8 RW4
MOVEA
RW1,
MOVEA
RW2,
@RW3+disp8 RW3
MOVEA
RW1,
MOVEA
RW2,
@RW2+disp8 RW2
MOVEA
RW1,
MOVEA
RW2,
@RW1+disp8 RW1
MOVEA
RW1,
MOVEA
RW2,
@RW0+disp8 RW0
MOVEA
RW1,
30
60
MOVEA
RW2,
addr16
@PC+disp16
MOVEA
RW2,
@RW1+RW7
MOVEA
RW2,
@RW0+RW7
MOVEA
RW2,
MOVEA
RW3,
@RW3+
MOVEA
RW3,
@RW2+
MOVEA
RW3,
@RW1+
MOVEA
RW3,
@RW0+
MOVEA
RW3,
@RW3+disp16 @RW3
MOVEA
RW2,
MOVEA
RW3,
@RW2+disp16 @RW2
MOVEA
RW2,
MOVEA
RW3,
@RW1+disp16 @RW1
MOVEA
RW2,
MOVEA
RW3,
@RW0+disp16 @RW0
MOVEA
RW2,
MOVEA
RW3,
@RW7+disp8 RW7
MOVEA
RW2,
MOVEA
RW3,
@RW6+disp8 RW6
MOVEA
RW2,
MOVEA
RW3,
@RW5+disp8 RW5
MOVEA
RW2,
MOVEA
RW3,
@RW4+disp8 RW4
MOVEA
RW2,
MOVEA
RW3,
@RW3+disp8 RW3
MOVEA
RW2,
MOVEA
RW3,
@RW2+disp8 RW2
MOVEA
RW2,
MOVEA
RW3,
@RW1+disp8 RW1
MOVEA
RW2,
MOVEA
RW3,
@RW0+disp8 RW0
MOVEA
RW2,
50
80
MOVEA
RW3,
addr16
@PC+disp16
MOVEA
RW3,
@RW1+RW7
MOVEA
RW3,
@RW0+RW7
MOVEA
RW3,
MOVEA
RW4,
@RW3+
MOVEA
RW4,
@RW2+
MOVEA
RW4,
@RW1+
MOVEA
RW4,
@RW0+
MOVEA
RW4,
@RW3+disp16 @RW3
MOVEA
RW3,
MOVEA
RW4,
@RW2+disp16 @RW2
MOVEA
RW3,
MOVEA
RW4,
@RW1+disp16 @RW1
MOVEA
RW3,
MOVEA
RW4,
@RW0+disp16 @RW0
MOVEA
RW3,
MOVEA
RW4,
@RW7+disp8 RW7
MOVEA
RW3,
MOVEA
RW4,
@RW6+disp8 RW6
MOVEA
RW3,
MOVEA
RW4,
@RW5+disp8 RW5
MOVEA
RW3,
MOVEA
RW4,
@RW4+disp8 RW4
MOVEA
RW3,
MOVEA
RW4,
@RW3+disp8 RW3
MOVEA
RW3,
MOVEA
RW4,
@RW2+disp8 RW2
MOVEA
RW3,
MOVEA
RW4,
@RW1+disp8 RW1
MOVEA
RW3,
MOVEA
RW4,
@RW0+disp8 RW0
MOVEA
RW3,
70
A0
MOVEA
RW4,
addr16
@PC+disp16
MOVEA
RW4,
@RW1+RW7
MOVEA
RW4,
@RW0+RW7
MOVEA
RW4,
MOVEA
RW5,
@RW3+
MOVEA
RW5,
@RW2+
MOVEA
RW5,
@RW1+
MOVEA
RW5,
@RW0+
MOVEA
RW5,
@RW3+disp16 @RW3
MOVEA
RW4,
MOVEA
RW5,
@RW2+disp16 @RW2
MOVEA
RW4,
MOVEA
RW5,
@RW1+disp16 @RW1
MOVEA
RW4,
MOVEA
RW5,
@RW0+disp16 @RW0
MOVEA
RW4,
MOVEA
RW5,
@RW7+disp8 RW7
MOVEA
RW4,
MOVEA
RW5,
@RW6+disp8 RW6
MOVEA
RW4,
MOVEA
RW5,
@RW5+disp8 RW5
MOVEA
RW4,
MOVEA
RW5,
@RW4+disp8 RW4
MOVEA
RW4,
MOVEA
RW5,
@RW3+disp8 RW3
MOVEA
RW4,
MOVEA
RW5,
@RW2+disp8 RW2
MOVEA
RW4,
MOVEA
RW5,
@RW1+disp8 RW1
MOVEA
RW4,
MOVEA
RW5,
@RW0+disp8 RW0
MOVEA
RW4,
90
C0
MOVEA
RW5,
addr16
@PC+disp16
MOVEA
RW5,
@RW1+RW7
MOVEA
RW5,
@RW0+RW7
MOVEA
RW5,
MOVEA
RW6,
@RW3+
MOVEA
RW6,
@RW2+
MOVEA
RW6,
@RW1+
MOVEA
RW6,
@RW0+
MOVEA
RW6,
@RW3+disp16 @RW3
MOVEA
RW5,
MOVEA
RW6,
@RW2+disp16 @RW2
MOVEA
RW5,
MOVEA
RW6,
@RW1+disp16 @RW1
MOVEA
RW5,
MOVEA
RW6,
@RW0+disp16 @RW0
MOVEA
RW5,
MOVEA
RW6,
@RW7+disp8 RW7
MOVEA
RW5,
MOVEA
RW6,
@RW6+disp8 RW6
MOVEA
RW5,
MOVEA
RW6,
@RW5+disp8 RW5
MOVEA
RW5,
MOVEA
RW6,
@RW4+disp8 RW4
MOVEA
RW5,
MOVEA
RW6,
@RW3+disp8 RW3
MOVEA
RW5,
MOVEA
RW6,
@RW2+disp8 RW2
MOVEA
RW5,
MOVEA
RW6,
@RW1+disp8 RW1
MOVEA
RW5,
MOVEA
RW6,
@RW0+disp8 RW0
MOVEA
RW5,
B0
E0
MOVEA
RW6,
addr16
@PC+disp16
MOVEA
RW6,
@RW1+RW7
MOVEA
RW6,
@RW0+RW7
MOVEA
RW6,
MOVEA
RW7,
@RW3+
MOVEA
RW7,
@RW2+
MOVEA
RW7,
@RW1+
MOVEA
RW7,
@RW0+
MOVEA
RW7,
@RW3+disp16 @RW3
MOVEA
RW6,
MOVEA
RW7,
@RW2+disp16 @RW2
MOVEA
RW6,
MOVEA
RW7,
@RW1+disp16 @RW1
MOVEA
RW6,
MOVEA
RW7,
@RW0+disp16 @RW0
MOVEA
RW6,
MOVEA
RW7,
@RW7+disp8 RW7
MOVEA
RW6,
MOVEA
RW7,
@RW6+disp8 RW6
MOVEA
RW6,
MOVEA
RW7,
@RW5+disp8 RW5
MOVEA
RW6,
MOVEA
RW7,
@RW4+disp8 RW4
MOVEA
RW6,
MOVEA
RW7,
@RW3+disp8 RW3
MOVEA
RW6,
MOVEA
RW7,
@RW2+disp8 RW2
MOVEA
RW6,
MOVEA
RW7,
@RW1+disp8 RW1
MOVEA
RW6,
MOVEA
RW7,
@RW0+disp8 RW0
MOVEA
RW6,
D0
MOVEA
RW7,
addr16
@PC+disp16
MOVEA
RW7,
@RW1+RW7
MOVEA
RW7,
@RW0+RW7
MOVEA
RW7,
@RW3+disp16
MOVEA
RW7,
@RW2+disp16
MOVEA
RW7,
@RW1+disp16
MOVEA
RW7,
@RW0+disp16
MOVEA
RW7,
@RW7+disp8
MOVEA
RW7,
@RW6+disp8
MOVEA
RW7,
@RW5+disp8
MOVEA
RW7,
@RW4+disp8
MOVEA
RW7,
@RW3+disp8
MOVEA
RW7,
@RW2+disp8
MOVEA
RW7,
@RW1+disp8
MOVEA
RW7,
@RW0+disp8
MOVEA
RW7,
F0
APPENDIX C
MOVEA
+D RW0,
@RW1+
MOVEA
RW1,
@RW1+disp8 RW1
MOVEA
RW1,
@RW0+
MOVEA
RW0,
MOVEA
RW1,
@RW0+disp8 RW0
MOVEA
RW0,
10
MOVEA
+1 RW0,
RW1
RW0
+0 RW0,
MOVEA
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ MOVEA RWi, ea Instruction Map
Table C-14 MOVEA RWi, ea Instruction (First Byte = 79H)
393
APPENDIX
APPENDIX C
C.8
F2MC-16LX Instruction Maps
F2MC-16LX Family
MOV Ri, ea Instruction Map
Table C-15lists MOV Ri, ea instruction map.
394
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
20
FUJITSU MICROELECTRONICS LIMITED
MOV
R1,
@RW2+disp8 R2
MOV
R0,
MOV
R1,
@RW3+disp8 R3
MOV
R0,
MOV
R1,
@RW4+disp8 R4
MOV
R0,
MOV
R1,
@RW5+disp8 R5
MOV
R0,
MOV
R1,
@RW6+disp8 R6
MOV
R0,
MOV
R1,
@RW7+disp8 R7
MOV
R0,
MOV
R1,
@RW0+disp16 @RW0
MOV
R0,
MOV
R1,
@RW1+disp16 @RW1
MOV
R0,
MOV
R1,
@RW2+disp16 @RW2
MOV
R0,
MOV
R1,
@RW3+disp16 @RW3
MOV
R0,
MOV
+3 R0,
R3
MOV
+4 R0,
R4
MOV
+5 R0,
R5
MOV
+6 R0,
R6
MOV
+7 R0,
R7
MOV
+8 R0,
@RW0
MOV
+9 R0,
@RW1
MOV
+A R0,
@RW2
MOV
+B R0,
@RW3
MOV
+C R0,
@RW0+
@PC+disp16
MOV
R0,
addr16
MOV
+F R0,
@RW3+
MOV
R0,
MOV
+E R0,
@RW2+
@RW1+RW7
MOV
R0,
@RW0+RW7
MOV
R0,
MOV
+2 R0,
R2
MOV
+D R0,
@RW1+
MOV
R1,
@RW1+disp8 R1
MOV
R1,
@RW3+
MOV
R1,
@RW2+
MOV
R1,
@RW1+
40
MOV
R1,
addr16
@PC+disp16
MOV
R1,
@RW1+RW7
MOV
R1,
@RW0+RW7
MOV
R1,
MOV
R2,
@RW3+
MOV
R2,
@RW2+
MOV
R2,
@RW1+
MOV
R2,
@RW0+
MOV
R2,
@RW3+disp16 @RW3
MOV
R1,
MOV
R2,
@RW2+disp16 @RW2
MOV
R1,
MOV
R2,
@RW1+disp16 @RW1
MOV
R1,
MOV
R2,
@RW0+disp16 @RW0
MOV
R1,
MOV
R2,
@RW7+disp8 R7
MOV
R1,
MOV
R2,
@RW6+disp8 R6
MOV
R1,
MOV
R2,
@RW5+disp8 R5
MOV
R1,
MOV
R2,
@RW4+disp8 R4
MOV
R1,
MOV
R2,
@RW3+disp8 R3
MOV
R1,
MOV
R2,
@RW2+disp8 R2
MOV
R1,
MOV
R2,
@RW1+disp8 R1
MOV
R1,
MOV
R2,
@RW0+disp8 R0
MOV
R1,
30
60
MOV
R2,
addr16
@PC+disp16
MOV
R2,
@RW1+RW7
MOV
R2,
@RW0+RW7
MOV
R2,
MOV
R3,
@RW3+
MOV
R3,
@RW2+
MOV
R3,
@RW1+
MOV
R3,
@RW0+
MOV
R3,
@RW3+disp16 @RW3
MOV
R2,
MOV
R3,
@RW2+disp16 @RW2
MOV
R2,
MOV
R3,
@RW1+disp16 @RW1
MOV
R2,
MOV
R3,
@RW0+disp16 @RW0
MOV
R2,
MOV
R3,
@RW7+disp8 R7
MOV
R2,
MOV
R3,
@RW6+disp8 R6
MOV
R2,
MOV
R3,
@RW5+disp8 R5
MOV
R2,
MOV
R3,
@RW4+disp8 R4
MOV
R2,
MOV
R3,
@RW3+disp8 R3
MOV
R2,
MOV
R3,
@RW2+disp8 R2
MOV
R2,
MOV
R3,
@RW1+disp8 R1
MOV
R2,
MOV
R3,
@RW0+disp8 R0
MOV
R2,
50
80
MOV
R3,
addr16
@PC+disp16
MOV
R3,
@RW1+RW7
MOV
R3,
@RW0+RW7
MOV
R3,
MOV
R4,
@RW3+
MOV
R4,
@RW2+
MOV
R4,
@RW1+
MOV
R4,
@RW0+
MOV
R4,
@RW3+disp16 @RW3
MOV
R3,
MOV
R4,
@RW2+disp16 @RW2
MOV
R3,
MOV
R4,
@RW1+disp16 @RW1
MOV
R3,
MOV
R4,
@RW0+disp16 @RW0
MOV
R3,
MOV
R4,
@RW7+disp8 R7
MOV
R3,
MOV
R4,
@RW6+disp8 R6
MOV
R3,
MOV
R4,
@RW5+disp8 R5
MOV
R3,
MOV
R4,
@RW4+disp8 R4
MOV
R3,
MOV
R4,
@RW3+disp8 R3
MOV
R3,
MOV
R4,
@RW2+disp8 R2
MOV
R3,
MOV
R4,
@RW1+disp8 R1
MOV
R3,
MOV
R4,
@RW0+disp8 R0
MOV
R3,
70
A0
MOV
R4,
addr16
@PC+disp16
MOV
R4,
@RW1+RW7
MOV
R4,
@RW0+RW7
MOV
R4,
MOV
R5,
@RW3+
MOV
R5,
@RW2+
MOV
R5,
@RW1+
MOV
R5,
@RW0+
MOV
R5,
@RW3+disp16 @RW3
MOV
R4,
MOV
R5,
@RW2+disp16 @RW2
MOV
R4,
MOV
R5,
@RW1+disp16 @RW1
MOV
R4,
MOV
R5,
@RW0+disp16 @RW0
MOV
R4,
MOV
R5,
@RW7+disp8 R7
MOV
R4,
MOV
R5,
@RW6+disp8 R6
MOV
R4,
MOV
R5,
@RW5+disp8 R5
MOV
R4,
MOV
R5,
@RW4+disp8 R4
MOV
R4,
MOV
R5,
@RW3+disp8 R3
MOV
R4,
MOV
R5,
@RW2+disp8 R2
MOV
R4,
MOV
R5,
@RW1+disp8 R1
MOV
R4,
MOV
R5,
@RW0+disp8 R0
MOV
R4,
90
C0
MOV
R5,
addr16
@PC+disp16
MOV
R5,
@RW1+RW7
MOV
R5,
@RW0+RW7
MOV
R5,
MOV
R6,
@RW3+
MOV
R6,
@RW2+
MOV
R6,
@RW1+
MOV
R6,
@RW0+
MOV
R6,
@RW3+disp16 @RW3
MOV
R5,
MOV
R6,
@RW2+disp16 @RW2
MOV
R5,
MOV
R6,
@RW1+disp16 @RW1
MOV
R5,
MOV
R6,
@RW0+disp16 @RW0
MOV
R5,
MOV
R6,
@RW7+disp8 R7
MOV
R5,
MOV
R6,
@RW6+disp8 R6
MOV
R5,
MOV
R6,
@RW5+disp8 R5
MOV
R5,
MOV
R6,
@RW4+disp8 R4
MOV
R5,
MOV
R6,
@RW3+disp8 R3
MOV
R5,
MOV
R6,
@RW2+disp8 R2
MOV
R5,
MOV
R6,
@RW1+disp8 R1
MOV
R5,
MOV
R6,
@RW0+disp8 R0
MOV
R5,
B0
E0
MOV
R6,
addr16
@PC+disp16
MOV
R6,
@RW1+RW7
MOV
R6,
@RW0+RW7
MOV
R6,
MOV
R7,
@RW3+
MOV
R7,
@RW2+
MOV
R7,
@RW1+
MOV
R7,
@RW0+
MOV
R7,
@RW3+disp16 @RW3
MOV
R6,
MOV
R7,
@RW2+disp16 @RW2
MOV
R6,
MOV
R7,
@RW1+disp16 @RW1
MOV
R6,
MOV
R7,
@RW0+disp16 @RW0
MOV
R6,
MOV
R7,
@RW7+disp8 R7
MOV
R6,
MOV
R7,
@RW6+disp8 R6
MOV
R6,
MOV
R7,
@RW5+disp8 R5
MOV
R6,
MOV
R7,
@RW4+disp8 R4
MOV
R6,
MOV
R7,
@RW3+disp8 R3
MOV
R6,
MOV
R7,
@RW2+disp8 R2
MOV
R6,
MOV
R7,
@RW1+disp8 R1
MOV
R6,
MOV
R7,
@RW0+disp8 R0
MOV
R6,
D0
MOV
R7,
addr16
@PC+disp16
MOV
R7,
@RW1+RW7
MOV
R7,
@RW0+RW7
MOV
R7,
@RW3+disp16
MOV
R7,
@RW2+disp16
MOV
R7,
@RW1+disp16
MOV
R7,
@RW0+disp16
MOV
R7,
@RW7+disp8
MOV
R7,
@RW6+disp8
MOV
R7,
@RW5+disp8
MOV
R7,
@RW4+disp8
MOV
R7,
@RW3+disp8
MOV
R7,
@RW2+disp8
MOV
R7,
@RW1+disp8
MOV
R7,
@RW0+disp8
MOV
R7,
F0
APPENDIX C
MOV
R1,
@RW0+
MOV
R0,
MOV
R1,
@RW0+disp8 R0
MOV
R0,
10
MOV
+1 R0,
R1
R0
+0 R0,
MOV
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ MOV Ri, ea Instruction Map
Table C-15 MOV Ri, ea Instruction (First Byte = 7AH)
395
APPENDIX
APPENDIX C
C.9
F2MC-16LX Instruction Maps
F2MC-16LX Family
MOVW RWi, ea Instruction Map
Table C-16lists MOVW RWi, ea instruction map.
396
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
MOVW
RW1,
@RW2+disp8 RW2
MOVW
RW0,
MOVW
RW1,
@RW3+disp8 RW3
MOVW
RW0,
MOVW
RW1,
@RW4+disp8 RW4
MOVW
RW0,
MOVW
RW1,
@RW5+disp8 RW5
MOVW
RW0,
MOVW
RW1,
@RW6+disp8 RW6
MOVW
RW0,
MOVW
RW1,
@RW7+disp8 RW7
MOVW
RW0,
MOVW
RW1,
@RW0+disp16 @RW0
MOVW
RW0,
MOVW
RW1,
@RW1+disp16 @RW1
MOVW
RW0,
MOVW
RW1,
@RW2+disp16 @RW2
MOVW
RW0,
MOVW
RW1,
@RW3+disp16 @RW3
MOVW
RW0,
MOVW
+3 RW0,
RW3
MOVW
+4 RW0,
RW4
MOVW
+5 RW0,
RW5
MOVW
+6 RW0,
RW6
MOVW
+7 RW0,
RW7
MOVW
+8 RW0,
@RW0
MOVW
+9 RW0,
@RW1
MOVW
+A RW0,
@RW2
MOVW
+B RW0,
@RW3
MOVW
+C RW0,
@RW0+
@PC+disp16
MOVW
RW0,
addr16
MOVW
+F RW0,
@RW3+
MOVW
RW0,
MOVW
+E RW0,
@RW2+
@RW1+RW7
MOVW
RW0,
@RW0+RW7
MOVW
RW0,
MOVW
+2 RW0,
RW2
MOVW
+D RW0,
@RW1+
MOVW
RW1,
@RW1+disp8 RW1
MOVW
RW1,
@RW3+
MOVW
RW1,
@RW2+
MOVW
RW1,
@RW1+
40
MOVW
RW1,
addr16
@PC+disp16
MOVW
RW1,
@RW1+RW7
MOVW
RW1,
@RW0+RW7
MOVW
RW1,
MOVW
RW2,
@RW3+
MOVW
RW2,
@RW2+
MOVW
RW2,
@RW1+
MOVW
RW2,
@RW0+
MOVW
RW2,
@RW3+disp16 @RW3
MOVW
RW1,
MOVW
RW2,
@RW2+disp16 @RW2
MOVW
RW1,
MOVW
RW2,
@RW1+disp16 @RW1
MOVW
RW1,
MOVW
RW2,
@RW0+disp16 @RW0
MOVW
RW1,
MOVW
RW2,
@RW7+disp8 RW7
MOVW
RW1,
MOVW
RW2,
@RW6+disp8 RW6
MOVW
RW1,
MOVW
RW2,
@RW5+disp8 RW5
MOVW
RW1,
MOVW
RW2,
@RW4+disp8 RW4
MOVW
RW1,
MOVW
RW2,
@RW3+disp8 RW3
MOVW
RW1,
MOVW
RW2,
@RW2+disp8 RW2
MOVW
RW1,
MOVW
RW2,
@RW1+disp8 RW1
MOVW
RW1,
MOVW
RW2,
@RW0+disp8 RW0
MOVW
RW1,
30
60
MOVW
RW2,
addr16
@PC+disp16
MOVW
RW2,
@RW1+RW7
MOVW
RW2,
@RW0+RW7
MOVW
RW2,
MOVW
RW3,
@RW3+
MOVW
RW3,
@RW2+
MOVW
RW3,
@RW1+
MOVW
RW3,
@RW0+
MOVW
RW3,
@RW3+disp16 @RW3
MOVW
RW2,
MOVW
RW3,
@RW2+disp16 @RW2
MOVW
RW2,
MOVW
RW3,
@RW1+disp16 @RW1
MOVW
RW2,
MOVW
RW3,
@RW0+disp16 @RW0
MOVW
RW2,
MOVW
RW3,
@RW7+disp8 RW7
MOVW
RW2,
MOVW
RW3,
@RW6+disp8 RW6
MOVW
RW2,
MOVW
RW3,
@RW5+disp8 RW5
MOVW
RW2,
MOVW
RW3,
@RW4+disp8 RW4
MOVW
RW2,
MOVW
RW3,
@RW3+disp8 RW3
MOVW
RW2,
MOVW
RW3,
@RW2+disp8 RW2
MOVW
RW2,
MOVW
RW3,
@RW1+disp8 RW1
MOVW
RW2,
MOVW
RW3,
@RW0+disp8 RW0
MOVW
RW2,
50
80
MOVW
RW3,
addr16
@PC+disp16
MOVW
RW3,
@RW1+RW7
MOVW
RW3,
@RW0+RW7
MOVW
RW3,
MOVW
RW4,
@RW3+
MOVW
RW4,
@RW2+
MOVW
RW4,
@RW1+
MOVW
RW4,
@RW0+
MOVW
RW4,
@RW3+disp16 @RW3
MOVW
RW3,
MOVW
RW4,
@RW2+disp16 @RW2
MOVW
RW3,
MOVW
RW4,
@RW1+disp16 @RW1
MOVW
RW3,
MOVW
RW4,
@RW0+disp16 @RW0
MOVW
RW3,
MOVW
RW4,
@RW7+disp8 RW7
MOVW
RW3,
MOVW
RW4,
@RW6+disp8 RW6
MOVW
RW3,
MOVW
RW4,
@RW5+disp8 RW5
MOVW
RW3,
MOVW
RW4,
@RW4+disp8 RW4
MOVW
RW3,
MOVW
RW4,
@RW3+disp8 RW3
MOVW
RW3,
MOVW
RW4,
@RW2+disp8 RW2
MOVW
RW3,
MOVW
RW4,
@RW1+disp8 RW1
MOVW
RW3,
MOVW
RW4,
@RW0+disp8 RW0
MOVW
RW3,
70
A0
MOVW
RW4,
addr16
@PC+disp16
MOVW
RW4,
@RW1+RW7
MOVW
RW4,
@RW0+RW7
MOVW
RW4,
MOVW
RW5,
@RW3+
MOVW
RW5,
@RW2+
MOVW
RW5,
@RW1+
MOVW
RW5,
@RW0+
MOVW
RW5,
@RW3+disp16 @RW3
MOVW
RW4,
MOVW
RW5,
@RW2+disp16 @RW2
MOVW
RW4,
MOVW
RW5,
@RW1+disp16 @RW1
MOVW
RW4,
MOVW
RW5,
@RW0+disp16 @RW0
MOVW
RW4,
MOVW
RW5,
@RW7+disp8 RW7
MOVW
RW4,
MOVW
RW5,
@RW6+disp8 RW6
MOVW
RW4,
MOVW
RW5,
@RW5+disp8 RW5
MOVW
RW4,
MOVW
RW5,
@RW4+disp8 RW4
MOVW
RW4,
MOVW
RW5,
@RW3+disp8 RW3
MOVW
RW4,
MOVW
RW5,
@RW2+disp8 RW2
MOVW
RW4,
MOVW
RW5,
@RW1+disp8 RW1
MOVW
RW4,
MOVW
RW5,
@RW0+disp8 RW0
MOVW
RW4,
90
C0
MOVW
RW5,
addr16
@PC+disp16
MOVW
RW5,
@RW1+RW7
MOVW
RW5,
@RW0+RW7
MOVW
RW5,
MOVW
RW6,
@RW3+
MOVW
RW6,
@RW2+
MOVW
RW6,
@RW1+
MOVW
RW6,
@RW0+
MOVW
RW6,
@RW3+disp16 @RW3
MOVW
RW5,
MOVW
RW6,
@RW2+disp16 @RW2
MOVW
RW5,
MOVW
RW6,
@RW1+disp16 @RW1
MOVW
RW5,
MOVW
RW6,
@RW0+disp16 @RW0
MOVW
RW5,
MOVW
RW6,
@RW7+disp8 RW7
MOVW
RW5,
MOVW
RW6,
@RW6+disp8 RW6
MOVW
RW5,
MOVW
RW6,
@RW5+disp8 RW5
MOVW
RW5,
MOVW
RW6,
@RW4+disp8 RW4
MOVW
RW5,
MOVW
RW6,
@RW3+disp8 RW3
MOVW
RW5,
MOVW
RW6,
@RW2+disp8 RW2
MOVW
RW5,
MOVW
RW6,
@RW1+disp8 RW1
MOVW
RW5,
MOVW
RW6,
@RW0+disp8 RW0
MOVW
RW5,
B0
E0
MOVW
RW6,
addr16
@PC+disp16
MOVW
RW6,
@RW1+RW7
MOVW
RW6,
@RW0+RW7
MOVW
RW6,
MOVW
RW7,
@RW3+
MOVW
RW7,
@RW2+
MOVW
RW7,
@RW1+
MOVW
RW7,
@RW0+
MOVW
RW7,
@RW3+disp16 @RW3
MOVW
RW6,
MOVW
RW7,
@RW2+disp16 @RW2
MOVW
RW6,
MOVW
RW7,
@RW1+disp16 @RW1
MOVW
RW6,
MOVW
RW7,
@RW0+disp16 @RW0
MOVW
RW6,
MOVW
RW7,
@RW7+disp8 RW7
MOVW
RW6,
MOVW
RW7,
@RW6+disp8 RW6
MOVW
RW6,
MOVW
RW7,
@RW5+disp8 RW5
MOVW
RW6,
MOVW
RW7,
@RW4+disp8 RW4
MOVW
RW6,
MOVW
RW7,
@RW3+disp8 RW3
MOVW
RW6,
MOVW
RW7,
@RW2+disp8 RW2
MOVW
RW6,
MOVW
RW7,
@RW1+disp8 RW1
MOVW
RW6,
MOVW
RW7,
@RW0+disp8 RW0
MOVW
RW6,
D0
MOVW
RW7,
addr16
@PC+disp16
MOVW
RW7,
@RW1+RW7
MOVW
RW7,
@RW0+RW7
MOVW
RW7,
@RW3+disp16
MOVW
RW7,
@RW2+disp16
MOVW
RW7,
@RW1+disp16
MOVW
RW7,
@RW0+disp16
MOVW
RW7,
@RW7+disp8
MOVW
RW7,
@RW6+disp8
MOVW
RW7,
@RW5+disp8
MOVW
RW7,
@RW4+disp8
MOVW
RW7,
@RW3+disp8
MOVW
RW7,
@RW2+disp8
MOVW
RW7,
@RW1+disp8
MOVW
RW7,
@RW0+disp8
MOVW
RW7,
F0
APPENDIX C
MOVW
RW1,
@RW0+
MOVW
RW0,
MOVW
+1 RW0,
RW1
RW0
20
MOVW
RW1,
@RW0+disp8 RW0
MOVW
RW0,
MOVW
+0 RW0,
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ MOVW RWi, ea Instruction Map
Table C-16 MOVW RWi, ea Instruction (First Byte = 7BH)
397
APPENDIX
APPENDIX C
F2MC-16LX Instruction Maps
F2MC-16LX Family
C.10 MOV ea, Ri Instruction Map
Table C-17lists MOV ea, Ri instruction map.
398
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
MOV
@RW0+disp16, @RW0,
R1
R2
MOV
MOV
@RW3+disp8, R3,
R0
R1
MOV
MOV
@RW4+disp8, R4,
R0
R1
MOV
MOV
@RW5+disp8, R5,
R0
R1
MOV
MOV
@RW6+disp8, R6,
R0
R1
MOV
MOV
@RW7+disp8, R7,
R0
R1
MOV
MOV
@RW0+disp16, @RW0,
R0
R1
MOV
MOV
@RW1+disp16, @RW1,
R0
R1
MOV
MOV
@RW2+disp16, @RW2,
R0
R1
MOV
MOV
@RW3+disp16, @RW3,
R0
R1
MOV
MOV
@RW0+RW7, @RW0+,
R0
R1
MOV
MOV
@RW1+RW7, @RW1+,
R0
R1
MOV
MOV
@PC+disp16, @RW2+,
R0
R1
MOV
addr16,
R0
MOV
+4 R4,
R0
MOV
+5 R5,
R0
MOV
+6 R6,
R0
MOV
+7 R7,
R0
MOV
+8 @RW0,
R0
MOV
+9 @RW1,
R0
MOV
+A @RW2,
R0
MOV
+B @RW3,
R0
FUJITSU MICROELECTRONICS LIMITED
MOV
+C @RW0+,
R0
MOV
+D @RW1+,
R0
MOV
+E @RW2+,
R0
MOV
+F @RW3+,
R0
MOV
@RW3+disp16, @RW3,
R2
R3
MOV
MOV
@RW2+disp16, @RW2,
R2
R3
MOV
MOV
@RW1+disp16, @RW1,
R2
R3
MOV
MOV
@RW0+disp16, @RW0,
R2
R3
MOV
MOV
@RW7+disp8, R7,
R2
R3
MOV
MOV
@RW6+disp8, R6,
R2
R3
MOV
MOV
@RW5+disp8, R5,
R2
R3
MOV
MOV
@RW4+disp8, R4,
R2
R3
MOV
MOV
@RW3+disp8, R3,
R2
R3
MOV
MOV
@RW2+disp8, R2,
R2
R3
MOV
MOV
addr16,
R1
MOV
MOV
@RW3+, addr16,
R2
R2
MOV
@RW3+,
R3
MOV
MOV
MOV
@PC+disp16, @RW2+, @PC+disp16, @RW2+,
R1
R2
R2
R3
MOV
MOV
MOV
MOV
@RW1+RW7, @RW1+, @RW1+RW7, @RW1+,
R1
R2
R2
R3
MOV
MOV
MOV
MOV
@RW0+RW7, @RW0+, @RW0+RW7, @RW0+,
R1
R2
R2
R3
MOV
MOV
@RW3+disp16, @RW3,
R1
R2
MOV
MOV
@RW2+disp16, @RW2,
R1
R2
MOV
MOV
@RW1+disp16, @RW1,
R1
R2
MOV
@RW7+disp8, R7,
R1
R2
MOV
MOV
@RW6+disp8, R6,
R1
R2
MOV
MOV
@RW5+disp8, R5,
R1
R2
MOV
MOV
@RW4+disp8, R4,
R1
R2
MOV
MOV
@RW3+disp8, R3,
R1
R2
MOV
R3
MOV
@RW1+disp8, R1,
R2
R3
MOV
R2
60
MOV
@RW0+disp8, R0,
MOV
50
R4
MOV
addr16,
R3
MOV
@RW3+,
R4
MOV
@PC+disp16, @RW2+,
R3
R4
MOV
MOV
@RW1+RW7, @RW1+,
R3
R4
MOV
MOV
@RW0+RW7, @RW0+,
R3
R4
MOV
MOV
@RW3+disp16, @RW3,
R3
R4
MOV
MOV
@RW2+disp16, @RW2,
R3
R4
MOV
MOV
@RW1+disp16, @RW1,
R3
R4
MOV
MOV
@RW0+disp16, @RW0,
R3
R4
MOV
MOV
@RW7+disp8, R7,
R3
R4
MOV
MOV
@RW6+disp8, R6,
R3
R4
MOV
MOV
@RW5+disp8, R5,
R3
R4
MOV
MOV
@RW4+disp8, R4,
R3
R4
MOV
MOV
@RW3+disp8, R3,
R3
R4
MOV
MOV
@RW2+disp8, R2,
R3
R4
MOV
MOV
@RW1+disp8, R1,
R3
R4
MOV
R3
80
MOV
@RW0+disp8, R0,
MOV
70
R5
MOV
addr16,
R4
MOV
@RW3+,
R5
MOV
@PC+disp16, @RW2+,
R4
R5
MOV
MOV
@RW1+RW7, @RW1+,
R4
R5
MOV
MOV
@RW0+RW7, @RW0+,
R4
R5
MOV
MOV
@RW3+disp16, @RW3,
R4
R5
MOV
MOV
@RW2+disp16, @RW2,
R4
R5
MOV
MOV
@RW1+disp16, @RW1,
R4
R5
MOV
MOV
@RW0+disp16, @RW0,
R4
R5
MOV
MOV
@RW7+disp8, R7,
R4
R5
MOV
MOV
@RW6+disp8, R6,
R4
R5
MOV
MOV
@RW5+disp8, R5,
R4
R5
MOV
MOV
@RW4+disp8, R4,
R4
R5
MOV
MOV
@RW3+disp8, R3,
R4
R5
MOV
MOV
@RW2+disp8, R2,
R4
R5
MOV
MOV
@RW1+disp8, R1,
R4
R5
MOV
R4
A0
MOV
@RW0+disp8, R0,
MOV
90
R6
MOV
addr16,
R5
MOV
@RW3+,
R6
MOV
@PC+disp16, @RW2+,
R5
R6
MOV
MOV
@RW1+RW7, @RW1+,
R5
R6
MOV
MOV
@RW0+RW7, @RW0+,
R5
R6
MOV
MOV
@RW3+disp16, @RW3,
R5
R6
MOV
MOV
@RW2+disp16, @RW2,
R5
R6
MOV
MOV
@RW1+disp16, @RW1,
R5
R6
MOV
MOV
@RW0+disp16, @RW0,
R5
R6
MOV
MOV
@RW7+disp8, R7,
R5
R6
MOV
MOV
@RW6+disp8, R6,
R5
R6
MOV
MOV
@RW5+disp8, R5,
R5
R6
MOV
MOV
@RW4+disp8, R4,
R5
R6
MOV
MOV
@RW3+disp8, R3,
R5
R6
MOV
MOV
@RW2+disp8, R2,
R5
R6
MOV
MOV
@RW1+disp8, R1,
R5
R6
MOV
R5
C0
MOV
@RW0+disp8, R0,
MOV
B0
R7
MOV
addr16,
R6
MOV
@RW3+,
R7
MOV
@PC+disp16, @RW2+,
R6
R7
MOV
MOV
@RW1+RW7, @RW1+,
R6
R7
MOV
MOV
@RW0+RW7, @RW0+,
R6
R7
MOV
MOV
@RW3+disp16, @RW3,
R6
R7
MOV
MOV
@RW2+disp16, @RW2,
R6
R7
MOV
MOV
@RW1+disp16, @RW1,
R6
R7
MOV
MOV
@RW0+disp16, @RW0,
R6
R7
MOV
MOV
@RW7+disp8, R7,
R6
R7
MOV
MOV
@RW6+disp8, R6,
R6
R7
MOV
MOV
@RW5+disp8, R5,
R6
R7
MOV
MOV
@RW4+disp8, R4,
R6
R7
MOV
MOV
@RW3+disp8, R3,
R6
R7
MOV
MOV
@RW2+disp8, R2,
R6
R7
MOV
MOV
@RW1+disp8, R1,
R6
R7
MOV
R6
E0
MOV
@RW0+disp8, R0,
MOV
D0
MOV
addr16,
R7
R7
@PC+disp16,
MOV
R7
@RW1+RW7,
MOV
R7
@RW0+RW7,
MOV
R7
@RW3+disp16,
MOV
R7
@RW2+disp16,
MOV
R7
@RW1+disp16,
MOV
R7
@RW0+disp16,
MOV
R7
@RW7+disp8,
MOV
R7
@RW6+disp8,
MOV
R7
@RW5+disp8,
MOV
R7
@RW4+disp8,
MOV
R7
@RW3+disp8,
MOV
R7
@RW2+disp8,
MOV
R7
@RW1+disp8,
MOV
R7
@RW0+disp8,
MOV
F0
APPENDIX C
MOV
@RW3+,
R1
MOV
MOV
MOV
+3 R3,
R0
MOV
@RW2+disp8, R2,
R1
R2
MOV
@RW2+disp8, R2,
R0
R1
MOV
MOV
MOV
+2 R2,
R0
MOV
@RW1+disp8, R1,
R1
R2
MOV
@RW1+disp8, R1,
R0
R1
MOV
MOV
R2
R1
R1
40
MOV
R0
MOV
30
@RW0+disp8, R0,
MOV
20
@RW0+disp8, R0,
MOV
10
MOV
+1 R1,
R0
R0
+0 R0,
MOV
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ MOV ea, Ri Instruction Map
Table C-17 MOV ea, Ri Instruction (First Byte = 7CH)
399
APPENDIX
APPENDIX C
F2MC-16LX Instruction Maps
F2MC-16LX Family
C.11 MOVW ea, RWi Instruction Map
Table C-18lists MOVW ea, RWi instruction map.
400
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
MOVW
@RW0+disp16, @RW0,
RW1
RW2
MOVW
MOVW
@RW3+disp8, RW3,
RW0
RW1
MOVW
MOVW
@RW4+disp8, RW4,
RW0
RW1
MOVW
MOVW
@RW5+disp8, RW5,
RW0
RW1
MOVW
MOVW
@RW6+disp8, RW6,
RW0
RW1
MOVW
MOVW
@RW7+disp8, RW7,
RW0
RW1
MOVW
MOVW
@RW0+disp16, @RW0,
RW0
RW1
MOVW
MOVW
@RW1+disp16, @RW1,
RW0
RW1
MOVW
MOVW
@RW2+disp16, @RW2,
RW0
RW1
MOVW
MOVW
@RW3+disp16, @RW3,
RW0
RW1
MOVW
MOVW
@RW0+RW7, @RW0+,
RW0
RW1
MOVW
MOVW
@RW1+RW7, @RW1+,
RW0
RW1
MOVW
MOVW
@PC+disp16, @RW2+,
RW0
RW1
MOVW
addr16,
RW0
MOVW
+4 RW4,
RW0
MOVW
+5 RW5,
RW0
MOVW
+6 RW6,
RW0
MOVW
+7 RW7,
RW0
MOVW
+8 @RW0,
RW0
MOVW
+9 @RW1,
RW0
MOVW
+A @RW2,
RW0
MOVW
+B @RW3,
RW0
FUJITSU MICROELECTRONICS LIMITED
MOVW
+C @RW0+,
RW0
MOVW
+D @RW1+,
RW0
MOVW
+E @RW2+,
RW0
MOVW
+F @RW3+,
RW0
MOVW
addr16,
RW1
MOVW
@RW3+,
RW2
MOVW
@PC+disp16, @RW2+,
RW1
RW2
MOVW
MOVW
@RW1+RW7, @RW1+,
RW1
RW2
MOVW
MOVW
@RW0+RW7, @RW0+,
RW1
RW2
MOVW
MOVW
@RW3+disp16, @RW3,
RW1
RW2
MOVW
MOVW
@RW2+disp16, @RW2,
RW1
RW2
MOVW
MOVW
@RW1+disp16, @RW1,
RW1
RW2
MOVW
@RW7+disp8, RW7,
RW1
RW2
MOVW
MOVW
@RW6+disp8, RW6,
RW1
RW2
MOVW
MOVW
@RW5+disp8, RW5,
RW1
RW2
MOVW
MOVW
@RW4+disp8, RW4,
RW1
RW2
MOVW
MOVW
@RW3+disp8, RW3,
RW1
RW2
MOVW
MOVW
60
RW3
MOVW
addr16,
RW2
MOVW
@RW3+,
RW3
MOVW
@PC+disp16, @RW2+,
RW2
RW3
MOVW
MOVW
@RW1+RW7, @RW1+,
RW2
RW3
MOVW
MOVW
@RW0+RW7, @RW0+,
RW2
RW3
MOVW
MOVW
@RW3+disp16, @RW3,
RW2
RW3
MOVW
MOVW
@RW2+disp16, @RW2,
RW2
RW3
MOVW
MOVW
@RW1+disp16, @RW1,
RW2
RW3
MOVW
MOVW
@RW0+disp16, @RW0,
RW2
RW3
MOVW
MOVW
@RW7+disp8, RW7,
RW2
RW3
MOVW
MOVW
@RW6+disp8, RW6,
RW2
RW3
MOVW
MOVW
@RW5+disp8, RW5,
RW2
RW3
MOVW
MOVW
@RW4+disp8, RW4,
RW2
RW3
MOVW
MOVW
@RW3+disp8, RW3,
RW2
RW3
MOVW
MOVW
@RW2+disp8, RW2,
RW2
RW3
MOVW
MOVW
@RW1+disp8, RW1,
RW2
RW3
MOVW
RW2
@RW0+disp8, RW0,
MOVW
50
MOVW
80
RW4
MOVW
addr16,
RW3
MOVW
@RW3+,
RW4
MOVW
@PC+disp16, @RW2+,
RW3
RW4
MOVW
MOVW
@RW1+RW7, @RW1+,
RW3
RW4
MOVW
MOVW
@RW0+RW7, @RW0+,
RW3
RW4
MOVW
MOVW
@RW3+disp16, @RW3,
RW3
RW4
MOVW
MOVW
@RW2+disp16, @RW2,
RW3
RW4
MOVW
MOVW
@RW1+disp16, @RW1,
RW3
RW4
MOVW
MOVW
@RW0+disp16, @RW0,
RW3
RW4
MOVW
MOVW
@RW7+disp8, RW7,
RW3
RW4
MOVW
MOVW
@RW6+disp8, RW6,
RW3
RW4
MOVW
MOVW
@RW5+disp8, RW5,
RW3
RW4
MOVW
MOVW
@RW4+disp8, RW4,
RW3
RW4
MOVW
MOVW
@RW3+disp8, RW3,
RW3
RW4
MOVW
MOVW
@RW2+disp8, RW2,
RW3
RW4
MOVW
MOVW
@RW1+disp8, RW1,
RW3
RW4
MOVW
RW3
@RW0+disp8, RW0,
MOVW
70
MOVW
A0
RW5
MOVW
addr16,
RW4
MOVW
@RW3+,
RW5
MOVW
@PC+disp16, @RW2+,
RW4
RW5
MOVW
MOVW
@RW1+RW7, @RW1+,
RW4
RW5
MOVW
MOVW
@RW0+RW7, @RW0+,
RW4
RW5
MOVW
MOVW
@RW3+disp16, @RW3,
RW4
RW5
MOVW
MOVW
@RW2+disp16, @RW2,
RW4
RW5
MOVW
MOVW
@RW1+disp16, @RW1,
RW4
RW5
MOVW
MOVW
@RW0+disp16, @RW0,
RW4
RW5
MOVW
MOVW
@RW7+disp8, RW7,
RW4
RW5
MOVW
MOVW
@RW6+disp8, RW6,
RW4
RW5
MOVW
MOVW
@RW5+disp8, RW5,
RW4
RW5
MOVW
MOVW
@RW4+disp8, RW4,
RW4
RW5
MOVW
MOVW
@RW3+disp8, RW3,
RW4
RW5
MOVW
MOVW
@RW2+disp8, RW2,
RW4
RW5
MOVW
MOVW
@RW1+disp8, RW1,
RW4
RW5
MOVW
RW4
@RW0+disp8, RW0,
MOVW
90
MOVW
C0
RW6
MOVW
addr16,
RW5
MOVW
@RW3+,
RW6
MOVW
@PC+disp16, @RW2+,
RW5
RW6
MOVW
MOVW
@RW1+RW7, @RW1+,
RW5
RW6
MOVW
MOVW
@RW0+RW7, @RW0+,
RW5
RW6
MOVW
MOVW
@RW3+disp16, @RW3,
RW5
RW6
MOVW
MOVW
@RW2+disp16, @RW2,
RW5
RW6
MOVW
MOVW
@RW1+disp16, @RW1,
RW5
RW6
MOVW
MOVW
@RW0+disp16, @RW0,
RW5
RW6
MOVW
MOVW
@RW7+disp8, RW7,
RW5
RW6
MOVW
MOVW
@RW6+disp8, RW6,
RW5
RW6
MOVW
MOVW
@RW5+disp8, RW5,
RW5
RW6
MOVW
MOVW
@RW4+disp8, RW4,
RW5
RW6
MOVW
MOVW
@RW3+disp8, RW3,
RW5
RW6
MOVW
MOVW
@RW2+disp8, RW2,
RW5
RW6
MOVW
MOVW
@RW1+disp8, RW1,
RW5
RW6
MOVW
RW5
@RW0+disp8, RW0,
MOVW
B0
MOVW
E0
RW7
MOVW
addr16,
RW6
MOVW
@RW3+,
RW7
MOVW
@PC+disp16, @RW2+,
RW6
RW7
MOVW
MOVW
@RW1+RW7, @RW1+,
RW6
RW7
MOVW
MOVW
@RW0+RW7, @RW0+,
RW6
RW7
MOVW
MOVW
@RW3+disp16, @RW3,
RW6
RW7
MOVW
MOVW
@RW2+disp16, @RW2,
RW6
RW7
MOVW
MOVW
@RW1+disp16, @RW1,
RW6
RW7
MOVW
MOVW
@RW0+disp16, @RW0,
RW6
RW7
MOVW
MOVW
@RW7+disp8, RW7,
RW6
RW7
MOVW
MOVW
@RW6+disp8, RW6,
RW6
RW7
MOVW
MOVW
@RW5+disp8, RW5,
RW6
RW7
MOVW
MOVW
@RW4+disp8, RW4,
RW6
RW7
MOVW
MOVW
@RW3+disp8, RW3,
RW6
RW7
MOVW
MOVW
@RW2+disp8, RW2,
RW6
RW7
MOVW
MOVW
@RW1+disp8, RW1,
RW6
RW7
MOVW
RW6
@RW0+disp8, RW0,
MOVW
D0
MOVW
addr16,
RW7
RW7
@PC+disp16,
MOVW
RW7
@RW1+RW7,
MOVW
RW7
@RW0+RW7,
MOVW
RW7
@RW3+disp16,
MOVW
RW7
@RW2+disp16,
MOVW
RW7
@RW1+disp16,
MOVW
RW7
@RW0+disp16,
MOVW
RW7
@RW7+disp8,
MOVW
RW7
@RW6+disp8,
MOVW
RW7
@RW5+disp8,
MOVW
RW7
@RW4+disp8,
MOVW
RW7
@RW3+disp8,
MOVW
RW7
@RW2+disp8,
MOVW
RW7
@RW1+disp8,
MOVW
RW7
@RW0+disp8,
MOVW
F0
APPENDIX C
MOVW
@RW3+,
RW1
MOVW
MOVW
MOVW
+3 RW3,
RW0
MOVW
@RW2+disp8, RW2,
RW1
RW2
MOVW
@RW2+disp8, RW2,
RW0
RW1
MOVW
MOVW
MOVW
+2 RW2,
RW0
MOVW
@RW1+disp8, RW1,
RW1
RW2
MOVW
@RW1+disp8, RW1,
RW0
RW1
MOVW
MOVW
RW2
RW1
RW1
RW0
MOVW
40
MOVW
+1 RW1,
RW0
RW0
MOVW
30
@RW0+disp8, RW0,
MOVW
20
@RW0+disp8, RW0,
MOVW
MOVW
+0 RW0,
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ MOVW ea, RWi Instruction Map
Table C-18 MOVW ea, RWi Instruction (First Byte = 7DH)
401
APPENDIX
APPENDIX C
F2MC-16LX Instruction Maps
F2MC-16LX Family
C.12 XCH Ri, ea Instruction Map
Table C-19lists XCH Ri, ea instruction map.
402
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
20
XCH
R1,
@RW1+disp8 R1
XCH
R0,
XCH
R1,
@RW2+disp8 R2
XCH
R0,
XCH
R1,
@RW3+disp8 R3
XCH
R0,
XCH
R1,
@RW4+disp8 R4
XCH
R0,
XCH
R1,
@RW5+disp8 R5
XCH
R0,
XCH
R1,
@RW6+disp8 R6
XCH
R0,
XCH
R1,
@RW7+disp8 R7
XCH
R0,
XCH
R1,
@RW0+disp16 @RW0
XCH
R0,
XCH
R1,
@RW1+disp16 @RW1
XCH
R0,
XCH
R1,
@RW2+disp16 @RW2
XCH
R0,
XCH
R1,
@RW3+disp16 @RW3
XCH
R0,
XCH
R1,
@RW0+RW7 @RW0+
XCH
R0,
XCH
R1,
@RW1+RW7 @RW1+
XCH
R0,
XCH
R1,
@PC+disp16 @RW2+
XCH
R0,
addr16
XCH
+2 R0,
R2
XCH
+3 R0,
R3
XCH
+4 R0,
R4
XCH
+5 R0,
R5
XCH
+6 R0,
R6
XCH
+7 R0,
R7
XCH
+8 R0,
@RW0
XCH
+9 R0,
@RW1
XCH
+A R0,
@RW2
XCH
+B R0,
@RW3
XCH
+C R0,
@RW0+
XCH
+D R0,
@RW1+
XCH
+E R0,
@RW2+
XCH
+F R0,
@RW3+
40
FUJITSU MICROELECTRONICS LIMITED
XCH
R1,
addr16
XCH
R2,
@RW3+
XCH
R2,
@PC+disp16 @RW2+
XCH
R1,
XCH
R2,
@RW1+RW7 @RW1+
XCH
R1,
XCH
R2,
@RW0+RW7 @RW0+
XCH
R1,
XCH
R2,
@RW3+disp16 @RW3
XCH
R1,
XCH
R2,
@RW2+disp16 @RW2
XCH
R1,
XCH
R2,
@RW1+disp16 @RW1
XCH
R1,
XCH
R2,
@RW0+disp16 @RW0
XCH
R1,
XCH
R2,
@RW7+disp8 R7
XCH
R1,
XCH
R2,
@RW6+disp8 R6
XCH
R1,
XCH
R2,
@RW5+disp8 R5
XCH
R1,
XCH
R2,
@RW4+disp8 R4
XCH
R1,
XCH
R2,
@RW3+disp8 R3
XCH
R1,
XCH
R2,
@RW2+disp8 R2
XCH
R1,
XCH
R2,
@RW1+disp8 R1
XCH
R1,
XCH
R2,
@RW0+disp8 R0
XCH
R1,
30
60
XCH
R2,
addr16
XCH
R3,
@RW3+
XCH
R3,
@PC+disp16 @RW2+
XCH
R2,
XCH
R3,
@RW1+RW7 @RW1+
XCH
R2,
XCH
R3,
@RW0+RW7 @RW0+
XCH
R2,
XCH
R3,
@RW3+disp16 @RW3
XCH
R2,
XCH
R3,
@RW2+disp16 @RW2
XCH
R2,
XCH
R3,
@RW1+disp16 @RW1
XCH
R2,
XCH
R3,
@RW0+disp16 @RW0
XCH
R2,
XCH
R3,
@RW7+disp8 R7
XCH
R2,
XCH
R3,
@RW6+disp8 R6
XCH
R2,
XCH
R3,
@RW5+disp8 R5
XCH
R2,
XCH
R3,
@RW4+disp8 R4
XCH
R2,
XCH
R3,
@RW3+disp8 R3
XCH
R2,
XCH
R3,
@RW2+disp8 R2
XCH
R2,
XCH
R3,
@RW1+disp8 R1
XCH
R2,
XCH
R3,
@RW0+disp8 R0
XCH
R2,
50
80
XCH
R3,
addr16
XCH
R4,
@RW3+
XCH
R4,
@PC+disp16 @RW2+
XCH
R3,
XCH
R4,
@RW1+RW7 @RW1+
XCH
R3,
XCH
R4,
@RW0+RW7 @RW0+
XCH
R3,
XCH
R4,
@RW3+disp16 @RW3
XCH
R3,
XCH
R4,
@RW2+disp16 @RW2
XCH
R3,
XCH
R4,
@RW1+disp16 @RW1
XCH
R3,
XCH
R4,
@RW0+disp16 @RW0
XCH
R3,
XCH
R4,
@RW7+disp8 R7
XCH
R3,
XCH
R4,
@RW6+disp8 R6
XCH
R3,
XCH
R4,
@RW5+disp8 R5
XCH
R3,
XCH
R4,
@RW4+disp8 R4
XCH
R3,
XCH
R4,
@RW3+disp8 R3
XCH
R3,
XCH
R4,
@RW2+disp8 R2
XCH
R3,
XCH
R4,
@RW1+disp8 R1
XCH
R3,
XCH
R4,
@RW0+disp8 R0
XCH
R3,
70
A0
XCH
R4,
addr16
XCH
R5,
@RW3+
XCH
R5,
@PC+disp16 @RW2+
XCH
R4,
XCH
R5,
@RW1+RW7 @RW1+
XCH
R4,
XCH
R5,
@RW0+RW7 @RW0+
XCH
R4,
XCH
R5,
@RW3+disp16 @RW3
XCH
R4,
XCH
R5,
@RW2+disp16 @RW2
XCH
R4,
XCH
R5,
@RW1+disp16 @RW1
XCH
R4,
XCH
R5,
@RW0+disp16 @RW0
XCH
R4,
XCH
R5,
@RW7+disp8 R7
XCH
R4,
XCH
R5,
@RW6+disp8 R6
XCH
R4,
XCH
R5,
@RW5+disp8 R5
XCH
R4,
XCH
R5,
@RW4+disp8 R4
XCH
R4,
XCH
R5,
@RW3+disp8 R3
XCH
R4,
XCH
R5,
@RW2+disp8 R2
XCH
R4,
XCH
R5,
@RW1+disp8 R1
XCH
R4,
XCH
R5,
@RW0+disp8 R0
XCH
R4,
90
C0
XCH
R5,
addr16
XCH
R6,
@RW3+
XCH
R6,
@PC+disp16 @RW2+
XCH
R5,
XCH
R6,
@RW1+RW7 @RW1+
XCH
R5,
XCH
R6,
@RW0+RW7 @RW0+
XCH
R5,
XCH
R6,
@RW3+disp16 @RW3
XCH
R5,
XCH
R6,
@RW2+disp16 @RW2
XCH
R5,
XCH
R6,
@RW1+disp16 @RW1
XCH
R5,
XCH
R6,
@RW0+disp16 @RW0
XCH
R5,
XCH
R6,
@RW7+disp8 R7
XCH
R5,
XCH
R6,
@RW6+disp8 R6
XCH
R5,
XCH
R6,
@RW5+disp8 R5
XCH
R5,
XCH
R6,
@RW4+disp8 R4
XCH
R5,
XCH
R6,
@RW3+disp8 R3
XCH
R5,
XCH
R6,
@RW2+disp8 R2
XCH
R5,
XCH
R6,
@RW1+disp8 R1
XCH
R5,
XCH
R6,
@RW0+disp8 R0
XCH
R5,
B0
E0
XCH
R6,
addr16
XCH
R7,
@RW3+
XCH
R7,
@PC+disp16 @RW2+
XCH
R6,
XCH
R7,
@RW1+RW7 @RW1+
XCH
R6,
XCH
R7,
@RW0+RW7 @RW0+
XCH
R6,
XCH
R7,
@RW3+disp16 @RW3
XCH
R6,
XCH
R7,
@RW2+disp16 @RW2
XCH
R6,
XCH
R7,
@RW1+disp16 @RW1
XCH
R6,
XCH
R7,
@RW0+disp16 @RW0
XCH
R6,
XCH
R7,
@RW7+disp8 R7
XCH
R6,
XCH
R7,
@RW6+disp8 R6
XCH
R6,
XCH
R7,
@RW5+disp8 R5
XCH
R6,
XCH
R7,
@RW4+disp8 R4
XCH
R6,
XCH
R7,
@RW3+disp8 R3
XCH
R6,
XCH
R7,
@RW2+disp8 R2
XCH
R6,
XCH
R7,
@RW1+disp8 R1
XCH
R6,
XCH
R7,
@RW0+disp8 R0
XCH
R6,
D0
XCH
R7,
addr16
@PC+disp16
XCH
R7,
@RW1+RW7
XCH
R7,
@RW0+RW7
XCH
R7,
@RW3+disp16
XCH
R7,
@RW2+disp16
XCH
R7,
@RW1+disp16
XCH
R7,
@RW0+disp16
XCH
R7,
@RW7+disp8
XCH
R7,
@RW6+disp8
XCH
R7,
@RW5+disp8
XCH
R7,
@RW4+disp8
XCH
R7,
@RW3+disp8
XCH
R7,
@RW2+disp8
XCH
R7,
@RW1+disp8
XCH
R7,
@RW0+disp8
XCH
R7,
F0
APPENDIX C
XCH
R1,
@RW3+
XCH
R0,
XCH
R1,
@RW0+disp8 R0
XCH
R0,
10
XCH
+1 R0,
R1
R0
+0 R0,
XCH
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ XCH Ri, ea Instruction Map
Table C-19 XCH Ri, ea Instruction (First Byte = 7EH)
403
APPENDIX
APPENDIX C
F2MC-16LX Instruction Maps
F2MC-16LX Family
C.13 XCHW RWi, ea Instruction Map
Table C-20lists XCHW RWi, ea instruction map.
404
FUJITSU MICROELECTRONICS LIMITED
CM44-00201-4E
CM44-00201-4E
FUJITSU MICROELECTRONICS LIMITED
XCHW
RW1,
@RW2+disp8 RW2
XCHW
RW0,
XCHW
RW1,
@RW3+disp8 RW3
XCHW
RW0,
XCHW
RW1,
@RW4+disp8 RW4
XCHW
RW0,
XCHW
RW1,
@RW5+disp8 RW5
XCHW
RW0,
XCHW
RW1,
@RW6+disp8 RW6
XCHW
RW0,
XCHW
RW1,
@RW7+disp8 RW7
XCHW
RW0,
XCHW
RW1,
@RW0+disp16 @RW0
XCHW
RW0,
XCHW
RW1,
@RW1+disp16 @RW1
XCHW
RW0,
XCHW
RW1,
@RW2+disp16 @RW2
XCHW
RW0,
XCHW
RW1,
@RW3+disp16 @RW3
XCHW
RW0,
XCHW
+3 RW0,
RW3
XCHW
+4 RW0,
RW4
XCHW
+5 RW0,
RW5
XCHW
+6 RW0,
RW6
XCHW
+7 RW0,
RW7
XCHW
+8 RW0,
@RW0
XCHW
+9 RW0,
@RW1
XCHW
+A RW0,
@RW2
XCHW
+B RW0,
@RW3
XCHW
+C RW0,
@RW0+
@PC+disp16
XCHW
RW0,
addr16
XCHW
+F RW0,
@RW3+
XCHW
RW0,
XCHW
+E RW0,
@RW2+
@RW1+RW7
XCHW
RW0,
@RW0+RW7
XCHW
RW0,
XCHW
+2 RW0,
RW2
XCHW
+D RW0,
@RW1+
XCHW
RW1,
@RW1+disp8 RW1
XCHW
RW1,
@RW3+
XCHW
RW1,
@RW2+
XCHW
RW1,
@RW1+
40
XCHW
RW1,
addr16
@PC+disp16
XCHW
RW1,
@RW1+RW7
XCHW
RW1,
@RW0+RW7
XCHW
RW1,
XCHW
RW2,
@RW3+
XCHW
RW2,
@RW2+
XCHW
RW2,
@RW1+
XCHW
RW2,
@RW0+
XCHW
RW2,
@RW3+disp16 @RW3
XCHW
RW1,
XCHW
RW2,
@RW2+disp16 @RW2
XCHW
RW1,
XCHW
RW2,
@RW1+disp16 @RW1
XCHW
RW1,
XCHW
RW2,
@RW0+disp16 @RW0
XCHW
RW1,
XCHW
RW2,
@RW7+disp8 RW7
XCHW
RW1,
XCHW
RW2,
@RW6+disp8 RW6
XCHW
RW1,
XCHW
RW2,
@RW5+disp8 RW5
XCHW
RW1,
XCHW
RW2,
@RW4+disp8 RW4
XCHW
RW1,
XCHW
RW2,
@RW3+disp8 RW3
XCHW
RW1,
XCHW
RW2,
@RW2+disp8 RW2
XCHW
RW1,
XCHW
RW2,
@RW1+disp8 RW1
XCHW
RW1,
XCHW
RW2,
@RW0+disp8 RW0
XCHW
RW1,
30
60
XCHW
RW2,
addr16
@PC+disp16
XCHW
RW2,
@RW1+RW7
XCHW
RW2,
@RW0+RW7
XCHW
RW2,
XCHW
RW3,
@RW3+
XCHW
RW3,
@RW2+
XCHW
RW3,
@RW1+
XCHW
RW3,
@RW0+
XCHW
RW3,
@RW3+disp16 @RW3
XCHW
RW2,
XCHW
RW3,
@RW2+disp16 @RW2
XCHW
RW2,
XCHW
RW3,
@RW1+disp16 @RW1
XCHW
RW2,
XCHW
RW3,
@RW0+disp16 @RW0
XCHW
RW2,
XCHW
RW3,
@RW7+disp8 RW7
XCHW
RW2,
XCHW
RW3,
@RW6+disp8 RW6
XCHW
RW2,
XCHW
RW3,
@RW5+disp8 RW5
XCHW
RW2,
XCHW
RW3,
@RW4+disp8 RW4
XCHW
RW2,
XCHW
RW3,
@RW3+disp8 RW3
XCHW
RW2,
XCHW
RW3,
@RW2+disp8 RW2
XCHW
RW2,
XCHW
RW3,
@RW1+disp8 RW1
XCHW
RW2,
XCHW
RW3,
@RW0+disp8 RW0
XCHW
RW2,
50
80
XCHW
RW3,
addr16
@PC+disp16
XCHW
RW3,
@RW1+RW7
XCHW
RW3,
@RW0+RW7
XCHW
RW3,
XCHW
RW4,
@RW3+
XCHW
RW4,
@RW2+
XCHW
RW4,
@RW1+
XCHW
RW4,
@RW0+
XCHW
RW4,
@RW3+disp16 @RW3
XCHW
RW3,
XCHW
RW4,
@RW2+disp16 @RW2
XCHW
RW3,
XCHW
RW4,
@RW1+disp16 @RW1
XCHW
RW3,
XCHW
RW4,
@RW0+disp16 @RW0
XCHW
RW3,
XCHW
RW4,
@RW7+disp8 RW7
XCHW
RW3,
XCHW
RW4,
@RW6+disp8 RW6
XCHW
RW3,
XCHW
RW4,
@RW5+disp8 RW5
XCHW
RW3,
XCHW
RW4,
@RW4+disp8 RW4
XCHW
RW3,
XCHW
RW4,
@RW3+disp8 RW3
XCHW
RW3,
XCHW
RW4,
@RW2+disp8 RW2
XCHW
RW3,
XCHW
RW4,
@RW1+disp8 RW1
XCHW
RW3,
XCHW
RW4,
@RW0+disp8 RW0
XCHW
RW3,
70
A0
XCHW
RW4,
addr16
@PC+disp16
XCHW
RW4,
@RW1+RW7
XCHW
RW4,
@RW0+RW7
XCHW
RW4,
XCHW
RW5,
@RW3+
XCHW
RW5,
@RW2+
XCHW
RW5,
@RW1+
XCHW
RW5,
@RW0+
XCHW
RW5,
@RW3+disp16 @RW3
XCHW
RW4,
XCHW
RW5,
@RW2+disp16 @RW2
XCHW
RW4,
XCHW
RW5,
@RW1+disp16 @RW1
XCHW
RW4,
XCHW
RW5,
@RW0+disp16 @RW0
XCHW
RW4,
XCHW
RW5,
@RW7+disp8 RW7
XCHW
RW4,
XCHW
RW5,
@RW6+disp8 RW6
XCHW
RW4,
XCHW
RW5,
@RW5+disp8 RW5
XCHW
RW4,
XCHW
RW5,
@RW4+disp8 RW4
XCHW
RW4,
XCHW
RW5,
@RW3+disp8 RW3
XCHW
RW4,
XCHW
RW5,
@RW2+disp8 RW2
XCHW
RW4,
XCHW
RW5,
@RW1+disp8 RW1
XCHW
RW4,
XCHW
RW5,
@RW0+disp8 RW0
XCHW
RW4,
90
C0
XCHW
RW5,
addr16
@PC+disp16
XCHW
RW5,
@RW1+RW7
XCHW
RW5,
@RW0+RW7
XCHW
RW5,
XCHW
RW6,
@RW3+
XCHW
RW6,
@RW2+
XCHW
RW6,
@RW1+
XCHW
RW6,
@RW0+
XCHW
RW6,
@RW3+disp16 @RW3
XCHW
RW5,
XCHW
RW6,
@RW2+disp16 @RW2
XCHW
RW5,
XCHW
RW6,
@RW1+disp16 @RW1
XCHW
RW5,
XCHW
RW6,
@RW0+disp16 @RW0
XCHW
RW5,
XCHW
RW6,
@RW7+disp8 RW7
XCHW
RW5,
XCHW
RW6,
@RW6+disp8 RW6
XCHW
RW5,
XCHW
RW6,
@RW5+disp8 RW5
XCHW
RW5,
XCHW
RW6,
@RW4+disp8 RW4
XCHW
RW5,
XCHW
RW6,
@RW3+disp8 RW3
XCHW
RW5,
XCHW
RW6,
@RW2+disp8 RW2
XCHW
RW5,
XCHW
RW6,
@RW1+disp8 RW1
XCHW
RW5,
XCHW
RW6,
@RW0+disp8 RW0
XCHW
RW5,
B0
E0
XCHW
RW6,
addr16
@PC+disp16
XCHW
RW6,
@RW1+RW7
XCHW
RW6,
@RW0+RW7
XCHW
RW6,
XCHW
RW7,
@RW3+
XCHW
RW7,
@RW2+
XCHW
RW7,
@RW1+
XCHW
RW7,
@RW0+
XCHW
RW7,
@RW3+disp16 @RW3
XCHW
RW6,
XCHW
RW7,
@RW2+disp16 @RW2
XCHW
RW6,
XCHW
RW7,
@RW1+disp16 @RW1
XCHW
RW6,
XCHW
RW7,
@RW0+disp16 @RW0
XCHW
RW6,
XCHW
RW7,
@RW7+disp8 RW7
XCHW
RW6,
XCHW
RW7,
@RW6+disp8 RW6
XCHW
RW6,
XCHW
RW7,
@RW5+disp8 RW5
XCHW
RW6,
XCHW
RW7,
@RW4+disp8 RW4
XCHW
RW6,
XCHW
RW7,
@RW3+disp8 RW3
XCHW
RW6,
XCHW
RW7,
@RW2+disp8 RW2
XCHW
RW6,
XCHW
RW7,
@RW1+disp8 RW1
XCHW
RW6,
XCHW
RW7,
@RW0+disp8 RW0
XCHW
RW6,
D0
XCHW
RW7,
addr16
@PC+disp16
XCHW
RW7,
@RW1+RW7
XCHW
RW7,
@RW0+RW7
XCHW
RW7,
@RW3+disp16
XCHW
RW7,
@RW2+disp16
XCHW
RW7,
@RW1+disp16
XCHW
RW7,
@RW0+disp16
XCHW
RW7,
@RW7+disp8
XCHW
RW7,
@RW6+disp8
XCHW
RW7,
@RW5+disp8
XCHW
RW7,
@RW4+disp8
XCHW
RW7,
@RW3+disp8
XCHW
RW7,
@RW2+disp8
XCHW
RW7,
@RW1+disp8
XCHW
RW7,
@RW0+disp8
XCHW
RW7,
F0
APPENDIX C
XCHW
RW1,
@RW0+
XCHW
RW0,
XCHW
+1 RW0,
RW1
RW0
20
XCHW
RW1,
@RW0+disp8 RW0
XCHW
RW0,
XCHW
+0 RW0,
10
00
F2MC-16LX Family
APPENDIX
F2MC-16LX Instruction Maps
■ XCHW RWi, ea Instruction Map
Table C-20 XCHW RWi, ea Instruction (First Byte = 7FH)
405
APPENDIX
APPENDIX C
406
F2MC-16LX Instruction Maps
FUJITSU MICROELECTRONICS LIMITED
F2MC-16LX Family
CM44-00201-4E
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
375
INDEX
Index
Numerics
2-byte Instruction
2-byte Instruction Map...................................... 349
A
A
Accumulator (A) ................................................ 16
Accumulator
Accumulator (A) ................................................ 16
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator) ....... 84
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator)........................................ 86
ASR (Arithmetic Shift Byte Data of Accumulator to
Right)................................................. 104
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 106
ASRW (Arithmetic Shift Word Data of Accumulator
to Right) ..................................... 108, 110
LSL (Logical Shift Byte Data of Accumulator to Left)
174
LSLL (Logical Shift Long Word Data of Accumulator
to Left) ............................................... 176
LSLW (Logical Shift Word Data of Accumulator to
Left)........................................... 178, 179
LSR (Logical Shift Byte Data of Accumulator to
Right)................................................. 181
LSRL (Logical Shift Long Word Data of Accumulator
to Right) ............................................. 183
LSRW (Logical Shift Word Data of Accumulator to
Right)......................................... 185, 187
MOV (Move Byte Data from Accumulator to
Destination) ........................................ 191
MOV (Move Byte Data from Source to Accumulator)
189
MOVB (Move Bit Data from Accumulator to Bit
Address)............................................. 201
MOVB (Move Bit Data from Bit Address to
Accumulator)...................................... 199
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................ 206
MOVL (Move Long Word Data from Source to
Accumulator)...................................... 205
MOVN (Move Immediate Nibble Data to
Accumulator)...................................... 207
MOVW (Move Word Data from Accumulator to
Destination) ........................................ 214
MOVW (Move Word Data from Source to
Accumulator)...................................... 212
376
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 222
MUL (Multiply Byte Data of Accumulator)........ 224
MUL (Multiply Byte Data of Accumulator and
Effective Address) .............................. 225
MULU (Multiply Unsigned Byte Data of
Accumulator) ..................................... 230
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 231
MULUW (Multiply Unsigned Word Data of
Accumulator) ..................................... 233
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)..... 234
MULW (Multiply Word Data of Accumulator)... 227
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 228
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 254
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 272
RORC (Rotate Byte Data of Accumulator with Carry
to Right)............................................. 274
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)....
286
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 288
SWAP (Swap Byte Data of Accumulator) .......... 296
SWAPW (Swap Word Data of Accumulator) ..... 297
ADD
ADD (Add Byte Data of Destination and Source to
Destination).......................................... 81
ADDC
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 84
ADDC (Add Byte Data of AL and AH with Carry to
AL) ..................................................... 83
ADDCW
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 86
ADDDC
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 88
ADDL
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 89
Address Specification
INC (Increment Byte Data (Address Specification))
......................................................... 155
INDEX
Addressing
Bank Addressing Mode ........................................ 8
Direct Addressing .............................................. 63
Indirect Addressing ............................................ 65
Linear Addressing Mode....................................... 7
ADDSP
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ........... 91
ADDW
ADDW (Add Word Data of AL and AH to AL) .... 92
ADDW (Add Word Data of Destination and Source to
Destination).......................................... 93
AND
AND (And Byte Data of Destination and Source to
Destination).......................................... 95
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 97
AND (And Byte Data of Destination and Source to
Destination).......................................... 95
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 97
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 99
ANDL
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 99
ANDW
ANDW (And Word Data of AH and AL to AL) .. 101
ANDW (And Word Data of Destination and Source to
Destination)........................................ 102
Application Procedure
Flowchart of Extended Intelligent I/O Service
Application Procedure ........................... 49
Arithmetic Shift Byte Data
ASR (Arithmetic Shift Byte Data of Accumulator to
Right) ................................................ 104
Arithmetic Shift Long Word Data
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 106
Arithmetic Shift Word Data
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)..................................... 108, 110
ASR
ASR (Arithmetic Shift Byte Data of Accumulator to
Right) ................................................ 104
ASRL
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 106
ASRW
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)..................................... 108, 110
B
Bank Addressing
Bank Addressing Mode .........................................8
Bank Registers
Bank Registers ...................................................26
Bank Select Prefix
Bank Select Prefix ..............................................32
Banks
Memory Space Divided into Banks and Values in
Each Register Bank................................10
BAP
Buffer Address Pointer (BAP) .............................54
Basic Page Map
Basic Page Map................................................343
BBcc
BBcc (Branch if Bit Condition satisfied) .............112
Bcc
Bcc (Branch relative if Condition satisfied) .........114
Bit Address
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................201
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................199
Bit Configuration
Interrupt Control Register (ICR) Bit Configuration 50
Bit Data
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................201
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................199
Bit Operation Instruction
Bit Operation Instruction Map ...........................345
Branch
BBcc (Branch if Bit Condition satisfied) .............112
Bcc (Branch relative if Condition satisfied) .........114
CBNE (Compare Byte Data and Branch if not equal) .
122
CWBNE (Compare Word Data and Branch if not
Equal).................................................131
DBNZ (Decrement Byte Data and Branch if not Zero)
133
DWBNZ (Decrement Word Data and Branch if not
Zero) ..................................................147
SBBS (Set Bit and Branch if Bit Set) ..................276
Branch Instruction
Branch Instruction ............................................334
Buffer Address Pointer
Buffer Address Pointer (BAP) .............................54
Byte
MUL (Multiply Byte Data of Accumulator) ........224
Byte Data
AND (And Byte Data of Destination and Source to
Destination) ..........................................95
377
INDEX
AND (And Byte Data of Immediate Data and
Condition Code Register) ....................... 97
CBNE (Compare Byte Data and Branch if not equal)
.......................................................... 122
CMP (Compare Byte Data of Destination and Source)
.......................................................... 125
DBNZ (Decrement Byte Data and Branch if not Zero)
.......................................................... 133
DEC (Decrement Byte Data) ............................. 135
DIV (Divide Word Data by Byte Data)............... 139
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 149
INC (Increment Byte Data (Address Specification))
.......................................................... 155
LSL (Logical Shift Byte Data of Accumulator to Left)
.......................................................... 174
LSR (Logical Shift Byte Data of Accumulator to
Right)................................................. 181
MOV (Move Byte Data from Accumulator to
Destination) ........................................ 191
MOV (Move Byte Data from AH to Memory) .... 197
MOV (Move Byte Data from Source to Accumulator)
.......................................................... 189
MOV (Move Byte Data from Source to Destination)
.......................................................... 195
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 222
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 225
MULU (Multiply Unsigned Byte Data of
Accumulator)...................................... 230
NEG (Negate Byte Data of Destination) ............. 235
NOT (Not Byte Data of Destination) .................. 240
OR (Or Byte Data of Destination and Source to
Destination) ........................................ 245
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 247
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ............................................... 272
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 274
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 283
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................ 285
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
.......................................................... 286
SWAP (Swap Byte Data of Accumulator)........... 296
XCH (Exchange Byte Data of Source to Destination)
.......................................................... 301
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 305
ZEXT (Zero Extend from Byte Data to Word Data)
.......................................................... 312
378
C
CALL
CALL (Call Subroutine) ................................... 116
CALLP
CALLP (Call physical Address) ........................ 118
CALLV
CALLV (Call Vectored Subroutine) .................. 120
Carry
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 84
ADDC (Add Byte Data of AL and AH with Carry to
AL) ..................................................... 83
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 86
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 88
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 272
RORC (Rotate Byte Data of Accumulator with Carry
to Right)............................................. 274
SUBC (Subtract Byte Data of AL from AH with Carry
to AL)................................................ 285
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
......................................................... 286
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 288
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 290
CBNE
CBNE (Compare Byte Data and Branch if not equal)
......................................................... 122
CCR
Condition Code Register (CCR) .......................... 23
Channel Selection Bits
Extended Intelligent I/O Service Channel Selection
Bits (bit7 to bit4: ICS0 to ICS3) ............. 51
Character String Operation Instruction
Character String Operation Instruction Map ....... 347
Clear Bit
CLRB (Clear Bit)............................................. 124
CLRB
CLRB (Clear Bit)............................................. 124
CMP
CMP (Compare Byte Data of Destination and Source)
......................................................... 125
CMPL
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 127
CMPW
CMPW (Compare Word Data of Destination and
Source) .............................................. 129
INDEX
CMR
Common Register Bank Prefix (CMR)................. 34
Common Register Bank Prefix
Common Register Bank Prefix (CMR)................. 34
Compare
CBNE (Compare Byte Data and Branch if not equal)
.......................................................... 122
CMP (Compare Byte Data of Destination and Source)
.......................................................... 125
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 127
CMPW (Compare Word Data of Destination and
Source) .............................................. 129
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 131
Condition Code Register
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 97
Condition Code Register (CCR) .......................... 23
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 247
Context
JCTX (Jump Context)....................................... 167
CPU
CPU Memory Space............................................. 6
Features of the F2MC-16LX CPU Core.................. 2
Overview of the F2MC-16LX CPU Core................ 2
Create
UNLINK (Unlink and Create New Stack Frame) 298
LINK (Link and create new stack frame)............ 172
CWBNE
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 131
D
Data Counter
Data Counter (DCT)........................................... 55
Data Operation Instruction
Numeric Data Operation Instructions ................. 327
DBNZ
DBNZ (Decrement Byte Data and Branch if not Zero)
.......................................................... 133
DCT
Data Counter (DCT)........................................... 55
DEC
DEC (Decrement Byte Data) ............................. 135
Decimal Data
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 88
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 290
DECL
DECL (Decrement Long Word Data)................. 136
Decrement
DBNZ (Decrement Byte Data and Branch if not Zero)
..........................................................133
DEC (Decrement Byte Data) .............................135
DECL (Decrement Long Word Data) .................136
DECW (Decrement Word Data).........................137
DWBNZ (Decrement Word Data and Branch if not
Zero) ..................................................147
DECW
DECW (Decrement Word Data).........................137
Dedicated Register
Dedicated Register Types ....................................14
Descriptor
Extended Intelligent I/O Service Descriptor (ISD) .53
Destination
ADD (Add Byte Data of Destination and Source to
Destination) ..........................................81
ADDL (Add Long Word Data of Destination and
Source to Destination)............................89
ADDW (Add Word Data of Destination and Source to
Destination) ..........................................93
AND (And Byte Data of Destination and Source to
Destination) ..........................................95
ANDL (And Long Word Data of Destination and
Source to Destination)............................99
ANDW (And Word Data of Destination and Source to
Destination) ........................................102
CMP (Compare Byte Data of Destination and Source)
..........................................................125
CMPL (Compare Long Word Data of Destination and
Source) ...............................................127
CMPW (Compare Word Data of Destination and
Source) ...............................................129
JMP (Jump Destination Address) .......................169
JMPP (Jump Destination Physical Address) ........171
MOV (Move Byte Data from Accumulator to
Destination) ........................................191
MOV (Move Byte Data from Source to Destination)
..........................................................195
MOV (Move Byte Immediate Data to Destination)
..........................................................193
MOVEA (Move Effective Address to Destination)
..........................................................203
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................206
MOVW (Move Immediate Word Data to Destination)
..........................................................216
MOVW (Move Word Data from Accumulator to
Destination) ........................................214
MOVW (Move Word Data from Source to
Destination) ........................................218
NEG (Negate Byte Data of Destination)..............235
NEGW (Negate Word Data of Destination).........237
NOT (Not Byte Data of Destination) ..................240
NOTW (Not Word Data of Destination)..............242
379
INDEX
OR (Or Byte Data of Destination and Source to
Destination) ........................................ 245
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 249
ORW (Or Word Data of Destination and Source to
Destination) ........................................ 252
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 283
SUBL (Subtract Long Word Data of Source from
Destination to Destination) ................... 291
SUBW (Subtract Word Data of Source from
Destination to Destination) ................... 293
XCH (Exchange Byte Data of Source to Destination)
.......................................................... 301
XCHW (Exchange Word Data of Source to
Destination) ........................................ 303
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 305
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 307
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 310
Detailed Execution Instruction
Reading Detailed Execution Instructions .............. 80
Symbols (abbreviations) Used in Detailed Execution
Instructions ........................................... 72
Device
Sample Configuration of an F2MC-16LX Device .... 3
Direct Addressing
Direct Addressing............................................... 63
Direct Page Register
Direct Page Register (DPR)................................. 25
DIV
DIV (Divide Word Data by Byte Data)............... 139
Divide
DIV (Divide Word Data by Byte Data)............... 139
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 143
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 145
DIVW (Divide Long Word Data by Word Data) . 141
DIVU
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 143
DIVUW
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 145
DIVW
DIVW (Divide Long Word Data by Word Data) . 141
DPR
Direct Page Register (DPR)................................. 25
DWBNZ
DWBNZ (Decrement Word Data and Branch if not
Zero).................................................. 147
380
E
ea-type Instruction
ea-type Instruction Map .................................... 351
Effective Address
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 84
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 86
Effective Address Field ........................ 62, 74, 321
MOVEA (Move Effective Address to Destination)
......................................................... 203
MUL (Multiply Byte Data of Accumulator and
Effective Address) .............................. 225
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 231
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)..... 234
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 228
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
......................................................... 286
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 288
Exception
Exception Occurrence because of the Execution of an
Undefined Instruction............................ 56
Exchange
XCH (Exchange Byte Data of Source to Destination)
......................................................... 301
XCHW (Exchange Word Data of Source to
Destination)........................................ 303
Exclusive Or
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 305
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 307
XORW (Exclusive Or Word Data of AH and AL to
AL) ................................................... 309
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 310
Execution Cycle
Calculating Execution Cycles.............................. 76
Calculating the Number of Execution Cycles...... 322
Execution Cycles ............................................... 75
Number of Execution Cycles............................. 318
EXT
EXT (Sign Extend from Byte Data to Word Data)
......................................................... 149
Extended Intelligent I/O Service
Extended Intelligent I/O Service Channel Selection
Bits (bit7 to bit4: ICS0 to ICS3) ............. 51
INDEX
Extended Intelligent I/O Service Enable Bit (bit3: ISE)
............................................................ 52
Extended Intelligent I/O Service End Status (bit5,bit4:
S0,S1) .................................................. 52
Flowchart of Extended Intelligent I/O Service
Application Procedure ........................... 49
Flowchart of Extended Intelligent I/O Service
Operation ............................................. 48
Overview of Extended Intelligent I/O Service ....... 46
Structure of Extended Intelligent I/O Service ........ 46
Extended Intelligent I/O Service Descriptor
Extended Intelligent I/O Service Descriptor (ISD). 53
Extended Intelligent I/O Service Status Register
Extended Intelligent I/O Service Status Register
(ISCS).................................................. 54
EXTW
EXTW (Sign Extend from Word Data to Long Word
Data).................................................. 150
F
F2MC-16LX
Features of the F2MC-16LX CPU Core.................. 2
Overview of the F2MC-16LX CPU Core................ 2
Sample Configuration of an F2MC-16LX Device.... 3
Fill
FILS (Fill String Byte) ..................................... 151
FILSW (Fill String Word)................................. 153
FILS
FILS (Fill String Byte) ..................................... 151
FILSW
FILSW (Fill String Word)................................. 153
Flag Change Inhibit Prefix Code
Flag Change Inhibit Prefix Code (NCC) ............... 35
G
General-purpose Registers
Calling General-purpose Registers in RAM .......... 30
H
Hardware Interrupt
Hardware Interrupt Operation Flow ..................... 42
I
I/O Register Address Pointer
I/O Register Address Pointer (IOA) ..................... 55
ICR
Functions of Interrupt Control Registers (ICR0 to
ICR15)................................................. 50
Interrupt Control Register (ICR) Bit Configuration 50
ILM
Interrupt Level Mask (ILM) ................................ 21
Immediate Data
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ............91
AND (And Byte Data of Immediate Data and
Condition Code Register) .......................97
MOV (Move Byte Immediate Data to Destination)
..........................................................193
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
..........................................................247
Immediate Nibble Data
MOVN (Move Immediate Nibble Data to
Accumulator) ......................................207
Immediate Word Data
MOVW (Move Immediate Word Data to Destination)
..........................................................216
MOVW (Move Immediate Word Data to io) .......220
INC
INC (Increment Byte Data (Address Specification))
..........................................................155
INCL
INCL (Increment Long Word Data)....................156
Increment
INC (Increment Byte Data (Address Specification))
..........................................................155
INCL (Increment Long Word Data)....................156
INCW (Increment Word Data) ...........................157
INCW
INCW (Increment Word Data) ...........................157
Indirect Addressing
Indirect Addressing.............................................65
Inherent Register
PUSHW (Push Word Data of Inherent Register to
Stack Memory)....................................262
Instruction
2-byte Instruction Map ......................................349
Bit Operation Instruction Map ...........................345
Branch Instruction ............................................334
Character String Operation Instruction Map ........347
ea-type Instruction Map.....................................351
Exception Occurrence because of the Execution of an
Undefined Instruction.............................56
Explanation of the Items Used in the Instruction Lists
..........................................................317
Explanation of the Symbols Used in the Instruction
Lists ...................................................319
Instruction Overview ..........................................70
Logical Operation Instruction ............................331
MOV ea, Ri Instruction Map .............................367
MOV Ri, ea Instruction Map .............................363
MOVEA RWi, ea Instruction Map .....................361
MOVW ea, RWi Instruction Map.......................369
MOVW RWi, ea Instruction Map.......................365
Numeric Data Operation Instructions..................327
Other Instructions .............................................336
381
INDEX
Reading Detailed Execution Instructions .............. 80
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes ..................... 36
Shift Instruction ............................................... 333
Structure of the Instruction Map ........................ 340
Symbols (abbreviations) Used in Detailed Execution
Instructions ........................................... 72
Transfer Instruction .......................................... 325
XCH Ri, ea Instruction Map .............................. 371
XCHW RWi, ea Instruction Map ....................... 373
Instruction Map
Structure of the Instruction Map ........................ 340
INT
INT (Software Interrupt (Vector Specification)) .. 161
INT (Software Interrupt) ................................... 159
INT9
INT9 (Software Interrupt) ................................. 163
Interrupt
Hardware Interrupt Operation Flow...................... 42
INT (Software Interrupt (Vector Specification)) .. 161
INT (Software Interrupt) ................................... 159
INT9 (Software Interrupt) ................................. 163
Interrupt Handling .............................................. 40
Interrupt Handling Flowchart .............................. 43
Interrupt Vectors ................................................ 45
INTP (Software Interrupt) ................................. 165
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes ..................... 36
RETI (Return from Interrupt) ............................ 268
Interrupt Control Register
Functions of Interrupt Control Registers (ICR0 to
ICR15) ................................................. 50
Interrupt Control Register (ICR) Bit Configuration 50
Interrupt Handling
Interrupt Handling .............................................. 40
Interrupt Handling Flowchart .............................. 43
Interrupt Level Mask
Interrupt Level Mask (ILM) ................................ 21
Interrupt Level Setting Bits
Interrupt Level Setting Bits (bit2 to bit0: IL2 to IL0)
............................................................ 52
Interrupt Vectors
Interrupt Vectors ................................................ 45
INTP
INTP (Software Interrupt) ................................. 165
IOA
I/O Register Address Pointer (IOA) ..................... 55
ISCS
Extended Intelligent I/O Service Status Register
(ISCS) .................................................. 54
ISD
Extended Intelligent I/O Service Descriptor (ISD) . 53
382
J
JCTX
JCTX (Jump Context) ...................................... 167
JMP
JMP (Jump Destination Address)....................... 169
JMPP
JMPP (Jump Destination Physical Address) ....... 171
Jump
JCTX (Jump Context) ...................................... 167
JMP (Jump Destination Address)....................... 169
JMPP (Jump Destination Physical Address) ....... 171
L
Left
LSL (Logical Shift Byte Data of Accumulator to Left)
......................................................... 174
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 176
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 178, 179
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 272
Linear Addressing
Linear Addressing Mode ...................................... 7
Linear Addressing Mode
Linear Addressing Mode ...................................... 7
LINK
LINK (Link and create new stack frame)............ 172
Logical Operation Instruction
Logical Operation Instruction............................ 331
Logical Shift
LSL (Logical Shift Byte Data of Accumulator to Left)
......................................................... 174
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 176
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 178, 179
LSR (Logical Shift Byte Data of Accumulator to
Right) ................................................ 181
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 183
LSRW (Logical Shift Word Data of Accumulator to
Right) ........................................ 185, 187
Long Word
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 99
NRML (NORMALIZE Long Word) .................. 243
Long Word Data
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 89
DECL (Decrement Long Word Data)................. 136
DIVW (Divide Long Word Data by Word Data) . 141
EXTW (Sign Extend from Word Data to Long Word
Data) ................................................. 150
INDEX
INCL (Increment Long Word Data) ................... 156
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 176
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 183
MOVL (Move Long Word Data from Accumulator to
Destination)........................................ 206
MOVL (Move Long Word Data from Source to
Accumulator)...................................... 205
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 249
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 291
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 307
ZEXTW (Zero Extend from Word Data to Long Word
Data).................................................. 313
LSL
LSL (Logical Shift Byte Data of Accumulator to Left)
.......................................................... 174
LSLL
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 176
LSLW
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 178, 179
LSR
LSR (Logical Shift Byte Data of Accumulator to
Right) ................................................ 181
LSRL
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 183
LSRW
LSRW (Logical Shift Word Data of Accumulator to
Right) ........................................ 185, 187
M
Memory Space
CPU Memory Space............................................. 6
Memory Space Divided into Banks and Values in
Each Register Bank ............................... 10
Multi-byte Data Layout in a Memory Space ......... 11
Mode
Bank Addressing Mode ........................................ 8
Linear Addressing Mode....................................... 7
MOV
MOV (Move Byte Data from Accumulator to
Destination)........................................ 191
MOV (Move Byte Data from AH to Memory) .... 197
MOV (Move Byte Data from Source to Accumulator)
.......................................................... 189
MOV (Move Byte Data from Source to Destination)
.......................................................... 195
MOV (Move Byte Immediate Data to Destination)
.......................................................... 193
MOV ea, Ri Instruction
MOV ea, Ri Instruction Map .............................367
MOV Ri, ea Instruction
MOV Ri, ea Instruction Map .............................363
MOVB
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................201
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................199
Move
MOV (Move Byte Data from Accumulator to
Destination) ........................................191
MOV (Move Byte Data from AH to Memory).....197
MOV (Move Byte Data from Source to Accumulator)
..........................................................189
MOV (Move Byte Data from Source to Destination)
..........................................................195
MOV (Move Byte Immediate Data to Destination)
..........................................................193
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................201
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................199
MOVEA (Move Effective Address to Destination)
..........................................................203
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................206
MOVL (Move Long Word Data from Source to
Accumulator) ......................................205
MOVN (Move Immediate Nibble Data to
Accumulator) ......................................207
MOVS (Move String Byte)................................208
MOVSW (Move String Word) ...........................210
MOVW (Move Immediate Word Data to Destination)
..........................................................216
MOVW (Move Immediate Word Data to io) .......220
MOVW (Move Word Data from Accumulator to
Destination) ........................................214
MOVW (Move Word Data from AH to Memory) 221
MOVW (Move Word Data from Source to
Accumulator) ......................................212
MOVW (Move Word Data from Source to
Destination) ........................................218
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator)........................222
MOVEA
MOVEA (Move Effective Address to Destination)
..........................................................203
MOVEA RWi, ea Instruction
MOVEA RWi, ea Instruction Map .....................361
MOVL
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................206
MOVL (Move Long Word Data from Source to
Accumulator) ......................................205
383
INDEX
MOVN
MOVN
(Move Immediate Nibble Data to
Accumulator)...................................... 207
MOVS
MOVS (Move String Byte) ............................... 208
MOVSW
MOVSW (Move String Word)........................... 210
MOVW
MOVW (Move Immediate Word Data to Destination)
.......................................................... 216
MOVW (Move Immediate Word Data to io) ....... 220
MOVW (Move Word Data from Accumulator to
Destination) ........................................ 214
MOVW (Move Word Data from AH to Memory) 221
MOVW (Move Word Data from Source to
Accumulator)...................................... 212
MOVW (Move Word Data from Source to
Destination) ........................................ 218
MOVW ea, RWi Instruction
MOVW ea, RWi Instruction Map ...................... 369
MOVW RWi, ea Instruction
MOVW RWi, ea Instruction Map ...................... 365
MOVX
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 222
MUL
MUL (Multiply Byte Data of Accumulator) ........ 224
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 225
Multi-byte Data
Access to Multi-byte Data ................................... 12
Multi-byte Data Layout in a Memory Space.......... 11
Multiply
MUL (Multiply Byte Data of Accumulator) ........ 224
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 225
MULU (Multiply Unsigned Byte Data of
Accumulator)...................................... 230
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address)......................... 231
MULUW (Multiply Unsigned Word Data of
Accumulator)...................................... 233
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address) ..... 234
MULW (Multiply Word Data of Accumulator) ... 227
MULW (Multiply Word Data of Accumulator and
Effective Address)............................... 228
MULU
MULU (Multiply Unsigned Byte Data of
Accumulator)...................................... 230
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address)......................... 231
MULUW
MULUW (Multiply Unsigned Word Data of
Accumulator)...................................... 233
384
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)..... 234
MULW
MULW (Multiply Word Data of Accumulator)... 227
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 228
N
NCC
Flag Change Inhibit Prefix Code (NCC)............... 35
NEG
NEG (Negate Byte Data of Destination)............. 235
Negate
NEG (Negate Byte Data of Destination)............. 235
NEGW (Negate Word Data of Destination) ........ 237
NEGW
NEGW (Negate Word Data of Destination) ........ 237
No Operation
NOP (No Operation) ........................................ 239
NOP
NOP (No Operation) ........................................ 239
NORMALIZE
NRML (NORMALIZE Long Word) .................. 243
NOT
NOT (Not Byte Data of Destination).................. 240
NOTW
NOTW (Not Word Data of Destination)............. 242
NRML
NRML (NORMALIZE Long Word) .................. 243
O
OR
OR (Or Byte Data of Destination and Source to
Destination)........................................ 245
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
......................................................... 247
Or
OR (Or Byte Data of Destination and Source to
Destination)........................................ 245
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
......................................................... 247
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 249
ORW (Or Word Data of AH and AL to AL) ....... 251
ORW (Or Word Data of Destination and Source to
Destination)........................................ 252
ORL
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 249
ORW
ORW (Or Word Data of AH and AL to AL) ....... 251
INDEX
ORW (Or Word Data of Destination and Source to
Destination)........................................ 252
P
Page Map
Basic Page Map ............................................... 343
PC
Program Counter (PC) ........................................ 24
Physical Address
JMPP (Jump Destination Physical Address)........ 171
RETP (Return from Physical Address) ............... 270
physical Address
CALLP (Call physical Address) ........................ 118
Pop
POPW (Pop Registers from Stack Memory) ....... 260
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 254
POPW (Pop Word Data of AH from Stack Memory)
.......................................................... 256
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 258
POPW
POPW (Pop Registers from Stack Memory) ....... 260
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 254
POPW (Pop Word Data of AH from Stack Memory)
.......................................................... 256
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 258
Prefix
Bank Select Prefix.............................................. 32
Common Register Bank Prefix (CMR)................. 34
Flag Change Inhibit Prefix Code (NCC) ............... 35
If Two or More Prefix Codes Appear in Succession
............................................................ 37
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes ..................... 36
Processor Status
Processor Status (PS).......................................... 20
Program Counter
Program Counter (PC) ........................................ 24
Program Status
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 258
PS
Processor Status (PS).......................................... 20
Push
PUSHW (Push Registers to Stack Memory) ....... 264
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 262
PUSHW
PUSHW (Push Registers to Stack Memory) ....... 264
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 262
R
RAM
Calling General-purpose Registers in RAM...........30
Register Banks in RAM ......................................28
Register
AND (And Byte Data of Immediate Data and
Condition Code Register) .......................97
Condition Code Register (CCR) ...........................23
Direct Page Register (DPR) .................................25
Extended Intelligent I/O Service Status Register
(ISCS) ..................................................54
Functions of Interrupt Control Registers (ICR0 to
ICR15) .................................................50
Interrupt Control Register (ICR) Bit Configuration 50
Interrupt Level Mask (ILM).................................21
Register Bank
Memory Space Divided into Banks and Values in
Each Register Bank................................10
Register Bank Pointer
Register Bank Pointer (RP)..................................22
Register Banks
Register Banks in RAM ......................................28
RET
RET (Return from Subroutine)...........................266
RETI
RETI (Return from Interrupt).............................268
RETP
RETP (Return from Physical Address)................270
Return
RET (Return from Subroutine)...........................266
RETI (Return from Interrupt).............................268
RETP (Return from Physical Address)................270
Right
ASR (Arithmetic Shift Byte Data of Accumulator to
Right) .................................................104
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right)..........................106
ASRW (Arithmetic Shift Word Data of Accumulator
to Right) .....................................108, 110
LSR (Logical Shift Byte Data of Accumulator to
Right) .................................................181
LSRL (Logical Shift Long Word Data of Accumulator
to Right) .............................................183
LSRW (Logical Shift Word Data of Accumulator to
Right) .........................................185, 187
RORC (Rotate Byte Data of Accumulator with Carry
to Right) .............................................274
ROLC
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ...............................................272
RORC
RORC (Rotate Byte Data of Accumulator with Carry
to Right) .............................................274
385
INDEX
Rotate
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ............................................... 272
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 274
RP
Register Bank Pointer (RP) ................................. 22
S
Sample Configuration
Sample Configuration of an F2MC-16LX Device .... 3
SBBS
SBBS (Set Bit and Branch if Bit Set).................. 276
Scan
SCEQ (Scan String Byte Until Equal) ................ 278
SCWEQ (Scan String Word until Equal) ............ 280
SCEQ
SCEQ (Scan String Byte Until Equal) ................ 278
SCWEQ
SCWEQ (Scan String Word until Equal) ............ 280
Set
SBBS (Set Bit and Branch if Bit Set).................. 276
SETB (Set Bit)................................................. 282
SETB
SETB (Set Bit)................................................. 282
Shift Instruction
Shift Instruction ............................................... 333
Sign
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 149
EXTW (Sign Extend from Word Data to Long Word
Data).................................................. 150
Sign Extension
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 222
Software Interrupt
INT (Software Interrupt (Vector Specification)) .. 161
INT (Software Interrupt) ................................... 159
INT9 (Software Interrupt) ................................. 163
INTP (Software Interrupt) ................................. 165
Source
ADD (Add Byte Data of Destination and Source to
Destination) .......................................... 81
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 89
ADDW (Add Word Data of Destination and Source to
Destination) .......................................... 93
AND (And Byte Data of Destination and Source to
Destination) .......................................... 95
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 99
ANDW (And Word Data of Destination and Source to
Destination) ........................................ 102
386
CMP (Compare Byte Data of Destination and Source)
......................................................... 125
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 127
CMPW (Compare Word Data of Destination and
Source) .............................................. 129
MOV (Move Byte Data from Source to Accumulator)
......................................................... 189
MOV (Move Byte Data from Source to Destination)
......................................................... 195
MOVL (Move Long Word Data from Source to
Accumulator) ..................................... 205
MOVW (Move Word Data from Source to
Accumulator) ..................................... 212
MOVW (Move Word Data from Source to
Destination)........................................ 218
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 222
OR (Or Byte Data of Destination and Source to
Destination)........................................ 245
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 249
ORW (Or Word Data of Destination and Source to
Destination)........................................ 252
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 283
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 291
SUBW (Subtract Word Data of Source from
Destination to Destination)................... 293
XCH (Exchange Byte Data of Source to Destination)
......................................................... 301
XCHW (Exchange Word Data of Source to
Destination)........................................ 303
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 305
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 307
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 310
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 18
Stack
POPW (Pop Registers from Stack Memory) ....... 260
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 254
POPW (Pop Word Data of AH from Stack Memory)
......................................................... 256
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 258
PUSHW (Push Registers to Stack Memory) ....... 264
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 262
Stack Frame
UNLINK (Unlink and Create New Stack Frame) 298
INDEX
LINK (Link and create new stack frame)............ 172
Stack Pointer
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ........... 91
String Byte
FILS (Fill String Byte) ..................................... 151
MOVS (Move String Byte) ............................... 208
SCEQ (Scan String Byte Until Equal) ................ 278
String Word
FILSW (Fill String Word)................................. 153
MOVSW (Move String Word) .......................... 210
SCWEQ (Scan String Word until Equal) ............ 280
SUB
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 283
SUBC
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................ 285
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
.......................................................... 286
SUBCW
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator)...................................... 288
SUBDC
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 290
SUBL
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 291
Subroutine
RET (Return from Subroutine) .......................... 266
Subtract
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 283
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................ 285
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
.......................................................... 286
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator)...................................... 288
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 290
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 291
SUBW (Subtract Word Data of AL from AH to AL)
.......................................................... 295
SUBW (Subtract Word Data of Source from
Destination to Destination)................... 293
SUBW
SUBW (Subtract Word Data of AL from AH to AL)
..........................................................295
SUBW (Subtract Word Data of Source from
Destination to Destination) ...................293
SWAP
SWAP (Swap Byte Data of Accumulator) ...........296
SWAPW
SWAPW (Swap Word Data of Accumulator) ......297
Symbol
Explanation of the Symbols Used in the Instruction
Lists ...................................................319
Symbols (abbreviations) Used in Detailed Execution
Instructions ...........................................72
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................18
T
Transfer Instruction
Transfer Instruction ..........................................325
U
Undefined Instruction
Exception Occurrence because of the Execution of an
Undefined Instruction.............................56
UNLINK
UNLINK (Unlink and Create New Stack Frame) .298
Unsigned Byte Data
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) .........................231
unsigned Byte Data
DIVU (Divide unsigned Word Data by unsigned Byte
Data) ..................................................143
unsigned Long Word Data
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ...........................145
Unsigned Word Data
MULUW (Multiply Unsigned Word Data of
Accumulator) ......................................233
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address) .....234
unsigned Word Data
DIVU (Divide unsigned Word Data by unsigned Byte
Data) ..................................................143
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ...........................145
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................18
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................18
387
INDEX
V
ORW (Or Word Data of AH and AL to AL) ....... 251
ORW (Or Word Data of Destination and Source to
Destination)........................................ 252
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 254
POPW (Pop Word Data of AH from Stack Memory)
......................................................... 256
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 258
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 262
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 288
SUBW (Subtract Word Data of AL from AH to AL)
......................................................... 295
SUBW (Subtract Word Data of Source from
Destination to Destination)................... 293
SWAPW (Swap Word Data of Accumulator) ..... 297
XCHW (Exchange Word Data of Source to
Destination)........................................ 303
XORW (Exclusive Or Word Data of AH and AL to
AL) ................................................... 309
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 310
ZEXT (Zero Extend from Byte Data to Word Data)
......................................................... 312
ZEXTW (Zero Extend from Word Data to Long Word
Data) ................................................. 313
Vector Specification
INT (Software Interrupt (Vector Specification)) .. 161
Vectored Subroutine
CALLV (Call Vectored Subroutine)................... 120
W
Wait
WBTc (Wait until Bit Condition Satisfied) ......... 299
WBTc
WBTc (Wait until Bit Condition Satisfied) ......... 299
Word Data
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer)............ 91
ADDW (Add Word Data of AL and AH to AL) .... 92
ADDW (Add Word Data of Destination and Source to
Destination) .......................................... 93
ANDW (And Word Data of AH and AL to AL) .. 101
ANDW (And Word Data of Destination and Source to
Destination) ........................................ 102
CMPL (Compare Long Word Data of Destination and
Source)............................................... 127
CMPW (Compare Word Data of Destination and
Source)............................................... 129
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 131
DECW (Decrement Word Data) ........................ 137
DIV (Divide Word Data by Byte Data)............... 139
DIVW (Divide Long Word Data by Word Data) . 141
DWBNZ (Decrement Word Data and Branch if not
Zero).................................................. 147
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 149
EXTW (Sign Extend from Word Data to Long Word
Data).................................................. 150
INCW (Increment Word Data)........................... 157
LSLW (Logical Shift Word Data of Accumulator to
Left)........................................... 178, 179
LSRW (Logical Shift Word Data of Accumulator to
Right)......................................... 185, 187
MOVW (Move Word Data from Accumulator to
Destination) ........................................ 214
MOVW (Move Word Data from AH to Memory) 221
MOVW (Move Word Data from Source to
Accumulator)...................................... 212
MOVW (Move Word Data from Source to
Destination) ........................................ 218
MULW (Multiply Word Data of Accumulator) ... 227
MULW (Multiply Word Data of Accumulator and
Effective Address)............................... 228
NEGW (Negate Word Data of Destination) ........ 237
NOTW (Not Word Data of Destination) ............. 242
388
X
XCH
XCH (Exchange Byte Data of Source to Destination)
......................................................... 301
XCH Ri, ea Instruction
XCH Ri, ea Instruction Map.............................. 371
XCHW
XCHW (Exchange Word Data of Source to
Destination)........................................ 303
XCHW RWi, ea Instruction
XCHW RWi, ea Instruction Map....................... 373
XOR
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 305
XORL
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 307
XORW
XORW (Exclusive Or Word Data of AH and AL to
AL) ................................................... 309
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 310
INDEX
Z
Zero Extend
ZEXT (Zero Extend from Byte Data to Word Data)
.......................................................... 312
ZEXTW (Zero Extend from Word Data to Long Word
Data).................................................. 313
ZEXT
ZEXT (Zero Extend from Byte Data to Word Data)
..........................................................312
ZEXTW
ZEXTW (Zero Extend from Word Data to Long Word
Data) ..................................................313
389
INDEX
390
CM44-00201-4E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
January 2010 the fourth edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Sales Promotion Dept.
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