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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-00104-3E
FR80 Family
32-BIT MICROCONTROLLER
PROGRAMMING MANUAL
FR80 Family
32-BIT MICROCONTROLLER
PROGRAMMING MANUAL
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
PREFACE
■ Objectives and targeted reader
FR80 Family is a 32 bit single chip microcontroller with CPU of new RISC Architecture as the core. FR80
Family has specifications that are optimum for embedded use requiring high performance CPU processing
power.
This manual explains the programming model and execution instructions for engineers developing a
product using this FR80 Family Microcontroller, especially the programmers who produce programs using
assembly language of the assembler for FR/FR80 Family.
For the rules of assembly grammar language and the method of use of Assembler Programs, kindly refer to
"FR Family Assembler Manual".
*: FR, the abbreviation of Fujitsu RISC controller, is a line of products of Fujitsu Semiconductor Limited.
Other company names and brand names are the trademarks or registered trademarks of their respective
owners.
■ Organization of this Manual
This manual consists of the following 7 chapters and 1 supplement.
CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
This chapter describes the features of FR80 Family CPU and its differences from hitherto FR Family.
CHAPTER 2 MEMORY ARCHITECTURE
This chapter describes Memory Architecture of the CPU of FR80 Family. Memory Architecture is the
method of allocation of memory space and access to this memory space.
CHAPTER 3 PROGRAMMING MODEL
This chapter describes registers in the CPU existing as programming model of FR80 Family CPU.
CHAPTER 4 RESET AND "EIT" PROCESSING
This chapter describes resetting of FR80 Family CPU and EIT processing. EIT processing is the generic
term for exceptions, interruption and trap.
CHAPTER 5 PIPELINE OPERATION
This chapter describes pipeline operation and delay divergence, the salient feature of FR80 Family CPU.
CHAPTER 6 INSTRUCTION OVERVIEW
This chapter describes outline of commands of FR80 Family CPU.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
This chapter describes Execution Instructions of FR80 Family CPU in Reference Format in the
alphabetical order.
APPENDIX
It contains instruction list and instruction map of FR80 Family CPU.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such
use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of
the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of information
contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2008-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
OVERVIEW OF FR80 FAMILY CPU ............................................................ 1
Features of FR80 Family CPU ............................................................................................................ 2
Changes from the earlier FR Family ................................................................................................... 4
CHAPTER 2
MEMORY ARCHITECTURE ........................................................................ 7
2.1
Address Space ................................................................................................................................... 8
2.1.1
Direct Address Area ...................................................................................................................... 9
2.1.2
Vector Table Area ........................................................................................................................ 10
2.1.3
20-bit Addressing Area & 32-bit Addressing Area ....................................................................... 12
2.2
Data Structure ................................................................................................................................... 13
2.2.1
Byte Data ..................................................................................................................................... 13
2.2.2
Half Word Data ............................................................................................................................ 13
2.2.3
Word Data ................................................................................................................................... 14
2.2.4
Byte Order ................................................................................................................................... 14
2.3
Word Alignment ................................................................................................................................ 15
2.3.1
Program Access .......................................................................................................................... 15
2.3.2
Data Access ................................................................................................................................ 15
CHAPTER 3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.4
3.4.1
3.4.2
3.4.3
PROGRAMMING MODEL .......................................................................... 17
FR80 Family CPU Register Configuration ........................................................................................
General-purpose Registers ...............................................................................................................
Configuration of General-purpose Registers ...............................................................................
Special Usage of General-purpose Registers .............................................................................
Relation between Stack Pointer and “R15” .................................................................................
Dedicated Registers .........................................................................................................................
Configuration of Dedicated Registers ..........................................................................................
Program Counter (PC) .................................................................................................................
Return Pointer (RP) .....................................................................................................................
System Stack Pointer (SSP) ........................................................................................................
User Stack Pointer (USP) ............................................................................................................
Table Base Register (TBR) .........................................................................................................
Multiplication/Division Register (MDH, MDL) ...............................................................................
Program Status (PS) .........................................................................................................................
Interrupt Level Mask Register (ILM) ............................................................................................
Condition Code Register (CCR) ..................................................................................................
System Condition Code Register (SCR) .....................................................................................
CHAPTER 4
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RESET AND "EIT" PROCESSING ............................................................ 35
4.1
Reset ................................................................................................................................................
4.2
Basic Operations in "EIT" Processing ...............................................................................................
4.2.1
Types of "EIT" Processing and Prior Preparation ........................................................................
4.2.2
"EIT" Processing Sequence .........................................................................................................
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4.2.3
4.3
4.3.1
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.2
4.8.3
Recovery from "EIT" Processing .................................................................................................
Exception Processing .......................................................................................................................
Undefined-instruction exception ..................................................................................................
Interrupts ...........................................................................................................................................
User interrupts .............................................................................................................................
Non-maskable Interrupts (NMI) ...................................................................................................
Traps .................................................................................................................................................
"INT" Instructions .........................................................................................................................
"INTE" Instruction ........................................................................................................................
Step Trace Traps .........................................................................................................................
Multiple "EIT" Processing and Priority Levels ...................................................................................
Multiple "EIT" Processing ............................................................................................................
Priority Levels of "EIT" Requests .................................................................................................
Timing When Register Settings Are Reflected .................................................................................
Timing when the interrupt enable flag (I) is requested ................................................................
Timing of Reflection of Interrupt Level Mask Register (ILM) .......................................................
Usage Sequence of User Interrupts .................................................................................................
Preparation while using user interrupts .......................................................................................
Processing during an Interrupt Processing Routine ....................................................................
Points of Caution while using User Interrupts ..............................................................................
CHAPTER 5
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.5
5.5.1
5.5.2
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.3.1
6.4
6.5
PIPELINE OPERATION ............................................................................. 55
Instruction execution based on Pipeline ...........................................................................................
Pipeline Operation and Interrupt Processing ....................................................................................
Mismatch in Acceptance and Cancellation of Interrupt ...............................................................
How to prevent mismatched pipeline conditions? .......................................................................
Register hazards ...............................................................................................................................
Occurrence of register hazard .....................................................................................................
Register Bypassing ......................................................................................................................
Interlocking ..................................................................................................................................
Interlocking produced by after Changing the Stack flag (S) ........................................................
Non-block loading .............................................................................................................................
Delayed branching processing .........................................................................................................
Example of branching with non-delayed branching instructions ..................................................
Example of processing of delayed branching instruction ............................................................
CHAPTER 6
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INSTRUCTION OVERVIEW ....................................................................... 65
Instruction System ............................................................................................................................
Instructions Formats .........................................................................................................................
Instructions Notation Formats ......................................................................................................
Addressing Formats ....................................................................................................................
Instruction Formats ......................................................................................................................
Register designated Field ............................................................................................................
Data Format ......................................................................................................................................
Data Format Used by Integer Type Instructions (Common with All FR Family) ..........................
Read-Modify-Write type Instructions .................................................................................................
Branching Instructions and Delay Slot ..............................................................................................
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6.5.1
Delayed Branching Instructions ...................................................................................................
6.5.2
Specific example of Delayed Branching Instructions ...................................................................
6.5.3
Non-Delayed Branching Instructions ...........................................................................................
6.6
Step Division Instructions .................................................................................................................
6.6.1
Signed Division ............................................................................................................................
6.6.2
Unsigned Division ........................................................................................................................
CHAPTER 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
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DETAILED EXECUTION INSTRUCTIONS ................................................ 83
ADD (Add 4bit Immediate Data to Destination Register) .................................................................. 85
ADD (Add Word Data of Source Register to Destination Register) .................................................. 87
ADD2 (Add 4bit Immediate Data to Destination Register) ................................................................ 89
ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ......................... 91
ADDN (Add Immediate Data to Destination Register) ...................................................................... 93
ADDN (Add Word Data of Source Register to Destination Register) ............................................... 95
ADDN2 (Add Immediate Data to Destination Register) .................................................................... 97
ADDSP (Add Stack Pointer and Immediate Data) ............................................................................ 99
AND (And Word Data of Source Register to Data in Memory) ....................................................... 101
AND (And Word Data of Source Register to Destination Register) ................................................ 103
ANDB (And Byte Data of Source Register to Data in Memory) ...................................................... 105
ANDCCR (And Condition Code Register and Immediate Data) ..................................................... 107
ANDH (And Halfword Data of Source Register to Data in Memory) ............................................... 109
ASR (Arithmetic shift to the Right Direction) ................................................................................... 111
ASR (Arithmetic shift to the Right Direction) ................................................................................... 113
ASR2 (Arithmetic shift to the Right Direction) ................................................................................. 115
BANDH (And 4bit Immediate Data to Higher 4bit of Byte Data in Memory) ................................... 117
BANDL (And 4bit Immediate Data to Lower 4bit of Byte Data in Memory) ..................................... 119
Bcc (Branch relative if Condition satisfied) ..................................................................................... 121
Bcc:D (Branch relative if Condition satisfied) .................................................................................. 123
BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte Data in Memory) .................................... 125
BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data in Memory) ..................................... 127
BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data in Memory) ........................................ 129
BORL (Or 4bit Immediate Data to Lower 4bit of Byte Data in Memory) ......................................... 131
BTSTH (Test Higher 4bit of Byte Data in Memory) ......................................................................... 133
BTSTL (Test Lower 4bit of Byte Data in Memory) .......................................................................... 135
CALL (Call Subroutine) ................................................................................................................... 137
CALL (Call Subroutine) ................................................................................................................... 139
CALL:D (Call Subroutine) ............................................................................................................... 141
CALL:D (Call Subroutine) ............................................................................................................... 143
CMP (Compare Immediate Data and Destination Register) ........................................................... 145
CMP (Compare Word Data in Source Register and Destination Register) .................................... 147
CMP2 (Compare Immediate Data and Destination Register) ......................................................... 149
DIV0S (Initial Setting Up for Signed Division) ................................................................................. 151
DIV0U (Initial Setting Up for Unsigned Division) ............................................................................. 153
DIV1 (Main Process of Division) ..................................................................................................... 155
DIV2 (Correction When Remain is 0) ............................................................................................. 157
DIV3 (Correction When Remain is 0) ............................................................................................. 159
DIV4S (Correction Answer for Signed Division) ............................................................................. 161
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7.40
7.41
7.42
7.43
7.44
7.45
7.46
7.47
7.48
7.49
7.50
7.51
7.52
7.53
7.54
7.55
7.56
7.57
7.58
7.59
7.60
7.61
7.62
7.63
7.64
7.65
7.66
7.67
7.68
7.69
7.70
7.71
7.72
7.73
7.74
7.75
7.76
7.77
7.78
7.79
7.80
7.81
7.82
7.83
7.84
7.85
DMOV (Move Word Data from Direct Address to Register) ...........................................................
DMOV (Move Word Data from Register to Direct Address) ...........................................................
DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) .......
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) .......
DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address) .......
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) .......
DMOVB (Move Byte Data from Direct Address to Register) ..........................................................
DMOVB (Move Byte Data from Register to Direct Address) ..........................................................
DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) ......
DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) ......
DMOVH (Move Halfword Data from Direct Address to Register) ...................................................
DMOVH (Move Halfword Data from Register to Direct Address) ...................................................
DMOVH (Move Halfword Data from Direct Address to Post Increment Register Indirect Address)
.........................................................................................................................................................
DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address)
.........................................................................................................................................................
ENTER (Enter Function) .................................................................................................................
EOR (Exclusive Or Word Data of Source Register to Data in Memory) .........................................
EOR (Exclusive Or Word Data of Source Register to Destination Register) ..................................
EORB (Exclusive Or Byte Data of Source Register to Data in Memory) ........................................
EORH (Exclusive Or Halfword Data of Source Register to Data in Memory) .................................
EXTSB (Sign Extend from Byte Data to Word Data) ......................................................................
EXTSH (Sign Extend from Byte Data to Word Data) ......................................................................
EXTUB (Unsign Extend from Byte Data to Word Data) ..................................................................
EXTUH (Unsign Extend from Byte Data to Word Data) ..................................................................
INT (Software Interrupt) ..................................................................................................................
INTE (Software Interrupt for Emulator) ...........................................................................................
JMP (Jump) ....................................................................................................................................
JMP:D (Jump) .................................................................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Register) .................................................................................
LD (Load Word Data in Memory to Program Status Register) .......................................................
LDI:20 (Load Immediate 20bit Data to Destination Register) .........................................................
LDI:32 (Load Immediate 32 bit Data to Destination Register) ........................................................
LDI:8 (Load Immediate 8bit Data to Destination Register) .............................................................
LDM0 (Load Multiple Registers) .....................................................................................................
LDM1 (Load Multiple Registers) .....................................................................................................
LDUB (Load Byte Data in Memory to Register) ..............................................................................
LDUB (Load Byte Data in Memory to Register) ..............................................................................
LDUB (Load Byte Data in Memory to Register) ..............................................................................
LDUH (Load Halfword Data in Memory to Register) .......................................................................
LDUH (Load Halfword Data in Memory to Register) .......................................................................
LDUH (Load Halfword Data in Memory to Register) .......................................................................
LEAVE (Leave Function) ................................................................................................................
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7.87
7.88
7.89
7.90
7.91
7.92
7.93
7.94
7.95
7.96
7.97
7.98
7.99
7.100
7.101
7.102
7.103
7.104
7.105
7.106
7.107
7.108
7.109
7.110
7.111
7.112
7.113
7.114
7.115
7.116
7.117
7.118
7.119
7.120
7.121
7.122
7.123
7.124
7.125
7.126
7.127
7.128
7.129
7.130
7.131
7.132
LSL (Logical Shift to the Left Direction) ..........................................................................................
LSL (Logical Shift to the Left Direction) ..........................................................................................
LSL2 (Logical Shift to the Left Direction) ........................................................................................
LSR (Logical Shift to the Right Direction) .......................................................................................
LSR (Logical Shift to the Right Direction) .......................................................................................
LSR2 (Logical Shift to the Right Direction) .....................................................................................
MOV (Move Word Data in Source Register to Destination Register) .............................................
MOV (Move Word Data in Source Register to Destination Register) .............................................
MOV (Move Word Data in Program Status Register to Destination Register) ................................
MOV (Move Word Data in Source Register to Destination Register) .............................................
MOV (Move Word Data in Source Register to Program Status Register) ......................................
MUL (Multiply Word Data) ..............................................................................................................
MULH (Multiply Halfword Data) ......................................................................................................
MULU (Multiply Unsigned Word Data) ............................................................................................
MULUH (Multiply Unsigned Halfword Data) ...................................................................................
NOP (No Operation) .......................................................................................................................
OR (Or Word Data of Source Register to Data in Memory) ............................................................
OR (Or Word Data of Source Register to Destination Register) .....................................................
ORB (Or Byte Data of Source Register to Data in Memory) ...........................................................
ORCCR (Or Condition Code Register and Immediate Data) ..........................................................
ORH (Or Halfword Data of Source Register to Data in Memory) ...................................................
RET (Return from Subroutine) ........................................................................................................
RET:D (Return from Subroutine) ....................................................................................................
RETI (Return from Interrupt) ...........................................................................................................
SRCH0 (Search First Zero bit position distance From MSB) ..........................................................
SRCH1 (Search First One bit position distance From MSB) ..........................................................
SRCHC (Search First bit value change position distance From MSB) ...........................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Register to Memory) .................................................................................
ST (Store Word Data in Program Status Register to Memory) .......................................................
STB (Store Byte Data in Register to Memory) ................................................................................
STB (Store Byte Data in Register to Memory) ................................................................................
STB (Store Byte Data in Register to Memory) ................................................................................
STH (Store Halfword Data in Register to Memory) .........................................................................
STH (Store Halfword Data in Register to Memory) .........................................................................
STH (Store Halfword Data in Register to Memory) .........................................................................
STILM (Set Immediate Data to Interrupt Level Mask Register) ......................................................
STM0 (Store Multiple Registers) .....................................................................................................
STM1 (Store Multiple Registers) .....................................................................................................
SUB (Subtract Word Data in Source Register from Destination Register) .....................................
SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) .............
SUBN (Subtract Word Data in Source Register from Destination Register) ...................................
XCHB (Exchange Byte Data) ..........................................................................................................
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APPENDIX ......................................................................................................................... 349
APPENDIX A Instruction Lists ....................................................................................................................
A.1 Meaning of Symbols .......................................................................................................................
A.1.1 Mnemonic and Operation Columns ................................................................................................
A.1.2 Operation Column ...........................................................................................................................
A.1.3 Format Column ...............................................................................................................................
A.1.4 OP Column .....................................................................................................................................
A.1.5 CYC Column ...................................................................................................................................
A.1.6 FLAG Column .................................................................................................................................
A.1.7 RMW Column .................................................................................................................................
A.1.8 Reference Column ..........................................................................................................................
A.2 Instruction Lists ..............................................................................................................................
A.3 List of Instructions that can be positioned in the Delay Slot ...........................................................
A.4 Instruction List where the number of execution cycles has been changed ....................................
APPENDIX B Instruction Maps ...................................................................................................................
B.1 Instruction Maps .............................................................................................................................
B.2 Instruction Maps of Instruction Format Type-E ..............................................................................
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INDEX................................................................................................................................... 373
viii
Major changes in this edition
Page
74, 75
Changes (For details, refer to main body.)
CHAPTER 6 INSTRUCTION
OVERVIEW
6.3 Data Format
Added the section "6.3 Data Format".
265
CHAPTER 7 DETAILED
EXECUTION INSTRUCTIONS
7.91 LSR2 (Logical Shift to
the Right Direction)
Corrected the summary.
left shift → right shift
352
APPENDIX
A.1 Meaning of Symbols
A.1.1 Mnemonic and Operation
Columns
Corrected the item "label9".
256 (100H) → -256 (100H)
353
Corrected the item "rel8".
128 (80H) → -128 (80H)
The vertical lines marked in the left side of the page show the changes.
ix
x
CHAPTER 1
OVERVIEW OF FR80 FAMILY
CPU
This chapter describes the features of FR80 Family CPU
and the changes from the hitherto FR Family.
1.1 Features of FR80 Family CPU
1.2 Changes from the earlier FR Family
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
1
CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
1.1
1.1
FR80 Family
Features of FR80 Family CPU
FR80 Family CPU is meant for 32 bit RISC controller having proprietary architecture of
Fujitsu. It has the most optimum architecture as CPU of microcontroller for embedded
control requiring high speed control.
■ General-purpose Register Architecture
It is load/store architecture based on 16 numbers of 32-bit General-purpose registers R0 to R15. The
architecture also has instructions that are suitable for embedded uses such as memory to memory transfer,
bit processing etc.
■ Linear Space for 32-bit (4G bytes) addressing
Address space is controlled for each byte unit. Linear specification of Address can be made based on 32-bit
address.
■ 16-bit fixed instruction length (excluding immediate data transfer instructions)
It is 16-bit fixed length instruction format excluding 32/20-bit immediate data transfer instruction. It
enables securing high object efficiency.
■ Pipeline Configuration
High speed one-instruction one-cycle processing of the basic instructions based on 5-stage pipeline
operation can be carried out. Pipeline has following 5-stage configuration.
• IF Stage: Load Instruction
• ID Stage: Interpret Instruction
• EX Stage: Execute Instruction
• MA Stage: Memory Access
• WB Stage: Write to register
In the FR80 Family, pipeline for memory loading has been added and non-blocking loading is carried out.
■ Non-blocking load
In FR80 Family, non-blocking loading is carried out making execution of LD (load) instructions efficient.
A maximum of 4 LD (Load) instructions can be issued in anticipation. In non-blocking, succeeding
instruction is executed without waiting for the completion of a load instruction, in case general-purpose
register storing the value of load instruction is not referred by the succeeding instruction.
■ Harvard Architecture
An instruction can be executed efficiently based on Harvard Architecture where instruction bus for
instruction access and data bus for data access are independent.
2
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
1.1
■ Multiplication Instruction
Multiplication/division computation can be executed at the instruction level based on an in-built multiplier.
32-bit multiplication, signed or unsigned, is executed in 5 cycles. 16-bit multiplication is executed in 3
cycles.
■ Step Division Instruction
32-bit ÷ 32-bit division, signed or unsigned, can be executed based on combination of step division
instructions.
■ Direct Addressing Instruction for peripheral access
Address of 256 words/ 256 half-words/ 256 bytes from the top of address space (low order address) can be
directly specified. It is convenient for address specification in the I/O Register of the peripheral resource.
■ High-speed interrupt processing complete within 6 cycles
Acceptance of interruption is processed at a high speed within 6 cycles. A 16-level priority order is given to
the request for interruption. Masking in line with the priority order can be carried out based on interruption
mask level of the CPU.
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CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
1.2
1.2
FR80 Family
Changes from the earlier FR Family
FR80 Family has partial addition and deletion of instructions and operational changes
from the earlier FR Family (FR30 Family, FR60 Family etc.).
■ Instructions that cannot be used in FR80 Family
Following instructions cannot be used in FR80 Family.
• Coprocessor Instructions (COPOP, COPLD, COPST, COPSV)
• Resource Instructions (LDRES, STRES)
Undefined Instruction Exceptions and not the Coprocessor Error Trap occur when execution of
Coprocessor Instruction is attempted. Undefined Instruction Exceptions occur when execution of Resource
Instruction is attempted.
■ Instructions added to FR80 Family
Following instructions have been added in FR80 Family. These instructions have replaced the bit search
module embedded as a peripheral function.
• SRCH1 (Bit Search Instruction Detection of First "1" bit from MSB to LSB)
• SRCH0 (Bit Search Instruction Detection of first "0" bit from MSB to LSB)
• SRCHC (Bit Search Instruction Detection of Change point from MSB to LSB)
see "Chapter 7 Detailed Execution Instructions" and "Appendix A.2 Instruction Lists" for operation of Bit
Search Instructions.
■ Alignment with word, half word at the time of data access
In FR80 family, when accessing data use the following address depending on the access size. (Alignment
cannot be carried out with hardware).
Word Access: Address should be multiple of 4 (2 LSB are 00)
Half word access: Address should be multiple of 2 (LSB is 0)
■ Instruction Execution Cycle
In FR80 Family, depending on non-blocking load and pre-fetch buffer definition of execution cycle of
some instructions is different from the earlier FR Family.
Definition of symbols b, c, d used in the execution cycles (CYC Column) has been changed. For details,
see "Appendix A.1 Meaning of Symbols" and "Appendix A.4 Instruction List where the number of
execution cycles has been changed".
4
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CM71-00104-3E
FR80 Family
CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
1.2
■ Operation of INTE Instructions during Step Execution
In FR80 Family, trap processing is initiated based on INTE instructions even during step execution based
on step trace trap.
In hitherto FR Family, trap processing is not initiated based on INTE instructions during step execution.
For trap processing based on step trace trap and INTE instructions, see “4.5 Traps”.
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CHAPTER 1 OVERVIEW OF FR80 FAMILY CPU
1.2
6
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FR80 Family
CM71-00104-3E
CHAPTER 2
MEMORY ARCHITECTURE
This chapter explains the memory architecture of FR80
Family CPU. Memory architecture refers to allocation of
memory spaces and methods used to access memory.
2.1 Address Space
2.2 Data Structure
2.3 Word Alignment
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CHAPTER 2 MEMORY ARCHITECTURE
2.1
2.1
FR80 Family
Address Space
The address space of FR80 Family CPU is 32 bits (4Gbyte).
CPU controls the address spaces in byte units. An address on the address space is accessed from the CPU
by specifying a 32-bit value. Address space is indicated in Figure 2.1-1.
Figure 2.1-1 Address space of FR80 Family CPU
Direct address area
General addressing
0000 0000
H
0000 0100
H
0000 0200
H
0000 0400
H
Byte data
Half-word data
Word data
000F FC00 H
0010 0000 H
000F FC00 H
Vector table
initial area
TBR
TBR initial value
Program or data area
FFFF FFFF H
Address space is also called memory space. It is a logical address space as seen from the CPU. Addresses
cannot be changed. Logical address as seen from the CPU, and the physical address actually allocated to
memory or I/O are identical.
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CM71-00104-3E
CHAPTER 2 MEMORY ARCHITECTURE
2.1
FR80 Family
2.1.1
Direct Address Area
In the lower address in the address space, there is a direct address area.
Direct address area directly specifies an address in the direct address specification
instruction. This area can be accessed only based on operand data in the instruction
without the use of general-purpose registers. The size of the address area that can be
specified by direct addressing varies according to the data type being accessed.
The correspondence between data type and area specified by direct address is as follows.
• byte data access: 0000 0000H to 0000 00FFH
• half-word data access: 0000 0000H to 0000 01FFH
• word data access: 0000 0000H to 0000 03FFH
The method of using the 8-bit address data contained in the operand of instructions that specify direct
addresses is as follows:
• byte data access: Lower 8 bits of the address are used as it is
• half word data access: Value is doubled and used as lower 9 bits of the address
• word data access: Value is quadrupled and used as lower 10 bits of the address
The relation between data types specified by direct address and memory address is shown in Figure 2.1-2.
Figure 2.1-2 Relation between data type specified by direct address and memory address
[Example 1] Byte data: DMOVB R13,@58H
Memory space
Object code:1A58H
No data shift
R13 12345678
58H
0000 0058 H
[Example 2] Half-word data: DMOVH R13,@58H
Right 1-bit shift
Left 1-bit shift
Object code:192CH
Memory space
58H
0000 0058H
R13 12345678
[Example 3] Word data: DMOV R13,@58H
Right 2-bit shift
Left 2-bit shift
Object code:1816H
R13 12345678
CM71-00104-3E
78
5678
Memory space
58H
0000 0058H
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1345678
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CHAPTER 2 MEMORY ARCHITECTURE
2.1
2.1.2
FR80 Family
Vector Table Area
An area of 1Kbyte from the address shown in the Table Base Register (TBR) is called
the “EIT” Vector Table Area.
Table Base Register (TBR) represents the top address of the vector table area. In this vector table area, the
entry addresses of EIT processing (Exception processing, Interrupt processing, Trap processing) are
described. The relation between Table Base Register (TBR) and vector table area is shown in Figure 2.1-3.
Figure 2.1-3 Relation between Table Base Register (TBR) and Vector Table Area addresses
Memory space
Number
EIT source
0000 0000 H
TBR
1 Kbyte
FFFF FFFFH
Vector
table
area
FFH
000H
Entry addressfor INT instruction
FEH
004H
Entry addressfor INT instruction
FDH
008H
Entry addressfor INT instruction
FCH
00CH
Entry addressfor INT instruction
00H
3FCH
Entry addressfor reset processing
As a result of reset, the value of Table Base Register (TBR) is initialized to "000F FC00H", and the range
of vector table area extends from "000F FC00H" to "000F FFFFH". By rewriting the Table Base Register
(TBR), the vector table area can be allocated to any desired location.
A vector table is composed of entry addresses for each "EIT" processing programs. Each vector table
contains values whose use is fixed according to the CPU architecture, and values that vary according to the
type of built-in peripheral functions. The structure of vector table area is shown in Table 2.1-1.
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CHAPTER 2 MEMORY ARCHITECTURE
2.1
FR80 Family
Table 2.1-1 Structure of Vector Table Area
Offset from TBR
Vector number
Model- dependence
EIT value description
Remarks
3FCH
00H
No
reset
3F8H
01H
No
system reserved
3F4H
to
3E4H
02H
to
06H
No
system reserved
3E0H
07H
No
3DCH
08H
No
3D8H
09H
No
INTE instruction
3D4H
0AH
No
system reserved
3D0H
0BH
No
system reserved
3CCH
0CH
No
Step trace trap
3C8H
0DH
No
system reserved
3C4H
0EH
No
Undefined instruction
exception
3C0H
0FH
No
NMI
3BCH
to
300H
10H
to
3FH
Yes
User interrupt
(used in external interrupt,
peripheral function interrupt)
Refer to the Hardware Manual
for each model
2FCH
40H
No
system reserved
Used in REALOS
2F8H
41H
No
system reserved
Used in REALOS
2F4H
to
000H
42H
to
FFH
No
Used in INT instruction
Disabled
system reserved
For use in the emulator
Emulator exception
For vector tables of actual models, refer to the hardware manuals for each model.
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CHAPTER 2 MEMORY ARCHITECTURE
2.1
2.1.3
FR80 Family
20-bit Addressing Area & 32-bit Addressing Area
The lower portion of the address space extending from 0000 0000H to 000F FFFFH
(1Mbyte) will be the 20-bit addressing area. The overall address space from 0000 0000H
to FFFF FFFFH will be 32-bit addressing space.
If all the program locations and data locations are positioned within the 20-bit addressing area, a compact
and high-speed program can be realized as compared to a 32-bit addressing area.
In a 20-bit addressing area, as the address values are within 20 bits, the LDI:20 instruction can be used for
immediate loading of address information. The instruction length (Code size) of LDI:20 instruction is
4bytes. By using LDI:20 instruction, the program becomes more compact than when using LDI:32
instruction of instruction length 6bytes.
Example of 20-bit Addressing
Code size
LDI:20
#label20,Ri
; 4 bytes
JMP
@Ri
; 2 bytes
Total 6 bytes
Example of 32-bit Addressing
Code size
LDI:32
#label32,Ri
; 6 bytes
JMP
@Ri
; 2 bytes
Total 8 bytes
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CM71-00104-3E
CHAPTER 2 MEMORY ARCHITECTURE
2.2
FR80 Family
2.2
Data Structure
FR80 Family CPU has three data types namely byte data (8-bits), half word data (16-bits)
and word data (32-bits). The byte order of FR80 Family CPU is big endian.
2.2.1
Byte Data
This is a data type having 8 bits as unit. Bit order is little endian, MSB side becomes bit7 and LSB side
becomes bit0. The structure of byte data is shown in Figure 2.2-1.
Figure 2.2-1 Structure of byte data
MSB bit
2.2.2
7
6
5
4
3
2
1
0
LSB
Half Word Data
This is a data type having 16 bits (2byte) as unit. Bit order is little endian, MSB side is bit15 while LSB
side is bit0. Bit15 to bit8 of MSB side represent the higher bytes while bit7 to bit0 of LSB side represent
the lower bytes. The structure of half word data is shown in Figure 2.2-2.
Figure 2.2-2 Structure of Half Word Data
MSB
bit 15
LSB
14
13
12
11
10
9
8
7
6
5
Higher bytes
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4
3
2
1
0
Lower bytes
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CHAPTER 2 MEMORY ARCHITECTURE
2.2
2.2.3
FR80 Family
Word Data
This is a data type having 32 bits (4byte) as unit. Bit order is little endian, MSB side is bit31 while LSB
side is bit0. Bit31 to bit16 of the MSB side become the higher half word, while bit15 to bit0 of the LSB
side become the lower half word. The structure of word data is shown in Figure 2.2-3.
Figure 2.2-3 Structure of Word Data
LSB
MSB
bit31
24 23
16 15
87
Higher half word
2.2.4
0
Lower half word
Byte Order
The byte order of FR80 Family CPU is big endian. When word data or half word data are allocated to
address spaces, the higher bytes are placed in the lower address side while the lower bytes are placed in the
higher address side. The arrangement of big endian byte data is shown in Figure 2.2-4.
For example, if a word data was written on the memory (RAM) at address location 0004 1234H of the
memory space, the highest byte will be stored at location 0004 1234H while the lowest byte will be stored
at location byte 0004 1237H.
Figure 2.2-4 Big Endian Byte Orde
Address
Byte
MSB
Half word
MSB
Word
MSB
LSB
Address
Address +1
Higher byte
Lower byte
Address
Address +1
LSB
Address +2
Highest byte
Lowest byte
Higher half word
14
Address +3
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LSB
Lower half word
CM71-00104-3E
CHAPTER 2 MEMORY ARCHITECTURE
2.3
FR80 Family
2.3
Word Alignment
The data type used determines restrictions on the designation of memory addresses
(word alignment).
2.3.1
Program Access
Unit of instruction length is half word (2byte) and all instructions are allocated to addresses which are
multiples of 2 (2n location).
At the time of execution of the instruction, bit0 of the program counter (PC) automatically becomes "0",
and is always at an even address. In a branched instruction, even if an odd address is generated as a result
of branch destination address calculation, the bit0 of the address will be assigned "0" and branched to an
even address.
There is no address exception in program access.
2.3.2
Data Access
There are following restrictions on addresses for data access depending upon the data type used.
Word data
Data is assigned to addresses that are multiples of 4 (4n location). The restriction of multiples of 4
on addresses is called ‘word boundary’. If the specified address is not a multiple of 4, the lower two
bits of the address are not set to "00" forcibly. There is no guarantee of operation when the specified
address is not a multiple of 4.
Half-word data
Data is assigned to addresses that are multiples of 2 (2n locations). The restriction of multiples of 2
on addresses is called ‘half-word boundary’. If the specified address is not a multiple of 2, the lower
1 bit of the address is not set to "0" forcibly. There is no guarantee of operation when the specified
address is not a multiple of 2.
Byte data
There is no restriction on allocation of addresses.
During word and half-word data access, condition that lower bit of an address has to be "0" is applicable
only for the result of computation of an effective address. Values still under calculation are used as they
are.
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CHAPTER 2 MEMORY ARCHITECTURE
2.3
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FR80 Family
CM71-00104-3E
CHAPTER 3
PROGRAMMING MODEL
This chapter describes the programming model of FR80
Family CPU.
3.1 FR80 Family CPU Register Configuration
3.2 General-purpose Registers
3.3 Dedicated Registers
3.4 Program Status (PS)
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CHAPTER 3 PROGRAMMING MODEL
3.1
3.1
FR80 Family
FR80 Family CPU Register Configuration
FR80 Family CPU uses two types of registers, namely, general-purpose registers and
dedicated registers.
General-purpose registers are registers that store computation data and address information. They comprise
16 registers from R0 to R15. Dedicated registers are registers that store information for specific
applications.
Figure 3.1-1 shows the configuration of registers in FR80 Family CPU.
Figure 3.1-1 FR80 Family CPU Register Configuration
32 bits
[Initial value]
R0
R1
R2
R3
R4
R5
R6
General-purpose registers
R7
R8
R9
R10
R11
R12
AC
R14
FP
R15
SP
Program counter
PC
Program status
PS
Table base register
Return pointer
-
ILM
-
SCR
CCR
TBR
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication/Division
registers
18
R13
MDH
MDL
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CM71-00104-3E
CHAPTER 3 PROGRAMMING MODEL
3.2
FR80 Family
3.2
General-purpose Registers
General-purpose registers are used for storing results of various calculations, as well
as information about addresses to be used as pointers for memory access.
3.2.1
Configuration of General-purpose Registers
FR80 Family CPU has sixteen general-purpose registers each 32 bits in length. General-purpose registers
have names R0 to R15.
In case of general instructions, the general-purpose registers can be used without any distinction. In some
instructions, three registers namely R13, R14 and R15 have special usages.
Figure 3.2-1 shows the configuration and initial values of general-purpose registers.
Figure 3.2-1 Configuration and initial values of general-purpose registers
32 bits
[Initial value]
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
AC
R14
FP
R15
SP
R0 to R14 are not initialized as a result of reset. R15 becomes 0000 0000H as a result of reset.
3.2.2
Special Usage of General-purpose Registers
General-purpose registers R13 to R15, besides being used as other general-purpose registers, are used in the
following way in some instructions.
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CHAPTER 3 PROGRAMMING MODEL
3.2
FR80 Family
R13 (Virtual Accumulator: AC)
• Base address register for load/store to memory instructions
[Example: LD @(R13,Rj), Ri]
• Accumulator for direct address designation
[Example: DMOV @dir10, R13]
• Memory pointer for direct address designation
[Example: DMOV @dir10,@R13+]
R14 (Frame Pointer: FP)
• Index register for load/store to memory instructions
[Example: LD @(R14,disp10), Ri]
• Frame pointer for reserve/release of dynamic memory area
[Example: ENTER #u10]
R15 (Stack Pointer: SP)
• Index register for load/store to memory instructions
[Example: LD @(R15,udisp6), Ri]
• Stack pointer
[Example: LD @R15+,Ri]
• Stack pointer for reserve/release of dynamic memory area
[Example: ENTER #u10]
3.2.3
Relation between Stack Pointer and “R15”
"R15" functions as an indirect register. Physically it becomes either the system stack pointer (SSP) or user
pointer (USP) for dedicated registers. When the notation "R15" is used in an instruction, this register will
function as "USP" if the stack flag (S) is "1" and as "SSP" if the stack flag is "0". Table 3.2-1 shows the
correlation between general-purpose register "R15" and stack pointer.
When something is written on "R15" as a general-purpose register, it is automatically written onto the
system stack pointer (SSP) or user stack pointer (USP) according to the value of stack flag (S).
Table 3.2-1 Correlation between General-purpose Register "R15" and Stack Pointer
General-purpose register
S Flag
Stack pointer
1
User stack pointer (USP)
0
System stack pointer (SSP)
R15
Stack flag (S) is present in the condition code register (CCR) section of the program status (PS).
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CM71-00104-3E
CHAPTER 3 PROGRAMMING MODEL
3.3
FR80 Family
3.3
Dedicated Registers
FR80 Family CPU has dedicated registers reserved for special usages.
3.3.1
Configuration of Dedicated Registers
Dedicated registers are used for special purposes. The following dedicated registers are available.
• Program counter (PC)
• Program status (PS)
• Return pointer (RP)
• System stack pointer (SSP)
• User stack pointer (USP)
• Table base register (TBR)
• Multiplication/Division Register (MDH, MDL)
Figure 3.3-1 shows the configuration and initial values of dedicated registers.
Figure 3.3-1 Configuration and Initial Values of Dedicated Registers
32 bits
[Initial value]
Program counter
PC
Program status
PS
Table base register
Return pointer
CM71-00104-3E
ILM
-
SCR
CCR
TBR
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication/Division
registers
-
MDH
MDL
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CHAPTER 3 PROGRAMMING MODEL
3.3
3.3.2
FR80 Family
Program Counter (PC)
Program counter (PC) is a 32-bit register that indicates the address containing the instruction that is
currently executing.
Figure 3.3-2 shows the bit configuration of program counter (PC).
Figure 3.3-2 Program Counter (PC) Bit Configuration
bit0
bit31
Initial value
XXXX XXXX H
The value of the lowest bit of the program counter (PC) is always read as “0”. Even if "1" is written to it as
a result of address calculation of branching destination, the lowest bit of branching address will be treated
as "0". When the program counter (PC) changes after the execution of an instruction and it indicates the
next instruction, the lowest bit is always read as "0".
Following a reset, the contents of the Program Counter (PC) are set to the value (reset entry address)
written in the reset vector of the vector table. As the table base register (TBR) is initialized first by reset,
the address of the reset vector will be 000F FFFCH.
3.3.3
Return Pointer (RP)
Return pointer (RP) is a 32-bit register which stores the address for returning from a subroutine.
Figure 3.3-3 shows the bit configuration of return pointer (RP).
Figure 3.3-3 Return Pointer (RP) Bit Configuration
bit0
bit31
Initial value
XXXXXXXX
H
In case of a CALL instruction with a delay slot, the value stored in RP will be the address of the CALL
instruction +4.
In case of a CALL instruction with no delay slot, the value stored in RP will be the address of the CALL
instruction +4.
When returning from a subroutine by the "RET" instruction, the address stored in the return pointer (RP) is
returned to the program counter (PC).
Return pointer (RP) does not have a stack configuration. When calling another subroutine from the
subroutine called using the "CALL2" instruction, it is necessary to first save the contents of the return
pointer (RP) and restore them before executing the “RET” instruction.
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CHAPTER 3 PROGRAMMING MODEL
3.3
FR80 Family
Figure 3.3-4 shows a sample operation of the return pointer (RP) during the execution of a "CALL"
instruction with no delay slot, and Figure 3.3-5 shows a sample operation of return pointer (RP) during the
execution of a "RET" instruction.
Figure 3.3-4 Sample Operation of RP during Execution of a "CALL" Instruction with No Delay Slot
Memory space
Before execution
PC
12345678H
RP
????????H
CALL SUB1
SUB1
Memory space
After execution
PC
SUB1
RP
1234567AH
CALL SUB1
SUB1
RET
RET
Figure 3.3-5 Sample Operation of RP during Execution of a "RET" Instruction.
Memory space
Memory space
Before execution
After execution
CALL SUB1
CALL SUB1
PC
SUB1
RP
1234567AH
ADD #1,R0
SUB1
3.3.4
PC
1234567AH
RP
1234567AH
RET
ADD #1,R0
SUB1
RET
System Stack Pointer (SSP)
The system stack pointer (SSP) is a 32-bit register that indicates the address to be saved/restored to the
system stack used at the time of EIT processing.
Figure 3.3-6 shows the bit configuration of system stack pointer (SSP).
Figure 3.3-6 System Stack Pointer (SSP) Bit Configuration
bit0
bit31
Initial value
00000000
H
When the stack flag (S) in the condition code register (CCR) is "0", the general-purpose register "R15" is
used as the system stack pointer (SSP). In a normal instruction, system stack pointer is used as the generalpurpose register “R15”.
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CHAPTER 3 PROGRAMMING MODEL
3.3
FR80 Family
When an "EIT" event occurs, regardless of the value of the stack flag (S), the program counter (PC) and
program status (PS) values are saved to the system stack area designated by system stack pointer (SSP).
The value of stack flag (S) is stored in the system stack as program status (PS), and is restored from the
system stack at the time of returning from the EIT event using "RETI" instruction.
System stack uses pre-decrement/post-decrement for storing and retrieving data. While saving data, after
performing a data size decrement on the value of system stack pointer (SSP), it is written onto the address
indicated by system stack pointer (SSP). While retrieving data, after the data is read from the address
indicated by the system stack pointer (SSP), a data size increment is performed on the value of system stack
pointer (SSP).
Figure 3.3-7 shows an example of system stack pointer (SSP) operation while executing instruction "ST
R13,@-R15" when the stack flag (S) is set to "0".
Figure 3.3-7 Example of System Stack Pointer (SSP) Operation
Before execution of ST R13,@-R15
After execution of ST R13,@-R15
Memory space
00000000 H
SSP
12345678H
USP
R13
SSP
12345674H
76543210H
USP
76543210H
17263540H
R13
17263540H
????????
S
CCR
3.3.5
????????
Memory space
00000000H
FFFFFFFFH
????????
FFFFFFFFH
S
CCR
0
17263540H
0
User Stack Pointer (USP)
User stack pointer (USP) is a 32-bit register used to save/retrieve data to/from the user stack.
Figure 3.3-8 shows the bit configuration of user stack pointer (USP).
Figure 3.3-8 User Stack Pointer (USP) Bit Configuration
bit0
bit31
Initial value
XXXXXXXX
H
When the stack flag (S) in the condition code register (CCR) is "1", the general-purpose register "R15" is
used as the user stack pointer (USP). In a normal instruction, user stack pointer (USP) is used as the
general-purpose register "R15".
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CM71-00104-3E
CHAPTER 3 PROGRAMMING MODEL
3.3
FR80 Family
User stack uses pre-decrement/post-decrement to save/retrieve data. While saving data, after performing a
data size decrement on the value of user stack pointer (USP), it is written onto the address indicated by the
user stack pointer (USP). While retrieving data, the data is read from the address indicated by the user stack
pointer (USP), and a data size increment is performed on the value of user stack pointer (USP).
Figure 3.3-9 shows an example of user stack pointer (USP) operation while executing the instruction "ST
R13,@-R15" when the stack flag (S) is set to "1".
Figure 3.3-9 Example of User Stack Pointer (USP) Operation
Before execution of ST R13,@-R15
After execution of ST R13,@-R15
Memory space
00000000 H
SSP
12345678 H
USP
R13
SSP
12345678 H
76543210 H
USP
7654320C H
17263540 H
R13
17263540H
????????
????????
S
CCR
3.3.6
Memory space
00000000 H
????????
FFFFFFFFH
FFFFFFFFH
S
CCR
1
17263540H
1
Table Base Register (TBR)
Table base register (TBR) is a 32-bit register that designates the vector table containing the entry addresses
for "EIT" operations.
Figure 3.3-10 shows the bit configuration of table base register (TBR).
Figure 3.3-10 Table Base Register (TBR) Bit Configuration
bit0
bit31
Initial value
000FFC00 H
The address of the reference vector is determined by the sum of the contents of the table base register
(TBR) and the vector offset corresponding to the "EIT" operation generated. Vector table layout is realized
in word units. As the address of the calculated vector is in word units, the lower two bits of the resulting
address value are explicitly read as “0”.
Figure 3.3-11 shows an example of table base register (TBR).
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Figure 3.3-11 Example of Table Base Register (TBR) Example
Vector correspondence table
bit31
Vector no.
bit0
Eaddr0 Eaddr1
Timer
interrupt
11H
PC
Eaddr2 Eaddr3
87654123 H TBR
3B8H
Adder
Vector table
87654123H +000003B8H
+0
+1
+2
+3
876544DBH
876544D8H
Eaddr0 Eaddr1
Eaddr2 Eaddr3
The reset value of table base register (TBR) is 000F FC00H. Do not set a value above FFFF FC00H for the
table base register (TBR).
Precautions:
If values greater than "FFFF FC00H" are assigned to the table base register (TBR), this operation
may result in an overflow when summed with the offset value. An overflow in turn will result in
vector access to the area "0000 0000H to 0000 03FFH", which can cause a program run away.
3.3.7
Multiplication/Division Register (MDH, MDL)
Multiplication/Division register (MDH, MDL) is a 64-bit register comprised of "MDH" represented by the
higher 32 bits and "MDL" represented by the lower 32 bits. During multiplication, the product is stored.
During division, the value set for the dividend and the quotient is stored.
Figure 3.3-12 shows the bit configuration of Multiplication/Division register (MDH, MDL).
Figure 3.3-12 Multiplication/Division Register (MDH, MDL) Bit Configuration
bit31
bit0
Initial value
MDH
XXXXXXXX H
MDL
XXXXXXXX H
The function of Multiplication/Division register (MDH, MDL) is different during a multiplication and
during a division operation.
● Function during Multiplication
In case of a 32 bit × 32 bit multiplication (MUL, MULU instruction), the calculation result of 64-bit length
is stored in the product register (MDH, MDL) as follows.
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MDH: higher 32 bits
MDL: lower 32 bits
In case of a 16 bit × 16 bit multiplication (MULH, MULUH instruction), the calculation result of 32-bit
length is stored in the product register (MDH, MDL) as follows.
MDH: undefined
MDL: result 32 bits
Figure 3.3-13 shows an example of multiplication operation using Multiplication/Division register (MDH,
MDL).
Figure 3.3-13 Example of Multiplication Operation using Multiplication/Division Register (MDH, MDL)
Before execution of instruction MUL R0, R1
After execution of instruction MUL R0, R1
R0
12345678H
R0
12345678H
R1
76543210H
R1
76543210H
MDH, MDL ???????? ???????? H
MDH, MDL 086A1C97 0B88D780 H
● Function during Division
Before starting the calculation, store the dividend in the Multiplication/Division register (MDH, MDL).
MDH: don’t care
MDL: dividend
When division is performed using any of the instructions DIV0S/DIV0U, DIVI1, DIV2, DIV3, DIV4S
meant for division, the result of division is stored in the Multiplication/Division register (MDH, MDL) as
follows.
MDH: remainder
MDL: quotient
Figure 3.3-14 shows an example of division operation using Multiplication/Division register (MDH, MDL).
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Figure 3.3-14 Example of Division Operation using Multiplication/Division Register (MDH,MDL)
Before execution of stepwise division
After execution of stepwise division
R0
R0
12345678H
12345678H
Using R0
MDH, MDL ???????? 76543210H
28
MDH, MDL 091A2640 00000006H
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CHAPTER 3 PROGRAMMING MODEL
3.4
FR80 Family
3.4
Program Status (PS)
Program status (PS) is a 32-bit register that indicates the status of program execution. It
sets the interrupt enable level, controls the program trace break function in the CPU,
and indicates the status of instruction execution.
Program status (PS) consists of the following three parts.
• Interrupt level mask register (ILM)
• System condition code register (SCR)
• Condition code register (CCR)
Figure 3.4-1 shows the bit configuration of program status (PS).
Figure 3.4-1 Program status (PS) Bit Configuration
bit31
bit20
Reserved
bit16
ILM
bit10 bit8 bit7
Reserved SCR
bit0
CCR
The reserved bits of program status (PS) are all reserved for future expansion. The read value of reserved
bits is always "0". Write values should always be written as "0".
3.4.1
Interrupt Level Mask Register (ILM)
Interrupt level mask register (ILM) is a 5-bit register used to store the interrupt level mask value. It lies
between bit20 to bit16 of the program status (PS).
Figure 3.4-2 shows the bit configuration of interrupt level mask register (ILM).
Figure 3.4-2 Interrupt Level Mask Register (ILM) Bit Configuration
bit20 bit19 bit18 bit17 bit16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
The value stored in interrupt level mask register (ILM), is used in the level mask of an interrupt. When the
interrupt enable flag (I) is "1", the value of interrupt level mask register (ILM) is compared to the level of
the currently requested interrupt. If the value of interrupt level mask register (ILM) is greater (interrupt
level is stronger), interrupt requested is accepted. Figure 3.4-3 shows the functions of interrupt level mask.
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Figure 3.4-3 Functions of Interrupt Level Mask
FR80 family CPU
ILM
Peripheral
Interrupt
request
1
29
ICR
25
Comp
AND
Interrupt controller
29>25
Interrupt activated
Activation OK
The values of interrupt level range from 0(00000B) to 31(11111B). The smaller the value of interrupt level,
the stronger it is, and the larger the value, the weaker it is. 0(00000B) is the strongest interrupt level, while
31(11111B) is the weakest.
There are following restrictions on values of the interrupt level mask register (ILM) that can be set from a
program.
• When the value of interrupt level mask register (ILM) lies between 0(00000B) to 15(01111B), only values
from 0(00000B) to 31(11111B) can be set.
• When the value of interrupt level mask register (ILM) lies between 16(10000B) to 31(11111B), only
values between 16(10000B) to 31(11111B) can be set.
• When setting of values between 0(00000B) to 15(01111B) is attempted, 16 is added on automatically and
values between 16(10000B) to 31(11111B) are set.
The interrupt level mask register (ILM) is initialized to 15(01111B) following a reset. If an interrupt request
is accepted, the interrupt level corresponding to that interrupt is set in the interrupt level mask register
(ILM).
For setting a value in interrupt level mask register (ILM) from a program, the STILM instruction is used.
3.4.2
Condition Code Register (CCR)
Condition code register (CCR) is an 8-bit register that indicates the status of instruction execution. It lies
between bit7 to bit0 of the program status (PS).
Figure 3.4-4 shows the bit configuration of condition code register (CCR).
Figure 3.4-4 Condition Code Register (CCR) Bit Configuration
CCR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
S
I
N
Z
V
C
Initial value
--00XXXX B
The contents of each bit are described below.
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[bit7, bit6] Reserved
These are reserved bits. Read value is always "0". Write value should always be "0".
[bit5] S: Stack Flag
This flag selects the stack pointer to be used as general-purpose register "R15". When the value of
stack flag (S) is "0", system stack pointer (SSP) is used, while when the value is "1", user stack
pointer (USP) is used.
Table 3.4-1 Stack Flag (S) of Condition Code Register
flag
value
Meaning
0
System stack pointer (SSP)
1
User stack pointer (USP)
S
If an EIT operation is accepted, stack flag (S) automatically becomes "0". However, the value of the
condition code register (CCR) saved in system stack is the value which is later replaced by "0".
The initial value of stack flag (S) after a reset is "0".
[bit4] I: Interrupt Enable Flag
This flag is used to enable/disable mask-able interrupts. The value "0" of interrupt enable flag(I)
disables an interrupt while "1" enables an interrupt. When an interrupt is enabled, the mask
operation of interrupt request is performed by interrupt level mask register (ILM).
Table 3.4-2 Interrupt Enable Flag (I) of Condition Code Register
flag
Value
Meaning
0
Interrupt disable
1
Interrupt enable
I
The value of this flag is replaced by "0" by execution of INT instruction. However, the value of
condition code register (CCR) saved in the system stack is the value which is later replaced by "0".
The initial value of an interrupt enable flag (I) after a reset is "0".
[bit3] N: Negative Flag
This flag is used to indicate positive or negative values when the results of a calculation are
expressed in two’s complement form. The value "0" of the negative flag (N) indicates a positive
value while "1" indicates a negative value.
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Table 3.4-3 Negative Flag (N) of Condition Code Register
flag
value
N
Meaning
0
Calculation result is a positive value
1
Calculation result is a negative value
The initial value of Negative flag (N) after a reset is undefined.
[bit2] Z: Zero Flag
This flag indicates whether the result of a calculation is zero or not. The value "0" of zero flag (Z)
indicates a non-zero value, while "1" indicates a zero value.
Table 3.4-4 Zero Flag (Z) of Condition Code Register
flag
value
Z
Meaning
0
Calculation result is a non-zero value
1
Calculation result is a zero value
The initial value of Zero flag (Z) after a reset is undefined.
[bit1] V: Overflow Flag
This flag indicates whether an overflow has occurred or not when the results of a calculation are
expressed in two’s complement form. The value "0" of an overflow flag (V) indicates no overflow,
while value "1" indicates an overflow.
Table 3.4-5 Overflow Flag (V) of Condition Code Register
flag
value
V
Meaning
0
No overflow
1
Overflow
Initial value of overflow flag (V) after a reset is indefinite
[bit0] C: Carry Flag
This flag indicates whether a carry or borrow condition has occurred in the highest bit of the results
of a calculation. The value "0" of the carry flag (C) indicates no carry or borrow, while a value "1"
indicates a carry or borrow condition.
Table 3.4-6 Carry Flag (C) of Condition Code Register
flag
C
32
value
Meaning
0
No carry or borrow
1
Carry or borrow condition
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The initial value of a carry flag (C) after reset is undefined.
3.4.3
System Condition Code Register (SCR)
System condition code register (SCR) is a 3-bit register used to control the intermediate data of stepwise
division and step trace trap. It lies between bit10 to bit8 of the program status (PS).
Figure 3.4-5 shows the bit configuration of system condition code register (SCR).
Figure 3.4-5 System Condition Code Register (SCR) Bit Configuration
bit10
bit9
bit8
Initial value
D1
D0
T
XX0 B
The contents of each bit are described below.
[bit10, bit9] D1, D0: Step Intermediate Data
These bits are used for intermediate data in stepwise division. This register is used to assure
resumption of division calculations when the stepwise division program is interrupted during
processing.
If changes are made to the contents of the intermediate data (D1, D0) during division processing, the
results of the division are not assured. If another processing is performed during stepwise division
processing, division can be resumed by saving/retrieving the program status (PS) in/from the system
stack.
Intermediate data (D1, D0) of stepwise division is made into a set by referencing the dividend and
divisor by executing the "DIV0S" instruction. It is cleared by executing the "DIV0U" instruction.
The initial value of intermediate data (D1, D0) of stepwise division after a CPU reset is undefined.
[bit8] T: Step Trace Trap Flag
This flag specifies whether the step trace trap operation has to be enabled or not. When the step trace
trap flag (T) is set to "1", step trace flag operation is enabled and the CPU generates an EIT event by
trap operation after each instruction execution.
Table 3.4-7 Step Trace Trap Flag (T) of System Condition Code Register
flag
value
Meaning
0
Step trace trap disabled
1
Step trace trap enabled
T
When the step trace trap flag (T) is "1", all NMI & user interrupts are disabled.
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Step trace trap function uses an emulator. During a user program which uses the emulator, step trace
trap function cannot be used (the emulator cannot be used for debugging in the step trace trap
routine).
The initial value of step trace trap flag (T) after a reset is "0".
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CHAPTER 4
RESET AND "EIT"
PROCESSING
This chapter describes reset and “EIT” processing in the
FR80 family CPU. “EIT” processing is the generic name
for exceptions, interrupt and trap
4.1 Reset
4.2 Basic Operations in "EIT" Processing
4.3 Exception Processing
4.4 Interrupts
4.5 Traps
4.6 Multiple "EIT" Processing and Priority Levels
4.7 Timing When Register Settings Are Reflected
4.8 Usage Sequence of User Interrupts
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4.1
4.1
FR80 Family
Reset
A Reset is a means of forcibly terminating the currently executing process, initializing
the entire device, and restarting the program from the beginning. Resets are used when
the device is started the first time, as well as to recover from error conditions.
When a reset is generated, CPU terminates the processing of the instruction execution at that time and goes
into inactive status until the reset is cancelled. When the reset is cancelled, the CPU initializes all internal
registers and starts execution beginning with the program indicated by the new value of the program
counter (PC).
Reset processing has a higher priority level than each operation of the "EIT" processing described later.
Reset is accepted even in between an "EIT" processing. A reset is accepted instantaneously, and the time
from the cancellation of reset to the execution of the first instruction, is "a+2" cycle by the CPU clock. "a"
is the data access cycle.
When a reset is generated, FR80 family CPU makes an attempt to initialize each register, but all registers
cannot be initialized. Each register sets a value through the program executed after a reset, and uses it.
Table 4.1-1 shows the registers that are initialized following a reset.
Table 4.1-1 Registers that are initialized following a reset
Register
Initial Value
Remarks
Program counter (PC)
Word data at location 000F FFFCH
Interrupt level mask register (ILM)
15(01111B)
Step trace trap flag (T)
“0”
Trace OFF
Interrupt enable flag (I)
“0”
Interrupt disabled
Stack flag (S)
“0”
Use SSP
Table base register (TBR)
000F FC00H
System stack pointer (SSP)
0000 0000H
General-purpose register “R15”
SSP
Reset vector
As per stack flag (S)
For details of My computer built-in functions (peripheral devices, etc.) following a reset, refer to the
Hardware Manual provided with each device.
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4.2
FR80 Family
4.2
Basic Operations in "EIT" Processing
Exceptions, interrupts and traps are similar operations applied under partially different
conditions. They save information for terminating or restarting the execution of
instructions and perform branching to a processing program.
4.2.1
Types of "EIT" Processing and Prior Preparation
"EIT" processing is a method which terminates the currently executing process and transfers control to a
predetermined processing program after saving restart information to the memory. "EIT" processing
programs can return to the prior program by use of the "RETI" instruction.
“EIT” processing operates in essentially the same manner for exceptions, interrupts and traps, with a few
minor differences listed below by which it differentiates them.
• Exceptions are related to the instruction sequence, and processing is designed to resume from the
instruction in which the exception occurred.
• Interrupts originate independently of the instruction sequence. Processing is designed to resume from the
instruction immediately following the acceptance of the interrupt.
• Traps are also related to the instruction sequence, and processing is designed to resume from the
instruction immediately following the instruction in which the trap occurred.
While performing "EIT" processing, apply to the following prior settings in the program.
• Set the values in vector table (defining as data)
• Set the value of system stack pointer (SSP)
• Set the value of table base register (TBR) as the initial address in the vector table
• Set the value of interrupt level mask register (ILM) above 16(10000B)
• Set the interrupt enable flag (I) to "1"
The setting of interrupt level mask register (ILM) and interrupt enable flag (I), will be required at the time
of using interrupts.
4.2.2
"EIT" Processing Sequence
FR80 family CPU processes "EIT" events as follows.
1. The vector table indicated by the table base register (TBR) and the offset value of the vector number
corresponding to the particular "EIT" are used to determine the entry address for the processing program
for the "EIT".
2. For restarting, the contents of the old program counter (PC) and the old program status (PS) are saved to
the stack area designated by the system stack pointer (SSP).
3. "0" is saved in the stack flag (S). Also, the interrupt level Mask Register (ILM) and interrupt enable flag
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4.2
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(I) are updated through "EIT".
4. Entry address is saved in the program counter (PC).
5. After the processing flow is completed, just before the execution of the instruction in the entry address,
the presence of new "EIT" sources is determined.
Figure 4.2-1 shows the operations in the "EIT" processing sequence.
Figure 4.2-1 Operations in "EIT" Processing Sequence
Instruction at which EIT event is detected
Canceled instruction
Canceled instruction
IF
ID
EX
MA
IF
ID
xxxx xxxx xxxx
IF
xxxx xxxx xxxx xxxx
(1) Vector address calculation and new PC setting
WB
ID(1) EX(1) MA(1) WB(1)
ID(2) EX(2) MA(2) WB(2)
(2) SSP update and PS save
(3) SSP update and PC save
(4) Detection of new EIT event
EIT sequence
ID(3) EX(3) MA(3) WB(3)
ID(4) EX(4) MA(4) WB(4)
IF
First instruction in EIT handler sequence (branching instruction)
ID
EX
MA
PC
Vector tables are located in the main memory, occupying an area of 1 Kbyte beginning with the address
shown in the table base register (TBR). This area is used as a table of entry addresses for "EIT" processing.
For details on vector tables, refer to "2.1.2 Vector Table Area" and "3.3.6 Table Base Register (TBR)".
Regardless of the value of stack flag (S), the program status (PS) and program counter (PC) is saved in the
stack pointed to by the system stack pointer (SSP). After an "EIT" processing has commenced, the program
counter (PC) is saved in the address pointed to by the system stack pointer (SSP), while the program status
(PS) is saved at address 4 plus the address pointed to by the system stack pointer (SSP).
Figure 4.2-2 shows an example of saving program counter (PC) and program status (PS) during the
occurrence of an "EIT" event.
Figure 4.2-2 Example of storing of PC, PS during an "EIT" event occurrence
[Example]
SSP
[Before interrupt]
80000000 H
[After interrupt]
SSP
Memory
7FFFFFF8 H
7FFFFFFC H
80000000 H
38
7FFFFFF8 H
Memory
7FFFFFF8 H
7FFFFFFC H
80000000 H
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.2
FR80 Family
4.2.3
Recovery from "EIT" Processing
"RETI" instruction is used for recovery from an "EIT" processing program. The "RETI" instruction
retrieves the value of program counter (PC) and program status (PS) from the system stack, "EIT" and
recovers from the "EIT" processing.
1. Retrieving program counter (PC) from the system stack
(SSP) → PC
SSP+4 → SSP
2. Retrieving program status (PS) from the system stack
(SSP) → PS
SSP+4 → SSP
To ensure the program execution results after recovery from the "EIT" processing program, it is required
that all contents of the CPU registers before the commencement of "EIT" processing program have been
saved at the time of recovery. The registers used in the "EIT" processing programs should be saved in the
system stack and retrieved just before the "RETI" instruction.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.3
4.3
FR80 Family
Exception Processing
Exceptions originate when there is a problem in the instruction sequence. Exceptions
are processed by first saving the necessary information to resume the currently
executing instruction, and then starting the processing routine corresponding to the
type of exception that has occurred.
Branching to the exception processing routine takes place before execution of the instruction that has
caused the exception. The address of the instruction in which the exception occurs becomes the program
counter (PC) value that is saved to the stack at the time of occurrence of the exception.
The following factor can cause occurrence of an exception:
• Undefined-instruction exception
4.3.1
Undefined-instruction exception
Undefined-instruction exceptions are caused by attempts to execute instruction codes for which operations
are not defined in the CPU.
If an undefined-instruction is detected at the time of decoding instructions, an undefined-instruction
exception is generated. Conditions for detection of undefined-instruction exception are as follows:
• Undefined-instruction is detected at the time of decoding an instruction
• Undefined-instructions placed in delay slots (not immediately after delayed branching instruction)
Undefined-instructions placed in delay slots do not generate undefined instruction exceptions. In such
cases, undefined instructions have the same operation as "NOP" instructions.
The following operations are performed if an undefined-instruction exception is accepted. The time
required to start exception processing with an undefined-instruction exception is 7 cycles of the CPU clock.
1. The entry address of the undefined-instruction exception is retrieved by referring the vector table.
(TBR+3C4H) → TMP
2. Contents of program status (PS) are saved to the system stack.
SSP - 4 → SSP
PS → (SSP)
3. The address of the instruction that caused the undefined-instruction exception is saved to the system
stack.
SSP - 4 → SSP
PC → (SSP)
4. The value “0” is stored to the stack flag (S) in the condition code register (CCR).
"0" → S
5. The value of entry address retrieved in 1. is stored in the program counter (PC).
TMP → PC
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.3
The address saved to the system stack as a program counter (PC) value represents the instruction itself that
caused the undefined instruction exception. When a "RETI" instruction is executed, the contents of the
system stack should be rewritten with the exception processing routine so that the execution will either
resume from the address of the instruction next to the instruction that caused the exception, or branch to the
appropriate processing routine.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.4
4.4
FR80 Family
Interrupts
Interrupts originate independently of the instruction sequence. They are processed by
saving the necessary information to resume the currently executing instruction
sequence, and then starting the processing routine corresponding to the type of the
interrupt that has occurred interrupt.
Instruction loaded and executing in the CPU before the interrupt will be executed till completion. However
any instruction loaded in the pipeline after the interrupt will be cancelled. Hence, after completion of the
interrupt processing, processing will return to the instruction following the generation of the interrupt
signal.
The following two factors cause the generation of interrupts.
• User interrupts
• Non-maskable interrupt (NMI)
In case an interrupt is generated during the execution of stepwise division instructions, intermediate data is
saved to the program status (PS) to enable resumption of processing. Therefore, if the interrupt processing
program overwrites the contents of the program status (PS) data in the stack, the processor will resume the
normal instruction operations following resumption of processing. However the results of the division
calculation will be incorrect.
4.4.1
User interrupts
User interrupts originate as requests from in-built peripheral functions. Here, the in-built interrupt
controller present in devices and external interrupt control units have been described as one of the
peripheral functions.
The interrupt requests from various in-built peripheral functions are accepted via interrupt controller.
There are some interrupt requests which use external interrupt control unit, taking external terminals as
interrupt input terminals. Figure 4.4-1 shows the acceptance procedure of user interrupts.
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4.4
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Figure 4.4-1 Acceptance Procedure of User Interrupts
FR80 family CPU
PS
Interrupt
request
SSP USP
I
AND
ILM
Interrupt
controller
Peripheral
resource
ICR#n
Interrupt
flag bit
S
Comparator
Each interrupt request is assigned an interrupt level by the interrupt controller, and it is possible to mask
requests according to their level values. Also, it is possible to disable all interrupts by using the interrupt
enable flag (I) in the condition code register (CCR).
When interrupt requests are generated by peripheral functions, they can be accepted under the following
conditions.
• The level of interrupt level mask register (ILM) is higher (i.e. the numerical value is smaller) than the
interrupt level set in the interrupt control register (ICR) corresponding to the vector number
• The interrupt enable flag (I) in the condition code register (CCR) is set to “1”
Interrupt control register (ICR) is a register of interrupt controller. Refer to the hardware manual of various
models for details about the interrupt controller.
The time required to start user interrupt processing can be expressed as a maximum of "n+6" cycles by the
CPU clock from the start of the instruction currently executing when the interrupt was received, where "n"
represents the number of execution cycles in the instruction. If the instruction includes memory access, or
insufficient instructions are present, the corresponding number of wait cycles must be added.
The following operations are performed after a user interrupt is accepted.
1. The entry address of the accepted interrupt factor is retrieved by referring to the vector table.
(TBR+ vector offset of the accepted interrupt factor vector) → TMP
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP
PS → (SSP)
3. The address of the next instruction is saved to the system stack.
SSP - 4 → SSP
next instruction address → (SSP)
4. The level of the accepted interrupt request are stored in interrupt level mask register (ILM)
interrupt level → ILM
5. The value "0" is stored in the stack flag (S) of condition code register (CCR)
"0" → S
6. The entry address of 1. is stored in the program counter (PC)
TMP → PC
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4.4
FR80 Family
When an interrupt is accepted by the processor, those instructions in the pipeline that cannot be interrupted
in time will continue to be executed. The remainder of the instructions will be cancelled, and will not be
processed after the interrupt. The "EIT" processing sequence saves the addresses of the cancelled
instructions to the system stack as program counter (PC) values.
When using user interrupts, it is required to set the interrupt level in the interrupt control register (ICR)
corresponding to the vector number of the interrupt controller. Also perform the settings of the various
peripheral functions and interrupt enable. Refer to the hardware manual of each model for details on
interrupt controller and various peripheral functions.
4.4.2
Non-maskable Interrupts (NMI)
Non-maskable interrupts (NMI) are interrupts that cannot be masked.
Depending upon the product series, there are models which do not support "NMI" (there are no external
"NMI" terminals). Refer to the hardware manual of various models to check whether "NMI" is supported or
not.
Even if the acceptance of interrupts have been restricted by setting of "0" in the interrupt enable flag (I) of
the condition code register (CCR), interrupts generated by "NMI" cannot be restricted. The masking of
interrupt level by the interrupt level mask register (ILM) is valid. If a value above 16(10000B) is set in the
interrupt level mask register (ILM) by a program, normally "NMI" cannot be masked by the interrupt level.
The value of interrupt level mask register (ILM) is initialized to 15(01111B) following a reset. Therefore,
NMI cannot be masked until a value above 16(10000B) by a program following a reset.
The time required to start processing of an "NMI" can be expressed as a maximum f "n+6" cycles by the
CPU clock from the start of the instruction currently executing when the interrupt was received, where "n"
represents the number of execution cycles in the instruction. If the instruction includes memory access, or
insufficient instructions are present, the corresponding number of wait cycles must be added.
When an "NMI" is accepted, the following operations are performed.
1. The entry address of "NMI" is retrieved by referring to the vector table
(TBR+3C0H) → TMP
2. The contents of the program status (PS) are saved to the system stack
SSP - 4 → SSP
PS → (SSP)
3. The address of the next instruction is saved to the system stack.
SSP - 4 → SSP
next instruction address → (SSP)
4. The value 15(01111B) is stored in the interrupt level mask register (ILM)
01111B → ILM
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.4
FR80 Family
5. The value "0" is stored in the stack flag (S) of the condition code register (CCR)
"0" → S
6. The entry address of 1. is stored in the program counter (PC)
TMP → PC
When an "NMI" is accepted by the processor, those instructions in the pipeline that cannot be interrupted in
time will continue to be executed. The remainder of the instructions will be cancelled, and will not be
processed after the interrupt has been accepted. The "EIT" processing sequence saves the addresses of the
cancelled instructions in the system stack as program counter (PC).
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
4.5
FR80 Family
Traps
Traps are generated from within the instruction sequence. Traps are processed by first
saving the necessary information to resume processing from the next instruction in the
sequence, and then starting the processing routine corresponding to the type of the
trap that has occurred.
Branching to the processing routine takes place after execution of the instruction that has caused the trap.
The address of the instruction in which the trap occurs becomes the program counter (PC) value that is
saved to the stack at the time of trap generation.
Following factors can lead to generation of traps.
• INT instruction
• INTE instruction
• Step trace traps
4.5.1
"INT" Instructions
The INT #u8 instruction is used to create a trap through software. It generates a trap corresponding to the
interrupt number designated in the operand.
When the "INT" instruction is executed, the following operations take place. The time required to start trap
processing through "INT" instruction is 6 cycles by the CPU clock.
1. The entry address of the "INT" instruction is retrieved by referring to the vector table.
(TBR+3FCH - 4 × u8) → TMP
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP
PS → (SSP)
3. The address of the next instruction is saved to the system stack.
SSP - 4 → SSP
next instruction address → (SSP)
4. The value "0" is stored in the interrupt enable flag (I) of the condition code register (CCR)
"0" → I
5. The value "0" I stored in the stack flag (S) of the condition code register (CCR)
"0" → S
6. The entry address of 1. is stored in the program counter (PC)
TMP → PC
The value of program counter (PC) saved to the system stack represents the address of the next instruction
after the "INT" instruction.
The "INT" instruction should not be used within an "INTE" instruction handler, a trap processing routine,
or trap processing routine of step trace trap. This will prevent normal operation from resuming after "RETI"
instruction.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
FR80 Family
4.5.2
"INTE" Instruction
The "INTE" instruction is used to create a software trap for debugging.
“INTE” instruction uses emulators. This technique can be used in user programs in case of systems that
have not been debugged by emulators.
The following operations take place when "INTE" instruction is executed. The time required to start
trap processing through “INTE” instruction is 6 cycles by the CPU clock.
1. The entry address of "INTE" instruction is retrieved by referring to the vector table.
(TBR+3D8H) → TMP
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP
PS → (SSP)
3. The address of the next instruction is saved to the system stack.
SSP - 4 → SSP
next instruction address → (SSP)
4. The value "4(00100B)" is stored in the interrupt level mask register (ILM) of the program status (PS)
00100B → ILM
5. The value "0" is stored in the stack flag (S) of the condition code register (CCR)
"0" → S
6. The entry address value of 1. is stored in the program counter (PC)
TMP → PC
The address saved in the system stack as program counter (PC) represents the address of the next
instruction after the "INTE" instruction.
The "INTE" instruction should not be used within a trap processing routine of "INTE" instruction or trap
processing routine of step trace trap. This will prevent normal operation from resuming after the "RETI"
instruction.
Trap processing through "INTE" instruction does not start when step execution through step trace trap is in
progress.
4.5.3
Step Trace Traps
Step trace traps are traps used for debugging programs. Through this, a trap can be created after the
execution of each instruction by setting the step trace trap flag (T) in the system condition code register
(SCR).
Step trace trap flag (T) uses emulators. For systems that have not been debugged by emulators, step trace
traps can be used within user programs.
Step trace trap is enabled from the instruction next to the instruction where the step trace trap flag (T) is set
to "1". A step trace trap is generated when the following conditions are met.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
FR80 Family
• Step trace trap flag (T) in the system condition code register (SCR) is set to "1".
• The currently executing instruction is not a delayed branching instruction
• The CPU is not processing an “INTE” instruction or a trap processing routine of step trace trap
Step trace trap is not generated immediately after the execution of a delayed branching instruction. It is
generated after the execution of instruction within the delay slots.
When a step trace trap is generated, the following operations take place.
1. The entry address of the step trace trap is retrieved by referring to the vector table
(TBR+3CCH) → TMP
2. The contents of the program status (PS) are saved to the system stack
SSP - 4 → SSP
PS → (SSP)
3. The address of the next instruction is saved to the system stack
SSP - 4 → SSP
next instruction address → (SSP)
4. The value "0" is stored in the stack flag (S) of the condition code register (CCR)
"0" → S
5. The entry address value of 1. is stored in the program counter (PC)
TMP → PC
The address saved as program counter (PC) in the system stack represents the address of the next
instruction after the step trace trap.
When the step trace trap is enabled by setting the step trace trap flag (T) to "1", the "NMI" and user
interrupts will get disabled.
The step trace trap flag (T) is not retuned to "0" following the acceptance of a step trace trap. The CPU
enters the step trace trap processing routine once a step trace trap is accepted, and does not accept a step
trace trap in the midst of an "EIT" processing program (until the processing returns from the processing
program by a "RETI" instruction).
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.6
FR80 Family
4.6
Multiple "EIT" Processing and Priority Levels
When multiple "EIT" requests occur at the same time, priority levels are used to select
one source and execute the corresponding "EIT" sequence.
4.6.1
Multiple "EIT" Processing
When multiple "EIT" requests occur at the same time, CPU selects one source and executes the
corresponding "EIT" sequence and then once applies "EIT" request detection for other sources before
executing the instruction of the entry address, and this operation gets repeated.
At the time of "EIT" request detection, when all acceptable "EIT" sources have been exhausted, the CPU
executes the processing routine of the "EIT" request accepted in the end.
When the processing is returned from the processing routine of the last "EIT" request accepted using the
“RETI” instruction, the processing routine of the last but one "EIT" request is executed. When the
processing is returned from the processing routine of the first accepted "EIT" request using the "RETI"
instruction, the control returns to the user program after having processed a series of "EIT" processes.
Figure 4.6-1 shows an example of multiple "EIT" processing.
Figure 4.6-1 Example of Multiple "EIT" Processing
User program
Processing routine of NMI
Processing routine
of INT instruction
Priority level
(1) First executes
(High) NMI generated
(Low) NMI instruction executed
(2) Secondly executes
For example, if A, B, C are three "EIT" requests that have occurred simultaneously, and have been
accepted in the order of B, C, A, the execution of the processing routine will be in the order A, C, B.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.6
4.6.2
FR80 Family
Priority Levels of "EIT" Requests
The sequence of accepting each request and executing the corresponding processing routines when multiple
"EIT" request occur simultaneously, is decided by two factors - by the priority levels of "EIT" requests,
and, how other "EIT" requests are to be masked when one "EIT" request has been accepted.
At the time when an "EIT" request occurs, and at the time of completion of an "EIT" sequence, the
detection of "EIT" requests being generated at that time is performed, and which "EIT" request will be
accepted will be decided. At the time of completion of the "EIT" sequence, the detection of "EIT" requests
is carried out under the condition where masking has been done for the "EIT" sources other than the "EIT"
request accepted just a while back. Table 4.6-1 shows the priority levels of "EIT" requests and masking of
other sources.
Table 4.6-1 Priority Levels of "EIT" Requests & Masking of Other Sources
“EIT” request
priority level
Masking of other sources
Reset
1
Other sources discarded
Undefined-instruction exception
2
Cancelled
INT instruction
3
interrupt enable flag (I) = 0
INTE instruction
4
ILM=4
User interrupt
5
ILM= level of source accepted
NMI
6
ILM=15
Step trace trap
7
ILM=4, NMI and user interrupts are disabled
There are times when the value of interrupt level mask register (ILM) gets modified due to the "EIT"
request accepted earlier and the other "EIT" sources occurring simultaneously get masked and cannot be
accepted. In such a case, until the processing routine of "EIT" sources that have occurred simultaneously
have been executed and the control has returned to the user program, the user interrupt is suspended and is
re-detected at the time of resumption of the user program.
Table 4.6-2 shows the sequence of execution of processing routines of "EIT" requests in relation to priority
levels and masking of other sources.
Table 4.6-2 Sequence of Execution of Processing Routines of "EIT" Requests
"EIT" Sources
Execution sequence of processing routines
50
1
Reset
2
Undefined-instruction exception
3
INTE instruction
4
Step trace trap
5
NMI
6
INT instruction
7
User interrupt
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.7
FR80 Family
4.7
Timing When Register Settings Are Reflected
The timing when the new values are reflected after the interrupt enable flag (I) of
program status (PS) and the value of interrupt level mask register (ILM) are modified will
be explained in this section.
4.7.1
Timing when the interrupt enable flag (I) is requested
The interrupt request (enable/disable) is reflected from the instruction next to the next of the instruction
which modifies the value of interrupt enable flag (I). For proper functioning of the user interrupt, NOP
instruction should be placed after the instruction that modifies the interrupt enable flag (I).
Figure 4.7-1 shows the timing of reflection of the interrupt enable flag (I) when interrupt enable is set to
(I=1), and Figure 4.7-2 shows the timing of reflection of the interrupt enable flag (I) when interrupt disable
is set to (I=0).
Figure 4.7-1 Timing of reflection of interrupt enable flag (I) when interrupt enable is set to (I=1)
Instruction
execution
I flag
Interrupt
ORCCR #10H
0
Disable
NOP
1
Disable
Instruction A
1
Enable
Interrupt enabled from here
Figure 4.7-2 Timing of reflection of interrupt enable flag (I) when interrupt disable is set to (I=0)
Instruction
execution
I flag
Interrupt
ANDCCR #EFH
1
Enable
NOP
0
Enable
Instruction A
0
Disable
Interrupt disabled from here
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.7
4.7.2
FR80 Family
Timing of Reflection of Interrupt Level Mask Register
(ILM)
Acceptance to interrupt request is reflected from the instruction next to next to the instruction which
modifies the value of interrupt level mask register (ILM). For proper functioning of the interrupt, “NOP”
instruction is placed after the instruction that modifies the interrupt level mask register (ILM).
Figure 4.7-3 shows the timing of reflection when the interrupt level mask register (ILM) is modified.
Figure 4.7-3 Timing of reflection when the Interrupt level mask register (ILM) is modified
Instruction
execution
ILM
Interrupt
reception
STILM #set_ILM_B
A
A
NOP
B
A
Instruction C
B
B
Instruction D
B
B
ILM reflected from here
"set_ILM_B" is a value of the interrupt level mask register (ILM) to be newly assigned. As in the case of
STILM #30, assign a numeric value of 0 to 31.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.8
FR80 Family
4.8
Usage Sequence of User Interrupts
User interrupts accept interrupt requests from in-built peripheral functions and external
terminals, and perform "EIT" processing. The general points of caution of programming
while using user interrupts have been described here. Refer to the hardware manual of
various models as the detailed procedure differs as per the peripheral function.
4.8.1
Preparation while using user interrupts
Before using user interrupts, settings for "EIT" processing need to be made. Perform the following settings
in the program beforehand.
• Set values in the vector table (defined as data)
• Set up the system stack pointer (SSP) values
• Set up the table base register (TBR) value as the initial address in the vector table
• Set a value of above 16(10000B) in the interrupt level mask register (ILM)
• Set the value of "1" in the interrupt enable flag (I)
After the above settings, the settings of the peripheral functions are performed. In case of peripheral
functions which use user interrupts, two bits in the register of the peripheral functions require to be set - a
flag bit that indicates that a phenomenon which can become an interrupt source has occurred, and an
interrupt enable bit which uses this flag bit to enable or disable the interrupt request.
The peripheral function verifies the operation halt status, the disable of interrupt request, and that the flag
bit has been cleared. This state is achieved following a reset.
In case the peripheral function is engaged in some operation, the interrupt request is disabled and the flag
bit cleared after the operation of the peripheral function has been halted.
The interrupt level is set in the interrupt control register (ICR) of the interrupt controller. As multiple
interrupt control registers (ICR) are available corresponding to various vector numbers in the, please set an
interrupt control register (ICR) corresponding to the vector number of the interrupt begin used.
The operation of the peripheral function is resumed after clearing the flag bit and enabling the interrupt
request.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.8
4.8.2
FR80 Family
Processing during an Interrupt Processing Routine
After the interrupt request for a user interrupt has been accepted in the CPU as "EIT" following its
generation, the control moves to the interrupt processing routine after the execution of the "EIT" sequence.
Vector numbers are assigned to each source of user interrupts, and the interrupt processing routine
corresponding to these vector numbers are started. The interrupt sources and vector numbers do not
necessarily have a one-to-one correspondence, and at times the same vector number is assigned to multiple
interrupt sources. In such a case, the same interrupt processing routine is used for multiple interrupt
sources.
Right in the beginning of the interrupt processing routine, the flag bit which indicates an interrupt source is
verified. If the flag bit has been set, interrupt request for that interrupt is generated and the required
processing (program) is executed after clearing the flag bit. In case, the same vector offset is being used for
multiple interrupt sources, there are multiple flag bits indicating interrupt sources, and each of them are
identified and processed in the same manner.
It is necessary to clear the flag bit while the interrupt of that particular interrupt source is in the disabled
state. When the interrupt processing routine is started after the execution of the "EIT" sequence, the
interrupt level of the user interrupt is stored in the interrupt level mask register (ILM) and the user interrupt
of that interrupt level is disabled. Make sure to clear the flag bit at the end of the interrupt processing
without modifying the interrupt level mask register (ILM).
The control is returned from the interrupt processing routine by the "RETI" instruction.
4.8.3
Points of Caution while using User Interrupts
The points of caution while using user interrupts have been described here.
Interrupt requests are enabled either when the corresponding flag bit has been cleared, or at the time of
clearing the flag bit. Enabling interrupt requests when the flag bit is in the set state, leads to the generation
of interrupt request immediately.
While enabling interrupt requests, do not clear flag bit besides the interrupt processing routine. Flag bit
should be cleared at the time of disabling interrupt request.
In case a flag bit is cleared when a peripheral function is performing an operation, there are times when the
flag bit cannot be cleared if the clearing of flag bit by writing to the register and the occurrence of a
phenomenon which can be an interrupt source take place simultaneously or at a very close interval.
Whether a flag bit will be cleared or not when the clearing of flag bit and the occurrence of a phenomenon
that can become an interrupt source take place simultaneously, differs from one peripheral function to the
other.
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CHAPTER 5
PIPELINE OPERATION
This chapter explains the chief characteristics of FR80
family CPU like pipeline operation, delayed branching
processing etc.
5.1 Instruction execution based on Pipeline
5.2 Pipeline Operation and Interrupt Processing
5.3 Register hazards
5.4 Non-block loading
5.5 Delayed branching processing
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CHAPTER 5 PIPELINE OPERATION
5.1
5.1
FR80 Family
Instruction execution based on Pipeline
FR80 Family CPU processes all instructions using a 5-stage pipeline operation. This
makes it possible to process to process nearly all instructions in one cycle. Normally,
FR80 Family CPU has a pipeline for memory loading in addition to instruction
execution.
Pipeline operation divides each type of step that carries out interpretation and execution of instructions of
CPU in to stages, and simultaneously executes different stages of each instruction. Instruction execution
that requires multiple cycles in other processing methods is apparently conducted in one cycle here. As
mentioned below, FR Family CPU uses 5-stage pipeline processing that simultaneously executes 5 types of
stages (IF, ID, EX, MA, WB).
• IF Stage: Load Instruction
Instruction address is generated and instruction is fetched.
• ID Stage: Interpret Instruction
Fetched instruction is decoded. Register reading is also carried out.
• EX Stage: Execute Instruction
Computation is executed.
• MA Stage: Memory Access
Loading or access to storage is executed against the memory.
• WB Stage: Write to register
Computation result (or loaded memory data) is written in the register.
Due to additional packaging of pipeline for memory loading, MA stage, WB stage of instructions that do
not carry out memory access, and MA stage, WB stage of Load instruction (LD instruction), can be
executed in an overlapping manner.
Example of FR80 Family CPU Pipeline operation (1) is shown in Figure 5.1-1 and Example of FR80
Family CPU Pipeline operation (2) is shown in Figure 5.1-2.
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CHAPTER 5 PIPELINE OPERATION
5.1
FR80 Family
Figure 5.1-1 Example of FR80 Family CPU Pipeline operation (1)
Example 1
LD
@R10, R1
LDI:8
#0x02, R2
CMP
R1, R2
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
BNE:D Label_G
ADD
#0x1, R1
WB
In principle, execution of instructions is carried out at a speed of one instruction per cycle. However,
multiple cycles are necessary for the execution of instruction in case of load store instruction accompanied
by memory wait, non-delayed branching instruction, and multiple cycle instruction. The speed of
instruction execution is also reduced in cases where there is a delay in the supply of instructions, such as
internal conflict of bus in the CPU, instruction execution through external bus interface etc.
Normally, instructions are executed sequentially in the instruction effective pipeline. For example, if
instruction A enters the pipeline before instruction B, it invariably reaches WB stage before instruction B.
However, when the register used in Load instruction (LD instruction) is not used in the subsequent
instruction, the subsequent instruction is executed before the completion of execution of load instruction
based on pipeline for memory load.
Figure 5.1-2 Example of FR80 Family CPU Pipeline operation (2)
Example 2
LD
@R10, R1
LDI:8
#0x02, R2
CMP
R1, R2
BNE:D Label_G
ADD
#0x1, R1
IF
ID
IF
EX
MA
MA
MA
WB
ID
EX
MA
WB
IF
ID
ID
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
MA stage is prolonged in case of Load instruction (LD instruction) till the completion of reading of the
loaded data. However, the subsequent instruction is executed as it is, if the register used in the load
instruction is not used in the subsequent instruction.
In the Example given in Figure 5.1-1, loading is carried out in R1 (load value is written in R1) based on
preceding LD instruction, and R1 contents are referred to in the subsequent CMP instruction. Since the
loaded data returns in 1 cycle, execution of instructions is sequential.
Similarly in the Example given in Figure 5.1-2, R1 that writes load value with LD instruction is used in the
CMP instruction. Since the loaded data does not return in 1 cycle, execution till LDI:8 instruction is carried
out and CMP instruction is made to wait at the ID stage by register hazard.
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CHAPTER 5 PIPELINE OPERATION
5.2
5.2
FR80 Family
Pipeline Operation and Interrupt Processing
It is possible at times that an event wherein it appears that interrupt request is lost after
acceptance of interrupt, if the flag that causes interrupt in the interrupt-enabled
condition, because pipeline operation is conducted, occurs.
5.2.1
Mismatch in Acceptance and Cancellation of Interrupt
Because FR80 Family CPU is carrying out pipeline processing, pipeline processing of multiple instructions
is already executed at the time of acceptance of interrupt. Therefore, in case corresponding interrupt
cancellation processing among the instructions under execution in the pipeline (For example, clearing of
flag bits that cause interrupt) is carried out, branching to corresponding interrupt processing program is
carried out normally but when control is transferred to interrupt processing, the interrupt request is at times
already over (Flag bits that cause interrupt having been cleared).
An Example of Mismatch in Acceptance and cancellation of interrupt is shown is Figure 5.2-1.
Figure 5.2-1 Example of Mismatch in Acceptance and Cancellation of interrupt
Interrupt request
None None None None Generated Cancel None None None
LD @R10, R1
IF
ST R2, @R11
ADD R1, R3(cancelled)
BNE TestOK(cancelled)
EIT sequence execution #1
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
--
--
--
IF
--
--
--
--
IF
ID
EX
MA
WB
--: Canceled stages
This type of phenomenon does not occur in case of exceptions and trap, because the operation for request
cancellation cannot be carried out in the program.
5.2.2
How to prevent mismatched pipeline conditions?
Mismatch in Acceptance and Deletion of interrupt can occur in case flag bits that cause interrupt are
cleared while interrupt request is enabled in the peripheral functions.
To avoid such a phenomenon, programmers should set the interrupt enable flag (I) at "0", disable interrupt
acceptance in CPU and clear the flag bits that cause an interrupt.
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CHAPTER 5 PIPELINE OPERATION
5.3
FR80 Family
5.3
Register hazards
The FR80 Family CPU executes program steps in the order in which they are written and
is therefore equipped with a function that detects the occurrence of register hazards
and stops pipeline processing when necessary.
5.3.1
Occurrence of register hazard
The CPU in pipeline operation may simultaneously process one instruction that involves writing values to a
register, and a subsequent instruction that attempts to refer to the same register before the write process is
completed. This is called register hazard.
In the example of Register Hazard in Figure 5.3-1, the program will read the address value at "R1" before
the desired value has been written to "R1" by the previous instruction. As a result the old value at "R1" will
be read instead of the new value. (However, register hazard is actually averted and new value is read).
Figure 5.3-1 Example of a register hazard
IF
ADD R0, R1
SUB R1, R2
5.3.2
ID
EX
MA
WB
IF
ID
EX
MA
: Write cycle to R1
WB
: Read cycle from R1
Register Bypassing
Even when a register hazard does occur, it is possible to process instructions without operating delays if the
data intended for the register to be accessed can be extricated from the preceding instruction. This type of
data transfer processing is called register bypassing and the FR80 Family CPU is equipped with a register
bypassing function.
An example of Register Bypassing is indicated in Figure 5.3-2. In this example, instead of reading the
"R1" in the "ID" stage of "SUB" instruction, the program uses the results of the calculation from "ADD"
instruction (before the results are written to the register) and thus executes the instruction without delay.
Figure 5.3-2 Example of a register bypass
ADD R0, R1
SUB R1, R2
CM71-00104-3E
IF
ID
EX
MA
WB
IF
ID
EX
MA
: Data calculation cycle to R1
WB
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: Read cycle from R1
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CHAPTER 5 PIPELINE OPERATION
5.3
5.3.3
FR80 Family
Interlocking
Instructions that are relatively slow in loading data to the CPU may cause register hazards that cannot be
handled by register bypassing.
In the example Figure 5.3-3, data required for the "ID" stage of the "SUB" instruction must be loaded to the
CPU in the "MA" stage of the "LD" instruction, creating a hazard that cannot be avoided by the bypass
function.
Figure 5.3-3 Example: Register Hazard that cannot be avoided by Bypassing
IF
LD @R0, R1
SUB R1, R2
ID
EX
MA
WB
IF
ID
EX
MA
: Data read cycle to R0
WB
: Read cycle from R1
In cases such as this, FR80 Family CPU executes the instruction correctly by pausing before the execution
of subsequent instruction. This function is called interlocking.
In the example in Figure 5.3-4, the "ID" stage of the "SUB" instruction is delayed until the data is loaded
from the "MA" stage of the "LD" instruction.
Figure 5.3-4 Example of Interlocking
LD @R0, R1
SUB R1, R2
5.3.4
IF
ID
EX
MA
WB
IF
ID
ID
EX
: Data read cycle to R0
MA
WB
: Read cycle from R1
Interlocking produced by after Changing the Stack flag
(S)
The general purpose register "R15" is designed to function as either the system stack pointer (SSP) or user
stack pointer (USP). For this reason the FR Family CPU is designed to automatically generate an interlock
whenever a change to the "S" flag in the condition code register (CCR) in the program status (PS) is
followed immediately by an instruction that references the "R15". This interlock enables the CPU to
reference the "SSP" or "USP" values in the order in which they are written in the program.
FR family hardware design similarly generates an interlock whenever a TYPE-A format instruction
immediately follows an instruction that changes the value of Stack flag (S).
For information on instruction formats, see Section "6.2.3 Instruction Formats".
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5.4
FR80 Family
5.4
Non-block loading
Non-block loading is carried out in FR80 Family CPU. A maximum of 4 loading instructions
can be issued with precedence.
In non-block loading, the subsequent instruction is executed without waiting for the completion of loading
instruction, if the general-purpose register in which the load instruction value is stored is not referred in the
subsequent instruction.
As shown below, when register "R1" that stores data value based on LD instruction is referred to in the
subsequent ADD instruction, the ADD instruction is executed after storing R1 value based on LD
instruction.
LD
@10,R1
ADD
R1,R2
; waits for completion of execution of preceding LD instruction
As shown below, ADD instruction is executed without waiting for the completion of execution of LD
instruction when "R1" that stores data value by LD instruction is not referred to in the subsequent ADD
instruction. After that, at the time of execution of SUB instruction that references "R1", if the preceding LD
instruction is not already executed, the SUB instruction is executed after waiting for the completion of
execution of that LD instruction.
LD
@10,R1
ADD
R2,R3
; Does not wait for completion of execution of preceding LD instruction
SUB
R1,R3
; waits for completion of execution of preceding LD instruction
A maximum of 4 load instructions can be executed with precedence. It can also be used in the following
way for issuing multiple LD instructions with precedence.
CM71-00104-3E
LD
@100,R1 ; LD instruction (1)
LD
@104,R2
LD
@108,R3
LD
@112,R4 ; a maximum of 4 LD instructions can be issued with precedence
ADD
R5,R6
SUB
R6,R0
ADD
R1,R5
; executed without waiting for the completion of execution of preceding LD
instruction
; executed after completion of execution of preceding LD instruction (1)
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5.5
5.5
FR80 Family
Delayed branching processing
Because FR80 Family CPU features pipeline operation, the loading of the instruction is
already completed at the time of execution of branching instruction. Delayed branching
processing is the function to execute the loaded instruction, and allows acceleration of
processing speeds.
5.5.1
Example of branching with non-delayed branching
instructions
Non-delayed branching instruction executes instructions in the order of program but the execution speed
drops down by 1 cycle as compared to delayed branching instruction when branching.
In a pipeline operation, by the time the CPU recognizes an instruction as a branching instruction the next
instruction has already been loaded. To process the program as written, the instruction following the
branching instruction must be cancelled in the middle of execution. Branching instructions that are handled
in this manner are non-delayed branching instructions.
The example of processing non-delayed branching instruction with fulfilled branching conditions is given
in Figure 5.5-1 which shows that execution of the "ST R2,@R12" instruction (instruction placed
immediately after branching instruction) that had started pipeline operation before fetching instruction from
the branching destination is cancelled in the middle. Due to this, program processing happens as the
program is written, but branching instruction apparently takes 2 cycles for completion.
Figure 5.5-1 Example of processing of Non-Delayed Branching instruction
(Branching conditions satisfied)
LD @R10, R1
LD @R11, R2
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
--
--
--
--
IF
ID
EX
MA
ADD R1, R3
ST R2, @R12(instruction immediately after)
ST R2, @R13(branch destination instruction)
WB
-- : Canceled stages
: PC change
Figure 5.5-2 shows an example of processing a non-delayed branching instruction when branching
conditions are not fulfilled. In this example, the "ST R2,@R12" instruction (instruction kept immediately
after branching instruction) that started pipeline processing before fetching instruction from the branching
destination is executed without being cancelled. The processing of program happens as written in the
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5.5
FR80 Family
program since the instructions are executed sequentially, without branching, and branching instruction
execution speed is apparently of 1 cycle.
Figure 5.5-2 Example of processing of Non-Delayed Branching instruction (Branching conditions not satisfied)
LD @R10, R1
IF
LD @R11, R2
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
Not canceled
IF
ID
EX
MA
WB
ADD R1, R3
ST R2, @R12(instruction immediately after)
ADD #4, R12(subsequent instruction)
5.5.2
Example of processing of delayed branching instruction
Delayed branching instructions are processed with an apparent execution speed of 1 cycle, regardless of
whether or not branching conditions are satisfied. When branching occurs, this is one cycle faster than
using non-delayed branching instructions. However, the apparent order of instruction processing is inverted
in cases where branching occurs.
An instruction immediately following a branching instruction will already be loaded by the CPU by the
time the branching instruction is executed. This position is called the delay slot. A delayed branching
instruction is a branching instruction that executes the instruction in the delay slot regardless of whether or
not branching conditions are satisfied.
Figure 5.5-3 shows an example of processing a delayed branching instruction when branching conditions
are satisfied. In this example, the branch destination instruction "ST R2,@R13" is executed after the
instruction "ST R2,@R12" in the delay slot. As a result, the branching instruction has an apparent
execution speed of 1 cycle. However, the instruction "ST R2,@R12" in the delay slot is executed before
the branch destination instruction "ST R2,@R13" and therefore the apparent order of processing is
inverted.
Figure 5.5-3 Example of processing of Delayed Branching instruction (Branching conditions satisfied)
LD @R10, R1
IF
LD @R11, R2
ADD R1, R3
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
Not canceled
IF
ID
EX
MA
WB
ST R2, @R12(delay slot instruction)
ST R2, @R13(branch destination instruction)
: PC update
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5.5
FR80 Family
Figure 5.5-4 shows an example of processing a delayed branching instruction when branching conditions
are not satisfied. In this example, the instruction "ST R2,@R12" in delay slot is executed without being
cancelled. As a result, the program is processed in the order in which it is written. The branching
instruction requires an apparent processing time of 1 cycle.
Figure 5.5-4 Example of processing of Delayed Branching instruction (Branching conditions not satisfied)
LD @R10, R1
IF
LD @R11, R2
ADD R1, R3
BNE:D TestOK (br
ST R2, @R12 (delay slot instruction)
ADD #4, R12
64
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
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Not canceled
WB
CM71-00104-3E
CHAPTER 6
INSTRUCTION OVERVIEW
This chapter presents an overview of the instructions
used with the FR80 Family CPU.
6.1 Instruction System
6.2 Instructions Formats
6.3 Data Format
6.4 Read-Modify-Write type Instructions
6.5 Branching Instructions and Delay Slot
6.6 Step Division Instructions
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CHAPTER 6 INSTRUCTION OVERVIEW
6.1
6.1
FR80 Family
Instruction System
FR80 Family CPU, in addition to Instruction System of General RISC CPU, is also
compatible with logical operation optimized for embedded use, bit operation and direct
addressing instructions.
Each instruction has a length of 16-bit (Some Immediate Data Transfer Instructions are 32-bit or48-bit length) realizing high
memory efficiency.
Instructions of FR80 Family CPU can be divided into the following 15 groups.
● Add/Subtract Instructions
These are the Instructions to carry out addition and subtraction between general-purpose registers or a
general-purpose register and immediate data. They also enable computation with carry used in multi-word
long computation or computations where flag value of Condition Code Register (CCR) convenient for
address calculation is not changed.
● Compare Instructions
These are the Instructions to carry out subtraction between general-purpose registers or a general-purpose
register and immediate data and reflect the results in the flag of Condition Code Register (CCR).
● Logical Calculation Instructions
These are the Instructions to carry out logical calculation for each bit between general-purpose registers or
a general-purpose register and memory (including I/O). Logical calculation types are logical product
(AND), logical sum (OR), and exclusive logical sum (EXOR). Memory addressing is register indirect.
● Bit Operation Instructions
These are the Instructions to carry out logical calculation between memory (including I/O) and immediate
value and operate directly for each bit. Logical calculation types are logical product (AND), logical sum
(OR), and exclusive logical sum (EXOR). Memory addressing is register indirect.
● Multiple/Divide Instructions
These are the instructions to carry out multiplication and division between general-purpose register and
multiplication/division result register. There are 32 bit × 32 bit, 16 bit × 16 bit multiplication instructions
and step division instructions to carry out 32 bit ÷ 32 bit division.
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FR80 Family
● Shift Instructions
These are the instructions to carry out shift (logical shift, arithmetic shift) of general-purpose registers. By
specifying general-purpose register or immediate data, shift (Barrel Shift) of multiple bits can be specified
at once.
● Immediate Data Transfer Instructions
These are the instructions to transfer immediate data to general-purpose registers and can transfer
immediate data of 8bit, 20 bit, and 32 bit.
● Memory Load Instructions
These are the instructions to load from memory (including I/O) to general-purpose registers or dedicated
registers. They can transfer data length of 3 types namely, bytes, half-words and words and memory
addressing is register indirect.
During memory addressing of some Instructions, Displacement Register Indirect or Increment/Decrement
Register Indirect Address is possible.
● Memory Store Instructions
These are the instructions to store from general-purpose register or dedicated register to memory (Including
I/O). They can transfer data length of 3 types namely, bytes, half-words and words and memory addressing
is register indirect.
During memory addressing of some Instructions, Displacement Register Indirect or Increment/Decrement
Register Indirect Address is possible.
● Inter-register Transfer Instructions/Dedicated Register Transfer Instructions
These are the instructions to transfer data between general-purpose registers or a general-purpose register
and dedicated register.
● Non-delayed Branching Instructions
These are the instructions that do not have delay slot and carry out branching, sub-routine call, interrupt and
return.
● Delayed Branching Instructions
These are the instructions that have delay slot and carry out branching, sub-routine call, interrupt and
return. Delay slot instructions are executed when branching.
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6.1
FR80 Family
● Direct Addressing Instructions
These are the instructions to transfer data between general-purpose register and memory (Including I/O) or
between two memories. Addressing is not register indirect but direct specification with operand of
instruction.
In some instructions, in combination with specific general-purpose registers, access is made in combination
with increment/decrement Register Indirect addressing.
● Bit Search Instructions
These are the instructions that have been added to FR80 Family CPU. They search 32-bit data of generalpurpose register from MSB and obtain the first 1 bit, 0 bit and bit position of change point (distance of bit
from MSB).
They correspond to bit search module packaged in the family prior to FR80 Family (FR30Family, FR60
Family etc.) as peripheral function.
● Other Instructions
These are the instructions to carry out flag setting, stack operation, sign/zero extension etc. of Program
Status (PS). There are also high-level language compatible Enter Function/Leave Function, Register Multi
load/store Instructions.
See "A.2 Instruction Lists" to know about the groups and types of Instructions.
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6.2
FR80 Family
6.2
Instructions Formats
This section describes about Instruction Formats of FR80 Family CPU.
6.2.1
Instructions Notation Formats
FR80 Family CPU is 2 operand format. There are 3 types of Instruction notation formats depending on the
number of operands. Instruction notation formats are as follows.
<Mnemonic> <Operand 1> <Operand 2>
Mnemonic calculations are carried out between operand 2 and operand 1 and the results are stored at
operand 2.
Ex:
ADD
R1,R2
; R2 + R1 -> R2
<Mnemonic> <Operand 1>
Operations are designated by a mnemonic and use operand 1.
Ex:
JMP
@R1
; R1 -> PC
<Mnemonic>
Operations are designated by a mnemonic.
Ex:
NOP
; No Operation
Operands have general-purpose register, dedicated register, immediate data and combinations of part of
general-purpose register and immediate data. Operand format varies depending on Instruction.
6.2.2
Addressing Formats
There are several methods for address specification when accessing memory in the memory space or I/O
register. Addressing format varies depending on Instruction.
@General-purpose Registers
It is Register Indirect Addressing. Address indicated by the content of the general-purpose register is
accessed.
@(R13, General-purpose Register)
Address where virtual accumulator (R13) and contents of general-purpose register are added is
accessed.
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6.2
FR80 Family
@(R14,Immediate Data)
Address where contents of Frame Pointer (R14) and immediate data are added is accessed.
Immediate data is specified in the multiples of data size (word, half word, byte).
@(R15, Immediate Data)
Address where contents of Stack Pointer (R15) and immediate data are added is accessed.
Immediate data is specified in the multiples of data size (word, half word, byte).
@R15+
Write access to the address indicated by the contents of Stack Pointer (R15) is made. 4 will be added
to the stack pointer (R15).
@-R15
Read access to the address which is deduction of 4 from the contents of Stack Pointer (R15) is made.
4 will be deducted from the Stack Pointer (R15).
@ Immediate Data
It is direct addressing. Address indicated by immediate data is accessed.
@R13+
Access to address indicated by the contents of virtual accumulator (R13) is made. Data size (Bytes)
will get added to virtual accumulator (R13).
6.2.3
Instruction Formats
The instruction of FR80 family CPU is 16-bit length (The forwarding part of immediate data instruction is
32-bit or 48-bit length). Bit configuration of Instructions varies depending on configuration of operands of
Instructions. Bit configuration of Instructions classified into groups is called Instruction Formats.
There are 8 types of Instructions Formats TYPE-A through TYPE-H.
TYPE-A
It has 8-bit OP Code (OP) and two Register designated fields (Rj/Rs,Ri)
MSB
LSB
OP
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Ri
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CHAPTER 6 INSTRUCTION OVERVIEW
6.2
FR80 Family
TYPE-B
It has 4-bit OP Code (OP) and 8-bit immediate data fields (i8/o8), register designated field (Ri)
MSB
LSB
OP
i8/o8
Ri
TYPE-C
It has 8-bit OP Code (OP) and 4-bit immediate data fields (u4/m4/i4), register designated field (Ri)
MSB
LSB
OP
u4/m4/i4
Ri
TYPE-D
It has 8-bit OP Code (OP) and 8-bit immediate data field (u8) or address designated field (rel8/dir8).
In some instructions, it is 8-bit register list designated field (reglist).
MSB
LSB
OP
u8/rel8/dir8/reglist
TYPE-E
It has 12-bit OP Codes (OP, SUB-OP) and register designated fields (Ri/Rs).
MSB
LSB
OP
SUB-OP
Ri/Rs
TYPE-E’
It is deformation of TYPE-E. It has 12-bit OP Code (OP, SUB-OP). TYPE-E register designated
field is fixed to 0000B. It is applied for instructions where 16-bit instruction code such as NOP
Instruction or RET Instructions etc. is defined.
MSB
LSB
OP
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SUB-OP
0
0
0
0
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CHAPTER 6 INSTRUCTION OVERVIEW
6.2
FR80 Family
TYPE-F
It has 5-bit OP Code (OP) and 11-bit address designated filed (rel11).
MSB
LSB
OP
rel11
TYPE-G
It has 8-bit OP code (OP) and 20bit immediate data field (i20), register designated field (Ri). It has
32-bit length and is applied only for LDI:20 Instruction.
MSB
(n+0)
LSB
OP
(n+2)
i20 (Upper)
Ri
i20 (Lower)
TYPE-H
It has 12bit OP code (OP) and 32bit immediate data field (i32), register designated field (Ri). It has
48-bit length and is applied only for LDI:32 Instruction.
MSB
(n+0)
72
LSB
OP
SUB-OP
(n+2)
i32 (Upper}
(n+4)
i32 (Lower)
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CHAPTER 6 INSTRUCTION OVERVIEW
6.2
FR80 Family
6.2.4
Register designated Field
Among Instruction formats, fields that designate general-purpose register are 4bit length Ri and Rj.
Relation between bit pattern of general purpose register and register designated field has been indicated in
Table 6.2-1.
Table 6.2-1 Bit pattern of general purpose register and register designated field
Ri / Rj
Register
Ri / Rj
Register
0000
R0
1000
R8
0001
R1
1001
R9
0010
R2
1010
R10
0011
R3
1011
R11
0100
R4
1100
R12
0101
R5
1101
R13
0110
R6
1110
R14
0111
R7
1111
R15
Among Instruction formats, field that designates dedicated register is 4bit length Rs. Relation between bit
pattern of dedicated register and register designated field has been indicated in Table 6.2-2.
Table 6.2-2 Bit pattern of dedicated register and register designated field
Rs
Register
Rs
0000
Table Base Register (TBR)
1000
0001
Return Pointer (RP)
1001
0010
System Stack Pointer (SSP)
1010
0011
User Stack Pointer (USP)
1011
0100
Multiply/Divide Register (MDH)
1100
0101
Multiply/Divide Register (MDL)
1101
Register
Reserved
0110
1110
Reserved
0111
1111
Bit pattern which is shown as "Reserved" in the field that designates dedicated register is the reserved
pattern. Operation when reserved pattern is specified is not covered by the warranty.
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CHAPTER 6 INSTRUCTION OVERVIEW
6.3
6.3
FR80 Family
Data Format
This section describes the data type and format supported by FR80 Family CPU.
6.3.1
Data Format Used by Integer Type Instructions (Common
with All FR Family)
● Signed integer byte
Signed integer byte is represented as consecutive 8 bits. Bit 7 represents the sign bit (S), and "0" represents
positive or zero and "1" represents negative.
MSB
7
6
LSB
0
S
● Unsigned integer byte
Unsigned integer byte is represented as consecutive 8 bits.
MSB
7
LSB
0
● Signed integer half word
Signed integer half word is represented as consecutive 16 bits. Bit 15 represents the sign bit (S), and "0"
represents positive or zero and "1" represents negative.
MSB
15
14
LSB
0
S
● Unsigned integer half word
Unsigned integer half word is represented as consecutive 16 bits.
MSB
15
LSB
0
● Signed integer word
Signed integer word is represented as consecutive 32 bits. Bit 31 represents the sign bit (S), and "0"
represents positive or zero and "1" represents negative.
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6.3
FR80 Family
MSB
31
LSB
0
30
S
● Unsigned integer word
Unsigned integer word is represented as consecutive 32 bits.
MSB
31
CM71-00104-3E
LSB
0
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CHAPTER 6 INSTRUCTION OVERVIEW
6.4
6.4
FR80 Family
Read-Modify-Write type Instructions
Read-Modify-Write type Instructions are those that carry out a series of operations
namely, arithmetic processing in the data read from the memory space and write the
result in the same address of the memory space.
IN registers of peripheral functions (I/O Registers), there are bits whose read values are different depending
on instructions that independently carry out read access like LD Instruction and Read-Modify-Write type
Instructions. Such bits have been described in the explanation on registers (I/O Registers) of peripheral
functions.
In case of Read-Modify-Write type Instructions, a different instruction based on EIT processing is not
executed between Read access and Write access of one instruction. This is used for exclusive control that
uses flag or semaphore between programs.
Whether or not an instruction is Read-Modify-Write system Instruction is defined for each instruction. See
"CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS".
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CHAPTER 6 INSTRUCTION OVERVIEW
6.5
FR80 Family
6.5
Branching Instructions and Delay Slot
FR80 Family CPU Branching Instructions are of two types namely, Delayed Branching
Instructions and Non-delayed Branching Instructions.
6.5.1
Delayed Branching Instructions
In case of Delayed Branching Instructions, prior to execution of Branching Destination Instructions,
instructions immediately after Branching Instructions are executed. Instructions immediately after Delayed
Branching Instructions are called Delay slot.
Branching Instructions having ":D" affixed to mnemonic are Delayed Branching Instructions. Next
Instruction will be Delayed Branching Instruction.
JMP:D
@Ri
CALL:D
label12
CALL:D
@Ri
RET:D
BRA:D
label9
BNO:D
label9
BEQ:D
label9
BNE:D
label9
BC:D
label9
BNC:D
label9
BN:D
label9
BP:D
label9
BV:D
label9
BNV:D
label9
BLT:D
label9
BGE:D
label9
BLE:D
label9
BGT:D
label9
BLS:D
label9
BHI:D
label9
Since Delay Slot instructions are executed prior to Branching operation, apparent execution cycle of
Branching Instruction will be 1 cycle. In case a valid instruction cannot be allocated in the Delay slot, it is
necessary to allocate NOP Instruction. Example of Delayed Branching Instruction has been given below.
;
Instructions alignment
ADD
R1,R2
BRA:D
LABEL
; Branching Instructions
MOV
R2,R3
; Delay slot (Executed before Branching)
R3,@R4
; Branching Destination
...
LABEL:
ST
In case of Conditional Branching Instruction, whether or not Branching conditions are established, Delay
slot instructions are executed.
Instructions that can be placed in the Delay slot are only those that satisfy following conditions.
• 1 cycle Instructions
• Those that are not Branching Instructions
• Instructions that do not affect the operation even when the order is changed
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6.5
FR80 Family
1 cycle Instructions are those where anyone variable namely 1, a, b, c, d is independently written in the
CYC Column of "A.2 Instruction Lists". (Instructions which have 2a or 1+b are not 1 cycle instructions).
For a list of instructions that can be placed in Delay Slot, see "A.3 List of Instructions that can be positioned
in the Delay Slot".
EIT processing such as Step Trace Trap, user interrupt, NMI etc. cannot be accepted between Delayed
Branching Instructions and Delay Slot Instructions. In case Delay Slot Instructions are undefined
Instructions, undefined instruction exceptions do not occur and undefined instructions operate as NOP
Instructions.
6.5.2
Specific example of Delayed Branching Instructions
Specific example of Delayed Branching Instruction is given below.
JMP:D @Ri Instruction, CALL:D @Ri Instruction
General-purpose register Ri referred to during JMP:D Instruction, CALL:D Instruction is not affected
by the Branching Destination Address even if Delay Slot Instruction updates Ri.
[Example]
LDI:32
#Label,R0
JMP:D
@R0
; Branching in Label
LDI:8
#0,R0
; Does not affect Branching Destination Address
...
RET:D Instruction
Return Pointer (RP) referred to by RET:D Instruction is not affected even if Delay Slot Instruction
updates the Return Pointer (RP).
[Example]
RET:D
MOV
; Branching to address indicated by RP set prior to this
R8,RP
; Not affected by Return Operation
...
Bcc:D label9 Instructions
Flag of Condition Code Register (CCR) referred to by Bcc:D Instruction is not affected by Delay Slot
Instructions.
[Example]
78
ADD
#1,R0
; Flag change
BC:D
overflow
; Branching based on execution result of preceding ADD Instruction
ANDCCR
#0
; Updating of this flag does not affect Branching
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6.5
FR80 Family
CALL:D Instruction
If Return Pointer (RP) is referred to based on Delay Slot Instruction of CALL:D Instruction, updated
content will be read based on CALL:D Instruction.
[Example]
6.5.3
CALL:D
Label
; Branching after updating of RP
MOV
RP,R0
; Execution result of RP of preceding CALL:D Instruction is transferred to
R0
Non-Delayed Branching Instructions
In case of Non-Delayed Branching Instructions, execution is carried out in the sequence of Instructions.
Instruction immediately after Branching Instruction is never executed before branching.
Branching Instructions without ":D" in mnemonic are Non-Delayed Branching Instructions. Next
instruction will be Non-Delayed Branching Instruction.
JMP
@Ri
CALL
label12
CALL
@Ri
RET
BRA
label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE
label9
BGT
label9
BLS
label9
BHI
label9
Execution cycles of Non-Delayed Branching Instruction will be 2 cycles when Branching and 1 cycle when
not branching. Example of Non-Delayed Branching Instruction is given below.
;
Sequence of Instructions
ADD
R1,R2
BRA
LABEL
; Branching Instruction
MOV
R2,R3
; Not executed
R3,@R4
; Branching Destination
...
LABEL:
ST
Compared to Delayed Branching Instructions where NOP Instruction is placed in the Delay Slot, efficiency
of instruction code can be increased. Execution speed and Code Efficiency both can be realized by using
Delayed Branching Instruction when valid instruction can be placed in the Delay Slot and using Nondelayed Branching Instruction otherwise.
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CHAPTER 6 INSTRUCTION OVERVIEW
6.6
6.6
FR80 Family
Step Division Instructions
In FR80 Family CPU, 32-bit signed/unsigned division is carried out based on combination
of Step Division Instructions.
Step Division Instructions are of following types.
• DIV0S (Initial Setting Up for Signed Division)
• DIV0U (Initial Setting Up for Unsigned Division)
• DIV1 (Main Process of Division)
• DIV2 (Correction When Remain is 0)
• DIV3 (Correction When Remain is 0)
• DIV4S (Correction Answer for Signed Division)
In order to realize signed division, combine the Instructions as follows.
DIV0S, DIV1 × 32, DIV2, DIV3, DIV4S
In order to realize unsigned division, combine the Instructions as follows.
DIV0U, DIV1 × 32
For various Instructions, see "CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS".
6.6.1
Signed Division
Signed 32bit dividend is divided with signed 32 bit divisor and quotient of signed 32 bit and remainder of
signed 32bit are obtained.
Before carrying out division, dividend and divisor are set in the following register.
• Multiplication/Division Register (MDL): Dividend of signed 32 bit (Dividend)
• One of general-purpose registers: Divisor of signed 32 bit (Divisor)
Signed division is carried out by executing following 36 Instructions. DIV1 Instructions 32 numbers are
arranged after DIV0S Instructions. In the operand of DIV0S Instructions, DIV1 Instructions, DIV2
Instructions general-purpose registers that store divisor are specified.
DIV0S
R2
; Divisor in R2
DIV1
R2
; #1
DIV1
R2
; #2
R2
; #30
...
DIV1
80
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CHAPTER 6 INSTRUCTION OVERVIEW
6.6
FR80 Family
DIV1
R2
; #31
DIV1
R2
; #32
DIV2
R2
DIV3
DIV4S
Division results are stored in the following registers.
• Multiplication/Division Register (MDL): quotient of signed 32 bit
• Multiplication/Division Register (MDH): remainder of signed 32 bit
Example of execution of signed division has been indicated in Figure 6.6-1.
Figure 6.6-1 Example of execution of signed division
R2
0 1 2 3 4 5 6 7
R2
0 1 2 3 4 5 6 7
MDH
× × × × × × × ×
MDH
F F F F F F F F
MDL
F E D C B A 9 8
MDL
F F F F F F F F
D1 D0 T
D1 D0 T
SCR
× × 0
SCR
Before execution
1 1 0
After execution
In SOFTUNE Assembler, DIV Instruction has been arranged to carry out signed division as Assembler
Pseudo Machine Instruction. Using this DIV Instruction in place of above mentioned 36 Instructions,
signed division can be described with 1 Instruction. See "FR family SOFTUNE Assembler Manual for V6"
for DIV Instruction.
6.6.2
Unsigned Division
Dividend of unsigned 32 bit dividend is divided with unsigned 32bit divisor and quotient of unsigned 32 bit
and remainder of unsigned 32 bit are obtained.
Before carrying out division, dividend and divisor are set in the following register.
• Multiplication/Division Register (MDL): Dividend of unsigned 32 bit (Dividend)
• One of general-purpose registers: Divisor of unsigned 32 bit (Divisor)
Unsigned division is carried out by executing following 33 Instructions. DIV1 Instructions 32 numbers are
arranged after DIV0U Instruction. In the operand of DIV0U Instructions, DIV1 Instructions, generalpurpose registers that store divisor are specified.
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CHAPTER 6 INSTRUCTION OVERVIEW
6.6
DIV0S
R2
; divisor in R2
DIV1
R2
; #1
DIV1
R2
; #2
DIV1
R2
; #30
DIV1
R2
; #31
DIV1
R2
; #32
FR80 Family
...
Division result is stored in the following registers.
• Multiplication/Division Register (MDL): quotient of unsigned 32 bit
• Multiplication/Division Register (MDH): remainder of unsigned 32 bit
Example of execution of unsigned division has been indicated in Figure 6.6-2.
Figure 6.6-2 Example of execution of unsigned division
R2
0 1 2 3 4 5 6 7
R2
0 1 2 3 4 5 6 7
MDH
× × × × × × × ×
MDH
0 0 0 0 0 0 7 8
MDL
F E D C B A 9 8
MDL
0 0 0 0 0 0 E 0
D1 D0 T
D1 D0 T
SCR
× × 0
SCR
Before execution
0 0 0
After execution
In SOFTUNE Assembler, DIV Instruction has been arranged to carry out unsigned division as Assembler
Pseudo Machine Instruction. Using this DIV Instruction in place of above mentioned 33 Instructions,
unsigned division can be described with 1 Instruction. See "FR family SOFTUNE Assembler Manual for
V6" for DIV Instruction.
82
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CHAPTER 7
DETAILED EXECUTION
INSTRUCTIONS
This chapter explains each of the execution instructions
used by the FR80 Family CPU, alphabetically in the
reference format.
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
FR80 Family
Refer to "Appendix A.1 Meaning of Symbols" for explanation regarding symbols used
in detailed execution instructions. The respective instructions are explained separately
in the following items.
● Assembler Format
Shows the format of writing the instruction in the assembler language.
● Operation
Shows the operation of an instruction by substituting it with an arrow mark (→).
● Flag Change
Shows whether the flag of the Condition Code Register (CCR) changes by the execution of an instruction.
● Classification
Shows Functional classification of instructions and the following sections of instructions.
• Instruction with delay slot: Instruction than can be positioned in the delay slot
• Read-Modify-Write system Instruction
• FR80Family: Instructions added in FR80 Family CPU
● Execution Cycle
Shows the required number of clock cycles for instruction execution
● Instruction Format
Shows the format and bit pattern of the instruction.
● Execution example
Shows the operation example at the time of instruction execution.
84
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.1
FR80 Family
7.1
ADD (Add 4bit Immediate Data to Destination Register)
Adds the result of higher 28 bits of 4-bit immediate data with zero extension (0 to 15)
and stores the results to Ri.
● Assembler Format
ADD #i4, Ri
● Operation
Ri + extu(i4) → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
1
0
0
i4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.1
FR80 Family
● Execution Example
ADD #2, R3
R3
; Bit pattern of instruction: 1010 0100 0010 0011
9 9 9 9 9 9 9 7
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
86
9 9 9 9 9 9 9 9
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.2
FR80 Family
7.2
ADD (Add Word Data of Source Register to Destination
Register)
Adds word data of Ri to Rj, stores result to Ri.
● Assembler Format
ADD Rj, Ri
● Operation
Ri + Rj → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
1
1
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.2
FR80 Family
● Execution Example
ADD R2, R3
; Bit pattern of instruction: 1010 0110 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
8 7 6 5 4 3 2 1
R3
9 9 9 9 9 9 9 9
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
88
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1 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.3
FR80 Family
7.3
ADD2 (Add 4bit Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension(-16 to
-1) to word data in Ri, stores results to Ri. Unlike SUB instruction, change in "C" flag of
this instruction is same as the ADD instruction SUB instruction.
● Assembler Format
ADD2 #i4, Ri
● Operation
Ri + extn(i4) → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
1
0
1
i4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.3
FR80 Family
● Execution Example
ADD2 #-2, R3
R3
; Bit pattern of instruction: 1010 0101 1110 0011
9 9 9 9 9 9 9 9
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
90
9 9 9 9 9 9 9 7
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.4
FR80 Family
7.4
ADDC (Add Word Data of Source Register and Carry Bit to
Destination Register)
Adds word data and carry flag (C) of Rj to Ri, stores results in Ri.
● Assembler Format
ADDC Rj, Ri
● Operation
Ri + Rj + C → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when MSB of the operation result is "1", cleared when MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
1
1
1
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.4
FR80 Family
● Execution Example
ADDC R2, R3
; Bit pattern of the instruction: 1010 0111 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
8 7 6 5 4 3 2 0
R3
9 9 9 9 9 9 9 9
N Z V C
CCR
0 0 0 1
N Z V C
CCR
Before execution
92
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1 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.5
FR80 Family
7.5
ADDN (Add Immediate Data to Destination Register)
Adds the result of the higher 28 bits of the 4-bit immediate data with zero extension
(0 to 15) to the word data of Ri, stores the results without changing flag settings.
● Assembler Format
ADDN #i4, Ri
● Operation
Ri + extu(i4) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
0
0
0
i4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.5
FR80 Family
● Execution Example
ADDN #2, R3
R3
; Bit pattern of the instruction: 1010 0000 0010 0011
9 9 9 9 9 9 9 7
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
94
9 9 9 9 9 9 9 9
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.6
FR80 Family
7.6
ADDN (Add Word Data of Source Register to Destination
Register)
Adds the word data of Rj to the word data of Ri, stores results in Ri without changing
flag settings.
● Assembler Format
ADDN Rj, Ri
● Operation
Ri + Rj → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
0
0
1
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.6
FR80 Family
● Execution Example
ADDN R2, R3
; Bit pattern of the instruction: 1010 0010 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
8 7 6 5 4 3 2 1
R3
9 9 9 9 9 9 9 9
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
96
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0 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.7
FR80 Family
7.7
ADDN2 (Add Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension (-16
to -1) to word data in "Ri", stores the results in "Ri" without changing flag settings.
● Assembler Format
ADDN2 #i4, Ri
● Operation
Ri + extn(i4) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
1
0
0
0
0
1
i4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.7
FR80 Family
● Execution Example
ADDN2 #-2, R3
R3
; Bit pattern of the instruction: 1010 0001 1110 0011
9 9 9 9 9 9 9 9
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
98
9 9 9 9 9 9 9 7
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.8
FR80 Family
7.8
ADDSP (Add Stack Pointer and Immediate Data)
Adds 4 times the 8-bit immediate data as a signed extended value to the word data of
"R15" and stores result in "R15". Specifies the value of s8 × 4 as "s10".
● Assembler Format
ADDSP #s10
● Operation
R15 + exts(s8×4) → R15
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
0
0
1
1
s8
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.8
FR80 Family
● Execution Example
ADDSP #-4
R15
; Bit pattern of the instruction: 1010 0011 1111 1111
8 0 0 0 0 0 0 0
R15
Before execution
100
FUJITSU SEMICONDUCTOR LIMITED
7 F F F F F F C
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.9
FR80 Family
7.9
AND (And Word Data of Source Register to Data in
Memory)
Takes the logical AND of the word data at memory address Ri and word data in Rj and
stores the results to the memory address corresponding to Ri.
● Assembler Format
AND Rj,@Ri
● Operation
(Ri) & Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Logical calculation instruction, Read/Modify/Write type instruction
● Execution Cycle
1+2a cycles
● Instruction Format
MSB
1
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LSB
0
0
0
0
1
0
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.9
FR80 Family
● Execution Example
AND R2,@R3
; Bit pattern of the instruction: 1000 0100 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0 1 0 1 0 1 0
Memory
12345678
1234567C
1234567C
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
102
1 0 1 0 0 0 0 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.10
FR80 Family
7.10
AND (And Word Data of Source Register to Destination
Register)
Takes the logical AND of word data in Ri and word data in Rj and stores the results to
Ri.
● Assembler Format
AND Rj, Ri
● Operation
Ri & Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "“0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Logical calculation instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
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LSB
0
0
0
0
0
1
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.10
FR80 Family
● Execution Example
AND R2, R3
; Bit pattern of the instruction: 1000 0010 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 0 1 0 1 0 1 0
R3
1 0 1 0 0 0 0 0
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
104
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.11
FR80 Family
7.11
ANDB (And Byte Data of Source Register to Data in
Memory)
Takes the logical AND of the byte data at memory address "Ri" and the byte data in "Rj"
and stores the results at Ri location in the memory.
● Assembler Format
ANDB Rj,@Ri
● Operation
(Ri) & Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit7) of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Logical calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
0
1
1
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.11
FR80 Family
● Execution Example
ANDB R2,@R3
; Bit pattern of the instruction: 1000 0110 0010 0011
R2
0 0 0 0 0 0 1 0
R2
0 0 0 0 0 0 1 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 1
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
106
1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.12
FR80 Family
7.12
ANDCCR (And Condition Code Register and Immediate
Data)
Takes the logical AND of byte data in the condition code register (CCR) and 8-bit
immediate data and returns the results to the CCR.
● Assembler Format
ANDCCR #u8
● Operation
CCR & u8 → CCR
● Flag Change
S
C
I
C
N
C
Z
C
V
C
C
C
S, I, N, Z, V, C: Varies according to results of operation.
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
0
0
1
1
u8
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.12
FR80 Family
● Execution Example
ANDCCR #0FEH ; Bit pattern of the instruction: 1000 0011 1111 1110
S I N Z V C
CCR
0 1 0 1 0 1
S I N Z V C
CCR
Before execution
108
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.13
FR80 Family
7.13
ANDH (And Halfword Data of Source Register to Data in
Memory)
Takes the logical AND of the half-word data at "Ri" location of the memory and the halfword data in "Rj" and stores the results at "Ri" location of the memory.
● Assembler Format
ANDH Rj,@Ri
● Operation
(Ri) & Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB (bit15) of the operation result is "1", cleared when the MSB (bit15) is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Logical calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
0
1
0
1
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.13
FR80 Family
● Execution Example
ANDH R2,@R3
; Bit pattern of the instruction: 1000 0101 0010 0011
R2
0 0 0 0 1 1 0 0
R2
0 0 0 0 1 1 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0 1 0
Memory
12345678
1234567A
1234567A
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
110
1 0 0 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14
FR80 Family
7.14
ASR (Arithmetic shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to
"Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and
the shift range is 0 to 31 bits.
● Assembler Format
ASR Rj, Ri
● Operation
Ri >> Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged.
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instructions, Instruction with delayed slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
1
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14
FR80 Family
● Execution Example
ASR R2, R3
; Bit pattern of the instruction: 1011 1010 0010 0011
R2
0 0 0 0
0 0 0 8
R2
0 0 0 0 0 0 0 8
R3
F F 0 F F F F F
R3
F F F F 0 F F F
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
112
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.15
FR80 Family
7.15
ASR (Arithmetic shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to
"Ri".
● Assembler Format
ASR #u4, Ri
● Operation
Ri >> u4 → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged.
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
1
0
0
0
u4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.15
FR80 Family
● Execution Example
ASR #8, R3
R3
; Bit pattern of the instruction: 1011 1000 1000 0011
F F 0 F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
114
F F F F 0 F F F
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.16
FR80 Family
7.16
ASR2 (Arithmetic shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "u4+16" bits, stores the result
to "Ri".
● Assembler Format
ASR2 #u4, Ri
● Operation
Ri >> {u4 + 16} → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged.
C: Holds the bit value shifted last.
● Classification
Shift instruction, Instruction with delayed slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
1
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.16
FR80 Family
● Execution Example
ASR2 #8, R3
R3
; Bit pattern of the instruction: 1011 1001 1000 0011
F 0 F F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
116
F F F F F F F 0
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.17
FR80 Family
7.17
BANDH (And 4bit Immediate Data to Higher 4bit of Byte
Data in Memory)
Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at
memory "Ri", stores the results to the memory address corresponding to "Ri".
● Assembler Format
BANDH #u4,@Ri
● Operation
(Ri) & {u4 << 4 + 0F H} → (Ri) [Operation uses higher 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit operation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
0
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.17
FR80 Family
● Execution Example
BANDH #0,@R3 ; Bit pattern of the instruction: 1000 0001 0000 0011
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 1
Memory
12345678
12345679
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
118
0 1
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18
FR80 Family
7.18
BANDL (And 4bit Immediate Data to Lower 4bit of Byte
Data in Memory)
Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at
memory "Ri", stores the results to the memory address corresponding to "Ri".
● Assembler Format
BANDL #u4,@Ri
● Operation
(Ri) & {F0H + u4} → (Ri) [Operation uses higher 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit operation instructions, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
0
0
0
0
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18
FR80 Family
● Execution Example
BANDL #0,@R3 ; Bit pattern of the instruction: 1000 0000 0000 0011
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 1
Memory
12345678
12345679
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
120
1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.19
FR80 Family
7.19
Bcc (Branch relative if Condition satisfied)
This is a branching instruction with no delay slot. If the conditions specified for each
instruction are satisfied, branch to the address indicated by "label9" relative to the
value of the program counter (PC). When calculating the address, double the value of
"rel8" as a signed extension. If conditions are not satisfied, no branching occurs.
● Assembler Format
BRA label9
BV
label9
BNO label9
BNV label9
BEQ label9
BLT label9
BNE label9
BGE label9
BC
label9
BLE label9
BNC label9
BGT label9
BN
label9
BLS label9
BP
label9
BHI
label9
● Operation
if (condition) then
PC + 2 + exts(rel8 × 2) → PC
Branching of each instruction is shown in Table 7.19-1.
Table 7.19-1 Branching conditions
Mnemonic
cc
Mnemonic
cc
Condition
BRA
0000
Always satisfied
BV
1000
V == 1
BNO
0001
Always unsatisfied
BNV
1001
V == 0
BEQ
0010
Z == 1
BLT
1010
(V ^ N) == 1
BNE
0011
Z == 0
BGE
1011
(V ^ N) == 0
BC
0100
C == 1
BLE
1100
((V ^ N) | Z) == 1
BNC
0101
C == 0
BGT
1101
((V ^ N) | Z) == 0
BN
0110
N == 1
BLS
1110
(C | Z) == 1
BP
0111
N == 0
BHI
1111
(C | Z) == 0
|: Logical add (or)
CM71-00104-3E
Condition
^: Exclusive-OR (exor) ==: comparison operation (satisfied by congruence)
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.19
FR80 Family
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Non-delayed branching instruction
● Execution Cycles
At time of branching: 2 cycles
At the time of no branching: 1 cycle
● Instruction Format
MSB
1
LSB
1
1
0
cc
rel8
● Execution Example
BHI label
; Bit pattern of the instruction: 1110 1111 0010 1000
...
label:
PC
; Address of BHI Instruction + 50H
F F 8 0 0 0 0 0
PC
N Z V C
CCR
1 0 1 0
N Z V C
CCR
Before execution
122
F F 8 0 0 0 5 2
FUJITSU SEMICONDUCTOR LIMITED
1 0 1 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.20
FR80 Family
7.20
Bcc:D (Branch relative if Condition satisfied)
This is a branching instruction with a delay slot. If the conditions established for each
particular instruction are satisfied, branch to the address indicated by "label9" relative
to the value of the program counter (PC). When calculating the address, double the
value of "rel8" as a signed extension. If conditions are not satisfied, no branching
occurs.
● Assembler Format
BRA:D label9
BV:D
label9
BNO:D label9
BNV:D label9
BEQ:D label9
BLT:D
label9
BNE:D label9
BGE:D
label9
BC:D
label9
BLE:D
label9
BNC:D label9
BGT:D
label9
BN:D
label9
BLS:D
label9
BP:D
label9
BHI:D
label9
● Operation
if (condition) then
PC + 2 + exts(rel8 × 2) → PC
Branching conditions of each instruction are shown in Table 7.20-1
Table 7.20-1 Branching conditions
Mnemonic
cc
Mnemonic
cc
Condition
BRA:D
0000
Always satisfied
BV:D
1000
V == 1
BNO:D
0001
Always unsatisfied
BNV:D
1001
V == 0
BEQ:D
0010
Z == 1
BLT:D
1010
(V ^ N) == 1
BNE:D
0011
Z == 0
BGE:D
1011
(V ^ N) == 0
BC:D
0100
C == 1
BLE:D
1100
((V ^ N) | Z) == 1
BNC:D
0101
C == 0
BGT:D
1101
((V ^ N) | Z) == 0
BN:D
0110
N == 1
BLS:D
1110
(C | Z) == 1
BP:D
0111
N == 0
BHI:D
1111
(C | Z) == 0
|: Logical add (or)
CM71-00104-3E
Condition
^: Exclusive-OR (exor) ==: comparison operation (satisfied by congruence)
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.20
FR80 Family
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Delayed branching instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
LSB
1
1
1
cc
rel8
● Execution Example
BHI:D label
; Bit pattern of the instruction: 1111 1111 0010 1000
LDI:8
; Instruction placed in delay slot
#255, R1
...
label:
; BHI:D instruction address + 50H
R1
8 9 4 7 9 7 A F
R1
0 0 0 0 0 0 F F
PC
F F 8 0 0 0 0 0
PC
F F 8 0 0 0 5 2
N Z V C
CCR
1 0 1 0
N Z V C
CCR
Before execution
1 0 1 0
After execution
The instruction placed in delay slot will be executed before the execution of the branch destination
instruction. The value of "R1" above will vary according to the specifications of the "LDI:8" instruction
placed in the delay slot.
124
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CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.21
FR80 Family
7.21
BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte
Data in Memory)
Takes the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte
data at memory address "Ri", stores the results to the memory address corresponding
to "Ri".
● Assembler Format
BEORH #u4,@Ri
● Operation
(Ri) ^ {u4 << 4} → (Ri) [Operation uses higher 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit Operation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
125
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.21
FR80 Family
● Execution Example
BEORH #1,@R3
R3
; Bit pattern of the instruction: 1001 1001 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
Memory
12345678
0 0
12345679
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
126
1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.22
FR80 Family
7.22
BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data
in Memory)
Takes the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte
data at memory address "Ri", stores the results to the memory address corresponding
to "Ri".
● Assembler Format
BEORL #u4,@Ri
● Operation
(Ri) ^ u4 → (Ri) [Operation uses higher 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit Operation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
0
0
0
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.22
FR80 Family
● Execution Example
BEORL #1,@R3
R3
; Bit pattern of the instruction: 1001 1000 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
0 0
Memory
12345678
12345679
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
128
0 1
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.23
FR80 Family
7.23
BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data
in Memory)
Takes the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at
memory address "Ri", stores the results to the memory address corresponding to "Ri".
● Assembler Format
BORH #u4,@Ri
● Operation
(Ri) | {u4 << 4} → (Ri) [Operation uses higher 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit Operation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.23
FR80 Family
● Execution Example
BORH #1,@R3
R3
; Bit pattern of the instruction: 1001 0001 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
0 0
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
130
1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.24
FR80 Family
7.24
BORL (Or 4bit Immediate Data to Lower 4bit of Byte Data in
Memory)
Takes the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at
memory address "Ri", stores the results to the memory address corresponding to "Ri".
● Assembler Format
BORL #u4,@Ri
● Operation
(Ri) | u4 → (Ri) [Operation uses lower 4 bits only]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Bit Operation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
0
0
0
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.24
FR80 Family
● Execution Example
BORL #1,@R3
R3
; Bit pattern of the instruction: 1001 0000 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
0 0
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
132
0 1
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.25
FR80 Family
7.25
BTSTH (Test Higher 4bit of Byte Data in Memory)
Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at
memory address "Ri" places the results in the condition code register (CCR).
● Assembler Format
BTSTH #u4,@Ri
● Operation
(Ri) & {u4 << 4} [Test uses higher 4 bits only]
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit7) of the operation result is "1", cleared when the MSB(bit7) is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Bit Operation instruction
● Execution Cycles
2+a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
1
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.25
FR80 Family
● Execution Example
BTSTH #1,@R3
R3
; Bit pattern of the instruction: 1000 1001 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
0 1
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
134
0 1
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.26
FR80 Family
7.26
BTSTL (Test Lower 4bit of Byte Data in Memory)
Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at
memory address "Ri", places the results in the flag of the condition code register
(CCR).
● Assembler Format
BTSTL #u4,@Ri
● Operation
(Ri) & u4 [Test uses lower 4 bits only]
● Flag Change
N
0
Z
C
V
-
C
-
N: Cleared
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged.
● Classification
Bit Operation instruction
● Execution Cycles
2+a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
1
0
0
0
u4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.26
FR80 Family
● Execution Example
BTSTL #1,@R3
R3
; Bit pattern of the instruction: 1000 1000 0001 0011
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
136
1 0
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.27
FR80 Family
7.27
CALL (Call Subroutine)
This is a branching instruction with no delay slot. After storing the address of the next
instruction in the return pointer (RP), branch to the address indicated by "label12"
relative to the value of the program counter (PC). When calculating the address, double
the value of "rel11" as a signed extension.
● Assembler Format
CALL label12
● Operation
PC + 2 → RP
PC + 2 + exts(rel11 × 2) → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Non-delayed branching instruction
● Execution Cycles
2 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
1
0
1
0
rel11
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.27
FR80 Family
● Execution Example
CALL label
; Bit pattern of the instruction: 1101 0000 1001 0000
...
label:
; CALL instruction address + 122H
PC
F F 8 0 0 0 0 0
PC
F F 8 0 0 1 2 2
RP
x x x x
RP
F F 8 0 0 0 0 4
x x x x
Before execution
138
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.28
FR80 Family
7.28
CALL (Call Subroutine)
This is a branching instruction with no delay slot. After saving the address of the next
instruction in the return pointer (RP), a branch to the address indicated by "Ri" occurs.
● Assembler Format
CALL @Ri
● Operation
PC + 2 → RP
Ri → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Non-delayed branching instruction
● Execution Cycles
2 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.28
FR80 Family
● Execution Example
CALL @R1
; Bit pattern of the instruction: 1001 0111 0001 0001
R1
F F F F F 8 0 0
R1
F F F F F 8 0 0
PC
8 0 0 0 F F F E
PC
F F F F F 8 0 0
RP
x x x x x x x x
RP
8 0 0 1 0 0 0 0
Before execution
140
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.29
FR80 Family
7.29
CALL:D (Call Subroutine)
This is a branching instruction with a delay slot. After saving the address of the next
instruction after the delay slot to the return pointer (RP), branch to the address
indicated by "label12" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel11" as a signed extension.
● Assembler Format
CALL:D label12
● Operation
PC + 4 → RP
PC + 2 + exts(rel11 × 2) → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Delayed branching instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
1
0
1
1
rel11
FUJITSU SEMICONDUCTOR LIMITED
141
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.29
FR80 Family
● Execution Example
CALL:D label
; Bit pattern of the instruction: 1101 1000 1001 0000
LDI:8
; Instruction placed in delay slot
#0, R2
…
label:
; CALL instruction address + 122H
R2
x x x x
PC
RP
x x x x
R2
0 0 0 0 0 0 0 0
F F 8 0 0 0 0 0
PC
F F 8 0 0 1 2 2
x x x x
RP
F F 8 0 0 0 0 4
x x x x
Before execution of "CALL" instruction
After branching
The instruction placed in delay slot is executed before execution of the branch destination instruction. The
value "R2" above will vary according to the specifications of the "LDI:8" instruction placed in the delay
slot.
142
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.30
FR80 Family
7.30
CALL:D (Call Subroutine)
This is a branching instruction with a delay slot. After saving the address of the next
instruction after the delay slot to the return pointer (RP), it branches to the address
indicated by "Ri".
● Assembler Format
CALL:D @Ri
● Operation
PC + 4 → RP
Ri → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Delayed branching instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
0
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
143
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.30
FR80 Family
● Execution Example
CALL:D @R1
; Bit pattern of the instruction: 1001 1111 0001 0001
LDI:8 #1, R1
; Instruction placed in delay slot
R1
F F F F F 8 0 0
R1
0 0 0 0 0 0 0 1
PC
8 0 0 0 F F F E
PC
F F F F F 8 0 0
RP
x x x x
RP
8 0 0 1 0 0 0 2
x x x x
Before execution of "CALL" instruction
After branching
The instruction placed in delay slot is executed before execution of the branch destination instruction. The
value "R1" above will vary according to the specifications of the "LDI:8" instruction placed in the delay
slot.
144
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.31
FR80 Family
7.31
CMP (Compare Immediate Data and Destination Register)
Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension
value (0 to 15) from the word data in "Ri", sets results in the flag of condition code
register (CCR).
● Assembler Format
CMP #i4, Ri
● Operation
Ri - extu(i4)
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Compare instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
0
0
0
i4
FUJITSU SEMICONDUCTOR LIMITED
Ri
145
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.31
FR80 Family
● Execution Example
CMP #3, R3
R3
; Bit pattern of the instruction: 1010 1000 0011 0011
0 0 0 0 0 0 0 3
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
146
0 0 0 0 0 0 0 3
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.32
FR80 Family
7.32
CMP (Compare Word Data in Source Register and
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", sets results in the flag of
condition code register (CCR).
● Assembler Format
CMP Rj, Ri
● Operation
Ri - Rj
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Compare instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
147
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.32
FR80 Family
● Execution Example
CMP R2, R3
; Bit pattern of the instruction: 1010 1010 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
148
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.33
FR80 Family
7.33
CMP2 (Compare Immediate Data and Destination Register)
Subtracts the result of the higher 28 bits of 4-bit immediate (from -16 to -1) data with
minus extension from the word data in "Ri", sets results in the flag of condition code
register (CCR).
● Assembler Format
CMP2 #i4, Ri
● Operation
Ri - extn(i4)
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Compare instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
0
0
1
i4
FUJITSU SEMICONDUCTOR LIMITED
Ri
149
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.33
FR80 Family
● Execution Example
CMP2 #-3, R3
R3
; Bit pattern of the instruction: 1010 1001 1101 0011
F F F F F F F D
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
150
F F F F F F F D
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.34
FR80 Family
7.34
DIV0S (Initial Setting Up for Signed Division)
This is a step division instruction. This command issued for signed division in which
multiplication division register (MDL) contains the dividend and the "Ri" the divisor,
with the quotient stored in the MDL and the remainder in multiplication division register
(MDH).
● Assembler Format
DIV0S Ri
● Operation
MDL[31] → D0
MDL[31] ^ Ri[31] → D1
exts(MDL) → MDH, MDL
The word data in MDL is extended to 64 bits, with the higher word in the "MDH" and the lower word in
the “MDL”. The value of the sign bit in the "MDL" and "Ri" is used to set the "D0" and "D1" flag bits in
the system condition code register (SCR).
● Flag Change
N
-
Z
-
V
-
C
-
D1
C
D0
C
N, Z, V, C: Flags unchanged.
D1: Set when the divisor and dividend signs are different, cleared when equal.
D0: Set when the dividend is negative, cleared when positive.
● Classification
Multiply/Divide Instruction
● Execution Cycles
1 cycle
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
151
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.34
FR80 Family
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
0
1
0
0
Ri
● Execution Example
DIV0S R2
; Bit pattern of the instruction: 1001 0111 0100 0010
R2
0 F F F F F F F
R2
0 F F F F F F F
MDH
0 0 0 0 0 0 0 0
MDH
F F F F F F F F
MDL
F F F F F F F 0
MDL
F F F F F F F 0
D1 D0 T
D1 D0 T
SCR
x x 0
SCR
Before execution
152
FUJITSU SEMICONDUCTOR LIMITED
1 1 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.35
FR80 Family
7.35
DIV0U (Initial Setting Up for Unsigned Division)
This is a step division command. This command issued for unsigned division in which
multiplication division register (MDL) contains the dividend and the "Ri" the divisor,
with the quotient stored in the MDL and the remainder in multiplication division register
(MDH).
● Assembler Format
DIV0U Ri
● Operation
0 → D0
0 → D1
0 → MDH
The MDH and bits "D0" and "D1" from system condition code register (SCR) are cleared to "0".
● Flag Change
N
-
Z
-
V
-
C
-
D1
0
D0
0
N, Z, V, C: Flags unchanged.
D1,D0: Cleared
● Classification
Multiply/Divide Instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
1
0
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
153
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.35
FR80 Family
● Execution Example
DIV0U R2
; Bit pattern of the instruction: 1001 0111 0101 0010
R2
0 0 F F F F F F
R2
0 0 F F F F F F
MDH
0 0 0 0 0 0 0 0
MDH
0 0 0 0 0 0 0 0
MDL
0 F F F F F F 0
MDL
0 F F F F F F 0
D1 D0 T
D1 D0 T
SCR
x x 0
SCR
Before execution
154
FUJITSU SEMICONDUCTOR LIMITED
0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.36
FR80 Family
7.36
DIV1 (Main Process of Division)
This is a step division instruction used for unsigned division.
● Assembler Format
DIV1 Ri
● Operation
{MDH, MDL} <<= 1
/* 1 bit left shift */
if (D1==1) {
MDH + Ri → temp
}
else {
MDH - Ri → temp
}
if ((D0 ^ D1 ^ C) == 0) {
temp → MDH
1 → MDL[0]
}
● Flag Change
N
-
Z
C
V
-
C
C
N, V: Unchanged
Z: Set when the result of step division is "0", cleared otherwise. Set according to remainder of division
results, not according to quotient.
C: Set when the operation result of step division involves a carry operation, cleared otherwise.
● Classification
Multiply/Divide Instruction
● Execution Cycles
1 cycle
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
155
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.36
FR80 Family
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
0
1
1
0
Ri
● Execution Example
DIV1 R2
; Bit pattern of the instruction: 1001 0111 0110 0010
R2
0 0 F F F F F F
R2
0 0 F F F F F F
MDH
0 0 F F F F F F
MDH
0 1 0 0 0 0 0 0
MDL
0 0 0 0 0 0 0 0
MDL
0 0 0 0 0 0 0 1
D1 D0 T
D1 D0 T
SCR
0 0 0
SCR
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
156
0 0 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.37
FR80 Family
7.37
DIV2 (Correction When Remain is 0)
This is a step division instruction used for signed division.
● Assembler Format
DIV2 Ri
● Operation
if (D1==1) {
MDH + Ri → temp
}
else {
MDH - Ri → temp
}
if (Z==1) {
0 → MDH
}
● Flag Change
N
-
Z
C
V
-
C
C
N, V: Unchanged
Z: Set when the result of step division is "0", cleared otherwise. Set according to remainder of division
results, not according to quotient.
C: Set when the operation result of step division involves a carry or borrow operation, cleared otherwise.
● Classification
Multiply/Divide Instruction
● Execution Cycles
c cycle(s)
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
157
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.37
FR80 Family
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
0
1
1
1
Ri
● Execution Example
DIV2 R2
; Bit pattern of the instruction: 1001 0111 0111 0010
R2
0 0 F F F F F F
R2
0 0 F F F F F F
MDH
0 0 F F F F F F
MDH
0 0 0 0 0 0 0 0
MDL
0 0 0 0 0 0 0 F
MDL
0 0 0 0 0 0 0 F
D1 D0 T
D1 D0 T
SCR
0 0 0
SCR
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
158
0 0 0
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.38
FR80 Family
7.38
DIV3 (Correction When Remain is 0)
This is a step division instruction used for signed division.
● Assembler Format
DIV3
● Operation
if (Z==1) {
MDL + 1 → MDL
}
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Multiply/Divide Instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
0
1
1
0
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
159
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.38
FR80 Family
● Execution Example
DIV3
; Bit pattern of the instruction: 1001 1111 0110 0000
R2
0 0 F F F F F F
R2
0 0 F F F F F F
MDH
0 0 0 0
0 0 0 0
MDH
0 0 0 0 0 0 0 0
MDL
0 0 0 0 0 0 0 F
MDL
0 0 0 0 0 0 1 0
D1 D0 T
D1 D0 T
SCR
0 0 0
SCR
N Z V C
CCR
0 1 0 0
N Z V C
CCR
Before execution
160
0 0 0
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.39
FR80 Family
7.39
DIV4S (Correction Answer for Signed Division)
This is a step division instruction used for signed division.
● Assembler Format
DIV4S
● Operation
if (D1==1) {
0 - MDL → MDL
}
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Multiply/Divide Instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
0
1
1
1
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
161
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.39
FR80 Family
● Execution Example
DIV4S
; Bit pattern of the instruction: 1001 1111 0111 0000
R2
0 0 F F F F F F
R2
0 0 F F F F F F
MDH
0 0 0 0
0 0 0 0
MDH
0 0 0 0 0 0 0 0
MDL
0 0 0 0 0 0 0 F
MDL
F F F F F F F 1
D1 D0 T
D1 D0 T
SCR
1 1 0
SCR
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
162
1 1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.40
FR80 Family
7.40
DMOV (Move Word Data from Direct Address to Register)
Transfers, to "R13" the word data at the direct address corresponding to 4 times the
value of "dir8". The value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV @dir10, R13
● Operation
(dir8 × 4) → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged.
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
0
0
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
163
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.40
FR80 Family
● Execution Example
DMOV @88H, R13
R13
x x x x
; Bit pattern of the instruction: 0000 1000 0010 0010
x x x x
R13
4 5 6 7
Memory
Memory
84 H
x x x x
x x x x
84 H
x x x x
x x x x
88 H
0 1 2 3
4 5 6 7
88 H
0 1 2 3
4 5 6 7
8CH
x x x x
x x x x
8CH
x x x x
x x x x
Before execution
164
0 1 2 3
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.41
FR80 Family
7.41
DMOV (Move Word Data from Register to Direct Address)
Transfers word data in "R13" to the direct address corresponding to 4 times the value of
"dir8". The value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV R13,@dir10
● Operation
R13 → (dir8 × 4)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
0
0
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
165
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.41
FR80 Family
● Execution Example
DMOV R13,@54H
R13
; Bit pattern of the instruction: 0001 1000 0001 0101
8 9 A B C D E F
R13
Memory
Memory
50 H
x x x x
x x x x
50 H
x x x x
54 H
x x x x
x x x x
54 H
8 9 A B C D E F
58 H
x x x x
x x x x
58 H
x x x x
Before execution
166
8 9 A B C D E F
FUJITSU SEMICONDUCTOR LIMITED
x x x x
x x x x
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.42
FR80 Family
7.42
DMOV (Move Word Data from Direct Address to Post
Increment Register Indirect Address)
Transfers the word data at the direct address corresponding to 4 times the value of
"dir8" to the address indicated in "R13". After the data transfer, it increments the value
of "R13" by 4. The value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV @dir10,@R13+
● Operation
(dir8 × 4) → (R13)
R13 + 4 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
1
0
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
167
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.42
FR80 Family
● Execution Example
DMOV @88H,@R13+
R13
; Bit pattern of the instruction: 0000 1100 0010 0010
F F F F 1 2 4 8
R13
Memory
00000088
1 4 1 4 2 1 3 5
Memory
00000088
1 4 1 4 2 1 3 5
FFFF1248
x x x x
x x x x
FFFF1248
1 4 1 4 2 1 3 5
FFFF124C
x x x x
x x x x
FFFF124C
x x x x
Before execution
168
F F F F 1 2 4 C
FUJITSU SEMICONDUCTOR LIMITED
x x x x
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.43
FR80 Family
7.43
DMOV (Move Word Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the word data at the address indicated in "R13" to the direct address
corresponding to 4 times the value "dir8". After the data transfer, it increments the value
of "R13" by 4. The value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV @R13+,@dir10
● Operation
(R13) → (dir8 × 4)
R13 + 4 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
1
0
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
169
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.43
FR80 Family
● Execution Example
DMOV @R13+,@54H
R13
; Bit pattern of the instruction: 0001 1100 0001 0101
F F F F 1 2 4 8
R13
Memory
Memory
00000054
x x x x x x x x
00000054
8 9 4 7 9 1 A F
FFFF1248
8 9 4 7 9 1 A F
FFFF1248
8 9 4 7 9 1 A F
FFFF124C
x x x x
x x x x
FFFF124C
x x x x x x x x
Before execution
170
F F F F 1 2 4 C
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.44
FR80 Family
7.44
DMOV (Move Word Data from Direct Address to Pre
Decrement Register Indirect Address)
Decrements the value of "R15" by 4, then transfers the word data at the direct address
corresponding to 4 times the value of "dir8" to the address indicated in "R15". The
value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV @dir10,@-R15
● Operation
R15 - 4 → R15
(dir8 × 4) → (R15)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
0
1
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
171
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.44
FR80 Family
● Execution Example
DMOV @2CH,@-R15
R15
; Bit pattern of the instruction: 0000 1011 0000 1011
7 F F F F F 8 8
R15
Memory
0000002C
8 2 A 2 8 2 A 9
Memory
0000002C
8 2 A 2 8 2 A 9
7FFFFF84
x x x x
x x x x
7FFFFF84
8 2 A 2 8 2 A 9
7FFFFF88
x x x x
x x x x
7FFFFF88
x x x x
Before execution
172
7 F F F F F 8 4
FUJITSU SEMICONDUCTOR LIMITED
x x x x
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.45
FR80 Family
7.45
DMOV (Move Word Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the word data at the address indicated in "R15" to the direct address
corresponding to 4 times the value "dir8". After the data transfer, it increments the value
of "R15" by 4. The value of "dir8 × 4" is specified as "dir10".
● Assembler Format
DMOV @R15+,@dir10
● Operation
(R15) → (dir8 × 4)
R15 + 4 → R15
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
0
1
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
173
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.45
FR80 Family
● Execution Example
DMOV @R15+,@38H
R15
; Bit pattern of the instruction: 0001 1011 0000 1110
7 F F E E E 8 0
R15
Memory
Memory
00000038
x x x x x x x x
00000038
8 3 4 3 8 3 4 A
7FFEEE80
8 3 4 3 8 3 4 A
7FFEEE80
8 3 4 3 8 3 4 A
7FFEEE84
x x x x x x x x
7FFEEE84
x x x x x x x x
Before execution
174
7 F F E E E 8 4
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.46
FR80 Family
7.46
DMOVB (Move Byte Data from Direct Address to Register)
Transfers the byte data at the address indicated by the value "dir8" to "R13". Uses zeros
to extend the higher 24 bits of data.
● Assembler Format
DMOVB @dir8, R13
● Operation
(dir8) → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
b cycle
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
0
1
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
175
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.46
FR80 Family
● Execution Example
DMOVB @91H, R13
R13
x x x x
; Bit pattern of the instruction: 0000 1010 1001 0001
x x x x
R13
0 0 0 0 0 0 3 2
Memory
90
x x
90
x x
91
3 2
91
3 2
92
x x
92
x x
Before execution
176
Memory
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.47
FR80 Family
7.47
DMOVB (Move Byte Data from Register to Direct Address)
Transfers the byte data from "R13" to the direct address indicated by the value "dir8".
● Assembler Format
DMOVB R13,@dir8
● Operation
R13 → (dir8)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
0
1
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
177
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.47
FR80 Family
● Execution Example
DMOVB R13,@53H
R13
; Bit pattern of the instruction: 0001 1010 0101 0011
F F F F F F F E
R13
F F F F F F F E
Memory
52
x x
52
x x
53
x x
53
F E
54
x x
54
x x
Before execution
178
Memory
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.48
FR80 Family
7.48
DMOVB (Move Byte Data from Direct Address to Post
Increment Register Indirect Address)
Moves the byte data at the direct address indicated by the value "dir8" to the address
indicated by "R13". After the data transfer, it increments the value of "R13" by 1.
● Assembler Format
DMOVB @dir8,@R13+
● Operation
(dir8) → (R13)
R13 + 1 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
1
1
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
179
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.48
FR80 Family
● Execution Example
DMOVB @71H,@R13+ ; Bit pattern of the instruction: 0000 1110 0111 0001
R13
8 8 0 0 1 2 3 4
R13
8 8 0 0 1 2 3 5
Memory
Memory
00000071
9 9
00000071
9 9
88001234
x x
88001234
9 9
88001235
x x
88001235
x x
Before execution
180
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.49
FR80 Family
7.49
DMOVB (Move Byte Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the byte data at the address indicated by "R13" to the direct address indicated
by the value "dir8". After the data transfer, it increments the value of "R13" by 1.
● Assembler Format
DMOVB @R13+,@dir8
● Operation
(R13) → (dir8)
R13 + 1 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
1
1
0
dir8
FUJITSU SEMICONDUCTOR LIMITED
181
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.49
FR80 Family
● Execution Example
DMOVB @R13+,@57H ; Bit pattern of the instruction: 0001 1110 0101 0111
R13
F F 8 0 1 2 2 0
R13
F F 8 0 1 2 2 1
Memory
Memory
00000057
x x
00000057
5 5
FF801220
5 5
FF801220
5 5
FF801221
x x
FF801221
x x
Before execution
182
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.50
FR80 Family
7.50
DMOVH (Move Halfword Data from Direct Address to
Register)
Transfers the half-word data at the direct address corresponding to 2 times the value
"dir8" to "R13". Uses zeros to extend the higher 16 bits of data. The value of "dir8 × 2"
is specified as "dir9".
● Assembler Format
DMOVH @dir9, R13
● Operation
(dir8 × 2) → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
0
0
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
183
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.50
FR80 Family
● Execution Example
DMOVH @88H, R13
R13
x x x x
; Bit pattern of the instruction: 0000 1001 0100 0100
x x x x
R13
0 0 0 0
Memory
Memory
86
x x x x
86
x x x x
88
B 2 B 6
88
B 2 B 6
8A
x x x x
8A
x x x x
Before execution
184
B 2 B 6
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.51
FR80 Family
7.51
DMOVH (Move Halfword Data from Register to Direct
Address)
Transfers the half-word data from "R13" to the direct address corresponding to 2 times
the value "dir8". The value of "dir8 × 2" is specified as "dir9".
● Assembler Format
DMOVH R13,@dir9
● Operation
R13 → (dir8 × 2)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
0
0
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
185
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.51
FR80 Family
● Execution Example
DMOVH R13,@52H
R13
F F F F
; Bit pattern of the instruction: 0001 1001 0010 1001
A E 8 6
R13
F F F F
Memory
Memory
50
x x x x
50
x x x x
52
x x x x
52
A E 8 6
54
x x x x
54
x x x x
Before execution
186
A E 8 6
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.52
FR80 Family
7.52
DMOVH (Move Halfword Data from Direct Address to Post
Increment Register Indirect Address)
Transfers the half-word data at the direct address corresponding to 2 times the value
"dir8" to the address indicated by "R13". After the data transfer, it increments the value
of "R13" by 2. The value of "dir8 × 2" is specified as "dir9".
● Assembler Format
DMOVH @dir9,@R13+
● Operation
(dir8 × 2) → (R13)
R13 + 2 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
1
0
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
187
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.52
FR80 Family
● Execution Example
DMOVH @88H,@R13+ ; Bit pattern of the instruction: 0000 1101 0100 0100
R13
F F 0 0 0 0 5 2
R13
F F 0 0 0 0 5 4
Memory
Memory
00000088
1 3 7 4
00000088
1 3 7 4
FF000052
x x x x
FF000052
1 3 7 4
FF000054
x x x x
FF000054
x x x x
Before execution
188
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.53
FR80 Family
7.53
DMOVH (Move Halfword Data from Post Increment
Register Indirect Address to Direct Address)
Transfers the half-word data at the address indicated by "R13" to the direct address
corresponding to 2 times the value "dir8". After the data transfer, it increments the value
of "R13" by 2. The value of "dir8 × 2" is specified as "dir9".
● Assembler Format
DMOVH @R13+,@dir9
● Operation
(R13) → (dir8 × 2)
R13 + 2 → R13
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Direct Addressing Instructions
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
1
1
0
1
dir8
FUJITSU SEMICONDUCTOR LIMITED
189
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.53
FR80 Family
● Execution Example
DMOVH @R13+,@52H ; Bit pattern of the instruction: 0001 1101 0010 1001
R13
F F 8 0 1 2 2 0
R13
F F 8 0 1 2 2 2
Memory
Memory
00000052
x x x x
00000052
8 9 3 3
FF801220
8 9 3 3
FF801220
8 9 3 3
FF801222
x x x x
FF801222
x x x x
Before execution
190
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.54
FR80 Family
7.54
ENTER (Enter Function)
This instruction is used for stack frame generation processing for high level languages.
The value "u8" is calculated as an unsigned value. The value of "u8 × 4" is specified as
"u10".
● Assembler Format
ENTER #u10
● Operation
R14 → (R15-4)
R15 - 4 → R14
R15 - extu(u8 × 4) → R15
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions
● Execution Cycles
1+a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
1
1
1
1
u8
FUJITSU SEMICONDUCTOR LIMITED
191
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.54
FR80 Family
● Execution Example
ENTER #0CH
; Bit pattern of the instruction: 0000 1111 0000 0011
R14
8 0 0 0
0 0 0 0
R14
7 F F F F F F 4
R15
7 F F F F F F 8
R15
7 F F F F F E C
Memory
Memory
7FFFFFEC
x x x x x x x x
7FFFFFEC
x x x x x x x x
7FFFFFF0
x x x x x x x x
7FFFFFF0
x x x x x x x x
7FFFFFF4
x x x x x x x x
7FFFFFF4
8 0 0 0 0 0 0 0
7FFFFFF8
x x x x x x x x
7FFFFFF8
x x x x x x x x
7FFFFFFC
x x x x x x x x
7FFFFFFC
x x x x x x x x
80000000
x x x x x x x x
80000000
x x x x x x x x
Before execution
192
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.55
FR80 Family
7.55
EOR (Exclusive Or Word Data of Source Register to Data in
Memory)
Takes the logical exclusive OR of the word data at memory address "Ri" and the word
data in "Rj", stores the results to the memory address corresponding to "Ri".
● Assembler Format
EOR Rj,@Ri
● Operation
(Ri) ^ Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
0
LSB
0
1
1
1
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
193
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.55
FR80 Family
● Execution Example
EOR R2,@R3
; Bit pattern of the instruction: 1001 1100 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0 1 0 1 0 1 0
Memory
12345678
1234567C
1234567C
N Z V C
CCR
0 0 0 0
Before execution
194
0 1 0 1 1 0 1 0
FUJITSU SEMICONDUCTOR LIMITED
N Z V C
CCR
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.56
FR80 Family
7.56
EOR (Exclusive Or Word Data of Source Register to
Destination Register)
Takes the logical exclusive OR of the word data in "Ri" and the word data in "Rj", stores
the results to "Ri".
● Assembler Format
EOR Rj, Ri
● Operation
Ri ^ Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
195
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.56
FR80 Family
● Execution Example
EOR R2, R3
; Bit pattern of the instruction: 1001 1010 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 0 1 0 1 0 1 0
R3
0 1 0 1 1 0 1 0
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
196
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.57
FR80 Family
7.57
EORB (Exclusive Or Byte Data of Source Register to Data
in Memory)
Takes the logical exclusive OR of the byte data at memory address "Ri" and the byte
data in "Rj", stores the results to the memory address corresponding to "Ri".
● Assembler Format
EORB Rj,@Ri
● Operation
(Ri) ^ Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit7) of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
197
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.57
FR80 Family
● Execution Example
EORB R2,@R3
; Bit pattern of the instruction: 1001 1110 0010 0011
R2
0 0 0 0 0 0 1 1
R2
0 0 0 0 0 0 1 1
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0
12345679
Memory
12345678
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
198
0 1
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.58
FR80 Family
7.58
EORH (Exclusive Or Halfword Data of Source Register to
Data in Memory)
Takes the logical exclusive OR of the half-word data at memory address "Ri" and the
half-word data in "Rj", stores the results to the memory address corresponding to "Ri".
● Assembler Format
EORH Rj,@Ri
● Operation
(Ri) ^ Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit15) of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
199
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.58
FR80 Family
● Execution Example
EORH R2,@R3
; Bit pattern of the instruction: 1001 1101 0010 0011
R2
0 0 0 0 1 1 0 0
R2
0 0 0 0 1 1 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0 1 0
1234567A
Memory
12345678
1234567A
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
200
0 1 1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.59
FR80 Family
7.59
EXTSB (Sign Extend from Byte Data to Word Data)
Extends the byte data indicated by "Ri" to word data as signed binary value.
● Assembler Format
EXTSB Ri
● Operation
exts(Ri[7:0]) → Ri [byte → word]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
Ri
201
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.59
FR80 Family
● Execution Example
EXTSB R1
R1
; Bit pattern of the instruction: 1001 0111 1000 0001
0 0 0 0 0 0 A B
R1
Before execution
202
FUJITSU SEMICONDUCTOR LIMITED
F F F F FFA B
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.60
FR80 Family
7.60
EXTSH (Sign Extend from Byte Data to Word Data)
Extends the half-word data indicated by "Ri" to word data as a signed binary value.
● Assembler Format
EXTSH Ri
● Operation
exts(Ri[15:0]) → Ri
[half-word → word]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
1
0
FUJITSU SEMICONDUCTOR LIMITED
Ri
203
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.60
FR80 Family
● Execution Example
EXTSH R1
R1
; Bit pattern of the instruction: 1001 0111 1010 0001
0 0 0 0 A B C D
R1
Before execution
204
FUJITSU SEMICONDUCTOR LIMITED
F F F F A B C D
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.61
FR80 Family
7.61
EXTUB (Unsign Extend from Byte Data to Word Data)
Extends the byte data indicated by "Ri" to word data as an unsigned binary value.
● Assembler Format
EXTUB Ri
● Operation
extu(Ri[7:0]) → Ri
[byte → word]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
205
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.61
FR80 Family
● Execution Example
EXTUB R1
R1
; Bit pattern of the instruction: 1001 0111 1001 0001
F F F F F F F F
R1
Before execution
206
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 0 0 F F
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.62
FR80 Family
7.62
EXTUH (Unsign Extend from Byte Data to Word Data)
Extends the half-word data indicated by "Ri" to word data as an unsigned binary value.
● Assembler Format
EXTUH Ri
● Operation
extu(Ri[15:0]) → Ri
[half-word → word]
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
1
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
207
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.62
FR80 Family
● Execution Example
EXTUH R1
R1
; Bit pattern of the instruction: 1001 0111 1011 0001
F F F F F F F F
R1
Before execution
208
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 F F F F
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.63
FR80 Family
7.63
INT (Software Interrupt)
This is a software interrupt instruction. Reads the vector table for the interrupt vector
number “u8” to determine the branch destination address, and branches.
● Assembler Format
INT #u8
Vector numbers 9 to 13, 64 and 65 are used by emulators for debugging interrupts and therefore the
corresponding numbers “INT#9” to “INT#13”, “INT#64”, “INT#65” should not be used in user programs.
● Operation
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
PC+2 → (SSP)
"0" → CCR:I
"0" → CCR:S
(TBR+3FCH-u8 × 4) → PC
Stores the values of the program counter (PC) and program status (PS) to the stack indicated by the system
stack pointer (SSP) for interrupt processing. Writes "0" to the "S" flag in the condition code register (CCR),
and uses the "SSP" as the stack pointer for following steps. Writes "0" to the "I" flag (interrupt enable flag)
in the "CCR" to disable external interrupts. Reads the vector table for the interrupt vector number "u8" to
determine the branch destination address, and branches.
● Flag Change
S
0
I
0
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
S, I: Cleared.
● Classification
Non-Delayed Branching instruction
CM71-00104-3E
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.63
FR80 Family
● Execution Cycles
1+3a cycles
● Instruction Format
MSB
0
LSB
0
0
1
1
1
1
1
u8
● Execution Example
INT #20H
; Bit pattern of the instruction: 0001 1111 0010 0000
R15
4 0 0 0 0 0 0 0
R15
7 F F F F F F 8
SSP
8 0 0 0 0 0 0 0
SSP
7 F F F F F F 8
TBR
0 0 0 F F C 0 0
TBR
0 0 0 F F C 0 0
USP
4 0 0 0 0 0 0 0
USP
4 0 0 0 0 0 0 0
PC
8 0 8 8 8 0 8 6
PC
6 8 0 9 6 8 0 0
PS
F F F F F 8 F 0
PS
F F F F F 8 C 0
S I N Z V C
CCR
1 1 0 0 0 0
S I N Z V C
CCR
Memory
Memory
000FFF7C
6 8 0 9 6 8 0 0
000FFF7C
6 8 0 9 6 8 0 0
7FFFFFF8
x x x x x x x x
7FFFFFF8
8 0 8 8 8 0 8 8
7FFFFFFC
x x x x x x x x
7FFFFFFC
F F F F F 8 F 0
80000000
x x x x x x x x
80000000
x x x x x x x x
Before execution
210
0 0 0 0 0 0
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.64
FR80 Family
7.64
INTE (Software Interrupt for Emulator)
This software interrupt instruction is used for debugging. It determines the branch
destination address by reading interrupt vector number "#9" from the vector table, then
branches.
● Assembler Format
INTE
● Operation
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
PC+2 → (SSP)
4 → ILM
"0" → CCR:S
(TBR+3D8H) → PC
It stores the values of the program counter (PC) and program status (PS) to the stack indicated by the
system stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition code
register (CCR), and uses the "SSP" as the stack pointer for the following steps. It determines the branch
destination address by reading interrupt vector number "#9" from the vector table, then branches.
There is not change to the "I" flag in the condition code register (CCR). The interrupt level mask register
(ILM) in the program status (PS) is set to level 4.
● Flag Change
S
0
I
-
N
-
Z
-
V
-
C
-
I, N, Z, V, C: Unchanged
S: Cleared.
● Classification
Non-Delayed Branching instruction
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
211
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.64
FR80 Family
● Execution Cycles
1+3a cycles
● Instruction Format
MSB
1
LSB
0
0
1
1
1
1
1
0
0
1
1
0
0
0
0
● Execution Example
INTE
; Bit pattern of the instruction: 1001 1111 0011 0000
R15
4 0 0 0 0 0 0 0
R15
7 F F F F F F 8
SSP
8 0 0 0 0 0 0 0
SSP
7 F F F F F F 8
USP
4 0 0 0 0 0 0 0
USP
4 0 0 0 0 0 0 0
TBR
0 0 0 F F C 0 0
TBR
0 0 0 F F C 0 0
PC
8 0 8 8 8 0 8 6
PC
6 8 0 9 6 8 0 0
PS
F F F 5 F 8 F 0
PS
F F E 4 F 8 D 0
ILM
1 0 1 0 1
ILM
S I N Z V C
CCR
1 1 0 0 0 0
S I N Z V C
CCR
Memory
0 1 0 0 0 0
Memory
000FFFD8
6 8 0 9 6 8 0 0
000FFFD8
6 8 0 9 6 8 0 0
7FFFFFF8
x x x x x x x x
7FFFFFF8
8 0 8 8 8 0 8 8
7FFFFFFC
x x x x x x x x
7FFFFFFC
F F F F F 8 F 0
80000000
x x x x x x x x
80000000
x x x x x x x x
Before execution
212
0 0 1 0 0
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.65
FR80 Family
7.65
JMP (Jump)
This is a branching instruction without a delay slot. Branches to the address indicated
in “Ri”.
● Assembler Format
JMP @Ri
● Operation
Ri → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Non-Delayed Branching instruction
● Execution Cycles
2 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
Ri
213
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.65
FR80 Family
● Execution Example
JMP @R1
; Bit pattern of the instruction: 1001 0111 0000 0001
R1
C 0 0 0 8 0 0 0
R1
0 0 0 0 0 0 F F
PC
F F 8 0 0 0 0 0
PC
C 0 0 0 8 0 0 0
Before execution
214
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After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.66
FR80 Family
7.66
JMP:D (Jump)
This is a branching instruction with delay slot. Branches to the address indicated by
"Ri".
● Assembler Format
JMP:D @Ri
● Operation
Ri → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Delayed Branching instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
0
0
0
0
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.66
FR80 Family
● Execution Example
JMP:D @R1
; Bit pattern of the instruction: 1001 1111 0000 0001
LDI:8 #0FFH, R1 ; Instruction placed in delay slot
R1
C 0 0 0 8 0 0 0
R1
0 0 0 0 0 0 F F
PC
F F 8 0 0 0 0 0
PC
C 0 0 0 8 0 0 0
Before execution of "JMP" instruction
After branching
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction. The value "R1" above will vary according to the specifications of the "LDI:8" instruction
placed in the delay slot.
216
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CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.67
FR80 Family
7.67
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "Rj" to "Ri".
● Assembler Format
LD @Rj, Ri
● Operation
(Rj) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.67
FR80 Family
● Execution Example
LD @R2, R3
; Bit pattern of the instruction: 0000 0100 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
0 0 0 0 0 0 0 0
R3
8 7 6 5 4 3 2 1
Memory
12345678
8 7 6 5 4 3 2 1
Memory
12345678
Before execution
218
FUJITSU SEMICONDUCTOR LIMITED
8 7 6 5 4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.68
FR80 Family
7.68
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R13 + Rj" to "Ri".
● Assembler Format
LD @(R13, Rj), Ri
● Operation
(R13+Rj) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
0
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.68
FR80 Family
● Execution Example
LD @(R13, R2), R3
; Bit pattern of the instruction: 0000 0000 0010 0011
R2
0 0 0 0 0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
x x x x
R3
8 7 6 5 4 3 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
x x x x
12345678
Memory
12345678
Memory
1234567C
8 7 6 5 4 3 2 1
1234567C
8 7 6 5 4 3 2 1
Before execution
220
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.69
FR80 Family
7.69
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R14 + o8 × 4" to "Ri". The value "o8" is a
signed calculation. The value of o8 × 4 is specified as "disp10".
● Assembler Format
LD @(R14, disp10), Ri
● Operation
(R14+o8 × 4) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
1
0
o8
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.69
FR80 Family
● Execution Example
LD @(R14,4), R3
; Bit pattern of the instruction: 0010 0000 0001 0011
R3
x x x x
R14
1 2 3 4 5 6 7 8
x x x x
8 7 6 5 4 3 2 1
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567C
8 7 6 5 4 3 2 1
1234567C
8 7 6 5 4 3 2 1
Before execution
222
R3
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.70
FR80 Family
7.70
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R15 + u4 × 4" to "Ri". The value "u4" is an
unsigned calculation. The value of u4 × 4 is specified as "udisp6".
● Assembler Format
LD @(R15, udisp6), Ri
● Operation
(R15+u4 ×4) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
0
1
1
u4
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.70
FR80 Family
● Execution Example
LD @(R15,4), R3
; Bit pattern of the instruction: 0000 0011 0001 0011
R3
x x x x
R15
1 2 3 4 5 6 7 8
x x x x
R3
8 7 6 5 4 3 2 1
R15
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567C
8 7 6 5 4 3 2 1
1234567C
8 7 6 5 4 3 2 1
Before execution
224
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.71
FR80 Family
7.71
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R15" to "Rj", and adds 4 to the value of "R15".
If "R15" is given as parameter "Ri", the value read from the memory will be loaded into
memory address "R15".
● Assembler Format
LD @R15+, Ri
● Operation
(R15) → Ri
R15 + 4 → R15
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
1
1
0
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.71
FR80 Family
● Execution Example
LD @R15+, R3
; Bit pattern of the instruction: 0000 0111 0000 0011
R3
x x x x
R15
1 2 3 4 5 6 7 8
x x x x
R3
8 7 6 5 4 3 2 1
R15
1 2 3 4 5 6 7 C
Memory
12345678
8 7 6 5 4 3 2 1
1234567C
Memory
12345678
1234567C
Before execution
226
8 7 6 5 4 3 2 1
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.72
FR80 Family
7.72
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R15" to dedicated register "Rs", and adds 4 to
the value of "R15". If the number of a non-existent register is given as parameter "Rs",
the read value will be ignored.
● Assembler Format
LD @R15+, Rs
● Operation
(R15) → Rs
R15 + 4 → R15
If "Rs" is designated as the system stack pointer (SSP) or user stack pointer (USP), and that pointer is
indicating "R15" [the "S" flag in the condition code register (CCR) is set to "0" to indicate the "SSP", and
to "1" to indicate the "USP"], the last value remaining in "R15" will be the value read from memory.
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
1
1
1
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
Rs
227
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.72
FR80 Family
● Execution Example
LD @R15+, MDH
; Bit pattern of the instruction: 0000 0111 1000 0100
R15
1 2 3 4 5 6 7 4
R15
1 2 3 4 5 6 7 8
MDH
x x x x
MDH
8 7 6 5 4 3 2 1
x x x x
12345670
Memory
12345670
Memory
12345674
8 7 6 5 4 3 2 1
12345674
8 7 6 5 4 3 2 1
Before execution
228
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.73
FR80 Family
7.73
LD (Load Word Data in Memory to Program Status
Register)
Loads the word data at memory address "R15" to the program status (PS), and adds 4
to the value of "R15".
● Assembler Format
LD @R15+, PS
● Operation
(R15) → PS
R15 + 4 → R15
At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range
16 to 31, only new "ILM" settings between 16 and 31 can be entered. If data in the range 0 to 15 is loaded
from memory, the value 16 will be added to that data before being transferred to the "ILM". IF the original
“ILM” value is in the range 0 to 15, then any value from 0 to 31 can be transferred to the "ILM".
● Flag Change
N
C
Z
C
V
C
C
C
N, Z, V, C: Data of (R15) is transferred.
● Classification
Memory Load instruction
● Execution Cycles
1+a cycles
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
1
1
1
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
229
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.73
FR80 Family
● Execution Example
LD @R15+, PS
; Bit pattern of the instruction: 0000 0111 1001 0000
R15
1 2 3 4 5 6 7 4
R15
1 2 3 4 5 6 7 8
PS
F F F F F 8 D 5
PS
F F F 8 F 8 C 0
12345670
Memory
12345670
Memory
12345674
F F F 8 F 8 C 0
12345674
F F F 8 F 8 C 0
Before execution
230
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.74
FR80 Family
7.74
LDI:20 (Load Immediate 20bit Data to Destination Register)
Extends the 20-bit immediate data with 000H in the higher bits, loads to "Ri".
● Assembler Format
LDI:20 #i20, Ri
● Operation
extu(i20) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Immediate Data Transfer instruction
● Execution Cycles
2 cycles
● Instruction Format
MSB
(n+0)
(n+2)
CM71-00104-3E
1
LSB
0
0
1
1
0
1
1
i20 (higher)
Ri
i20 (lower)
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.74
FR80 Family
● Execution Example
LDI:20 #54321H, R3
; Bit pattern of the instruction: 1001 1011 0101 0011
;
R3
0 0 0 0 0 0 0 0
0100 0011 0010 0001
R3
Before execution
232
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 5 4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.75
FR80 Family
7.75
LDI:32 (Load Immediate 32 bit Data to Destination
Register)
Loads 1 word of immediate data to "Ri".
● Assembler Format
LDI:32 #i32, Ri
● Operation
i32 → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Immediate Data Transfer instruction
● Execution Cycles
d cycle(s)
● Instruction Format
MSB
(n+0)
1
LSB
0
0
1
1
1
1
1
1
(n+2)
i32 (higher)
(n+4)
i32 (lower)
CM71-00104-3E
0
0
FUJITSU SEMICONDUCTOR LIMITED
0
Ri
233
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.75
FR80 Family
● Execution Example
LDI:32 #87654321H, R3 ; Bit pattern of the instruction: 1001 1111 1000 0011
R3
;
1000 0111 0110 0101
;
0100 0011 0010 0001
0 0 0 0 0 0 0 0
R3
Before execution
234
FUJITSU SEMICONDUCTOR LIMITED
8 7 6 5 4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.76
FR80 Family
7.76
LDI:8 (Load Immediate 8bit Data to Destination Register)
Extends the 8-bit immediate data with 24 zero bits in the higher bits, loads to "Ri".
● Assembler Format
LDI:8 #i8, Ri
● Operation
extu(i8) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Immediate Data Transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
1
0
0
i8
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.76
FR80 Family
● Execution Example
LDI:8 #21H, R3
R3
; Bit pattern of the instruction: 1100 0010 0001 0011
0 0 0 0 0 0 0 0
R3
Before execution
236
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 0 0 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.77
FR80 Family
7.77
LDM0 (Load Multiple Registers)
The "LDM0" instruction stores the word data from the address "R15" to the registers in
the range R0 to R7 as members of the parameter "reglist" and repeats the operation of
adding 4 to "R15". Registers are processed in ascending numerical order.
● Assembler Format
LDM0 (reglist)
Registers from R0 to R7 are separated in "reglist", multiple register are arranged and specified.
● Operation
The following operations are repeated according to the number of registers specified in the parameter
“reglist”.
(R15) → Ri
R15+4 → R15
Table 7.77-1 shows the bit of reglist of the LDM0 instruction and the correspondence of the register.
Table 7.77-1 Bit of reglist of the LDM0 instruction and the correspondence of the register
Bit
Register
7
R7
6
R6
5
R5
4
R4
3
R3
2
R2
1
R1
0
R0
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.77
FR80 Family
● Classification
Other instructions
● Execution Cycles
If "n" is the number of registers specified in the parameter "reglist", the execution cycles required are as
follows.
When n=0: 1 cycle
Otherwise: b × n cycles
● Instruction Format
MSB
1
LSB
0
0
0
1
1
0
0
reglist
● Execution Example
LDM0 (R3, R4)
; Bit pattern of the instruction: 1000 1100 0001 1000
R3
x x x x
x x x x
R3
9 0 B C 9 3 6 3
R4
x x x x
x x x x
R4
8 3 4 3 8 3 4 A
R15
7 F F F F F C 0
R15
7 F F F F F C 8
Memory
Memory
7FFFFFC0
9 0 B C 9 3 6 3
7FFFFFC0
9 0 B C 9 3 6 3
7FFFFFC4
8 3 4 3 8 3 4 A
7FFFFFC4
8 3 4 3 8 3 4 A
7FFFFFC8
x x x x
7FFFFFC8
x x x x
x x x x
Before execution
238
FUJITSU SEMICONDUCTOR LIMITED
x x x x
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.78
FR80 Family
7.78
LDM1 (Load Multiple Registers)
Loads the word data of address "R15" to multiple registers "R8" to "R15" specified in
"reglist", repeats the operation of adding 4 to "R15". Registers are processed in
ascending numerical order. If "R15" is specified in the parameter "reglist", the final
contents of "R15" will be read from memory.
● Assembler Format
LDM1 (reglist)
Registers from R8 to R15 are separated in "reglist", multiple register are arranged and specified.
● Operation
The following operations are repeated according to the number of registers specified in the parameter
“reglist”.
(R15) → Ri
R15+4 → R15
Table 7.78-1 shows the bit of reglist of the LDM0 instruction and the correspondence of the register.
Table 7.78-1 Bit of reglist of the LDM0 instruction and the correspondence of the register
Bit
Register
7
R15
6
R14
5
R13
4
R12
3
R11
2
R10
1
R9
0
R8
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.78
FR80 Family
● Classification
Other instructions
● Execution Cycles
If "n" is the number of registers specified in the parameter "reglist" the execution cycles required are as
follows.
When n=0: 1 cycle
Otherwise: b × n cycles
● Instruction Format
MSB
1
LSB
0
0
0
1
1
0
1
reglist
● Execution Example
LDM1 (R10, R11, R12)
; Bit pattern of the instruction: 1000 1101 0001 1100
R10
x x x x x x x x
R10
8 F E 3 9 E 8 A
R11
x x x x x x x x
R11
9 0 B C 9 3 6 3
R12
x x x x x x x x
R12
8 D F 7 8 8 E 4
R15
7 F F F F F C 0
R15
7 F F F F FC C
Memory
Memory
7FFFFFC0
8 F E 3 9 E 8 A
7FFFFFC0
8 F E 3 9 E 8 A
7FFFFFC4
9 0 B C 9 3 6 3
7FFFFFC4
9 0 B C 9 3 6 3
7FFFFFC8
8 D F 7 8 8 E 4
7FFFFFC8
8 D F 7 8 8 E 4
7FFFFFCC
x x x x x x x x
7FFFFFCC
x x x x x x x x
Before execution
240
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.79
FR80 Family
7.79
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "Rj", loads to "Ri".
● Assembler Format
LDUB @Rj, Ri
● Operation
extu((Rj)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
241
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.79
FR80 Family
● Execution Example
LDUB @R2, R3
; Bit pattern of the instruction: 0000 0110 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
x x x x
R3
0 0 0 0 0 0 2 1
x x x x
Memory
12345678
2 1
Before execution
242
FUJITSU SEMICONDUCTOR LIMITED
Memory
12345678
2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.80
FR80 Family
7.80
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "R13 + Rj", loads to "Ri".
● Assembler Format
LDUB @(R13, Rj), Ri
● Operation
extu((R13+Rj)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
243
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.80
FR80 Family
● Execution Example
LDUB @(R13, R2), R3
; Bit pattern of the instruction: 0000 0010 0010 0011
R2
0 0 0 0
0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
x x x x
x x x x
R3
0 0 0 0 0 0 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567C
2 1
1234567C
2 1
Before execution
244
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.81
FR80 Family
7.81
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "R14 + o8", loads to "Ri". The
value "o8" is a signed calculation. The value of o8 is specified in "disp8".
● Assembler Format
LDUB @(R14, disp8), Ri
● Operation
extu((R14+o8)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
1
1
0
o8
FUJITSU SEMICONDUCTOR LIMITED
Ri
245
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.81
FR80 Family
● Execution Example
LDUB @(R14,1), R3
; Bit pattern of the instruction: 0110 0000 0001 0011
R3
x x x x
x x x x
R3
0 0 0 0 0 0 2 1
R14
1 2 3 4
5 6 7 8
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
12345679
2 1
12345679
2 1
Before execution
246
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.82
FR80 Family
7.82
LDUH (Load Halfword Data in Memory to Register)
Extends with zeros the half-word data at memory address "Rj", loads to "Ri".
● Assembler Format
LDUH @Rj, Ri
● Operation
extu((Rj)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
247
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.82
FR80 Family
● Execution Example
LDUH @R2, R3
; Bit pattern of the instruction: 0000 0101 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
x x x x
R3
0 0 0 0 4 3 2 1
x x x x
Memory
12345678
4 3 2 1
Before execution
248
FUJITSU SEMICONDUCTOR LIMITED
Memory
12345678
4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.83
FR80 Family
7.83
LDUH (Load Halfword Data in Memory to Register)
Extends with zeros the half-word data at memory address "R13 + Rj", loads to "Ri".
● Assembler Format
LDUH @(R13, Rj), Ri
● Operation
extu((R13+Rj)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
0
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
249
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.83
FR80 Family
● Execution Example
LDUH @(R13, R2), R3
; Bit pattern of the instruction: 0000 0001 0010 0011
R2
0 0 0 0 0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
x x x x
R3
0 0 0 0 4 3 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
x x x x
12345678
Memory
12345678
Memory
1234567C
4 3 2 1
1234567C
4 3 2 1
Before execution
250
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.84
FR80 Family
7.84
LDUH (Load Halfword Data in Memory to Register)
Extends with zeros the half-word data at memory address "R14 + o8 × 2", loads to "Ri".
The value "o8" is a signed calculation. The value of (o8 × 2) is specified in "disp9".
● Assembler Format
LDUH @(R14, disp9), Ri
● Operation
extu((R14+o8 × 2)) → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Load instruction, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
1
0
0
o8
FUJITSU SEMICONDUCTOR LIMITED
Ri
251
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.84
FR80 Family
● Execution Example
LDUH @(R14,2), R3
; Bit pattern of the instruction: 0100 0000 0001 0011
R3
x x x x
x x x x
R14
1 2 3 4 5 6 7 8
R3
0 0 0 0 4 3 2 1
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567A
4 3 2 1
1234567A
4 3 2 1
Before execution
252
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.85
FR80 Family
7.85
LEAVE (Leave Function)
This instruction is used for stack frame release processing for high level languages.
● Assembler Format
LEAVE
● Operation
R14+4 → R15
(R15-4) → R14
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
b cycle(s)
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
1
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
253
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.85
FR80 Family
● Execution Example
LEAVE
; Bit pattern of the instruction: 1001 1111 1001 0000
R14
7 F F F F F F 4
R14
8 0 0 0
R15
7 F F F F F E C
R15
7 F F F F F F 8
Memory
Memory
7FFFFFEC
x x x x
x x x x
7FFFFFEC
x x x x
x x x x
7FFFFFF0
x x x x
x x x x
7FFFFFF0
x x x x
x x x x
7FFFFFF4
8 0 0 0
0 0 0 0
7FFFFFF4
8 0 0 0
0 0 0 0
7FFFFFF8
x x x x
x x x x
7FFFFFF8
x x x x
x x x x
7FFFFFFC
x x x x
x x x x
7FFFFFFC
x x x x
x x x x
80000000
x x x x
x x x x
80000000
x x x x
x x x x
Before execution
254
0 0 0 0
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.86
FR80 Family
7.86
LSL (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
● Assembler Format
LSL Rj, Ri
● Operation
Ri << Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
1
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
255
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.86
FR80 Family
● Execution Example
LSL R2, R3
; Bit pattern of the instruction: 1011 0110 0010 0011
R2
0 0 0 0
0 0 0 8
R2
0 0 0 0 0 0 0 8
R3
F F F F F F F F
R3
F F F F F F 0 0
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
256
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.87
FR80 Family
7.87
LSL (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "u4" bits, stores the result to "Ri".
● Assembler Format
LSL #u4, Ri
● Operation
Ri << u4 → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
1
0
0
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
257
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.87
FR80 Family
● Execution Example
LSL #8, R3
R3
; Bit pattern of the instruction: 1011 0100 1000 0011
F F F F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
258
F F F F F F 0 0
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.88
FR80 Family
7.88
LSL2 (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "u4 + 16" bits, stores the result to
"Ri".
● Assembler Format
LSL2 #u4, Ri
● Operation
Ri << {u4+16} → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
1
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
259
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.88
FR80 Family
● Execution Example
LSL2 #8, R3
R3
; Bit pattern of the instruction: 1011 0101 1000 0011
F F F F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
260
F F 0 0 0 0 0 0
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.89
FR80 Family
7.89
LSR (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
● Assembler Format
LSR Rj, Ri
● Operation
Ri >> Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
261
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.89
FR80 Family
● Execution Example
LSR R2, R3
; Bit pattern of the instruction: 1011 0010 0010 0011
R2
0 0 0 0
0 0 0 8
R2
0 0 0 0 0 0 0 8
R3
F F F F F F F F
R3
0 0 F F F F F F
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
262
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.90
FR80 Family
7.90
LSR (Logical Shift to the Right Direction)
Makes a logical left shift of the word data in "Ri" by "u4" bits, stores the result to "Ri".
● Assembler Format
LSR #u4, Ri
● Operation
Ri >> u4 → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
0
0
0
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
263
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.90
FR80 Family
● Execution Example
LSR #8, R3
R3
; Bit pattern of the instruction: 1011 0000 1000 0011
F F F F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
264
0 0 F F F F F F
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.91
FR80 Family
7.91
LSR2 (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "u4 + 16" bits, stores the result to
"Ri".
● Assembler Format
LSR2 #u4, Ri
● Operation
Ri >> {u4+16} → Ri
● Flag Change
N
C
Z
C
V
-
C
C
N: Cleared
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
● Classification
Shift instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
0
0
1
u4
FUJITSU SEMICONDUCTOR LIMITED
Ri
265
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.91
FR80 Family
● Execution Example
LSR2 #8, R3
R3
; Bit pattern of the instruction: 1011 0001 1000 0011
F F F F F F F F
R3
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
266
0 0 0 0 0 0 F F
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.92
FR80 Family
7.92
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data in "Rj" to "Ri".
● Assembler Format
MOV Rj, Ri
● Operation
Rj → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Inter-register transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
0
1
0
1
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
267
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.92
FR80 Family
● Execution Example
MOV R2, R3
; Bit pattern of the instruction: 1000 1011 0010 0011
R2
8 7 6 5 4 3 2 1
R2
8 7 6 5 4 3 2 1
R3
x x x x
R3
8 7 6 5 4 3 2 1
x x x x
Before execution
268
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.93
FR80 Family
7.93
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data in dedicated register "Rs" to general-purpose register "Ri".
● Assembler Format
MOV Rs, Ri
● Operation
Rs → Ri
If the number of a non-existent dedicated register is given as "Rs", undefined data will be transferred.
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Inter-Register Transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
1
1
1
Rs
FUJITSU SEMICONDUCTOR LIMITED
Ri
269
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.93
FR80 Family
● Execution Example
MOV MDL, R3
; Bit pattern of the instruction: 1011 0111 0101 0011
R3
x x x x
x x x x
MDL
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
MDL
8 7 6 5 4 3 2 1
Before execution
270
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.94
FR80 Family
7.94
MOV (Move Word Data in Program Status Register to
Destination Register)
Moves the word data in the program status (PS) to general-purpose register "Ri".
● Assembler Format
MOV PS, Ri
● Operation
PS → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Inter-Register Transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
271
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.94
FR80 Family
● Execution Example
MOV PS, R3
; Bit pattern of the instruction: 0001 0111 0001 0011
R3
x x x x x x x x
R3
F F F 8 F 8 C 0
PS
F F F 8 F 8 C 0
PS
F F F 8 F 8 C 0
Before execution
272
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.95
FR80 Family
7.95
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data of general-purpose register "Ri" to dedicated register "Rs".
● Assembler Format
MOV Ri, Rs
● Operation
Ri → Rs
If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Inter-Register Transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
0
0
1
1
Rs
FUJITSU SEMICONDUCTOR LIMITED
Ri
273
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.95
FR80 Family
● Execution Example
MOV R3, MDL
; Bit pattern of the instruction: 1011 0011 0101 0011
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
MDL
x x x x
MDL
8 7 6 5 4 3 2 1
x x x x
Before execution
274
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.96
FR80 Family
7.96
MOV (Move Word Data in Source Register to Program
Status Register)
Stores the word data of general-purpose register "Ri" to program status (PS).
● Assembler Format
MOV Ri, PS
● Operation
Ri → PS
At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range
16 to 31, only new "ILM" settings between 16 and 31 can be entered. If data in the range 0 to 15 is loaded
from "Ri", the value +16 will be added to that data before being transferred to the "ILM". If the original
"ILM" value is in the range 0 to 15, then any value from 0 to 31 can be transferred to the "ILM".
● Flag Change
N
C
Z
C
V
C
C
C
N, Z, V, C: Data from Ri is transferred.
● Classification
Inter-Register Transfer instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
0
0
1
1
1
0
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
Ri
275
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.96
FR80 Family
● Execution Example
MOV R3, PS
; Bit pattern of the instruction: 0000 0111 0001 0011
R3
F F F 3 F 8 D 5
R3
F F F 3 F 8 D 5
PS
x x x x
PS
F F F 3 F 8 D 5
x x x x
Before execution
276
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.97
FR80 Family
7.97
MUL (Multiply Word Data)
Multiplies the word data in "Rj" by the word data in "Ri" as signed numbers, and stores
the resulting signed 64-bit data with the high word in the multiplication/division register
(MDH), and the low word in the multiplication/division register (MDL).
● Assembler Format
MUL Rj, Ri
● Operation
Ri × Rj → MDH, MDL
● Flag Change
N
C
Z
C
V
C
C
-
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Cleared when the operation result is in the range -2147483648 to 2147483647, cleared otherwise.
C: Unchanged
● Classification
Multiply/Divide Instruction
● Execution Cycles
5 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
1
1
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
277
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.97
FR80 Family
● Execution Example
MUL R2, R3
; Bit pattern of the instruction: 1010 1111 0010 0011
R2
0 0 0 0 0 0 0 2
R2
0 0 0 0 0 0 0 2
R3
8 0 0 0 0 0 0 1
R3
8 0 0 0 0 0 0 1
MDH
x x x x
x x x x
MDH
F F F F F F F F
MDL
x x x x
x x x x
MDL
0 0 0 0 0 0 0 2
N Z V C
N Z V C
CCR
0 0 0 0
CCR
Before execution
278
FUJITSU SEMICONDUCTOR LIMITED
0 0 1 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.98
FR80 Family
7.98
MULH (Multiply Halfword Data)
Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the
lower 16 bits of "Ri" as signed numbers, and stores the resulting signed 32-bit data in
the multiplication/division register (MDL). The multiplication/division register (MDH) is
undefined.
● Assembler Format
MULH Rj, Ri
● Operation
Ri × Rj → MDL
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when "MDL" of the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Multiply/Divide Instruction
● Execution Cycles
3 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
1
1
1
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
279
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.98
FR80 Family
● Execution Example
MULH R2, R3
; Bit pattern of the instruction: 1011 1111 0010 0011
R2
F E D C B A 9 8
R2
F E D C B A 9 8
R3
0 1 2 3 4 5 6 7
R3
0 1 2 3 4 5 6 7
MDH
x x x x
x x x x
MDH
x x x x
MDL
x x x x
x x x x
MDL
E D 2 F 0 B 2 8
N Z V C
N Z V C
CCR
0 0 0 0
CCR
Before execution
280
x x x x
FUJITSU SEMICONDUCTOR LIMITED
1 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.99
FR80 Family
7.99
MULU (Multiply Unsigned Word Data)
Multiplies the word data in "Rj" by the word data in "Ri" as unsigned numbers and
stores the resulting unsigned 64-bit data with the high word in the multiplication/
division register (MDH), and the low word in the multiplication/division register (MDL).
● Assembler Format
MULU Rj, Ri
● Operation
Ri × Rj → MDH, MDL
● Flag Change
N
C
Z
C
V
C
C
-
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the "MDL" of the operation result is "0", cleared otherwise.
V: Cleared when the operation result is in the range 0 to 4294967295, set otherwise.
C: Unchanged
● Classification
Multiply/Divide Instruction
● Execution Cycles
5 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
0
1
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
281
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.99
FR80 Family
● Execution Example
MULU R2, R3
; Bit pattern of the instruction: 1010 1011 0010 0011
R2
0 0 0 0 0 0 0 2
R2
0 0 0 0 0 0 0 2
R3
8 0 0 0 0 0 0 1
R3
8 0 0 0 0 0 0 1
MDH
x x x x
x x x x
MDH
0 0 0 0 0 0 0 1
MDL
x x x x
x x x x
MDL
0 0 0 0 0 0 0 2
N Z V C
N Z V C
CCR
0 0 0 0
CCR
Before execution
282
FUJITSU SEMICONDUCTOR LIMITED
0 0 1 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.100
FR80 Family
7.100
MULUH (Multiply Unsigned Halfword Data)
Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the
lower 16 bits of "Ri" as unsigned numbers, and stores the resulting unsigned 32-bit
data in the multiplication/division register (MDL). The multiplication/division register
(MDH) is undefined.
● Assembler Format
MULUH Rj, Ri
● Operation
Ri × Rj → MDL
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the "MDL" of the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Multiply/Divide Instruction
● Execution Cycles
3 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
1
1
0
1
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.100
FR80 Family
● Execution Example
MULUH R2, R3
; Bit pattern of the instruction: 1011 1011 0010 0011
R2
F E D C B A 9 8
R2
F E D C B A 9 8
R3
0 1 2 3 4 5 6 7
R3
0 1 2 3 4 5 6 7
MDH
x x x x
x x x x
MDH
x x x x
MDL
x x x x
x x x x
MDL
3 2 9 6 0 B 2 8
N Z V C
N Z V C
CCR
0 0 0 0
CCR
Before execution
284
x x x x
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.101
FR80 Family
7.101
NOP (No Operation)
This instruction performs no operation.
● Assembler Format
NOP
● Operation
No operation
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
1
0
1
0
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
285
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.101
FR80 Family
● Execution Example
NOP
PC
; Bit pattern of the instruction: 1001 1111 1010 0000
8 3 4 3 8 3 4 A
PC
Before execution
286
FUJITSU SEMICONDUCTOR LIMITED
8 3 4 3 8 3 4 C
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.102
FR80 Family
7.102
OR (Or Word Data of Source Register to Data in Memory)
Takes the logical OR of the word data at memory address "Ri" and the word data in "Rj",
stores the results to the memory address corresponding to "Ri".
● Assembler Format
OR Rj,@Ri
● Operation
(Ri) | Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
287
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.102
FR80 Family
● Execution Example
OR R2,@R3
; Bit pattern of the instruction: 1001 0100 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
1 0 1 0 1 0 1 0
Memory
12345678
1234567C
1234567C
N Z V C
CCR
0 0 0 0
Before execution
288
1 1 1 1 1 0 1 0
FUJITSU SEMICONDUCTOR LIMITED
N Z V C
CCR
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.103
FR80 Family
7.103
OR (Or Word Data of Source Register to Destination
Register)
Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the
results to "Ri".
● Assembler Format
OR Rj, Ri
● Operation
Ri | Rj → Ri
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
0
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.103
FR80 Family
● Execution Example
OR R2, R3
; Bit pattern of the instruction: 1001 0010 0010 0011
R2
1 1 1 1 0 0 0 0
R2
1 1 1 1 0 0 0 0
R3
1 0 1 0 1 0 1 0
R3
1 1 1 1 1 0 1 0
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
290
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.104
FR80 Family
7.104
ORB (Or Byte Data of Source Register to Data in Memory)
Takes the logical OR of the byte data at memory address "Ri" and the byte data in “Rj”,
stores the results to the memory address corresponding to "Ri".
● Assembler Format
ORB Rj,@Ri
● Operation
(Ri) | Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit7) of the operation result is "1", cleared when the MSB(bit7) is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
291
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.104
FR80 Family
● Execution Example
ORB R2,@R3
; Bit pattern of the instruction: 1001 0110 0010 0011
R2
0 0 0 0 0 0 1 1
R2
0 0 0 0 0 0 1 1
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
Memory
12345678
1 0
12345679
12345679
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
292
1 1
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.105
FR80 Family
7.105
ORCCR (Or Condition Code Register and Immediate Data)
Takes the logical OR of the byte data in the condition code register (CCR) and the
immediate data, and returns the results in to the "CCR".
● Assembler Format
ORCCR #u8
● Operation
CCR | u8 → CCR
● Flag Change
S
C
I
C
N
C
Z
C
V
C
C
C
S, I, N, Z, V, C: Varies according to results of calculation.
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
0
1
1
u8
FUJITSU SEMICONDUCTOR LIMITED
293
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.105
FR80 Family
● Execution Example
ORCCR #10H
; Bit pattern of the instruction: 1001 0011 0001 0000
S I N Z V C
CCR
0 0 0 1 0 1
S I N Z V C
CCR
Before execution
294
FUJITSU SEMICONDUCTOR LIMITED
0 1 0 1 0 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.106
FR80 Family
7.106
ORH (Or Halfword Data of Source Register to Data in
Memory)
Takes the logical OR if the half-word data at memory address "Ri" and the half-word
data in "Rj", stores the results to the memory address corresponding to "Ri".
● Assembler Format
ORH Rj,@Ri
● Operation
(Ri) | Rj → (Ri)
● Flag Change
N
C
Z
C
V
-
C
-
N: Set when the MSB(bit15) of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V, C: Unchanged
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
295
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.106
FR80 Family
● Execution Example
ORH R2,@R3
; Bit pattern of the instruction: 1001 0101 0010 0011
R2
0 0 0 0 1 1 0 0
R2
0 0 0 0 1 1 0 0
R3
1 2 3 4 5 6 7 8
R3
1 2 3 4 5 6 7 8
Memory
12345678
Memory
12345678
1 0 1 0
1234567A
1234567A
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
296
1 1 1 0
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.107
FR80 Family
7.107
RET (Return from Subroutine)
This is a branching instruction with no delay slot. Branches to the address indicated by
the return pointer. Used for return from Subroutine.
● Assembler Format
RET
● Operation
RP → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Non-Delayed Branching instruction
● Execution Cycles
2 cycles
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
0
1
0
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
297
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.107
FR80 Family
● Execution Example
RET
; Bit pattern of the instruction: 1001 0111 0010 0000
PC
F F F 0 8 8 2 0
PC
8 0 0 0 A E 8 6
RP
8 0 0 0 A E 8 6
RP
8 0 0 0 A E 8 6
Before execution
298
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.108
FR80 Family
7.108
RET:D (Return from Subroutine)
This is a branching instruction with a delay slot. Branches to the address indicated by
the return pointer (RP). Used for return from Subroutine.
● Assembler Format
RET:D
● Operation
RP → PC
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Delayed Branching instruction
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
0
1
1
1
1
1
0
0
1
0
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
299
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.108
FR80 Family
● Execution Example
RET:D
; Bit pattern of the instruction: 1001 1111 0010 0000
MOV R0, R1
; Instruction placed in delay slot
R0
0 0 1 1 2 2 3 3
R0
0 0 1 1 2 2 3 3
R1
x x x x x x x x
R1
0 0 1 1 2 2 3 3
PC
F F F 0 8 8 2 0
PC
8 0 0 0 A E 8 6
RP
8 0 0 0 A E 8 6
RP
8 0 0 0 A E 8 6
Before execution of "RET" instruction
After branching
The instruction placed in delay slot will be executed before execution of the branch destination instruction.
The value of "R1" above will vary according to the specifications of the "MOV" instruction placed in the
delay slot.
300
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.109
FR80 Family
7.109
RETI (Return from Interrupt)
Loads data from the stack indicated by system stack pointer (SSP), to the program
counter (PC) and program status (PS), and retakes control from the EIT operation
handler.
● Assembler Format
RETI
● Operation
(SSP) → PC
SSP+4 → SSP
(SSP) → PS
SSP+4 → SSP
At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range
16 to 31, only new "ILM" settings between 16 and 31 can be entered. If data in the range 0 to 15 is loaded
in memory, the value 16 will be added to that data before being transferred to the "ILM". If the original
"ILM" value is in the range 0 to 15, then any value between 0 and 31 can be transferred to the "ILM".
● Flag Change
S
C
I
C
N
C
Z
C
V
C
C
C
S, I, N, Z, V, C: Change according to the values retrieved from the stack.
● Classification
Non-Delayed Branching instruction
● Execution Cycles
1+2b cycles
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
301
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.109
FR80 Family
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
● Execution Example
RETI
; Bit pattern of the instruction: 1001 0111 0011 0000
R15
7 F F F F F F 8
R15
4 0 0 0 0 0 0 0
SSP
7 F F F F F F 8
SSP
8 0 0 0 0 0 0 0
USP
4 0 0 0 0 0 0 0
USP
4 0 0 0 0 0 0 0
PC
F F 0 0 9 0 B C
PC
8 0 8 8 8 0 8 8
PS
F F F 0 F 8 D 4
PS
F F F 3 F 8 F 1
ILM
1 0 0 0 0
ILM
S I N Z V C
CCR
S I N Z V C
0 1 0 1 0 0
CCR
Memory
1 1 0 0 0 1
Memory
7FFFFFF8
8 0 8 8 8 0 8 8
7FFFFFF8
8 0 8 8 8 0 8 8
7FFFFFFC
F F F 3 F 8 F 1
7FFFFFFC
F F F 3 F 8 F 1
80000000
x x x x x x x x
80000000
x x x x x x x x
Before execution
302
1 0 0 1 1
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.110
FR80 Family
7.110
SRCH0 (Search First Zero bit position distance From MSB)
This is a "0" search instruction used for bit searching. Takes a comparison of word
data in "Ri" from MSB (bit31) and "0", stores the distance in "Ri" from the first "0" that
is found and bit MSB (bit31).
● Assembler Format
SRCH0 Ri
● Operation
search_zero(Ri) → Ri
If “0” bit is not found (in case all word data of Ri is "1" bit), "32" is stored in "Ri". In case MSB(bit31) is
"0", "0" is stored in "Ri" and "31" is stored in "Ri" when LSB (bit0) is "0" and other bits are "1".
The "Ri" bit pattern before execution of instruction its relation with the values stored in "Ri" is shown in
Table 7.110-1.
Table 7.110-1 Input pattern of SRCH0 instruction and its results
Input ("Ri" bit pattern before execution of instruction)
Result
Remarks
11111111_11111111_11111111_11111111
32
Not found
0xxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
0
MSB(bit31) was "1"
10xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
1
110xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
2
1110xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
3
...
11111111_11111111_11111111_11110xxx
28
11111111_11111111_11111111_111110xx
29
11111111_11111111_11111111_1111110x
30
11111111_11111111_11111111_11111110
31
Only LSB(bit0) was "0"
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
303
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.110
FR80 Family
● Classification
Bit Search instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
0
LSB
0
1
0
1
1
1
1
1
0
0
Ri
● Execution Example
SRCH0 R2
R2
; Bit pattern of the instruction: 1001 0111 1100 0010
F C 3 4 5 6 7 8
R2
Before execution
304
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 0 0 0 6
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.111
FR80 Family
7.111
SRCH1 (Search First One bit position distance From MSB)
This is a "1" search instruction used for bit searching. Takes a comparison of word
data in "Ri" from MSB (bit31) and "1", stores the distance in "Ri" from the first "1" that
is found and bit MSB(bit31).
● Assembler Format
SRCH1 Ri
● Operation
search_one(Ri) → Ri
If "1" bit is not found (in case all word data of Ri is "0" bit), 32 is stored in "Ri". In case MSB(bit31) is
"1", 0 is stored in "“Ri" and "31" is stored in "Ri" when LSB (bit0) is "1" and other bits are "0".
The "Ri" bit pattern before execution of instruction its relation with the values stored in "Ri" is shown in
Table 7.111-1.
Table 7.111-1 Input bit pattern of SRCH1 instruction and its results
Input ("Ri" bit pattern before execution of the instruction)
Results
Remarks
00000000_00000000_00000000_00000000
32
Not found
1xxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
0
MSB(bit31) was "0"
01xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
1
001xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
2
0001xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
3
...
00000000_00000000_00000000_00001xxx
28
00000000_00000000_00000000_000001xx
29
00000000_00000000_00000000_0000001x
30
00000000_00000000_00000000_00000001
31
Only LSB(bit0) was "0"
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
305
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.111
FR80 Family
● Classification
Bit Search instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
1
1
0
1
Ri
● Execution Example
SRCH1 R2
R2
; Bit pattern of the instruction: 1001 0111 1101 0010
0 0 3 4 5 6 7 8
R2
Before execution
306
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 0 0 0 A
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.112
FR80 Family
7.112
SRCHC (Search First bit value change position distance
From MSB)
This is a "Change point" search instruction used for bit searching. Takes a comparison
of data in "Ri" with MSB (bit31), stores in "Ri" the distance from the first varying bit
value that is found and bit MSB (bit31).
● Assembler Format
SRCHC Ri
● Operation
search_change(Ri) → Ri
If the values of all bits are the same, 32 is stored in "Ri". In case the values of MSB (bit31) the adjacent
"bit30" is different, 1 is stored in "Ri" and 31 is stored in "Ri" when only the value of LSB (bit0) is
different.
The "Ri" bit pattern before execution of instruction its relation with the values stored in "Ri" is shown in
Table 7.112-1.
Table 7.112-1 Input bit pattern of SRCHC instruction and its results
Input ("Ri" bit pattern before execution of instruction)
Results
Remarks
00000000_00000000_00000000_00000000
11111111_11111111_11111111_11111111
32
Not found
01xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
10xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
1
Difference between bit value of
MSB(bit31) and bit30
001xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
110xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
2
0001xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
1110xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
3
00001xxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
11110xxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
4
...
00000000_00000000_00000000_00001xxx
11111111_11111111_11111111_11110xxx
28
00000000_00000000_00000000_000001xx
11111111_11111111_11111111_111110xx
29
00000000_00000000_00000000_0000001x
11111111_11111111_11111111_1111110x
30
00000000_00000000_00000000_00000001
11111111_11111111_11111111_11111110
31
Bit value of only LSB(bit0) is
different
* The value of result (Ri) can not become 0.
CM71-00104-3E
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307
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.112
FR80 Family
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Bit Search instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
LSB
0
0
1
0
1
1
1
1
1
1
0
Ri
● Execution Example
SRCHC R2
R2
; Bit pattern of the instruction: 1001 0111 1110 0010
F F 3 4 5 6 7 8
R2
Before execution
308
FUJITSU SEMICONDUCTOR LIMITED
0 0 0 0 0 0 0 8
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.113
FR80 Family
7.113
ST (Store Word Data in Register to Memory)
Loads word data in "Ri" to memory address "Rj".
● Assembler Format
ST Ri,@Rj
● Operation
Ri → (Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
309
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.113
FR80 Family
● Execution Example
ST R3,@R2
; Bit pattern of the instruction: 0001 0100 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
Memory
12345678
x x x x x x x x
Memory
12345678
Before execution
310
FUJITSU SEMICONDUCTOR LIMITED
8 7 6 5 4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.114
FR80 Family
7.114
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "R13 + Rj".
● Assembler Format
ST Ri,@(R13, Rj)
● Operation
Ri → (R13+Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
0
0
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
311
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.114
FR80 Family
● Execution Example
ST R3,@(R13, R2)
; Bit pattern of the instruction: 0001 0000 0010 0011
R2
0 0 0 0 0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
12345678
1234567C
Memory
x x x x x x x x
12345678
Memory
1234567C
8 7 6 5 4 3 2 1
Before execution
312
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After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.115
FR80 Family
7.115
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "R14 + o8 × 4". The value "o8" is a
signed calculation. The value of "o8 × 4" is specified in "disp10".
● Assembler Format
ST Ri,@(R14, disp10)
● Operation
Ri → (R14+o8 × 4)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
1
1
o8
FUJITSU SEMICONDUCTOR LIMITED
Ri
313
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.115
FR80 Family
● Execution Example
ST R3,@(R14,4)
; Bit pattern of the instruction: 0011 0000 0001 0011
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
R14
1 2 3 4 5 6 7 8
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567C
x x x x x x x x
1234567C
8 7 6 5 4 3 2 1
Before execution
314
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.116
FR80 Family
7.116
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "R15 + u4 × 4". The value "u4" is an
unsigned calculation. The value of "u4 × 4" is specified in "udisp6".
● Assembler Format
ST Ri,@(R15, udisp6)
● Operation
Ri → (R15+u4 × 4)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
0
1
1
u4
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.116
FR80 Family
● Execution Example
ST R3,@(R15,4)
; Bit pattern of the instruction: 0001 0011 0001 0011
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
R15
1 2 3 4 5 6 7 8
R15
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567C
x x x x x x x x
1234567C
8 7 6 5 4 3 2 1
Before execution
316
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After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.117
FR80 Family
7.117
ST (Store Word Data in Register to Memory)
Subtracts 4 from the value of "R15", stores the word data in "Ri" to the memory address
indicated by the new value of "R15". If "R15" is given as the parameter "Ri", the data
transfer will use the value of "R15" before subtraction.
● Assembler Format
ST Ri,@-R15
● Operation
R15 - 4 → R15
Ri → (R15)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
1
1
0
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
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317
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.117
FR80 Family
● Execution Example
ST R3,@-R15
; Bit pattern of the instruction: 0001 0111 0000 0011
R3
8 7 6 5 4 3 2 1
R3
8 7 6 5 4 3 2 1
R15
1 2 3 4 5 6 7 8
R15
1 2 3 4 5 6 7 4
Memory
12345674
x x x x x x x x
12345678
Memory
12345674
12345678
Before execution
318
8 7 6 5 4 3 2 1
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.118
FR80 Family
7.118
ST (Store Word Data in Register to Memory)
Subtracts 4 from the value "R15", stores the word data in dedicated register "Rs" to the
memory address indicated by the new value of "R15".
● Assembler Format
ST Rs,@-R15
● Operation
R15 - 4 → R15
Rs → (R15)
If the number of a non-existent dedicated register is specified in parameter "Rs", the read value will be
ignored.
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
0
0
FUJITSU SEMICONDUCTOR LIMITED
Rs
319
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.118
FR80 Family
● Execution Example
ST MDH,@-R15
; Bit pattern of the instruction: 0001 0111 1000 0100
R15
1 2 3 4 5 6 7 8
R15
1 2 3 4 5 6 7 4
MDH
8 7 6 5 4 3 2 1
MDH
8 7 6 5 4 3 2 1
12345670
Memory
12345670
Memory
12345674
x x x x x x x x
12345674
8 7 6 5 4 3 2 1
Before execution
320
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.119
FR80 Family
7.119
ST (Store Word Data in Program Status Register to
Memory)
Subtracts 4 from the value of "R15", stores the word data in the program status (PS) to
the memory address indicated by the new value of "R15".
● Assembler Format
ST PS,@-R15
● Operation
R15 - 4 → R15
PS → (R15)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
1
1
1
0
0
1
FUJITSU SEMICONDUCTOR LIMITED
0
0
0
0
321
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.119
FR80 Family
● Execution Example
ST PS,@-R15
; Bit pattern of the instruction: 0001 0111 1001 0000
R15
1 2 3 4 5 6 7 8
R15
1 2 3 4 5 6 7 4
PS
F F F 8 F 8 C 0
PS
F F F 8 F 8 C 0
12345670
Memory
12345670
12345674
x x x x x x x x
12345674
Before execution
322
FUJITSU SEMICONDUCTOR LIMITED
Memory
F F F 8 F 8 C 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.120
FR80 Family
7.120
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "Rj".
● Assembler Format
STB Ri,@Rj
● Operation
Ri → (Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
1
0
Rj
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.120
FR80 Family
● Execution Example
STB R3,@R2
; Bit pattern of the instruction: 0001 0110 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
0 0 0 0 0 0 2 1
R3
0 0 0 0 0 0 2 1
Memory
12345678
x x
Memory
12345678
Before execution
324
FUJITSU SEMICONDUCTOR LIMITED
2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.121
FR80 Family
7.121
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "R13 + Rj".
● Assembler Format
STB Ri,@(R13, Rj)
● Operation
Ri → (R13+Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
0
LSB
0
1
0
0
1
0
Rj
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.121
FR80 Family
● Execution Example
STB R3,@(R13, R2)
; Bit pattern of the instruction: 0001 0010 0010 0011
R2
0 0 0 0 0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
0 0 0 0 0 0 2 1
R3
0 0 0 0 0 0 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
1234567B
Memory
1234567B
Memory
1234567C
x x
1234567C
2 1
Before execution
326
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.122
FR80 Family
7.122
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "R14 + o8". The value "o8" is a signed
calculation. The value of "o8" is specified in "disp8".
● Assembler Format
STB Ri,@(R14, disp8)
● Operation
Ri → (R14+o8)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
1
1
1
o8
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Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.122
FR80 Family
● Execution Example
STB R3,@(R14,1)
; Bit pattern of the instruction: 0111 0000 0001 0011
R3
0 0 0 0 0 0 2 1
R3
0 0 0 0 0 0 2 1
R14
1 2 3 4 5 6 7 8
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
12345679
x x
12345679
2 1
Before execution
328
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.123
FR80 Family
7.123
STH (Store Halfword Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "Rj".
● Assembler Format
STH Ri,@Rj
● Operation
Ri → (Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
1
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
329
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.123
FR80 Family
● Execution Example
STH R3,@R2
; Bit pattern of the instruction: 0001 0101 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
0 0 0 0 4 3 2 1
R3
0 0 0 0 4 3 2 1
Memory
12345678
x x x x
Memory
12345678
Before execution
330
FUJITSU SEMICONDUCTOR LIMITED
4 3 2 1
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.124
FR80 Family
7.124
STH (Store Halfword Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "R13 + Rj".
● Assembler Format
STH Ri,@(R13, Rj)
● Operation
Ri → (R13+Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
0
0
1
0
0
0
1
Rj
FUJITSU SEMICONDUCTOR LIMITED
Ri
331
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.124
FR80 Family
● Execution Example
STH R3,@(R13, R2)
; Bit pattern of the instruction: 0001 0001 0010 0011
R2
0 0 0 0 0 0 0 4
R2
0 0 0 0 0 0 0 4
R3
0 0 0 0 4 3 2 1
R3
0 0 0 0 4 3 2 1
R13
1 2 3 4 5 6 7 8
R13
1 2 3 4 5 6 7 8
1234567A
Memory
1234567A
Memory
1234567C
x x x x
1234567C
4 3 2 1
Before execution
332
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.125
FR80 Family
7.125
STH (Store Halfword Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "R14 + o8 × 2". The value of "o8 ×
2" is specified in "disp9".
● Assembler Format
STH Ri,@(R14, disp9)
● Operation
Ri → (R14+o8×2)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Memory Store instruction, Instruction with delay slot
● Execution Cycles
a cycle(s)
● Instruction Format
MSB
0
CM71-00104-3E
LSB
1
0
1
o8
FUJITSU SEMICONDUCTOR LIMITED
Ri
333
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.125
FR80 Family
● Execution Example
STH R3,@(R14,2)
; Bit pattern of the instruction: 0101 0000 0001 0011
R3
0 0 0 0 4 3 2 1
R3
0 0 0 0 4 3 2 1
R14
1 2 3 4 5 6 7 8
R14
1 2 3 4 5 6 7 8
12345678
Memory
12345678
Memory
1234567A
x x x x
1234567A
4 3 2 1
Before execution
334
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.126
FR80 Family
7.126
STILM (Set Immediate Data to Interrupt Level Mask
Register)
Transfers the immediate data to the interrupt level mask register (ILM) in the program
status (PS).
● Assembler Format
STILM #u8
● Operation
if (ILM < 16)
u8 → ILM
else if (u8 < 16)
u8+16 → ILM
else
u8 → ILM
Only the lower 5 bits (bit4 to bit0) of the immediate data are valid. At the time this instruction is executed,
if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM" settings
between 16 and 31 can be entered. If the value "u8" is in the range 0 to 15, the value 16 will be added to
that data before being transferred to the "ILM". If the original "ILM" value is in the range 0 to 15, then any
value between 0 and 31 can be transferred to the "ILM".
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Instruction with delay slot
● Execution Cycles
1 cycle
CM71-00104-3E
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335
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.126
FR80 Family
● Instruction Format
MSB
1
LSB
0
0
0
0
1
1
1
u8
● Execution Example
STILM #14H
ILM
; Bit pattern of the instruction: 1000 0111 0001 0100
1 1 1 1 1
ILM
Before execution
336
FUJITSU SEMICONDUCTOR LIMITED
1 0 1 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.127
FR80 Family
7.127
STM0 (Store Multiple Registers)
The "STM0" instruction stores the word data from multiple registers specified in
"reglist" (from R0 to R7) and repeats the operation of storing the result in address
"R15" after subtracting the value of 4 from "R15". Registers are processed in ascending
order.
● Assembler Format
STM0 (reglist)
Registers from R0 to R7 are separated by ",", arranged and specified in "reglist".
● Operation
The following operations are repeated according to the number of registers in "reglist".
R15-4 → R15
Ri → (R15)
The bit values and register numbers for "reglist" (STM0) are shown in Table 7.127-1.
Table 7.127-1 Bit values and register numbers for "reglist" (STM0)
Bit
Register
7
R0
6
R1
5
R2
4
R3
3
R4
2
R5
1
R6
0
R7
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
337
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.127
FR80 Family
● Classification
Other instructions
● Execution Cycles
If "n" is the number of registers specified in the parameter "reglist", the execution cycles required are as
follows.
When n=0: 1 cycle
Otherwise: a × n cycles
● Instruction Format
MSB
1
LSB
0
0
0
1
1
1
0
reglist
● Execution Example
STM0 (R2, R3)
; Bit pattern of the instruction: 1000 1110 0011 0000
R2
9 0 B C 9 3 6 3
R2
9 0 B C 9 3 6 3
R3
8 3 4 3 8 3 4 A
R3
8 3 4 3 8 3 4 A
R15
7 F F F F F C 8
R15
7 F F F F F C 0
Memory
Memory
7FFFFFC0
x x x x x x x x
7FFFFFC0
9 0 B C 9 3 6 3
7FFFFFC4
x x x x x x x x
7FFFFFC4
8 3 4 3 8 3 4 A
7FFFFFC8
x x x x x x x x
7FFFFFC8
x x x x x x x x
Before execution
338
FUJITSU SEMICONDUCTOR LIMITED
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.128
FR80 Family
7.128
STM1 (Store Multiple Registers)
The "STM1" instruction stores the word data from multiple registers specified in
"reglist" (from R8 to R15) and repeats the operation of storing the result in address
"R15" after subtracting the value of 4 from "R15". Registers are processed in ascending
order. If "R15" is specified in the parameter "reglist", the contents of "R15" retained
before the instruction is executed will be written to memory.
● Assembler Format
STM1 (reglist)
Registers from R8 to R15 are separated by ",", arranged and specified.in "reglist".
● Operation
The following operations are repeated according to the number of registers in "reglist".
R15-4 → R15
Ri → (R15)
The bit values and register numbers for "reglist" (STM1) are shown in Table 7.128-1.
Table 7.128-1 Bit values and register numbers for "reglist" (STM1)
Bit
Register
7
R8
6
R9
5
R10
4
R11
3
R12
2
R13
1
R14
0
R15
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.128
FR80 Family
● Classification
Other instructions
● Execution Cycles
If "n" is the number of registers specified in the parameter "reglist", the execution cycles required are as
follows.
When n=0: 1 cycle
Otherwise: a × n cycles
● Instruction Format
MSB
1
0
LSB
0
0
1
1
1
1
reglist
● Execution Example
STM1 (R10, R11, R12)
; Bit pattern of the instruction: 1000 1111 0011 1000
R10
8 F E 3 9 E 8 A
R10
8 F E 3 9 E 8 A
R11
9 0 B C 9 3 6 3
R11
9 0 B C 9 3 6 3
R12
8 D F 7 8 8 E 4
R12
8 D F 7 8 8 E 4
R15
7 F F F F FC C
R15
7 F F F F F C 0
Memory
Memory
7FFFFFC0
x x x x x x x x
7FFFFFC0
8 F E 3 9 E 8 A
7FFFFFC4
x x x x x x x x
7FFFFFC4
9 0 B C 9 3 6 3
7FFFFFC8
x x x x x x x x
7FFFFFC8
8 D F 7 8 8 E 4
7FFFFFCC
x x x x x x x x
7FFFFFCC
x x x x x x x x
Before execution
340
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After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.129
FR80 Family
7.129
SUB (Subtract Word Data in Source Register from
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", stores the results to "Ri".
● Assembler Format
SUB Rj, Ri
● Operation
Ri - Rj → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
1
0
0
Rj
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Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.129
FR80 Family
● Execution Example
SUB R2, R3
; Bit pattern of the instruction: 1010 1100 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
9 9 9 9 9 9 9 9
R3
8 7 6 5 4 3 2 1
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
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1 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.130
FR80 Family
7.130
SUBC (Subtract Word Data in Source Register and Carry
bit from Destination Register)
Subtracts word data in "Rj" and carry flag (C) from "Ri", stores the results to "Ri".
● Assembler Format
SUBC Rj, Ri
● Operation
Ri - Rj - C → Ri
● Flag Change
N
C
Z
C
V
C
C
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0"
Z: Set when the operation result is "0", cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when an borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
1
0
1
Rj
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Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.130
FR80 Family
● Execution Example
SUBC R2, R3
; Bit pattern of the instruction: 1010 1101 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
9 9 9 9 9 9 9 9
R3
8 7 6 5 4 3 2 0
N Z V C
CCR
0 0 0 1
N Z V C
CCR
Before execution
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1 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.131
FR80 Family
7.131
SUBN (Subtract Word Data in Source Register from
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri" without
changing the flag settings.
● Assembler Format
SUBN Rj, Ri
● Operation
Ri - Rj → Ri
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Add/Subtract instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
MSB
1
CM71-00104-3E
LSB
0
1
0
1
1
1
0
Rj
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Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.131
FR80 Family
● Execution Example
SUBN R2, R3
; Bit pattern of the instruction: 1010 1110 0010 0011
R2
1 2 3 4 5 6 7 8
R2
1 2 3 4 5 6 7 8
R3
9 9 9 9 9 9 9 9
R3
8 7 6 5 4 3 2 1
N Z V C
CCR
0 0 0 0
N Z V C
CCR
Before execution
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0 0 0 0
After execution
CM71-00104-3E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.132
FR80 Family
7.132
XCHB (Exchange Byte Data)
Exchanges the contents of the byte address indicated by "Rj" and those indicated by
"Ri". The lower 8 bits of data originally at "Ri" are transferred to the byte address
indicated by "Rj" and the data originally at "Rj" is extended with zeros and transferred
to "Ri".
● Assembler Format
XCHB @Rj, Ri
● Operation
Ri → TEMP
extu((Rj)) → Ri
TEMP → (Rj)
● Flag Change
N
-
Z
-
V
-
C
-
N, Z, V, C: Unchanged
● Classification
Other instructions, Read/Modify/Write type instruction
● Execution Cycles
2a cycles
● Instruction Format
MSB
1
CM71-00104-3E
0
LSB
0
0
1
0
1
0
Rj
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Ri
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.132
FR80 Family
● Execution Example
XCHB @R1, R0
; Bit pattern of the instruction: 1000 1010 0001 0000
R0
0 0 0 0 0 0 7 8
R0
0 0 0 0 0 0 F D
R1
8 0 0 0 0 0 0 2
R1
8 0 0 0 0 0 0 2
Memory
80000001
x x
80000001
x x
80000002
F D
80000002
7 8
80000003
x x
80000003
x x
Before execution
348
Memory
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After execution
CM71-00104-3E
APPENDIX
It includes Instruction Lists and Instruction Maps of
FR80 Family.
APPENDIX A Instruction Lists
APPENDIX B Instruction Maps
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APPENDIX
APPENDIX A
Instruction Lists
APPENDIX A
FR80 Family
Instruction Lists
It includes Instruction Lists of FR80 Family CPU.
A.1 Meaning of Symbols
A.2 Instruction Lists
A.3 List of Instructions that can be positioned in the Delay Slot
A.4 Instruction List where the number of execution cycles has been changed
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FR80 Family
A.1
APPENDIX A
APPENDIX
Instruction Lists
Meaning of Symbols
This section describes the meaning of symbols used in the Instruction Lists and
Detailed Execution Instructions has been explained.
A.1.1
Mnemonic and Operation Columns
These are the symbols used in Mnemonic and Operation columns of Instruction Lists as well as assembler
format of Detailed Execution Instructions and operation.
i4
It is 4-bit immediate data. 0(0H) to 15(FH) in case of zero extension and -16(0H) to -1(FH) in case of
minus extension can be specified.
Table A.1-1 zero extension and minus extension values of 4-bit immediate data
Specified Value
Bit Pattern
Zero Extension
Minus Extension
0000B
0
-16
0001B
1
-15
0010B
2
-14
...
1101B
13
-3
1110B
14
-2
1111B
15
-1
i8
8-bit immediate data, range 0 (00H) to 255 (FFH)
i20
20-bit immediate data, range 0 (00000H) to 1,048,575 (FFFFFH)
i32
32-bit immediate data, range 0 (0000 0000H) to 4,294,967,295 (FFFF FFFFH)
s8
signed 8-bit immediate data, range -128 (80H) to 127 (7FH)
s10
signed 10-bit immediate data, range -512 (200H) to 508 (1FCH) in multiples of 4
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APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
u4
unsigned 4-bit immediate data, range 0 (0H) to 15 (FH)
u8
unsigned 8-bit immediate data, range 0 (00H) to 255 (FFH)
u10
unsigned 10-bit immediate data, range 0 (000H) to 1020 (3FCH) in multiples of 4
udisp6
unsigned 6-bit address values, range 0 (00H) to 60 (3CH) in multiples of 4
disp8
signed 6-bit address values, range -128 (80H) to 127 (7FH)
disp9
signed 9-bit address values, range -256 (100H) to 254 (0FEH) in multiples of 2
disp10
signed 10-bit address values, range -512 (200H) to 508 (1FCH) in multiples of 4
dir8
Unsigned 8Bit address values, range 0 (00H) to 255 (FFH)
dir9
unsigned 9-bit address values, range 0 (000H) to 510 (1FEH) in multiples of 2
dir10
unsigned 10-bit address values, range 0 (000H) to 1020 (3FCH) in multiples of 4
label9
branch address, range -256 (100H) to 254 (0FEH) in multiples of 2 for the value of Program Counter
(PC) +2
label12
branch address, range -2048 (800H) to 2046 (7FEH) in multiples of 2 for the value of Program Counter
(PC) +2
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APPENDIX A
APPENDIX
Instruction Lists
rel8
signed 8-bit relative address. Result which is double the value of rel8 for the value of Program Counter
(PC) +2 will denote the Branch Destination Address. Range -128 (80H) to 127 (7FH)
rel11
signed 11-bit relative address. Result which is double the value of rel11 for the value of Program
Counter (PC) +2 will denote the Branch Destination Address. Range -1024 (400H) to 1023 (3FFH)
Ri, Rj
Indicates General-purpose Registers (R0 to R15)
Table A.1-2 Specification of General-purpose register based on Rj/Ri
Ri / Rj
Register
Ri / Rj
Register
0000
R0
1000
R8
0001
R1
1001
R9
0010
R2
1010
R10
0011
R3
1011
R11
0100
R4
1100
R12
0101
R5
1101
R13
0110
R6
1110
R14
0111
R7
1111
R15
Rs
Indicates Dedicated Registers (TBR, RP, USP, SSP, MDH, MDL)
Table A.1-3 Specification of Dedicated Register based on Rs
Rs
Register
Rs
0000
Table Base Register (TBR)
1000
0001
Return Pointer (RP)
1001
0010
System Stack Pointer (SSP)
1010
0011
User Stack Pointer (USP)
1011
0100
Multiplication/Division Register (MDH)
1100
0101
Multiplication/Division Register (MDL)
1101
0110
0111
Register
Reserved (Disabled)
1110
Reserved (Disabled)
1111
(reglist)
Indicates 8-bit Register list. Register corresponding to each bit value can be specified.
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APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
Table A.1-4 Correspondence between reglist of LDM0,LDM1Instruction and
General purpose Register
LDM0 Instruction
LDM1Instruction
reglist
Register
reglist
Register
bit0
R0
bit0
R8
bit1
R1
bit1
R9
bit2
R2
bit2
R10
bit3
R3
bit3
R11
bit4
R4
bit4
R12
bit5
R5
bit5
R13
bit6
R6
bit6
R14
bit7
R7
bit7
R15
Table A.1-5 Correspondence between reglist of STM0,STM1Instruction and
General purpose Register
STM0 Instruction
A.1.2
STM1 Instruction
reglist
Register
reglist
Register
bit0
R7
bit0
R15
bit1
R6
bit1
R14
bit2
R5
bit2
R13
bit3
R4
bit3
R12
bit4
R3
bit4
R11
bit5
R2
bit5
R10
bit6
R1
bit6
R9
bit7
R0
bit7
R8
Operation Column
These are symbols used in Operation Column of Instruction Lists and operation of Detailed Execution
Instructions.
extu( )
indicates a zero extension operation, in which portion lacking higher bits is complimented by adding
"0" bit.
extn( )
indicates a minus extension operation, in which portion lacking higher bits is complimented by adding
"1" bit.
exts( )
indicates a sign extension operation, in which zero extension is performed for the data within ( ) if MSB
is "0" and a minus extension is performed if MSB is "1".
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CM71-00104-3E
FR80 Family
APPENDIX A
APPENDIX
Instruction Lists
&
Indicates logical calculation of each bit (AND)
|
Indicates the logical sum of each bit (OR)
^
Indicates Dedicated Logical Sum of each bit (EXOR)
()
Indicates specification of indirect address. It is address memory read/write value of the Register or
formula within ( ).
{}
Indicate the calculation priority. Since ( ) is used for specifying indirect address, different bracket
namely { } is used.
if (Condition) then {formula} or if (condition) then {Formula 1} else {Formula 2}
Indicates the execution of conditions. If the conditions are established, formula after ‘then’ is executed
and when the conditions are not established, formula next to ‘else’ is executed. Formula can be
described variously using the { }.
[m:n]
Bits from m to n are extracted and targeted for operation.
A.1.3
Format Column
Symbols used in the Format Column of the Instruction Lists.
A to H
Indicates the Instruction Formats. A to H correspond to TYPE-A to TYPE-H.
A.1.4
OP Column
Hexadecimal value used in the Instruction Lists. They denote operation codes (OP, SUB-OP). They branch
into the following depending on the Instruction Format.
TYPE-A, TYPE-C, TYPE-D, TYPE-G
2-digit hexadecimal value represents 8-bit OP code
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APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
TYPE-B
2-digit hexadecimal value represents higher 4 bits of OP code with lower 4 bits of 0000B.
TYPE-E, TYPE-E’, TYPE-H
4-digit hexadecimal value represents higher 8 bits of OP code with higher 2 digits, 4-bits of SUB-OP
code with the next 1 digit and the remainder with "0".
TYPE-F
2-digit hexadecimal code represents higher 5 bits of OP code with lower 3 bits of 000B.
A.1.5
CYC Column
Symbols used in CYC Column of Instruction Lists and execution cycles of Detailed Execution Instructions.
Numerical values represent CPU clock cycles. Minimum of a to d is 1 cycle.
a
Memory access cycles. Cycles change depending on the access target. Minimum value is 1 cycle.
b
Memory access cycles. Cycles change depending on the access target. Minimum value is 1 cycle.
It is 1 cycle when uncompleted LD Instructions are less than 4 Instructions and Register which is the
object of load operation is not referred by the subsequent Instruction.
When uncompleted LD Instructions become more than 4 in number, an interlock will be applied from
that point till the completion of first LD Instruction and the number of execution cycles will be
increased by (Memory Access Cycles - Number of cycles from the issue of an Instruction till first LD
Instruction is completed).
When the Register which is target of load operation is referred to by the succeeding Instruction, an
interlock will be applied from that point and the number of execution cycles will increase by (Memory
Access Cycles - Number of cycle from the issue of an Instruction till an instruction refers to the targeted
Register + 1).
c
An interlock will be applied when the immediately next Instruction refers to Multiplication/Division
Register (MDH) and the number of execution cycles will be increased to 2. Otherwise it will be 1
cycle.
d
There will be 2 cycles when pre-fetching of Instruction in the Pre-fetch Buffer is not carried out.
Minimum value is 1 cycle.
356
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CM71-00104-3E
FR80 Family
A.1.6
APPENDIX A
APPENDIX
Instruction Lists
FLAG Column
Symbols used for flag change in the Flag Column of Instruction Lists and Detailed Execution Instructions.
Represents change in Negative Flag (N), Zero Flag (Z), Overflow Flag (V), Carry Flag (C) of the Condition
Code Register (CCR).
C
Varies depending on the result of operation
No change
0
Value becomes "0"
1
Value becomes "1"
A.1.7
RMW Column
Symbols used in the RMW Column of Instruction Lists. It represents whether or not it is Read-ModifyWrite Instruction.
Instruction is not Read-Modify-Write Instruction.
❍
Instruction is Read-Modify-Write Instruction.
A.1.8
Reference Column
Represents the portion explained in "CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS".
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APPENDIX
APPENDIX A
A.2
Instruction Lists
FR80 Family
Instruction Lists
This part indicates Instruction Lists of FR80 Family CPU.
There are a total of 162 instructions in FR80 Family CPU. These instructions are divided into the following
15 categories.
•
Add/Subtract Instructions (10Instructions)
•
Compare Calculation Instructions (3 Instructions)
•
Logical Calculation Instructions (12 Instructions)
•
Bit Operation Instructions (8 Instructions)
•
Multiply/ Divide Instructions (10 Instructions)
•
Shift Instructions (9 Instructions)
•
Immediate Data Transfer Instructions (3 Instructions)
•
Memory Load Instructions (13 Instructions)
•
Memory Store Instructions (13 Instructions)
•
Inter-Register Transfer Instructions/Dedicated Register Transfer Instructions (5 Instructions)
•
Non-delayed Branching Instructions (23 Instructions)
•
Delayed Branching Instructions (20 Instructions)
•
Direct Addressing Instructions (14 Instructions)
•
Bit Search Instructions (3 Instructions)
•
Other Instructions (16 Instructions)
Table A.2-1 Add/Subtract Instructions (10Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
ADD Rj, Ri
A
A6
1
CCCC
-
Ri+Rj → Ri
ADD #i4, Ri
C
A4
1
CCCC
-
Ri+extu(i4) → Ri
i4 is zero extension
7.1
ADD2 #i4, Ri
C
A5
1
CCCC
-
Ri+extn(i4) → Ri
i4 is Minus extension
7.3
ADDC Rj, Ri
A
A7
1
CCCC
-
Ri+Rj+C → Ri
Add with carry
7.4
ADDN Rj, Ri
A
A2
1
----
-
Ri+Rj → Ri
ADDN #i4, Ri
C
A0
1
----
-
Ri+extu(i4) → Ri
i4 is Zero extension
7.5
ADDN2 #i4, Ri
C
A1
1
----
-
Ri+extn(i4) → Ri
i4 is Minus extension
7.7
SUB Rj, Ri
A
AC
1
CCCC
-
Ri-Rj → Ri
SUBC Rj, Ri
A
AD
1
CCCC
-
Ri-Rj-C →Ri
SUBN Rj, Ri
A
AE
1
----
-
Ri-Rj → Ri
Mnemonic
358
Operation
FUJITSU SEMICONDUCTOR LIMITED
Remarks
Reference
7.2
7.6
7.129
Add with carry
7.130
7.131
CM71-00104-3E
FR80 Family
APPENDIX A
APPENDIX
Instruction Lists
Table A.2-2 Compare Calculation Instructions (3 Instructions)
Mnemonic
CMP Rj, Ri
CMP #i4, Ri
CMP2 #i4, Ri
Format
OP
CYC
FLAG
NZVC
RMW
A
C
C
AA
A8
A9
1
1
1
CCCC
CCCC
CCCC
-
Operation
Ri-Rj
Ri-extu(i4)
Ri-extn(i4)
Remarks
i4 is Zero extension
i4 is Minus extension
Reference
7.32
7.31
7.33
Table A.2-3 Logical Calculation Instructions (12 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
A
A
A
A
A
A
A
A
A
A
A
A
82
84
85
86
92
94
95
96
9A
9C
9D
9E
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
1
1+2a
1+2a
1+2a
CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC--
❍
❍
❍
❍
❍
❍
❍
❍
❍
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR Rj, Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
Operation
Remarks
Ri & Rj → Ri
(Ri) & Rj → (Ri)
(Ri) & Rj → (Ri)
(Ri) & Rj → (Ri)
Ri | Rj → Ri
(Ri) | Rj → (Ri)
(Ri) | Rj → (Ri)
(Ri) | Rj → (Ri)
Ri ^ Rj → Ri
(Ri) ^ Rj → (Ri)
(Ri) ^ Rj → (Ri)
(Ri) ^ Rj → (Ri)
Word
Word
Half-Word
Byte
Word
Word
Half-Word
Byte
Word
Word
Half-Word
Byte
Reference
7.10
7.9
7.13
7.11
7.103
7.102
7.106
7.104
7.56
7.55
7.58
7.57
Table A.2-4 Bit Operation Instructions (8 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
BANDL #u4, @Ri
C
80
1+2a
----
❍
(Ri) & {F0H+u4} → (Ri)
Lower 4- bit
7.18
BANDH #u4, @Ri
C
81
1+2a
----
❍
(Ri) & {u4<<4+0FH} → (Ri)
Higher 4 bit
7.17
BORL #u4, @Ri
BORH #u4, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
BTSTL #u4, @Ri
BTSTH #u4, @Ri
C
C
C
C
C
C
90
91
98
99
88
89
1+2a
1+2a
1+2a
1+2a
2+a
2+a
------------0C-CC--
❍
❍
❍
❍
-
(Ri) | u4 → (Ri)
(Ri) | {u4<<4} → (Ri)
(Ri) ^ u4 → (Ri)
(Ri) ^ {u4<<4} → (Ri)
(Ri) & u4
(Ri) & {u4<<4}
Lower 4- bit
Higher 4 bit
Lower 4- bit
Higher 4 bit
Lower 4- bit
Higher 4 bit
7.24
7.23
7.22
7.21
7.26
7.25
Operation
Remarks
Reference
Table A.2-5 Multiply/ Divide Instructions (10 Instructions)
Mnemonic
Format
OP
CYC
MUL Rj, Ri
MULU Rj, Ri
MULH Rj, Ri
MULUH Rj, Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
A
A
A
A
E
E
E
E
E’
E’
AF
AB
BF
BB
97-4
97-5
97-6
97-7
9F-6
9F-7
5
5
3
3
1
1
1
c
1
1
CM71-00104-3E
FLAG
NZVC
CCCCCCCC-CC--------C-C
-C-C
-------
Operation
RMW
-
Ri
Ri
Ri
Ri
× Rj → MDH,MDL
× Rj → MDH,MDL
× Rj → MDL
× Rj → MDL
In the Specified
Instruction Sequence
MDL ÷ Ri → MDL
MDL%Ri → MDH
FUJITSU SEMICONDUCTOR LIMITED
Remarks
32 × 32 bit = 64 bit
Unsigned
16 × 16 bit = 32 bit
Unsigned
Step Calculation
32 ÷ 32 bit = 32 bit
Reference
7.97
7.99
7.98
7.100
7.34
7.35
7.36
7.37
7.38
7.39
359
APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
Table A.2-6 Shift Instructions (9 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
LSL Rj, Ri
A
B6
1
CC-C
-
Ri << Rj → Ri
LSL #u4, Ri
C
B4
1
CC-C
-
Ri << u4 → Ri
LSL2 #u4, Ri
C
B5
1
CC-C
-
Ri << {u4+16} → Ri
LSR Rj, Ri
A
B2
1
CC-C
-
Ri >> Rj → Ri
LSR #u4, Ri
C
B0
1
CC-C
-
Ri >> u4 → Ri
LSR2 #u4, Ri
C
B1
1
CC-C
-
Ri >> {u4+16} → Ri
7.91
ASR Rj, Ri
A
BA
1
CC-C
-
Ri >> Rj → Ri
7.14
Mnemonic
Operation
Remarks
Reference
7.86
Logical Shift
7.87
7.88
7.89
Logical Shift
ASR #u4, Ri
C
B8
1
CC-C
-
Ri >> u4 → Ri
ASR2 #u4, Ri
C
B9
1
CC-C
-
Ri >> {u4+16} → Ri
7.90
Arithmetic Shift
7.15
7.16
Table A.2-7 Immediate Data Transfer Instructions (3 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
LDI:32 #i32, Ri
H
9F-8
d
----
-
i32 → Ri
LDI:20 #i20, Ri
G
9B
d
----
-
extu(i20) → Ri
Higher 12-Bits are Zero extension
7.74
LDI:8 #i8, Ri
B
C0
1
----
-
extu(i8) → Ri
Higher 24-Bits are Zero extension
7.76
Operation
Remarks
Reference
7.75
Table A.2-8 Memory Load Instructions (13 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
LD @Rj, Ri
A
04
b
----
-
(Rj) → Ri
7.67
LD @(R13, Rj), Ri
A
00
b
----
-
(R13+Rj) → Ri
7.68
LD @(R14, disp10), Ri
B
20
b
----
-
(R14+o8 × 4) → Ri
7.69
LD @(R15, udisp6), Ri
C
03
b
----
-
(R15+u4 × 4) → Ri
Mnemonic
Operation
Remarks
Reference
7.70
LD @R15+, Ri
E
07-0
b
----
-
(R15) → Ri,
R15+4 → R15
LD @R15+, Rs
E
07-8
b
----
-
(R15) → Rs,
R15+4 → R15
7.72
LD @R15+, PS
E
07-9
1+a
CCCC
-
(R15) → PS,
R15+4 → R15
7.73
LDUH @Rj, Ri
A
05
b
----
-
extu((Rj)) → Ri
LDUH @(R13, Rj), Ri
A
01
b
----
-
extu((R13+Rj)) → Ri
LDUH @(R14, disp9), Ri
B
40
b
----
-
extu((R14+o8 × 2)) → Rj
LDUB @Rj, Ri
A
06
b
----
-
extu((Rj)) → Ri
LDUB @(R13, Rj), Ri
A
02
b
----
-
extu((R13+Rj)) → Ri
LDUB @(R14, disp8), Ri
B
60
b
----
-
extu((R14+o8)) → Ri
Word
7.71
HalfWord
Zero extension
7.82
7.83
7.84
7.79
Byte
Zero extension
7.80
7.81
• Relation of field "o8" in the Instruction Format TYPE-B and field "u4" in TYPE-C Format to the values
disp8 to disp10, udisp6 in assembly notation is as follows.
o8 = disp8
o8 = disp9 >> 1
o8 = disp10 >> 2
u4 = udisp6 >> 2
360
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
APPENDIX A
APPENDIX
Instruction Lists
Table A.2-9 Memory Store Instructions (13 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
ST Ri, @Rj
A
14
a
----
-
Ri → (Rj)
7.113
ST Ri, @(R13, Rj)
A
10
a
----
-
Ri → (R13+Rj)
7.114
ST Ri, @(R14, disp10)
B
30
a
----
-
Ri → (R14+o8 × 4)
7.115
ST Ri, @(R15, udisp6)
C
13
a
----
-
Ri → (R15+u4 × 4)
7.116
ST Ri, @-R15
E
17-0
a
----
-
R15-4 → R15,
Ri → (R15)
ST Rs, @-R15
E
17-8
a
----
-
R15-4 → R15,
Rs → (R15)
7.118
ST PS, @-R15
E
17-9
a
----
-
R15-4 → R15,
PS → (R15)
7.119
STH Ri, @Rj
A
15
a
----
-
Ri → (Rj)
7.123
STH Ri, @(R13, Rj)
A
11
a
----
-
Ri → (R13+Rj)
STH Ri, @(R14, disp9)
B
50
a
----
-
Ri → (R14+o8 × 2)
7.125
STB Ri, @Rj
A
16
a
----
-
Ri → (Rj)
7.120
STB Ri, @(R13, Rj)
A
12
a
----
-
Ri → (R13+Rj)
STB Ri, @(R14, disp8)
B
70
a
----
-
Ri → (R14+o8)
Mnemonic
Operation
Remarks
Word
Half-Word
Byte
Reference
7.117
7.124
7.121
7.122
• Relation of field "o8" in the Instruction Format TYPE-B and field "u4" in TYPE-C Format to the values
disp8 to disp10, udisp6 in assembly notation is as follows.
o8 = disp8
o8 = disp9 >> 1
o8 = disp10 >> 2
u4 = udisp6 >> 2
Table A.2-10 Inter-Register Transfer Instructions/Dedicated Register Transfer Instructions (5 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
Operation
Remarks
Reference
MOV Rj, Ri
A
8B
1
----
-
Rj → Ri
Transfer between general-purpose
Registers
7.92
MOV Rs, Ri
A
B7
1
----
-
Rs → Ri
Rs: Dedicated Register
7.93
MOV Ri, Rs
A
B3
1
----
-
Ri → Rs
Rs: Dedicated Register
7.95
MOV PS, Ri
E
17-1
1
----
-
PS → Ri
PS: Program Status
7.94
MOV Ri, PS
E
07-1
c
CCCC
-
Ri → PS
PS: Program Status
7.96
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
361
APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
Table A.2-11 Non-delayed Branching Instructions (23 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
JMP @Ri
E
97-0
2
----
-
Ri → PC
7.65
CALL label12
F
D0
2
----
-
PC+2 → RP,
PC+2+exts(rel11 × 2) → PC
7.27
CALL @Ri
RET
E
E’
97-1
97-2
2
2
-------
-
Mnemonic
Operation
Remarks
PC+2 → RP, Ri → PC
Reference
7.28
7.107
RP → PC
SSP-4 → SSP, PS → (SSP),
SSP-4 → SSP, PC+2 → (SSP),
0 → CCR:I, 0 → CCR:S,
(TBR+3FC-u8 × 4) → PC
SSP → SSP, PS → (SSP),
SSP → SSP, PC+2 → (SSP),
0 → CCR:S, 4 → ILM,
(TBR+3D8) → PC
(SSP) → PC, SSP+4 → SSP,
(SSP) → PS, SSP+4 → SSP
INT #u8
D
1F
1+3a
----
-
INTE
E’
9F-3
1+3a
----
-
RETI
E’
97-3
1+2b
----
-
BNO label9
BRA label9
D
D
E1
E0
1
2
-------
-
No branch
BEQ label9
D
E2
2/1
----
-
7.19
BNE label9
D
E3
2/1
----
-
BC label9
D
E4
2/1
----
-
BNC label9
D
E5
2/1
----
-
BN label9
D
E6
2/1
----
-
BP label9
D
E7
2/1
----
-
BV label9
D
E8
2/1
----
-
BNV label9
D
E9
2/1
----
-
if (Z==1) then
PC+2+exts(rel8 × 2) → PC
if (Z==0) then
PC+2+exts(rel8 × 2) → PC
if (C==1) then
PC+2+exts(rel8 × 2) → PC
if (C==0) then
PC+2+exts(rel8 × 2) → PC
if (N==1) then
PC+2+exts(rel8 × 2) → PC
if (N==0) then
PC+2+exts(rel8 × 2) → PC
if (V==1) then
PC+2+exts(rel8 × 2) → PC
if (V==0) then
PC+2+exts(rel8 × 2) → PC
BLT label9
D
EA
2/1
----
-
7.19
BGE label9
D
EB
2/1
----
-
BLE label9
D
EC
2/1
----
-
BGT label9
D
ED
2/1
----
-
BLS label9
D
EE
2/1
----
-
BHI label9
D
EF
2/1
----
-
if (V ^ N==1) then
PC+2+exts(rel8 × 2) → PC
if (V ^ N==0) then
PC+2+exts(rel8 × 2) → PC
if ({V ^ N} | Z==1) then
PC+2+exts(rel8 × 2) → PC
if ({V ^ N} | Z==0) then
PC+2+exts(rel8 × 2) → PC
if (C or Z==1) then
PC+2+exts(rel8 × 2) → PC
if (C or Z==0) then
PC+2+exts(rel8 × 2) → PC
7.63
7.64
7.109
7.19
7.19
PC+2+exts(rel8 × 2) → PC
7.19
7.19
7.19
7.19
7.19
7.19
7.19
7.19
7.19
7.19
7.19
7.19
• The value of "2/1" in CYC Column indicates 2 cycles if branching and 1 if not branching.
• It is necessary to set the Stack Flag (S) to "0" for RETI execution.
• The field "rel8" in TYPE_D Instruction Format and the field "rel11" in TYPE-F Format have the
following relation to the values of label9, label12 in assembly notation.
rel8 = (label9-PC-2)/2
rel11 = (label12-PC-2)/2
362
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
APPENDIX A
APPENDIX
Instruction Lists
Table A.2-12 Delayed Branching Instructions (20 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
JMP:D @Ri
E
9F-0
1
----
-
Ri → PC
7.66
CALL:D label12
F
D8
1
----
-
PC+4 → RP,
PC+2+exts(rel11 × 2) → PC
7.29
CALL:D @Ri
E
9F-1
1
----
-
PC+4 → RP, Ri → PC
7.30
RET:D
E’
9F-2
1
----
-
RP → PC
7.108
BNO:D label9
D
F1
1
----
-
No branch
7.20
BRA:D label9
D
F0
1
----
-
PC+2+exts(rel8 × 2) → PC
7.20
BEQ:D label9
D
F2
1
----
-
if (Z==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BNE:D label9
D
F3
1
----
-
if (Z==0) then
PC+2+exts(rel8 × 2) → PC
7.20
BC:D label9
D
F4
1
----
-
if (C==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BNC:D label9
D
F5
1
----
-
if (C==0) then
PC+2+exts(rel8 × ) → PC
7.20
BN:D label9
D
F6
1
----
-
if (N==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BP:D label9
D
F7
1
----
-
if (N==0) then
PC+2+exts(rel8 × 2) → PC
7.20
BV:D label9
D
F8
1
----
-
if (V==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BNV:D label9
D
F9
1
----
-
if (V==0) then
PC+2+exts(rel8 × 2) → PC
7.20
BLT:D label9
D
FA
1
----
-
if (V ^ N==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BGE:D label9
D
FB
1
----
-
if (V ^ N==0) then
PC+2+exts(rel8 × 2) → PC
7.20
BLE:D label9
D
FC
1
----
-
if ({V ^ N} | Z==1) then
PC+2+exts(rel × 2) → PC
7.20
BGT:D label9
D
FD
1
----
-
if ({V ^ N} | Z==0) then
PC+2+exts(rel8 × 2) → PC
7.20
BLS:D label9
D
FE
1
----
-
if (C or Z==1) then
PC+2+exts(rel8 × 2) → PC
7.20
BHI:D label9
D
FF
1
----
-
if (C or Z==0) then
PC+2+exts(rel8 × 2) → PC
7.20
Mnemonic
Operation
Remarks
Reference
• Delayed Branching Instructions are branched after always executing the following Instruction (the Delay
Slot).
• The field "rel8" in TYPE-D instruction format and the field "rel11" in TYPE-D format have the
following relation to the values label9, label12 in assembly notation.
rel8 = (label9-PC-2)/2
rel11 = (label12-PC-2)/2
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
363
APPENDIX
APPENDIX A
Instruction Lists
FR80 Family
Table A.2-13 Direct Addressing Instructions (14 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
DMOV @dir10, R13
D
08
b
----
-
(dir8 × 4) → R13
7.40
DMOV R13, @dir10
D
18
a
----
-
R13 → (dir8 × 4)
7.41
DMOV @dir10, @R13+
D
0C
1+2a
----
-
(dir8 × 4) → (R13),
R13+4 → (R13)
7.42
DMOV @R13+, @dir10
D
1C
1+2a
----
-
(R13) → (dir8 × 4),
R13+4 → (R13)
DMOV @dir10, @-R15
D
0B
1+2a
----
-
R15-4 → (R15),
(dir8 × 4) → (R15)
7.44
DMOV @R15+, @dir10
D
1B
1+2a
----
-
(R15) → (dir8 × 4),
R15+4 → (R15)
7.45
DMOVH @dir9, R13
D
09
b
----
-
(dir8 × 2) → R13
7.50
DMOVH R13, @dir9
D
19
a
----
-
R13 → (dir8 × 2)
7.51
DMOVH @dir9, @R13+
D
0D
1+2a
----
-
(dir8 × 2) → (R13),
R13+2 → (R13)
DMOVH @R13+, @dir9
D
1D
1+2a
----
-
(R13) → (dir8 × 2),
R13+2 → (R13)
7.53
DMOVB @dir8, R13
D
0A
b
----
-
(dir8) → R13
7.46
DMOVB R13, @dir8
D
1A
a
----
-
R13 → (dir8)
7.47
DMOVB @dir8, @R13+
D
0E
1+2a
----
-
(dir8) → (R13),
R13+2 → (R13)
DMOVB @R13+, @dir8
D
1E
1+2a
----
-
(R13) → (dir8),
R13+2 → (R13)
Mnemonic
Operation
Remarks
Word
Reference
7.43
Half-Word
Byte
7.52
7.48
7.49
• The field "dir8" in FORMAT_D Instruction format has the following relation to the values of dir8, dir9,
dir10 in assembly notation.
dir8 = dir8
dir8 = dir9 >> 1
dir8 = dir10 >> 2
Table A.2-14 Bit Search Instructions (3 Instructions)
Mnemonic
Format
OP
CYC
FLAG
NZVC
RMW
SRCH0 Ri
E
97-C
1
----
-
search_zero(Ri) → Ri
Searches first 0 Bit
7.110
SRCH1 Ri
E
97-D
1
----
-
search_one(Ri) → Ri
Searches first 1 Bit
7.111
SRCHC Ri
E
97-E
1
----
-
search_change(Ri) → Ri
Searches first change
7.112
364
Operation
FUJITSU SEMICONDUCTOR LIMITED
Remarks
Reference
CM71-00104-3E
FR80 Family
APPENDIX A
APPENDIX
Instruction Lists
Table A.2-15 Other Instructions (16 Instructions)
Format
OP
CYC
FLAG
NZVC
RMW
NOP
E’
9F-A
1
----
-
No change
7.101
ANDCCR #u8
D
83
1
CCC
C
-
CCR & u8 → CCR
7.12
ORCCR #u8
D
93
1
CCC
C
-
CCR | u8 → CCR
7.105
STILM #u8
D
87
1
----
-
u8 → ILM
ADDSP #s10
D
A3
1
----
-
R15+s8 × 4 → R15
EXTSB Ri
E
97-8
1
----
-
exts(Ri[7:0]) → Ri
Sign extension 8 → 32
7.59
EXTUB Ri
E
97-9
1
----
-
extu(Ri[7:0]) → Ri
Zero extension8 → 32
7.61
EXTSH Ri
E
97-A
1
----
-
exts(Ri[15:0]) → Ri
Sign extension 16 → 32
7.60
EXTUH Ri
E
97-B
1
----
-
extu(Ri[15:0]) → Ri
Zero extension16 → 32
7.62
LDM0 (reglist)
D
8C
*1
----
-
(R15) → reglist,
R15+4 → R15
Load Multiple
R0 to R7
7.77
LDM1 (reglist)
D
8D
*1
----
-
(R15) → reglist,
R15+4 → R15
Load Multiple
R8 to R15
7.78
STM0 (reglist)
D
8E
*2
----
-
R15-4 → R15,
reglist → (R15)
Store multiple
R0 to R7
7.127
STM1 (reglist)
D
8F
*2
----
-
R15-4 → R15,
reglist → (R15)
Store multiple
R8 to R15
7.128
ENTER #u10
D
0F
1+a
----
-
R14 → (R15-4),
R15-4 → R14,
R15-extu(u8 × 4) → R15
Function entry
processing
7.54
LEAVE
E’
9F-9
b
----
-
R14+4 → R15,
(R15-4) → R14
Function exit
processing
7.85
XCHB @Rj, Ri
A
8A
2a
----
❍
Ri → TEMP,
extu((Rj)) → Ri,
TEMP → (Rj)
Byte data for
semaphore processing
7.132
Mnemonic
Operation
Remarks
Sets ILM immediate value
Reference
7.126
7.8
*1: The number of execution cycles for LDM0(reglist) and LDM1(reglist) is b × n cycles when "n" is the number of registers
designated.
*2: The number of execution cycles for STM0(reglist)and STM1(reglist) is a × n when "n" is the number of registers
designated.
• In the ADDSP Instruction, the field s8 in TYPE-D Instruction Format has the following relation to the
value of s10 in assembly notation.
s8 = s10 >> 2
• In the ENTER Instruction, the field u8 in TYPE-D Instruction Format has the following relation to the
value of u10 in assembly notation.
u8 = u10 >> 2
CM71-00104-3E
FUJITSU SEMICONDUCTOR LIMITED
365
APPENDIX
APPENDIX A
A.3
Instruction Lists
FR80 Family
List of Instructions that can be positioned in the Delay Slot
This section shows the Instructions List that can be positioned in the delay slot of Delay
Branching Instruction.
● Add/Subtract Instructions
ADD Rj, Ri
ADD #14, Ri
ADD2 #i4, Ri
ADDC Rj, Ri
ADDN Rj, Ri
ADDN #i4, Ri
ADDN2 #i4, Ri
SUB Rj, Ri
SUBC Rj, Ri
SUBN Rj, Ri
● Compare Calculation Instructions
CMP Rj, Ri
CMP #i4, Ri
CMP2 #i4, Ri
● Logical Calculation Instructions
AND Rj, Ri
OR Rj, Ri
EOR Rj, Ri
● Multiply/ Divide Instructions
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
LSL Rj, Ri
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
ASR #u4, Ri
ASR2 #u4, Ri
● Shift Instructions
● Immediate Data Transfer Instructions
LDI:8 #i8, Ri
● Memory Load Instructions
366
LD @Rj, Ri
LD @(R13, Rj), Ri
LD @(R14, disp10), Ri
LD @(R15, udisp6), Ri
LD @R15+, Ri
LD @R15+, Rs
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
APPENDIX A
LDUH @Rj, Ri
LDUH @(R13, Rj), Ri
LDUH @(R14, disp9), Ri
LDUB @Rj, Ri
LDUB @(R13, Rj), Ri
LDUB @(R14, disp8), Ri
ST Ri, @Rj
ST Ri, @(R13, Rj)
ST Ri, @(R14, disp10)
ST Ri, @(R15, udisp6)
ST Ri, @-R15
ST Rs, @-R15
STH Ri, @Rj
STH Ri, @(R13, Rj)
STH Ri, @(R14, disp9)
STB Ri, @Rj
STB Ri, @(R13, Rj)
STB Ri, @(R14, disp8)
APPENDIX
Instruction Lists
● Memory Store Instructions
ST PS, @-R15
● Inter-Register Transfer Instructions
MOV Rj, Ri
MOV Rs, Ri
MOV PS, Ri
MOV Ri, PS
MOV Ri, Rs
● Direct Addressing Instructions
DMOV @dir10, R13
DMOV R13, @dir10
DMOVH @dir9, R13
DMOVH R13, @dir9
DMOVB @dir8, R13
DMOVB R13, @dir8
SRCH1 Ri
SRCHC Ri
NOP
ANDCCR #u8
ORCCR #u8
STILM #u8
ADDSP #s10
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
● Bit Search Instructions
SRCH0 Ri
● Other Instructions
LEAVE
CM71-00104-3E
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APPENDIX
APPENDIX A
A.4
Instruction Lists
FR80 Family
Instruction List where the number of execution cycles has
been changed
This section shows the Instruction List where the definition of number of execution
cycles has changed between FR80 Family CPU and earlier FR Family CPU.
Table A.4-1 Instruction List where the definition of number of execution cycles has
changed
FR80 Family
CYC
Mnemonic
Earlier FR Family
CYC
Remarks
DIV1 Ri
1
d
DIV2 Ri
c
1
LDI:32 #i32, Ri
d
3
LDI:20 #i20, Ri
d
2
LD @R15+, PS
1+a
1+a+b
MOV Ri, PS
1
c
INT #u8
1+3a
3+3a
INTE
1+3a
3+3a
RETI
1+2b
2+2a
DMOV @dir10, @R13+
1+2a
2a
DMOV @R13+, @dir10
1+2a
2a
DMOV @dir10, @-R15
1+2a
2a
DMOV @-R15, @dir10
1+2a
2a
DMOVH @dir9, @R13+
1+2a
2a
DMOVH @R13+, @dir9
1+2a
2a
DMOVB @dir8, @R13+
1+2a
2a
DMOVB @R13+, @dir8
1+2a
2a
ANDCCR #u8
1
c
ORCCR #u8
1
c
LDM0 (reglist)
LDM1 (reglist)
b×n
a × (n-1)+b+1
n is number of registers designated
STM0 (reglist)
STM1 (reglist)
a×n
a × n+1
n is number of registers designated
In FR80 Family CPU, definition of execution cycles b, c, d has been changed in the CYC Column of
Instruction List and Detailed Execution Instructions.
368
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
APPENDIX B
APPENDIX B
APPENDIX
Instruction Maps
Instruction Maps
It includes instruction maps of FR80 Family CPU.
B.1 Instruction Maps
B.2 Instruction Maps of Instruction Format Type-E
CM71-00104-3E
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370
E format
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F
#u8
ENTER #u10
E
INT
DMOVH @d9, DMOVH
@R13+
@R13+, @ d9
DMOVB
DMOVB
@d8, @R13+ @R13+, @ d8
D
ORCCR
#u8
OR Rj, Ri
BORH
#u4,@Ri
ORH
Rj,@Ri
STM1
(reglist)
STM0
(reglist)
LDM1
(reglist)
LDM0
(reglist)
BT STH
#u4,@Ri
A
E format
EORB
Rj,@Ri
EORH
Rj,@Ri
LSL #u4,Ri
MOV Ri, Rs
LSR Rj, Ri
LSR2 #u4,Ri
MOV Rs, Ri
ASR #u4,Ri
ASR Rj,Ri
MUL Rj,Ri
SUBN Rj,Ri
MULH Rj,Ri
SUBCRj, Ri STRES
#u4,@Ri+
LDRES
@Ri+,#u4
MULU R j, Ri MULUH
Rj, Ri
CMP Rj,Ri
CMP2 #i4,Ri ASR2
#u4,Ri
CMP #i4,Ri
ADDCRj,Ri
LSL Rj,Ri
ADD2 #i4,Ri LSL2 #u4,Ri
ADD #i4,Ri
ADDSP
#s10
ADDN Rj,Ri
ADDN2
#i4,Ri
EORRj,@ Ri SUB R j, Ri
LD:20
#i20,Ri
EOR Rj,Ri
BEORH
#u4,@Ri
B
ADDN# i4,Ri LSR #u4,Ri
ORB Rj,@Ri ADD Rj,Ri
STILM #u8 E format
STB
Ri,@(R14,
BT
STL
BEORL
disp8)
#u4,@Ri
#u4,@Ri
MOV Rj,Ri
LDUB
@(R14,
disp8),Ri
ANDB
Rj,@Ri
ANDH
Rj,@Ri
DMOV
DMOV
@d10,@R13+ @R13+,@d10
STH
Ri,@(R14,
disp9)
9
BORL
#u4,@Ri
AND Rj,@Ri OR Rj,@Ri
ANDCCR
#u8
AND Rj,Ri
BANDH
#u4,@Ri
DMOV
DMOV
@d10,@–R15 @R15+,@d10
LDUH
@(R14,
disp9),Ri
8
BANDL
#u4,@Ri
B
ST Ri,@
(R14,
disp10)
7
C
LD @(R14,
disp10),Ri
6
XCHB
@Rj,Ri
DMOV
R13,@d10
5
DMOVH @d9, DMOVH
R13
R13, @d 9
8
4
DMOVB@ d8, DMOVB
R13
R13, @d 8
E format
DMOV
@d10,R13
7
STB Ri,@Rj
STH Ri,@ Rj
3
9
[email protected],Ri
ST Ri,@ Rj
2
A
[email protected],Ri
LD @Rj,Ri
4
6
LD @ (R15,
udisp6),Ri
3
5
LDUB
STB Ri ,
@(R13,Rj), Ri @(R13,Rj)
2
ST Ri,
@(R15,ud6)
LDUH
STH Ri,
@(R13,Rj), Ri @(R13,Rj)
1
1
0
LD @(R13,Rj), ST Ri,
Ri
@(R13,Rj)
LDI:8 #i 8,Ri
C
CALL:D
label12
CALL
label12
D
E
BHI label9
BLS label9
BGT label9
BLE label9
BGE label9
BLT label9
BNV label9
BV label9
BP label9
BN label9
BNC label9
BC label9
BNE label9
BEQ label9
BNO label9
BRA label9
F
BHI:D
label9
BLS:D
label9
BGT:D
label9
BLE:D
label9
BGE:D
label9
BLT:D label9
BNV:D
label9
BV:D
label9
BP:D
label9
BN:D
label9
BNC:D
label9
BC:D
label9
BNE:D
label9
BEQ:D
label9
BNO:D
label9
BRA:D
label9
B.1
0
Higher 4 bits
APPENDIX
APPENDIX B
Instruction Maps
FR80 Family
Instruction Maps
Instruction maps are as follows.
Figure B.1-1 illustrates in tabular form 8 bit operation codes (OP) for each instruction. Instructions where
operation code (OP) is less than 8 bit, they have been converted into 8 bit by packing them on MSB side.
Figure B.1-1 Instruction Map
Lower 4 b its
CM71-00104-3E
FR80 Family
B.2
APPENDIX B
APPENDIX
Instruction Maps
Instruction Maps of Instruction Format Type-E
Instruction format indicates the instruction maps of TYPE-E, TYPE-E instructions.
Figure B.2-1 illustrates in tabular form 8 bit operation codes (OP) and 4 bit sub-operation codes (SUB-OP)
for each instruction.
Figure B.2-1 Instruction Map of Instruction Format TYPE-E
Higher 8 bits
Lower 4 bits
07
17
97
9F
0
LD @R15+,Ri
ST Ri,@-R15
JMP @Ri
JMP:D @Ri
1
MOV Ri,PS
MOV PS,Ri
CALL @Ri
CALL:D @Ri
2
-
-
RET
RET:D
3
-
-
RETI
INTE
4
-
-
DIV0S Ri
-
5
-
-
DIV0U Ri
-
6
-
-
DIV1 Ri
DIV3
7
-
-
DIV2 Ri
DIV4S
8
LD @R15+,Rs
ST Rs,@-R15
EXTSB Ri
LDI:32 #i32,Ri
9
LD @R15+,PS
ST PS,@-R15
EXTUB Ri
LEAVE
NOP
A
-
-
EXTSH Ri
B
-
-
EXTUH Ri
C
-
-
-
SRCH0
D
-
-
-
SRCH1
E
-
-
-
SRCHC
-
-: Undefined
CM71-00104-3E
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APPENDIX
APPENDIX B
372
Instruction Maps
FR80 Family
FUJITSU SEMICONDUCTOR LIMITED
CM71-00104-3E
FR80 Family
INDEX
The index follows on the next page.
This is listed in alphabetic order.
CM71-00104-3E
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373
FR80 Family
Index
Numerics
A
20-bit Addressing
20-bit Addressing Area & 32-bit Addressing Area
............................................................12
32-bit Addressing
20-bit Addressing Area & 32-bit Addressing Area
............................................................12
Access
Data Access ....................................................... 15
Program Access ................................................. 15
ADD
ADD (Add 4bit Immediate Data to Destination
Register)............................................... 85
ADD (Add Word Data of Source Register to
Destination Register) ............................. 87
ADD2 (Add 4bit Immediate Data to Destination
Register)............................................... 89
ADDC
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 91
ADDN
ADDN (Add Immediate Data to Destination Register)
............................................................ 93
ADDN (Add Word Data of Source Register
to Destination Register) ......................... 95
ADDN2 (Add Immediate Data to Destination
Register)............................................... 97
Address Space
Address Space...................................................... 8
Addressing
20-bit Addressing Area & 32-bit Addressing Area
............................................................ 12
Addressing Formats
Addressing Formats............................................ 69
ADDSP
ADDSP (Add Stack Pointer and Immediate Data)
............................................................ 99
Alignment
Word Alignment ................................................ 15
AND
AND (And Word Data of Source Register to Data
in Memory)........................................ 101
AND (And Word Data of Source Register
to Destination Register) ....................... 103
ANDB
ANDB (And Byte Data of Source Register to Data
in Memory)......................................... 105
ANDCCR
ANDCCR (And Condition Code Register and
Immediate Data).................................. 107
ANDH
ANDH (And Halfword Data of Source Register
to Data in Memory) ............................. 109
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FR80 Family
Arithmetic shift
ASR (Arithmetic shift to the Right Direction)
..................................................111, 113
ASR2 (Arithmetic shift to the Right Direction)
..........................................................115
ASR
ASR (Arithmetic shift to the Right Direction)
..................................................111, 113
ASR2 (Arithmetic shift to the Right Direction)
..........................................................115
B
BANDH
BANDH (And 4bit Immediate Data to Higher 4bit
of Byte Data in Memory)......................117
BANDL
BANDL (And 4bit Immediate Data to Lower 4bit
of Byte Data in Memory)......................119
Bcc
Bcc (Branch relative if Condition satisfied) .........121
Bcc:D
Bcc:D (Branch relative if Condition satisfied)
..........................................................123
BEORH
BEORH (Eor 4bit Immediate Data to Higher 4bit
of Byte Data in Memory)......................125
BEORL
BEORL (Eor 4bit Immediate Data to Lower 4bit
of Byte Data in Memory)......................127
BORH
BORH (Or 4bit Immediate Data to Higher 4bit of
Byte Data in Memory)..........................129
BORL
BORL (Or 4bit Immediate Data to Lower 4bit of
Byte Data in Memory)..........................131
Branch
Bcc (Branch relative if Condition satisfied) .........121
Bcc:D (Branch relative if Condition satisfied)
..........................................................123
Branching
Delayed Branching Instructions ...........................77
Delayed branching processing..............................62
Example of branching with non-delayed branching
instructions ...........................................62
Example of processing of delayed branching
instruction.............................................63
Non-Delayed Branching Instructions ....................79
Specific example of Delayed Branching Instructions
............................................................78
Branching Instructions
Branching Instructions and Delay Slot ..................77
CM71-00104-3E
BTSTH
BTSTH (Test Higher 4bit of Byte Data in Memory)
.......................................................... 133
BTSTL
BTSTL (Test Lower 4bit of Byte Data in Memory)
.......................................................... 135
Bypassing
Register Bypassing ............................................. 59
Byte Data
ANDB (And Byte Data of Source Register to Data
in Memory)......................................... 105
BTSTH (Test Higher 4bit of Byte Data in Memory)
.......................................................... 133
BTSTL (Test Lower 4bit of Byte Data in Memory)
.......................................................... 135
Byte Data .......................................................... 13
DMOVB (Move Byte Data from Direct Address
to Post Increment Register Indirect Address)
.......................................................... 179
DMOVB (Move Byte Data from Direct Address
to Register) ......................................... 175
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
.......................................................... 181
DMOVB (Move Byte Data from Register to
Direct Address) ................................... 177
EORB (Exclusive Or Byte Data of Source Register
to Data in Memory) ............................. 197
EXTSB (Sign Extend from Byte Data to Word Data)
.......................................................... 201
EXTSH (Sign Extend from Byte Data to Word Data)
.......................................................... 203
EXTUB (Unsign Extend from Byte Data to
Word Data)......................................... 205
EXTUH (Unsign Extend from Byte Data to
Word Data)......................................... 207
LDUB (Load Byte Data in Memory to Register)
.......................................... 241, 243, 245
ORB (Or Byte Data of Source Register to Data
in Memory)......................................... 291
STB (Store Byte Data in Register to Memory)
.......................................... 323, 325, 327
XCHB (Exchange Byte Data) ............................ 347
Byte Order
Byte Order......................................................... 14
C
CALL
CALL (Call Subroutine) ........................... 137, 139
CALL:D
CALL:D (Call Subroutine) ........................ 141, 143
Carry Bit
ADDC (Add Word Data of Source Register and
Carry Bit to Destination Register) ........... 91
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FR80 Family
CCR
Condition Code Register (CCR) ...........................30
CMP
CMP (Compare Immediate Data and
Destination Register)............................145
CMP (Compare Word Data in Source Register and
Destination Register)............................147
CMP2 (Compare Immediate Data and
Destination Register)............................149
Condition Code Register
ANDCCR (And Condition Code Register and
Immediate Data) ..................................107
Condition Code Register (CCR) ...........................30
ORCCR (Or Condition Code Register and Immediate
Data) ..................................................293
Correction
DIV2 (Correction When Remain is 0).................157
DIV3 (Correction When Remain is 0).................159
DIV4S (Correction Answer for Signed Division)
..........................................................161
CPU
Features of FR80 Family CPU ...............................2
FR80 Family CPU Register Configuration ............18
D
Data Access
Data Access .......................................................15
Data Structure
Data Structure ....................................................13
Dedicated Registers
Configuration of Dedicated Registers ...................21
Dedicated Registers ............................................21
Delay Slot
Branching Instructions and Delay Slot ..................77
Delayed Branching
Delayed branching processing..............................62
Delayed Branching Instruction
Delayed Branching Instructions ...........................77
Example of processing of delayed branching
instruction.............................................63
Specific example of Delayed Branching Instructions
............................................................78
Destination Register
ADD (Add 4bit Immediate Data to
Destination Register)..............................85
ADD2 (Add 4bit Immediate Data to
Destination Register)..............................89
ADDN (Add Immediate Data to Destination Register)
............................................................93
ADDN2 (Add Immediate Data to
Destination Register)..............................97
CMP (Compare Immediate Data and
Destination Register)............................145
CM71-00104-3E
CMP2 (Compare Immediate Data and
Destination Register) ........................... 149
LDI:8 (Load Immediate 8bit Data to
Destination Register) ........................... 235
Direct Address
Direct Address Area ............................................. 9
DMOV (Move Word Data from Direct Address
to Post Increment Register Indirect Address)
.......................................................... 167
DMOV (Move Word Data from Direct Address
to Pre Decrement Register Indirect Address)
.......................................................... 171
DMOV (Move Word Data from Direct Address
to Register) ......................................... 163
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
.......................................................... 169
DMOV (Move Word Data from Register to Direct
Address)............................................. 165
DMOVB (Move Byte Data from Direct Address
to Post Increment Register Indirect Address)
.......................................................... 179
DMOVB (Move Byte Data from Direct Address
to Register) ......................................... 175
DMOVB (Move Byte Data from Register
to Direct Address) ............................... 177
DMOVH (Move Halfword Data from Direct Address
to Register) ......................................... 183
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
.......................................................... 187
DIV
DIV0S (Initial Setting Up for Signed Division)
.......................................................... 151
DIV0U (Initial Setting Up for Unsigned Division)
.......................................................... 153
DIV1 (Main Process of Division)....................... 155
DIV2 (Correction When Remain is 0) ................ 157
DIV3 (Correction When Remain is 0) ................ 159
DIV4S (Correction Answer for Signed Division)
.......................................................... 161
Division
DIV0S (Initial Setting Up for Signed Division)
.......................................................... 151
DIV0U (Initial Setting Up for Unsigned Division)
.......................................................... 153
DIV1 (Main Process of Division)....................... 155
DIV4S (Correction Answer for Signed Division)
.......................................................... 161
Signed Division.................................................. 80
Step Division Instructions ................................... 80
Unsigned Division.............................................. 81
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FR80 Family
DMOV
DMOV (Move Word Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................167
DMOV (Move Word Data from Direct Address
to Pre Decrement Register Indirect Address)
..........................................................171
DMOV (Move Word Data from Direct Address
to Register) .........................................163
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..................................................169, 173
DMOV (Move Word Data from Register
to Direct Address)................................165
DMOVB
DMOVB (Move Byte Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................179
DMOVB (Move Byte Data from Direct Address
to Register) .........................................175
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................181
DMOVB (Move Byte Data from Register
to Direct Address)................................177
DMOVH
DMOVH (Move Halfword Data from Direct Address
to Register) .........................................183
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................187
DMOVH (Move Halfword Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................189
DMOVH (Move Halfword Data from Register
to Direct Address)................................185
E
EIT
Basic Operations in "EIT" Processing ...................37
"EIT" Processing Sequence .................................37
Multiple "EIT" Processing ...................................49
Multiple "EIT" Processing and Priority Levels ......49
Priority Levels of "EIT" Requests ........................50
Recovery from "EIT" Processing..........................39
Types of "EIT" Processing and Prior Preparation
............................................................37
Emulator
INTE (Software Interrupt for Emulator)..............211
ENTER
ENTER (Enter Function)...................................191
EOR
BEORH (Eor 4bit Immediate Data to Higher 4bit
of Byte Data in Memory).....................125
CM71-00104-3E
BEORL (Eor 4bit Immediate Data to Lower 4bit
of Byte Data in Memory) .................... 127
EOR (Exclusive Or Word Data of Source Register
to Destination Register) ....................... 195
EOR (Exclusive Or Word Data of Source Register
to Data in Memory) ............................. 193
EORB
EORB (Exclusive Or Byte Data of Source Register
to Data in Memory) ............................ 197
EORH
EORH (Exclusive Or Halfword Data
of Source Register to Data in Memory)
.......................................................... 199
Exception
Exception Processing.......................................... 40
Undefined-instruction exception .......................... 40
Exchange
XCHB (Exchange Byte Data) ............................ 347
Exclusive Or
EOR (Exclusive Or Word Data of Source Register
to Destination Register)....................... 195
EOR (Exclusive Or Word Data of Source Register
to Data in Memory) ............................. 193
EORB (Exclusive Or Byte Data of Source Register
to Data in Memory) ............................ 197
EORH (Exclusive Or Halfword Data
of Source Register to Data in Memory)
.......................................................... 199
Extend
EXTSB (Sign Extend from Byte Data to Word Data)
.......................................................... 201
EXTSH (Sign Extend from Byte Data to Word Data)
.......................................................... 203
EXTUB (Unsign Extend from Byte Data
to Word Data) ..................................... 205
EXTSB
EXTSB (Sign Extend from Byte Data to Word Data)
.......................................................... 201
EXTSH
EXTSH (Sign Extend from Byte Data to Word Data)
.......................................................... 203
EXTUB
EXTUB (Unsign Extend from Byte Data
to Word Data) ..................................... 205
EXTUH
EXTUH (Unsign Extend from Byte Data
to Word Data) ..................................... 207
F
First One bit
SRCH1 (Search First One bit position distance
From MSB) ....................................... 305
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377
FR80 Family
First Zero bit
SRCH0 (Search First Zero bit position distance
From MSB).........................................303
flag
Timing when the interrupt enable flag (I) is requested
............................................................51
Format
Instruction Formats .............................................70
Formats
Addressing Formats ............................................69
Instructions Formats ...........................................69
Instructions Notation Formats ..............................69
FR Family
Changes from the earlier FR Family .......................4
FR80 Family
Features of FR80 Family CPU ...............................2
FR80 Family CPU Register Configuration ............18
G
General-purpose Registers
Configuration of General-purpose Registers ..........19
General-purpose Registers ...................................19
Special Usage of General-purpose Registers..........19
H
Half Word Data
Half Word Data ..................................................13
Halfword Data
ANDH (And Halfword Data of Source Register
to Data in Memory)..............................109
DMOVH (Move Halfword Data from Direct Address
to Register) .........................................183
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................187
DMOVH (Move Halfword Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................189
DMOVH (Move Halfword Data from Register
to Direct Address)................................185
EORH (Exclusive Or Halfword Data
of Source Register to Data in Memory)
..........................................................199
LDUH (Load Halfword Data in Memory to Register)
..........................................247, 249, 251
MULH (Multiply Halfword Data) ......................279
MULUH (Multiply Unsigned Halfword Data)
..........................................................283
ORH (Or Halfword Data of Source Register to Data
in Memory) .........................................295
STH (Store Halfword Data in Register to Memory)
..........................................329, 331, 333
CM71-00104-3E
hazard
Occurrence of register hazard .............................. 59
Register hazards ................................................. 59
I
I
Timing when the interrupt enable flag (I) is requested
............................................................ 51
ILM
Interrupt Level Mask Register (ILM) ................... 29
Immediate 20bit Data
LDI:20 (Load Immediate 20bit Data
to Destination Register) ....................... 231
Immediate 32 bit Data
LDI:32 (Load Immediate 32 bit Data
to Destination Register) ....................... 233
Immediate 8bit Data
LDI:8 (Load Immediate 8bit Data
to Destination Register) ....................... 235
Immediate Data
ADD (Add 4bit Immediate Data
to Destination Register) ......................... 85
ADD2 (Add 4bit Immediate Data
to Destination Register) ......................... 89
ADDN (Add Immediate Data to Destination Register)
............................................................ 93
ADDN2 (Add Immediate Data
to Destination Register) ......................... 97
ADDSP (Add Stack Pointer and Immediate Data)
............................................................ 99
BANDH (And 4bit Immediate Data to Higher 4bit
of Byte Data in Memory) ..................... 117
BANDL (And 4bit Immediate Data to Lower 4bit
of Byte Data in Memory) ..................... 119
BEORH (Eor 4bit Immediate Data to Higher 4bit
of Byte Data in Memory) .................... 125
BEORL (Eor 4bit Immediate Data to Lower 4bit
of Byte Data in Memory) .................... 127
BORH (Or 4bit Immediate Data to Higher 4bit
of Byte Data in Memory) ..................... 129
BORL (Or 4bit Immediate Data to Lower 4bit
of Byte Data in Memory) ..................... 131
CMP (Compare Immediate Data and
Destination Register) ........................... 145
CMP2 (Compare Immediate Data and
Destination Register) ........................... 149
ORCCR (Or Condition Code Register and
Immediate Data)................................. 293
STILM (Set Immediate Data to Interrupt Level
Mask Register).................................... 335
Increment Register
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
.................................................. 169, 173
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FR80 Family
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................181
Indirect Address
DMOV (Move Word Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................167
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................169
Instruction
Branching Instructions and Delay Slot ..................77
Delayed Branching Instructions ...........................77
Example of branching with non-delayed branching
instructions ...........................................62
Example of processing of delayed branching
instruction.............................................63
Instruction execution based on Pipeline ................56
"INT" Instructions ..............................................46
"INTE" Instruction..............................................47
Non-Delayed Branching Instructions ....................79
Read-Modify-Write type Instructions ...................76
Specific example of Delayed Branching Instructions
............................................................78
Step Division Instructions....................................80
Instruction Format
Instruction Formats .............................................70
Instructions Formats ...........................................69
Instruction System
Instruction System ..............................................66
Instructions Notation Formats
Instructions Notation Formats ..............................69
INT
INT (Software Interrupt) ...................................209
"INT" Instructions ..............................................46
INTE
INTE (Software Interrupt for Emulator)..............211
"INTE" Instruction..............................................47
Interlocking
Interlocking........................................................60
Interlocking produced by after Changing
the Stack flag (S) ...................................60
Interrupt
INT (Software Interrupt) ...................................209
INTE (Software Interrupt for Emulator)..............211
Interrupts ...........................................................42
Mismatch in Acceptance and Cancellation of Interrupt
............................................................58
Non-maskable Interrupts (NMI) ...........................44
Pipeline Operation and Interrupt Processing ..........58
Points of Caution while using User Interrupts........54
Preparation while using user interrupts .................53
Processing during an Interrupt Processing Routine
............................................................54
CM71-00104-3E
RETI (Return from Interrupt) ............................ 301
Usage Sequence of User Interrupts....................... 53
User interrupts ................................................... 42
interrupt enable flag
Timing when the interrupt enable flag (I) is requested
............................................................ 51
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 29
Timing of Reflection of Interrupt Level Mask Register
(ILM)................................................... 52
Interrupt Processing Routine
Processing during an Interrupt Processing Routine
............................................................ 54
J
JMP
JMP (Jump) ..................................................... 213
JMP:D
JMP:D (Jump).................................................. 215
Jump
JMP (Jump) ..................................................... 213
JMP:D (Jump).................................................. 215
L
LD
LD (Load Word Data in Memory to Program
Status Register) ................................... 229
LD (Load Word Data in Memory to Register)
.................. 217, 219, 221, 223, 225, 227
LDI:20
LDI:20 (Load Immediate 20bit Data
to Destination Register) ....................... 231
LDI:32
LDI:32 (Load Immediate 32 bit Data
to Destination Register) ....................... 233
LDI:8
LDI:8 (Load Immediate 8bit Data
to Destination Register) ....................... 235
LDM
LDM0 (Load Multiple Registers)....................... 237
LDM1 (Load Multiple Registers)....................... 239
LDUB
LDUB (Load Byte Data in Memory to Register)
.......................................... 241, 243, 245
LDUH
LDUH (Load Halfword Data in Memory to Register)
.......................................... 247, 249, 251
LEAVE
LEAVE (Leave Function) ................................. 253
Load
LD (Load Word Data in Memory
to Program Status Register) .................. 229
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LD (Load Word Data in Memory to Register)
..................217, 219, 221, 223, 225, 227
LDI:20 (Load Immediate 20bit Data
to Destination Register) ........................231
LDI:32 (Load Immediate 32 bit Data
to Destination Register) .......................233
LDI:8 (Load Immediate 8bit Data
to Destination Register) ........................235
LDM0 (Load Multiple Registers) .......................237
LDM1 (Load Multiple Registers) .......................239
LDUB (Load Byte Data in Memory to Register)
..........................................241, 243, 245
LDUH (Load Halfword Data in Memory to Register)
..........................................247, 249, 251
Logical Shift
LSL (Logical Shift to the Left Direction)
..................................................255, 257
LSL2 (Logical Shift to the Left Direction) ..........259
LSR (Logical Shift to the Right Direction)
..................................................261, 263
LSR2 (Logical Shift to the Right Direction) ........265
LSL
LSL (Logical Shift to the Left Direction)
..................................................255, 257
LSL2 (Logical Shift to the Left Direction) ..........259
LSR
LSR (Logical Shift to the Right Direction)
..................................................261, 263
LSR2 (Logical Shift to the Right Direction) ........265
M
MDH
Multiplication/Division Register (MDH, MDL)
............................................................26
MDL
Multiplication/Division Register (MDH, MDL)
............................................................26
MOV
MOV (Move Word Data in Program Status Register
to Destination Register) .......................271
MOV (Move Word Data in Source Register
to Destination Register)
..........................................267, 269, 273
MOV (Move Word Data in Source Register
to Program Status Register) ..................275
Move
MOV (Move Word Data in Program Status Register
to Destination Register) .......................271
MOV (Move Word Data in Source Register
to Destination Register)
..........................................267, 269, 273
MOV (Move Word Data in Source Register
to Program Status Register) ..................275
CM71-00104-3E
MSB
SRCH0 (Search First Zero bit position distance
From MSB) ........................................ 303
SRCH1 (Search First One bit position distance
From MSB) ........................................ 305
MUL
MUL (Multiply Word Data) .............................. 277
MULH
MULH (Multiply Halfword Data) ...................... 279
Multiple
Multiple "EIT" Processing .................................. 49
Multiple "EIT" Processing and Priority Levels
............................................................ 49
Multiple Registers
LDM0 (Load Multiple Registers)....................... 237
LDM1 (Load Multiple Registers)....................... 239
STM0 (Store Multiple Registers) ....................... 337
STM1 (Store Multiple Registers) ....................... 339
Multiplication/Division Register
Multiplication/Division Register (MDH, MDL)
............................................................ 26
Multiply
MUL (Multiply Word Data) .............................. 277
MULH (Multiply Halfword Data) ...................... 279
MULU (Multiply Unsigned Word Data) ............. 281
MULUH (Multiply Unsigned Halfword Data)
.......................................................... 283
MULU
MULU (Multiply Unsigned Word Data) ............. 281
MULUH
MULUH (Multiply Unsigned Halfword Data)
.......................................................... 283
N
NMI
Non-maskable Interrupts (NMI)........................... 44
No Operation
NOP (No Operation)......................................... 285
Non-block loading
Non-block loading.............................................. 61
non-delayed branching
Example of branching with non-delayed branching
instructions ........................................... 62
Non-Delayed Branching Instructions
Non-Delayed Branching Instructions.................... 79
Non-maskable Interrupts
Non-maskable Interrupts (NMI)........................... 44
NOP
NOP (No Operation)......................................... 285
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O
OR
BORH (Or 4bit Immediate Data to Higher 4bit
of Byte Data in Memory)......................129
BORL (Or 4bit Immediate Data to Lower 4bit
of Byte Data in Memory)......................131
OR (Or Word Data of Source Register to Data
in Memory) .........................................287
OR (Or Word Data of Source Register
to Destination Register) ........................289
ORB
ORB (Or Byte Data of Source Register to Data
in Memory) ........................................291
ORCCR
ORCCR (Or Condition Code Register and
Immediate Data) .................................293
ORH
ORH (Or Halfword Data of Source Register to Data
in Memory) ........................................295
Priority Levels of "EIT" Requests ........................ 50
Processing
Multiple "EIT" Processing .................................. 49
Multiple "EIT" Processing and Priority Levels
............................................................ 49
Program Access
Program Access ................................................. 15
Program Counter
Program Counter (PC) ........................................ 22
Program Status
LD (Load Word Data in Memory to Program Status
Register)............................................. 229
MOV (Move Word Data in Program Status Register
to Destination Register) ....................... 271
Program Status (PS) ........................................... 29
Program Status Register
ST (Store Word Data in Program Status Register
to Memory)......................................... 321
PS
Program Status (PS) ........................................... 29
P
R
PC
Program Counter (PC).........................................22
Pipeline
How to prevent mismatched pipeline conditions?
............................................................58
Instruction execution based on Pipeline ................56
Pipeline Operation and Interrupt Processing ..........58
Pointer
ADDSP (Add Stack Pointer and Immediate Data)
............................................................99
Post
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................173
DMOVB (Move Byte Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................179
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................181
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................187
DMOVH (Move Halfword Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................189
Prior Preparation
Types of "EIT" Processing and Prior Preparation
............................................................37
Priority Levels
Multiple "EIT" Processing and Priority Levels
............................................................49
CM71-00104-3E
Read-Modify-Write
Read-Modify-Write type Instructions ................... 76
Recovery
Recovery from "EIT" Processing ......................... 39
Register
Timing of Reflection of Interrupt Level Mask Register
(ILM)................................................... 52
Register Bypassing
Register Bypassing ............................................. 59
Register Configuration
FR80 Family CPU Register Configuration............ 18
Register designated Field
Register designated Field .................................... 73
Register hazard
Occurrence of register hazard .............................. 59
Register hazards ................................................. 59
Register Settings
Timing When Register Settings Are Reflected
............................................................ 51
Remain
DIV2 (Correction When Remain is 0) ................ 157
DIV3 (Correction When Remain is 0) ................ 159
Reset
Reset................................................................. 36
RET
RET (Return from Subroutine) .......................... 297
RET:D
RET:D (Return from Subroutine)....................... 299
RETI
RETI (Return from Interrupt) ............................ 301
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Return
RET (Return from Subroutine)...........................297
RET:D (Return from Subroutine) .......................299
RETI (Return from Interrupt).............................301
Return Pointer
Return Pointer (RP) ............................................22
RP
Return Pointer (RP) ............................................22
S
SCR
System Condition Code Register (SCR)................33
Search
SRCH0 (Search First Zero bit position distance
From MSB)........................................303
SRCH1 (Search First One bit position distance
From MSB)........................................305
SRCHC (Search First bit value change position
distance From MSB) ............................307
Sign Extend
EXTSB (Sign Extend from Byte Data to Word Data)
..........................................................201
EXTSH (Sign Extend from Byte Data to Word Data)
..........................................................203
Signed Division
DIV0S (Initial Setting Up for Signed Division)
..........................................................151
DIV4S (Correction Answer for Signed Division)
..........................................................161
Signed Division ..................................................80
Slot
Branching Instructions and Delay Slot ..................77
Software Interrupt
INT (Software Interrupt) ...................................209
INTE (Software Interrupt for Emulator)..............211
Source Register
ADD (Add Word Data of Source Register
to Destination Register) ..........................87
ADDC (Add Word Data of Source Register and
Carry Bit to Destination Register) ...........91
ADDN (Add Word Data of Source Register
to Destination Register) ..........................95
AND (And Word Data of Source Register to Data
in Memory) ........................................101
AND (And Word Data of Source Register
to Destination Register) ........................103
ANDB (And Byte Data of Source Register to Data
in Memory) .........................................105
ANDH (And Halfword Data of Source Register
to Data in Memory)..............................109
CMP (Compare Word Data in Source Register and
Destination Register)...........................147
CM71-00104-3E
EOR (Exclusive Or Word Data of Source Register
to Destination Register)....................... 195
EOR (Exclusive Or Word Data of Source Register
to Data in Memory) ............................. 193
EORB (Exclusive Or Byte Data of Source Register
to Data in Memory) ............................ 197
EORH (Exclusive Or Halfword Data
of Source Register to Data in Memory)
.......................................................... 199
MOV (Move Word Data in Source Register
to Destination Register)
.......................................... 267, 269, 273
MOV (Move Word Data in Source Register
to Program Status Register) .................. 275
OR (Or Word Data of Source Register to Data
in Memory)........................................ 287
OR (Or Word Data of Source Register
to Destination Register) ....................... 289
ORB (Or Byte Data of Source Register to Data
in Memory)........................................ 291
ORH (Or Halfword Data of Source Register to Data
in Memory)........................................ 295
SUB (Subtract Word Data in Source Register
from Destination Register) ................... 341
SUBC (Subtract Word Data in Source Register and
Carry bit from Destination Register)
.......................................................... 343
SUBN (Subtract Word Data in Source Register
from Destination Register) ................... 345
Special Usage
Special Usage of General-purpose Registers ......... 19
SRCH
SRCH0 (Search First Zero bit position distance
From MSB) ....................................... 303
SRCH1 (Search First One bit position distance
From MSB) ........................................ 305
SRCHC
SRCHC (Search First bit value change position
distance From MSB)............................ 307
SSP
System Stack Pointer (SSP)................................. 23
ST
ST (Store Word Data in Program Status Register
to Memory)......................................... 321
ST (Store Word Data in Register to Memory)
.................. 309, 311, 313, 315, 317, 319
Stack flag
Interlocking produced by after Changing
the Stack flag (S)................................... 60
Stack Pointer
ADDSP (Add Stack Pointer and Immediate Data)
............................................................ 99
Relation between Stack Pointer and "R15"............ 20
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STB
STB (Store Byte Data in Register to Memory)
..........................................323, 325, 327
Step Division Instructions
Step Division Instructions....................................80
Step Trace
Step Trace Traps.................................................47
STH
STH (Store Halfword Data in Register to Memory)
..........................................329, 331, 333
STILM
STILM (Set Immediate Data to Interrupt Level
Mask Register) ....................................335
STM
STM0 (Store Multiple Registers) .......................337
STM1 (Store Multiple Registers) .......................339
Store
ST (Store Word Data in Program Status Register
to Memory) ........................................321
ST (Store Word Data in Register to Memory)
..................309, 311, 313, 315, 317, 319
STB (Store Byte Data in Register to Memory)
..........................................323, 325, 327
STH (Store Halfword Data in Register to Memory)
..........................................329, 331, 333
STM0 (Store Multiple Registers) .......................337
STM1 (Store Multiple Registers) .......................339
SUB
SUB (Subtract Word Data in Source Register
from Destination Register)....................341
SUBC
SUBC (Subtract Word Data in Source Register and
Carry bit from Destination Register)
..........................................................343
SUBN
SUBN (Subtract Word Data in Source Register
from Destination Register)...................345
Subroutine
CALL (Call Subroutine)............................137, 139
CALL:D (Call Subroutine) ........................141, 143
RET (Return from Subroutine)...........................297
RET:D (Return from Subroutine) .......................299
Subtract
SUB (Subtract Word Data in Source Register
from Destination Register)...................341
SUBC (Subtract Word Data in Source Register and
Carry bit from Destination Register)
..........................................................343
SUBN (Subtract Word Data in Source Register
from Destination Register)....................345
System Condition Code Register
System Condition Code Register (SCR)................33
CM71-00104-3E
System Stack Pointer
System Stack Pointer (SSP)................................. 23
T
Table Base Register
Table Base Register (TBR).................................. 25
Test
BTSTH (Test Higher 4bit of Byte Data in Memory)
.......................................................... 133
BTSTL (Test Lower 4bit of Byte Data in Memory)
.......................................................... 135
Trace
Step Trace Traps ................................................ 47
Traps
Step Trace Traps ................................................ 47
Traps................................................................. 46
TBR
Table Base Register (TBR).................................. 25
U
Undefined-instruction
Undefined-instruction exception .......................... 40
Unsign Extend
EXTUB (Unsign Extend from Byte Data
to Word Data) ..................................... 205
EXTUH (Unsign Extend from Byte Data
to Word Data) ..................................... 207
Unsigned Division
DIV0U (Initial Setting Up for Unsigned Division)
.......................................................... 153
Unsigned Division.............................................. 81
Unsigned Halfword Data
MULUH (Multiply Unsigned Halfword Data)
.......................................................... 283
Unsigned Word Data
MULU (Multiply Unsigned Word Data) ............. 281
User Interrupt
Points of Caution while using User Interrupts
............................................................ 54
Preparation while using user interrupts ................. 53
Usage Sequence of User Interrupts....................... 53
User interrupts ................................................... 42
User Stack Pointer
User Stack Pointer (USP) .................................... 24
USP
User Stack Pointer (USP) .................................... 24
V
value change
SRCHC (Search First bit value change position
distance From MSB)............................ 307
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FR80 Family
Vector Table
Vector Table Area ..............................................10
EXTSH (Sign Extend from Byte Data to Word Data)
.......................................................... 203
EXTUB (Unsign Extend from Byte Data
to Word Data) ..................................... 205
EXTUH (Unsign Extend from Byte Data
to Word Data) ..................................... 207
LD (Load Word Data in Memory to Program
Status Register) ................................... 229
LD (Load Word Data in Memory to Register)
.................. 217, 219, 221, 223, 225, 227
MOV (Move Word Data in Program Status Register
to Destination Register) ....................... 271
MOV (Move Word Data in Source Register
to Destination Register) ....... 267, 269, 273
MOV (Move Word Data in Source Register
to Program Status Register) .................. 275
MUL (Multiply Word Data) .............................. 277
MULU (Multiply Unsigned Word Data) ............. 281
OR (Or Word Data of Source Register to Data
in Memory)........................................ 287
OR (Or Word Data of Source Register
to Destination Register) ....................... 289
ST (Store Word Data in Program Status Register
to Memory)........................................ 321
ST (Store Word Data in Register to Memory)
.................. 309, 311, 313, 315, 317, 319
SUB (Subtract Word Data in Source Register
from Destination Register) ................... 341
SUBC (Subtract Word Data in Source Register and
Carry bit from Destination Register)
.......................................................... 343
SUBN (Subtract Word Data in Source Register
from Destination Register) .................. 345
Word Data ......................................................... 14
W
Word Alignment
Word Alignment.................................................15
Word Data
ADD (Add Word Data of Source Register
to Destination Register) ..........................87
ADDC (Add Word Data of Source Register and
Carry Bit to Destination Register) ...........91
ADDN (Add Word Data of Source Register
to Destination Register) ..........................95
AND (And Word Data of Source Register to Data
in Memory) .........................................101
AND (And Word Data of Source Register
to Destination Register) ........................103
CMP (Compare Word Data in Source Register and
Destination Register)............................147
DMOV (Move Word Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................167
DMOV (Move Word Data from Direct Address
to Pre Decrement Register Indirect Address)
..........................................................171
DMOV (Move Word Data from Direct Address
to Register) .........................................163
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..................................................169, 173
DMOV (Move Word Data from Register
to Direct Address)................................165
EOR (Exclusive Or Word Data of Source Register
to Destination Register) ........................195
EOR (Exclusive Or Word Data of Source Register
to Data in Memory).............................193
EXTSB (Sign Extend from Byte Data to Word Data)
..........................................................201
CM71-00104-3E
X
XCHB
XCHB (Exchange Byte Data) ............................ 347
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CM71-00104-3E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR80 Family
32-BIT MICROCONTROLLER
PROGRAMMING MANUAL
September 2010 the third edition
Published
FUJITSU SEMICONDUCTOR LIMITED
Edited
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