S29CD016J and S29CD032J Feature Review and Migration Considerations Application Note 1. Abstract The S29CD-J family was primarily designed for Burst Read Accesses for use in under hood automotive engine and transmission control applications. The S29CD/CL-J family replaced legacy AM29BDD160 and S29CD-G Burst mode flash. This document provides a comparison of their respective feature sets and highlights recommended usage. The topics covered include comparison of: Feature Sets, Package Pin Outs, Burst Read Access Timing, and Recommended Programming Methodologies. 2. Comparison of S29CD/CL-J and Legacy 32-Bit Burst Flash 2.1 Basic Feature Comparison The S29CD-J and S29CL-J flash were designed to replace the AM29BDD-G and the S29CD-G families. The S29CD/CL-J family substantially maintained hardware and software compatibility while offering significant improvements in the device read margins and offering faster initial access timing. 2.1.1 Architecture / Feature Comparisons Table 2.1 provides a feature comparison summary for the S29CD/CL-J, S29CD/CL-G and AM29BDD-G flash families. Table 2.1 Feature Comparison (Sheet 1 of 2) Feature / Family Am29BDD160G S29CD016J S29CL016J S29CD016G Lithography 170 nm 170 nm 110 nm Data Bus x16 or x32 x32 x32 VCC Range 2.5 - 2.75 V 2.5 - 2.75 V 2.5 - 2.75V 3.0 - 3.6V VIO Range 3.6V tolerant I/O 3.6V tolerant I/O 3.6V tolerant I/O Sim. R/W Bank Architecture 2 Banks: 75% / 25% 2 Banks: 75% / 25% 2 Banks: 75% / 25% Secure Silicon Region 256 byte 256 byte Electronic Marking 256 byte Electronic Marking WP# Option Protects 2 outermost sectors of large bank Protects 2 outermost sectors of large bank Protects 2 outermost sectors of large bank Erase/Program Suspend/ Resume Program/Erase Suspend/ Resume Program/Erase Suspend/ Resume Program/Erase Suspend/ Resume Sector Protection Advance Sector Protection Advance Sector Protection Advance Sector Protection Device ID 7E, 08, 01/00 7E, 36, 01/00 7E, 08, 01/00 7E, 36, 01/00 (2.6V) or 7E, 08, 01/00 (2.6V) 7E, 46, 01/00 (3.3V) Manufacture ID 01 01 01 Chip ID Electronic Info Not Available Located in Secure Sector 3Q2005 Dedicated OTP Chip ID Speed Option Clock Rate 40 MHz, 56 MHz, 66 MHz 40 MHz, 56 MHz, 66 MHz 40 MHz, 56 MHz, 66 MHz Publication Number S29CD016_32J_Migration_AN Revision 01 Issue Date January 17, 2011 A pplication Note Table 2.1 Feature Comparison (Sheet 2 of 2) Feature / Family 2.1.2 2.1.2.1 Am29BDD160G S29CD016J S29CL016J S29CD016G Package Options 80-Pin PQFP 80-Ball FBGA KGD 80-Pin PQFP 80-Ball FBGA KGD 80-Pin PQFP 80-Ball FBGA KGD Dual-Op One direction One direction Bi-direction Configuration Register CR14=0 default CR14=1 disable Auto Sleep Mode CR14=1 disable Auto Sleep Mode Bank Architecture Bank 1 and 2 Bank 0 and 1 Bank 0 and 1 CFI Table Address 28h 1Bh 51h Data 05h (x16, x32) Data: 0023h min VCC Data 00h no unlock bypass Data 03h (x32 only) Data: 0023h min VCC Data 00h no unlock bypass Data 03h (x32 only) Data: 0025h min VCC Data 01h unlock bypass CLK Tolerance 2.75V 3.6V 3.6V Typical Program Time (Double Word) 18 µs 18 µs 8 µs Program Time in Unlock Bypass Mode (Double Word) 18 µs 18 µs 8 µs Program Time in ACC Mode (Double Word) 18 µs 18 µs 8 µs Package Pin Out Comparison PQRP-80 Figure 2.1 highlights the S29CD/CL-J pin compatibility with both the AM29BDD160G and the S29CD-G families in the PQRP-80. Table 2.2 details AM29BDD160 and S29CD-G usage for pins 21 and 80. VIO RESET# CLK NC RY/BY# ADV# NC VSS VCC CE# OE# WE# WP# NC IND/WAIT# NC Figure 2.1 PQFP Pin Out 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DQ16 DQ17 DQ18 DQ19 VIO VSS DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VIO VSS DQ28 DQ29 DQ30 DQ31 NC A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80-Pin PQFP DQ15 DQ14 DQ13 DQ12 VSS VIO DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSS VIO DQ3 DQ2 DQ1 DQ0 A19 A18 A17 A16 2 A15 A14 A13 A12 A11 A10 A9 VCC ACC VSS A8 A7 A6 A5 A4 A3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S29CD016J and S29CD032J Feature Review and Migration Considerations January 17, 2011 Ap pl ic atio n No t e Table 2.2 PQRP-80 Package Comparison Pin# 2.1.2.2 AM29BDD-G S29CD-G S29CD/CL-J Comment 21 A-1 VCC Pull-up NC: Not Internally Connected 80 WORD# VCC Pull-up NC: Not Internally Connected BDD160G: In order to operate in x32 mode, the Word pin must be connected to high and A-1 pin can be connected to high or low. 80-Ball Fortified BGA Figure 2.2 highlights the S29CD/CL-J pin compatibility with both the AM29BDD160G and the S29CD-G families in the 80 Ball BGA package. Table 2.3 details the AM29BDD160 and S29CD-G usage for balls C7 and K8, which are NC on the S29CD-J. Figure 2.2 80-Ball BGA A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 A2 A1 A0 DQ29 VIO VSS VIO DQ20 DQ16 NC A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 A3 A4 NC DQ30 DQ26 DQ24 DQ23 DQ18 IND/WAIT# NC A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 DQ21 DQ19 OE# WE# A6 A5 A7 DQ31 DQ28 DQ25 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 VSS A8 NC NC DQ27 RY/BY# DQ22 DQ17 CE# VCC A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 ACC A9 A10 NC DQ1 DQ5 DQ9 WP# NC VSS A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 VCC A12 A11 A19 DQ2 DQ6 DQ10 DQ11 ADV# CLK A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 A14 A13 A18 DQ0 DQ4 DQ7 DQ8 DQ12 DQ14 RESET# A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 A15 A16 A17 DQ3 VIO VSS VIO DQ13 DQ15 VCCQ Table 2.3 80-Ball BGA Pin Out Comparison Pin# C7 K8 January 17, 2011 AM29BDD-G A-1 WORD# S29CD-G S29CD/CL-J VCC Pull-up NC: Not Internally Connected VCC Pull-up NC: Not Internally Connected Comment BDD160G: In order to operate in x32 mode, the Word pin must be connected to high and A-1 pin can be connected to high or low. S29CD016J and S29CD032J Feature Review and Migration Considerations 3 A pplication 2.2 Note Flash Burst Read Accesses The AM29BDD160G, S29CD-G, and S20CD/CL-J families support both Asynchronous and Synchronous (Burst) accesses. Burst access improves systems performance by reducing the time required for a microcontroller to capture a series of sequential data from the flash. Consider the read access times using asynchronous and synchronous accesses: The clock period for a S29CD016J operating at 56 MHz is ~17.85 ns, while the initial access time is 54 ns. The asynchronous access the flash device performs a random access for every address in a set of sequential data. The total time to read the series of data is the sum of the initial access time for each data access. The total asynchronous access time = tIACC1 + tIACC2 + tIACC3 + tIACC4 = 54 ns + 54 ns + 54 ns + 54 ns = 216 ns Burst read enables sequential data outputs on every clock cycle after the initial access is completed. The total time to read a data series in burst mode is the sum of the one initial access time plus the sum of each clock period. The total burst read access time = tIACC1 + tCLK2 + tCLK3 + tCLK4 = 54 ns + 17.85 ns + 17.85 ns + 17.85 ns + 17.85 ns = 107.55 ns The burst read access mode significantly reduces the overall access time for sequential data reads compared to asynchronous access. 2.2.1 Initial Burst Read Access AM29BDD160G and S29CD-G The initial read access for Am29BDD160G and S29CD016G can only begin once CE# and ADV# are driven low, as the CE# blocks the ADV# signal. See Figure 2.3. Figure 2.3 Initial Burst Read Access Am29BDD160G and S29CD016G CLK ADV# CE# Addresses Valid Address DATA Data tIACC 2.2.2 Initial Read Access S29CD/CL-J Spansion reviewed how many microcontrollers assert control signals during initial flash access and determined that ADV# is asserted prior to asserting the CE#, which adds additional delay to the S29CD-G initial access. The S29CD/CL-J design further optimizes the overall read bandwidth by further reducing the initial access time compared to the AM29BDD160 and S29CD-G devices. The S29CD/CL-J design decouples the CE# and ADV# signals. Now the initial read access is initiated by the later of the falling edge of ADV# or when the address is valid. See Figure 2.4 and Figure 2.5 which show the S29CD/CL-J initial access timing and that the initial access time is not delayed by the timing of the CE# assertion. 4 S29CD016J and S29CD032J Feature Review and Migration Considerations January 17, 2011 Ap pl ic atio n No t e Figure 2.4 Initial Burst Read Access S29CD/CL-J CLK ADV# CE# Addresses Valid Address Data DATA DATA tIACC S29CD/CL-J Burst Read Initial Access CLK ADV# CE# Addresses Valid Address DATA Data DATA tIACC S29CD/CL-J Burst Read Initial Access Timing (ADV# asserted after Address is valid) 2.2.3 Configuring the S29CD016J for Burst Mode The S29CD/CL-J supports a Configuration Register which defines burst mode operation. The Configuration Register commands provide access to set the Configuration Register parameters. One of the key burst mode parameters in the Configuration Register is the Initial Burst Access Delay Configuration (IAD3-IAD0), which determines the number of clock cycles that must occur between address latching and the output of the first burst data. Table 2.4 shows the Configuration Register bit settings and the corresponding clock cycles. Table 2.4 Burst Initial Access Delay Nomenclature and Configuration Register Settings January 17, 2011 Initial Burst Access Configuration Register (IAD3-IAD0) CR13-CR10 Initial Burst Access Clock Cycles 4-1-1-1 0010 4 CLK cycle initial burst access delay 5-1-1-1 0011 5 CLK cycle initial burst access delay 6-1-1-1 0100 6 CLK cycle initial burst access delay 7-1-1-1 0101 7 CLK cycle initial burst access delay 8-1-1-1 0110 8 CLK cycle initial burst access delay 9-1-1-1 0111 9 CLK cycle initial burst access delay S29CD016J and S29CD032J Feature Review and Migration Considerations 5 A pplication Note Figure 2.5 shows the timing diagram for a 5-1-1-1 burst mode access. The initial access is started by the later occurrence of the falling edge of ADV# or by address valid during the first clock cycle. The data is output during the fifth clock cycle and the processor reads the data on the sixth clock cycle. New data is output on subsequent rising clock edges until the burst read is completed. Figure 2.5 5-1-1-1 Burst Read Access Processor Latches Data CLK ADV# Addresses 1st CLK 2nd CLK WS 1 WS 2 CLK to ADV 3rd CLK WS 3 4th CLK 5th CLK WS 4 Initial Access Starts Here Valid Addr DQ31-DQ0 D0 Initial Access Done - 1 st 64 bit Burst Access Starts 2.3 6 th CLK D1 D2 2nd 64 bit Burst Access Starts Recommended Programming Setup and Execution In many system implementations, the S29CD-J/S29CL-J flash device shares an External Bus Interface with other peripherals such as SRAM, which can support Burst Read capabilities (see Figure 2.6). The System Controller can access the S29CD-J/S29CL-J and perform basic read, erase, and program operations. During embedded flash programming operations system noise, along with extensive Burst Read activity on the External Bus Interface could create conditions where programming errors could occur in the S29CD032J/S29CL032J. This behavior has been observed in an application where the System Controller executes code from external SRAM while programming the S29CD032J/S29CL032J flash device. This issue has never been observed in other applications using the S29CD/CL016J or in systems where the System Controller executes the code to from its internal SRAM to complete the programming. 6 S29CD016J and S29CD032J Feature Review and Migration Considerations January 17, 2011 Ap pl ic atio n No t e Figure 2.6 External Bus Interface System Controller Address Bus External Bus Interface Spansion Flash Memory S29CD032J/S29CL032J Control Lines SRAM Memory Data Bus During the embedded programming operation, Spansion recommends mitigating ADV# signal activity (burst read accesses to other peripherals on the External Bus Interface) after the program command sequence has been sent by the System Controller. Upon completion of the embedded programming operation, normal burst read activity can resume on this bus. The timing diagram below highlights the start and stop of the “quiet bus time” (tWHWH1). During time tWHWH1 it is recommended to minimize burst read activity on the External Bus Interface. Figure 2.7 Program Operation Timing Program Command Sequence (last two cycles) tAS tWC 555h Addresses Read Status Data (last two cycles) PA CE# PA PA tCH OE# tAH tWHWH1 tWP WE# tWPH tCS tDS A0h Data tDH tDH PD Status tBUSY DOUT tRB RY/BY# VCC tVCS January 17, 2011 S29CD016J and S29CD032J Feature Review and Migration Considerations 7 A pplication Note Spansion also recommends the use of high reliability programming methodologies for non-consumer applications. Please reference the Spansion application note High Reliability Programming Methodologies http://www.spansion.com/Support/AppNotes/High_Reliability_Prog_Methodology_AN.pdf for additional background information and implementation guidance. 3. Conclusion S29CD/CL-J The S29CD/CL-J family replaces the legacy AM29BDD160 and S29CD-G Burst mode flash; all these flash devices support Burst Read Accesses which is a key feature for use in under hood automotive engine and transmission control applications. This document reviews the feature sets, performance, and recommended usage differences between the S29CD/CL-J family and the legacy Burst Read flash. Examples S29CD/CL-J design changes like decoupling the CE# and the ADV# signals to enable earlier start of Initial Burst Read Accesses and recommended programming practices were also provided. This information is important for customers migrating to the CD016J, or using the device for the first time. 4. References S29CD/CL-J Data Sheet High Reliability Programming Methodology for Floating Gate Flash 8 S29CD016J and S29CD032J Feature Review and Migration Considerations January 17, 2011 App l ic atio n No t e 5. Revision History Section Description Revision 01 (January 17, 2011) Initial Release January 17, 2011 S29CD016J and S29CD032J Feature Review and Migration Considerations 9 A pplication Note Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 10 S29CD016J and S29CD032J Feature Review and Migration Considerations January 17, 2011