Datasheet

S70FL256P
256-Mbit 3.0V Flash
This product is not recommended for new and current designs. For new and current designs, the S25FL256S supersedes S70FL256P. This is the
factory-recommended migration path. Refer to the S25FL256S datasheet for specifications and ordering information, and AN98592 for changes
required to migrate from existing designs based on S70FL256P.
Distinctive Characteristics
Architectural Advantages
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Performance Characteristics
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 Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
 Power Saving Standby Mode
– Standby Mode 160 µA (typical)
– Deep Power-Down Mode 6 µA (typical)
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 Single Power Supply Operation
– Full voltage range: 2.7 to 3.6V read and write operations
 Memory Architecture
– Uniform 64 kB sectors
– Top or bottom parameter block (Two 64-kB sectors
broken down into sixteen 4-kB sub-sectors each) for
each Flash die
– Uniform 256 kB sectors (no 4-kB sub-sectors)
– 256-byte page size
 Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
 Erase
– Bulk erase function for each Flash die
– Sector erase (SE) command (D8h) for 64 kB and 256 kB
sectors
– Sub-sector erase (P4E) command (20h) for 4 kB sectors
(for uniform 64-kB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 kB sectors
(for uniform 64-kB sector device only)
 Cycling Endurance
– 100,000 cycles per sector typical
 Data Retention
– 20 years typical
 Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
 One-time programmable (OTP) area on each Flash die for
permanent, secure identification; can be programmed and
locked at the factory or by the customer
 CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash devices
 Process Technology
– Manufactured on 0.09 µm MirrorBit® process technology
 Package Option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 24-ball BGA (6  8 mm) package, 5  5 pin configuration
Memory Protection Features
 Memory Protection
– W#/ACC pin works in conjunction with Status Register Bits
to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Software Features
N
– SPI Bus Compatible Serial Interface
General Description
This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die. For detailed
specifications, refer to the discrete die datasheet.
Document Name
Cypress Document Number
S25FL129P, 128-Mbit 3.0V Flash Memory Datasheet
002-00648
Cypress Semiconductor Corporation
Document Number: 002-00647 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 10, 2016
S70FL256P
Contents
1.
Block Diagram.............................................................. 3
7.
DC Characteristics........................................................ 7
2.
Connection Diagrams.................................................. 4
8.
Test Conditions ............................................................. 8
3.
Input/Output Description............................................. 5
4.
Logic Symbol ............................................................... 5
9.
9.1
AC Characteristics........................................................ 9
Capacitance .................................................................. 10
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Device Operations .......................................................
Programming .................................................................
Simultaneous Die Operation ..........................................
Sequential Reads...........................................................
Sector/Bulk Erase ..........................................................
Status Register ..............................................................
Configuration Register ...................................................
Block Protection .............................................................
6.
Read Identification (RDID)........................................... 6
10. Ordering Information .................................................. 11
10.1 Valid Combinations ....................................................... 11
6
6
6
6
6
6
6
6
Revision History.......................................................... 14
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12.
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11. Physical Dimensions .................................................. 12
11.1 SL3 016 — 16-pin Wide Plastic Small
Outline Package (300-mil Body Width) .........................12
11.2 ZSA024 — 24-ball Ball Grid Array (6 ´ 8 mm)
Package ........................................................................13
Document Number: 002-00647 Rev. *F
Page 2 of 16
S70FL256P
1. Block Diagram
SI/IO0
S I/IO 0
W #/A C C /IO 2
W#/ACC/IO2
S O /IO 1
SO/IO1
CS#1
CS#
VSS
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SCK
VCC
VSS
VCC
ew
SCK
FL129P
Flash
Memory
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H O LD #/IO 3
HOLD#/IO3
S O /IO 1
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W #/A C C /IO 2
N
S I/IO 0
H O LD #/IO 3
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FL129P
Flash
Memory
VSS
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SCK
CS#
VCC
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CS#2
Document Number: 002-00647 Rev. *F
Page 3 of 16
S70FL256P
2.
Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
1
16
SCK
VCC
2
15
SI/IO0
DNC
3
14
DNC
DNC
4
13
DNC
DNC
5
12
DNC
CS2#
6
11
DNC
CS1#
7
10
GND
SO/IO1
8
9
W#/ACC/IO2
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Note:
DNC = Do Not Connect (Reserved for future use)
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HOLD#/IO3
2
A
DNC
en
B
DNC
5
DNC
DNC
VCC
DNC
SCK
GND
CS1#
CS2# W#/ACC/IO2 DNC
DNC
SO/IO1
SI/IO0 HOLD#/IO3 DNC
DNC
DNC
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Figure 2.2 6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration
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DNC
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DNC
DNC
DNC
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Document Number: 002-00647 Rev. *F
Page 4 of 16
S70FL256P
3.
Input/Output Description
I/O
Description
SO/IO1
I/O
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as
an I/O pin in Dual and Quad I/O, and Quad Page Program modes.
SI/IO0
I/O
Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and
program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual and Quad I/O mode.
SCK
Input
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising
edge of SCK. Triggers output on SO after the falling edge of SCK.
CS1#
CS2#
Input
Chip Selects: Places one of the Flash die in active power mode when driven low. Deselects Flash die
and places SO at high impedance when high. After power-up, device requires a falling edge on CS1#
and CS2# before any command is written. Device is in standby mode when a program, erase, or Write
Status Register operation is not in progress.
HOLD#/IO3
I/O
Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is
at high impedance, and all input at SI and SCK are ignored. Requires that CS1# or CS2# also be driven
low. Functions as an I/O pin in Quad I/O mode.
W#/ACC/IO2
I/O
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low,
prevents any program or erase command from altering the data in the protected memory area.
Functions as an I/O pin in Quad I/O mode.
VCC
Input
Supply Voltage
GND
Input
Ground
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Signal
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4. Logic Symbol
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VCC
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SI/IO0
SO/IO1
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SCK
CS1#
CS2#
W#/ACC/IO2
HOLD#/IO3
GND
Document Number: 002-00647 Rev. *F
Page 5 of 16
S70FL256P
5. Device Operations
5.1
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
5.2
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
Sequential Reads
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5.3
5.4
D
es
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to
sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#.
Sector/Bulk Erase
Status Register
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5.5
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A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is
not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die.
Configuration Register
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5.6
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Each Flash die of the dual die stack is managed by its own Status Register. Reads and updates to the Status Registers must be
managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain
consistency when switching between die.
Block Protection
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Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits
must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to
maintain consistency when switching between die.
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ot
R
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must
be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no
address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain
consistency when switching between die.
6. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device
identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the FL256P dual die stack will have identical
identification data as the FL129P die, with the exception of the CFI data at byte 27h, as shown in Table 6.1.
Table 6.1 Product Group CFI Device Geometry Definition
Byte
Data
Description
27h
19h
Device Size = 2^N byte
Document Number: 002-00647 Rev. *F
Page 6 of 16
S70FL256P
7.
DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit
match the measurement conditions specified in the Test Specifications in Table 8.1 on page 8, when relying on the quoted
parameters.
Table 7.1 DC Characteristics (CMOS Compatible)
Test Conditions

VCC
Supply Voltage
VHH
ACC Program Acceleration Voltage
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Limits
Typ. (1)
Max.
2.7
3.6
V
VCC - 0.6








2
µA
µA
VCC = 2.7V to 3.6V
8.5


0.3
0.7 x VCC
IOL = 1.6 mA, VCC = VCC min.
IOH = -0.1 mA
Unit
Min.
9.5
V
0.3 x VCC
V
VCC +0.5
V
0.4
V
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Parameter
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Symbol

V
Input Leakage Current
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
VCC = VCC Max,
VIN = VCC or GND


2
At 80 MHz
(Dual or Quad)


44
At 104 MHz (Serial)


32
At 40 MHz (Serial)


CS# = VCC


26
mA
CS# = VCC






15
mA
26
mA
26
mA
CS# = VCC;
SO + VIN = GND or VCC

160
500
µA
CS# = VCC;
SO + VIN = GND or VCC

6
20
µA
ICC2
Active Power Supply Current (Page
Program)
ICC3
Active Power Supply Current (WRR)
ICC4
Active Power Supply Current (SE)
ICC5
Active Power Supply Current (BE) (2)
ISB1
Standby Current
IPD
Deep Power-down Current
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ICC1
Active Power Supply Current - READ
(SO = Open)
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ILI
CS# = VCC
CS# = VCC
mA
15
ot
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
N
2. Bulk Erase is on a die per die basis, not for the whole device.
Document Number: 002-00647 Rev. *F
Page 7 of 16
S70FL256P
8. Test Conditions
Figure 8.1 AC Measurements I/O Waveform
0.8 VCC
0.7 VCC
0.5 VCC
0.3 VCC
Input Levels
0.2 VCC
Table 8.1 Test Specifications
Parameter
Min
CL
Load Capacitance
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Symbol
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Input and Output
Timing Reference levels
Max
30
Input Rise and Fall Times (1)
N
Output Timing Reference Voltage
5
ns
0.2 VCC to 0.8 VCC
V
V
0.5 VCC
V
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Note:
1. Input rise and fall times are 0-100%.
pF
0.3 VCC to 0.7 VCC
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Input Pulse Voltage
Input Timing Reference Voltage
Unit
Document Number: 002-00647 Rev. *F
Page 8 of 16
S70FL256P
9.
AC Characteristics
Table 9.1 AC Characteristics
Typ
(Notes)
Max (Notes)
Unit
SCK Clock Frequency for READ command
SCK Clock Frequency for RDID command
SCK Clock Frequency for all others:
FAST_READ, PP, QPP, P4E, P8E, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRR, READ_ID
DC
DC


40
50
MHz
MHz
DC

104 (serial)
80 (dual/quad)
MHz
Clock High Time
Clock Low Time
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
4.5
4.5
0.1
0.1








ns
ns
V/ns
V/ns
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50
3
3
3
2


ns
tCSS
tCSH








ns
ns
ns
ns
tSU:DAT
tHD:DAT
0

9 (Serial)
10.5 (Dual/Quad)
7.8 (Serial)
9 (Dual/Quad)
ns
0











Clock Low to Output Valid
tHO
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tV
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
Data in Hold Time
tDP
tVHH
tWC
Time to enter Deep Power-down Mode
ACC Voltage Rise and Fall time
ACC at VHH and VIL or VIH to first command
tSE
tBE
tPE
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tHLCH
tCHHH
tHHCH
tCHHL
tHZ
tLZ
tWPS
tWPH
tW
tPP
tEP
en
tRES
Output Hold Time
Output Disable Time
HOLD# Active Setup Time (relative to SCK)
HOLD# Active Hold Time (relative to SCK)
HOLD# Non Active Setup Time (relative to SCK)
HOLD# Non Active Hold Time (relative to SCK)
HOLD# enable to Output Invalid
HOLD# disable to Output Valid
W#/ACC Setup Time (4)
W#/ACC Hold Time (4)
WRR Cycle Time
Page Programming (1)(2)
Page Programming (ACC = 9V) (1)(2)(3)
Sector Erase Time (64 kB) (1)(2)
Sector Erase Time (256 kB) (1)(2)
Bulk Erase Time (1)(2)(8)
Parameter Sector Erase Time (4 kB or 8 kB) (1)(2)
Deep Power-down to Standby Mode
tDIS
D
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tCS (9)
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tWH, tCH (5)
tWL, tCL (5)
tCRT, tCLCH
tCFT, tCHCL
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fR
Parameter (Notes)

3
3
3
3


20
100









2.2
5
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n
Min.
(Notes)
Symbol (Notes)
1.5
1.2
0.5
2
128
200





8




8
8


50
3
2.4
2
8
256
800
30
10


ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
sec
sec
sec
ms
µs
µs
µs

Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern.
2. Under worst-case conditions of 85°C; VCC = 2.7V; 100,000 cycles.
3. Acceleration mode (9V ACC) only in Program mode, not Erase.
Document Number: 002-00647 Rev. *F
Page 9 of 16
S70FL256P
4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
5. tWH + tWL must be less than or equal to 1/fC.
6.  Full Vcc range (2.7 – 3.6V) and CL = 30 pF.
7.  Regulated Vcc range (3.0 – 3.6V) and CL = 30 pF.
8. Bulk Erase is on a die per die basis, not for the whole device.
9. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
to be valid.
Capacitance
CIN
COUT
Parameter
Test Conditions
Input Capacitance
(applies to CS1#, CS2#, SCK, SI/IO0, SO/IO1, W#/ACC/IO2,
HOLD#/IO3)
VOUT = 0V
Min
Output Capacitance
(applies to SI/IO0, SO/IO1, W#/ACC/IO2, HOLD#/IO3)
VIN = 0V
Max
Unit

10.0
16.0
pF

22.0
30.0
pF
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Notes:
1. Sampled, not 100% tested.
Typ
ig
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Symbol
D
es
9.1
2. Test conditions TA = 25°C, f = 1.0 MHz.
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3. For more information on pin capacitance, please consult the IBIS models.
Document Number: 002-00647 Rev. *F
Page 10 of 16
S70FL256P
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL
256
P
0X
M
F
I
00
1
Packing Type (Note 1)
0 = Tray
1 = Tube
3 = 13” Tape and Reel
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Model Number (Additional Ordering Options)
21 = BGA package, Uniform 256 kB sectors
20 = BGA package, Uniform 64 kB sectors
01 = SO package, Uniform 256 kB sectors
00 = SO package, Uniform 64 kB sectors
Temperature Range
I = Industrial (–40°C to + 85°C)
D
es
Package Materials
F = Lead (Pb)-free
H = Low-Halogen, Lead (Pb)-free
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Package Type
M = 16-pin SO package
B = 24-ball BGA 6  8 mm package, 1.00 mm pitch
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Speed
0X = 104 MHz
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Device Technology
P = 0.09 µm MirrorBit® Process Technology
Density
256 = 256 Mbit
Valid Combinations
m
10.1
en
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Device Family
S70FL
Cypress Stacked Memory 3.0V-Only, Serial Peripheral Interface (SPI) Flash Memory
om
Table 10.1 lists the valid combinations configurations planned to be supported in volume for this device.
ec
Table 10.1 S70FL256P Valid Combinations Table
Speed Option
S70FL256P
N
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Base Ordering
Part Number
R
S70FL256P Valid Combinations
Package and
Temperature
MFI
0X
BHI
Model
Number
00
01
20
21
Packing Type
0, 1, 3
0, 3
Package Marking
70FL256P0XMFI00
70FL256P0XMFI01
70FL256P0XBHI20
70FL256P0XBHI21
Note:
1. Package Marking omits the leading “S70” and speed, package and model number.
Document Number: 002-00647 Rev. *F
Page 11 of 16
S70FL256P
11. Physical Dimensions
SL3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
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11.1
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NOTES:
1.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
SL3016 (inches)
SL3016 (mm)
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
JEDEC
MS-013(D)AA
MS-013(D)AA
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
MIN
MAX
MIN
A
0.093
0.104
2.35
A1
0.004
0.012
A2
0.081
0.104
b
0.012
0.020
b1
0.011
c
0.008
c1
0.008
E
e
L
0.019
0.27
ec
0.48
0.013
0.20
0.33
0.012
0.20
0.30
R
2.55
0.51
0.406 BSC
10.30 BSC
10.30 BSC
0.295 BSC
7.50 BSC
.050 BSC
1.27 BSC
0.016
0.050
0.40
.055 REF
1.40 REF
L2
.010 BSC
0.25 BSC
16
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
16
h
0.10
0.30
0.25
θ
0°
8°
0°
8°
θ1
5°
15°
5°
15°
θ2
4.
1.27
L1
N
.
0.30
0.31
0.406 BSC
N
E1
2.65
0.10
2.05
ot
D
MAX
om
SYMBOL
m
PACKAGE
0°
0.75
0°
3644 \ 16-038.03 Rev C \ 02.03.10 (JK)
Document Number: 002-00647 Rev. *F
Page 12 of 16
S70FL256P
ZSA024 — 24-ball Ball Grid Array (6  8 mm) Package
ZSA024
JEDEC
N/A
1.
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.20
---
---
A2
0.70
---
0.90
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
4.00 BSC.
MATRIX FOOTPRINT
E1
4.00 BSC.
MATRIX FOOTPRINT
MD
5
ME
5
n
24
1.00 BSC
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
MATRIX SIZE E DIRECTION
0.45
BALL DIAMETER
0.00
N
ot
A1
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
BALL COUNT
R
eD
SD / SE
om
0.40
1.00 BSC.
MATRIX SIZE D DIRECTION
ec
0.35
eE
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
m
D
Øb
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
de
8.00 mm x 6.00 mm
PACKAGE
en
DxE
NOTES:
d
PACKAGE
fo
r
N
ew
D
es
ig
n
11.2
7
BALL PITCH
BALL PITCH
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
SOLDER BALL PLACEMENT
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3645 16-038.86 Rev A \ 02.26.10
Document Number: 002-00647 Rev. *F
Page 13 of 16
S70FL256P
12. Revision History
Document History Page
Document Title: S70FL256P, 256-Mbit 3.0V Flash
Document Number: 002-00647
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
–
BWHA
03/03/2010
Initial release
03/17/2010
Valid Combinations:
Corrected Package Marking specification from discrete to MCP format
Read Identification (RDID):
Added section to explain CFI change from FL129P
BWHA
ig
n
–
General:
Changed product description from “256-Mbit CMOS 3.0 Volt Flash Memory with
93-MHz SPI Serial (Serial Peripheral Interface) Multi I/O Bus” to “256-Mbit
CMOS 3.0 Volt Flash Memory with 104-MHz SPI Serial (Serial Peripheral
Interface) Multi I/O Bus”
Changed data sheet status from Advanced Information to Preliminary
Distinctive Characteristics:
Changed Normal READ clock rate from 36 to 40 MHz
Changed FAST_READ maximum clock rate from 93 to 104 MHz
Changed DUAL I/O FAST_READ clock rate from 72 to 80 MHz and effective
data rate from18 to 20 MB/s
Ordering Information:
Changed description for Speed characters 0X from 93 to 104 MHz
DC Characteristics:
Changed ILI (Input Leakage Current) value from ± 4 to ± 2 µA (max)
Changed ILO (Output Leakage Current) value from ± 4 to ± 2 µA (max)
Changed ICC1 (Active Power Supply Current - READ) test condition frequencies
from 72/93/36 MHz to 80/104/40 MHz
Changed ICC1 (Active Power Supply Current - READ) value @ 80 MHz (dual/
quad) from 41.8 to 44 mA (max)
Changed ICC1 (Active Power Supply Current - READ) value @ 104 MHz (serial)
from 27.5 to 32 mA (max)
Changed ICC1 (Active Power Supply Current - READ) value @ 40 MHz (serial)
from13.2 to 15 mA (max)
Changed ICC2 (Active Power Supply Current - Page Program) value from 28.6
to 26 mA (max)
Changed ICC3 (Active Power Supply Current - WRR) value from 16.5 to 15 mA
(max)
Changed ICC4 (Active Power Supply Current - SE) value from 28.6 to 26 mA
(max)
Changed ICC5 (Active Power Supply Current - BE) value from 28.6 to 26 mA
(max)
Added Note 2, clarifying that Bulk Erase is on a die per die basis, not for the
whole device
Test Conditions:
Added note clarifying that input rise and fall times are 0-100%
–
BWHA
06/17/2010
N
ot
R
ec
om
*B
m
en
de
d
fo
r
N
ew
D
es
*A
Description of Change
Document Number: 002-00647 Rev. *F
Page 14 of 16
S70FL256P
Document History Page (Continued)
Document Title: S70FL256P, 256-Mbit 3.0V Flash
Document Number: 002-00647
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
–
BWHA
06/17/2010
*C
–
BWHA
06/24/2011
Global:
Promoted data sheet designation from Preliminary to Full Production
*D
–
BWHA
01/30/2013
Capacitance:
Added “Typical” values column
Corrected “Max” values for CIN / COUT (Input / Output Capacitance)
*E
4925834
BWHA
09/24/2015
*F
5155743
BWHA
03/10/2016
en
de
d
fo
r
N
ew
D
es
ig
n
*B (cont.)
AC Characteristics:
Changed fR (SCK Frequency for READ/RDID) values from 36/45 to 40/50 MHz
(max)
Changed fC (SCK Frequency for others) values from 93/72 to 104/80 MHz
(max)
Changed tV (Clock Low to Output Valid) values from 9.6/11.4/7.8/9.6 to 9/10.5/
7.8/9 ns (max)
Added tBE (Bulk Erase Time)
Added Note 8 clarifying that Bulk Erase is on a die per die basis, not for the
whole device
Added Note 9 clarifying that a minimum time of tCS must be kept between the
rising edge of one chip select and the falling edge of the other when switching
between die for proper device functionality.
Capacitance:
Merged CIN capacitance values into a single line item
Merged Single I/O, Dual I/O, and Quad I/O max capacitance values into a single
line item
Added CIN / COUT (Input / Output Capacitance) values of 6/8 pF (max)
Added Notes clarifying test conditions
m
Updated to Cypress template
N
ot
R
ec
om
Added NRND note in page 1 specifying the suggested replacement parts.
Updated General Description.
Document Number: 002-00647 Rev. *F
Page 15 of 16
S70FL256P
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
cypress.com/arm
cypress.com/psoc
cypress.com/automotive
Clocks & Buffers
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/clocks
Interface
Cypress Developer Community
cypress.com/interface
Lighting & Power Control
Community | Forums | Blogs | Video | Training
cypress.com/powerpsoc
Memory
Technical Support
cypress.com/memory
PSoC
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
cypress.com/usb
ew
cypress.com/wireless
N
ot
R
ec
om
m
en
de
d
fo
r
N
Wireless/RF
ig
n
Automotive
D
es
ARM® Cortex® Microcontrollers
© Cypress Semiconductor Corporation 2010-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 002-00647 Rev. *F
Revised March 10, 2016
Page 16 of 16
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