AN98581 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family AN98581 provides conversion guidelines for migrating from the Microchip SST25VF-B, SST25VF-C and SST26VF SPI series to the Cypress S25FL1-K SPI Flash Family. Cypress S25FL1-K flash is a feature rich and cost-optimized serial peripheral interface (SPI), non-volatile NOR flash family manufactured on a 90 nm 3-volt floating gate process. Contents 1 2 1 Introduction ............................................................... 1 Feature Comparison ................................................. 1 2.1 Hardware Package ........................................... 3 2.2 Block Structure ................................................. 3 2.3 Program Method ............................................... 4 2.4 Multi-I/O Operation ........................................... 4 2.5 Status Registers ............................................... 4 2.6 Block Protection Scheme ................................. 6 2.7 Variable Latency ............................................... 8 2.8 Burst Read Mode ............................................. 8 2.9 OTP (One-Time Program) Area ........................8 2.10 Reset Operations ..............................................8 3 Command Set Comparison ....................................... 9 4 Timing Considerations ............................................. 11 4.1 Power-Up Timing ............................................11 4.2 Data In Setup/Hold Time .................................12 4.3 Further Timing Comparison ............................12 5 Conclusion............................................................... 13 Document History Page ...................................................14 Worldwide Sales and Design Support ..............................15 Introduction Cypress S25FL1-K flash is a feature rich and cost-optimized serial peripheral interface (SPI), non-volatile NOR flash family manufactured on a 90 nm 3-volt floating gate process. The S25FL1-K family is composed of three members: S25FL116K 16 Mbit (2 MB) S25FL132K 32 Mbit (4 MB) S25FL164K 64 Mbit (8 MB) This application note provides conversion guidelines for migrating from the Microchip SST25VF-B, SST25VF-C and SST26VF SPI series to the Cypress S25FL1-K SPI Flash Family. This application note is based on information available to date from data sheets and other application notes publicly available from Cypress and Microchip. Please refer also to the latest relevant specifications. The document discusses the specification differences when migrating from SST25VF-B, SST25VF-C and SST26VF to S25FL1-K. 2 Feature Comparison Microchip SST25VF-B, SST25VF-C, and SST26VF are well suited for migration to Cypress S25FL1-K products. Some of the reasons are compatible pinouts, packages, command set, and 4-kB sector structure. Both Cypress S25FL1-K and Microchip devices support Single (Standard) I/O mode. Cypress S25FL1-K also supports Dual I/O and Quad I/O modes, while Microchip has Dual I/O mode on the SST25VF-C family and Quad mode on the SST26VF family. The main differences between Cypress S25FL1-K and Microchip SST25VF-B family are: Data program scheme (See Program Method on page 4.) Status register structure (See Status Registers on page 4.) Block protection scheme (See Block Protection Scheme on page 6.) The main differences between Cypress S25FL1-K and Microchip SST25VF-C family are: www.cypress.com Document No. 001-98581 Rev. *A 1 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Data program scheme (See Program Method on page 4.) Status register structure (See Status Registers on page 4.) Block protection scheme (See Block Protection Scheme on page 6.) OTP handle methods (See OTP (One-Time Program) Area on page 8.) Hardware reset (See Reset Operations on page 8.) The main differences between Cypress S25FL1-K and Microchip SST26VF family are: Block structure (See Block Structure on page 3.) Status register structure (See Status Registers on page 4.) Block protection scheme (See Block Protection Scheme on page 6.) OTP handle methods (See OTP (One-Time Program) Area on page 8.) Software reset (See Reset Operations on page 8.) Table 1 summarizes the feature similarities and differences between S25FL-1K and SST25VF-B, SST25VF-C, SST26VF. Table 1. High Level Feature Support Comparison Feature / Parameter Single (Standard) IO Operations S25FL-1K SST25VF-B SST25VF-C SST26VF Dual IO Operations x x Quad IO Operations x x Standard Normal Read SCK Frequency (max) 50 MHz 25 MHz 33 MHz 33 MHz Standard Fast Read SCK Frequency (max) 108 MHz 80 MHz 80 MHz 80 MHz Dual Fast Read SCK Frequency (max) 108 MHz x 75 MHz (Dual-Output) 50 MHz (Dual I/O) x Quad Fast Read SCK Frequency (max) 108 MHz x x 80 MHz Wrapped Read Modes x x x x x Program Page Size 256 bytes 1 byte 256 bytes 256 bytes AAI (Auto Address Increment)-WordProgram x ? x x Program/Erase Suspend x x x Dual-Input PageProgram x x x 4 kB, 64 kB, and Chip Erase 32-kB Block Erase x Write Protection Index Jump Read Read Protection x x x Volatile Configuration x Hardware Reset x x x Software Reset x x x One Time Programmable Region(s) 3 x 256 bytes x 32 bytes 32 bytes -40°C to +85°C -40°C to +105°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +8°5°C -40°C to +85°C Temperature Range Option www.cypress.com Document No. 001-98581 Rev. *A 2 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family 2.1 Hardware Package The pinout of the SST25VF-B and SST26VF families is identical. For the SST25VF-C family, HOLD# can be used as RESET# when CS# is high. The S25FL1-K can have its HOLD# pin connected to a system RESET function without causing it any problems. This allows direct replacement of the SST25VF064C without PCB redesign. Figure 1 shows those SOIC packages and pinouts. Please refer to the data sheets for detailed package information. Figure 1. SOIC 150/208/300 mil Package and Pinout (16-pin and 8-pin Versions) HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC CS# 7 10 GND SO/IO1 8 9 W#/ACC/IO2 CS# 1 8 VCC SO/IO1 2 7 HOLD#/IO3 WP#/IO2 3 6 SCK GND 4 5 SI/IO0 Note: 1. On SST25VF-C, RST#/HOLD# replaces HOLD#. Table 2 and Table 3 summarize the available packages from Cypress and Microchip. Table 2. Cypress S25FL1-K Available Packages Cypress S25FL1-K S25FL116K S25FL132K S25FL164K SOIC8 150 mil x SOIC8 208 mil SOIC16 300 mil x x USON 5x6 24-Ball BGA 6 x 8 5 x5 ball and 6 x 4 ball Table 3. Microchip Available Packages SST25VF-B SOIC8 200 mil 2.2 SST25VF-C SST26VF 25VF016B 25VF032B 25VF064C 25VF016 25VF032 SOIC16 300 mil x x x x WSON 6 x 5 x WSON 6 x 8 x x x x Block Structure Both Microchip products (SST25VF-B, SST25VF-C, and SST26VF) and Cypress S25FL1-K support 4-kB sector erase. The SST25VF-B and SST25VF-C support both 32-kB block erase and 64-kB block erase, while Cypress S25FL1K supports 64-kB block erase only. www.cypress.com Document No. 001-98581 Rev. *A 3 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Figure 2 shows block structure of SST26VF. Block erase command needs to be sent according to the structure. Software change is needed when migrating from SST26VF to S25FL1-K if block erase command (D8H) is used. Figure 2. Block Structure of SST26VF Top of Memory Block 8 kbyte 8 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 2 Sectors for 8-kbyte blocks 8 Sectors for 32-kbyte blocks 16 Sectors for 64-kbyte blocks 4 kbyte 4 kbyte 64 kbyte 4 kbyte 4 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 8 kbyte 8 kbyte Bottom of Memory Block 2.3 Program Method Both Microchip products (SST25VF-C and SST26VF) and Cypress S25FL1-K supports page program with program length from 1 to 256 bytes. SST25VF-C supports Dual-Input Page-Program, while S25FL1-K does not. The page program command (02H) in the SST25VF-B can only program 1 byte to flash. AAI (Auto Address Increment)-Word-Program is used to program multiple bytes to flash. When migrating to S25FL1-K, AAI-Word-Program function needs to be removed and the page program command used instead. 2.4 Multi-I/O Operation The SST25VF-C supports Dual output read and Dual I/O read, which is also supported by S25FL1-K. The SST26VF supports Quad I/O bus operation and when enabled, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or a “Reset Quad I/O instruction” is executed. S25FL1-K supports Quad output read and Quad I/O read operations but does not support Quad I/O bus operation. Changes to the software will be required when migrating to S25FL1-K if Quad I/O bus operation is used. 2.5 Status Registers The SST25VF-B, SST25VF-C, and SST26VF have only one status register (SR1). Cypress FL1-K devices have two additional status registers (SR2 and SR3), which can be used to provide status on additional device features and to configure the burst wrap feature. The Write Status Register instruction allows www.cypress.com Document No. 001-98581 Rev. *A 4 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family the three status registers to be written in one command sequence. Only non-volatile status register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 through 2 of Status Register 1), CMP, LB3, LB2, LB1, LB0, QE, SRP1 (bits 6 through 0 of Status Register 2) and W6, W5, W4, and LC (bits 6 through 0 of Status Register 3) can be written. All other status register bit locations are read-only and will not be affected by the Write Status Register instruction. Table 4 illustrates the status register bit assignments for Microchip products and S25FL1-K. Table 4. Status Register Bit Assignments for Microchip Products and S25FL1-K Cypress Bits S25FL1-K SST25VF-B SST25VF-C SST26VF Name Function Name Function Name Function Name Function SRP0 Status Register Protect0 BPL BP Lock Bit BPL BP Lock Bit BUSY Embedded Operation Status SR1[6] SEC Sector/ Block Protect AAI Auto Address Increment Programmi ng status SEC Security ID (OTP) status RES Reserved SR1[5] TB Top/Bottom Protect BP3 BP3 SEC Security ID (OTP) status SR1[4] BP2 BP2 BP2 WPLD Write Protection Lock-Down status SR1[7] Block Protect Bits Block Protect Bits Block Protect Bits BP1 BP1 WSP Write SuspendProgram status BP0 BP0 WSE Write SuspendErase status Write Enable Latch WEL Write Enable Latch BUSY Embedded Operation Status RES Reserved x x x x x x x x x x SR1[3] BP1 SR1[2] BP0 SR1[1] WEL Write Enable Latch WEL Write Enable Latch WEL SR1[0] BUSY Embedded Operation Status BUSY Embedded Operation Status SR2[7] RFU Reserved x SR2[6] CMP Compleme nt Protect x SR2[5] LB3 x x x x x x SR2[4] LB2 x x x x x x SR2[3] LB1 Security Register Lock Bits x x x x x x SR2[2] LB0 x x x x x x SR2[1] QE Quad Enable x x x x x x SR2[0] SRP1 Status Register Protect1 x x x x x x SR3[7] RFU Reserved x x x x x x SR3[6] W6 x x x x x SR3[5] W5 Burst Wrap Length x x x x x x x x x x x x x SR3[4] W4 Burst Wrap Enable Latency Control (LC) Variable Read Latency Control SR3[3] SR3[2] SR3[1] SR3[0] www.cypress.com Microchip x x x x x x x x x x x x x x x x x x x x x x x x Document No. 001-98581 Rev. *A 5 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family 2.6 Block Protection Scheme The SST25VF-B and SST25VF-C protect sector data based on Block Protect Bits (BP3-0). The BP Bits are nonvolatile read/write bits in the status register (SR[5-2]) that provide Write Protection control and status. Table 5 shows sector protection area of SST25VF-B and SST25VF-C. Please refer also to the status register handling. Table 5. Sector Protection Area of SST25VF-B and SST25VF-C SST25VF-B BP Status VF016B BP BP BP BP 3 2 1 0 0 0 0 0 Protected Portion SST25VF-C VF032B Protected Addresses Protected Portion None None VF064C Protected Addresses Protected Portion Protected Addresses None None None None Upper 1/64 3F0000H3FFFFFH Upper 1/128 7F0000H7FFFFFH 0 0 0 1 Upper 1/32 1F0000H1FFFFFH 0 0 1 0 Upper 1/16 1E0000H1FFFFFH Upper 1/32 3E0000H3FFFFFH Upper 1/64 7E0000H7FFFFFH 0 0 1 1 Upper 1/8 1C0000H1FFFFFH Upper 1/16 3C0000H3FFFFFH Upper 1/32 7C0000H7FFFFFH 0 1 0 0 Upper 1/4 180000H1FFFFFH Upper 1/8 380000H3FFFFFH Upper 1/16 780000H7FFFFFH 0 1 0 1 Upper 1/2 100000H1FFFFFH Upper 1/4 300000H3FFFFFH Upper 1/8 700000H7FFFFFH 0 1 1 0 All Blocks 000000H1FFFFFH Upper 1/2 200000H3FFFFFH Upper 1/4 600000H7FFFFFH 0 1 1 1 All Blocks 000000H1FFFFFH All Blocks 000000H3FFFFFH Upper 1/2 400000H7FFFFFH 1 0 0 0 None None None None All Blocks 000000H7FFFFFH 1 0 0 1 Upper 1/32 1F0000H1FFFFFH Upper 1/64 3F0000H3FFFFFH All Blocks 000000H7FFFFFH 1 0 1 0 Upper 1/16 1E0000H1FFFFFH Upper 1/32 3E0000H3FFFFFH All Blocks 000000H7FFFFFH 1 0 1 1 Upper 1/8 1C0000H1FFFFFH Upper 1/16 3C0000H3FFFFFH All Blocks 000000H7FFFFFH 1 1 0 0 Upper 1/4 180000H1FFFFFH Upper 1/8 380000H3FFFFFH All Blocks 000000H7FFFFFH 1 1 0 1 Upper 1/2 100000H1FFFFFH Upper 1/4 300000H3FFFFFH All Blocks 000000H7FFFFFH 1 1 1 0 All Blocks 000000H1FFFFFH Upper 1/2 200000H3FFFFFH All Blocks 000000H7FFFFFH 1 1 1 1 All Blocks 000000H1FFFFFH All Blocks 000000H3FFFFFH All Blocks 000000H7FFFFFH The SST26VF has a Block-Protection register that provides a software mechanism to write-lock the array and write-lock, and/or read-lock, the parameter blocks. The Block-Protection Register is 48-bits wide on the SST26VF016 and 80-bits wide on the SST26VF032: two bits each for the eight 8-kB parameter blocks (write-lock and read-lock), and one bit each for the remaining 32-kB and 64-kB overlay blocks (write-lock). The Cypress S25FL1-K allows all, none, or a portion of the memory array be protected from Program and Erase instructions via the status register. It is similar to the sector protection scheme used by SST25VF-B and SST25VF-C but more flexible. The Block Protect Bits (BP2-0) provide Write Protection control and status. The factory default setting for the block protection bits is 0 (none of the array is protected.). The non-volatile Top/Bottom bit (TB) controls whether the Block Protect Bits (BP2-0) protect from the Top (TB=0) or the Bottom (TB=1) of the array. The non-volatile Sector/ Block Protect bit (SEC) selects whether the Block Protect Bits (BP2-0) protect 4-kB sectors (SEC=1) or 64-kB blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array. www.cypress.com Document No. 001-98581 Rev. *A 6 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register. It is used in conjunction with SEC, TB, and BP2-0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1, and BP0 will be reversed. Refer to the Cypress data sheet for the valid combinations. Table 6 and Table 7 show S25FL1-K's sector protection using S25FL116K as an example. Table 6. FL116K Block Protection (CMP = 0) Status Register Protected Portion Protected Addresses 0 None None 0 1 Upper 1/32 1F0000h - 1FFFFFH 1 0 Upper 1/16 1E0000h - 1FFFFFH 1 Upper 1/8 1C0000h - 1FFFFFH 0 Upper 1/4 180000h - 1FFFFFH 1 Upper 1/2 100000h - 1FFFFFH 1 Lower 1/32 000000h - 00FFFFH 1 0 Lower 1/16 000000h - 01FFFFH 1 1 Lower 1/8 000000h - 03FFFFH SEC TB BP2 BP1 BP0 x x 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 Lower 1/4 000000h - 07FFFFH 0 1 1 0 1 Lower 1/2 000000h - 0FFFFFH x x 1 1 x All 000000h - 1FFFFFH 1 0 0 0 1 Upper 1/512 1FF000h - 1FFFFFH 1 0 0 1 0 Upper 1/256 1FE000h - 1FFFFFH 1 0 0 1 1 Upper 1/128 1FC000h - 1FFFFFH 1 0 1 0 x Upper 1/64 1F8000h - 1FFFFFH 1 1 0 0 1 Lower 1/512 000000h - 000FFFH 1 1 0 1 0 Lower 1/256 000000h - 001FFFH 1 1 0 1 1 Lower 1/128 000000h - 003FFFH 1 1 1 0 x Lower 1/64 000000h - 007FFFH Table 7. FL116K Block Protection (CMP = 1) Status Register www.cypress.com Protected Portion Protected Addresses All 000000h - 1FFFFFH SEC TB BP2 BP1 BP0 x x 0 0 0 0 0 0 0 1 Lower 31/32 000000h - 1EFFFFH 0 0 0 1 0 Lower 15/16 000000h - 1DFFFFH 0 0 0 1 1 Lower 7/8 000000h - 1BFFFFH 0 0 1 0 0 Lower 3/4 000000h - 17FFFFH 0 0 1 0 1 Lower 1/2 000000h - 0FFFFFH 0 1 0 0 1 Upper 31/32 010000h - 1FFFFFH 0 1 0 1 0 Upper 15/16 020000h - 1FFFFFH 0 1 0 1 1 Upper 7/8 040000h - 1FFFFFH 0 1 1 0 0 Upper 3/4 080000h - 1FFFFFH 0 1 1 0 1 Lower 1/2 100000h - 1FFFFFH x x 1 1 x None None 1 0 0 0 1 Lower 511/512 000000h - 1FEFFFH 1 0 0 1 0 Lower 255/156 000000h - 1FDFFFH 1 0 0 1 1 Lower 127/128 000000h - 1FBFFFH Document No. 001-98581 Rev. *A 7 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Table 7. FL116K Block Protection (CMP = 1) Status Register 2.7 BP0 Protected Portion Protected Addresses SEC TB BP2 BP1 1 0 1 0 x Lower 63/64 000000h - 1F7FFFH 1 1 0 0 1 Upper 511/512 001000h - 1FFFFFH 1 1 0 1 0 Upper 255/256 002000h - 1FFFFFH 1 1 0 1 1 Upper 127/128 004000h - 1FFFFFH 1 1 1 0 x Upper 63/64 008000h - 1FFFFFH Variable Latency The Cypress S25FL1-K adds support for variable latency read timing. Customers can use the default latency code value when migrating from Microchip products to S25FL1-K without any change in read timing. Or, they can set latency code (SR3[3-0]) and change read timing to enable faster initial access time or higher clock rate read commands. See full feature details in S25FL1-K data sheet. 2.8 Burst Read Mode The Microchip SST26VF supports 8/16/32/64-byte linear burst with wrap-around. Set Burst command cycle (C0H) is used to set burst length. Read Burst command cycle (0CH) is used to execute a Read Burst operation. The Cypress S25FL1-K supports Fast Quad IO Read (EBH) in Burst with Wrap mode. Status Register 3 provides a bit (SR3[4]) to enable a read with wrap option for the Quad I/O Read command. To set burst length, Status Register 3 provides bits (SR3[6:5]) to select the alignment boundary. Burst wrap length can be aligned on 8-, 16-, 32-, or 64-byte boundaries. The S25FL1-K also supports Set Burst with Wrap command (77H) preceding the Fast Quad IO Read command. See full feature details in S25FL1-K data sheet. 2.9 OTP (One-Time Program) Area The Microchip SST25VF-C and SST26VF supports 32 bytes' OTP area. Eight bytes are unique, factory pre-programmed identifier and 24 bytes are user-programmable. Read SID (88H) is used to read OTP area. Program SID (A5H) is used to program OTP area. Lockout SID (85H) is used to lockout OTP area programming. The Cypress S25FL1-K provides three 256 bytes' Security Registers. Each security register can be read (opcode 48H), programmed (opcode 42H), erased (opcode 44H), and permanently locked by setting status register bits LB1, LB2 and LB3 to 1. 2.10 Reset Operations The Microchip SST25VF-C has a RST# pin that provides a hardware method for resetting the device. The Microchip SST26VF supports a software reset operation. It is used to put the device in normal operating ready mode. This operation consists of two commands: Reset-Enable (RSTEN 66H) and Reset (RST 99H). The Cypress S25FL1-K does not have a hardware Reset pin. If the host system memory controller resets, without a complete power down and power up sequence, while S25FL1-K is set to Continuous Mode Read, S25FL1-K will not recognize any initial standard SPI commands from the controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset (FFFFh) command as the first command after a system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard SPI commands to be recognized. If Burst Wrap Mode is used, it is also recommended to issue a Set Burst with Wrap (77h) command that sets the W4 bit to one as the second command after a system Reset. Doing so will release the device from the Burst Wrap Mode and allow standard sequential read SPI command operation. Issuing these commands immediately after a non-power-cycle (warm) system reset ensures the device operation is consistent with the power on default device operation. www.cypress.com Document No. 001-98581 Rev. *A 8 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family 3 Command Set Comparison Microchip devices and S25FL1-K share similar instructions (op-codes) in their command set, which determine a compatible set of internal algorithms. Nevertheless, not all commands are supported when comparing one product family with the other. Table 8 shows a comparison summary of the command set of a Cypress S25FL1-K device and Microchip SST25VF-B, SST25VF-C, and SST26VF. Table 8. Command Set of S25FL1-K and Microchip Devices (Sheet 1 of 2) Command Description S25FL1-K SST25VF-B SST25VF-C SST26VF Configuration, Status, Erase, Program Commands Read Status Register 1 05H 05H 05H 05H Read Status Register 2 35H x x x Read Status Register 3 33H x x x Write Enable 06H 06H 06H 06H Write Enable for Volatile Status Register 50H 50H 50H x Write Disable 04H 04H 04H 04H Write Status Registers 01H 01H 01H x Set Burst with Wrap 77H x x x Page Program 02H 02H (1) 02H 02H x ADH x x Auto Address Increment Programming Dual Input Program x x A2H x Sector Erase (4 kB) 20H 20H 20H 20H Block Erase (32 kB) x 52H 52H x Block Erase (64 kB) D8H D8H D8H x Block Erase x x x D8H (2) Chip Erase C7H/60H C7H/60H C7H/60H C7H Suspends Program/Erase x x x B0H Resumes Program/Erase x x x 30H 03H 03H 03H 03H Fast Read 0BH 0BH 0BH 0BH Fast Read Dual Output 3BH x 3BH x Fast Read Quad Output 6BH x x x Fast Read Dual I/O BBH x BBH x Fast Read Quad I/O EBH x x x Continuous Read Mode Reset FFH x x x Read Commands Read Data Set Burst Length x x x C0H nB Burst with Wrap x x x 0CH Jump to address within 256 Byte page indexed by n x x x 08H Jump to address within block indexed by n x x x 09H Jump to block indexed by n x x x 10H ID, Security, and Other Commands Deep Power-down B9H x x x Release Power down / Device ID ABH x x x Manufacturer/ Device ID 90H 90H/ABH 90H/ABH x JEDEC ID Read 9FH 9FH 9FH 9FH Quad I/O JEDEC ID Read Read SFDP Register www.cypress.com x x x AFH 5AH x x x Document No. 001-98581 Rev. *A 9 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Table 8. Command Set of S25FL1-K and Microchip Devices (Sheet 2 of 2) S25FL1-K SST25VF-B SST25VF-C SST26VF Read Security Registers Command Description 48H x x x Erase Security Registers 44H x x x Program Security Registers 42H x x x Enable SO to output RY/BY# status during AAI programming x 70H x x Disable SO to output RY/BY# status during AAI programming x 80H x x Enable HOLD# ping functionality of the RST#/HOLD# pin x x AAH x Read Security ID x x 88H 88H Program User Security ID area x x A5H A5H Lockout Security ID Programming x x 85H 85H No Operation x x x 00H Reset Enable x x x 66H Reset Memory x x x 99H Enable Quad I/O x x x 38H Reset Quad I/O x x x FFH Read Block Protection Register x x x 72H Write Block Protection Register x x x 42H Lock Down Block Protection Register x x x 8DH Notes: 1. 02H command sequence of SST25VF-B can program 1 byte only every time. 2. Block size being erased of SST26VF is based on its block structure. www.cypress.com Document No. 001-98581 Rev. *A 10 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family 4 4.1 Timing Considerations Power-Up Timing One of the most sensitive electrical specifications is the power-up timing needed to correctly initialize the device. Table 9 and Figure 3 show the power-up characteristics of the S25FL1-K family. Table 9. S25FL1-K Power-Up Timing Requirement Parameter Spec Symbol Min Unit Max VCC (min) to CS# Low tVSL 10 Time Delay Before Write Command tPUW 1 10 ms µs Write Inhibit Threshold Voltage VWI 1.0 2.0 V Figure 3. Power-Up Timing and Voltage Levels VCC VCC (max) Program, Erase, and Write instructions are ignored CS# must track VCC VCC (min) t VSL Reset State Read instructions allowed Device is fully accessible VWI t PUW Time On the Microchip side, VCC ramp rate is more restrictive. All functionalities and DC specifications are specified for a VCC ramp rate of greater than 1V per 100 ms (0v - 3.0V in less than 300 ms for SST25VF-B/SST25VF-C, and 0V to 2.7V in less than 270 ms for SST26VF). Table 10 shows the power-up characteristics of the Microchip products. Table 10. SST25VF-B, SST25VF-C, and SST26VF Power-Up Timing Requirement Parameter Symbol Min Unit VCC Min to Read Operation TPU-READ 100 µs VCC Min to Write Operation TPU-WRITE 100 µs www.cypress.com Document No. 001-98581 Rev. *A 11 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family 4.2 Data In Setup/Hold Time Two AC timing parameters that are critical in SPI designs are Data In Setup Time and Data In Hold Time. They specify how long data needs to be valid before and after the rising edge of the clock signal, respectively. The minor different requirement should not be an issue in the design but may just need to be verified. Table 11 shows the Data in Setup/Hold timing characteristics for both S25FL1-K and Microchip devices. Table 11. Data in Setup/Hold Timing Characteristics Comparison S25FL1-K Parameter Min Unit Data In Setup Time 2 ns Data In Hold Time 5 ns SST25VF016B SCK Frequency Limits 25 MHz Parameter 50 MHz 80 MHz Min Unit Data In Setup Time 5 2 2 ns Data In Hold Time 5 5 4 ns SST25VF032B SCK Frequency Limits 25 MHz Parameter 66 MHz 80 MHz Min Unit Data In Setup Time 5 2 2 ns Data In Hold Time 5 4 4 ns SST25VF-C SCK Frequency Limits 33 MHz Parameter 50 MHz 75/80 MHz Min Unit Data In Setup Time 3 3 2 ns Data In Hold Time 5 5 4 ns SST26VF SCK Frequency Limits 33 MHz Parameter 4.3 80 MHz Min Unit Data In Setup Time 3 3 ns Data In Hold Time 4 4 ns Further Timing Comparison In general, the timing characteristics of both Microchip and Cypress flash families are almost identical, with just a little deviation. One difference is that the S25FL1-K family has a faster CS# deselect time than SST25VF-B and SST25VF-C. There is no need to do any changes but it is important to note that read performance of the application can be increased easily here. When SPI clock frequency is 80 MHz, CS# deselect time for read after writes of SST26VF is 12.5 ns minimum. The minor different requirement should not be an issue in the design but may just need to be verified when migrating from SST26VF to S25FL-1K. Table 12 shows a comparison between S25FL1-K and Microchip devices with regards to the various CS# deselect times. www.cypress.com Document No. 001-98581 Rev. *A 12 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Table 12. CS# Deselect Timing Characteristics Comparison S25FL1-K Parameter CS# deselect time between Reads CS# deselect time for Read after Writes Min Unit 7 ns 40 ns SST25VF016B SCK Frequency Limits 25M Hz Parameter 50 MHz 80 MHz Min CS# deselect time 100 Unit 50 50 ns SST25VF032B SCK Frequency Limits 25MHz Parameter 66MHz 80MHz Min CS# deselect time 100 Unit 50 50 ns SST25VF-C SCK Frequency Limits 33 MHz Parameter 50 MHz 75/80 MHz Min CS# deselect time 50 Unit 50 50 ns SST26VF SCK Frequency Limits 33 MHz Parameter CS# deselect time 5 80 MHz Min 100 12.5 Unit ns Conclusion Migrating from Microchip SST25VF-B, SST25VF-C, and SST26VF families to the Cypress S25FL1-K is straightforward and requires minimal accommodation in regards to either system software or hardware. Additionally, once accommodations are made, if required, S25FL1-K flash will enable access to a wider range of SPI flash features and superior read throughput up to 54 Mbytes/s using Quad bit data path. www.cypress.com Document No. 001-98581 Rev. *A 13 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Document History Page Document Title: AN98581 - Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Document Number: 001-98581 Rev. ECN No. Orig. of Change 4929335 MSWI ** *A www.cypress.com Submission Date Description of Change 04/26/2013 Initial version 09/22/2015 Updated in Cypress template Document No. 001-98581 Rev. *A 14 Migration from Microchip SST25VF-B, SST25VF-C, and SST26VF to Cypress S25FL1-K SPI Flash Family Worldwide Sales and Design Support Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. # 999 Products PSoC® Solutions Automotive..................................cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers ................................ cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface......................................... cypress.com/go/interface Cypress Developer Community Lighting & Power Control ............cypress.com/go/powerpsoc Memory........................................... cypress.com/go/memory PSoC ....................................................cypress.com/go/psoc Touch Sensing .................................... cypress.com/go/touch Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support USB Controllers ....................................cypress.com/go/USB Wireless/RF .................................... cypress.com/go/wireless MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: Fax: Website: 408-943-2600 408-943-4730 www.cypress.com © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-98581 Rev. *A 15