Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74HC4060
CMOS IC
14-STAGE ASYNCHRONOUS
BINARY COUNTERS AND
OSCILLATORS

SOP-16
DESCRIPTION
The U74HC4060 are high-speed Si-gate CMOS device.
The U74HC4060 devices consist of an oscillator section and
14 ripple-carry binary counter stages. The oscillator configuration
allows design of erther RC or crystal oscillator circuits with three
oscillator terminals (CLKI, CLKO, CLKO) , ten buffered outputs
(QD to QJ and QL to QM) and an overriding asynchronous master
reset (CLR) . The oscillator may be replaced by an esternal clock
signal at input CLKI. In this case keep the other oscillator pins
(CLKO, CLKO) floating. The counter advances on the
negative-going transition of CLKI. A high level at the clear (CLR)
input disables the oscillator and resets the counter to zero (all Q
output low).

TSSOP-16
FEATURES
* Operate from 2.0V to 6.0V
* Low Input Current:1.0uA
* Outputs Can Drive Up To 10 LSTTL Loads
* Low Power Consumption ,80uA Max ICC
* 4mA Output Drive at 5V
* Typical tPD=14ns
* Allow Design of Either RC or Crystal Oscillator Circuits

ORDERING INFORMATION
Ordering Number
U74HC4060G-S16-R
U74HC4060G-P16-R

Package
SOP-16
TSSOP-16
Packing
Tape Reel
Tape Reel
MARKING
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Copyright © 2015 Unisonic Technologies Co., Ltd
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U74HC4060
PIN CONFIGURATION
QL
1
16
VCC
QM
2
15
QJ
QN
3
14
QH
QF
4
13 QI
QE
5
12 CLR
QG
6
11 CLKI
QD
7
10 CLKO
8

CMOS IC
9 CLKO
GND

FUNCTION TABLE
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
Note: H: HIGH voltage level
L: LOW voltage level
X: Don’t care.High impedance OFF-state
↑: Low-to-High CP transition
↓: High-to-Low CP transition

LOGIC SYMBOL
10
CLKO
11
12
CLKI
CLR
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9
CLKO
QD
QE
QF
QG
QH
QI
QJ
QL
QM
QN
7
5
4
6
14
13
15
1
2
3
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U74HC4060
CMOS IC
LOGIC DIAGRAM

CLKO
CLKO
DFFA
CLKI
DFFD
CP
CP
CLR
Q
DFFM
DFFL
CP
Q
CLR
DFFG
CP
CP
CLR
Q
Q
CLR
DFFN
CP
CLR
Q
CLR
Q
TIMING DIAGRAM

1
2
4
8
16
32
64
128
256
512
1024 2048 4096 8192 16384
CLKI
CLR
QD
QE
QF
QG
QH
QI
QJ
QL
QM
QN
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U74HC4060

CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
-0.5 ~ 7.0
V
Input Clamp Current (VI<0 or VI>VCC)
IIK
±20
mA
Output Clamp Current (VO<0 or VO>VCC)
IOK
±20
mA
VCC or GND Current
ICC
±50
mA
Continuous Output Current(VO=0 to VCC)
IOUT
±25
mA
Storage Temperature
TSTG
-65 ~ + 150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise or Fall Times

ELECTRICAL
SYMBOL
VCC
VIN
VOUT
TA
tR, tF
TEST CONDITIONS
Operating
MIN
2.0
0
0
-40
VCC=2.0V
VCC=4.5V
VCC=6.0V
TYP MAX UNIT
6.0
V
VCC
V
VCC
V
+85
°C
1000
ns
500
400
CHARACTERISTICS (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
High-Level Input Voltage
VIH
Low-Lever Input Voltage
VIL
High-Level Output Voltage
VOH
Low-Level Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
II(LEAK)
Icc
TEST CONDITIONS
VCC=2V
VCC=4.5V
VCC=6V
VCC=2V
VCC=4.5V
VCC=6V
VCC=2V, IOH=-20μA
VCC=4.5V, IOH=-20μA
VCC=6V, IOH=-20μA
VCC=4.5V, IOH=-4.0mA
VCC=6V, IOH=-5.2mA
VCC=2V, IOL=20μA
VCC=4.5V, IOL=20μA
VCC=6V, IOL=20μA
VCC=4.5V, IOH=4mA
VCC=6V, IOL=5.2mA
VCC=6V, VIN= VCC or GND
VCC=6V, VIN=VCC or GND, IOUT=0
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MIN TYP MAX UNIT
1.5
V
3.15
V
4.2
V
0.5
V
1.35
V
1.8
V
1.9 1.998
V
4.4 4.499
V
5.9 5.999
V
3.98 4.3
V
5.48 5.8
V
0.002 0.1
V
0.001 0.1
V
0.001 0.1
V
0.17 0.26
V
0.15 0.26
V
±100 nA
8
μA
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U74HC4060

CMOS IC
TIMING REQUIREMENTS
(over recommended operating free-air temperature range, unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC=2V
FCOLCK Clock Frequency
VCC=4.5V
VCC=6V
VCC=2V
CLKI high or low VCC=4.5V
VCC=6V
tW Pulse Duration
VCC=2v
CLR high
VCC=4.5V
VCC=6V
VCC=2V
tsu, Setup time, CLR Inactive Before CLKI High To Low VCC=4.5V
VCC=6V

115
23
20
115
23
20
200
40
34
TYP MAX UNIT
4.3
22 MHz
25
ns
ns
SWITCHING CHARACTERISTICS
(over recommended operating free-air temperature range, CL=50pF, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
VCC=2V
Propagation delay from CLKI to QD
tPD
VCC=4.5V
VCC=6V
VCC=2V
Propagation delay from CLKI to Any Q
tPHL
VCC=4.5V
VCC=6V
VCC=2V
Output rise or fall time
tt
VCC=4.5V
VCC=6V
VCC=2V
Maxinum Clock Pulse Frequency
fmax
VCC=4.5V
VCC=6V

MIN
MIN TYP MAX UNIT
240 490
ns
58
98
42
83
66
140
ns
18
28
24
24
28
75
ns
8
15
6
13
5.5
10
MHz
28
45
33
53
OPERATING CHARACTERISTICS
PARAMETER
Power Dissipation Capacitance
SYMBOL
CPD
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TEST CONDITIONS
No load
MIN
TYP MAX UNIT
88
pF
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U74HC4060

CMOS IC
TEST CIRCUIT AND WAVEFORMS
High-Level Pulse
Vcc
50%
50%
0V
tw
Low-Level Pulse
Vcc
50%
50%
0V
Vcc
Input
50%
50%
0V
tpHL
tpLH
Output
90%
50%
10%
tr
Output
Vcc
90%
50%
10%
tf
tpHL
tpLH
90%
50%
10%
tf
90%
50%
10%
tr
0V
Vcc
0V
Note: A. CL =50pF ,CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics : PRR ≤1MHz, Zo = 50Ω,
tr ≤6ns, tf ≤6ns.
C. For clock inputs ,fmax is measured when the input duty cycle is 50%.
D. tpLH and tpHL are the same as tpd.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
m alfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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