Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74LVC74A
CMOS IC
DUAL POSITIVE-EDGETRIGGERED D-TYPE
FLIP-FLOPS WITH CLEAR
AND PRESET

DESCRIPTION
The U74LVC74A is a dual positive-edge-triggered D-type
flip-flop.
The preset ( PRE ) and clear ( CLR ) input can set or reset the
output, egardless of the levels f others inputs. When the PRE and
CLR are inactive(high),data at the data input meeting the set-up
time requirements is transferred to the outputs on the positive-going
edge of the clock pulse. Following the hold-time interval, data D can
be changed without affecting the levels at the outputs.

FEATURES
* 1.65V to 3.6V VCC Operation
* Inputs Accept Voltages to 5.5V
* Max tpd at 5.2ns of 3.3V
* Typical VOLP<0.8V at VCC=3.3V, TA=25°C
* Typical VOHV>2V at VCC=3.3V, TA=25°C

ORDERING INFORMATION
Ordering Number
U74LVC74AG-S14-R
U74LVC74AG-P14-R

Package
SOP-14
TSSOP-14
Packing
Tape Reel
Tape Reel
MARKING
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Copyright © 2013 Unisonic Technologies Co., Ltd
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U74LVC74A
CMOS IC

PIN CONFIGURATION

FUNCTION TABLE (each gate)
INPUT
OUTPUT
PRE
CLR
CLK
D
Q
Q
L
H
H
L
X
X
X
X
H
L
L
H
L
L
X
X
H
H
H
H
H
↑
↑
H
L
H
L
H
L
H
H
H
L
X
Q0
Q0
+: This configuration is unstable, as it is not persist when either PRE or CLR return to high level.

LOGIC DIAGRAM (positive logic)
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U74LVC74A

CMOS IC
ABSOLUTE MAXIMUM RATING (unless otherwise specified)(Note 1)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
-0.5~6.5
V
Input Voltage
VIN
-0.5~ 6.5
V
Output Voltage(active mode)
VOUT
-0.5~VCC+0.5
V
Input Clamp Current(VIN<0)
IIK
-50(MAX)
mA
Output Clamp Current(VOUT<0)
IOK
-50(MAX)
mA
Output Current
IOUT
±50
mA
VCC or GND Current
ICC
±100
mA
Storage Temperature
TSTG
-65 ~ +150
°C
Notes: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

RECOMMENDED OPERATING COMDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
SYMBOL
VCC
VIN
VOUT
High-level input voltage
VIH
Low-level input voltage
VIL
High-level Output Current
IOH
Low-level Output Current
IOL
Input Transition Rise or Fall Rate
Operating Temperature
CONDITIONS
VCC =1.65V~1.95V
VCC=2.3V~2.7V
VCC =2.7V~3.6V
VCC =1.65V~1.95V
VCC=2.3V~2.7V
VCC =2.7V~3.6V
VCC =1.65V
VCC=2.3V
VCC =2.7V
VCC =3V
VCC =1.65V
VCC=2.3V
VCC =2.7V
VCC =3V
∆t/∆v
TA
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MIN
1.65
0
0
0.65×VCC
1.7
2
-40
TYP
MAX
3.6
5.5
VCC
UNIT
V
V
V
V
0.35×VCC
0.7
0.8
-4
-8
-12
-24
4
8
12
24
10
+85
V
mA
mA
ns/V
°C
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
CMOS IC
STATIC CHARACTERISTICS
PARAMETER
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
Quiescent Supply Current
SYMBOL
VOH
VOL
II(LEAK)
IQ
Additional Quiescent Supply
Current
∆IQ
Input Capacitance
CIN

TEST CONDITIONS
IOH=-100uA VCC=1.65V~3.6V
IOH=-4mA
VCC=1.65V
IOH=-8mA
VCC=2.3V
VCC=2.7V
IOH=-12mA
VCC=3V
IOH=-24mA
VCC=3V
VCC=1.65V~3.6V
IOL=100uA
IOL=4mA
VCC=1.65V
IOL=8mA
VCC=2.3V
IOL=12mA
VCC=2.7V
IOL=24mA
VCC=3V
VCC=0V~3.6V
VIN=5.5V or GND
VCC=3.6V
VIN=VCC or GND IOUT=0
VCC=2.7V to 3.6V
One input at VCC-0.6V,
Other inputs at VCC or GND
VCC=3.3V, VIN=VCC or GND
MIN
VCC-0.2
1.2
1.7
2.2
2.4
2.2
TYP
MAX
UNIT
V
0.2
0.45
0.7
0.4
0.55
V
±5
μA
10
μA
500
μA
5
pF
DYNAMIC CHARACTERISTICS (Input: tR, tF≤2.5ns; PRR≤1MHz)
PARAMETER
Fclock Clock frequency
SYMBOL
fCLOCK
Pulse duration
tW
Setup time before CLK↑
tsu
Hold time ,data after CLK↑
th
TEST CONDITIONS
VCC=1.8V±0.15V
VCC=2.5V±0.2V
VCC=2.7V
VCC=3.3V±0.3V
PRE or CLR Low
VCC=1.8V±0.15V
CLK High or Low
PRE or CLR Low
VCC=2.5V±0.2V
CLK High or Low
PRE or CLR Low
VCC=2.7V
CLK High or Low
PRE or CLR Low
VCC=3.3V±0.3V
CLK High or Low
Data
VCC=1.8V±0.15V
PRE or CLR Inactive
Data
VCC=2.5V±0.2V
PRE or CLR Inactive
Data
VCC=2.7V
PRE or CLR Inactive
Data
VCC=3.3V±0.3V
PRE or CLR Inactive
VCC=1.8V±0.15V
VCC=2.5V±0.2V
VCC=2.7V
VCC=3.3V±0.3V
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MIN
4.1
4.1
3.3
3.3
3.3
3.3
3.3
3.3
3.6
2.7
2.3
1.9
3.4
2.2
3
2
1
1
1
0
TYP
MAX
83
83
83
150
UNIT
MHZ
ns
ns
ns
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CMOS IC
DYNAMIC CHARACTERISTICS
See Fig. 1 and Fig. 2 for test circuit and waveforms.
PARAMETER
SYMBOL
TEST CONDITIONS
VCC=1.8V±0.15V
VCC=2.5V±0.2V
Maxinum Clock Pulse Frequency
fmax
VCC=2.7V
VCC=3.3V±0.3V
VCC=1.8V±0.15V, CL=30pF, RL=1KΩ
VCC=2.5V±0.2V, CL=30pF, RL=500Ω
Propagation delay from input
tPLH/tPHL
(CLK) to output(Q or Q)
VCC=2.7V, CL=50pF, RL=500Ω
VCC=3.3V±0.3V, CL=50pF, RL=500Ω
VCC=1.8V±0.15V, CL=30pF, RL=1KΩ
VCC=2.5V±0.2V, CL=30pF, RL=500Ω
Propagation delay from input
tPLH/tPHL
( PRE or CLR ) to output(Q or Q)
VCC=2.7V, CL=50pF, RL=500Ω
VCC=3.3V±0.3V, CL=50pF, RL=500Ω

MIN
83
83
83
150
1
1
1
1
1
1
1
1
TYP
MIN
24
24
26
TYP
MAX UNIT
MHz
7.1
4.4
6
5.2
6.9
4.6
6.4
5.4
ns
ns
OPERATING CHARACTERISTICS
PARAMETER
SYMBOL
Power Dissipation Capacitance
CPD
TEST CONDITIONS
VCC=1.8V, f=10MHz
VCC=2.5V, f=10MHz
VCC=3.3V, f=10MHz
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MAX UNIT
pF
pF
pF
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
CMOS IC
TEST CIRCUIT AND WAVEFORMS
Note: CL includes probe and jig capacitance.
Fig. 1 Load circuitry for switching times.
VCC
1.8V±0.15V
2.5V±0.2V
2.7V
3.3V±0.3V
Inputs
VIN
VCC
VCC
2.7V
2.7V
tR, tF
≤2ns
≤2ns
≤2.5ns
≤2.5ns
VM
CL
RL
VCC/2
VCC/2
1.5V
VCC/2
30pF
30pF
50pF
50pF
1KΩ
500Ω
500Ω
500Ω
Fig. 2 Propagation delay from input to output and input voltage waveforms.
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
CMOS IC
TEST CIRCUIT AND WAVEFORMS(Cont.)
Fig. 3 PROPAGATION DELAY TIMES
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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