UNISONIC TECHNOLOGIES CO., LTD U74LVC1G74 CMOS IC SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET DESCRIPTION SOP-8 This single positive-edge-triggered D-type flip-flop is designed for 1.65V to 5.5V VCC operation. A low level at the preset( PRE ) or clear ( CLR ) input sets or resets the outputs, regardless of the levels of the other inputs .when PRE and CLR are inactive(high),data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FEATURES * Supports 5-V VCC operation * Inputs accept voltages to 5.5V * Max tpd of 5.9ns at 3.3V * Typical VOLP<0.8V at VCC=3.3V, TA=25°C * Typical VOHV>2V at VCC=3.3V, TA=25°C * Low Power Consumption, ICC=10μA (Max.) * Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection ORDERING INFORMATION Ordering Number U74LVC1G74G-S08-R www.unisonic.com.tw Copyright © 2014 Unisonic Technologies Co., Ltd Package SOP-8 Packing Tape Reel 1 of 7 QW-R502-989.B U74LVC1G74 CMOS IC MARKING PIN CONFIGURATION FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK D Q Q L H H L X X X X H L L H L L X X H H H H ↑ ↑ H H L * H L H H L H* L H X Q0 Q0 * This configuration is unstable, it does not persist when PRE or CLR returns to high level. LOGIC DIAGRAM (positive logic) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 7 QW-R502-989.B U74LVC1G74 CMOS IC ABSOLUTE MAXIMUM RATING (unless otherwise specified) (Note 1) PARAMETER SYMBOL RATINGS UNIT Supply Voltage VCC -0.5~6.5 V Input Voltage VIN -0.5~ 6.5 V Voltage range applied to any output in the VOUT -0.5~ 6.5 V high-impedance or power-off state Voltage range applied to any output in the VOUT -0.5~VCC+0.5 V high or low state Input Clamp Current(VIN<0) IIK -50 mA Output Clamp Current(VOUT<0) IOK -50 mA Output Current IOUT ±50 mA VCC or GND Current ICC ±100 mA Storage Temperature TSTG -65 ~ +150 °C Notes: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage Output Voltage High-level input voltage SYMBOL VCC VIN VOUT VIH Low-level input voltage VIL High-level Output Current IOH CONDITIONS VCC =1.65V to 1.95V VCC=2.3V to 2.7V VCC =3V to 3.6V VCC =4.5V to 5.5V VCC =1.65V to 1.95V VCC=2.3V to 2.7V VCC =3V to 3.6V VCC =4.5V to 5.5V VCC =1.65V VCC=2.3V VCC =3V VCC =4.5V VCC =1.65V VCC=2.3V Low-level Output Current Input Transition Rise or Fall Rate IOL ∆t/∆v VCC =3V VCC =4.5V VCC =1.8V±0.15V, 2.5V±0.2V VCC =3.3V±0.3V, VCC =5V±0.5V, MIN 1.65 0 0 TYP MAX 5.5 5.5 VCC 0.65×VCC 1.7 2 0.7×VCC V 0.35×VCC 0.7 0.8 0.3×VCC -4 -8 -16 -24 -32 4 8 16 24 32 Operating Temperature TA -40 Note: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw UNIT V V V V mA mA 20 10 5 +85 ns/V °C 3 of 7 QW-R502-989.B U74LVC1G74 CMOS IC STATIC CHARACTERISTICS (All typical values are at VCC=3.3V, TA=25°C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS MIN VCC=1.65V to 5.5V, IOH=-100μA VCC-0.1 VCC=1.65V, IOH=-4mA 1.2 VCC=2.3V, IOH=-8mA 1.9 High-Level Output Voltage VOH 2.4 IOH=-16mA VCC=3V IOH=-24mA 2.3 VCC=4.5V, IOH=-32mA 3.8 VCC=1.65V to 5.5V, IOL=100uA VCC=1.65V, IOL=4mA VCC=2.3V, IOL=8mA Low-Level Output Voltage VOL IOL=16mA VCC=3V IOL=24mA VCC=4.5V, IOH=32mA Input Leakage Current II(LEAK) VCC =0V ~ 5.5V, VIN=5.5V or GND Power OFF Leakage Current Ioff VCC =0V, VIN or VOUT=5.5V VCC = 1.65V to 5.5V, Quiescent Supply Current IQ VIN= 5.5V or GND IOUT=0 VCC=3V to 5.5V, Additional Quiescent Supply ∆IQ One input at VCC-0.6V, Current Per Input Pin Other inputs at VCC or GND Input Capacitance CIN VCC =3.3V, VIN=VCC or GND TYP MAX UNIT V 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 μA μA 10 μA 500 μA 5 V pF TIMING REQUIREMENTS PARAMETER Clock frequency SYMBOL fclock TEST CONDITIONS VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V CLK VCC=1.8V PRE or CLR Low VCC=2.5V Pulse duration tw VCC=3.3V VCC=5.0V VCC=1.8V Setup time before CLK↑ from Data to PRE or CLR inactive VCC=2.5V tsu VCC=3.3V VCC=5.0V Hold time, data after CLK↑ th VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN TYP MAX 80 175 175 200 6.2 UNIT MHz MHz MHz MHz ns 6.2 ns CLK 2.7 ns PRE or CLR Low 2.7 ns CLK 2.7 ns PRE or CLR Low 2.7 ns CLK 2 2 2.9 ns ns ns PRE or CLR Low 1.9 PRE or CLR Low CLK 1.7 PRE or CLR Low 1.4 ns CLK 1.3 ns PRE or CLR Low 1.2 ns CLK 1.1 ns PRE or CLR Low 1.0 ns 0 0.3 1.2 0.5 ns ns ns ns 4 of 7 QW-R502-989.B U74LVC1G74 CMOS IC SWITCHING CHARACTERISTICS (See Fig. 1 and Fig. 2 for test circuit and waveforms.) PARAMETER Minimum Frequency Response Propagation delay from input (CLK) to output(Q) SYMBOL fMax tPLH/tPHL Propagation delay from input (CLK) to output( Q ) Propagation delay from input ( PRE or CLR ) to output(Q or Q ) tPLH/tPHL tPLH/tPHL TEST CONDITIONS VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V VCC=1.8V VCC=2.5V VCC=3.3V VCC=5.0V MIN TYP 80 175 175 200 4.8 2.2 2.2 1.4 6 3 2.6 1.6 4.4 2.3 1.7 1.6 MAX UNIT 13.4 7.1 5.9 4.1 14.4 7.7 6.2 4.4 12.9 7 5.9 4.1 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns OPERATING CHARACTERISTICS(TA=25°C, unless otherwise specified) PARAMETER Power Dissipation Capacitance SYMBOL CPD TEST CONDITIONS VCC=1.8V VCC=2.5V f=10MHz VCC=3.3V VCC=5.0V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN TYP 35 35 37 40 MAX UNIT pF pF pF pF 5 of 7 QW-R502-989.B U74LVC1G74 CMOS IC TEST CIRCUIT AND WAVEFORMS From Output RL (Note) CL TEST CIRCUIT Note: CL includes probe and jig capacitance. Fig. 1 Load circuitry for switching times. VCC 1.8V 2.5V 3.3V 5V Inputs VIN VCC VCC 3V VCC tR, tF ≤2ns ≤2ns ≤2.5ns ≤2.5ns UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw VM CL RL VCC/2 VCC/2 1.5V VCC/2 30pF 30pF 50pF 50pF 1KΩ 500Ω 500Ω 500Ω 6 of 7 QW-R502-989.B U74LVC1G74 CMOS IC TEST CIRCUIT AND WAVEFORMS(Cont.) Note: All input pulses are supplied by generators having the following characteristics: PRR≤10MHz, ZO=50Ω Fig. 2 Propagation delay from input to output and input voltage waveforms. UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 7 QW-R502-989.B