Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74AHC595
CMOS IC
8-BIT SHIFT REGISTER WITH
3-STATE OUTPUT REGISTERS

SOP-16
DESCRIPTION
The UTC 74AHC595 contains an 8-bit serial-in, parallel-out shift
register that feeds an 8-bit D-type storage register. The storage
register has parallel 3-state outputs. Separate clocks are provided
for both the shift and storage registers. The shift register has a direct
SSOP-16
(150mil)
overriding clear ( SRCLR ) input, serial (SER) input, and a serial
output for cascading. When the output-enable ( OE ) input is high, all
outputs, except QH’, are in the high-impedance state.
Both the shift-register clock (SRCLK) and storage-register clock
(RCLK) are positive-edge triggered. If both clocks are connected
together the shift register always is one clock pulse ahead of the
storage register.

TSSOP-16
FEATURES
* Operation Voltage Range: 2 ~ 5.5V
* Shift Register Has Direct Clear
* 8-bit Serial-In, Parallel-Out Shift

ORDERING INFORMATION
Ordering Number
U74AHC595G-S16-R
U74AHC595G-R16-R
U74AHC595G-P16-R

Package
SOP-16
SSOP-16
TSSOP-16
Packing
Tape Reel
Tape Reel
Tape Reel
MARKING
SOP-16 / TSSOP-16
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Copyright © 2015 Unisonic Technologies Co., Ltd
SSOP-16
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

CMOS IC
PIN CONFIGURATION
FUNCTION TABLE
FUNCTION
INPUTS
RCLK
OE
SRCLR
SER
QH’
Qn
X
X
L
L
X
L
NC
X
↑
L
L
X
L
L
X
X
H
L
X
L
Z
↑
X
L
H
H
QG’
NC
X
↑
L
H
X
NC
Qn’
↑
↑
L
H
X
QG’ Qn’
A Low-Level on SRCLR only affects the shift
registers.
Empty shift register loaded into storage register.
Shift register clear. Parallel outputs in
high-impedance OFF-state
Logic high level shifted into the first shift register.
Contents of all shift register stages shifted through,
e.g. previous state of stage G(internal QG’) appears
on the serial output(QH’).
Contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel
output stages.
Contents of shift register shifted through. Previous
contents of the shift register is transferred to the
storage register and the parallel output stages.
Note:H : HIGH voltage level.
L : LOW voltage level.
X : Don’t care.
Z : High impedance OFF-state.
NC: No change.
↑ : Low-to-High transition.
↓ : High-to-Low transition.
UNISONIC TECHNOLOGIES CO., LTD
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OUTPUTS
SRCLK
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
CMOS IC
LOGIC DIAGRAM (POSITIVE LOGIC)
SRCLR
SRCLK
SER
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
SRA
SRB
SRC
SRD
SRE
SRF
SRG
SRH
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
LRA
LRB
LRC
LRD
LRE
LRF
LRG
LRH
Q
Q
Q
Q
Q
Q
Q
Q
QA
QB
QC
QD
QE
QF
QG
QH
RCLK
QH’
OE

TIMING DIAGRAM
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
CMOS IC
ABSOLUTE MAXIMUM RATING (unless otherwise specified)(Note 2)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
-0.5 ~ 7.0
V
Input Voltage
VIN
-0.5 ~ 7.0
V
Output Voltage(active mode)
VOUT
-0.5 ~ VCC+0.5
V
Input Clamp Current (ViN<0)
IIK
-20
mA
Output Clamp Current (VOUT<0)
IOK
±20
mA
Output Current
IOUT
±25
mA
VCC or GND Current
ICC
±75
mA
Storage Temperature
TSTG
-65 ~ +150
°C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

THERMAL DATA
PARAMETER
Junction to Ambient

SYMBOL
SOP-16
SSOP-16
TSSOP-16
θJA
UNIT
°С/W
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Transition Rise or Fall Rate

RATINGS
73
90
108
SYMBOL
VCC
VIN
VOUT
TA
VCC=3.3±0.3V
VCC=5±0.5V
MIN
2
0
0
-40
TYP
MAX
5.5
5.5
VCC
125
100
20
∆t/∆v
UNIT
V
V
V
°C
ns/V
ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
HIGH-level input voltage
VIH
LOW-lever output voltage
VIL
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
VOH
VOL
II(LEAK)
Output Off-state Current
IOZ
Quiescent Supply Current
Input Capacitance
Output Capacitance
ICC
CIN
COUT
TEST CONDITIONS
VCC=2V
VCC=3V
VCC=5.5V
VCC=2V
VCC=3V
VCC=5.5V
VCC=2V, IOH=-50μA
VCC=3V, IOH=-50μA
VCC=4.5V, IOH=-50μA
VCC=3V, IOH=-4mA
VCC=4.5V, IOH=-8mA
VCC=2V, IOL=50μA
VCC=3V, IOL=50μA
VCC=4.5V, IOL=50μA
VCC=3V, IOL=4mA
VCC=4.5V, IOH=8mA
VCC=0 ~ 5.5V, IIN=5.5V or GND
VCC=5.5V, VIN=VCC or GND,
VOUT=VCC or GND, OE =VIH or VIL
VCC=5.5V, VIN=GND or VCC, IOUT=0
VCC=5V, VIN=VCC or GND
VCC=5V, VOUT=VCC or GND
UNISONIC TECHNOLOGIES CO., LTD
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MIN
1.5
2.1
3.85
TYP
MAX UNIT
V
0.5
0.9
1.65
1.9
2.9
4.4
2.58
3.94
2
3
4.5
3
5.5
V
V
0.1
0.1
0.1
0.36
0.36
±0.1
μA
±0.25
μA
4
10
μA
pF
pF
V
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CMOS IC
DYNAMIC CHARACTERISTICS (TA=25°C, unless otherwise specified)
PARAMETER
Maximum Clock Frequency
SYMBOL
fmax
tPLH
Propagation delay from input RCLK
to output QA-QH
tPHL
tPLH
Propagation delay from input
SRCLK to output QH'
tPHL
Propagation delay from input
SRCLR to output QH'
tPHL
tPZH
Propagation delay from input OE
to output QA-QH
tPZL
Propagation delay from input OE
to output QA-QH
tPHZ
tPLZ
TEST CONDITIONS
CL=15pF,VCC=3.3±0.3V
CL=50pF, VCC=3.3±0.3V
CL=15pF, VCC=5±0.5V
CL=50pF, VCC=5±0.5V
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
CL=15pF
VCC=3.3±0.3V
CL=50pF
CL=15pF
VCC=5±0.5V
CL=50pF
VCC=3.3±0.3V
VCC=5±0.5V
CL=50pF
VCC=3.3±0.3V
VCC=5±0.5V
UNISONIC TECHNOLOGIES CO., LTD
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MIN
80
55
135
95
TYP
120
105
170
140
6
7.9
4.3
5.6
6
7.9
4.3
5.6
6.6
9.2
4.5
6.4
6.6
9.2
4.5
6.4
6.2
9
4.5
6.4
6
7.8
4.3
5.7
7.8
9.6
5.4
6.8
8.1
3.5
9.3
3.4
MAX UNIT
MHz
MHz
MHz
MHz
11.9
ns
15.4
ns
7.4
ns
9.4
ns
11.9
ns
15.4
ns
7.4
ns
9.4
ns
13
ns
16.5
ns
8.2
ns
10.2
ns
13
ns
16.5
ns
8.2
ns
10.2
ns
12.8
ns
16.3
ns
8
ns
10
ns
11.5
ns
15
ns
8.6
ns
10.6
ns
11.5
ns
15
ns
8.6
ns
10.6
ns
15.7
ns
10.3
ns
15.7
ns
10.3
ns
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CMOS IC
TIMING REQUIREMENTS (TA=25°С, unless otherwise specified)
PARAMETER
SYMBOL
Pulse duration, SRCLK high or low
Pulse duration, RCLK high or low
tW
Pulse duration, SRCLR low
Setup Time, SER before SRCLK↑
Setup Time, SRCLK↑ before RCLK↑
Setup Time, SRCLR low before
RCLK↑
tSU
VCC=5±0.5V
VCC=3.3±0.3V
Setup Time, SRCLR high (inactive)
before SRCLK↑
Hold Time, SER after SRCLK↑

TEST CONDITIONS
VCC=3.3±0.3V
VCC=5±0.5V
VCC=3.3±0.3V
VCC=5±0.5V
VCC=3.3±0.3V
VCC=5±0.5V
VCC=3.3±0.3V
VCC=5±0.5V
VCC=3.3±0.3V
VCC=5±0.5V
VCC=3.3±0.3V
tH
MIN
5
5
5
5
5
5
3.5
3
8
5
8
TYP
5
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
ns
VCC=5±0.5V
2.5
ns
VCC=3.3±0.3V
VCC=5±0.5V
1.5
2
ns
ns
OPERATING CHARACTERISTICS (VCC=5V, TA=25°C, unless otherwise specified)
PARAMETER
Power Dissipation Capacitance
SYMBOL
CPD
TEST CONDITIONS
No load, f=1MHz
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MIN
TYP
25.2
MAX UNIT
pF
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CMOS IC
TEST CIRCUIT AND WAVEFORMS

VCC
VCC
Input
50% VCC
Timing Input
tw
50% VCC
tSU
50% VCC
0V
th
VCC
0V
Data Input
50% VCC
50% VCC
0V
VCC
VCC
1/2xVCC
Input
tPHL
tPLH
Output
0V
VOH
1/2xVCC
tPLH
1/2xVCC
1/2xVCC
1/2xVCC
Input
Output
0V
tPHZ
VOH-0.3
1/2xVCC
1/2xVCC
tPHL
1/2xVCC
VOL
VOL
VOH
VOH
tPLZ
1/2xVCC
Output
VCC
tPZH
VOL
Output
VOL+0.3
tPZL
1/2xVCC
0V
Note: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics:
PRR ≤1MHZ, ZO=50Ω, tr ≤3ns, tf ≤3ns.
3. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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