Brushless DC Motor Flash Type 8-Bit MCU HT45FM30 Revision: V.1.00 Date: February ����������������� 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Table of Contents Features.............................................................................................................. 7 CPU Features........................................................................................................................... 7 Peripheral Features................................................................................................................... 7 General Description........................................................................................... 8 Block Diagram.................................................................................................... 9 Pin Assignment................................................................................................ 10 Pin Description................................................................................................ 11 Absolute Maximum Ratings............................................................................ 13 D.C. Characteristics......................................................................................... 14 A.C. Characteristics......................................................................................... 15 Power-on Reset Characteristics..................................................................... 15 ADC Electrical Characteristics....................................................................... 15 Comparator Electrical Characteristics.......................................................... 16 OPA Electrical Characteristics....................................................................... 16 Shunt Regulator Electrical Characteristics................................................... 16 System Architecture........................................................................................ 17 Clocking and Pipelining........................................................................................................... 17 Program Counter..................................................................................................................... 18 Stack....................................................................................................................................... 18 Arithmetic and Logic Unit – ALU............................................................................................. 19 Flash Program Memory................................................................................... 19 Structure.................................................................................................................................. 19 Special Vectors....................................................................................................................... 20 Look-up Table.......................................................................................................................... 20 Table Program Example.......................................................................................................... 20 In Circuit Programming........................................................................................................... 21 RAM Data Memory........................................................................................... 22 Structure.................................................................................................................................. 22 Special Function Register Description.......................................................... 24 Indirect Addressing Registers – IAR0, IAR1........................................................................... 24 Memory Pointers – MP0, MP1................................................................................................ 24 Bank Pointer – BP................................................................................................................... 25 Accumulator – ACC................................................................................................................. 26 Program Counter Low Register – PCL.................................................................................... 26 Look-up Table Registers – TBLP, TBHP, TBLH....................................................................... 26 Status Register – STATUS...................................................................................................... 26 Rev. 1.00 2 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU EEPROM Data Memory.................................................................................... 28 EEPROM Data Memory Structure.......................................................................................... 28 EEPROM Control Registers.................................................................................................... 28 Reading Data from the EEPROM........................................................................................... 30 Writing Data to the EEPROM.................................................................................................. 30 Write Protection....................................................................................................................... 30 EEPROM Interrupt.................................................................................................................. 30 Programming Considerations.................................................................................................. 31 Programming Examples.......................................................................................................... 31 Oscillator.......................................................................................................... 32 System Oscillator Overview.................................................................................................... 32 System Clock Configurations.................................................................................................. 32 Operating Modes............................................................................................. 34 System Operation Modes........................................................................................................ 34 Control Register...................................................................................................................... 35 Oscillator Wake-up Time......................................................................................................... 36 Operating Mode Switching and Wake-up................................................................................ 37 NORMAL Mode to SLOW Mode Switching............................................................................. 37 SLOW Mode to NORMAL Mode Switching............................................................................. 39 Entering the SLEEP Mode...................................................................................................... 39 Entering the IDLE0 Mode........................................................................................................ 39 Entering the IDLE1 Mode........................................................................................................ 39 Standby Current Considerations............................................................................................. 40 Wake-up.................................................................................................................................. 40 Watchdog Timer............................................................................................... 41 Watchdog Timer Clock Source................................................................................................ 41 Watchdog Timer Control Register........................................................................................... 41 Watchdog Timer Operation..................................................................................................... 42 Reset and Initialisation.................................................................................... 43 Reset Functions...................................................................................................................... 43 Reset Initial Conditions........................................................................................................... 44 Input/Output Ports........................................................................................... 47 Pin-shared priority................................................................................................................... 48 Pull-high Resistors.................................................................................................................. 48 Port A Wake-up....................................................................................................................... 49 I/O Port Control Registers....................................................................................................... 50 Pin-remapping Functions........................................................................................................ 51 Pin-remapping Registers......................................................................................................... 51 I/O Pin Structures.................................................................................................................... 53 Programming Considerations.................................................................................................. 54 Rev. 1.00 3 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Timer Modules – TM........................................................................................ 54 Introduction ............................................................................................................................ 54 TM Operation.......................................................................................................................... 55 TM Clock Source..................................................................................................................... 55 TM Interrupts........................................................................................................................... 55 TM External Pins..................................................................................................................... 55 TM Input/Output Pin Control Registers................................................................................... 56 Programming Considerations.................................................................................................. 57 Compact Type TM – CTM................................................................................ 58 Compact TM Operation........................................................................................................... 58 Compact Type TM Register Description................................................................................. 58 Compact Type TM Operating Modes...................................................................................... 62 Compare Match Output Mode................................................................................................. 62 Timer/Counter Mode............................................................................................................... 65 PWM Output Mode.................................................................................................................. 65 Standard Type TM – STM................................................................................ 68 Standard TM Operation........................................................................................................... 68 Standard Type TM Register Description................................................................................. 69 Standard Type TM Operating Modes...................................................................................... 72 Compare Output Mode............................................................................................................ 72 Timer/Counter Mode............................................................................................................... 75 PWM Output Mode.................................................................................................................. 75 Single Pulse Mode.................................................................................................................. 78 Capture Input Mode................................................................................................................ 80 Analog to Digital Converter............................................................................ 82 A/D Overview.......................................................................................................................... 82 A/D Converter Register Description........................................................................................ 82 A/D Converter Data Registers – ADRL, ADRH....................................................................... 83 A/D Converter Control Registers – ADCR0, ADCR1, ACERL................................................. 83 A/D Operation......................................................................................................................... 86 A/D Input Pins......................................................................................................................... 87 Summary of A/D Conversion Steps......................................................................................... 88 Programming Considerations.................................................................................................. 89 A/D Transfer Function............................................................................................................. 89 A/D Programming Example..................................................................................................... 90 Operational Amplifier – OPA........................................................................... 92 Operational Amplifier Registers............................................................................................... 92 Operational Amplifier Operation.............................................................................................. 92 Operational Amplifier Offset Cancellation function.................................................................. 93 Rev. 1.00 4 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Comparators.................................................................................................... 94 Comparator Operation............................................................................................................ 94 Comparator Registers............................................................................................................. 95 Comparator Interrupt............................................................................................................... 99 Programming Considerations.................................................................................................. 99 Digital to Analog Converter – DAC............................................................... 100 DAC control........................................................................................................................... 100 DAC Register Description..................................................................................................... 100 Serial Interface Module – SIM....................................................................... 101 SPI Interface......................................................................................................................... 101 SPI Interface Operation......................................................................................................... 101 SPI Registers........................................................................................................................ 102 SPI Communication.............................................................................................................. 105 I2C Interface.......................................................................................................................... 107 I2C Interface Operation.......................................................................................................... 107 I2C Registers......................................................................................................................... 108 I2C Bus Communication........................................................................................................ 112 I2C Bus Start Signal............................................................................................................... 113 Slave Address....................................................................................................................... 114 I2C Bus Read/Write Signal.................................................................................................... 114 I2C Bus Slave Address Acknowledge Signal......................................................................... 114 I2C Bus Data and Acknowledge Signal................................................................................. 114 I2C Time-out Control.............................................................................................................. 116 Peripheral Clock Output................................................................................ 117 Peripheral Clock Operation................................................................................................... 117 Interrupts........................................................................................................ 118 Interrupt Registers................................................................................................................. 118 Interrupt Operation................................................................................................................ 127 HALL Interrupt....................................................................................................................... 129 External Interrupt .................................................................................................................. 131 Capture Timer Module Interrupt............................................................................................ 131 Comparator Interrupt............................................................................................................. 132 A/D Converter Interrupt......................................................................................................... 132 PWM Automatic Brake Control Interrupt............................................................................... 132 Over current Protection Interrupt........................................................................................... 132 Multi-function Interrupts......................................................................................................... 133 TM Interrupts......................................................................................................................... 133 PWM Interrupt....................................................................................................................... 133 Time Base Interrupts............................................................................................................. 134 LVD Interrupt......................................................................................................................... 135 EEPROM Interrupt................................................................................................................ 136 Interrupt Wake-up Function................................................................................................... 136 Programming Considerations................................................................................................ 136 Rev. 1.00 5 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Low Voltage Detector – LVD......................................................................... 137 LVD Register......................................................................................................................... 137 LVD Operation....................................................................................................................... 138 Pulse Width Modulator.................................................................................. 139 PWM Clock Source............................................................................................................... 139 PWM Operation..................................................................................................................... 140 PWM Output Control............................................................................................................. 142 PWM Dead Time Function.................................................................................................... 143 Polarity Control...................................................................................................................... 143 PWM Mask Output Control................................................................................................... 144 PWM Interrupt....................................................................................................................... 146 Over Current Protection................................................................................ 154 Over Current Protection Interrupt.......................................................................................... 156 Over Current Protection Function Register........................................................................... 157 Automatic Brake Control.............................................................................. 158 Automatic Brake modes........................................................................................................ 159 PWM Automatic Brake Control Interrupt............................................................................... 160 PWM Interrupt Auto A/D Start function.................................................................................. 162 Special Register Write Protection................................................................ 164 Capture Timer Module – CAPTM.................................................................. 165 Capture Mode....................................................................................................................... 165 Compare Mode..................................................................................................................... 166 Capture Timer Module Interrupt............................................................................................ 166 Shunt Regulator............................................................................................. 170 Application Circuit......................................................................................... 171 Instruction Set................................................................................................ 172 Introduction........................................................................................................................... 172 Instruction Timing.................................................................................................................. 172 Moving and Transferring Data............................................................................................... 172 Arithmetic Operations............................................................................................................ 172 Logical and Rotate Operations.............................................................................................. 173 Branches and Control Transfer............................................................................................. 173 Bit Operations....................................................................................................................... 173 Table Read Operations......................................................................................................... 173 Other Operations................................................................................................................... 173 Instruction Set Summary....................................................................................................... 174 Instruction Definition..................................................................................... 176 Package Information..................................................................................... 185 16-pin TSSOP Outline Dimensions....................................................................................... 185 20-pin TSSOP Outline Dimensions....................................................................................... 186 Reel Dimensions................................................................................................................... 187 Carrier Tape Dimensions....................................................................................................... 188 Rev. 1.00 6 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Features CPU Features • Operating Voltage: fSYS=16MHz: 3.3~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Two oscillators: –– Internal RC -- HIRC –– Internal 32kHz RC -- LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 16MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 2K×16 • Data Memory: 192×8 • EEPROM Memory: 64×8 • Watchdog Timer function • 18 bidirectional I/O lines • Two pin-shared external interrupts • HALL Sensor inputs Interrupt • 3-channel 12-bit PWM with complementary output • Single 16-bit Capture Timer Module – CAPTM • Single 16-bit Compact Type Timer Module • Single 10-bit Standard Type Timer Module • 4 Comparator functions • Single 8-bit DAC function • Dual Time-Base functions for generation of fixed time interrupt signals • 5-channel 10-bit resolution A/D converter • Low voltage reset function • Low voltage detect function • Over current protection function • External interrupt PWM automatic break function • PWM interrupt auto start A/D conversion • Special register protection function • Internal 5V Shunt Regulator • Internal Programmable Gain Amplifier • Serial Interfaces Module-dual SPI and I2C funtion • Package Types: 16-pin TSSOP and 20-pin TSSOP Rev. 1.00 7 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU General Description The HT45FM30 is a DC Fan Flash Memory A/D type 8-bit high performance RISC architecture microcontroller, especially designed for DC motor control applications. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 10-bit A/D converter, four comparator functions, internal Programmable Gain Amplifier, multi-channel PWM generator, Hall Sensor Interrupt, Capture Time Module and an 8-bit D/A converter. Multiple and extremely flexible Timer Modules provide timing and pulse generation. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A choice of HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the device will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Rev. 1.00 8 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Block Diagram Low Voltage Detect Low Voltage Reset Watchdog Timer Reset Circuit 8-bit RISC MCU Core Interrupt Controller HALL Interrupt Flash Program Memory HIRC Oscillator Stack Flash/EEPROM Programming Circuitry (ICP) LIRC Oscillator 10-Bit A/D Converter EEPROM Data Memory RAM Data Memory TB0/TB1 8-Bit D/A Converter + + + - I/O Rev. 1.00 CAPT PWM SIM TM0 TM1 9 TMn + - February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pin Assignment PA4/PWM1L PA5/INT2/TP0_0/TP1_0/[SCK/SCL]/[PWM2H] PB5/PWM1H PA6/INT1/TP0_1/TP1_1/[SDI/SDA]/[PWM2L] PB4/PWM0L PA7/[TCK0]/[INT1]/PCK/SDO/[PWM1H] PB3/PWM0H VSS PB2/INT0C/C0X/C3+ VDD PB1/INT0B/C1X/C3- PA0/TCK1/[INT2]/[TP1_0]/SDI/SDA/AN0/VREF PB0/INT0A/C1- PA1/TCK0/[TP1_1]/AN1/C0- PA3/SCS/[PWM1H]/AN3/C1+ PA2/SCK/SCL/AN2/C0+/OPA+ HT45FM30 16 TSSOP – A PA4/PWM1L PA5/INT2/TP0_0/TP1_0/[SCK/SCL]/[PWM2H] PB5/PWM1H PA6/INT1/TP0_1/TP1_1/[SDI/SDA]/[PWM2L] PC2/[SCK/SCL]/C2X/PWM2H PB4/PWM0L PC3/[SCS]/C3X/PWM2L PB3/PWM0H PC1/[TP0_1]/[SDO]/C2+ PA7/[TCK0]/[INT1]/PCK/SDO/[PWM1H] PC0/[TP0_0]/[SDI/SDA]/C2- VSS VDD PB2/INT0C/C0X/C3+ PB1/INT0B/C1X/C3- PA0/[TCK1]/[INT2]/[TP1_0]/SDI/SDA/AN0/VREF PB0/INT0A/C1- PA1/TCK0/[TP1_1]/AN1/C0- PA3/SCS/[PWM1H]/AN3/C1+ PA2/SCK/SCL/AN2/C0+/OPA+ HT45FM30 20 TSSOP – A Rev. 1.00 10 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pin Description Pad Name PA0/TCK1/INT2/TP1_0/ SDI/SDA/AN0/VREF PA1/TCK0/TP1_1/AN1/ C0- PA2/SCK/SCL/AN2/ C0+/OPA+ Function OPT PA0 PAPU PAWU PA5/INT2/TP0_0/ TP1_0/SCK/SCL/ PWM2H Rev. 1.00 ST O/T Description CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. TCK1 ― ST — TM1 input INT2 ― ST — External Interrupt 2 input TP1_0 PRM0 ST CMOS SDI — ST — SDA — ST NMOS TM1 I/O SPI Data input I2C Data AN0 ACERL AN — A/D converter input VREF ADCR1 AN — A/D converter reference input PA1 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. TCK0 PRM0 ST — TP1_1 PRM0 ST CMOS AN1 ACERL AN — A/D converter input C0- CP0C AN — Comparator 0 negative input PA2 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up TM0 input TM1 I/O SCK — ST CMOS SPI Serial Clock SCL — ST NMOS I2C Clock AN2 ACERL AN — A/D converter input C0+ CP0C AN — Comparator 0 positive input OPA+ ADCR1 AN — OPA positive input PA3 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. SCS PA3/SCS/PWM1H/AN3/ C1+ PWM1H PA4/PWM1L I/T — ST CMOS SPI Slave Select PRM1 PWMC1 — CMOS PWM output AN3 ACERL AN — A/D converter input C1+ CP1C AN — Comparator 1 positive input PA4 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. PWM1L PWMC1 — CMOS PWM output PA5 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. INT2 — ST — TP0_0 PRM0 ST CMOS TM0 I/O TP1_0 PRM0 ST CMOS TM1 I/O SCK — ST CMOS SPI Serial Clock SCL — ST NMOS I2C Clock PWM2H PRM1 PWMC1 — CMOS PWM output 11 External Interrupt 2 input February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pad Name PA6/INT1/TP0_1/ TP1_1/SDI/SDA/ PWM2L PA7/TCK0/INT1/PCK/ SDO/PWM1H Function OPT PA6 PAPU PAWU PB1/INT0B/C1X/C3- PB2/INT0C/C0X/C3+ PB3/PWM0H PB4/PWM0L PB5/PWM1H PC0/TP0_0/SDI/SDA/ C2- PC1/TP0_1/SDO/C2+ Rev. 1.00 ST O/T Description CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. INT1 — ST — TP0_1 PRM0 ST CMOS TM0 I/O TP1_1 PRM0 ST CMOS TM1 I/O SDI — ST — SDA — ST NMOS I2C Data PWM2L PRM1 PWMC1 — CMOS PWM output PA7 PAPU PAWU ST CMOS Bidirectional I/O lines. Register enabled pull-up and wake-up. TCK0 PRM0 ST — TM0 input INT1 — ST — External Interrupt 1 input External Interrupt 1 input SPI Data input PCK — — CMOS Peripheral Clock output SDO — — CMOS SPI Data output — CMOS PWM output Bidirectional I/O lines. Register enabled pull-up. PRM1 PWM1H PWMC1 PB0/INT0A/C1- I/T PB0 PBPU ST CMOS INT0A — ST — External Interrupt 0 input Comparator 1 negative input C1- CP1C AN — PB1 PBPU ST CMOS INT0B — ST — C1X CP1C — CMOS C3- CP3C AN — PB2 PBPU ST CMOS INT0C — ST — C0X CP0C — CMOS C3+ CP3C AN — PB3 PBPU ST CMOS Bidirectional I/O lines. Register enabled pull-up. PWM0H — — CMOS PWM output PB4 PBPU ST CMOS Bidirectional I/O lines. Register enabled pull-up. PWM0L — — CMOS PWM output PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up . — CMOS PWM output PRM1 PWM1H PWMC1 General purpose I/O. Register enabled pull-up. External Interrupt 0 input Comparator 1 output Comparator 3 negative input Bidirectional I/O lines. Register enabled pull-up. External Interrupt 0 input Comparator 0 output Comparator 3 positive input PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up . TP0_0 PRM0 ST CMOS TM0 I/O SDI — ST — SDA — ST NMOS SPI Data input I2C Data C2- CP2C AN — PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up . TP0_1 PRM0 ST CMOS TM0 I/O SPI Data output SDO — — CMOS C2+ CP2C AN — 12 Comparator 2 negative input Comparator 2 positive input February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pad Name Function OPT I/T O/T Description PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up SPI Serial Clock SCK — ST CMOS SCL — ST NMOS I2C Clock C2X CP2C — CMOS Comparator 2 output PWM2H PRM1 PWMC1 — CMOS PWM output General purpose I/O. Register enabled pull-up . PC2/SCK/SCL/C2X/ PWM2H PC3 PCPU ST CMOS SCS — ST CMOS SPI Slave Select C3X CP3C — CMOS Comparator 3 output PWM2L PRM1 PWMC1 — CMOS PWM output VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, GND PC3/SCS/C3X/PWM2L Note: The pins in the table are for the largest package size. As a result some pins on the smaller packages may not exist. I/T: Input type; O/T: Output type OPT: Optional by register option PWR: Power; ST: Schmitt Trigger input AN: Analog input pin CMOS: CMOS output Absolute Maximum Ratings Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature .................................................................................................. -50°C to 150°C Operating Temperature . ............................................................................................. -40°C to 125°C IOH Total...................................................................................................................................-100mA IOL Total.................................................................................................................................... 100mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 13 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD1 Operating Voltage (HIRC OSC) — fSYS=16MHz VLVR — 5.5V V IDD1 Operating Current (HIRC OSC, fSYS=fH, fSUB=fLIRC) No load, Regulator disable, fH=16MHz, 5V WDT enable — 5.0 7.5 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/2, WDT enable — 3.4 5.1 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/4, WDT enable — 2.2 3.3 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/8, WDT enable — 1.8 2.7 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/16, WDT enable — 1.6 2.4 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/32, WDT enable — 1.5 2.2 mA 5V No load, Regulator disable, fH=16MHz, fL=fH/64, WDT enable — 1.4 2.1 mA IDD2 Operating Current (HIRC OSC, fSYS=fL, fSUB=fLIRC) IDD3 Operating Current (LIRC OSC, fSYS=fL=fLIRC, fSUB=fLIRC) 5V No load, Regulator disable, WDT enable, LVR enable — 100 150 μA ISTB1 Stanby Current(Idle) (HIRC OSC, fSYS=fH, fSUB=fLIRC) 5V No load, Regulator disable, system HALT, WDT enable, fSYS=16MHz — 2.2 3.3 mA ISTB2 Stanby Current(Idle) (HIRC OSC, fSYS=off, fSUB=fLIRC) 5V No load, Regulator disable, system HALT, WDT enable, fSYS=16MHz — 3.0 6.0 μA ISTB3 Stanby Current(Idle) No load, Regulator disable, system 5V (HIRC OSC, fSYS=fH/64, fSUB=fLIRC) HALT, WDT enable, fSYS=16MHz/64 — 1.3 2.0 mA ISTB4 Stanby Current(Idle) (LIRC OSC, fSYS=fL=fLIRC, fSUB=fLIRC) 5V No load, Regulator disable, system HALT, WDT enable, fSYS=fLIRC — 5.0 10 μA ISTB5 Stanby Current(Sleep) (fSYS=off, fSUB=fLIRC) 5V No load, Regulator disable, system HALT, WDT enable — 3.0 6.0 μA ISTB6 Stanby Current(Sleep) (fSYS=off, fSUB=fLIRC) — No load, Regulator disable, system HALT, WDT enable, LVDEN=1 — 60 90 μA VIL Input Low Voltage for I/O Ports or Input Pins 5V — 0 — 1.5 V — — 0 — 0.2VDD V VIH Input High Voltage for I/O Ports or Input Pins 5V — 3.5 — 5.0 V — — 0.8VDD — VDD V VLVR Low Voltage Reset Voltage — LVR enable -5% 3.15 +5% V +5% V LVDEN=1, VLVD=3.3V VLVD Low Voltage Detector Voltage — LVDEN=1, VLVD=3.6V 3.3 -5% LVDEN=1, VLVD=4.2V 3.6 4.2 IOL I/O Port Sink Current 5V VOL=0.1VDD 10 20 — mA IOH I/O Port Source Current 5V VOH=0.9VDD -5 -10 — mA RPH Pull-high Resistance of I/O Ports 5V — 10 30 50 kΩ VBG Bandgap reference with buffer voltage — — -3% 1.25 +3% V IBG Bandgap reference with buffer driving current — VBG is used — 240 360 μA Note: The IDD and ISTB are not include shunt current of Shunt Regulator. Rev. 1.00 14 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU A.C. Characteristics Ta=25°C Symbol Test Conditions Parameter Min. Typ. Max. -2% 16 +2% MHz — — 1 MHz fSYS=HIRC OSC — 15~16 — fSYS=LIRC OSC — 1~2 — Condition VDD Ta=-40°C to 125°C Unit fSYS System clock(HIRC) 5V fTCK Timer I/P Frequency(TCKn) — tSST System start-up timer period (wake-up from HALT) — tINT Interrupt pulse width — — 1 — — μs tLVR Low Voltage Width to Reset — — 60 120 240 μs tLVD Low Voltage Width to Interrupt — — 20 60 120 μs tLVDS LVDO stable time — — 15 — — μs tBGS VBG turn on stable time — — 10 — — ms tEERD EEPROM Read Time — — 1 2 4 tSYS tEEWR EEPROM Write Time — — 1 2 4 ms — tSYS Note: tSYS=1/fSYS Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms ADC Electrical Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit V VAD A/D Input Voltage — — 0 — VDD/VREF VREF ADC input reference voltage range — — 2 — VDD+0.1 V DNL Differential non-linearity 5V — — ±1 ±2 LSB INL Integral non-linearity 5V IADC Only ADC Enable, Others Disable 5V tAD A/D Clock Period — tADC AD Conversion Time — tON2ST ADC on to ADC start — Rev. 1.00 — No load — 10 bit ADC — 15 — ±2 ±4 LSB — 0.8 1.2 mA 0.125 — 10 μs — 12 — tAD 2 — — μs February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Comparator Electrical Characteristics Symbol Ta=25°C Test Conditions Parameter VDD Condition Min. Typ. Max. Unit VCMP Comparator operating voltage — — VLVR — 5.5 V VCMPOS Comparator input offset voltage 5V — -10 — +10 mV VHYS Hysteresis width 5V — 20 40 60 mV VCM Comparator common mode voltage range — — VSS — VDD-1.4V V AOL Comparator open loop gain — — 60 80 — dB tPD Comparator response time 5V With 100mV overdrive(Note) — 370 560 ns Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to (VCM+100mV) or from VDD to (VCM-100mV). OPA Electrical Characteristics Symbol VOPA Parameter OPA operating voltage Ta=25°C Test Conditions Condition VDD — — 5V AOF4~AOF0=‘10000’ 5V After offset calibration Min. Typ. Max. Unit VLVR — 5.5 V -15 — +15 mV mV VOPAOS OPA input offset voltage -2 — +2 VCM OPA common mode voltage range — — VSS — VDD-1.4V V PSRR Power Supply Rejection Ratio — — 60 — — dB CMRR Common Mode Rejection Ratio — 60 — — dB AOL OPA open loop gain — 60 80 — dB SR Slew Rate+, Rate- — No load 1.8 2.5 — V/μs GBW Gain Band Width — RL=1MΩ, CL=100pF 500 2000 — kHz VCM=0~VDD-1.4V — Shunt Regulator Electrical Characteristics Symbol Parameter Condition Ta=25°C Min. Typ. Max. Unit V VUNREG Input Supply Voltage — 7 — 20 VDD Shunt Voltage — -5% 5 +5% V ISUPPLY Shunt Current — 5 — 80 mA Rev. 1.00 16 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.00 17 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register Low Byte PC10~PC8 PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Rev. 1.00 18 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU P ro g ra m T o p o f S ta c k B o tto m S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r S ta c k L e v e l 3 o f S ta c k C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 4 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Program Memory Structure Rev. 1.00 19 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “700H” which refers to the start address of the last page within the 2K words Program Memory of the device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “706H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.00 20 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer-note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer tbhp,a mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address “706H” transferred to ; tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “705H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register ; tempreg2 : : org 700h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. Rev. 1.00 Holtek Writer Pin Name MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data ICPCK PA2 Programming Clock ICPMS PA7 Programming Mode Select VDD VDD Power Supply VSS VSS Ground 21 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line as a programming mode select. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplemenetary literature. During the programming process the PA7 pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. Rev. 1.00 Capacity Banks 192×8 0: 80H~FFH 1: 80H~BFH 22 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bank 0 Bank 1 Bank 0 Bank 1 00H IAR0 30H ADRL 01H MP0 31H ADRH 02H IAR1 32H ADCR0 03H MP1 33H ADCR1 04H BP 34H ACERL 05H ACC 35H CP0C 06H PCL 36H CP1C 07H TBLP 37H CP2C 08H TBLH 38H CP3C 09H TBHP 39H DAC 0AH STATUS 3AH DACC 0BH SMOD 3BH HALLC 0CH LVDC 3CH HALLD 0DH INTEG 3DH PRM0 0EH WDTC 3EH PRM1 0FH TBC 3FH Unimplemented, read as “0” PTSFR 10H INTC0 40H Unimplemented, read as “0” 11H INTC1 41H 12H INTC2 42H EED 13H INTC3 43H TMPC0 14H MFI0 44H - 47H Unimplemented, read as “0” 15H MFI1 48H CAPTC0 16H MFI2 49H CAPTC1 17H Unimplemented, read as “0” 4AH CAPTMDL 18H PAWU 4BH CAPTMDH 19H PAPU 4CH CAPTMAL 1AH PA 4DH CAPTMAH 1BH PAC 4EH CAPTMCL 1CH PBPU 4FH CAPTMCH 1DH PB 50H PWMC0 1EH PBC 51H PWMC1 1FH PCPU 52H PWMC2 20H PC 53H PWMC3 21H PCC 54H PWMC4 22H TM0C0 55H PWMC5 23H TM0C1 56H PWMC6 24H TM0DL 57H PWMDL 25H TM0DH 58H PWMDH 26H TM0AL 59H PWMPL 27H TM0AH 5AH PWMPH 28H TM0RP 5BH PWML 29H TM1C0 5CH PWMH 2AH TM1C1 5DH PWMDT 2BH TM1DL 5EH ASADCC 2CH TM1DH 5FH ASADCT 2DH TM1AL 60H PWMBKC 2EH TM1AH 61H PWMBKD 2FH OPAC 62H PWMOCC Rev. 1.00 23 EEC EEA February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bank 0 63H PRM2 64H I2CTOC 65H SIMC0 66H SIMC1 Bank 1 67H SIMD 68H SIMC2/SIMA 69H~7FH Unimplemented, read as “0” 80H~BFH General Purpose General Purpose Data Memory Data Memory Bank 1 (64 Bytes) C0H~FFH Bank 0 (128 Bytes) Unimplemented, read as “0” RAM Data Memory The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the PTSFR and EEC registers at the address of 3FH and 40H, which are only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory is the address 00H. Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer, MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Rev. 1.00 24 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code.section at 0 ´code´ org00h start: mov a, 04h mov block, a mov a, offset adres1 mov mp0, a loop: clr IAR0 inc mp0 sdz block jmp loop continue: ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by mp0 ; increment memory pointer ; check if last memory location has been cleared The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Bank Pointer – BP For this device, the Data Memory is divided into two banks. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. BP Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 25 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. Rev. 1.00 26 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x “x” unknown Bit 7, 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 Unimplemented, read as “0” TO: Watchdog Time-Out flag 0: after power up or executing the “CLR WDT” or “HALT” instruction 1: a watchdog time-out occurred PDF: Power down flag 0: after power up or executing the “CLR WDT” instruction 1: by executing the “HALT” instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Z: Zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation. C is also affected by a rotate through carry instruction. 27 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU EEPROM Data Memory One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for this device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Capacity Address 64×8 00H~3FH EEPROM Control Registers EEA (Address register) and EED (Data register) in Bank 0, and EEC (Control register) in Bank 1 are EEPROM control registers for accessing the EEPROM. As indirect addressing is the only way to access the EEC register, all read and write operations to this register must take place using the Indirect Addressing Register, IAR1, and the Memory Pointer, MP1. Because the EEC control register is located in Bank 1 of the RAM Data Memory at location 40H, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer set to “1”. EEPROM Control Registers List Name Bit 7 6 5 4 3 2 1 0 D0 EEA — — D5 D4 D3 D2 D1 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 Data EEPROM address data EEPROM address bit 5~bit 0 28 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: disable 1: enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: write cycle has finished 1: activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: disable 1: enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: read cycle has finished 1: activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 Data EEPROM data data EEPROM data 29 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multifunction interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.00 30 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Programming Examples Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle – set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.3 SET IAR1.2 BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.00 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; start Write Cycle – set WR bit ; check for write cycle end ; disable EEPROM read/write 31 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. System Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base functions. The device provides two oscillator circuits for system clocks, named the high frequency internal RC oscillator, HIRC, and the low frequency internal 32kHz RC oscillator, LIRC. Type Name Freq. Internal High Speed RC HIRC 16MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations The device has two different clock sources for both the CPU and peripheral function operation. By providing the user two clock options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from an HIRC oscillator. The low speed system clock source can be sourced from the internal clock fL, sourced from LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. Each of these internal clocks is sourced from the LIRC oscillator. Rev. 1.00 32 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU System Clock Configurations Note: 1. When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. 2. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 16MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via software option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Rev. 1.00 33 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Operating Modes Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-verse, lower speed clocks reduce current consumption. As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode Description CPU fSYS fSUB fTBC NORMAL Mode On fH~fH/64 On On SLOW Mode On fL On On IDLE0 Mode Off Off On On IDLE1 Mode Off On On On SLEEP Mode Off Off On Off • NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, the HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. • SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used is the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, fH is off. • SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP mode the CPU will be stopped. However the fSUB clock will continue to operate. • IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped and the Watchdog Timer clock, fSUB, will be still on. Rev. 1.00 34 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU • IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fSUB, will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5 Rev. 1.00 CKS2~CKS0: The fHL Clock Selection 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0" Bit 3 LTO: LIRC System OSC SST ready flag 0: not ready 1: ready This is the low speed system oscillator SST ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: HIRC System OSC SST ready flag 0: not ready 1: ready This is the high speed system oscillator SST ready flag which indicates when the high speed system oscillator is stable after a wake-up has occurred. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. 35 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 1 IDLEN: IDLE Mode Control 0: disable 1: enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mod. If the bit is low the device will enter the SLEEP mode when a HALT instruction is executed. Bit 0 HLCLK: System Clock Selection 0: fH/2~fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. WDTC Register Bit 7 6 5 4 Name FSYSON WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 0 1 0 Bit 7 FSYSON: fSYS Control in IDLE Mode 0: disable 1: enable Bit 6~0 WDT related control registers described elsewhere 3 2 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Oscillator Wake-up Time To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. It will take 15~16 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. Rev. 1.00 36 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.00 37 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Rev. 1.00 38 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT". instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in WDTC register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock and fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in WDTC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock and fSUB clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 39 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to device which has different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 40 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal low speed oscillator, fLIRC. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the required time-out period. WDTC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name FSYSON WS2 WS1 WS0 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 0 1 0 Bit 7 FSYSON: fSYS control in IDLE Mode 0: disable 1: enable Bit 6~4 WS2~WS0: WDT Time-out Period Selection 000: 256/fLIRC 001: 512/fLIRC 010: 1024/fLIRC 011: 2048/fLIRC 100: 4096/fLIRC 101: 8192/fLIRC 110: 16384/fLIRC 111: 32768/fLIRC These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the time‑out period. Bit 3~0 Undefined bit These bits can be read or written by user software program. 41 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Watchdog Timer Operation In these devices the Watchdog Timer supplied by the fLIRC oscillator and is therefore always on. The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. The Watchdog Timer is cleared using a single CLR WDT instruction. The maximum time out period is when the 215 division ratio is selected. As an example, with the LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum time-out of 7.8ms for the 28 division ration. Watchdog Timer Rev. 1.00 42 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is When the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are four ways in which a microcontroller reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart • Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected as VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart Rev. 1.00 43 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU • Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as power on reset except that the Watchdog time-out flag TO will be set to “1”. Note: tRSTD is power-on delay, typical time=50ms WDT Time-out Reset during Normal Operation Timing Chart • Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u" unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs, and AN0~AN3 as A/D input pins Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Rev. 1.00 44 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) LVR Reset (Normal Operation) LVR Reset (HALT) WDT Time-out (HALT)* IAR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu IAR1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---- -xxx - - - - - uuu - - - - - uuu - - - - - uuu - - - - - uuu STATUS --00 xxxx - - 1 u uuuu - - uu uuuu - - 0 1 uuuu - - 1 1 uuuu SMOD 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu - uuuu LVDC --00 -000 --00 -000 --00 -000 --00 -000 - - uu - uuu INTEG ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 uuuu - uuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PB - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PBC - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PCPU ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PC - - - - 1111 - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu PCC - - - - 1111 - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu TM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u - - - TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0RP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 ---- --00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 ---- --00 - - - - - - uu Rev. 1.00 45 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Register Reset (Power On) WDT Time-out (Normal Operation) LVR Reset (Normal Operation) LVR Reset (HALT) WDT Time-out (HALT)* OPAC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ADRL(ADRFS=0) xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu - - - - - - ADRL(ADRFS=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADRFS=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADRFS=1) ---- --xx ---- --xx ---- --xx ---- --xx - - - - - - uu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu - uuu ADCR1 0000 -000 0000 -000 0000 -000 0000 -000 uuuu - uuu ACERL - - - - 1111 - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu CP0C 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 uuuu uuuu CP1C 1 0 0 0 1 - 11 1 0 0 0 1 - 11 1 0 0 0 1 - 11 1 0 0 0 1 - 11 uuuu u - uu CP2C 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 uuuu uuuu CP3C 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 1 0 0 0 1 0 11 uuuu uuuu DAC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu DACC 0000 00-- 0000 00-- 0000 00-- 0000 00-- uuuu uu - - HALLC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu HALLD ---- -000 ---- -000 ---- -000 ---- -000 - - - - - uuu PRM0 -000 0000 -000 0000 -000 0000 -000 0000 - uuu uuuu PRM1 ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PRM2 --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu EEA --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu EED 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TMPC0 --01 --01 --01 --01 --01 --01 --01 --01 - - uu - - uu CAPTC0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMDL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMDH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMAL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMAH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMCL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu CAPTMCH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWMC0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMC1 --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PWMC2 --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PWMC3 --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PWMC4 --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PWMC5 ---- --10 ---- --10 ---- --10 ---- --10 - - - - - - uu PWMC6 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMDL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMDH ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PWMPL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMPH ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PWML 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMH ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PWMDT 00-- 0000 00-- 0000 00-- 0000 00-- 0000 uu - - uuuu ASADCC ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu ASADCT 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMBKC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.00 46 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Reset (Power On) Register WDT Time-out (Normal Operation) LVR Reset (Normal Operation) LVR Reset (HALT) WDT Time-out (HALT)* PWMBKD --00 0000 --00 0000 --00 0000 --00 0000 - - uu uuuu PWMOCC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMC2/SIMA 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PTSFR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 ---- 0000 - - - - uuuu Note: "*" stands for "warm reset" "-" not implement "u" stands for "unchanged" "x" stands for "unknown" Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A,[m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 PBC — — D5 D4 D3 D2 D1 D0 PCPU — — — — D3 D2 D1 D0 PC — — — — D3 D2 D1 D0 PCC — — — — D3 D2 D1 D0 I/O Register List Rev. 1.00 47 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pin-shared priority The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The chosen function of the multi-function I/O pins is set by application program control. The following table shows Pin-shared priority. Pin Name PA0/TCK1/INT2/TP1_0/SDI/SDA/AN0/VREF PA1/TCK0/TP1_1/AN1/C0PA2/SCK/SCL/AN2/C0+/OPA+ PA3/SCS/PWM1H /AN3/C1+ Priority 1 2 AN0, VREF AN1, C0- 3 4 SDI/SDA TP1_0 ****INT2, TCK1 TP1_1 AN2, C0+, OPA+ SCK/SCL 5 6 PA0 — TCK0 PA1 — — PA2 — — — AN3, C1+ PWM1H SCS PA3 — — PA4/PWM1L PWM1L PA4 — — — — PA5/INT2/TP0_0/TP1_0/SCK/SCL/PWM2H PWM2H SCK/SCL TP1_0 TP0_0 PA6/INT1/TP0_1/TP1_1/SDI/SDA/PWM2L PWM2L SDI/SDA TP1_1 TP0_1 **INT1 PA6 PA7/TCK0/INT1/PCK/SDO/PWM1H PWM1H SDO PCK *INT1 TCK0 PA7 PB0/INT0A/C1- C1- ***INT0A PB0 — — — PB1/INT0B/C1X/C3- C3- ***INT0B C1X PB1 — — PB2/INT0C/C0X/C3+ C3+ ***INT0C C0X PB2 — — PB3/PWM0H PWM0H PB3 — — — — PB4/PWM0L PWM0L PB4 — — — — PB5/PWM1H PWM1H PB5 — — — — PC0 — — SDI/SDA TP0_0 *****INT2 PA5 PC0/TP0_0/SDI/SDA/C2- C2- PC1/TP0_1/SDO/C2+ C2+ SDO TP0_1 PC1 — — PC2/SCK/SCL/C2X/PWM2H PWM2H C2X SCK/ SCL PC2 — — PC3/SCS/C3X/PWM2L PWM2L C3X SCS PC3 — — Note: “**” When PA6 selects INT1 as PWM Brake input (BKEN=1) or Over Current Protection Function input pin, INT1 has higher priority then TP0_1, TP1_1, PWM2L. “***” When INT0A, INT0B or INT0C be selected as HALL sensor interrupt input, this only has input function, output function disable. “****” When PA0 select INT2 as Over Current Protection Function input pin, INT2 has higher priority then TP1_0. “*****” When PA5 select INT2 as Over Current Protection Function input pin, INT2 has higher priority then TP0_0, TP1_0, PWM2H. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PCPU, and are implemented using weak PMOS transistors. Rev. 1.00 48 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAPU: Port A bit 7~bit 0 Pull-High Control 0: disable 1: enable PBPU Register Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 PBPU: Port B bit 5~bit 0 Pull-High Control 0: disable 1: enable PCPU Register Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 PCPU: Port C bit 3~bit 0 Pull-High Control 0: disable 1: enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 PAWU: Port A bit 7~bit 0 Wake Up Control 0: disable 1: enable 49 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I/O Port Control Registers Each I/O port has its own control register known as PAC~PCC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 1 1 1 Bit 7~0 PAC: Port A bit 7~bit 0 Input/Output Control 0: output 1: input PBC Register Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 Unimplemented, read as "0" Bit 5~0 PBC: Port B bit 5~bit 0 Input/Output Control 0: output 1: input PCC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as "0" Bit 3~0 PCC: Port C bit 3~bit 0 Input/Output Control 0: output 1: input 50 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a series of PRM0 , PRM1and PRM2 registers to establish certain pin functions. Generally speaking, the analog function has higher priority than the digital function. However, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Pin-remapping Register List Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PRM0 — TCK0PS TP11PS TP10PS TP01PS TP00PS INT2PS INT1PS PRM1 — — — — P2HPS P2LPS P1HPS1 P1HPS0 PRM2 — — SCSPS SDOPS SDIPS1 SDIPS0 SCKPS1 SCKPS0 Bit 7 6 5 4 3 2 1 0 Name — TCK0PS TP11PS TP10PS TP01PS TP00PS INT2PS INT1PS R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 PRM0 Register Rev. 1.00 Bit 7 Unimplemented, read as "0" Bit 6 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA1 1: TCK0 on PA7 Bit 5 TP11PS: TP1_1 Pin Remapping Control 0: TP1_1 on PA6 1: TP1_1 on PA1 Bit 4 TP10PS: TP1_0 Pin Remapping Control 0: TP1_0 on PA5 1: TP1_0 on PA0 Bit 3 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PA6 1: TP0_1 on PC1 Bit 2 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA5 1: TP0_0 on PC0 Bit 1 INT2PS: INT2 Pin Remapping Control 0: INT2 on PA5 1: INT2 on PA0 Bit 0 INT1PS: INT1 Pin Remapping Control 0: INT1 on PA6 1: INT1 on PA7 51 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PRM1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — P2HPS P2LPS P1HPS1 P1HPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 P2HPS: PWM2H Pin Remapping Control 0: PWM2H on PC2 1: PWM2H on PA5 Bit 2 P2LPS: PWM2L Pin Remapping Control 0: PWM2L on PC3 1: PWM2L on PA6 Bit 1~0 P1HPS1~P1HPS0: PWM1H Pin Remapping Control 00: PWM1H on PB5 01: PWM1H on PA3 10: Undefined 11: PWM1H on PA7 PRM2 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 Name — — SCSPS SDOPS SDIPS1 SDIPS0 SCKPS1 SCKPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 SCSPS: SCS Pin Remapping Control 0: SCS on PA3 1: SCS on PC3 Bit 4 SDOPS: SDO Pin Remapping Control 0: SDO on PA7 1: SDO on PC1 Bit 3~2 SDIPS1~SDIPS0: SDI/SDA Pin Remapping Control 00: SDI/SDA on PA0 01: SDI/SDA on PA6 10: Undefined 11: SDI/SDA on PC0 Bit 1~0 SCKPS1~SCKPS0: SCK/SCL Pin Remapping Control 00: SCK/SCL on PA2 01: SCK/SCL on PA5 10: Undefined 11: SCK/SCL on PC2 52 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.00 53 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PCC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PC, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard sections. Introduction The device contains a 16-bit Compact Type and a 10-bit Standard Type TM unit which are with their individual reference name, TM0 and TM1. Although similar in nature, the different TM types vary in their feature complexity. The common features to both of Compact and Standard TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. Function CTM STM Timer/Counter √ √ I/P Capture ― √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty ― 1 Edge Edge Duty or Period Duty or Period TM Function Summary Rev. 1.00 54 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TM Operation The two different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. Rev. 1.00 55 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Rev. 1.00 56 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name — — T1CP1 T1CP0 — — T0CP1 T0CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 1 — — 0 1 Bit 7~6 Unimplemented, read as "0" Bit 5 T1CP1: TP1_1 pin Control 0: disable 1: enable Bit 4 T1CP0: TP1_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented, read as "0" Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte TMxAL ––note that here data is only written to the 8-bit buffer. ♦ Step 2. Write data to High Byte TMxAH ♦ ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA ♦♦ Step 1. Read data from the High Byte TMxDH or TMxAH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL or TMxAL ––this step reads data from the 8-bit buffer. Rev. 1.00 57 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Compact Type TM – CTM Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. Note: n=0 Compact Type TM Block Diagram Compact TM Operation At its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 8 bits wide whose value is compared with the highest 8 bits in the counter while the CCRA is the 16 bits and therefore compares with all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Register Description Overall operation of the Compact TM is controlled using seven registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the eight CCRP bits. A register is used to setup the value on the internal CCRP 8-bit register, these eight bits are then compared with the internal counter's highest eight bits. Rev. 1.00 58 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM0C0 T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR D0 TM0DL D7 D6 D5 D4 D3 D2 D1 TM0DH D15 D14 D13 D12 D11 D10 D9 D8 TM0AL D7 D6 D5 D4 D3 D2 D1 D0 TM0AH D15 D14 D13 D12 D11 D10 D9 D8 TM0RP D7 D6 D5 D4 D3 D2 D1 D0 Compact TM Register List TM0C0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 T0PAU: TM0 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3 T0ON: TM0 Counter On/Off Control 0: off 1: on This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high. Bit 2~0 Unimplemented, read as “0” 59 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TM0C1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T0M1~T0M0: Select TM0 Operating Mode 00: Compare Match Output Mode 01: Undefined Mode 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T0IO1~T0IO0: Select TP0_0, TP0_1 output function Compare Match Output Mode 00: no change 01: output low 10: output high 11: toggle output PWM Mode 00: force inactive state 01: force active state 10: PWM output 11: undefined Timer/counter Mode: unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1 register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high. Bit 3 T0OC: TP0_0, TP0_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode 0: active low 1: active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. 60 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 2 T0POL: TP0_0, TP0_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T0DPX: TM0 PWM period/duty Control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T0CCLR: Select TM0 Counter clear condition 0: TM0 Comparator P match 1: TM0 Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not used in the PWM Mode. TM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TM0DL: TM0 Counter Low Byte Register bit 7~bit 0 TM0 16-bit Counter bit 7~bit 0 TM0DH Register Bit 7 6 5 4 3 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R R POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TM0DH: TM0 Counter High Byte Register bit 7~bit 0 TM0 16-bit Counter bit 15~bit 8 TM0AL Register Bit 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 7 TM0AL: TM0 CCRA Low Byte Register bit 7~bit 0 TM0 16-bit CCRA bit 7~bit 0 61 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TM0AH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0AH: TM0 CCRA High Byte Register bit 7~bit 0 TM0 16-bit CCRA bit 15~bit 8 TM0RP Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0RP: TM0 CCRP Register bit 7~bit 0 TM0 CCRP 8-bit register, compared with the TM0 Counter bit 15~bit 8. Comparator P Match Period 0: 65536 TM0 clocks 1~255: 256×1~255 TM0 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter's highest eight bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the T0M1 and T0M0 bits in the TM0C1 register. Compare Match Output Mode To select this mode, bits T0M1 and T0M0 in the TM0C1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the T0CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both T0AF and T0PF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the T0CCLR bit in the TM0C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the T0AF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when T0CCLR is high no T0PF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 16-bit, FFFF Hex, value, however here the T0AF interrupt request flag will not be generated. Rev. 1.00 62 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a T0AF interrupt request flag is generated after a compare match occurs from Comparator A. The T0PF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the T0IO1 and T0IO0 bits in the TM0C1 register. The TM output pin can be selected using the T0IO1 and T0IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the T0ON bit changes from low to high, is setup using the T0OC bit. Note that if the T0IO1 and T0IO0 bits are zero then no pin change will take place. Co�nte� Val�e Co�nte� ove�flow CCRP=0 0x��� TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nte� clea�ed �� CCRP val�e CCRP > 0 Co�nte� Resta�t Res�me CCRP Pa�se CCRA Stop Time TnON TnPAU TnPOL CCRP Int. �lag TnP� CCRA Int. �lag TnA� TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected �� TnA� flag. Remains High �ntil �eset �� TnON �it O�tp�t Toggle with TnA� flag He�e TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inve�ts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t cont�olled �� othe� pin-sha�ed f�nction Compare Match Output Mode – TnCCLR=0 Note: 1. n=0 2. With T0CCLR=0 the Comparator P match will clear the counter 3. TM output pin controlled only by T0AF flag 4. Output pin reset to initial state by T0ON bit rising edge Rev. 1.00 63 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Co�nte� ove�flow CCRA > 0 Co�nte� clea�ed �� CCRA val�e 0x��� CCRA=0 Res�me CCRA Pa�se Stop Co�nte� Resta�t CCRP Time TnON TnPAU TnPOL No TnA� flag gene�ated on CCRA ove�flow CCRA Int. �lag TnA� CCRP Int. �lag TnP� TnP� not gene�ated O�tp�t does not change TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected �� TnA� flag. Remains High �ntil �eset �� TnON �it O�tp�t Toggle with TnA� flag He�e TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inve�ts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t cont�olled �� othe� pin-sha�ed f�nction Compare Match Output Mode – TnCCLR=1 Note: 1. With T0CCLR=1 the Comparator A match will clear the counter 2. TM output pin controlled only by T0AF flag 3. TM output pin reset to initial state by T0ON rising edge 4. T0PF flags not generated when T0CCLR=1 5. n=0 Rev. 1.00 64 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Timer/Counter Mode To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the T0CCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the T0DPX bit in the TM0C1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The T0OC bit in the TM0C1 register is used to select the required polarity of the PWM waveform while the two T0IO1 and T0IO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The T0POL bit is used to reverse the polarity of the PWM output waveform. Rev. 1.00 65 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnDPX = 0; TnM [1:0] = 10 Co�nte� clea�ed �� CCRP Co�nte� Reset when TnON �et��ns high CCRP Pa�se Res�me CCRA Co�nte� Stop if TnON �it low Time TnON TnPAU TnPOL CCRA Int. �lag TnA� CCRP Int. �lag TnP� TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�cle set �� CCRA PWM Pe�iod set �� CCRP PWM �es�mes ope�ation O�tp�t cont�olled �� O�tp�t Inve�ts othe� pin-sha�ed f�nction when TnPOL = 1 PWM Mode – TnDPX=0 Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when T0IO1, T0IO0=00 or 01 4. TnCCLR bit has no influence on PWM operation 5. n=0 Rev. 1.00 66 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnDPX = 1; TnM [1:0] = 10 Co�nte� clea�ed �� CCRA Co�nte� Reset when TnON �et��ns high CCRA Pa�se Res�me CCRP Co�nte� Stop if TnON �it low Time TnON TnPAU TnPOL CCRP Int. �lag TnP� CCRA Int. �lag TnA� TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�cle set �� CCRP PWM Pe�iod set �� CCRA PWM �es�mes ope�ation O�tp�t cont�olled �� O�tp�t Inve�ts othe� pin-sha�ed f�nction when TnPOL = 1 PWM Mode – TnDPX=0 Note: 1. Here TnDPX=1 – Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0=00 or 01 4. TnCCLR bit has no influence on PWM operation 5. n=0 Rev. 1.00 67 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. Note: n=1 Standard Type TM Block Diagram Standard TM Operation At the core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared the with highest 3 bits in the counter while the CCRA is the ten bits and therefore compares all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.00 68 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 10-bit Standard TM Register List TM1C0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3 T1ON: TM1 Counter On/Off Control 0: off 1: on This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. 69 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TM1C1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1IO1~T1IO0: Select TP1_0, TP1_1 output function Compare Match Output Mode 00: no change 01: output low 10: output high 11: toggle output PWM Mode/Single Pulse Output Mode 00: force inactive state 01: force active state 10: PWM output 11: single pulse output Capture Input Mode 00: input capture at rising edge of TP1_0, TP1_1 01: input capture at falling edge of TP1_0, TP1_1 10: input capture at falling/rising edge of TP1_0, TP1_1 11: input capture disabled Timer/counter Mode: unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. 70 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. Bit 3 T1OC: TP1_0, TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/Single Pulse Output Mode 0: active low 1: active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1POL: TP1_0, TP1_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T1DPX: TM1 PWM period/duty Control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. TM1DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 71 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TM1DH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 TM1AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 TM1AH Register Bit 7 6 5 4 3 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the T1M1 and T1M0 bits in the TM1C1 register. Compare Output Mode To select this mode, bits T1M1 and T1M0 in the TM1C1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the T1CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both T1AF and T1PF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the T1CCLR bit in the TM1C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the T1AF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when T1CCLR is high no T1PF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. Rev. 1.00 72 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a T1AF interrupt request flag is generated after a compare match occurs from Comparator A. The T1PF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the T1IO1 and T1IO0 bits in the TM1C1 register. The TM output pin can be selected using the T1IO1 and T1IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the T1ON bit changes from low to high, is setup using the T1OC bit. Note that if the T1IO1 and T1IO0 bits are zero then no pin change will take place. Co�nte� Val�e Co�nte� ove�flow CCRP=0 0x��� TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nte� clea�ed �� CCRP val�e CCRP > 0 Co�nte� Resta�t Res�me CCRP Pa�se CCRA Stop Time TnON TnPAU TnPOL CCRP Int. �lag TnP� CCRA Int. �lag TnA� TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected �� TnA� flag. Remains High �ntil �eset �� TnON �it O�tp�t Toggle with TnA� flag He�e TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inve�ts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t cont�olled �� othe� pin-sha�ed f�nction Compare Match Output Mode – TnCCLR=0 Note: 1. With T1CCLR=0 the Comparator P match will clear the counter 2. TM output pin controlled only by T1AF flag 3. Output pin reset to initial state by TnON bit rising edge 4. n=1 Rev. 1.00 73 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Co�nte� ove�flow CCRA > 0 Co�nte� clea�ed �� CCRA val�e 0x��� CCRA=0 Res�me CCRA Pa�se Stop Co�nte� Resta�t CCRP Time TnON TnPAU TnPOL No TnA� flag gene�ated on CCRA ove�flow CCRA Int. �lag TnA� CCRP Int. �lag TnP� TnP� not gene�ated O�tp�t does not change TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected �� TnA� flag. Remains High �ntil �eset �� TnON �it O�tp�t Toggle with TnA� flag He�e TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inve�ts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t cont�olled �� othe� pin-sha�ed f�nction Compare Match Output Mode – TnCCLR=1 Note: Points to note for above diagram: 1. With T1CCLR=1 the Comparator A match will clear the counter 2. TM output pin controlled only by T1AF flag 3. TM output pin reset to initial state by T1ON rising edge 4. T1PF flags not generated when T1CCLR=1 5. n=1 Rev. 1.00 74 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Timer/Counter Mode To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 10 respectively and also the T1IO1 and T1IO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the T1CCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the T1DPX bit in the TM1C1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The T1OC bit in the TM1C1 register is used to select the required polarity of the PWM waveform while the two T1IO1 and T1IO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The T1POL bit is used to reverse the polarity of the PWM output waveform. Rev. 1.00 75 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnDPX = 0; TnM [1:0] = 10 Co�nte� clea�ed �� CCRP Co�nte� Reset when TnON �et��ns high CCRP Pa�se Res�me CCRA Co�nte� Stop if TnON �it low Time TnON TnPAU TnPOL CCRA Int. �lag TnA� CCRP Int. �lag TnP� TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�cle set �� CCRA PWM Pe�iod set �� CCRP PWM �es�mes ope�ation O�tp�t cont�olled �� O�tp�t Inve�ts othe� pin-sha�ed f�nction when TnPOL = 1 PWM Mode – TnDPX=0 Note: 1. Here T1DPX=0–Counter cleared by CCRP 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when T1IO1, T1IO0=00 or 01 4. T1CCLR bit has no influence on PWM operation 5. n=1 Rev. 1.00 76 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Co�nte� Val�e TnDPX = 1; TnM [1:0] = 10 Co�nte� clea�ed �� CCRA Co�nte� Reset when TnON �et��ns high CCRA Pa�se Res�me CCRP Co�nte� Stop if TnON �it low Time TnON TnPAU TnPOL CCRP Int. �lag TnP� CCRA Int. �lag TnA� TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�cle set �� CCRP PWM Pe�iod set �� CCRA PWM �es�mes ope�ation O�tp�t cont�olled �� O�tp�t Inve�ts othe� pin-sha�ed f�nction when TnPOL = 1 PWM Mode – TnDPX=1 Note: 1. Here T1DPX=1–Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when T1IO1, T1IO0=00 or 01 4. T1CCLR bit has no influence on PWM operation 5. n=1 Rev. 1.00 77 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Single Pulse Mode To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 10 respectively and also the T1IO1 and T1IO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the T1ON bit, which can be implemented using the application program. However in the Single Pulse Mode, the T1ON bit can also be made to automatically change from low to high using the external TCK1 pin, which will in turn initiate the Single Pulse output. When the T1ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The T1ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the T1ON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. Single Pulse Generation Rev. 1.00 78 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when TnON returns high CCRA Pause Counter Stops by software Resume CCRP Time TnON Software Trigger Auto. set by TCKn pin Cleared by CCRA match TCKn pin Software Trigger Software Trigger Software Clear Software Trigger TCKn pin Trigger TnPAU TnPOL CCRP Int. Flag TnPF No CCRP Interrupts generated CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Output Inverts when TnPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA match 2. CCRP is not used 3. Pulse triggered by TCK1 pin or setting T1ON bit high 4. TCK1 pin active edge will auto set T1ON bit 5. n=1 Rev. 1.00 79 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU However a compare match from Comparator A will also automatically clear the T1ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the T1ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Capture Input Mode To select this mode bits T1M1 and T1M0 in the TM1C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TP1_0 or TP1_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the T1IO1 and T1IO0 bits in the TM1C1 register. The counter is started when the T1ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TP1_0 or TP1_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TP1_0 or TP1_1 pin the counter will continue to free run until the T1ON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The T1IO1 and T1IO0 bits can select the active trigger edge on the TP1_0 or TP1_1 pin to be a rising edge, falling edge or both edge types. If the T1IO1 and T1IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TP1_0 or TP1_1 pin, however it must be noted that the counter will continue to run. As the TP1_0 or TP1_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The T1CCLR and T1DPX bits are not used in this Mode. Rev. 1.00 80 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Counter Value TnM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time TnON TnPAU TM capture pin TPn_x Active edge Active edge Active edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX YY 10 – Both edges 11 – Disable Capture Capture Input Mode Note: 1. T1M1, T1M0=01 and active edge set by T1IO1 and T1IO0 bits 2. TM Capture input pin active edge transfers counter value to CCRA 3. T1CCLR bit not used 4. No output function – T1OC and T1POL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. 6. n=1 Rev. 1.00 81 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 10-bit digital value. Input Channels A/D Channel Select Bits Input Pins 4 ACS4, ACS2~ACS0 AN0~AN3 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the ADC data 10-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ADRL(ADRFS=0) D1 D0 — — — — — Bit0 — ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=0) D9 D8 D7 D6 D5 D4 D3 D2 ADRH(ADRFS=1) — — — — — — D9 D8 ADCR0 START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 ADCR1 ACS4 V125EN OPAEN VREFS — ADCK2 ADCK1 ADCK0 ACERL — — ACE3 ACE2 ACE1 ACE0 — — VDD fSYS ACE3~ACE0 ADCK2~ADCK0 ÷ 2N (N=0~6) A/D Clock PA3/AN3 PA1/AN1 PA0/AN0 PA2/AN2/OPA+ ADOFF Bit VREFS Bit A/D Reference Voltage ADRL A/D Converter OPA ×4 ADRH VSS ACS4, ACS2~ACS0 OPAEN Bit PA0/AN0 A/D Data Registers ADRFS bit START EOCB ADOFF 1.25V V125EN A/D Converter Structure Rev. 1.00 82 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU A/D Converter Data Registers – ADRL, ADRH As the device contains an internal 10-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 10 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D9 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS ADRH ADRL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1, ACERL are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter. It is the function of the ACS4, ACS2~ACS0 bits to determine which analog channel input pins or internal 1.25V or OPA output is actually connected to the internal A/D converter. The ACERL control register contains the ACE3~ACE0 bits which determine which pins on Port A are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. Rev. 1.00 83 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU ADCR0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7 START: Start the A/D conversion 0-->1-->0 : start 0-->1 : reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. Bit 5 ADOFF: ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4 ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 6 1: ADC Data MSB is ADRH bit 1, LSB is ADRL bit 0 This bit controls the format of the 10-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3 Unimplemented, read as "0" Bit 2~0 ACS2~ACS0: Select A/D channel (when ACS4 is "0") 000: AN0 001: AN1 010: AN2 011: AN3 100: OPA output signal other: connect to VSS These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/D Converter. 84 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU ADCR1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name ACS4 V125EN OPAEN R/W R/W R/W R/W VREFS — ADCK2 ADCK1 ADCK0 R/W — R/W R/W POR 0 0 0 R/W 0 — 0 0 0 Bit 7 ACS4: Select Internal 1.25V as ADC input Control 0: disable 1: enable This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6 V125EN: Internal 1.25V Control 0: disable 1: enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. When 1.25V is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5 OPAEN: Internal OPA Control 0: disable 1: enable This bit controls the internal OPA on/off function to the A/D converter. When the bit is set high the OPA output can be used by the A/D converter and the OPA input pin OPA+ is as analog input. The OPA output voltage is 4 times the OPA input. When OPAEN is low, the OPA circuit will not consume power. Bit 4 VREFS: Select ADC reference voltage 0: internal ADC power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low then the internal reference is used which is taken from the power supply pin VDD. Bit 3 Unimplemented, read as "0" Bit 2~0 ADCK2~ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: undefined These three bits are used to select the clock source for the A/D converter. 85 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU ACERL Register Bit 7 6 5 4 3 2 1 0 Name — — — — ACE3 ACE2 ACE1 ACE0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as "0" Bit 3 ACE3: Define PA3 is A/D input or not 0: not A/D input 1: A/D input, AN3 Bit 2 ACE2: Define PA2 is A/D input or not 0: not A/D input 1: A/D input, AN2 Bit 1 ACE1: Define PA1 is A/D input or not 0: not A/D input 1: A/D input, AN1 Bit 0 ACE0: Define PA0 is A/D input or not 0: not A/D input 1: A/D input, AN0 A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tADCK, is 0.5µs, care must be taken for system clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to “000”. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Rev. 1.00 86 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE3~ACE0 bits in the ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other functions. The ACE3~ACE0 bits in the ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE3~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable the A/D input as when the ACE3~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. A/D Input Structure Rev. 1.00 87 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4, ACS2~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE3~ACE0 bits in the ACERL registers. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. A/D Conversion Timing Rev. 1.00 88 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the device contains a 10-bit A/D converter, its full-scale converted digitised value is equal to 3FFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of VDD or VREF divided by 1024. 1LSB=(VDD or VREF)/1024 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value×(VDD or VREF)/1024 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5LSB below the VDD or VREF level. Ideal A/D Transfer Function Rev. 1.00 89 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.25V clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL,a mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : : jmp start_conversion;start next a/d conversion Rev. 1.00 90 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.25V clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL,a mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a; save STATUS to user defined memory : : mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.00 91 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Operational Amplifier – OPA The device includes an internal OPA with a fixed gain of four times. The output can be connected to the A/D converter or to the negative input of the comparator CMP0. Operational Amplifier Registers The internal Operational Amplifier is fully under the control of internal registers, ADCR0, ADCR1, CP0C and OPAC. These registers control the input path selection, enable/disable function and calibration function. Operational Amplifier Operation When the ACS2~ACS0 bits in the ADCR0 register in the A/D converter are set to 100B, then the OPA output will be selected as A/D converter input. The OPAEN bit in the ADCR1 register is used as the enable/disable bit for the Operational Amplifier. When the bit is set high the OPA output is used by the A/D converter and the OPA input pin OPA+ is as analog input. The OPA output voltage is 4 times of the OPA input. When the OPAEN is low, the OPA is disabled and powered off to reduce power consumption. The C0NOPA bit in the CP0C register is used as the enable/disable bit for OPA output to connect to C0-.when the bit is set high, the OPA output can be connected to C0-. ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7~3 Bit 2~0 A/D Converter related registers, described elsewhere ACS2~ACS0: Select A/D channel (when ACS4 is "0") 000: AN0 001: AN1 010: AN2 011: AN3 100: OPA output signal other: connect to VSS ADCR1 Register Bit 7 6 5 4 3 2 1 0 Name ACS4 V125EN OPAEN VREFS — ADCK2 ADCK1 ADCK0 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 0 0 — 0 0 0 Bit 7,6,4~0 A/D Converter related registers, described elsewhere Bit 5 OPAEN: Internal OPA Control 0: disable 1: enable This bit controls the internal OPA on/off function to the A/D converter. When the bit is set high the OPA output can be used by the A/D converter and the OPA input pin OPA+ is as analog input. The OPA output voltage is 4 times of the OPA input. When the OPAEN is low, the OPA circuit will not consume power. Rev. 1.00 92 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CP0C Register Bit 7 6 5 4 3 Name C0PSEL C0EN C0POL C0OUT C0OS 2 1 0 R/W R/W R/W R/W R R/W R/W R/W R/W POR 1 0 0 0 1 0 1 1 C0NOPA C0NSEL0 C0HYEN Bit 7~3 Comparator related registers, described elsewhere Bit 2 C0NOPA: OPA output enable or disable connect to Comparator0 negative input 0: disable 1: enable Bit 1~0 Comparator related registers, described elsewhere OPAC Register Bit 7 6 5 4 3 2 1 0 Name OPAOP AOFM ARS AOF4 AOF3 AOF2 AOF1 AOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 OPAOP: Operational amplifier output; positive logic. This bit is read only. Bit 6 AOFM: Input offset voltage cancellation mode and operational amplifier mode selection 0: input offset voltage operational amplifier mode 1: input offset voltage cancellation mode Bit 5 ARS: Operational amplifier input offset voltage cancellation reference selection bit 0: select OPA negative input as the reference input 1: select OPA positive input as the reference input Bit 4~0 AOF4~AOF0: Operational amplifier input offset voltage cancellation control bits Operational Amplifier Offset Cancellation function OPA allows for a commode mode adjustment method of its input offset voltage. ARS AOFM S1 S2 S3 OFF 0 0 ON ON 0 1 OFF ON ON 1 0 ON ON OFF 1 1 ON OFF ON The calibration steps are as following: • • • • Rev. 1.00 Set AOFM=1 to setup the offset cancellation mode, here S3 is closed Set ARS to select which input pin is to be used as the reference voltage – S1 or S2 is closed Adjust AOF0~AOF3 until the output status changes Set AOFM=0 to restore the normal OPA mode 93 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Comparators Four comparators are contained within this device. These comparators are controlled by the registers, CP0C, CP1C, CP2C and CP3C, offering the flexible features, such as power-down, polarity selection, hysteresis selection etc. The comparators I/Os are pin-shared with the other pins. If the comparator function is not selected, the designer can assign the corresponding I/O pins to the other functions. C0POL C0+ 8-bit DAC + Comparator 0 - C0OPA output C0X C0SEL C1POL C1+ C0OUT + Comparator 1 - C1OUT C1X C1SEL C1C2POL C2+ + Comparator 2 - C2- C2OUT C2X C2SEL C1C3POL C3+ + Comparator 3 - C3- C3OUT C3X C3SEL C1- Comparator Operation The device contains four comparators which are used to compare input signals and to provide an output based on their difference. These four internal comparators are fully controlled by the control registers, CP0C~CP3C. The comparator output can be read by a bit, namely CnOUT, in the corresponding control registers and can be transferred out to an I/O pin as well. In addition, the output polarity, hysteresis and power down functions are included in these comparators. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level; however, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value. The comparators have their own interrupt which is described in the interrupt section. Rev. 1.00 94 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Comparator Registers There are four registers, CP0C~CP3C, to manage the overall comparator operations. The control registers are summarised in the following table. Name Bit7 Bit6 Bit5 Bit4 Bit3 CP0C C0PSEL C0EN C0POL C0OUT C0OS Bit2 Bit1 Bit0 CP1C C1PSEL C1EN C1POL C1OUT C1OS CP2C C2PSEL C2EN C2POL C2OUT C2OS C2NSEL1 C2NSEL0 C2HYEN CP3C C3PSEL C3EN C3POL C3OUT C3OS C3NSEL1 C3NSEL0 C3HYEN C0NOPA C0NSEL0 C0HYEN — C1NSEL0 C1HYEN Comparator Registers List CP0C Register Rev. 1.00 Bit 7 6 5 4 3 Name C0PSEL C0EN C0POL C0OUT C0OS 2 1 0 R/W R/W R/W R/W R R/W R/W R/W R/W POR 1 0 0 0 1 0 1 1 C0NOPA C0NSEL0 C0HYEN Bit 7 C0PSEL: Comparator 0 positive input pin selection 0: not select 1: select If the bit is set high, the Comparator 0 positive input pin will be enabled and the I/O pin function will be disabled. No matter comparator 0 positive input pin is selected or not, C0+ can be connected to 8-bit DAC. Bit 6 C0EN: Comparator 0 enable/disable control 0: disable 1: enable This is the Comparator 0 enable/disable control bit. If the bit is cleared to zero, the comparator 0 will be disabled to reduce the power consumption. For power sensitive applications, this bit should be cleared to zero before the device enters the Power-down mode. Bit 5 C0POL: Comparator 0 output polarity control 0: output not inverted 1: output inverted This is the comparator 0 polarity control bit. If the bit is cleared to zero, then the C0OUT bit will reflect the non-inverted output condition of the comparator 0. If the bit is set to high, the comparator 0 C0OUT bit will be inverted. Bit 4 C0OUT: Comparator 0 output bit C0POL=0 0: C0+<C0- 1: C0+>C0- C0POL=1 0: C0+>C0- 1: C0+<C0This bit indicates the comparator 0 output status. The polarity of the bit is determined by the comparator 0 inputs and the C0POL bit. Bit 3 C0OS: Output path select 0: C0X pin 1: internal use This is the comparator 0 output path control bit. If the bit is set to “0”, the comparator output is connected to an external C0X pin. If this bit is set to high, the comparator 0 output is for internal use only. The shared pin is now used as the other functions. 95 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 2 C0NOPA: OPA output connects to comparator 0 negative input control bit 0: disable 1: enable Bit 1 C0NSEL: Select Comparator 0 negative input pin or not 0: not select 1: select This is the Comparator 0 pin selection.If the bit is set to high, the Comparator 0 negative input pin will be enabled. As a result, the pin will disable the I/O pin functions. No matter the comparator 0 negative input pin is selected or not, the C0- can be connected to OPA output. Bit 0 C0HYEN: Hysteresis Control 0: disable 1: enable This is the hysteresis control bit and if this bit is set high, it will apply a limited amount of hysteresis to the comparator 0, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. CP1C Register Rev. 1.00 Bit 7 6 5 4 3 2 Name C1PSEL C1EN C1POL C1OUT C1OS — 1 0 R/W R/W R/W R/W R R/W — R/W R/W POR 1 0 0 0 1 — 1 1 C1NSEL0 C1HYEN Bit 7 C1PSEL: Comparator 1 positive input pin selection 0: not select 1: select If the bit is set high, the Comparator 1 positive input pin will be enabled and the I/O pin function will be disabled. Bit 6 C1EN: Comparator 1 enable/disable control 0: disable 1: enable This is the Comparator 1 enable/disable control bit. If the bit is cleared to zero, the comparator 1 will be disabled to reduce the power consumption. For power sensitive applications, this bit should be cleared to zero before the device enters the Power-down mode. Bit 5 C1POL: Comparator 1 output polarity control 0: output not inverted 1: output inverted This is the comparator 1 polarity control bit. If the bit is cleared to zero, then the C1OUT bit will reflect the non-inverted output condition of the comparator 1. If the bit is set to high, the comparator 1 C1OUT bit will be inverted. Bit 4 C1OUT: Comparator 1 output bit C1POL=0 0: C1+<C1- 1: C1+>C1- C1POL=1 0: C1+>C1- 1: C1+<C1This bit indicates the comparator 1 output status. The polarity of the bit is determined by the comparator 1 inputs and the C1POL bit. 96 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 3 C1OS: Output path select 0: C1X pin 1: internal use This is the comparator 1 output path control bit. If the bit is set to “0”, the comparator output is connected to an external C1X pin. If this bit is set to high, the comparator 1 output is for internal use only. The shared pin is now used as the other functions. Bit 2 Unimplemented, read as “0” Bit 1 C1NSEL: Select Comparator 1 negative input pin or not 0: not select 1: select This is the Comparator 1 pin selection. If the bit is set to high, the Comparator 1 negative input pin will be enabled. As a result, the pin will disable the I/O pin functions. No matter whether the comparator 1 negative input pin is selected or not, C1- can be connected to 8-bit DAC. Bit 0 C1HYEN: Hysteresis Control 0: disable 1: enable This is the hysteresis control bit. Setting this bit high will apply a limited amount of hysteresis to the comparator 1, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator 1 threshold. CP2C Register Rev. 1.00 Bit 7 6 5 4 3 Name C2PSEL C2EN C2POL C2OUT C2OS 2 1 0 R/W R/W R/W R/W R R/W R/W R/W R/W POR 1 0 0 0 1 0 1 1 C2NSEL1 C2NSEL0 C2HYEN Bit 7 C2PSEL: Comparator 2 positive input pin selection 0: not select 1: select If the bit is set high, the Comparator 2 positive input pin will be enabled and the I/O pin function will be disabled. Bit 6 C2EN: Comparator 2 enable/disable control 0: disable 1: enable This is the Comparator 2 enable/disable control bit. If the bit is cleared to zero, the comparator 2 will be disabled to reduce the power consumption. For power sensitive applications, this bit should be cleared to zero before the device enters the Power-down mode. Bit 5 C2POL: Comparator 2 output polarity control 0: output not inverted 1: output inverted This is the comparator 2 polarity control bit. If the bit is cleared to zero, then the C2OUT bit will reflect the non-inverted output condition of the comparator 2. If the bit is set to high, the comparator 2 C2OUT bit will be inverted. Bit 4 C2OUT: Comparator 2 output bit C2POL=0 0: C2+<C2- 1: C2+>C2- C2POL=1 0: C2+>C2- 1: C2+<C297 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU This bit indicates the comparator 2 output status. The polarity of the bit is determined by the comparator 2 inputs and the C2POL bit. Bit 3 C2OS: Output path select 0: C2X pin 1: internal use This is the comparator 2 output path control bit. If the bit is set to “0”, the comparator output is connected to an external C2X pin. If this bit is set to high, the comparator 2 output is for internal use only. The shared pin is now used as the other functions. Bit 2~1 C2NSEL1~C2NSEL0: Select Comparator 2 negative input pin or not 00: Comparator 2 negative input pin and Comparator 1 negative input pin not select 01: Comparator 2 negative input pin select 10: Comparator 1 negative input pin select 11: Comparator 2 negative input pin and Comparator 1 negative input pin not select These are the Comparator 2 pin select bits.If the C2NSEL1 bit is set to “0”, the C2NSEL0 bit is set to “1”, the Comparator 2 negative input pin will be enabled. As a result, the pin will disable the I/O pin function. If the C2NSEL1 bit is set to “1” and the C2NSEL0 bit is set to “0”, the Comparator 1 negative input pin will be enabled. As a result, the pin will disable the I/O pin function. No matter whether the comparator 2 negative input pin is selected or not, C2- can be connected to 8-bit DAC. Bit 0 C2HYEN: Hysteresis Control 0: disable 1: enable This is the hysteresis control bit and if this bit is set high, it will apply a limited amount of hysteresis to the comparator 2, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. CP3C Register Rev. 1.00 Bit 7 6 5 4 3 Name C3PSEL C3EN C3POL C3OUT C3OS 2 1 0 R/W R/W R/W R/W R R/W R/W R/W R/W POR 1 0 0 0 1 0 1 1 C3NSEL1 C3NSEL0 C3HYEN Bit 7 C3PSEL: Comparator 3 positive input pin selection 0: not select 1: select If the bit is set high, the Comparator 3 positive input pin will be enabled and the I/O pin function will be disabled. Bit 6 C3EN: Comparator 3 enable/disable control 0: disable 1: enable This is the Comparator 3 enable/disable control bit. If the bit is cleared to zero, the comparator 3 will be disabled to reduce the power consumption. For power sensitive applications, this bit should be cleared to zero before the device enters the Power-down mode. Bit 5 C3POL: Comparator 3 output polarity control 0: output not inverted 1: output inverted This is the comparator 3 polarity control bit. If the bit is cleared to zero, then the C3OUT bit will reflect the non-inverted output condition of the comparator 3. If the bit is set to high, the comparator 3 C3OUT bit will be inverted. 98 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 4 C3OUT: Comparator 3 output bit C3POL=0 0: C3+<C3- 1: C3+>C3- C3POL=1 0: C3+>C3- 1: C3+<C3This bit indicates the comparator 3 output status. The polarity of the bit is determined by the comparator 3 inputs and the C3POL bit. Bit 3 C3OS: Output path select 0: C3X pin 1: internal use This is the comparator 3 output path control bit. If the bit is set to “0”, the comparator output is connected to an external C3X pin. If this bit is set to high, the comparator 3 output is for internal use only. The shared pin is now used as the other functions. Bit 2~1 C3NSEL1~C3NSEL0: Select Comparator 3 negative input pin or not 00: Comparator 3 negative input pin and Comparator 1 negative input pin not select 01: Comparator 3 negative input pin select 10: Comparator 1 negative input pin select 11: Comparator 3 negative input pin and Comparator 1 negative input pin not select These are the Comparator 3 pin select bits. If the C3NSEL1 bit is set to “0”, the C3NSEL0 bit is set to “1”, the Comparator 3 negative input pin will be enabled. As a result, the pin will disable the I/O pin functions. If the C3NSEL1 bit is set to “1” and the C3NSEL0 bit is set to “0”, the Comparator 3 negative input pin will be enabled. As a result, the pin will disable the I/O pin functions. No matter the comparator 3 negative input pin is selected or not, the C3- can be connected to 8-bit DAC. Bit 0 C3HYEN: Hysteresis Control 0: disable 1: enable This is the hysteresis control bit and if this bit is set high, it will apply a limited amount of hysteresis to the comparator 3, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Comparator Interrupt Each comparator also possesses its own interrupt function. When any one of the comparators change state, their relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the CnOUT bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins, the I/O registers for these pins will be read as zero (port control register is “1”) or will read as port data register value (port control register is “0”) if the comparator function is enabled. Rev. 1.00 99 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Digital to Analog Converter – DAC The device contains an internal 8-bit Digital to Analog Converter function. The DAC output can be connected to the Comparator 0 positive input or the Comparator 1, 2, 3 negative inputs. The DAC reference voltage, VREF, can be selected from VDD or the internal 1.25V reference. DAC control The internal register DAC contains the 8-bit digital value for conversion by the internal DAC. There is also a DAC enable/disable control bit in the DACC control register for overall on/off control of the DAC circuit. If the DAC circuit is not enabled, the the DAC value outputs will be invalid. Writing a “1” to the DACON bit in bit7 of DACC will enable the enable DAC circuit, while writing a “0” to the DACON bit will disable the DAC circuit and will reduce the power consumption. DAC Register Description DAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 DAC Data Register bit 7~bit 0 DAC Output=VDD×(DAC.7~0)/256 or 1.25×(DAC.7~0)/256 DACC Register Bit Name Rev. 1.00 7 6 DACON DACVREF 5 4 3 2 1 0 DAC0P DAC1N DAC2N DAC3N — — R/W R/W R/W R/W R/W R/W R/W — — POR 0 0 0 0 0 0 — — Bit 7 DACON: DAC On/Off Control 0: DAC off to reduce power consumption 1: DAC on. Bit 6 DACVREF: Select VDD or Internal 1.25V as DAC reference voltage 0: VDD 1: internal 1.25V reference voltage Bit 5 DAC0P: DAC output enable or disable connect to comparator 0 positive input 0: disable 1: enable Bit 4 DAC1N: DAC output enable or disable connect to comparator 1 negative input 0: disable 1: enable Bit 3 DAC2N: DAC output enable or disable connect to comparator 2 negative input 0: disable 1: enable Bit 2 DAC3N: DAC output enable or disable connect to comparator 3 negative input 0: disable 1: enable Bit 1~0 Unimplemented, read as "0" 100 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four line SPI interface or the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM pins are pin-shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by setting the correct bits in the SIMC0 and SIMC2 registers. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to “1” enable SCS pin function, set CSEN bit to “0” the SCS pin will be as I/O function. SPI Master/Slave Connection The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge Rev. 1.00 101 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF 0 SPI Register List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×” unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. Rev. 1.00 102 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: unused These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: disable 1: enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 unimplemented, read as “0” 103 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SIMC2 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bit This bit can be read or written by user software program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive.The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin Control 0: disable 1: enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI Write Collision flag 0: no collision 1: collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Bit 0 TRF: SPI Transmit/Receive Complete flag 0: data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set “1” automatically when an SPI data transmission is completed, but must set to “0” by the application program. It can be used to generate an interrupt. 104 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.00 105 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.00 106 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. I2C Block Diagram Rev. 1.00 107 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r I2C Registers There are four control registers associated with the I2C bus, SIMC0, SIMC1, SIMA and I2CTOC and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. The SIM pins are pin-shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 I2CTOC I2CTOEN I2CTOF I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 I2C Register List Rev. 1.00 108 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control described elsewhere Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency described elsewhere Bit 1 SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 unimplemented, read as “0” 109 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SIMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I C Bus data transfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: not address match 1: address match The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to “0” when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: Select I2C slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: slave send acknowledge flag 1: slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to “0” before further data is received. Bit 2 SRW: I2C Slave Read/Write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C address match wake-up control 0: disable 1: enable This bit should be set to “1” to enable I2C address match wake-up from SLEEP or IDLE Mode. 2 110 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU RXAK: I2C Bus Receive acknowledge flag 0: slave receive acknowledge flag 1: slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. Bit 0 I2CTOC Register Bit 7 6 Name I2CTOEN I2CTOF 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 Bit 7 I2CTOEN: I2C Time-out Control 0: disable 1: enable Bit 6 I2CTOF: Time-out flag 0: no time-out 1: time-out occurred Bit 5~0 I2CTOS5~I2CTOS0: Time-out Time Definition I2C time-out clock source is fLIRC/32 I2C Time-out time is given by: ([I2CTOS5:I2CTOS0]+1)×(32/fLIRC) The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×” unknown Rev. 1.00 111 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×” unknown Bit 7~1 IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6~bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to “1” to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. Rev. 1.00 112 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram Rev. 1.00 113 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will informthe master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to “0”. I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Rev. 1.00 114 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I2C Bus ISR Flow Chart Rev. 1.00 115 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU I2C Time-out Control In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, clock, a time-out function is provided. If the clock source to the I2C is not received then after a fixed time period, the I2C circuitry and registers will be reset. The time-out counter starts counting on an I2C bus “START” & “address match” condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the I2CTOC register, then a time-out condition will occur. The time-out function will stop when an I2C “STOP” condition occurs. S C L S ta rt S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 A C K 1 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and I2CTOEN bit will be cleared to zero and the I2CTF bit will be set high to indicate that a time-out condition as occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector. When an I2C time-out occurs the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMDR, SIMAR, SIMC0 No change SIMC1 Reset to POR condition I C Registers After Time-out 2 The I2CTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using bits in the I2CTOC register. The time-out time is given by the formula: ((1~64)×32)/fLIRC. This gives a range of about 1ms to 64ms. Note also that the LIRC oscillator is continuously enabled. Rev. 1.00 116 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to “1” enables the Peripheral Clock, setting PCKEN bit to “0” disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 Name SIM2 SIM1 SIM0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — PCKEN PCKPSC1 PCKPSC0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control described elsewhere Bit 4 PCKEN: PCK Output Pin Control 0: disable 1: enable Bit 3~2 PCKPSC1, PCKPSC0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control described elsewhere Bit 0 unimplemented, read as “0” 117 1 0 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupts and internal interrupts functions. The external interrupts are generated by the action of the external INT0A, INT0B, INT0C, INT1 and INT2 pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators, Time Base, LVD, EEPROM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable disable bit or “F” for request flag. Function Enable Bit Request Flag Global EMI INTn Pin INTnE INTnF HALL HALLE HALLF Comparator CPnE CPnF A/D Converter PWM Notes — ADE ADF PWMOVIE PWMOVIF PWMBKIE PWMBKIF PWMDE PWMDF — n=1 or 2 — n=0~3 — — PWMPE PWMPF Multi-function MFnE MFnF n=0~2 Time Base TBnE TBnF n=0 or 1 LVD LVE LVF — EEPROM DEE DEF — CAPTOE CAPTOF CAPTME CAPTMF CAPTIE CAPTIF TnPE TnPF TnAE TnAF SIME SIMF Capture Timer TM SIM — n=0~1 — Interrupt Register Bit Naming Conventions Rev. 1.00 118 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Interrupt Register Contents Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTEG — — — — INT2S1 INT2S0 INT1S1 INT1S0 INTC0 — CAPTIF INT1F HALLF CAPTIE INT1E HALLE EMI INTC1 CP3F CP2F CP1F CP0F CP3E CP2E CP1E CP0E INTC2 PWMOVIF PWMBKIF CAPTMF INTC3 MF2F CAPTOF MFI0 T1AF T1PF MFI1 SIMF TB0F MFI2 INT2F DEF LVF 6 5 ADF PWMOVIE PWMBKIE CAPTME MF0F MF2E CAPTOE T0AF T0PF T1AE T1PE T0AE T0PE SIME TB0E PWMDE PWMPE INT2E DEE LVE TB1E PWMDF PWMPF TB1F MF1E ADE MF1F MF0E INTEG Register Bit Rev. 1.00 7 4 3 2 1 0 Name — — — — INT2S1 INT2S0 INT1S1 INT1S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2 INT2S1, INT2S0: Defines INT2 interrupt active edge 00: disabled Interrupt 01: rising Edge Interrupt 10: falling Edge Interrupt 11: dual Edge Interrupt Bit 1~0 INT1S1, INT1S0: Defines INT1 interrupt active edge 00: disabled Interrupt 01: rising Edge Interrupt 10: falling Edge Interrupt 11: dual Edge Interrupt 119 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU INTC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 Name — CAPTIF INT1F HALLF CAPTIE INT1E HALLE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 CAPTIF: Capture Timer capture Interrupt Request Flag 0: no request 1: interrupt request Bit 5 INT1F: INT1 Interrupt Request Flag 0: no request 1: interrupt request Bit 4 HALLF: HALL Interrupt Request Flag 0: no request 1: interrupt request Bit 3 CAPTIE: Capture Timer capture Interrupt Control 0: disable 1: enable Bit 2 INT1E: INT1 Interrupt Control 0: disable 1: enable Bit 1 HALLE: HALL Interrupt Control 0: disable 1: enable Bit 0 EMI: Global Interrupt Control 0: disable 1: enable 120 0 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU INTC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name CP3F CP2F CP1F CP0F CP3E CP2E CP1E CP0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CP3F: Comparator 3 Interrupt Request Flag 0: no request 1: interrupt request Bit 6 CP2F: Comparator 2 Interrupt Request Flag 0: no request 1: interrupt request Bit 5 CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 4 CP0F: Comparator 0 Interrupt Request Flag 0: no request 1: interrupt request Bit 3 CP3E: Comparator 3 Interrupt Control 0: disable 1: enable Bit 2 CP2E: Comparator 2 Interrupt Control 0: disable 1: enable Bit 1 CP1E: Comparator 1 Interrupt Control 0: disable 1: enable Bit 0 CP0E: Comparator 0 Interrupt Control 0: disable 1: enable 121 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU INTC2 Register Bit Name Rev. 1.00 7 6 5 4 PWMOVIF PWMBKIF CAPTMF ADF 3 2 1 PWMOVIE PWMBKIE CAPTME 0 ADE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 PWMOVIF: PWM Over current Interrupt Request Flag 0: no request 1: interrupt request Bit 6 PWMBKIF: PWM Brake Interrupt Request Flag 0: no request 1: interrupt request Bit 5 CAPTMF: Capture Timer Compare match Interrupt Request Flag 0: no request 1: interrupt request Bit 4 ADF : A/D Converter Interrupt Request Flag 0: no request 1: interrupt request Bit 3 PWMOVIE: PWM Over current Interrupt Control 0: disable 1: enable Bit 2 PWMBKIE: PWM Brake Interrupt Control 0: disable 1: enable Bit 1 CAPTME: Capture Timer Compare match Interrupt Control 0: disable 1: enable Bit 0 ADE: A/D Converter Interrupt Control 0: disable 1: enable 122 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU INTC3 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name MF2F CAPTOF MF1F MF0F MF2E CAPTOE MF1E MF0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request Bit 6 CAPTOF: Capture Timer counter overflow Interrupt Request Flag 0: no request 1: interrupt request Bit 5 MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request Bit 4 MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request Bit 3 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable Bit 2 CAPTOE: Capture Timer counter overflow Interrupt Control 0: disable 1: enable Bit 1 MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable Bit 0 MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable 123 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU MFI0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name T1AF T1PF T0AF T0PF T1AE T1PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T1AF: TM1 Comparator A Match Interrupt Request Flag 0: no request 1: interrupt request Bit 6 T1PF: TM1 Comparator P Match Interrupt Request Flag 0: no request 1: interrupt request Bit 5 T0AF: TM0 Comparator A Match Interrupt Request Flag 0: no request 1: interrupt request Bit 4 T0PF: TM0 Comparator P Match Interrupt Request Flag 0: no request 1: interrupt request Bit 3 T1AE: TM1 Comparator A Match Interrupt Control 0: disable 1: enable Bit 2 T1PE: TM1 Comparator P Match Interrupt Control 0: disable 1: enable Bit 1 T0AE: TM0 Comparator A Match Interrupt Control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P Match Interrupt Control 0: disable 1: enable 124 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU MFI1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIMF TB0F PWMDF PWMPF SIME TB0E PWMDE PWMPE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SIMF: SIM interrupt request flag 0: no request 1: interrupt request Bit 6 TB0F: Time Base 0 Interrupt Request Flag 0: no request 1: interrupt request Bit 5 PWMDF: PWM Duty Interrupt Request Flag 0: no request 1: interrupt request Bit 4 PWMPF: PWM Period Interrupt Request Flag 0: no request 1: interrupt request Bit 3 SIME: SIM Interrupt Control 0: disable 1: enable Bit 2 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable Bit 1 PWMDE: PWM Duty Interrupt Control 0: disable 1: enable Bit 0 PWMPE: PWM Period Interrupt Control 0: disable 1: enable 125 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU MFI2 Register Rev. 1.00 Bit 7 6 5 4 3 2 Name INT2F R/W R/W POR 0 DEF LVF TB1F INT2E R/W R/W R/W R/W 0 0 0 0 Bit 7 INT2F: INT2 Interrupt Request Flag 0: no request 1: interrupt request Bit 6 DEF: Data EEPROM Interrupt Request Flag 0: no request 1: interrupt request Bit 5 LVF: LVD Interrupt Request Flag 0: no request 1: interrupt request Bit 4 TB1F: Time Base 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 3 INT2E: INT2 Interrupt Control 0: disable 1: enable Bit 2 DEE: Data EEPROM Interrupt Control 0: disable 1: enable Bit 1 LVE: LVD Interrupt Control 0: disable 1: enable Bit 0 TB1E: Time Base 1 Interrupt Control 0: disable 1: enable 126 1 0 DEE LVE TB1E R/W R/W R/W 0 0 0 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.00 127 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU EMI auto disabled in ISR Interrupt Name Legend xxF Request Flag – no auto reset in ISR xxF Request Flag – auto reset in ISR xxE Enable Bit Interrupt Name Request Flags Enable Bits Request Flags Enable Bits Master Enable HALL HALLF HALLE EMI 04H INT1 Pin INT1F INT1E EMI 08H CAPTIE EMI 0CH CP0E EMI 10H Capture Timer CAPTIF capture Vector Comp. 0 CP0F Comp. 1 CP1F CP1E EMI 14H Comp. 2 CP2F CP2E EMI 18H Comp. 3 CP3F CP3E EMI 1CH A/D ADE EMI 20H CAPTME EMI 24H PWM Break PWMBKIF PWMBKIE EMI 28H PWM Over current PWMOVIF PWMOVIE EMI 2CH ADF Capture Timer compare match CAPTMF TM0 P T0PF T0PE TM0 A T0AF T0AE TM1 P T1PF T1PE TM1 A T1AF T1AE M.Funct.0 MF0F MF0E EMI 30H PWMPE M.Funct.1 MF1F MF1E EMI 34H CAPTOE EMI 38H MF2E EMI 3CH PWM Period PWMPF PWM Duty PWMDF PWMDE Time Base 0 TB0F TB0E SIMF SIME SIM Time Base 1 TB1F INT2 Pin LVD EEPROM INT2F Cap.Timer Overflow CAPTOF M. Funct. 2 MF2F Priority High TB1E INT2E LVF LVE DEF DEE Low Interrupts contained within Multi-Function Interrupts Interrupt Structure Rev. 1.00 128 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU HALL Interrupt The HALL interrupt is controlled by signal transitions on the HALL input. An HALL interrupt request will take place when the HALL interrupt request flag, namely HALLF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the HALL inputs. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bits, HALLE and the HALLnE bits in the HALLC register, must first be set. When the HALL interrupt is enabled, the stack is not full and the correct transition type appears on the external HALL inputs, a subroutine call to the HALL interrupt vector, will take place. When the interrupt is serviced, the HALL interrupt request flag, namely HALLF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the HALL interrupt input pins will remain valid even if the pin is used as an HALL interrupt input pin. C1X INT0A C2X INT0B C3X INT0C M U X Noise Filter Double Edge or Disable M U X Noise Filter Double Edge or Disable M U X Noise Filter Double Edge or Disable OR HALL Interrupt HALL0E ~ HALL2E bits Rev. 1.00 129 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU HALLC Register Bit 7 6 5 4 3 2 1 0 Name HALLDS HALL2E HALL1E HALL0E HALLNF HALLS2 HALLS1 HALLS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 HALLDS: Select HALLD Register Content source 0: HALLD bit 2~bit 0 are read only bits, representing the state of C3OUT, C2OUT, C1OUT 1: HALLD bit 2~bit 0 are read only bits, representing the state of INT0C, INT0B, INT0A pin Bit 6 HALL2E: HALL Interrupt Source 2 enable or disable 0: disable 1: enable If HALL2E is “1”, HALL interrupt will occur when INT0C or C3OUT has an active edge change. Bit 5 HALL1E: HALL Interrupt Source 1 enable or disable 0: disable 1: enable If HALL1E is “1”, HALL interrupt will occur when INT0B or C2OUT has an active edge change. Bit 4 HALL0E: HALL Interrupt Source 0 enable or disable 0: disable 1: enable If HALL0E is “1”, HALL interrupt will occur when INT0A or C1OUT has an active edge change. Bit 3 HALLNF: HALL Interrupt Noise Filters enable or disable 0: disable all HALL Interrupt Noise Filters 1: enable all HALL Interrupt Noise Filters Noise Filter time selection is the same as Noise Filter time selection of Capture Input. Bit 2 HALLS2: HALL Interrupt Source 2 selection 0: from C3OUT 1: from INT0C pin Bit 1 HALLS1: HALL Interrupt Source 1 selection 0: from C2OUT 1: from INT0B pin Bit 0 HALLS0: HALL Interrupt Source 0 selection 0: from C1OUT 1: from INT0A pin HALLD Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — D2 D1 D0 R/W — — — — — R R R POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2~0 HALL Interrupt data register bit 2~bit 0 HALL Interrupt data register bit 2~bit0 are read only bits, representing the state of C3OUT, C2OUT, C1OUT or representing the state of INT0C, INT0B, INT0A pin, decided by the HALLDS bit. 130 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU External Interrupt The external interrupts are controlled by signal transitions on the pins INT1, INT2. An external interrupt request will take place when the external interrupt request flags, INT1F, INT2F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT1E, INT2E, must first be set. Note that due to the INT2 is located in Multi-function Interrupt 2, therefore, the MF2E must also be set to enable the INT2 interrupt function. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt 1 request flag, INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that due to the INT2 is located in Multi-function interrupt, therefore, the INT2F will not be automatically reset and must be manually reset by the application program. Any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Capture Timer Module Interrupt The Capture Timer Module has three interrupts, including Capture Interrupt, Compare match interrupt and Capture counter overflow interrupt. These three Interrupts request will take place when the Capture Timer Module request flags, CAPTIF, CAPTMF, and CAPTOF are set. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective Capture Timer Module Interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and the capture blocks, Compare match or Capture counter overflow are triggered, a subroutine call to the relevant interrupt vector location, will take place. When the Capture Timer Module interrupt is serviced, the corresponding request flags will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.00 131 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Comparator Interrupt The comparator interrupt is controlled by the four internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F~CP3F, are set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bits, CP0E~CP3E, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the corresponding request flags will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Converter Interrupt This device contains an A/D converter which has its own independent interrupt. The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. PWM Automatic Brake Control Interrupt The PWM Automatic Brake Control has an interrupt, PWM Brake Interrupt. There is one interrupt request flag PWMBKIF and one enable bit PWMBKIE. A PWM Brake interrupt request will take place when the PWM Brake request flag is set, a situation which occurs when a PWM Brake situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective PWM Break Interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and a PWM Break situation occurs, a subroutine call to the relevant Interrupt vector locations, will take place. When the interrupt is serviced, the PWM Brake Interrupt flag, PWMBKIF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Over current Protection Interrupt The PWM Over Current Protection has an interrupt, PWM Over Current Interrupt. There is one interrupt request flag PWMOVIF and one enable bit PWMOVIE. A PWM Over Current request will take place when the PWM Over Current request flag is set, a situation which occurs when a PWM Over Current situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective PWM Over Current enable bit must first be set. When the interrupt is enabled, the stack is not full and a PWM Over Current occurs, a subroutine call to the relevant Interrupt vector locations, will take place. When the interrupt is serviced, the PWM Over Current Interrupt flag, PWMOVIF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.00 132 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Multi-function Interrupts Within the device there are some Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, PWM Period Interrupt, PWM Duty Interrupt, Time Base interrupts, SIM interrupt, LVD interrupt, EEPROM interrupt and External Interrupt 2 interrupt. A Multi-function interrupt request will take place when any of the Multi-function Interrupt request flags, MF0F~MF2F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, PWM Period Interrupt, PWM Duty Interrupt, Time Base interrupts, SIM interrupt, LVD interrupt, EEPROM interrupt and External Interrupt 2 interrupt, will not be automatically reset and must be manually reset by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MF0E, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector location, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MF0F flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. PWM Interrupt The PWM has two interrupts which are contained within the Multi-function Interrupts. There are two interrupt request flags, PWMDF and PWMPF, and two enable bits, PWMDE and PWMPE. A PWM interrupt request will take place when any of the PWM request flags are set, a situation which occurs when a PWM comparator Period or Duty match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective PWM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MF1E, must first be set. When the interrupt is enabled, the stack is not full and a PWM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the PWM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MF1F flag will be automatically cleared. As the PWM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.00 133 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F, will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI, Time Base enable bits, TB0E or TB1E, and associated Multi-function interrupt enable bit, MF1E or MF2E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective Multiple interrupt request flag, MF1F or MF2F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. Note that due to the Time Base interrupts are located in Multi-function interrupt, therefore, the TB0F and TB1F will not be automatically reset and must be manually reset by the application program. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. TBC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7 TBON: TB0 and TB1 Control bit 0: disable 1: enable Bit 6 TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3 Unimplemented, read as “0” Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB 134 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Time Base Interrupt • Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and the respective Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.00 135 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU EEPROM Interrupt The EEPROM interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF2F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 136 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0 are used to select one of three fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 LVDO: LVD Output Flag 0: no Low Voltage Detect 1: low Voltage Detect Bit 4 LVDEN: Low Voltage Detector Control 0: disable 1: enable Bit 3 Unimplemented, read as "0" Bit 2~0 VLVD2~VLVD0: LVD Voltage select bits 000~100: reserved 101: 3.3V 110: 3.6V 111: 4.2V 137 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with 3.3, 3.6 or 4.2V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.00 138 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Pulse Width Modulator This device is provided with a three-channel 12-bit PWM function. Each channel has a pair of Complementary PWM output. Useful for such applications such as motor speed control, the PWM function provides a flexible signal output with a selectable frequency and with a duty cycle that can be varied by setting particular 12-bit values into the corresponding PWM registers. The inclusion of Dead-Time insertion, Polarity setting control, Mask output control, PWM Period and Duty Interrupts and high driving current ability ensure that this device will find excellent use in the 3-Phase Brushless DC (BLDC) motor application area. PWM Clock Source The PWM clock, fPWM, is sourced from the system clock fSYS. It can be further subdivided using an internal divider to provide a frequency range from fSYS~fSYS/128 using the PWMCK0~PWMCK2 bits in the PWMC1 register. This clock source is used to drive an internal PWM 12-bit counter which is compared with the programmed PWM data value for period and duty cycle control. The following diagram illustrates the basic operation of the PWM. fSYS/1 PWM0H fSYS/2 fSYS/4 fSYS/8 fSYS/16 MUX fPWM PWM Generator fSYS/32 Complementary PWM and Dead Time Control PWM0L Mask Output Control Polarity Control PWM1H PWM1L PWM2H fSYS/64 PWM2L fSYS/128 PWMCK[2:0] PWMEN PWMCEN DTEN PnLMEN PnHMEN PnLP PnHP PWM Block Diagram Rev. 1.00 139 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWM Operation The following diagram illustrates the PWM generator basic functional block diagram. PWMP Register(new) PWM Period Interrupt PWMLD PWMLP Register(old) COMPARE fPWM PWM Counter (PWMD) Complementary PWM Dead Time Mask Polarity Control PWMnL PWMnH Counter Reset COMPARE PWM Register(old) PWM Duty Interrupt PWMLD PWM Register(new) The PWM function is managed by the control registers, namely PWMC0~PWMC6. The PWMON bit is used to control the PWM function enable or disable. The data in the PWMP register will be transferred to the 12-bit counter when the PWMON bit is set from low to high or the PWMLD and the counter experience a compare match. Note that if a compare value is greater than the counter reloaded value, then the PWM output will be permanently high. In addition there are two special cases. If the compare registers are set to 000H, the PWM output will remain low, and if the compare registers are set to FFFH, the PWM output will remain high until there is a change in the compare register. The data in the PWMP register is not directly written into the Counter register which controls the counter. The data is actually written first into a holding register. The data in the holding register will be transferred into the register which contains the actual reload value when the following conditions are met: PWMLD=1, PWMON=1 and a PWMP compare match. The width of each PWM output pulse is determined by the value in the appropriate compare register. Each PWM register pair, PWMPH, PWMPL and PWMH, PWML, is in a 12-bit width format by combining 4 LSBs in a high byte register and 8 bits in a low byte register to determine the PWM period and duty cycle. Note that the duty registers and period registers are double-buffered registers. They are used to set the duty cycle and to count the period for the PWM waveform respectively. The 1st buffer can be operated by the user and the 2nd buffer is used as the actual compare value in the current period. To set the load bit high will enable a transfer of data from the 1st buffer to the 2nd buffer when the counter underflows or experiences a match. Rev. 1.00 140 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU The following equations show the period and duty formulas for each PWM operation mode. • Period=(PWMP+1)×CPU clock period/pre-scaler In the PWM Output mode, the 12 bit counter will start counting from 0 until it matches the duty cycle PWM value. When the data experiences a match, it will toggle the PWM generator output to low. The counter will continue counting until it matches the value of the period register PWMP(old). Then it will toggle the PWM generator output to high. After that, the PWM(new) and PWMP(new) will be updated as PWMLD=1 and generate a PWM interrupt if the PWM interrupt is enabled. The following diagram illustrates the Edge-aligned PWM timing and operational flow. If 12-bit up counter matches PWMP 1. Update new duty cycle register (PWM0, 2, 4 and 6) if Load = 1 2. Update new PWMP period register (PWMP) if Load = 1 PWMP(new) PWMP(old) PWM0(new) PWM0(old) New Duty Cycle PWM0 generator ouput PWM period New PWM period New PWM0 is written New PWMP is written PWM PWMP(7FF) PWMP(3FF) PWMF s/w clear s/w clear s/w clear s/w clear s/w clear PWM generator ouput Edges to generate PWM interrupts PWM Period PWM Waveform Output Rev. 1.00 141 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWM Output Control There are a total of six PWM pins, divided into three pairs of complimentary PWM outputs. The PWM outputs are controlled using register bits. The PWM outputs can be either a single output, PWMH, or a complimentary pair of outputs, PWMnH and PWMnL. Both the PWMnH and PWMnL outputs can be set to be either active high or active low using software options. The PWM output ports will default to floating types after a reset. I/O Pin PWM Line PB3 PWM0H PB4 PWM0L PB5 or PA3 PWM1H PA4 PWM1L PA5 or PC2 PWM2H PA6 or PC3 PWM2L The PWMEN bit in the PWMC0 register acts as a master control bit for the PWM outputs. When this bit is high the selected PWM outputs will be active and when the bit is low all the PWM outputs will have other functions. The three PWM pins PWM0H, PWM1H and PWM2H have a control bit, PWMEN, and the complementary PWM pins, PWM0L, PWM1L and PWM2L, have a control bit, PWMCEN. When these bits are set to high their three corresponding PWM pins will be active, when the bits are cleared to zero their PWM pins will be set to the inactive state as defined by software options. As not all of the PWM may be required, the devices offer the flexibility to select which pins are used as PWM pins and which pins are used as I/O pins. This is determined either by bits in the PWMC1 and PWMC2 registers. The following table illustrates the PWM I/O selection. PWM0H, PWM1H, PWM2H selection table PWMEN PnHEN I/O or PWM 0 0 I/O 0 1 I/O 1 0 I/O 1 1 PWMnH PWMCEN PnLEN I/O or PWM 0 0 I/O 0 1 I/O 1 0 I/O 1 1 PWMnL PWM0L, PWM1L, PWM2L selection table Each PWM and complementary PWM has a corresponding control bit to select enable or disable. Rev. 1.00 142 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWM Dead Time Function The dead time generator inserts an “off” period, called “dead time”, between the “turning off” of one pin and the “turning on” of the complementary pin of the PWM paired pins. Each PWM output normally drives a pair of push-pull power transistors for load driving. The danger here is that for short periods of time, both output transistors may be on simultaneously resulting in virtual short circuit conditions across the power supply. To prevent this happening a dead time function is included which ensures that there is a period of time when both output transistors are off when the PWM output changes state. Each complementary output pair for the PWM module has an 4-bit counter, used to produce the dead time insertion. The complementary outputs will not change state until the timer counts down to zero. The following timing diagram indicates the dead time insertion for one pair of PWM signals. Active PWMxH (PWM without Dead Time) PWMxL Inactive Dead Time Dead Time PWMxH (PWM with Dead Time) Dead Time PWMxL Note: The PWM and Complementary PWM Outputs include Dead Time (Both PWMLEV and PWMCLEV=0) PWM Dead Time Timing The PWMDT register is used for the dead time control bits data writing protection. In Power Inverter applications, a dead time insertion can avoid the upper and lower switches of the half bridge circuit being active at the same time. Hence the dead time control is crucial to the operation of a system. A period of time must be provided to ensure that both output transistors are off when the PWM output changes state. Polarity Control Each PWM port of formed from the PWM0H/PWM0L~PWM2H/PWM2L pins has independent polarity control to configure the polarity of PWM output active state. The PWM output will default to an active high value. This implies that the PWM OFF state is low and the PWM ON state is high which are controlled via registers on each individual PWM channel. The following diagram illustrates the initial state before the PWM starts operation with different polarity settings. Rev. 1.00 143 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Initial State PWM Starts PB3 PB4 PWM0H PWM0L PWM0H PWM0L PWM0H off on off off off on off off off on off on on PWM0L off off PWM0H off on PWM0L off off off on off off on on P0HP=0 off P0LP=0 on P0HP=1 off P0LP=0 on P0HP=0 off on off P0LP=1 P0HP=1 P0LP=1 Note : The mark, , indicates the Dead-time insertion which is only available in the Complementary mode. PnHP and PnLP are the Polarity control bits which determine the PWM outputs active levels. The PWM0 initial state and polarity control has a rising edge with dead time insertion. PWM Mask Output Control There are two kinds of PWM Mask Output Control. One is controlled by the PWMC2 and PWMC3 registers and the other is controlled by the PWMC6 register. PWM Mask Output Control (PWMC2/PWMC3) When the PWMMD bit is equal to “0”, the PWM Mask output function is decided by the PWMC2 and PWMC3 bits. Each of the PWM output channels can be manually overridden by using the appropriate bits in the PWMC2 and PWMC3 control registers to drive the PWM I/O pins to specific logic states independent of the duty cycle comparison units. The PWMC3 register, including six control bits, determines which PWM I/O pins will be overridden. The PWMC3 register will default to 00H after reset. The PWMC2 register, including six control bits, determines the state of the PWM I/O pins when a specific output is masked via the PWMC3 control bits. The PWMC2 register will default to 00H after reset. The PWMC2 control bits are active high. When the PWMC2 bits are set to high, the output on the corresponding PWM I/O pins will be determined by the state of the PWMC3 bits and the polarity control bits. Rev. 1.00 144 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWM Mask Output Control(PWMC6) When the PWMMD bit=1, the PWM Mask Output is decided by the PWMC6 register. The following table illustrates the basic operation. PWMC6.7~ PWMC6.6 PWM0H PWM1H PWM2H PWM0L PWM1L PWM2L 00B PWM or 0 (P0HM=1 or 0) Complementary 1 or 0 1 or 0 1 or 0 PWM or 0 (P1HM=1 or 0) (P2HM=1 or 0) (P1LM=1 or 0) (P0LM=1 or 0) 01B 1 or 0 (P0HM=1 or 0) PWM or 0 1 or 0 1 or 0 (P1HM=1 or 0) (P2HM=1 or 0) (P0LM=1 or 0) Complementary 1 or 0 PWM or 0 (P2LM=1 or 0) (P1LM=1 or 0) 10B 1 or 0 (P0HM=1 or 0) 1 or 0 PWM or 0 1 or 0 (P1HM=1 or 0) (P2HM=1 or 0) (P0LM=1 or 0) 1 or 0 (P1LM=1 or 0) 11B PWM or 0 (P0HM=1 or 0) Complementary Complementary Complementary PWM or 0 PWM or 0 PWM or 0 PWM or 0 PWM or 0 (P1HM=1 or 0) (P2HM=1 or 0) (P0LM=1 or 0) (P1LM=1 or 0) (P2LM=1 or 0) 1 or 0 (P2LM=1 or 0) Complementary PWM or 0 (P2LM=1 or 0) Note: The PWM outputs, described in the above table, still have to be setup using the polarity register. If PWMEN=0, then the “PWM”, shown in the above table, is equal to “1”. If PWMCEN=0, then the “Complementary PWM”, shown in the above table, is equal to “1”. If PWMC6[7:6]=00B, and if PWMC6[3:2]=11B, then PWM1H and PWM1L will both output “0”. If PWMC6[5:4]=11B, then PWM2H and PWM2L will both output “0”; If only one of the PWM and Complementary PWM outputs is enabled, then one output will be either a PWM or the Complementary PWM output and the other output will be “0”. If PWMC6[7:6]=01B, and if PWMC6[1:0]=11B, then PWM0H and PWM0L will both output “0”. If PWMC6[5:4]=11B, then PWM2H and PWM2L will both output “0”; If only one of the PWM and Complementary PWM outputs is enabled, then one output will be either a PWM or a Complementary PWM output and the other output will be “0”. If PWMC6[7:6]=10B, and if PWMC6[1:0]=11B, then the PWM0H and PWM0L outputs will both output “0”. If PWMC6[3:2]=11B, then PWM1H and PWM1L will both output “0”; If only one of the PWM and Complementary PWM is enabled, then one output will be either a PWM or a Complementary PWM output and the other output will be “0”. If the PWMC6[7:6]=11B, and if the PWM or the Complementary PWM is enabled, then the output of the PWMnH and PWMnL will be either PWM or the Complementary PWM output, the other output will be “0”. Rev. 1.00 145 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWM Interrupt There are two interrupts related to the PWM. • An Interrupt that is synchronously requested at the PWM frequency when the counter and the PWM period register experience a compare match (PWM period) (PWMPE, PWMPF). • An Interrupt that is synchronously requested at the PWM frequency when the counter and the PWM duty register experience a compare match (PWM duty) (PWMDE, PWMDF). PWM Register List Name Bit7 Bit6 PWMC0 DTEN PWMC1 — — PWMC2 — — Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCK2 PWMCK1 PWMCK0 PWMON PWMMD PWMCEN PWMEN P2LEN P2HEN P1LEN P1HEN P0LEN P2LMEN P2HMEN P1LMEN P1HMEN P0LMEN P0HEN P0HMEN PWMC3 — — P2LD P2HD P1LD P1HD P0LD PWMC4 — — P2LP P2HP P1LP P1HP P0LP P0HP PWMC5 — — — — — — PTREN PWMLD PWMMD0 P2LM P2HM P1LM P1HM P0LM P0HM PWMC6 PWMMD1 P0HD PWMDL D7 D6 D5 D4 D3 D2 D1 D0 PWMDH — — — — D11 D10 D9 D8 PWMPL D7 D6 D5 D4 D3 D2 D1 D0 PWMPH — — — — D11 D10 D9 D8 PWML D7 D6 D5 D4 D3 D2 D1 D0 PWMH — — — — D11 D10 D9 D8 — — D3 D2 D1 D0 4 3 2 1 0 PWMDT PWMDTS1 PWMDTS0 PWMC0 Register Rev. 1.00 Bit 7 6 5 Name DTEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PWMCK2 PWMCK1 PWMCK0 PWMON PWMMD PWMCEN PWMEN Bit 7 DTEN: Dead-time insertion for the PWM pair enable/disable 0: disable dead-time insertion 1: enable dead-time insertion The Dead-time insertion is only active when this pair of complementary PWM is enabled. If the Dead-time insertion is inactive, the pin-pair outputs are complementary without any delay. Bit 6~4 PWMCK2~PWMCK0: Select PWM clock prescaler rate 000: fSYS/1 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These three bits are used to select the clock source for the PWM. The clock source, fSYS, is the high speed system clock. 146 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 3 PWMON: PWM output On/Off Control 0: off 1: on This bit is used to control the overall on/off function of the PWM. Setting the bit high will enable the PWM to run and clearing the bit will disable the PWM. Clearing this bit to zero will stop the counter. Bit 2 PWMMD: PWM Output Mask Mode selection 0: mask by PWMC2 and PWMC3 1: mask by PWMC6 Bit 1 PWMCEN: Complementary PWM signal enable/disable control 0: complementary PWM signal disable 1: complementary PWM signal enable Bit 0 PWMEN: PWM signal enable/disable control 0: PWM signal disable 1: PWM signal enable PWMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — P2LEN P2HEN P1LEN P1HEN P0LEN P0HEN R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 P2LEN: PWM2L output enable/disable 0: disable 1: enable Bit 4 P2HEN: PWM2H output enable/disable 0: disable 1: enable Bit 3 P1LEN: PWM1L output enable/disable 0: disable 1: enable Bit 2 P1HEN: PWM1H output enable/disable 0: disable 1: enable Bit 1 P0LEN: PWM0L output enable/disable 0: disable 1: enable Bit 0 P0HEN: PWM0H output enable/disable 0: disable 1: enable 147 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMC2 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 P2LMEN P2HMEN P1LMEN P1HMEN P0LMEN P0HMEN Name — — R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 P2LMEN: PWM2L output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. Bit 4 P2HMEN: PWM2H output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. Bit 3 P1LMEN: PWM1L output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. Bit 2 P1HMEN: PWM1H output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. Bit 1 P0LMEN: PWM0L output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. Bit 0 P0HMEN: PWM0H output mask enable/disable 0: disable 1: enable The PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel will be an output with a value determined by the PWMC3 register. 148 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMC3 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 Name — — P2LD P2HD P1LD P1HD P0LD P0HD R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 P2LD: PWM2L output level when mask enabled 0: low 1: high Bit 4 P2HD: PWM2H output level when mask enabled 0: low 1: high Bit 3 P1LD: PWM1L output level when mask enabled 0: low 1: high Bit 2 P1HD: PWM1H output level when mask enabled 0: low 1: high Bit 1 P0LD: PWM0L output level when mask enabled 0: low 1: high Bit 0 P0HD: PWM0H output level when mask enabled 0: low 1: high 149 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMC4 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 Name — — P2LP P2HP P1LP P1HP P0LP P0HP R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 P2LP: PWM2L output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. Bit 4 P2HP: PWM2H output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. Bit 3 P1LP: PWM1L output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. Bit 2 P1HP: PWM1H output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. Bit 1 P0LP: PWM0L output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. Bit 0 P0HP: PWM0H output polarity control 0: PWM output is active high (initial state=0) 1: PWM output is active low (initial state=1) The register bit controls the initial state as well as the polarity/active state of the PWM output. 150 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMC5 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PTREN PWMLD R/W — — — — — — R/W R/W POR — — — — — — 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1 PTREN: Specific registers protect function control bit 0: disable 1: enable Bit 0 PWMLD: PWM counter and PWM compare register load control 0: disable 1: enable Setting this bit to high will enable this function. The PWMP register value will be loaded to the counter register after the counter overflows, and the related hardware will be cleared by the next clock cycle. Clearing this bit will disable this function. The value of the PWMP and PWMD registers will not be loaded to the PWM counter and the PWM compare registers. PWMC6 Register Bit Name Rev. 1.00 7 6 PWMMD1 PWMMD0 5 4 3 2 1 0 P2LM P2HM P1LM P1HM P0LM P0HM R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PWMMD1~PWMMD0: PMW Output MASK control 00: only PWM0H and PWM0L are output enabled, PWM1H, PWM1L, PWM2H, PWM2L are masked 01: only PWM1H and PWM1L are output enabled, PWM0H, PWM0L, PWM2H, PWM2L are masked 10: only PWM2H and PWM2L are output enabled, PWM0H, PWM0L, PWM1H, PWM1L are masked 11: ALL PWMnH and PWMnL are output enabled Bit 5 P2LM: PWM2L mask control 0: output 0 1: output Complementary PWM or 1 The PWM2L output Complementary PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMCEN control bits. Bit 4 P2HM: PWM2H mask control 0: output 0 1: output PWM or 1 The PWM2H output PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMEN control bits. Bit 3 P1LM: PWM1L mask control 0: output 0 1: output Complementary PWM or 1 The PWM1L output Complementary PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMCEN control bits. Bit 2 P1HM: PWM1H mask control 0: output 0 1: output PWM or 1 The PWM1H output PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMEN control bits. 151 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Bit 1 P0LM: PWM0L mask control 0: output 0 1: output Complementary PWM or 1 The PWM0L output Complementary PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMCEN control bits. Bit 0 P0HM: PWM0H mask control 0: output 0 1: output PWM or 1 The PWM0H output PWM or “1” is decided by the PWMMD1, PWMMD0 and PWMEN control bits. PWMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PWMDL: PWM Counter Low Byte Register bit 7~bit 0 PWM 12-bit Counter bit 7~bit 0 PWMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — D11 D10 D9 D8 R/W — — — — R R R R POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 PWMDH: PWM Counter High Byte Register bit 3~bit 0 PWM 12-bit Counter bit 11~bit 8 PWMPL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PWMPL: PWM Period Low Byte Register bit 7~bit 0 PWMP 12-bit Register bit 7~bit 0 PWMPH Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — D11 D10 D9 D8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 PWMPH.3~PWMPH.0: PWM Period High Byte Register bit 3~bit 0 PWMP 12-bit Register bit 11~bit 8 152 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWML Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PWML: PWM Duty Low Byte Register bit 7~bit 0 PWM 12-bit Duty Setting Register bit 7~bit 0 PWMH Register Bit 7 6 5 4 3 2 1 0 Name — — — — D11 D10 D9 D8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 PWMH.3~PWMH.0: PWM Duty High Byte Register bit 3~bit 0 PWM 12-bit Duty Setting Register bit 11~bit 8 PWMDT Register Bit 6 5 4 3 2 1 0 — — D3 D2 D1 D0 R/W R/W R/W — — R/W R/W R/W R/W POR 0 0 — — 0 0 0 0 Name Bit 7~6 Rev. 1.00 7 PWMDTS1 PWMDTS0 PWMDT: PWM Dead Time clock source selection 00: fPWMDT is fSYS/1 01: fPWMDT is fSYS/2 10: fPWMDT is fSYS/4 11: fPWMDT is fSYS/8 Bit 5~4 Unimplemented, read as "0" Bit 3~0 PWMDT: PWM Dead Time Register bit 3~bit 0 Dead-time counter, 4-bit dead time value bits for Dead Time Unit PWM Dead-time=(PWMDT.3~0+1)/fPWMDT 153 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Over Current Protection This device provides an over current protection function. The over current signal can be srouced from INT1, INT2, C0OUT or C1OUT, which can be selected by the OCS1 and OCS0 bits in the PWMOCC register. C0X C1X INT1 M U X Start the Over Current Protection Circuit Noise Filter Trigger the Over Current Interrupt INT2 There are four kinds of Over current signals, rising edge, falling edge, low level and high level, which are used to trigger the over current protection function. The Low level over current protection function is shown in the following timing diagram. If the over current protection function is enabled and an over current situation occurs, then, the PWM signal will be set to the inactive state and the complementary PWM will be set to the active state automatically. However, the polarity control register can still decide if the last output is inverted or not. If necessary, this protection function can also be disabled by the OCEN bit in in the PWMOCC register during the over current protection status. Rev. 1.00 154 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Low Level Over Current Protection Function over current signal PWM period New PWM period start PWM period PWMH Without dead time *Note PWML Without dead time PWMH With dead time PWML With dead time : Dead time, Low state, This profile is before the output polarity control circuit. The over current signal is low level active. Note: The over current signal in the timing diagram can be selected as a low level or high level to trigger the over current protection function, which will also generate an over current interrupt when the over current protection function has been triggered. The falling edge over current protection function is shown in the following timing diagram. If the over current protection function is enabled and an over current situation occurs, PWMON will be cleared to “0” by the hardware to stop PWM generation. If PWMON is resumed to “1”, then the current protection condition will be released by the hardware. After starting the over current protection function, the PWM signal will be set to the inactive state and the complementary PWM will be set to the active state automatically, however, the polarity control register can still decide if the last output is inverted or not. If necessary, this protection function can also be disabled by the OCEN bit in the PWMOCC register during the over current protection status. Rev. 1.00 155 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Falling Edge Over Current Protection Function over current signal PWM period PWM period PWMH Without dead time *Note PWML Without dead time PWMH With dead time PWML Witht dead time : Dead time, Low state, This profile is before the output polarity control circuit. The over current signal is falling edge active. Note: The over current signal in the timing diagram can be selected as a falling edge or rising edge to start over current protection function, which will generate an over current interrupt when the over current protection function has been enabled. Over Current Protection Interrupt The PWM Over Current Protection function includes a, PWM Over Current Interrupt. There is one interrupt request flag, PWMOVIF, and one enable bit, PWMOVIE. A PWM Over Current Protection interrupt will take place when the PWM Over Current request flag is set, a situation which occurs when a PWM Over Current situation happens. Refer to the Interrupt section for details. Rev. 1.00 156 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Over Current Protection Function Register PWMOCC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name OCEN OCNFEN OCNFT OCNFS OCS1 OCS0 OCM1 OCM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 OCEN: Over current Protection Function enable or disable 0: disable 1: enable When the function is enabled, the output mode of INT1 or INT2 will be disabled and the pin will only have an input mode. Bit 6 OCNFEN: Over current signal Noise Filter enable or disable 0: disable 1: enable Bit 5 OCNFT: Defines the number of sample times for the over current signal noise filter 0: twice 1: 4 times The over current signal noise filter circuit requires sampling twice or 4 times continuously. When the sampled values are the same, the signal will be acknowledged. The sample clock is decided by OCNFS. Bit 4 OCNFS: Defines over current signal noise filter clock source 0: tSYS 1: 4tSYS Over current signal noise filter clock is sourced from the system clock or from 4 times the system clock. Bit 3~2 OCS1 and OCS0: Over current signal source 00: C0OUT 01: C1OUT 10: INT1 11: INT2 Bit 1~0 OCM1~OCM0: Select Over current Protection Mode 00: low Level 01: high Level 10: falling Edge 11: rising Edge 157 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Automatic Brake Control This device provides an Automatic Brake function for motor control. The Brake signal can be input on the INT1 pin. There are four kinds of Automatic Brake Control signals, rising edge, falling edge, low level or high level to trigger this function. The following diagram illustrates the basic functional operation. INT1 PWM Output Brake State & Trigger PWM Brake Interrupt Noise Filter BKM0, BKM1 Rev. 1.00 158 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Automatic Brake modes There are three modes, Disable Auto Brake mode, Level Auto Brake mode and Edge Auto Brake mode, for the Automatic Brake function, controlled by the BKM1 and BKM0 bits in the PWMBKC register. Disable Auto Brake Mode: Set the BKM [1:0] control bits to “00” and “11” to disable the Automatic Brake Control function. The Brake function has to be implemented using Software. Level Auto Brake Mode: Set the BKM [1:0] control bits to “01” to activate the Level Auto Brake mode. The following diagram illustrates the level brake timing diagram. In the braking condition, the PWM0H, PWM0L, PWM1H, PWM1L, PWM2H and PWM2L output states are decided by the PWMBKD register, however, the polarity control register can still decide if the final output is inverted or not. Automatic Brake Control MODE 01 Brake PWM period New PWM period start PWM period PWMH Without dead time *Note PWML Without dead time PWMH With dead time PWML With dead time : Dead time, Low state, This profile is before the output polarity control circuit. The Brake singal is low active. *Note: in Brake state (red line), PWMxL and PWMxH output states are decided by PWMBKD.0~5. Note: The Brake trigger signal can be selected to be either a low level or high level. If there is a triggered signal input, then this will generate a brake interrupt. Rev. 1.00 159 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Edge Auto Brake Mode: Set the BKM[1:0] control bits to “10” to activate the Edge Auto Brake mode. The following diagram shows the Edge brake timing. In this mode, the PWMON bit will be set to “0” by hardware to stop PWM generation. After this PWMON is resumed to “1” and the Brake condition will be released automatically. In the braking condition, the PWM0H, PWM0L, PWM1H, PWM1L, PWM2H and PWM2L output states are decided by the PWMBKD register, however, the polarity control register can still decide if the final output is inverted or not. Automatic Brake Control MODE 10 Brake PWM period PWM period PWMH Without dead time *Note PWML Without dead time PWMH With dead time PWML With dead time : Dead time, Low state, This profile is before the output polarity control circuit. The Brake signal is falling edge active. *Note: in Brake state (red line), PWMxL and PWMxH output states are decided by PWMBKD.0~5. Note: The Brake triggered signal can be selected as a falling edge or a rising edge. If there is a triggered signal input, that will generate a brake interrupt. PWM Automatic Brake Control Interrupt The PWM Automatic Brake Control has a, PWM Brake Interrupt. There is one interrupt request flag, PWMBKIF, and one enable bit, PWMBKIE. A PWM Brake interrupt request will take place when the PWM Brake request flag is set, a situation which occurs when a PWM Brake situation happens. Refer to the Interrupt section for details. Automatic Brake Control Register List Rev. 1.00 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMBKC BKF BKNFEN BKNFT BKNFS BKEN BKTR BKM1 BKM0 PWMBKD — — P2LBK P2HBK P1LBK P1HBK P0LBK P0HBK 160 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMBKC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name BKF BKNFEN BKNFT BKNFS BKEN BKTR BKM1 BKM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 BKF: PWM Brake flag 0: PWM brake did not occur, or release PWM brake state 1: PWM Brake occurs When a PWM brake occursand PWMON=0, set BKF to 0 to release the PWM brake state. After the PWM has experienced a brake, set PWMON to 1 again, this action will also release the PWM brake state and restart PWM. Bit 6 BKNFEN: PWM Brake Noise Filter enable or disable 0: disable 1: enable Bit 5 BKNFT: Defines PWM Brake noise filter sample times 0: twice 1: 4 times The PWM Brake noise filter circuit requirea sampling twice or 4 times continuously, When the sampled values are the same, the signal will be acknowledged. The sample clock is decided by BKNFS. Bit 4 BKNFS: Defines the PWM Brake noise filter clock source 0: tSYS 1: 4tSYS The PWM Brake noise filter clock is sourced from the system clock or 4 times the system clock. Bit 3 BKEN: PWM Brake Function enable or disable 0: disable 1: enable When the function is enabled, the INT1 ouput mode will be disabled and the pin will only have an input mode. Bit 2 BKTR: Select the PWM auto brake trigger mode 0: low level or falling edge 1: high level or rising edge Bit 1~0 BKM1~BKM0: Select the PWM Brake Mode 00: disable Auto Brake 01: level Auto Brake 10: edge Auto Brake 11: disable Auto Brake 161 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU PWMBKD Register Bit 7 6 5 4 3 2 1 0 Name — — P2LBK P2HBK P1LBK P1HBK P0LBK P0HBK R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 P2LBK: PWM2L output control in brake state 0: PWM2L output low in brake state 1: PWM2L output high in brake state Bit 4 P2HBK: PWM2H output control in brake state 0: PWM2H output low in brake state 1: PWM2H output high in brake state Bit 3 P1LBK: PWM1L output control in brake state 0: PWM1L output low in brake state 1: PWM1L output high in brake state Bit 2 P1HBK: PWM1H output control in brake state 0: PWM1H output low in brake state 1: PWM1H output high in brake state Bit 1 P0LBK: PWM0L output control in brake state 0: PWM0L output low in brake state 1: PWM0L output high in brake state Bit 0 P0HBK: PWM0H output control in brake state 0: PWM0H output low in brake state 1: PWM0H output high in brake state PWM Interrupt Auto A/D Start function This device provides various PWM interrupts to trigger the Auto A/D Start function. This is selected by two control bits, ASSEL1 and ASSEL0. The ASADCEN bit is used to enable or disable this function. In addition, the delay time control is managed by the ASDTEN bit and the delay time is decided by the ASADCT prescale register. PWM Interrupt Auto A/D Start Control Register List Name Rev. 1.00 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ASADCC — — — — ASDTEN ASSEL1 ASSEL0 ASADCEN ASADCT D7 D6 D5 D4 D3 D2 D1 D0 162 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU ASADCC Register Bit 7 6 5 4 3 2 1 0 Name — — — — ASDTEN ASSEL1 ASSEL0 ASADCEN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 ASTDEN: PWM Interrupt Auto A/D Start delay time Control 0: disable delay time 1: enable delay time Bit 2~1 ASSEL1~ASSEL0: PWM Interrupt Auto A/D Start mode selection 00: none 01: PWM Period Interrupt 10: PWM Duty Interrupt 11: both PWM Period and Duty Bit 0 ASADCEN: PWM Interrupt Auto A/D Start function control 0: disable 1: enable ASADCT Register Bit 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 7 ASADCT: PWM Interrupt Auto A/D Start function delay time selection 0: delay time=256/fSYS Other: delay time=(ASADCT.7~0)/fSYS 163 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Special Register Write Protection This device provides a special register write protection function for some specific registers, namely PWMBKD, PWMC1, PMMC4, PWMDT and PWMBKC. This function is enabled by the PTREN bit in the PWMC5 register and managed by the PTSFR register. If the PTREN bit is cleared to “0”, then the protection function will be disabled. If the PTREN bit is set “1” and if this PTSFR register is written with a value of 55H first, followed by AAH successively, then the data in the protected registers can be updated, otherwise these registers can only be read from and not written to. In addition, if the writing data time, between writing 55H and AAH, is greater than 4/fSUB, the procedure will be defined as invalid and these special registers will also be protected and cannot be updated with new data. PWMC5 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PTREN PWMLD R/W — — — — — — R/W R/W POR — — — — — — 1 0 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1 PTREN: Special Register Write Protection enable bit 0: disable 1: enable Bit 0 PWMLD: PWM counter and PWM compare register load control described elsewhere. PTSFR Register Bit 6 5 4 3 2 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 7 PFSFR: 8-bit Register writing the PTSFR register with 55H and 0AAH successively to allow some of the protected registers to be written to. 164 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Capture Timer Module – CAPTM The Capture Timer Module is a 16-bit up counter which is configured and controlled by the CAPTC0 and the CAPTC1 registers. This module is also equipped with up to 8 input channels, selected by the CAPTS [2:0] bits. The clock source is provided by fSYS, divided by 1, 2, 4, 8, 16, 32, 64 or 128. The CAPTON bit is used to control the module enable or disable. In addition, a Capture Timer Module interrupt function is provided. Capture Mode The capture timer module is designed to detect and measure the pulse width and period of square waves. It can support up to 8 capture inputs and includes an internal digital noise rejection filter. The module is configured by the CAPCON0 and CAPCON1 registers. In addition, each Capture input has its own edge detector selection. The capture timer module contains the capture registers, the noise filter and the trigger edge option. The capture registers, CAPTMCL and CAPTMCH, are used to store the captured data. The noise filter is used to filter unwanted glitches or pulses on the trigger input pin. It is enabled using the CAPFIL bit. If the noise filter is enabled, the capture logic is required to be sampled 2 or 4 times(tSYS or 4 tSYS) in order to recognize an edge as a capture event. The trigger edge option is controlled by the CAPEG1 and CAPEG0 bits. It supports positive edge, negative edge and both edge trigger types. The capture module is enabled by a control bit, CAPEN. The Capture Timer Module Counter is a 16-bit up counter with various compare modes. Refer to the Compare Mode section for the details. The Capture module can be triggered by the following external input pins or internal comparator output bits: INT0A, INT0B, INT0C, INT1, C0OUT, C1OUT, C2OUT, and C3OUT. If the CAPEN bit is enabled then each time the external pin or internal bit is triggered, the contents of the free running 16-bit counter, CAPTMDL and CAPTMDH, will be captured into the capture registers, CAPTMCL and CAPTMCH. This will also set the CAPTIF flag bit in the interrupt control register and generate an interrupt if the interrupt is enabled by the control bit, CAPTIE. Setting the CAPCLR bit, will allow the hardware to reset the 16-bit counter automatically after the CAPTMDL and CAPTMDH values have been captured. Capture Interrupt INT0A INT0B INT0C INT1 MUX C0X Noise Filter C1X C2X Rising Or Falling Or Double Edge Or Disable Capture Register CAPTMCH, CAPTMCL Capture Counter CAPTMDH, CAPTMDL Clear Capture Counter C3X Capture Compare Register CAPTMAH, CAPTMAL CAPTS2~CAPTS0 Rev. 1.00 CAPFIL Overflow Interrupt CAPEG1~CAPEG0 165 Compare Compare Interrupt Clear Capture Counter February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Compare Mode The CAPTM can be configured to be in a Compare mode. CAPTMAL and CAPTMAH are used as the compare registers. When the CAPTM counter counts up to match with the CAPTMAL and CAPTMAH values, the CAPTMF bit will be set which will then generate an interrupt request. Setting the CAPTCLR bit to high will allow the hardware to reset the CAPTM counter automatically after a compare match occurs. Capture Timer Module Interrupt The Capture Timer Module has three interrupts, Capture Interrupt, Compare match interrupt and Capture counter overflow interrupt. These three Interrupts requests will take place when the Capture Timer Module request flags, CAPTIF, CAPTMF, and CAPTOF are set. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective Capture Timer Module Interrupt enable bit, and relevant Interrupt enable bit, CAPTIE, CAPTME and CAPTOE, must first be set. When the interrupt is enabled, the stack is not full, when a capture, compare match or capture counter overflow occurs, a subroutine call to the relevant interrupt vector location, will take place. Refer to the Interrupt section for details. Capture Timer Register List Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CAPTC0 CAPTPAU CAPTCK2 CAPTCK1 CAPTCK0 CAPTON CAPTS2 CAPTS1 CAPTS0 CAPTC1 CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAPTCLR CAPTMDL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMDH D15 D14 D13 D12 D11 D10 D9 D8 CAPTMAL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMAH D15 D14 D13 D12 D11 D10 D9 D8 CAPTMCL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMCH D15 D14 D13 D12 D11 D10 D9 D8 Rev. 1.00 166 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CAPTC0 Register Bit 7 6 5 4 3 Name CAPTPAU CAPTCK2 CAPTCK1 CAPTCK0 CAPTON Rev. 1.00 2 1 0 CAPTS2 CAPTS1 CAPTS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CAPTPAU: CAPTM Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit to high. Clearing the bit to zero will restore normal counter operation. When in the Pause condition, the CAPTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit is set to high and resume counting from this value when this bit is set to low. Bit 6~4 CAPTCK2~CAPTCK0: Select CAPTM Counter clock 000: fSYS/1 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These three bits are used to select the clock source for the CAPTM. The clock source fSYS is the system clock. Bit 3 CAPTON: CAPTM Counter On/Off Control 0: off 1: on This bit controls the overall on/off function of the CAPTM. Setting the bit high will enable the counter and clearing the bit will disable the CAPTM. Clearing this bit to zero will stop the counter from counting and turn off the CAPTM. When the bit changes state from low to high, the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. Bit 0~2 CAPTS2~CAPTS0: Select CAPTM capture input 000: INT0A 001: INT0B 010: INT0C 011: INT1 100: C0OUT 101: C1OUT 110: C2OUT 111: C3OUT These three bits are used to select the capture input for the CAPTM. 167 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CAPTC1 Register Bit Name 7 6 CAPEG1 CAPEG0 5 4 CAPEN 3 CAPNFT CAPNFS 2 CAPFIL 1 0 CAPCLR CAPTCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CAPEG1, CAPEG0: CAPTM capture active edge control bits 00: disabled CAPTM capture 01: rising edge capture 10: falling edge capture 11: dual edge capture Bit 5 CAPEN: CAPTM Capture Input Control 0: disable 1: enable This bit controls the CAPTM capture input source enable or disable. Bit 4 CAPNFT: Defines the CAPTM noise filter sample times 0: 2 times 1: 4 times The CAPTM input will only be valid if the same value is sampled either 2 or 4 times. The sample clock is decided by the CAPNFS bit. Bit 3 CAPNFS: CAPTM noise filter clock source selection 0: tSYS 1: 4tSYS The CAPTM noise filter clock is sourced from the system clock or 4 times the system clock. Bit 2 CAPFIL: CAPTM capture input filter control 0: disable 1: enable This bit controls the CAPTM capture input filter enable or disable. Bit 1 CAPCLR: CAPTM Counter capture auto-reset control 0: disable 1: enable This bit enable/disable the hardware automatically to reset the CAPTM Counter when the value in CAPTMDL and CAPTMDH has been transferred into the capture register CAPTMCL and CAPTMCH. Bit 0 CAPTCLR: CAPTM Counter compare match auto-reset control 0: disable 1: enable Setting the CAPTCLR bit, will allow the hardware to reset the CAPTM counter automatically after a match has occurred. CAPTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 CAPTMDL: CAPTM Counter Low Byte Register bit 7~bit 0 CAPTM 16-bit Counter bit 7~bit 0 168 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CAPTMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CAPTMDH: CAPTM Counter High Byte Register bit 7~bit 0 CAPTM 16-bit Counter bit 15~bit 8 CAPTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CAPTMAL: CAPTM Compare Low Byte Register bit 7~bit 0 CAPTM 16-bit Compare Register bit 7~bit 0 CAPTMAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CAPTMAH: CAPTM Compare High Byte Register bit 7~bit 0 CAPTM 16-bit Compare Register bit 15~bit 8 CAPTMCL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR x x x x x x x x "x" unknown Bit 7~0 CAPTMCL: CAPTM Capture Low Byte Register bit 7~bit 0 CAPTM 16-bit Capture Register bit 7~bit 0 CAPTMCH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR x x x x x x x x "x" unknown Bit 7~0 Rev. 1.00 CAPTMCH: CAPTM Capture High Byte Register bit 7~bit 0 CAPTM 16-bit Capture Register bit 15~bit 8 169 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Shunt Regulator The device includes an internal shunt regulator to provide a stable 5V power supply for the device VDD. There is no need therefore to supply an external voltage regulator in the systems if an unregulated power supply is used. External devices can also connect directly to the VDD pin to share the regulated supply voltage but will contribute to the total VDD supply current, ILOAD. A shunt regulator generates a specific supply voltage by creating a voltage drop across a resistor. The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage reference. The current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage VUNREG and the VDD of the microcontroller. An external current limit resistor, RSER, located between the unregulated power supply, VUNREG, and the VDD pin, induces the difference in voltage between VUNREG and VDD. The supply voltage, VUNREG, and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses a band gap voltage as a regulated voltage reference, this voltage reference is permanently enabled in the device. Rev. 1.00 170 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Application Circuit VD D VDD 0.1µ F VS S PA0 ~PA7 P B 0~ P B 5 PC0~PC3 Note: 1. The total current consumption of MCU and external circuit determine the resistance R1 value and wattage. 2. Recommend C1 to use Tantalum Capacitor, and the value is 10μF. 3. Recommend C2 to use bypass capacitor, and the valueis 0.1μF. 4. Please put C1 and C2 as close to IC as possible Rev. 1.00 171 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5µs and branch or call instructions would be implemented within 1µs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ″CLR PCL″ or ″MOV PCL, A″. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 172 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ″SET [m].i″ or ″CLR [m].i″ instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the ″HALT″ instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 173 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Arithmetic Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Rev. 1.00 174 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 175 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 Add Data Memory to ACC 176 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 177 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 178 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 179 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i = 0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i = 0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i = 0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i = 0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i = 0~6) [m].7 ← [m].0 None Rev. 1.00 180 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i = 0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i = 0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i = 0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m] = 0 None Rev. 1.00 181 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC = 0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m] = 0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC = 0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 182 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7 ~ [m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 ← [m].7 ~ [m].4 ACC.7 ~ ACC.4 ← [m].3 ~ [m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m] = 0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Rev. 1.00 183 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU TABRD [m] Description Operation Affected flag(s) Read table to TBLH and Data Memory The program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 184 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin TSSOP Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.039 ― 0.041 A1 0.002 ― 0.006 A2 0.041 ― 0.047 B ― 0.010 ― C 0.004 ― 0.006 D 0.193 ― 0.201 E 0.244 ― 0.260 E1 0.169 ― 0.177 e ― 0.026 ― L 0.020 ― 0.028 y ― ― 0.003 θ 0° ― 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 1.00 ― 1.05 A1 0.05 ― 0.15 A2 1.05 ― 1.20 B ― 0.25 ― C 0.11 ― 0.15 D 4.90 ― 5.10 E 6.20 ― 6.60 E1 4.30 ― 4.50 e ― 0.65 ― L 0.50 ― 0.70 y ― ― 0.076 θ 0° ― 8° 185 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU 20-pin TSSOP Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.041 ― 0.047 A1 0.002 ― 0.006 A2 0.037 ― 0.041 B ― 0.009 ― C 0.005 ― 0.007 D 0.252 ― 0.260 E 0.248 ― 0.256 E1 0.169 ― 0.177 e ― 0.026 ― L 0.018 ― 0.030 y ― ― 0.004 θ 0° ― 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 1.05 ― 1.20 A1 0.05 ― 0.15 A2 0.95 ― 1.05 B ― 0.22 ― C 0.13 ― 0.17 D 6.40 ― 6.60 E 6.30 ― 6.50 E1 4.30 ― 4.50 e ― 0.65 ― L 0.45 ― 0.75 y ― ― 0.10 θ 0° ― 8° 186 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Reel Dimensions TSSOP 16L Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 16.8+0.3/-0.2 2.0±0.5 T2 Reel Thickness 22.2±0.2 TSSOP 20L Symbol Rev. 1.00 Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 16.4+0.3/-0.2 2.0±0.5 T2 Reel Thickness 19.1 max. 187 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Carrier Tape Dimensions TSSOP 16L Symbol Description W Carrier Tape Width Dimensions in mm 16.0+0.3/-0.1 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation(Width Direction) 7.5±0.5 D Perforation Diameter 1.5+0.1/-0.0 D1 Cavity Hole Diameter 1.5+0.1/-0.0 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation(Length Direction) 2.0±0.1 A0 Cavity Length 6.8±0.1 B0 Cavity Width 5.4±0.1 K0 Cavity Depth 1.6±0.1 t Carrier Tape Thickness C Cover Tape Width 0.300±0.013 13.3±0.1 TSSOP 20L Symbol Rev. 1.00 Description Dimensions in mm W Carrier Tape Width P Cavity Pitch 16.0±0.3 E Perforation Position F Cavity to Perforation(Width Direction) 7.5±0.1 D Perforation Diameter 1.5+0.1/-0.0 D1 Cavity Hole Diameter 1.5+0.1/-0.0 8.0±0.1 1.75±0.10 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation(Length Direction) 2.0±0.1 A0 Cavity Length 6.8±0.1 B0 Cavity Width 6.9±0.1 K0 Cavity Depth 1.6±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 188 February 05, 2013 HT45FM30 Brushless DC Motor Flash Type 8-Bit MCU Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311, 86-769-2626-1322 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright © 2013 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 189 February 05, 2013