LPC Bus Controller April 2011 Reference Design RD1049 Introduction The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance. It is used to connect peripherals around the CPU and to replace the Industry Standard Architecture (ISA) bus which can only run up to 8 MHz. The primary benefit is that signals can be transmitted across a minimum of seven traces for an LPC bus versus 52 traces for an ISA bus. This relieves the pressure of routing on the often-congested motherboard and at the same time improves the overall system integrity. The Lattice LPC Bus Controller Reference Design implements a LPC host and a LPC peripheral that support the seven required LPC control signals. The design is implemented in Verilog as well as VHDL, and Lattice design tools are used for synthesis, place and route, and simulation. The design can be targeted to multiple Lattice device families, and its small size makes it portable across different FPGA/CPLD architectures. This reference design is based on the Low Pin Count Interface Specification (version 1.1) that is available from the Intel website. It is assumed the reader is familiar with the LPC Specification prior to evaluating and implementing this reference design. Features and Limitations This reference design includes two projects, one for the LPC host and the other for the LPC peripheral. This implementation supports I/O read and write. It is not a fully spec-compliant implementation because the LPC host lacks DMA read and DMA write ability. Also, the state machines implemented for I/O read and write do not make full use of the available commands. For example, the read sync does not distinguish between short idle and long idle. There is also no timeout for sync. Figure 1. Reference Design Block Diagram IO_READ_STATUS LFRAME IO_WRITE_STATUS HOST_DATA_IN LRESET LPC Host CURRENT_HOST_STATE LACK LAD[3:0] LPC Bus Back-end Interface HOST_ADDRESS_IN HOST_READY HOST_DATA_OUT Project for LPC Host CURRENT_PERI_STATE LPC Bus LPC_EN LRESET LACK LAD[3:0] IO_READ_STATUS LPC Peripheral IO_WRITE_STATUS LPC_DATA_OUT LPC_DATA_OUT ADDR_HIT PERI_DIN Back-end Interface PERI_ADDRESS_OUT LFRAME Project for LPC Peripheral © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1049_01.6 Lattice Semiconductor LPC Bus Controller Functional Description LPC Host Module The LPC host is the initiator of commands. Supported commands are I/O read and write. If the write flag is high, the LPC host transmits the contents of the data and address provided via the back-end interface across the LPC interface to the peripheral. The host then waits for the sync indicator from the peripheral to terminate the write. Read operations behave like the write cycle. Figure 2. State Machine for the LPC Host Module Force Reset Idle IO_READ_STATUS Start IO_WRITE_STATUS IOR_CYC_TYPE IOR_CYC_TYPE RD_ADDR1 WR_ADDR1 RD_ADDR2 WR_ADDR2 RD_ADDR3 WR_ADDR3 RD_ADDR4 WR_ADDR4 RD_TAR1 WR_DATA1 RD_TAR2 WR_DATA2 RD_SYNC WR_TAR1 RD_DATA1 WR_TAR2 RD_DATA2 WR_SYNC LAD! = 0000 LAD! = 0000 FINAL_TAR1 FINAL_TAR2 2 Lattice Semiconductor LPC Bus Controller Table 1. LPC Host Signal Descriptions Name Direction Description LPC Interface LAD LFRAME Bi-directional Input Multiplexed command, Address, and Data Active-low frame signal LRESET Input Active-low reset signal LCLK Input Clock Input Address used for reads and writes Back-end Interface Host_Address_In IO_Read_Status Input Active-high read request IO_Write_Status Input Active-high write request Input Data sent from host to peripheral HOST_DATA_IN Current_Host_State Output Current host state Host_Ready Output Active-high status that host is ready for next operation HOST_DATA_OUT Output Data received from peripheral to host 3 Lattice Semiconductor LPC Bus Controller LPC Peripheral Module The LPC peripheral is primarily a passive recipient and reactor to commands initiated by the host. Supported commands are I/O read and write. Figure 3. State Machine for the LPC Peripheral Module Idle Start IO_RD IO_WR IO_RD_ADDR_LCLK1 IO_WR_ADDR_LCLK1 IO_RD_ADDR_LCLK2 IO_WR_ADDR_LCLK2 IO_RD_ADDR_LCLK3 IO_WR_ADDR_LCLK3 IO_RD_ADDR_LCLK4 IO_WR_ADDR_LCLK4 IO_RD_TAR_LCLK1 IO_WR_DATA_LCLK1 IO_RD_TAR_LCLK2 IO_WR_DATA_LCLK2 IO_RD_SYNC IO_WR_TAR_LCLK1 IO_RD_DATA_LCLK1 IO_WR_TAR_LCLK2 IO_RD_DATA_LCLK2 IO_WR_SYNC LAST_TAR_LCK1 LAST_TAR_LCK2 4 Lattice Semiconductor LPC Bus Controller Table 2. LPC Peripheral Signal Descriptions Name Direction Description LPC Interface LAD Bi-directional Multiplexed Command, Address and Data LFRAME Input Active-low frame signal LRESET Input Active-low reset signal LCLK Input Clock Back-end Interface Addr_Hit Input Peri_Din Input Data sent when host requests a read IO_Read_Status Output Active-high read status IO_Write_Status Output Active-high write status Current_Peri_State Output Current peripheral state Lpc_En Output Active-high status signal indicating the peripheral is ready for next operation. Lpc_Data_In Output Data received by peripheral for writing Lpc_Data_Out Output Data sent to host when a read is requested The CPU must provide external control, address and data inputs to the LPC host in order to perform a read or write operation to the peripheral. When the host requests a read operation, the peripheral must supply the data to be returned on the Peri_Data_In bus. When the host performs a write operation, the peripheral receives the data from the host on the Peri_Write_Out bus. Testbench Description The testbench for this design includes the following modules: • LPC_Host • LPC_Peripheral An I/O write and then an I/O read are performed to demonstrate functionality of the design. Timing Specifications The following diagrams show the major milestones in the LPC Reference Design. Figure 4 shows a CPU writing to a LPC peripheral device. The host is writing address 0xF0F0 with data 0x5A. Figure 4. LPC Host Write Cycle 5 Lattice Semiconductor LPC Bus Controller Figure 5 shows a CPU reading from a LPC peripheral device. The host is reading address 0xF0F0 and gets 0xA5. The testbench throws any write data away, and only provides a constant 0xA5 to the host for read cycles. It is the designer’s responsibility to connect the back-end to a storage medium. Figure 5. LPC Host Read Cycle 6 Lattice Semiconductor LPC Bus Controller Implementation This design is implemented in Verilog and VHDL. When using this design in a different device, density, speed, or grade, performance and utilization may vary. Default settings are used during the fitting of the design. Table 3. Performance and Resource Utilization Project Device Family MachXO2™ 1 MachXO™ 2 LPC Peripheral LatticeECP3™ 3 LatticeXP2™ 4 ispMACH® 4000ZE5 MachXO21 MachXO2 LPC Host LatticeECP3™ 3 LatticeXP24 ispMACH 4000ZE5 1. 2. 3. 4. 5. Language Speed Grade Utilization fMAX (MHz) I/Os Architecture Resources VHDL -5 73 LUTs >33 52 N/A Verilog -5 73 LUTs >33 52 N/A VHDL -3 73 LUTs >33 52 N/A Verilog -3 73 LUTs >33 52 N/A VHDL -7 97 LUTs >33 52 N/A Verilog -7 96 LUTs >33 52 N/A VHDL -5 95 LUTs >33 52 N/A Verilog -5 90 LUTs >33 52 N/A VHDL -5 (ns) 66 Macrocells >33 52 N/A Verilog -5 (ns) 66 Macrocells >33 52 N/A VHDL -5 92 LUTs >33 50 N/A Verilog -5 84 LUTs >33 50 N/A VHDL -3 89 LUTs >33 50 N/A Verilog -3 84 LUTs >33 50 N/A VHDL -7 109 LUTs >33 52 N/A Verilog -7 107 LUTs >33 52 N/A VHDL -5 119 LUTs >33 50 N/A Verilog -5 119 LUTs >33 50 N/A VHDL -5 (ns) 26 Macrocells >33 50 N/A Verilog -5 (ns) 26 Macrocells >33 50 N/A Performance and utilization characteristics are generated using LCMXO2-1200HC-5MG132C with Lattice Diamond™ 1.2 design software. Performance and utilization characteristics are generated using LCMXO256C-3T100C with Lattice Diamond 1.2 design software. Performance and utilization characteristics are generated using LFE3-95EA-7FN1156C with Lattice Diamond 1.2 design software. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond 1.2 design software. Performance and utilization characteristics are generated using LC4256ZE-5TN100C, with Lattice ispLEVER® Classic 1.4 software software. References • Low Pin Count Interface Specification, Intel Corporation Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 7 Lattice Semiconductor LPC Bus Controller Revision History Date Version February 2009 01.0 Initial release. Change Summary July 2009 01.1 Added support for ispMACH 4000ZE CPLD family. Design separated into LPC host and LPC peripheral projects. October 2009 01.2 Added VHDL support. January 2010 01.3 Added support for LatticeXP2 device family. April 2010 01.4 Updated code and includes standardized VHDL syntax. November 2010 01.5 Added support for MachXO2 device family and Lattice Diamond design software. April 2011 01.6 Updated signal names in Reference Design Block Diagram, LPC Host Signal Descriptions table and LPC Peripheral Signal Descriptions table. Added support for LatticeECP3 device family and Lattice Diamond 1.2 design software. 8