IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH16543A REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP and TSSOP packages The LVCH16543A 16-bit registered transceiver is built using advanced dual metal CMOS technology. The LVCH16543A can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low in order to enter data from the A port or to output data from the B port. LEAB controls the latch function. When LEAB is low, the A to B latches are transparent. A subsequent low-to-high transition of LEAB puts the A latches in the storage mode. OEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using CEBA, LEBA, and OEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of this 16-bit registered transceiver can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16543A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16543A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OEBA 56 2OEBA 29 2CEBA 31 1CEBA 54 30 1LEBA 55 2LEBA 1OEAB 1 2OEAB 1CEAB 3 2CEAB 1LEAB 2 2LEAB 27 1A1 5 C1 2A1 1D 52 28 26 C1 15 42 1B1 1D C1 C1 1D 1D 2B1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4612/3 IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V 1OEAB 1 56 1OEBA TSTG Storage Temperature –65 to +150 °C 1LEAB 2 55 1LEBA IOUT DC Output Current –50 to +50 mA 1CEAB 3 54 1CEBA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA GND 4 53 GND 52 1B1 Continuous Current through each VCC or GND mA 5 ICC ISS ±100 1A1 1A2 6 51 1B2 VCC 7 50 VCC 1A3 8 49 1B3 1A4 9 48 1B4 1A5 10 47 1B5 GND 11 46 GND 1A6 12 45 1B6 1A7 13 44 1B7 Pin Names 1A8 14 43 1B8 xOEAB A-to-B Output Enable Input (Active LOW) 2A1 15 42 2B1 xOEBA B-to-A Output Enable Input (Active LOW) 2A2 16 41 2B2 xCEAB A-to-B Enable Input (Active LOW) 2A3 17 B-to-A Enable Input (Active LOW) 40 2B3 xCEBA xLEAB A-to-B Latch Enable Input (Active LOW) GND 18 39 GND xLEBA B-to-A Latch Enable Input (Active LOW) 2A4 19 38 2B4 2A5 20 37 2B5 2A6 21 36 2B6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 33 2B8 GND 25 32 GND 2CEAB 26 31 2CEBA xCEAB 2LEAB 27 30 2LEBA H 2OEBA X L L L L X H 28 2OEAB 29 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN DESCRIPTION Parameter Conditions Typ. xAx A-to-B Data Inputs or B-to-A 3-State Outputs(1) xBx B-to-A Data Inputs or A-to-B 3-State Outputs(1) FUNCTION TABLE (EACH 8-BIT SECTION)(1,2) Inputs CAPACITANCE (TA = +25°C, F = 1.0MHz) (1) Description NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP/ TSSOP TOP VIEW Symbol INDUSTRIAL TEMPERATURE RANGE Max. Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF Output Buffers xOEAB xAx to xBx xBx X X Storing High Z X H Storing High Z L L Transparent Current A Inputs H L Storing Previous A Inputs L H Transparent High Z H H Storing High Z X Storing Not Recommended xLEAB (3) NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance 2. A-to-B data flow is shown. B-to-A data flow is similar but uses xCEBA, xLEBA, and xOEBA. 3. Before xLEAB LOW-to-HIGH transition. Unit CIN Latch Status NOTE: 1. As applicable to the device type. 2 IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V — — — VI = 0.7V — — — VI = 0 to 3.6V — — ±500 IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current Test Conditions VCC = 3V VI = 2V IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 µA µA IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 44 pF 4 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH Propagation Delay, Transparent Mode tPHL xAx to xBx or xBx to xAx tPLH Propagation Delay tPHL xLEBA to xAx, xLEAB to xBx tPZH Output Enable Time tPZL xCEBA or xCEAB to xAx or xBx tPZH Output Enable Time VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit — 6.1 1.2 5.4 ns — 7.4 1.5 6.1 ns — 7.9 1.2 6.6 ns — 7.6 1 6.3 ns — 7.1 1.5 6.6 ns — 6.9 1.5 6.3 ns tPZL xOEBA or xOEAB to xAx or xBx tPHZ Output Disable Time tPLZ xCEBA or xCEAB to xAx or xBx tPHZ Output Disable Time tPLZ xOEBA or xOEAB to xAx or xBx tSU Set-up Time, data before CE↑ 1.1 — 1.1 — ns tSU Set-up Time, data before LE↑, CE LOW 1.1 — 1.1 — ns tH Hold Time, data after CE↑ 1.9 — 1.9 — ns tH Hold Time, data after LE↑, CE LOW 1.9 — 1.9 — ns tW Pulse Duration, xLEBA or xLEAB, xCEBA or xCEAB LOW 3.3 — 3.3 — ns Output Skew(2) — — — 500 ps tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF VIN tPLH tPHL VIH VT 0V LVC Link Propagation Delay DISABLE ENABLE VIH VT 0V CONTROL INPUT tPZL GND VOUT OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH D.U.T. 500Ω RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC Pulse (1, 2) Generator VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION CL tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC Link LVC Link Test Circuit for All Outputs Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open OUTPUT 1 tPLH1 tSK (x) tSK (x) tPLH2 tSU tH LOW-HIGH-LOW PULSE VOH VT VOL LVC Link VT tW HIGH-LOW-HIGH PULSE VOH VT VOL OUTPUT 2 tREM Set-up, Hold, and Release Times VIH VT 0V tPHL1 tH TIMING INPUT Test INPUT tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V VT LVC Link Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 LVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Temp. Range LVC X XX Bus-Hold Family XXXX XX Device Type Package PV PA PAG Shrink Small Outline Package Thin Shrink Small Outline Package TSSOP - Green 543A 16-Bit Registered Transceiver with 3-State Outputs, 5V Tolerant I/O Double-Density, ±24mA 16 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 H Bus-hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com