PIC32MZ EMBEDDED CONNECTIVITY (EC) PIC32MZ Embedded Connectivity (EC) Family Silicon Errata and Data Sheet Clarification The PIC32MZ Embedded Connectivity (EC) family of devices that you have received conform functionally to the current Device Data Sheet (DS60001191D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB X IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC32MZ Embedded Connectivity (EC) family silicon. Note: 4. 5. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A5). Data Sheet clarifications and corrections (if applicable) start on page 19, following the discussion of silicon issues. Note: Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB X IDE project. Configure the MPLAB X IDE project for the appropriate device and hardware debugger. Select Window > Dashboard, and then click the Refresh Debug Tool Status icon ( ). The part number and the Device and Revision ID values appear in the Output window. If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device and Revision ID values for the various PIC32MZ Embedded Connectivity (EC) family silicon revisions are shown in Table 1. The silicon revision level can be identified using the current version of MPLAB® X IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: SILICON DEVREV VALUES Part Number Device ID(1) PIC32MZ1024ECG064 0x05103053 PIC32MZ1024ECH064 0x05108053 PIC32MZ1024ECM064 0x05130053 PIC32MZ2048ECG064 0x05104053 PIC32MZ2048ECH064 0x05109053 PIC32MZ2048ECM064 0x05131053 PIC32MZ1024ECG100 0x0510D053 PIC32MZ1024ECH100 0x05112053 PIC32MZ1024ECM100 0x0513A053 PIC32MZ2048ECG100 0x0510E053 PIC32MZ2048ECH100 0x05113053 PIC32MZ2048ECM100 0x0513B053 Note 1: Revision ID for Silicon Revision(1) A3 A4 A5 0x3 0x4 0x5 Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet (DS60001191D) for detailed information on Device and Revision IDs for your specific device. 2013-2015 Microchip Technology Inc. DS80000588J-page 1 PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 1: SILICON DEVREV VALUES (CONTINUED) Part Number Device ID(1) PIC32MZ1024ECG124 0x05117053 PIC32MZ1024ECH124 0x0511C053 PIC32MZ1024ECM124 0x05144053 PIC32MZ2048ECG124 0x05118053 PIC32MZ2048ECH124 0x0511D053 PIC32MZ2048ECM124 0x05145053 PIC32MZ1024ECG144 0x05121053 PIC32MZ1024ECH144 0x05126053 PIC32MZ1024ECM144 0x0514E053 PIC32MZ2048ECG144 0x05122053 PIC32MZ2048ECH144 0x05127053 PIC32MZ2048ECM144 0x0514F053 Note 1: Revision ID for Silicon Revision(1) A3 A4 A5 0x3 0x4 0x5 Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet (DS60001191D) for detailed information on Device and Revision IDs for your specific device. DS80000588J-page 2 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Affected Revisions(1) Issue Summary A3 A4 A5 ADC INT0 Trigger 1. When using INT0 as a trigger source for ADC conversion, the INT0EP bit in the INTCON register controls which edge triggers the conversion (rising or falling). However, only a rising edge will trigger the conversion. ADC Data Format 2. Two’s complement (signed) input mode does not produce expected results. X X X Boot Flash Boot Sequence 3. When Boot Flash 1 is selected to be mapped to a Lower Boot Alias memory, the device may instead incorrectly map Boot Flash 2. X X X Comparator Voltage Reference Range Selection 4. The Comparator Voltage Reference (CVREF) module range selection (CVRR bit in the CVRCON register) does not function. X X X Ethernet Controller Alternate MII and RMII Configurations 5. The Alternate Ethernet pins, AERXDV and AERXCLK, are not available on 100-pin devices. X X X Ethernet Controller MII Configuration 6. X X X Ethernet Controller RMII Mode 7. MII pins that are not used by the Ethernet module during RMII operation may not be available for other functions. X X X X X X MII mode is not available on 64-pin devices. X X X I/O Port Open Drain 8. The Open Drain selection (ODCx) on I/O port pins is not available when the pin is configured for anything other than a standard port output. the Open Drain feature is not available for dedicated or remappable Peripheral Pin Select (PPS) output features. Oscillator FRC Tuning 9. Changing values in the OSCTUN register has no effect on the FRC accuracy. X X X Oscillator Ceramic Resonator 10. The Ceramic Resonator cannot be used as an input to the Oscillator module (OSC1/OSC2 pins). X X X Secondary Oscillator Crystal Oscillator 11. A crystal oscillator cannot be used as the input to the Secondary Oscillator (SOSCI/SOSCO pins). X X X Reserved — 12. — — — PowerSaving Modes Dream Mode 13. X X X PowerSaving Modes Sleep Mode 14. X X X SPI Maximum Speed Operation 15. X X X Reserved — 16. — — — X X X Dream mode does not function. The device may not exit Sleep mode. System Bus Note 1: — Permission Access The SPI clock speed does not meet the published specification. — When Permission Access is enabled, any access by an initiator 17. that is not allowed will not succeed; however, the status registers may not accurately report the violations. Only those issues indicated in the last column apply to the current silicon revision. 2013-2015 Microchip Technology Inc. DS80000588J-page 3 PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Affected Revisions(1) Issue Summary A3 A4 A5 USB Suspend Mode USB — USB Endpoint FIFO Reserved — The USB module will not function if the device enters Sleep 18. mode and the USB PHY is turned off by setting the USBSSEN bit in the CFGCON register to ‘1’. X X X 19. The USB module requires a start-up delay. X X X 20. Endpoint FIFOs cannot be read using 32-bit reads. X X X 21. — — — — X X X When the Watchdog Timer expires during Sleep mode, it causes a Reset rather than a non-maskable interrupt (NMI). X X X Watchdog Timer Window Mode When the Watchdog Timer is used in Window mode, the 22. module may issue a Reset even if the user tries to clear the module within the allowed window. Watchdog Timer Reset Trigger 23. PMP Address Lines PMP address lines block the use of lower-order functions when 24. the PMP is used but the corresponding bit in the PMAEN register is cleared. X X X I2 C Master Stop 25. The hardware Master Stop control does not function. X X X The Crypto Engine processes data in big-endian order rather 26. than little-endian. X X X X X X X X X X X X X X X X X X X X X X X X Upon a reset, the Transmit Buffer Empty Status (TXEMPTYIF) 35. bit in the SQI1INTSTAT register is cleared to zero instead of being set to one. X X X — — — Crypto Engine Byte Ordering Random Number Generator True Random Number Generator (TRNG) Mode 27. Flash Code-Protect 28. ADC Group Interrupt SQI Soft Reset 30. SQI XIP Mode 31. XIP mode is not operational. SQI Buffer Thresholds 32. SQI Interrupts SQI Read Clock Speed SQI Transmit Buffer Empty Status Reserved — 36. Comparator Offset 37. The Comparator offset does not meet the published specification X X X I/O Pins SOSCO Function 38. I/O pins shared with the SOSCO function cannot be used as general purpose input or output. X X X I2 C Overrun Interrupt 39. X X X Flash Memory Program Write Protect 40. X X X Note 1: TRNG mode does not function. Once the Code-Protect feature is enabled, a device cannot be erased using ICSP™ or JTAG. When using Channel Scan, Class 3 inputs are always part of 29. the Group Interrupt regardless of the setting of the AGIENx bits in the AD1IRQENx register. A Soft Reset is only possible when clock divider values are ‘0’ and ‘1’. Transmit and receive operation may not function properly. 33. Some Interrupt Signal Enable bits are set upon a Reset. 34. Clock for read operations does not meet the published specification. — A Slave interrupt is not generated during an overrun condition. The Program Write Protect (PWP) bits protect all Program Memory. X Only those issues indicated in the last column apply to the current silicon revision. DS80000588J-page 4 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Affected Revisions(1) Issue Summary A3 A4 A5 Oscillator POSC 41. A crystal oscillator cannot be used as an input to the Primary Oscillator (OSC1/OSC2 pins). X X 5V Tolerant I/O Pins Pull-ups 42. Internal pull-up resistors may not guarantee a logical ‘1’ on digital inputs on 5V tolerant pins. X X X ADC — 43. Certain ADC operating modes are not supported. X X X 44. The ADC module does not meet published specifications. X X X 45. Disabling the Prefetch does not invalidate contents. X X X Switching the System Clock (SYSCLK) to the Secondary PLL 46. (SPLL) causes a device Reset. This affects both software and hardware (IESO) clock switching. X X X ADC — Prefetch Module Disable Oscillator Clock Switch DMA Interrupt Trigger 47. A UART6 Transfer Done interrupt cannot be used to trigger DMA activity. X X X UART Auto-baud 48. The Automatic Baud Rate feature does not function to set the baud rate. X X X Reserved — 49. — — — Oscillator POSC Crystal 50. X X X Reserved — 51. — — — — I2 C SDA Hold Time 52. Lengthening the SDA hold time causes bus collisions in 1 MHz mode. X X X System Bus Simultaneous Access 53. CAN data may become corrupted during simultaneous operation. X X X Reserved — 54. — — — — Oscillator Reference Clock 55. The Reference Clock cannot use input frequencies greater than 100 MHz. X X X UART Synchronization 56. On a RX FIFO overflow, shift registers stop receiving data, which causes the UART to lose synchronization. X X X Timer1 Prescaler 57. Timer1 will not generate interrupts with an external asynchronous clock input and prescaler other than 1:1. X X X PMP Read 58. A PMP read does not generate an interrupt when the WAITE bit = 0. X X X PMP Wait Cycle 59. The pulse width of WAITE is ‘0’ when the WAITM<3:0> bits = 0000. X X X Reserved — 60. — — — X X X X X X Watchdog Timer Clearing Flash Panel Swap Note 1: — Crystal support for the Primary Oscillator does not meet published specifications for frequency and voltage. — Clearing the Watchdog Timer does not function as specified in 61. the data sheet. 62. The NVMKEY unlock sequence is not required to change the Flash panel order. Only those issues indicated in the last column apply to the current silicon revision. 2013-2015 Microchip Technology Inc. DS80000588J-page 5 PIC32MZ EMBEDDED CONNECTIVITY (EC) Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A5). 1. Module: ADC When using INT0 as a trigger source for ADC conversion, the INT0EP bit in the INTCON register controls which edge triggers the conversion (rising or falling). However, only a rising edge will trigger the conversion. Work around None. Affected Silicon Revisions A3 A4 A5 X X X 2. Module: ADC Two’s complement (signed) input mode does not produce the expected results. Signed mode selections are SHxMOD<1:0> = 01 for singleended or SHxMOD<1:0> = 11 for differential inputs. Work around 2 Use unipolar (unsigned) mode selections for all sample and holds. Where needed, convert the unsigned results to signed values. Unsigned 12-bit results can be converted to signed values by subtracting 2048 from the signed result. Use one of the following settings for SH0MOD through SH5MOD: • SHxMOD<1:0> = 00, for unsigned single-ended or • SHxMOD<1:0> = 10, for unsigned differential inputs Affected Silicon Revisions A3 A4 A5 X X X 3. Module: Boot Flash When Boot Flash 1 is selected to be mapped to a Lower Boot Alias memory, the device may instead incorrectly map Boot Flash 2. Work around Program an invalid sequence number (such as 0xFFFFFFFF or 0x00000000) into Boot Flash 2. This will force the device to map Boot Flash 1 into the Lower Boot Alias memory. Affected Silicon Revisions Work arounds: A3 A4 A5 Work around 1 X X X Use two's complement format for all inputs. The Two's complement format works properly when all sample and holds are set for this format. Singleended or Differential mode can still be selected independently. Use one of the following settings for SH0MOD through SH5MOD: • SHxMOD<1:0> = 01, for signed single-ended or • SHxMOD<1:0> = 11, for signed differential inputs 4. Module: Comparator Voltage Reference The Comparator Voltage Reference (CVREF) module range selection (CVRR bit in the CVRCON register) does not function. The default setting of the CVREF Range Selection bit (CVRR) is set to 0 to 0.67 CVRSRC, with a step size of CVRSRC/24, and cannot be changed. Work around Use an External Voltage Reference and adjust it appropriately to achieve the desired CVREF output. Affected Silicon Revisions DS80000588J-page 6 A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) 5. Module: Ethernet Controller 9. Module: Oscillator The Alternate Ethernet pins, AERXDV and AERXCLK, are not available on 100-pin devices. Changing values in the OSCTUN register has no effect on the FRC accuracy. Work around Work around Only use either the MII or RMII configuration. None. Affected Silicon Revisions Affected Silicon Revisions A3 A4 A5 A3 A4 A5 X X X X X X 6. Module: Ethernet Controller 10. Module: Oscillator MII mode is not available on 64-pin devices. In this mode, the Ethernet pin, ERXD2, is not available. The Ceramic Resonator cannot be used as an input to the Oscillator module (OSC1/OSC2 pins). Work around Work around Use the RMII or Alternate RMII configurations. Instead, use either a crystal oscillator or the external clock. Affected Silicon Revisions A3 A4 A5 X X X Affected Silicon Revisions A3 A4 A5 X X X 7. Module: Ethernet Controller MII pins that are not used by the Ethernet module during RMII operation are not released, and therefore, lower priority functions on these pins are not available in this mode. However, higher priority functions on these pins, such as EBI and analog inputs (for ADC and Comparators), can still be used. Work around None. 11. Module: Secondary Oscillator A crystal oscillator cannot be used as the input to the Secondary Oscillator (SOSCI/SOSCO pins). Work around Instead, use the external clock. Affected Silicon Revisions A3 A4 A5 X X X Affected Silicon Revisions A3 A4 A5 X X X 8. Module: I/O Port The Open Drain selection (ODCx) on I/O port pins is not available when the pin is configured for anything other than a standard port output. the Open Drain feature is not available for dedicated or remappable Peripheral Pin Select (PPS) output features. Work around 12. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 13. Module: Power-Saving Modes Dream mode is intended as a feature allowing DMA operation while the CPU is in Idle mode; however, Dream mode does not function. Work around None. Affected Silicon Revisions None. Affected Silicon Revisions A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. A3 A4 A5 X X X DS80000588J-page 7 PIC32MZ EMBEDDED CONNECTIVITY (EC) 14. Module: Power-Saving Modes The device may not exit Sleep mode. Work arounds Enable Flash in Sleep mode by clearing the Flash Sleep Mode Configuration bit, FSLEEP, in the DEVCFG0/ADEVCFG0 configuration register. Affected Silicon Revisions A3 A4 A5 X X X 15. Module: SPI The SPI clock speed does not meet the published specification. The maximum supported SPI clock speed is 27 MHz. 18. Module: USB The USB module will not function if the device enters Sleep mode and the USB PHY is turned off by setting the USBSSEN bit in the CFGCON register to ‘1’. Work around Keep the USB PHY operational in Sleep mode by setting the USBSSEN bit to ‘0’. Affected Silicon Revisions A3 A4 A5 X X X 19. Module: USB The USB module requires a start-up delay. Work around Work around None. When enabling the USB PLL, add a three second delay before turning on the USB module. Affected Silicon Revisions A3 A4 A5 X X X Affected Silicon Revisions A3 A4 A5 X X X 16. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 17. Module: System Bus When Permission Access is enabled, any access by an initiator that is not allowed will not succeed; however, the status registers may not accurately report the violations. Work around 20. Module: USB Endpoint FIFOs cannot be read using 32-bit reads. Work around Use 8-bit reads, reading each portion and copying into a 32-bit value. Affected Silicon Revisions A3 A4 A5 X X X None. Affected Silicon Revisions A3 A4 A5 X X X 21. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 22. Module: Watchdog Timer When the Watchdog Timer is used in Window mode, the module may issue a Reset even if the user tries to clear the module within the allowed window. Work around None. Affected Silicon Revisions DS80000588J-page 8 A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) 23. Module: Watchdog Timer When the Watchdog Timer expires during Sleep mode, it causes a Reset rather than a Nonmaskable Interrupt (NMI). Enable the I2C module by setting the ON bit in the I2CxCON register. To avoid using software delay loops, set up a Timer module with an interval equivalent to 1 BRG time. Load the Period register with the value equivalent to 1 BRG time. The Timer interrupt will occur for every 1 BRG time period. 5. 6. Work around None. Affected Silicon Revisions A3 A4 A5 X X X 24. Module: PMP PMP address lines block the use of lower-order functions when the PMP is used but the corresponding bit in the PMAEN register is cleared. For example, on 100-pin devices, pin 2 is EBIA5/AN34/PMA5/RA5; however, clearing bit 5 of the PMAEN register does not allow RA5 to function as GPIO even though PMA5 is not to be used with the PMP. Step 2: To create the Stop condition on the I2C bus, do not set the PEN bit in the I2CxCON register. Instead, a software routine should be invoked to provide delays and manipulate the GPIO (bitbang) that the I2C pins share that would create a Stop condition. A Stop condition occurs when SDA goes high 1 BRG time after SCL goes high. SCL goes high at least 1 BRG time after receiving ACK or NACK from the slave. When the Mater is ready to send a Stop condition, perform the following steps to create the Stop condition: Work around 1. 2. Higher-order functions are available and should be used instead. As described in the previous example, EBIA5 and AN34 would be available. 3. Start the Timer module. After 1 BRG time period has elapsed, disable the I2C module by clearing the ON bit in the I2CxCON register. After 1 more additional BRG time periods have elapsed, change the direction of the SDA pin to an input by setting the corresponding TRIS bit. After 2 more additional BRG time periods have elapsed, enable the I2C module by setting the ON bit in the I2CxCON register. Clear the LAT bit of the SDA pin. Clear the TRIS bit of the SDA pin to be configured as an output. Set the LAT bit of the SCL pin. Set the TRIS bit of the SCL pin to be configured as input. Stop the Timer module. Affected Silicon Revisions A3 A4 A5 X X X 25. Module: I2C The hardware Master Stop control (PEN bit) does not function. Work around Instead of hardware, use software to create the Stop condition, which involves execution of two separate steps. Step 1: During I2C software initialization, perform the following actions: 1. 2. 3. 4. Clear the LAT bit of the SDA pin. Clear the TRIS bit of the SDA pin to be configured as an output. Set the LAT bit of the SCL pin. Set the TRIS bit of the SCL pin to be configured as an input. 4. 5. 6. 7. 8. 9. Disabling the I2C module When users want to disable the I2C module for saving power, the following steps must be performed: 1. 2. Set the LAT bit of the SDA pin. Set the TRIS bit of the SDA pin to be configured as an input. Turn OFF the I2C module by clearing the ON bit in the I2CxCON register. 3. Affected Silicon Revisions 2013-2015 Microchip Technology Inc. A3 A4 A5 X X X DS80000588J-page 9 PIC32MZ EMBEDDED CONNECTIVITY (EC) 26. Module: Crypto Engine The Crypto Engine processes data in big-endian order rather than little-endian. Use the SWAPEN bit (CECON<5>) to bytereverse the data on input. After the data is processed, it must be byte-reversed by software or programmable DMA. Affected Silicon Revisions A3 A4 A5 X X X 27. Module: Random Number Generator True RNG mode does not function. 28. Module: Flash Under normal conditions, once the Code-Protect feature is enabled, a device cannot be accessed (read and/or write) through external interfaces such as ICSP™ or JTAG. To gain access through these interfaces, the Code-Protect bit must be erased, either by issuing an erase command (using ICSP or JTAG) or with the help of RTSP code. However, the device erase command using ICSP or JTAG does not function, once the Code-Protect feature is enabled. Work arounds: Work around 1 Instead, use Pseudo-Random Number Generator (PRNG) mode. Use the RTSP method to update code in a Code-Protect enabled device. In this mode, Flash memory can be erased and programmed with desired data. Affected Silicon Revisions Work around 2 Work around A3 A4 A5 X X X Use the RTSP method with the Live-Update feature of the device to erase the Code-Protect bit. Using this method, the application will erase the Code-Protect bit located in the inactive Boot Flash memory, and update this Boot Flash sequence to a higher number versus the active Boot Flash memory. On the next POR, Boot Flash memory with the erased Code-Protect bit will be used to configure the device, including Code-Protect configuration. Affected Silicon Revisions A3 A4 A5 X 29. Module: ADC When using Channel Scan, Class 3 inputs are always part of the Group Interrupt regardless of the setting of the AGIENx bits in the AD1IRQENx register. Conversions should only be part of the Group interrupt if a AGIENx bit is set. Work around None. Affected Silicon Revisions DS80000588J-page 10 A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) 30. Module: SQI 34. Module: SQI A SQI Soft Reset, which is controlled by the RESET bit in the SQI1CFG register does not work when the CLKDIV<7:0> bits in the SQI1CLKCON register have a value of two or higher. Clock speed for read operations does not meet the maximum specification (SQ10) of 50 MHz. For read operations the maximum clock is 25 MHz. Work around None. Set the CLKDIV<7:0> bits to a value of zero or one. Affected Silicon Revisions Affected Silicon Revisions A3 A4 A5 X X X 31. Module: SQI XIP mode is not operational (MODE<2:0> bits = 011 in the SQI1CFG register). Work around A3 A4 A5 X X X 35. Module: SQI For all resets, the Transmit Buffer Empty Status (TXEMPTYIF) bit in the SQI1INTSTAT register is cleared to zero instead of being set to one. Work around Work around None. Use PIO mode (MODE<2:0> bits = 001) or DMA mode (MODE<2:0> bits = 010). Affected Silicon Revisions Affected Silicon Revisions A3 A4 A5 X X X 32. Module: SQI Transmit and receive operation may not function properly. Work around Set the TXCMDTHR<5:0> and RXCMDTHR<5:0> bits in the SQI1CMDTHR register to multiples of 4 (32-bit aligned data buffers). Affected Silicon Revisions A3 A4 A5 X X X 33. Module: SQI The TXEMPTYISE, TXTHRISE, RXEMPTYISE, RXTHRISE, and CONEMPTYISE Interrupt Signal Enable bits in the SQI1INTSEN register are enabled on a device Reset. A3 A4 A5 X X X 36. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 37. Module: Comparator The Input Offset Voltage parameter (D300) is not within the published data sheet specification. The typical value is ±30 mV. Work around None. Affected Silicon Revisions A3 A4 A5 X X X 38. Module: I/O Pins Clear these bits by software. When the Secondary Oscillator is disabled through the FSOSCEN bit (DEVCFG1<6>), the SOSCO pin does not tri-state and is driven to Vss. An I/O pin shared with the SOSCO function cannot be used as a general purpose input or output. Affected Silicon Revisions Work around Work around A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. None. Affected Silicon Revisions A3 A4 A5 X X X DS80000588J-page 11 PIC32MZ EMBEDDED CONNECTIVITY (EC) 39. Module: I2C 42. Module: 5V Tolerant I/O Pins When operating in Slave mode, the I2C module does not trigger an interrupt when an overrun condition occurs. Work around Monitor the I2COV bit in the I2CxSTAT register using software. Affected Silicon Revisions A3 A4 A5 X X X 40. Module: Flash Memory Under normal conditions, setting the Program Write Protect (PWP) bits sets a mark below which the program memory is protected. Memory above this setting may be erased or written. However, the device protects all of program memory when any PWP bits are set. When internal pull-ups are enabled on 5V tolerant I/O pins, the level as measured on the pin and available to external device inputs may not exceed the minimum value of VIH, and therefore qualify as a logic “high”. However, with respect to the PIC32 device, as long as VDD 3V and the load doesn't exceed -50 µA, the internal pull-ups are guaranteed to be recognized as a logic “high” internally to the device. Work around It is recommend to only use external pull-ups: • To guarantee a logic “high” for external logic input circuits outside of the PIC32 device • For PIC32 device inputs, if the external load exceeds -50 µA or VDD < 3V Affected Silicon Revisions A3 A4 A5 X X X Work around 43. Module: ADC None. Note: Affected Silicon Revisions A3 A4 A5 X X X 41. Module: Oscillator Depending on the revision of silicon, a crystal oscillator cannot be used as the input to the Primary Oscillator (OSC1/OSC2 pins). Work around For Revision A3 and A4 silicon: Use an external clock or an internal FRC. The following ADC operating modes are not supported: • • • • • • For Revision A5 silicon: See Data Sheet Clarification 2: Primary Oscillator. Affected Silicon Revisions A3 A4 X X A5 A related code example is available in MPLAB Harmony, Version 1.02 or later. For more information, visit http://www.micochip.com/harmony. • • • Software polling of ADC status bits Manual software ADC triggering ADC interrupt modes (use DMA Interrupt mode) ADC SFR accesses by the CPU while ADC is operating ADC Boost or low-power mode. Individual ADC Input Conversion Requests (i.e., RQCNVRT bit in the ADCCON3 register) Use of ADC S&H Channels 0-4 except for calibration Any ADC references other than external VREF+ and VREF- pins ADC Differential mode Work around None. Affected Silicon Revisions DS80000588J-page 12 A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) 44. Module: ADC For Revision A5 silicon with date codes of 1503xxx (i.e., 1/12/15) or later: For Revision A3 and A4 silicon: Note: Note: A related code example is available in MPLAB Harmony, Versions 1.00 or 1.01. These versions are available in the MPLAB Harmony archive. For more information, visit http:// www.micochip.com/harmony. These devices will have ADC performance as specified in Table 3 and Table 4. For Revision A5 silicon with date codes prior to 1503xxx (i.e., 1/12/15): The ADC module does not meet the published Throughput Rate (AD51) and Full-Scale Input Range (AD12) specifications. The updated Maximum Throughput Rate (AD51) specification is 125 ksps, assuming 16x Oversampling mode. The updated Maximum Full-Scale Input Range is 2.5V for both Differential and Singled-Ended modes. The updated Minimum Full-Scale Input Range is -2.5V for Differential mode. TABLE 3: Symbol Device Supply AD01 AVDD These devices were not calibrated appropriately and may not perform to the specifications defined in Table 3 and Table 4. Work around None. Affected Silicon Revisions A3 A4 A5 X X X ADC1 MODULE SPECIFICATIONS AC CHARACTERISTICS(3,4) Param. A related code example is available in MPLAB Harmony, Version 1.02 or later. For more information, visit: http://www.micochip.com/harmony. Characteristics Module VDD Supply Standard Operating Conditions (see Notes 2,3,4): 2.5V to 3.6V (unless otherwise stated) Operating temperature 0°C TA +85°C Min. Typical Max. Units Greater of VDD – 0.3 or 2.5 VSS — V Conditions Module VSS Supply AD02 AVSS Reference Inputs Reference Voltage High AVSS + 2.0 AD05 VREFH — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 — AVDD V VREFH = VREF+ (Note 1) AD06 AD07 AVSS 2.0 — — VREFH – 2.0 AVDD V V (Note 1) — — 100 .002 150 1 A A ADC operating ADC off 0 — Lesser of VDD – 0.6 or 2.5 AVDD – VREF/2 10k V Single-ended mode only (Differential mode is not supported) — VREFL VREF Reference Voltage Low Absolute Reference Voltage (VREFH – VREFL) Current Drain AD08 IREF AD08a Analog Input AD12 VINH-VINL Full-Scale Input Range — V — — — V Common Mode Input AVSS + Voltage VREF/2 AD17 RIN Recommended — — (Note 1) Impedance of Analog For minimum sampling Voltage Source time Note 1: These parameters are not characterized or tested in manufacturing. 2: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is guaranteed, but not characterized. 3: Specifications are based on adherence to the requirements listed in Section 28.1 “ADC Configuration Requirements”. 4: All data was collected using a dedicated external precision voltage source connected to VREF+ and with VREF- tied to external AVSS. External VREF+ and VREF- must be used at all times. AD14 VINCM 2013-2015 Microchip Technology Inc. DS80000588J-page 13 PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 3: ADC1 MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS(3,4) Param. Symbol Characteristics Standard Operating Conditions (see Notes 2,3,4): 2.5V to 3.6V (unless otherwise stated) Operating temperature 0°C TA +85°C Min. Typical Max. ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr Resolution 8 data bits AD21c INL Integral Nonlinearity -5 ±3 +5 AD22c DNL Differential Nonlinearity -1 ±1 +2 AD23c GERR Gain Error -10 ±3 +10 AD24c EOFF Offset Error -9 ±1 +9 Units Conditions bits — LSb VINL = VREF- = VREFL = 0V, VREF+ = VREFH = 2.5V LSb VINL = VREF- = VREFL = 0V, VREF+ = VREFH = 2.5V LSb VINL = VREF- = VREFL = 0V, VREF+ = VREFH = 2.5V LSb VINL = VREF- = VREFL = 0V, VREF+ = VREFH = 2.5V — Guaranteed AD25e — Monotonicity — — — Dynamic Performance AD31b SINAD Signal to Noise and — 42 — dB — Distortion AD34b ENOB Effective Number of bits — 7 — bits — Note 1: These parameters are not characterized or tested in manufacturing. 2: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is guaranteed, but not characterized. 3: Specifications are based on adherence to the requirements listed in Section 28.1 “ADC Configuration Requirements”. 4: All data was collected using a dedicated external precision voltage source connected to VREF+ and with VREF- tied to external AVSS. External VREF+ and VREF- must be used at all times. DS80000588J-page 14 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) TABLE 4: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS(2,4,5) Param. Symbol Characteristics No. Standard Operating Conditions (see Notes 3,4,5): 2.5V to 3.6V (unless otherwise stated) Operating temperature 0°C TA +85°C Min. Typ.(1) Max. Units Conditions Clock Parameters AD50 TAD ADC Clock Period 1000 — 2000 ns — — — — — Throughput Rate AD51 FTP SH0 – SH4 (Class 1 Inputs) SH5 (Class 2 and 3 Inputs) Conversion Pipeline SH0-SH4 functionality is not supported. Sampling must be performed on SH5 only. See Note 3. Single Class 2 or 3 input, 1 MHz ADC Clock, Source impedance 10 k, ksps SAMC = ‘b00001010, Assumes there are no pending sample conversion operations at time of trigger. See Note 3. — — 66.6 — — 1 Msps — — — TAD — Timing Parameters AD60 TSAMP Sample Time for SH0-SH4 (Class 1 Inputs) Sample Time for SH5 (Class 2 and 3 Inputs) AD62 TCONV SH0-SH4 functionality is not supported. Sampling must be performed on SH5 only. Source Impedance 10 k, 1 MHz ADC clock 10 — — TAD Conversion Time (after sample time is complete) — — 10 TAD SH0-SH4 functionality is not supported. Sampling must be performed on SH5 only. For SH5, TSAMP + TCONV provides Trigger to data ready timing; AD64 TCAL Calibration Time — 160 — TAD — AD65 TWAKE Wake-up time from LowPower Mode — 2 — TAD — Note 1: 2: 3: 4: 5: These parameters are not characterized, or tested in manufacturing. The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is guaranteed, but not characterized. Assuming correct PLL configuration (i.e., 192 MHz system clock). Specifications are based on adherence to the requirements listed in Section 28.1 “ADC Configuration Requirements”. All data was collected using a dedicated external precision voltage source connected to VREF+ and with VREF- tied to external AVSS. External VREF+ and VREF- must be used at all times. 2013-2015 Microchip Technology Inc. DS80000588J-page 15 PIC32MZ EMBEDDED CONNECTIVITY (EC) 45. Module: Prefetch The Prefetch module does not invalidate buffer contents when the module is disabled by setting the PREFEN<1:0> bits to ‘b00. Work around To disable the Prefetch module, execute four 32-bit NOP commands before and after setting the PREFEN<1:0> bits to ‘b00. Affected Silicon Revisions A3 A4 A5 X X X 48. Module: UART The UART Automatic baud rate feature is intended to set the baud rate during run-time based on external data input. However, this feature does not function. Work around None. Affected Silicon Revisions A3 A4 A5 X X X 49. Module: Reserved 46. Module: Oscillator Switching the System Clock (SYSCLK) to the System PLL (SPLL) causes a device Reset. This affects both software and hardware (IESO) clock switching. The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 50. Module: Oscillator Work around The Primary Oscillator does not meet the published specifications for crystal support. To switch the clock source, disable IESO, and execute the following steps in software: Work around 1. Reduce the speed of all peripheral buses to 128:1 through PBCLKx (where ‘x’ 7) and reduce the speed of the CPU bus to 128:1 through PBCLK7. Perform the clock switch. Set the speed of the CPU bus to the previous clock switch divisor and set the speed of the peripheral buses to their previous clock switch divisor. 2. 3. Affected Silicon Revisions A3 A4 A5 X X X 47. Module: DMA To use a crystal with the Primary Oscillator, the following limitations on voltage and frequency must be observed: • 2.4V VDD 3.6V • Crystal Speed = 12 MHz Additional details can be found in Data Sheet Clarification 2: Primary Oscillator. Affected Silicon Revisions A3 A4 A5 X X X 51. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. The UART6 Transfer Done Interrupt (190) cannot be used to trigger a DMA activity, such as a start or a stop. Work around None. Affected Silicon Revisions A3 A4 A5 X X X DS80000588J-page 16 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) 52. Module: I2C 56. Module: UART Setting the SDAHT bit in the I2C module lengthens the time that the SDAx pin is held after SCLx falls to 300 ns from 100 ns. However, the actual hold time is longer than 300 ns, and as a result, it causes a bus collision when operating at 1 MHz. Work around During a RX FIFO overflow condition, the shift register stops receiving data. This causes the UART to lose synchronization with the serial data stream. The only way to recover from this is to turn the UART OFF and ON until it synchronizes. This could require several OFF/ON sequences. Do not set the SDAHT bit when operating the I2C module at 1 MHz. Work arounds Affected Silicon Revisions Avoid the RX overrun condition by ensuring that the UARTx module has a high enough interrupt priority such that other peripheral interrupt processing latencies do not exceed the time to overrun the UART RX buffer based on the application baud rate. Alternately or in addition to, set the URXISEL bits in the UxSTA register to generate an earlier RX interrupt based on RX FIFO fill status to buy more time for interrupt latency processing requirements. A3 A4 A5 X X X 53. Module: System Bus When operating the system bus at 8 MHz, having the CAN module access one RAM bank while the Crypto module accesses the other RAM bank can cause the CAN data to become corrupted. Work around Operate the system bus at frequencies faster than 8 MHz. Affected Silicon Revisions A3 A4 A5 X X X Work around 1: Work around 2: If avoiding RX FIFO overruns is not possible, implement a ACK/NAK software handshake protocol to repeat lost packet transfers after restoring UART synchronization. Affected Silicon Revisions A3 A4 A5 X X X 54. Module: Reserved The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. 55. Module: Oscillator 57. Module: Timer1 Timer1 will not generate interrupts with an external asynchronous clock input and prescaler other than 1:1. The Reference Clock Module cannot accept input frequencies greater than 100 MHz. Therefore, SYSCLK cannot be used as an input if the SYSCLK operates at frequencies greater than 100 MHz. Work around Work around Alternately, use External Synchronous Clock mode if this is an option for the application Instead of using SYSCLK, use PBCLK1 as the input, which is limited to 100 MHz and is synchronized to SYSCLK. Affected Silicon Revisions A3 A4 A5 X X X 2013-2015 Microchip Technology Inc. With External Clock Asynchronous mode, use the 1:1 Prescaler mode with a software timer overflow variable to keep track of the desired equivalent of the greater than 1:1 prescaler setting. Affected Silicon Revisions A3 A4 A5 X X X DS80000588J-page 17 PIC32MZ EMBEDDED CONNECTIVITY (EC) 58. Module: PMP When the PMP is set to Master mode, and the WAITE bit is set to ‘0’ to have no wait states after the read strobe, a read operation does not generate an interrupt. Work around None. 61. Module: Watchdog Timer The data sheet specifies that a 16-bit write to the WDTCLRKEY<15:0> bits is required to clear the Watchdog Timer. However, a 16-bit write does not work. In addition, writing to the WDTCONCLR, WDTCONSET, and WDTCONINV registers clears the Watchdog Timer, which should not occur. Work around Affected Silicon Revisions A3 A4 A5 X X X 59. Module: PMP If the WAITM<3:0> bits = 0000, the end phase should be 1 TPB. However, the end phase does not delay. Use a 32-bit write to the WDTCON register to clear the Watchdog Timer. Affected Silicon Revisions A3 A4 A5 X X X 62. Module: Flash The SWAP bit (NVMCON<7>) can be changed without executing the NVMKEY unlock sequence. Work around None Work around Affected Silicon Revisions A3 A4 A5 X X X 60. Module: Reserved None. Affected Silicon Revisions A3 A4 A5 X X X The issue previously reported in a prior revision of this errata, is no longer relevant and was removed. DS80000588J-page 18 2013-2015 Microchip Technology Inc. PIC32MZ EMBEDDED CONNECTIVITY (EC) Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS60001191D): Note: Corrections in tables are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: System Bus Arbitration The following legal notification was omitted from Section 4.2 “System Bus Arbitration” of the Memory Organization chapter. 2. Module: Primary Oscillator To use the Primary Oscillator with a crystal, only the following crystal is supported for PIC32MZ EC family devices: XTAL = ABLS-LR-12.000MHZ-18-D-R-T No other crystals are guaranteed to function 100% over voltage, temperature, and population. Adequate testing required in your application to ensure reliable operation. The following configuration. figure shows the required (To USB PLL) 4.2 System Bus Arbitration VDD Note: The System Bus interconnect implements one or more instantiations of the SonicsSX® interconnect from Sonics, Inc. This document contains materials that are (c) 2003-2015 Sonics, Inc., and that constitute proprietary information of Sonics, Inc. SonicsSX is a registered trademark of Sonics, Inc. All such materials and trademarks are used under license from Sonics, Inc. 2013-2015 Microchip Technology Inc. C1 = 2 pF Primary Oscillator (POSC) OSC1 XTAL 4.7 M 4.7 k To SYSCLK Mux RF Enable C2 = 4 pF OSC2 DS80000588J-page 19 PIC32MZ EMBEDDED CONNECTIVITY (EC) APPENDIX A: REVISION HISTORY Updated for revision A5 silicon. Rev A Document (11/2013) Initial release of this document, issued for revision A3 silicon. This version includes the following issues: 1 (ADC), 2 (ADC), 3 (Boot Flash), 4 (Comparator Voltage Reference), 5 (Ethernet Controller), 6 (Ethernet Controller), 7 (Ethernet Controller), 8 (I/O Port), 9 (Oscillator), 10 (Oscillator), 11 (Secondary Oscillator), 12 (LPRC Oscillator), 13 (Power-Saving Modes), 14 (Power-Saving Modes), 15 (SPI), 16 (SQI), 17 (System Bus), 18 (USB), 19 (USB), 20 (USB), 21 (USB), 22 (Watchdog Timer), 23 (Watchdog Timer), 24 (PMP), 25 (I2C), 26 (Crypto Engine), and 27 (Random Number Generator). Rev B Document (12/2013) Updated issues 7 (Ethernet 14 (Power-Saving Modes). Rev E Document (9/2014) Controller) and Updated silicon issues 24 (PMP), 25 (I2C), and 41 (Oscillator). Added silicon issues 46 (Oscillator), 47 (DMA), 48 (UART), 49 (Deadman Timer), 50 (Oscillator), and 51 (ADC). Removed data sheet clarifications 1 through 6 and 8 through 11. Issue 7 was retained, which is now issue 1 (ADC Configuration Requirements). Added data sheet clarifications 2 (I/O Ports) and 3 (Primary Oscillator). Rev F Document (10/2014) Content in issue 51, which was included in the previous errata version, was removed and this issue have been marked as Reserved. Updated issue 44 (ADC). Content in issue 21, which was included in a previous errata version, was removed and this issue has been marked as Reserved. Added data sheet clarification 4 (Internal FRC Oscillator.). Added data sheet clarification issues 1 (Power-Down Current) and 2 (Operating Conditions), and silicon issues 28 (Flash) and 29 (ADC). Updated silicon issues 25 (I2C), 30 (SQI), 43 (ADC), 44 (ADC), and 50 (Oscillator). Rev C Document (4/2014) Updated for revision A4 silicon. Content in issues 12 and 16, which was included in a previous errata version, was removed and these issues have been marked as Reserved. Added silicon issues 30 (SQI), 31 (SQI), 32 (SQI), 33 (SQI), 34 (SQI), 35 (SQI), 36 (Comparator), 37 (Comparator), 38 (I/O Pins), 39 (I2C), 40 (Flash Memory), 41 (Oscillator), 42 (5V Tolerant I/O Pins), 43 (ADC), 44 (ADC), and 45 (Prefetch). Added data sheet clarification issues 3 (Internal FRC Accuracy), 4 (Internal LPRC Accuracy), 5 (Internal Backup FRC (BFRC) Accuracy), 6 (ADC1 Module Specifications and Timing Requirements), 7 (ADC Configuration Requirements), 8 (SQI Timing Requirements), 9 (DC Temperature and Voltage Specifications.), 10 (Recommended Minimum Connection), and 11 (I/O Ports). Rev D Document (5/2014) Updated silicon issues 43 (ADC) and 44 (ADC) and data sheet clarifications 6 (ADC1 Module Specifications and Timing Requirements) and 7 (ADC Configuration Requirements). Rev G Document (12/2014) Updated Data Sheet Clarification 1 (ADC Configuration Requirements) and 3 (Primary Oscillator). Added silicon issues 52 (I2C), 53 (System Bus), 54 (Power-Saving Modes), 55 (Oscillator), and 56 (UART). Added Data Sheet Clarification 5 (Internal LPRC Oscillator). Rev H Document (7/2015) Content in issues 36, 49, and 54, which was included in the previous errata version, has been removed and these issues have been marked as Reserved. Updated silicon issue 50 (Oscillator). Added silicon issues 57 (Timer1), 58 (PMP), 59 (PMP), 60 (Oscillator), 61 (Watchdog Timer), and 62 (Flash). Removed data sheet clarification 1 (ADC Configuration Requirements), 2 (I/O Ports), 3 (Internal FRC Oscillator), 4 (Internal LPRC Oscillator), and 5 (USB). Updated data sheet clarification issue 2 (Primary Oscillator), which is now issue 2. Added data sheet clarification 1 (System Bus Arbitration). Rev J Document (9/2015) Removed data sheet clarification issue 60 (Oscillator). DS80000588J-page 20 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-786-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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