UTMI+ Specification

UTMI+ Specification, Revision 1.0, February 25th , 2004
UTMI+ Specification
Revision 1.0
Page 1
UTMI+ Specification, Revision 1.0, February 25th , 2004
Revision History
Revision
Issue Date
th
0.7
0.71
0.72
April 24 , 2002
April 29th, 2002
June 4th, 2002
0.8
0.81
0.82
June 17th, 2002
July 3rd, 2002
July 22nd, 2002
0.83
October 23rd, 2002
0.9rc
January 8th, 2003
0.9rc2
January 17th, 2003
0.9rc3
February 7th, 2003
0.9
February 21st, 2003
0.91
October 13th, 2003
0.92
November 13th, 2003
1.0
February 25th, 2004
Comment
Initial version
Reworked the different levels
Extended definition of OpMode
Added outline on how to implement multi-port host controllers using
UTMI+
Promoted to version 0.8 to allow review by OTG workgroup members
Clarified Optional charge pump, rewording for grammer and clarity
Added signal IdPullup
Added signal FsSerialMode and legacy interface signals
Added signal TxBitstuffEnable / TxBitstuffEnableH
Removed signal SessEnd
Changed FsSerialMode into FsLsSerialMode
Added SessEnd signal back because there is still uncertainty that an
OTG system will work without this signal in all conditions.
Added clarifications
Added clarification of long EOP generation
Modified suspend/resume behaviour in host mode
Changed IdPullup timing
Added chapter on T&MT connector
Added section on ambiguities in UTMI v1.05 spec
Added clarification on HostDisconnect signal when PHY is in suspend
Changed TermSelect definition for LS devices
Changed clarification for RxActive/RxValid during transmit
Added clarification for LineState
Added more clarification to LineState
Promoted to version 0.9 by OTG workgroup
Changed time between IdPullup being asserted and IdDig having a valid
value.
Updated LineState tables
Changed behaviour of OpMode during chirp sequence
Updated disclaimer
Changed time T1 during resume to be minimum 16 LS bit times. This
allows the transceiver to complete the resume signaling in a correct
way.
Version approved by the Promoters and Adopters of UTMI+/ULPI
"The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters
and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual
property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's
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UTMI+ Specification, Revision 1.0, February 25th , 2004
or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of
use of the Specification."
Table of Contents
1.
Introduction................................................................................................................................. 6
1.1 Purpose.................................................................................................................................. 6
1.2 Audience................................................................................................................................ 6
1.3 Disclaimers............................................................................................................................. 6
1.4 Relevant Documents................................................................................................................ 6
2.
Definition of Different levels........................................................................................................ 7
2.1 UTMI+ level 0 : USB2.0 peripherals ........................................................................................... 7
2.1.1 Additional requirements and clarifications on top of UTMI ................................................ 8
2.2 UTMI+ level 1 : USB2.0 peripherals, host controllers and On-the-Go devices (HS and FS only)...... 9
2.2.1 Additional signals for UTMI+ level 1. .............................................................................. 9
2.2.2 Generation of long EOP ............................................................................................. 15
2.2.3 Data line pulsing........................................................................................................ 16
2.2.4 HS keep-alive generation............................................................................................ 16
2.2.5 UTMI+ level 1 transceiver core used in a USB2.0 peripheral........................................... 17
2.3 UTMI+ level 2 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / no hub
support)...................................................................................................................................... 17
2.3.1 XcvrSelect(1:0) .......................................................................................................... 18
2.3.2 LS keep-alive generation ............................................................................................ 19
2.3.3 LineState.................................................................................................................. 19
2.4 UTMI+ level 3 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / preamble)
20
2.4.1 XcvrSelect(1:0) .......................................................................................................... 20
2.4.2 Multi-port host controllers ........................................................................................... 21
3.
Explanation of different signaling modes................................................................................. 22
3.1 Chirp sequence..................................................................................................................... 22
3.2 Suspend / Resume signaling for downstream facing ports ......................................................... 22
3.3 Transmit error reporting for downstream facing ports ................................................................. 24
3.4 Selection of different signaling modes for upstream and downstream facing ports ........................ 25
4.
T&MT Connector ....................................................................................................................... 26
Figures
Figure 1 : UTMI+ levels ...........................................................................................................................7
Figure 2 : UTMI+ level 0 entity diagram (16-bit interface).............................................................................8
Figure 3 : UTMI+ level 1 entity diagram................................................................................................... 10
Figure 4 : HostDisconnect behaviour (signals are not on scale)................................................................. 14
Figure 5 : Data line pulsing for a Dual-Role B-device ................................................................................ 16
Figure 6 : HS keep-alive generation ........................................................................................................ 16
Figure 7 : UTMI+ level 2 entity diagram................................................................................................... 18
Figure 8 : LS keep-alive generation......................................................................................................... 19
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UTMI+ Specification, Revision 1.0, February 25th , 2004
Figure 9 : Reset sequence for a HS peripheral connected to a HS Host Controller ...................................... 22
Figure 10 : Resume signaling on downstream facing ports........................................................................ 23
Figure 11 : Transmit error reporting for downstream facing ports................................................................ 24
Tables
Table 1 : Filtering of LineState .................................................................................................................9
Table 2 : UTMI+ level 1 transceiver core used in a USB2.0 peripheral ........................................................ 17
Table 3 : LineState for upstream facing ports (DpPulldown and DmPulldown = 0)........................................ 20
Table 4 : LineState for downstream facing ports(DpPulldown and DmPulldown = 1)..................................... 20
Table 5 : Different signaling modes for upstream and downstream facing ports ........................................... 25
Table 6 : T&MT connector pinning[1] ........................................................................................................ 26
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UTMI+ Specification, Revision 1.0, February 25th , 2004
Acronyms and Terms
FS
HS
IC
LS
OTG
SE0
USB
USB-IF
UTMI
Full-Speed
High-Speed
Integrated Circuit
Low-Speed
On-The-Go
Single Ended Zero
Universal Serial Bus
USB Implementers Forum
USB 2.0 Transceiver Macrocell Interface
Contributors
Bart Vertenten
Srinivas Pattamatta
Jerome Tjia
Chung Wing Yan
Farran Mackay
Chris Kolb
Christopher Meyers
David Cobbs
David Wooten
Eric Huang
Ravikumar Govindaraman
Saleem Mohammad
Michael Pennell
Nabil Takla
Paul Berg
Peter Hirt
Alok Kaushik
Rob Douglas
Andy King
Zong Liang Wu
Hemal Doshi
Philips
Philips
Philips
Philips
Philips
ARC
ARC
Cypress
Cypress
Synopsys
Synopsys
Synopsys
SMSC
Innovative
MCCI
ST Microelectronics
ST Microelectronics
Mentor Graphics
Mentor Graphics
TransDimension
Portalplayer Inc
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UTMI+ Specification, Revision 1.0, February 25th , 2004
1. Introduction
1.1
Purpose
The purpose of this document is to specify an interface to which USB 2.0 ASIC, ASSP, discrete PHY, system peripherals
and IP vendors can develop USB2.0 products. The existing UTMI specification describes an interface only for USB2.0
peripherals. The UTMI specification can not be used to develop USB 2.0 host or On-The-Go peripherals. The intention
of this UTMI+ specification is to extend the UTMI specification to standardize the interface for USB 2.0 hosts and USB
2.0 On-The-Go peripherals. The UTMI+ specification defines and standardizes the interoperability characteristics with
existing USB 2.0 hosts and peripherals.
1.2
Audience
This document is intended for developers and vendors of USB 2.0 ASIC, ASSP, discrete PHY, system, peripheral and IP
products.
1.3
Disclaimers
This document is a recommendation of the contributors indicated in the title pages. It does not necessarily reflect the
position of their respective companies, the OTG working group, or the position of the USB-IF.
1.4
Relevant Documents
•
•
•
•
•
•
•
USB 2.0 Transceiver Macrocell Interface Specification, version 1.05, Steve McGowan, March 29th, 2001
USB 2.0 Transceiver and Macrocell Tester(T&MT) Interface Specification, Wes Talarek, version 1.2, April 4th,
2001
On-The-Go Supplement to the USB 2.0 Specification (www.usb.org/developers/onthego)
USB 2.0 Specification (www.usb.org/developers/docs.html)
OTG Certification Specification Revision 0.7
ECN_27%_ Resistor (www.usb.org/app/members/ecn_html)
OTG Labeling Specification Revision 0.63
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2. Definition of Different levels
The level of complexity needed for a high-speed USB On-The-Go peripheral can be very different. Especially the
complexity needed for the host controller part is very dependent on the targeted peripheral list. Therefore the UTMI+
specification is built up in progressive levels. The base (level 0) for UTMI+ is the UTMI specification version 1.05[1].
Level 1 is targeted for USB On-The-Go Dual-Role-Devices that must be capable of generating HS and FS traffic. Level 2
adds the possibility of generating LS traffic towards LS devices that are directly connected to the USB On-The-Go DRD.
Finally, Level 3 adds the possibility to have also USB 2.0 FS hubs in the USB tree and let the host controller part of the
USB On-The-Go DRD communicate with LS devices that are connected to the USB FS hub controller.
Any transceiver core that is developed to a given level shall be compliant with all levels below that level.
In Figure 1, a general overview is given on how the different levels layer on each other.
UTMI+ level 3
USB2.0 peripheral, host controllers, On-the-Go devices
(HS, FS, LS, preamble packet)
UTMI+ level 2
USB2.0 peripheral, host controllers, On-the-Go devices
(HS, FS, LS but no preamble packet)
UTMI+ level 1
USB2.0 peripherals, host controllers and On-the-Go devices
(HS and FS only)
UTMI+ level 0 =
UTMI spec. version 1.05 + clarification
USB2.0 peripherals only
Figure 1 : UTMI+ levels
2.1
UTMI+ level 0 : USB2.0 peripherals
The base of the UTMI+ specification is the UTMI specification version 1.05. This is defined as UTMI+ level 0. The
transceiver cores that pretend to be UTMI+ level 0 compliant can be used in a USB2.0 peripheral design. These cores
cannot be used to implement USB2.0 Hosts or On-the-Go peripherals without additional logic.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
16-bit interface
DataIn(15:8)
DataOut(15:8)
DataIn(7:0)
DataOut(7:0)
TXValid
TXReady
TXValidH
RXActive
DataBus16_8
RXValid
RXValidH
Reset
CLK
SuspendM
RXError
XcvrSelect
DP
TermSelect
DM
OpMode(1:0)
LineState(1:0)
Figure 2 : UTMI+ level 0 entity diagram (16-bit interface)
During the implementation of UTMI+, it was found that some parts of the UTMI spec were not clearly specified or could
be interpreted in different ways. This caused that integration of UTMI transceiver from one vendor with the USB device
core from another vendor was not always working. To remove these problems from future designs any core that is
UTMI+ compliant must implement the requirements described in section 2.1.1.
For more details on how to implement a UTMI+ level 0 transceiver see also the UTMI spec[1]. In Figure 2 a general
overview is given of all interface signals needed for UTMI+ level 0 transceiver with 16-bit interface. For a UTMI+ level 0
transceiver with 8-bit interface the TXValidH, RXValidH, DataBus16_8, DataIn(15:8) and DataOut(15:8) signals are not
needed.
2.1.1
2.1.1.1
Additional requirements and clarifications on top of UTMI
Use of LineState for timers
The UTMI spec mentions several times that LineState is the most accurate signal to be used for timing a certain state on
the USB bus. It is not a hard requirement for the USB device core designer to use this signal. He can use whatever
method he wants as long as correct behavior on the USB bus is guaranteed without forcing additional constraints on the
PHY design.
2.1.1.2
LineState filtering
Minimal filtering should be applied to LineState to ensure that skew on the DP/DM signals does not generate unwanted
SE0 or SE1 states between J and K states. For instance, for FS mode Table 7-9 of the USB 2.0 Specification identifies the
“Width of SE0 interval during differential transition” to be 14ns max. These SE0 states are noise to the SIE and should
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UTMI+ Specification, Revision 1.0, February 25th , 2004
not be propagated by LineState. To be able to filter worst case SE0 noise, the transceiver should implement filtering as
indicated in Table 1.
Filtering should only occur on an SE0. If during filtering the SE0 a non-SE0 event occurs then the filtering should stop
and linestate behaviour continues as previously.
Bus speed
Low-speed mode filtering
Full-speed mode filtering
High-speed mode filtering
8-bit interface (CLK = 60MHz)
14 CLK cycles
2 CLK cycles
2 CLK cycles
16-bit interface (CLK = 30 MHz)
7 CLK cycles
1 CLK cycle
1 CLK cycle
Table 1 : Filtering of LineState
2.1.1.3
RxActive/RxValid during transmit
The UTMI PHY must internally block the USB receive path once a USB transmit has begun. The receive path can be
unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.
2.1.1.4
TxReady behavior when not bitstuffing
TxReady must be used in chirp mode. If TxReady is not asserted by the UTMI PHY when the USB device core was
sending a chirp, it can cause the device core to lock-up if the device core is holding the transmit data on the bus until it
sees TxReady asserted. By explicitly requiring that TxReady must be asserted for all transmit data including chirp data,
this problem can be avoided.
2.1.1.5
Receive End Delay
At the end of page 59 of the UTMI spec v.1.05 there is a contradiction between the number of bit times and the number
of clock cycles for Total Receive End Delay for an interface running at 30MHz. 6 30 MHz clock cycles is actually 96 bit
times. For a 16 bit transceiver interface, the Total Receive End Delay must be between 32-96 bit times or 2-6, 30 MHz
CLKs
2.2
UTMI+ level 1 : USB2.0 peripherals, host controllers and On-the-Go devices (HS
and FS only)
Any transceiver core that has an interface compliant with UTMI+ level 1, has all signals compliant with UTMI+ level 0. A
transceiver core with UTMI+ level 1 interface can be used for USB2.0 peripheral, host or On-the-Go device designs that
support only HS and FS traffic. If a host controller needs to be able to communicate with a LS device some additional
functions are required that are not part of level1 (cfr section 2.3).
Transceivers implementing level 1 may optionally include an integrated charge pump to supply VBUS current to the OnThe-Go connector. If the charge pump is integrated within the transceiver macrocell then a description of the charge
pump must be given in the transceiver datasheet to allow integrators to build a complete USB On-The-Go peripheral. If
the charge pump is not integrated within the transceiver macrocell then the optional DrvVbus signal may be omitted from
the macrocell.
2.2.1
Additional signals for UTMI+ level 1.
USB On-The-Go peripherals have some additional capabilities and therefore some new signals need to be implemented.
1.
2.
A USB On-The-Go dual role peripheral needs to be capable to distinguish between a mini-A and mini-B plug.
A USB On-The-Go peripheral has to know if Vbus is below or above a certain voltage level.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
3.
4.
5.
6.
A USB On-The-Go peripheral must be able to drive Vbus and charge or discharge Vbus.
A USB On-The-Go dual role peripheral needs to be able to switch the pull-up resistor on DP and the pull-down
resistor on both DP and DM.
The downstream facing port of a host controller must have 15 kOhm pull-down resistors on both DP and DM lines.
Some signals are needed to do the correct switching of the resistors
The host controller must be able to detect a disconnect of a peripheral. This is possible for a FS peripheral by using
LineState, but it is not possible for HS peripherals using the current UTMI specification. Therefore an additional
signal needs to be implemented. To make the design of the digital SIE easier, this new disconnect signal will be used
in both speeds (HS/FS) to indicate if there is a device connected or not.
In Figure 3 an overview is given of all signals needed for the UTMI+ level 1 interface.
UTMI+ level 1 entity
16-bit interface
UTMI+ level 0 entity
16-bit interface
DataIn(15:8)
DataOut(15:8)
DataIn(7:0)
DataOut(7:0)
TXValid
TXReady
TXValidH
RXActive
DataBus16_8
RXValid
RXValidH
Reset
SuspendM
CLK
RXError
XcvrSelect
DP
TermSelect
DM
OpMode(1:0)
LineState(1:0)
HostDisconnect
IdPullup
IdDig
DpPulldown
DmPulldown
DrvVbus
AValid
ChrgVbus
BValid
DischrgVbus
VbusValid
SessEnd
TxBitstuffEnable
TxBitstuffEnableH
Tx_Enable_N
Rx_DP
Tx_DAT
Rx_DM
Tx_SE0
Rx_RCV
FsLsSerialMode
Figure 3 : UTMI+ level 1 entity diagram
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.2.1.1
IdDig / IdPullup
The id signal is indicating the state of the ID pin on the USB mini receptacle. This pin makes it able to determine which
kind of plug is connected. To save power, there is also an IdPullup signal. Only when this IdPullup signal is high, the
analog Id line will be sampled and the IdDig signal will indicate the correct value.
IdPullup
Signal that enables the sampling of the analog Id line.
0b : Sampling of Id pin is disabled. IdDig is not valid
1b : Sampling of Id pin is enabled.
Indicates whether the connected plug is a mini-A or mini-B. This is only valid when IdPullup
is set to 1b. It must be valid within 50ms after IdPullup is set to 1b.
0b : connected plug is a mini-A
1b : connected plug is a mini-B
IdDig
2.2.1.2
AValid
The AValid signal is used to indicate if the session for an A-peripheral is valid. This signal is 1b when Vbus is above 2V.
Avalid
2.2.1.3
Indicates if the session for an A-peripheral is valid (0.8V < Vth < 2V).
0b : Vbus < 0.8V
1b : Vbus > 2V
BValid
The BValid signal is used to indicate if the session for a B-peripheral is valid. This signal is 1b when Vbus is above 4V.
Bvalid
2.2.1.4
Indicates if the session for an B-peripheral is valid (0.8V < Vth < 4V).
0b : Vbus < 0.8V
1b : Vbus > 4V
VbusValid
The VbusValid signal is used to determine whether or not the voltage on Vbus is at a valid level for operation. The
minimum threshold for the Vbus comparator is 4.4V
VbusValid
2.2.1.5
Indicates if the voltage on Vbus is at a valid level for operation (4.4V < Vth < 4.75V).
0b : Vbus < 4.4V
1b : Vbus > 4.75V
SessEnd
The SessEnd signal is used to determine if the voltage on Vbus is below its B-Device Session End threshold.
SessEnd
Indicates if the voltage on Vbus (0.2V < Vth < 0.8V).
1b : Vbus < 0.2V
0b : Vbus > 0.8V
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UTMI+ Specification, Revision 1.0, February 25th , 2004
According to the definition in the OTG supplement of the USB 2.0 specification, it must be possible to build a USB OTG
DRD without the SessEnd signal. The detection can be done in the digital controller section. 50ms after Vbus is
discharged, the voltage on Vbus must be below the B-device Session End Threshold. This is correct in a normal working
environment. However it is always possible that in systems for some reason the Vbus does not go down to levels less
than SessEnd (e.g. standard host, short circuit on the charge pump so that Vbus is always on, etc). Therefore it is seen
that this signal is a must and is preferred to be used in order to have a correct working system in all cases.
2.2.1.6
DrvVbus
The DrvVbus is an enable signal to drive 5V on Vbus. The DrvVbus signal is optional for transceiver
implementations,depending on whether an integrated charge pump is implemented. The DrvVbus signal is mandatory for
SIE implementing an interface that is compliant with level 2 of UTMI+.
DrvVbus
2.2.1.7
This signal enables to drive 5V on Vbus
0b : do not drive Vbus
1b : drive 5V on Vbus
DischrgVbus
If DischrgVbus is active then Vbus will be pulled down through a resistor to ground. This is needed to discharge Vbus
before initiating SRP. B-peripherals use this signal to ensure that Vbus is at a low enough voltage before starting SRP.
The minimum time that DischrgVbus needs to be asserted is 50 ms.
DischrgVbus
The signal enables discharging Vbus.
1b : discharge Vbus through a resistor (this has to be active for at least 50 ms)
0b : do not discharge Vbus through a resistor
2.2.1.8
ChrgVbus
If ChrgVbus is active then Vbus will be pulled up through a resistor. This is done to initiate SRP.
The minimum time that ChrgVbus needs to be asserted is 30 ms.
ChrgVbus
The signal enables charging Vbus.
1b : charge Vbus through a resistor (this has to be active for at least 30 ms)
0b : do not charge Vbus through a resistor
2.2.1.9
DpPulldown / DmPulldown
DpPulldown
DmPulldown
This signal enables the 15k Ohm pull-down resistor on the DP line.
0b : Pull-down resistor not connected to DP
1b : Pull-down resistor connected to DP
This signal enables the 15k Ohm pull-down resistor on the DM line.
0b : Pull-down resistor not connected to DM
1b : Pull-down resistor connected to DM
These two signals are used to switch on the 15k Ohm pull-down resistors on both DP and DM for a host.
These signals should not been toggled during normal operation.
Using the TermSelect signal can do switching the pull-up resistor for a peripheral.
For a peripheral both signals should been set to 0b. For a host controller both signals should been set to 1b.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.2.1.10 HostDisconnect
HostDisconnect
This signal is used for all types of peripherals connected to it. It is only valid when
DpPulldown and DmPulldown are 1b. If DpPulldown and DmPulldown are not 1b then the
behaviour of HostDisconnect is undefined.
As long as there is no peripheral connected, this signal will be 1b. If a peripheral is
connected, then the value of this signal will be 0b.
Internally there are two disconnect signals, one that detects disconnect in HS mode and one that detects
connect/disconnect in FS mode. Depending on XcvrSelect one of these signals is routed to the actual output port
HostDisconnect. If in HS mode a disconnect is detected, the HostDisconnect signal will be set to 1b. At that moment the
Macrocell will be switched to FS mode (XcvrSelect = 01b).
In FS/LS mode, a disconnect condition occurs if the transceiver detects a SE0 signaling for 2.5 us and a connect
condition occurs if the transceiver detects non-SE0 signaling for 2.5 us. If a disconnect is detected, hostdisconnect is
asserted and if a connect is detected it is deasserted.
In HS mode, a disconnect condition is evaluated every time a HS SOF packet is sent. If a disconnect is detected,
hostdisconnect is asserted.
When hostdisconnect is asserted in high-speed mode the transceiver is placed into full-speed mode by the host core.
Also when the host core wants to put the USB bus (which has a hi-speed device connected) into suspend mode, it
switches the transceiver from hi-speed mode into full-speed mode. At that moment the connected hi-speed device is still
in hi-speed and the USB bus state is still in SE0. To prevent false full-speed connect/disconnects, the hostdisconnect
signal cannot be updated for 4 ms from the transition into full-speed. After the 4 ms recovery time the status of the fullspeed connect/disconnect can be determined and the hostdisconnect signal updated accordingly. The 4 ms of recovery
time allows the peripheral device connected to the host to detect the suspend signaling on the USB bus, move into the
FS suspend mode and bring the USB bus to the Full Speed Idle state (Jstate).
However if the transceiver is put into power down (which can happen for power consumption reasons), the
hostdisconnect signal is deasserted immediately (in both cases : device connected or not) and the 4 ms recovery time is
not required. The core attached must look at LineState to see if the state of the USB bus changes. If it does, the core
should bring the transceiver out of power down and look at the hostdisconnect signal. When the transceiver comes out
of power down the hostdisconnect signal must have the correct value within 1 ms after the clock is back up and running.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
Disconnect of HS peripheral
SOF tokens on
the USB bus
Hi-speed device
disconnected
USB bus
HS disconnect
FS/LS disconnect
TermSelect
HostDisconnect
4ms recovery time
Transition from operational to suspend
SOF tokens on
the USB bus
Device goes into suspend
J-state
USB bus
HS disconnect
FS/LS disconnect
Host puts bus in suspend mode
TermSelect
HostDisconnect
4ms recovery time
Figure 4 : HostDisconnect behaviour (signals are not on scale)
2.2.1.11 OpMode
OpMode(1:0)
These signals select between various operational modes :
00b : Normal operation (The UTMI+ transceiver automatically appends the SYNC and EOP
pattern)
01b : Non-driving
10b : Disable bit stuffing and NRZI encoding
11b : Normal operation without automatic generation of SYNC and EOP. NRZI encoding is
always enabled. Bit stuffing depends on the value of TxBitstuffEnable and
TxBitstuffEnableH. This is only valid when XcvrSelect is set to 00b. If OpMode is set to 11b
together with XcvrSelect not equal to 00b, the behavior of the transceiver is undefined.
The extension of OpMode is done to have control on all bits that are sent on the USB bus. This mode has to be used in
order to send a HS keep-alive packet on the USB bus (cfr. section 2.2.4).
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.2.1.12 TxBitstuffEnable / TxBitstuffEnableH
These signals is only used when Opmode is set to 11b. While OpMode is set to 11b the automatic generation of SYNC
and EOP is disabled. However if for some reason somebody wants to have control over generation the SYNC and EOP
pattern, there must be a way to indicate to the transceiver that a Bitstuff error must be generated on the bus for the EOP.
These signals make it also possible to transmit high-speed USB packets while the transceiver is put into OpMode = 11b.
TxBitstuffEnable
TxBitstuffEnableH
Indicates if the data on the DataOut(7:0) lines needs to be bitstuffed or not.
0b : Bitstuffing is disabled
1b : Bitstuffing is enabled
Indicates if the data on the DataOut(15:8) lines needs to be bitstuffed or not.
0b : Bitstuffing is disabled
1b : Bitstuffing is enabled
This signal is only required when the 16 bit mode is selected.
2.2.1.13 FsLsSerialMode
The FsLsSerialMode signal indicates how the digital core signals the FS and LS packets to the transceiver. If this signal
is set to 0b, the packets are communicated via the parallel interface as defined in the UTMI spec.
If the signal is set to 1b, the packets are communicated using the serial interface as indicated below.
The reason to add this to the interface is to make it possible to reuse existing FS/LS host controller IP without changing
its interface. This also makes that if this interface is used for the host controller part, it is possible to implement complete
host controller functionality using a UTMI+ level 1 compliant interface. This could be seen as a contradiction with the
actual naming of the levels. However the leveling naming is referring to the situation where only the parallel interface is
used.
FsLsSerialMode
Tx_Enable_N
Tx_DAT
Tx_Se0
Rx_DP
Rx_DM
Rx_RCV
2.2.2
0b : FS and LS packets are sent using the parallel interface.
1b : FS and LS packets are sent using the serial interface.
Active low output enable signal.
Differential data at D+/D- output
Force Single-Ended Zero
Single-ended receive data, positive terminal.
The data is only valid if FsLsSerialMode is set to 1b
Single-ended receive data, negative terminal
The data is only valid if FsLsSerialMode is set to 1b
Receive data
The data is only valid if FsLsSerialMode is set to 1b
Generation of long EOP
Most of the HS USB packets that are generated consist of an 8-bit EOP. Only when a SOF has to be sent on the USB
bus, the EOP must be 40 bits. To generate the correct packets on the USB bus, the transceiver must check the PID value
of every packet that is transmitted in HS mode. When the PID is equal to SOF, the transceiver must generate a 40-bit
EOP. In all other HS cases the transceiver generates an 8-bit EOP on the USB bus
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.2.3
Data line pulsing
Data line pulsing can be implemented by using the XcvrSelect, DpPullDown, DmPullDown and TermSelect signals.
In the figure 5 the period T has to be between 5 and 10 ms.
XcvrSelect
01b
DpPulldown
DmPulldown
TermSelect
T
Figure 5 : Data line pulsing for a Dual-Role B-device
2.2.4
HS keep-alive generation
In certain cases the debug port of an EHCI compliant host controller needs to be able to transmit a HS keep-alive SYNC
packet. This is a SYNC pattern without any other data or EOP. The figure underneath indicates how this HS keep-alive
can be generated.
CLK
TxValid
DataIn(7:0)
00h
80h
TxReady
XcvrSelect(1:0)
OpMode(1:0)
00b
11b
Figure 6 : HS keep-alive generation
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.2.5
UTMI+ level 1 transceiver core used in a USB2.0 peripheral
A transceiver core that is compliant to UTMI+ level 1 can be used together with a SIE that is compliant with the UTMI
specification to develop a USB 2.0 peripheral. To be able to do some signals have to be tied off or can be left open. This
is indicated in Table 1.
Signal
DpPulldown
DmPulldown
HostDisconnect
IdDig
IdPullup
AValid
BValid
VbusValid
Direction
In
in
out
out
in
out
out
out
SessEnd
DrvVbus
DischrgVbus
ChrgVbus
TxBitStuffEnable
TxBitStuffEnableH
FsLsSerialMode
Tx_Enable_N
Tx_DAT
Tx_SE0
Rx_DP
Rx_DM
Rx_RCV
out
in
in
in
in
in
in
in
in
in
out
out
out
Value when used in USB2.0 peripheral
0b
0b
Open
Open
0b
Open
Open
same use as defined in UTMI+ level 2
0b : Vbus < 4.4V
1b : Vbus > 4.75V
Open
0b
0b
0b
0b
0b
0b
1b
0b
0b
Open
Open
Open
Table 2 : UTMI+ level 1 transceiver core used in a USB2.0 peripheral
2.3
UTMI+ level 2 : USB2.0 peripherals, host controllers and On-the-Go devices (HS
/ FS / LS / no hub support)
If a host controller must be able to handle LS traffic some more extensions are needed. This level covers all USB 2.0
traffic described in the USB specification except a host sending a LS packet to a USB LS device that is connected
through a FS hub (PRE PID handling). This is covered in the next level.
•
•
The host controller must be able to transmit packets at LS.
The host controller must be able to send LS keep-alive packets on a low-speed bus. A LS keep-alive packet is
equal to a LS EOP.
Figure 7 gives an overview of all signals.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
UTMI+ level 2 entity
16-bit interface
UTMI+ level 1 entity
16-bit interface
UTMI+ level 0 entity
16-bit interface
DataIn(15:8)
DataOut(15:8)
DataIn(7:0)
DataOut(7:0)
TXValid
TXReady
TXValidH
RXActive
DataBus16_8
RXValid
RXValidH
Reset
CLK
SuspendM
RXError
XcvrSelect(1)
XcvrSelect(0)
DP
TermSelect
OpMode(1:0)
DM
LineState(1:0)
HostDisconnect
IdPullup
IdDig
DpPulldown
DmPulldown
DrvVbus
AValid
ChrgVbus
BValid
DischrgVbus
VbusValid
SessEnd
TxBitstuffEnable
TxBitstuffEnableH
Tx_Enable_N
Rx_DP
Tx_DAT
Rx_DM
Tx_SE0
Rx_RCV
FsLsSerialMode
Figure 7 : UTMI+ level 2 entity diagram
2.3.1
XcvrSelect(1:0)
XcvrSelect(1:0)
Transceiver Select. This signal selects between the LS, FS and HS transceivers :
00b : HS transceiver
01b : FS transceiver
10b : LS transceiver
11b : Reserved (cfr. Section 2.4.1 for definition of this value in level 3)
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UTMI+ Specification, Revision 1.0, February 25th , 2004
2.3.2
LS keep-alive generation
To generate a LS keep-alive packet on a LS bus, the signals on the UTMI+ level 2 interface need to be asserted as
indicated in Figure 8. The SIE will set TxValid with XcvrSelect in the mode Low Speed transceiver enabled and TxData
0xA5 on the 8 LSB. The transceiver will decode this assertion and determine that it needs to send a low-speed keep-alive
packet on the USB bus.
LS Bits
0
2
1
4
3
CLK (not to scale)
XcvrSelect
"10"
TxValid
DataIn(7:0)
0xA5
TxReady
NRZI Encoded Data
Idle ('J' State)
SE0
'J' State driven Idle ('J' State)
by host
Figure 8 : LS keep-alive generation
2.3.3
LineState
Table 3 gives an overview on the conditions that cause the different values that must appear on the LineState signal for
upstream facing ports. The same for downstream facing ports is indicated in Table 4. The values of Linestate that are
indicated as “Invalid” should never appear in that mode.
The top part of the table indicates the control inputs the transceiver to indicate the operational mode, while the bottom
part of the table specifies the receiver input conditions used by the transceiver to generate the line state output signals.
In full-speed and low-speed mode, LineState(0) always reflects DP and LineState(1) reflects DM.
E.g. if for a downstream facing port, the XcvrSelect is set to “00”, TermSelect is set to ‘0’ and OpMode is set to “00”,
LineState will indicate “SE0” if there is Squelch in the PHY. If there is not(Squelch) the value on LineState will be “JState”
Low
Speed
10
1
SE0
Full
Speed
01/11
1
SE0
High
Speed
00
0
Squelch
01
LS-K
FS-J
! Squelch
10
LS-J
FS-K
Invalid
11 (SE1)
SE1
SE1
Invalid
Mode
XcvrSelect
TermSelect
00 (SE0)
Line
State
(1:0)
Page 19
Chirp
00
1
Squelch
! Squelch &
HS_Differential_Receiver_Output
! Squelch &
! HS_Differential_Receiver_Output
Invalid
UTMI+ Specification, Revision 1.0, February 25th , 2004
Table 3 : LineState for upstream facing ports (DpPulldown and DmPulldown = 0)
Low
Speed
10
1
don’t care
SE0
Full
Speed
01/11
1
don’t care
SE0
High
Speed
00
0
00/01/11
Squelch
01
LS-K
FS-J
! Squelch
10
LS-J
FS-K
Invalid
11 (SE1)
SE1
SE1
Invalid
Mode
XcvrSelect
TermSelect
OpMode
00 (SE0)
Line
State
(1:0)
Chirp
00
0
10
Squelch
! Squelch &
HS_Differential_Receiver_Output
! Squelch &
! HS_Differential_Receiver_Output
Invalid
Table 4 : LineState for downstream facing ports(DpPulldown and DmPulldown = 1)
2.4
UTMI+ level 3 : USB2.0 peripherals, host controllers and On-the-Go devices (HS
/ FS / LS / preamble)
This is a further enhancement of level 2. In this level it will be feasible to handle LS traffic that has to be sent from the
host to the LS device via a FS hub. In level 2, the host controller part of the USB On-The-Go DRD is only feasible to
communicate with LS device directly connected to the host if the parallel interface is used. The additional functionality
for this level is that the host part must be able to generate preamble packets.
2.4.1
XcvrSelect(1:0)
XcvrSelect(1:0)
Transceiver Select. This signal selects between the LS, FS and HS transceivers :
00b : HS transceiver
01b : FS transceiver
10b : LS transceiver
11b : Send a LS packet on a FS bus or receive a LS packet.
If XcrvSelect is 11b, the transceiver will send a preamble packet at FS before sending the LS
packet. In receive mode it will wait to receive an LS packet with the LS transceiver enabled.
The transceiver must send all data (both FS preamble packet and the LS data) with FS
signaling (fast rise & fall times & opposite polarity)
XcvrSelect controls a number of transceiver related elements, for instance.
Selects the receiver (source for the Mux block) in the receive path. For 00b, it will select the HS receive path. For 01b,
it will select the FS receive path and for 10b or 11b it will select the LS receive path.
It is used as a gating term for enabling the HS, FS or LS Transmit Driver
Switch internal UTMI clocks to shared logic.
In the USB2.0 specification[2] section 8.6.5 there is a definition on how the signals on the USB bus have to look like
when sending a LS packet on a FS bus. This has to be handled inside the UTMI+ core. The XcvrSelect will be put to 11b
together with the actual data that has to be sent at low-speed. If the transceiver is in host mode, it will first issue a PRE
packet at full-speed, then it will drive the bus to the Idle state and time for the hub setup time before sending OUT the
actual data at low-speed.
Note : If XcvrSelect is 11b, then the transceiver also needs to detect a FS EOP as the end of a packet. This is needed
because when a LS device is babbling, the hub between this device and the host controller will disable this port and stop
Page 20
UTMI+ Specification, Revision 1.0, February 25th , 2004
the packet that is sent to the host controller with a FS EOP. This is to prevent a babble condition on the port of the host
controller.
2.4.2
Multi-port host controllers
UTMI+ transceivers that are compliant with level 3 can be used to implement a multi-port host controller. If a transceiver
vendor wants to support multi-port host applications then they may optionally provide a mechanism to slave the
multiple transceiver to a single UTMI clock for connection to a single SIE in the host controller. There are different
mechanisms to implement this. The implementation of this mechanism is beyond the scope of this specification.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
3. Explanation of different signaling modes
3.1
Chirp sequence
Figure 9 specifies how the signals need to be applied for both a host controller and a peripheral during reset when a
high-speed peripheral is connected to a high-speed host controller. The signals are given for the case that both the
peripheral and the host controller are using a UTMI+ level 1 or higher compliant transceiver core.
All the timing of the different events must be implemented in the peripheral or host controller core. The core must also
indicate the difference between sending a chirp-K and a chirp-J to the transceiver. It can do this by using the TxData
lines.
FS Detect
Host Drives
Device Responds
Host Responds
HS Idle
HostMode
XcvrSelect(1:0)
01(FS)
00(HS)
TermSelect
OpMode(1:0)
00(normal)
10(Chirp)
00(normal)
TXValid
LINESTATE
J
SE0
S
E
0
Device Chirp K
HOST
Host Chirp KJKJKJ...
SE0
DEVICE
HostMode
XcvrSelect(1:0)
01(FS)
00(HS)
TermSelect
OpMode(1:0)
00(normal)
10(Chirp)
00(normal)
TXValid
LINESTATE
J
SE0
Device Chirp K
S
E
0
Host Chirp KJKJKJ...
J
SE0
USB
DP
DM
Figure 9 : Reset sequence for a HS peripheral connected to a HS Host Controller
3.2
Suspend / Resume signaling for downstream facing ports
This section only applies for downstream facing ports. A port is configured as a downstream facing port when both
dppulldown and dmpulldown are active.
When a downstream facing port is transmitting a resume (full speed data K), it must be ended with either a low speed
EOP (if previously in low / full speed before suspend) or a transition to high speed idle (if previously in high speed).
In Figure 10 these different cases are shown.
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UTMI+ Specification, Revision 1.0, February 25th , 2004
In this figure, the timing T1 is needed to ensure that the data path from the low speed state machine is not cut off before
the LS EOP has been transmitted fully. This time needs to be minimum 16 LS bit times.
To differentiate between HS and FS, the transceiver will not drive a final FS-J at the end of resume if the transceiver is
switched to HS mode no later than ½ LS bit time (4 FS bit times) before the end of the SE0. The transceiver should be
switched in HS mode no earlier than when SE0 is detected on LineState. If this is not taken into account there is a risk
that the transceiver is switched while “K” is still driven on the USB bus.
For resume signaling on upstream facing port please refer to the UTMI specification.
LS traffic
LS Suspend
Resume-K
XcvrSelect
EOP
LS traffic
10b
00b
OpMode
10b
TxData
00b
00h
TxValid
TermSelect
FS traffic
FS Suspend
Resume-K
EOP
FS traffic
XcvrSelect
01b or 11b
01b
01b or 11b
OpMode
00b
10b
00b
TxData
00h
TxValid
TermSelect
T1
HS traffic
XcvrSelect
OpMode
FS Suspend
00b
Resume-K
01b
00b
00b
10b
TxData
00h
TxValid
TermSelect
Figure 10 : Resume signaling on downstream facing ports
Page 23
HS traffic
00b
UTMI+ Specification, Revision 1.0, February 25th , 2004
3.3
Transmit error reporting for downstream facing ports
In FS/LS, to indicate that there was a problem with the data transmitter (e.g. buffer underrun) a bit stuff error is generated
followed by an EOP. To do this OpMode is switched to 10b to disable the encoding and 00h is loaded into DataIn for at
least 1 clock cycle before negating TxValid. However this causes conflict with device resume generation that does not
add and EOP when the encoding is not active.
Therefore transmit error reporting will only be carried out for at least 1 byte/word. Any greater than this and the
generation of the EOP is not guaranteed.
DataIn
OpMode
00h
10b
00b
00b
TxValid
Figure 11 : Transmit error reporting for downstream facing ports
Page 24
UTMI+ Specification, Revision 1.0, February 25th , 2004
3.4
Selection of different signaling modes for upstream and downstream facing
ports
For upstream facing ports TermSelect is used as a switch for enabling the pull-up resistor. If XcvrSelect(1) is set to logic
‘0’, TermSelect controls the pull-up resistor on DP. If XcvrSelect is set to “10”, TermSelect is logic ‘1’ and both
DpPulldown and DmPulldown are set to logic ‘0’, the pull-up resistor is on DM is switched on. If both DpPulldown and
DmPulldown are 1b then TermSelect is used to switch on/off the HS terminations. When DpPulldown and DmPulldown
are 1b the pull-up resistor on DP or DM is never switched on.
OpMode for downstream facing ports is not only used for disabling bit stuffing but also to distinguish between chirp
mode and normal operation mode.
Analog Transceiver State
OTG Host Low Speed
Host Low Speed
Host Low Speed Suspend
Host Low Speed Resume
Peripheral Low Speed
Peripheral Low Speed Suspend
OTG Host Full Speed
Host Full Speed
OTG Peripheral Full Speed
Peripheral Full Speed
OTG Host High Speed
Host High Speed
Host HS/FS Suspend
Host HS/FS Resume
OTG Peripheral High Speed
Peripheral High Speed
Peripheral HS/FSSuspend
Peripheral Resume
Host Chirp
Peripheral Chirp
Tristate Drivers
XcvrSelect(1:0)
10b
10b
10b
10b
10b
10b
01b or 11b
01b or 11b
01b
01b
00b
00b
01b
01b
00b
00b
01b
01b
00b
00b
--b
TermSelect
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
0b
0b
1b
1b
0b
0b
1b
1b
0b
1b
-b
OpMode(1:0)
00b
00b
00b
10b
00b
00b
00b
00b
00b
00b
00b or 11b
00b or 11b
00b or 11b
10b
00b or 11b
00b or 11b
00b or 11b
10b
10b
10b
01b
DpPulldown
1b
1b
1b
1b
0b
0b
1b
1b
0b
0b
1b
1b
1b
1b
0b
0b
0b
0b
1b
0b
-b
Table 5 : Different signaling modes for upstream and downstream facing ports
Page 25
DmPulldown
1b
1b
1b
1b
0b
0b
1b
1b
1b
0b
1b
1b
1b
1b
1b
0b
0b
0b
1b
0b
-b
UTMI+ Specification, Revision 1.0, February 25th , 2004
4. T&MT Connector
For UTMI there was a standard connector defined to easily test function cores with transceivers. This definition is
extended to suite the UTMI+ extensions. The definition of the different pins is given in Table 6.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Function
Ddir[3]
GND
TxBitstuffEnableH
GND
SesEnd
BValid
IdDig
VDD
GND
Tx_DAT
ChrgVbus
DmPulldown
GND
DrvVbus
Vstatus4
VDD
Reset
OpMode1
XcvrSelect0
TermSelect
GND
SuspendM
LineState0
GND
LineState1
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Function
TxBitstuffEnable
GND
VBUS_out
VbusValid
VendorID_0
Data15
GND
Data13
Data11
GND
Data9
Data7
VDD
GND
Force_RxErr
Data5
Data3
GND
Data1
Vstatus0
GND
VBUS_in
Rx_DM
DC_PSNT_N
HostDisconnect
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Function
GND
System Clock
GND
GND
FsLsSerialMode
AValid
VDD
DischrgVbus
Tx_SE0
TxValid
IdPullup
GND
DpPulldown
IFType0
GND
RxActive
OpMode0
GND
VDD
Vstatus1
Vstatus2
RxValid
GND
RxError
TxReady
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
GND
ValidH
XcvrSelect1
Tx_Enable_N
GND
VDD
Data14
Data12
GND
Data10
Data8
VDD
Data6
IFType1
Clk
Data4
GND
Data2
Data0
GND
Vstatus3
Rx_DP
RX_RCV
VendorID_1
GND/3v3-PSUSHDM[2]
Table 6 : T&MT connector pinning [1]
[1] All non-standard T&MT pinning is marked in italics
[2] Pin 100 (GND in T&MT definition) has been designated 3V3-PSU-SHDN. The pin 100 "redefinition" is to do with the implementation
of the daughter card. It is a way of choosing whether the daughter card should be supplied through the T&MT connector or from the
on board power supplies. If pin 100 is connected to ground then the T&MT supplies the power. If it is left floating then the on board
power supplies are used.
[3] If DDIR is active then all bidirectional signals become inputs to the transceiver (i.e. for the transceiver to transmit data onto the
cable DDIR must be set to logic ‘1’).
Page 26