CBTL06GP212 High performance DisplayPort switch with high common-mode voltage support

CBTL06GP212
High performance DisplayPort switch with high
common-mode voltage support
Rev. 1 — 2 May 2012
Product brief
1. General description
The CBTL06GP212 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express
applications at Generation 2 (‘Gen2’) speeds. It provides four differential channels
capable of 1 : 2 switching or 2 : 1 multiplexing (bidirectional and AC-coupled) PCI Express
or DisplayPort signals, using high-bandwidth pass-gate technology. It provides support for
high common-mode/bias voltage on the high speed differential channels. Additionally, it
provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or
DDC (Direct Display Control) signals, for a total of six channels on the display side. The
AUX and DDC channels provide a four-position multiplexer such that an additional level of
multiplexing can be accomplished when AUX and DDC I/Os are on separate pins of the
display source device.
The CBTL06GP212 is designed for Gen2 speeds, at 5.0 Gbit/s for PCI Express or
5.4 Gbit/s for DisplayPort. It consumes 2 mA current (typical) in operational mode and
provides a shutdown function to support battery-powered applications.
A typical application of CBTL06GP212 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass gate
technology), the CBTL06GP212 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
2. Features
 1 : 2 switching or 2 : 1 multiplexing of DisplayPort
(v1.2 - 5.4 Gbit/s) or PCI Express (v2.0 - 5.0 Gbit/s)
signals
 4 high-speed differential channels with
2 : 1 muxing/switching for DisplayPort or
PCI Express signals
 1 channel with 4 : 1 muxing/switching
for AUX at 1 Mbit/s or DDC signals
 1 channel with 2 : 1 muxing/switching
for single-ended HPD signal
 High-bandwidth analog pass-gate technology
 Supports a wide range of common-mode/bias
voltage on high speed differential channels
 Supports high-speed signal switching over a wide
common-mode range and differential swing
 RON on DP high-speed channels: 6 Ω
 Low insertion loss:
 −0.5 dB at 100 MHz
 −1.5 dB at 1.35 GHz
 −2.5 dB at 2.7 GHz
 Low crosstalk: −35 dB at 2.7 GHz
 Low off-state isolation: −30 dB at 2.7 GHz
 Low return loss: −8 dB at 2.7 GHz
 Very low intra-pair skew (5 ps typical)
 Very low inter-pair skew (< 80 ps)
 3 dB bandwidth at 5 GHz
 Switch/multiplexer position select CMOS input
 Shutdown mode CMOS input
 Supports backdrive protection
 Single 3.3 V power supply
CBTL06GP212
NXP Semiconductors
High performance DisplayPort 1.2 switch
 Operation current of 2 mA typical, shut-down current 10 μA maximum
 ESD 2 kV HBM, 500 V CDM
 Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
 Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
 Docking stations
 Notebook computers
 Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Type number
Solder process
CBTL06GP212EE/G
[1]
Pb-free (SnAgCu
solder compound)
Package
Name
Description
Version
TFBGA48
plastic thin fine-pitch ball grid array package;
48 balls; body 5 × 5 × 0.8 mm[1]
SOT918-1
Total height including solder balls after printed circuit board mounting = 1.15 mm.
VDD
CBTL06GP212
DIN1_n+
DIN1_n−
DIN2_n+
DIN2_n−
4
0
4
DOUT_n+
DOUT_n−
4
1
DAUX1+
DAUX1−
00
DAUX2+
DAUX2−
10
DDC_CLK1
DDC_DAT1
01
DDC_CLK2
DDC_DAT2
11
HPD_1
0
HPD_2
1
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
HPDIN
GPU_SEL
DDC_AUX_SEL
XSD
Fig 1.
Functional diagram
© NXP B.V. 2012.
GND
CBTL06GP212
Product brief
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 May 2012
Document identifier: CBTL06GP212
© NXP B.V. 2012. All rights reserved.
Rev. 1 — 2 May 2012
2 of 2
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