CBTL06DP213 Third generation high-performance DisplayPort multiplexer

CBTL06DP213
Third generation high-performance DisplayPort multiplexer
Rev. 1 — 13 February 2012
Product brief
1. General description
CBTL06DP213 is an NXP third generation high-performance multi-channel multiplexer,
meant for DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating
at data rate of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary
high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1
multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable
of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and
Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated
AUX and DDC I/Os, CBTL06DP213 provides an additional level of multiplexing of AUX
and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP213 is on motherboards where one of two GPU
DisplayPort sources needs to be selected to connect to a DisplayPort sink device or
connector. A controller chip selects which path to use by setting a select signal HIGH or
LOW. Due to the bidirectional nature of the signal paths, CBTL06DP213 can also be used
in the reverse topology, e.g., to connect one display source device to one of two display
sink devices or connectors.
2. Features
 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals
 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
main link signals
 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
 1 channel with 2 : 1 multiplexing/switching for HPD signal
 High-bandwidth analog pass-gate technology
 Ron on DP high-speed channels: 14 Ω
 Low insertion loss:
 −0.9 dB at 100 MHz
 −1.3 dB at 2.7 GHz
 −3 dB at 11.1 GHz
 Low crosstalk: −35 dB at 2.7 GHz
 Low off-state isolation: −30 dB at 2.7 GHz
 Low return loss:
 −20.3 dB at 100 MHz
 −16.7 dB at 1.35 GHz
 −12.9 dB at 2.7 GHz
 Very low intra-pair skew (5 ps typical)
 Very low inter-pair skew (< 80 ps)
CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
 Switch/multiplexer position select CMOS input
 DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
 Supports HDMI/DVI incorrect dongle connection
 Single 3.3 V power supply
 Operation current of 2 mA typical, shutdown current 10 μA maximum
 ESD 2 kV HBM, 500 V CDM
 Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications




Motherboard applications requiring DisplayPort and PCIe switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Solder process
CBTL06DP213EE
6D213
Pb-free (SnAgCu TFBGA48
solder compound)
[1]
Package
Name
Description
Version
plastic thin fine-pitch ball grid array package; SOT918-1
48 balls; body 5 × 5 × 0.8 mm[1]
Total height including solder balls after printed circuit board mounting = 1.15 mm maximum.
VDD
CBTL06DP213
IN1_n+
IN1_n−
IN2_n+
IN2_n−
4
0
4
OUT_n+
OUT_n−
4
1
AUX1+
AUX1−
00
AUX2+
AUX2−
10
DDC_CLK1
DDC_DAT1
01
DDC_CLK2
DDC_DAT2
11
HPD_1
0
HPD_2
1
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
HPDIN
© NXP B.V. 2012.
GPU_SEL
DDC_AUX_SEL
XSD
GND
Fig 1.
002aag784
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 February 2012
Document identifier: CBTL06DP213
Functional diagram
CBTL06DP213
Product brief
© NXP B.V. 2012. All rights reserved.
Rev. 1 — 13 February 2012
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