Ultra-reliable LFPAK56 and LFPAK33

Ultra-reliable
LFPAK56 and LFPAK33
Tougher just got smaller
NXP’s LFPAK – Designed for reliability
MOSFET package evolution
Designing a complex automotive system, a high efficiency industrial power supply or a slimline portable PC ? NXP has a range
of smaller, faster, cooler MOSFETs to help you deliver maximum reliability.
MOSFET packaging technology has changed enormously over the last 40 years in line with ever increasing demands
for smaller, more capable electronic devices.
The first TO220 device was introduced in the 1980s, providing a package that was smaller, less expensive and easier
to assemble than its predecessors. With the rise of surface mount technology towards the end of the decade, a new leadframe
was developed and the D2PAK was born.
The industry then split in two. Some manufacturers preferred the lower cost but more limited options afforded by
high volume IC packages such as the SO8. Others simply shrank the D2PAK in size and developed the DPAK.
Since 1999, NXP has led the way with LFPAK, our ground-breaking solution for high reliability, high performance MOSFETs
in a variety of commercial, industrial and automotive applications.
At the turn of the century NXP introduced the LFPAK56, which has similar dimensions to an SO8 but was specifically designed
to deliver maximum performance in power applications. Such was its success that it became the first Power-SO8 package
to achieve AEC Q101 qualification. Building on this heritage, NXP has now introduced a miniaturized version, the LFPAK33.
The first products were in the Power-SO8 compatible LFPAK56, developed as a ‘true’ power package. Design
and construction were optimized to give the best thermal and electrical performance, cost and reliability.
DFN3333
(LFPAK33)
As industries trend toward miniaturization, LFPAK is still the answer and our LFPAK33 is the ideal solution for the popular
3.3 x 3.3 mm outline footprint.
Power-SO8
(LFPAK56)
Miniaturisation
Thermal Performance
Thermal
 No wires, no glue
 175 °C Tj max
DPAK
(SOT428)
Mechanical
D2PAK
(SOT404)
Electrical performance
 Low package resistance and inductance
 Current handling up to 100 A
TO220
(SOT78)
Cost
 Fewer manufacturing steps means costeffective, high volume production
Mechanical robustness
 Exposed leads absorb thermal and mechanical
stresses
Cost (but limited
power capability)
Surface
mount
TO-3
Electrical
Performance
SO-8
Size, cost,
ease of
assembly
Manufacturability
Manufacturability
 Easy optical inspection of solder joints
 Low package height
 Wave solderable (LFPAK56)
Compatibility
 100% compatible with industry-standard
footprints
Size, ruggedness,
power density
2.35
2.25
0.635 0.617
0.05 (all around)
0.75 0.62
1.05
1.91
2.47
0.51
3.9
0.51
0.6
0.83
0.4 (x8)
0.65 (x6)
0.3 (x8)
0.25 (x6)
Notes : 1. Dimensions in mm
2. Stencil Thickness - 125 μm
Cost
solder land
solder paste
aperture
occupied area
solder resist
Compatibility
1970s
1980s
1990s
2000s
2010s
LFPAK rugged construction
Resilient to mechanical and thermal stress
Innovative clip-bonding
The silicon die is soldered to the drain tab forming the electrical drain connection. Then the top-clip is soldered to the silicon
die to provide source and gate connections, eliminating bond wires and reducing package resistance and inductance.
Customer feedback consistently shows that LFPAK is more reliable and rugged than competitor QFN and other micro-lead
devices. The LFPAK56 meets full automotive qualification (AEC Q101), clear proof of its superior ruggedness and reliability in
the toughest conditions.
The following diagram shows the mechanical stresses that can occur when a device is rapidly heated and cooled. Different
rates of expansion and contraction of the PCB and the MOSFET package can cause cracking of the MOSFET moulding as well
as solder joint failures on a QFN device. LFPAK’s construction allows the gate and source pins to ‘flex’ and safely absorb these
stresses.
Solid Source
Clip
Mold
Silicon DIE
Solder paste
Solder joint inspection of QFN & micro-lead devices often requires costly X-ray analysis and specialist SMT rework equipment.
LFPAK solder joints can be visually inspected and, if necessary, it is possible to rework an LFPAK device using simple, low-cost
tools.
Gate Clip
Copper Drain Tab
The drain tab is soldered directly to the PCB to provide a low electrical resistance path and also low thermal resistance
between the MOSFET and the PCB.
Upper lead-frame bonded directly
to die giving reduced electrical
resistance & inductance in
The LFPAK’s exposed lead-frame provides
compliance and allows for movement caused
by thermal expansion and mechanical strain.
LFPAK
SOURCE connection
Direct connection between
DRAIN-tab-PCB results in
drastically reduced Rthj-mb
MOSFET assembly techniques
Compare the LFPAK with competitor Power-SO8 types which are often constructed using wire bonding as shown right. LFPAK
uses a combined copper clip which is soldered in a single operation to the gate and source. This reduces spreading resistance,
and gives LFPAK superior electrical and thermal characteristics as well as increased reliability.
Cu wire-bonding
LFPAK eliminates wire-bonding used in many competitor devices.
The combined gate and source clip with soldered die-attach delivers:




maximum mechanical ruggedness and reliability
lowest electrical resistance
lowest thermal resistance
simplified manufacturing process
Mechanical stresses occur when a SMT device
is subject to rapid temperature change or if
the PCB bends due to mechanical strain or
vibration.
QFN sawn & micro-lead packages are fully
encapsulated and do not allow for movement
due to thermal expansion or mechanical
strain. Mechanical & thermal stresses can
lead to solder-joint failures
Cracking can also occur in the mould material
around the pins which can lead to moisture
ingress & ionic contamination, causing
degradation and early failure of the MOSFET.
Movement due to thermal and/or mechanical stress in PCB
Movement due to thermal and/or mechanical stress in PCB
Superior thermal and electrical performance
Manufacturing and quality
The LFPAK was developed as a true power package. Package design has been optimized for thermal and electrical
performance, cost and reliability.
High volume electronics manufacturing environments make use of sophisticated optical inspection equipment to monitor the
quality of their output. Solder joints in particular, are subject to stringent rules and manufacturing results are continuously fed
back into the process control system.
The fully encapsulated nature of QFN and DFN type devices mean that only part of the solder joint is visible without the use
of expensive X-ray equipment. In contrast, the exposed leads of LFPAK are available for detailed solder joint inspection and
assessment.
LFPAK56 – Automotive Qualified
NXP Automotive Power MOSFETs are commonly deployed in many critical applications such as braking, power
steering and engine management, where quality and reliability requirements are paramount.
The LFPAK56’s copper source clip design overcomes the limitations of SO8 and Power-SO8 packages and has
been fully qualified to the stringent AEC Q101 standard for discrete devices.
Temperature Rating
Current, ID
NXP LFPAK
Typical Wire Bonded Power Pack
Package RDSON
LFPAK summary
Parameter
LFPAK56 *
LFPAK33 **
Junction temperature
175 °C
175 °C
ID (max)
100 A
70 A
Rth (j-c) typ / (max)
0.40 K/W (0.45)
1.44 K/W (1.65)
Maximum power dissipation
137 W
91 W
SOA (ID at 10 V / 100 µs)
325 A
105 A
RDSon (typ, at VGS = 10 V)
0.75 mΩ
2.45 mΩ
Height
1.0 mm
0.85 mm
External leads for optical inspection and reduced stress
√
√
Industry standard footprint
√
√
* Based on PSMN0R9-25YLC
** Based on PSMN2R9-30MLC
LFPAK56 (SOT669) soldering and footprint compatibility
LFPAK56 universal footprint design
There are many power MOSFETs available in the Power-SO8 family. However as there is no generic JEDEC standard for PowerSO8 devices, each device generally has a different PCB footprint. None of the manufacturers’ devices are guaranteed to be
interchangeable with other devices.
Through careful design of the PCB footprint, it is possible to design a universal footprint, such as the one shown below, that
meets the requirements of various Power-SO8 manufacturers. This universal footprint example shows the solder resist and
solder stencil details that allow a PCB designer to create a footprint compatible the majority of Power-SO8 types.
The following diagram shows that the package styles and recommended PCB footprints differ significantly from each
manufacturer.
Fairchild
Fairchild
Power 56
Power
56
Vishay
Vishay
PowerPak SO8
PowerPak
SO8
Infineon
Infineon
Super SO8
SuperSO8
NEC
NEC
HVSON-8
HVSON-8
ON
Semi
ON Semi
DFN6
DFN6
STM
STM
PowerFlat 6x5
PowerFlat
6x5
4.7
4.2
0.25
(2�)
NXP
NXP
LFPAK
LFPAK
0.9
(3�)
0.25
(2�)
0.6
(4�)
3.45
0.6
(3�)
3.5
2.55
2
0.25
(2�)
NXP’s LFPAK56 (SOT669 & SOT1023) does achieve electrical and mechanical compatibility with these Power-SO8 types.
Each variant may require a different solder-resist, solder-stencil and machine programming unless careful consideration has
been made in advance to design a universal footprint which will allow multiple devices to be fitted to the PCB. The following
diagram shows each manufacturer’s original footprint with their Power-SO8 mounted on it.
SR opening =
Cu + 0.075
1.1
2.15
3.3
SP opening =
Cu − 0.050
Fairchild
Power 56
Vishay
PowerPak SO8
Infineon
Super SO8
NEC
HVSON-8
ON Semi
DFN6
STM
PowerFlat
Renesas
LFPAK
0.7
(4�)
1.27
3.81
The diagram below shows the manufacturers footprint with an LFPAK56 mounted. This shows how it is possible to fit an
LFPAK56 packaged product instead of a competitor device.
LFPAK56 on
Fairchild
Footprint
LFPAK56 on
Vishay Footprint
LFPAK56 on
Infineon
Footprint
LFPAK56 on
Renesas
Footprint
LFPAK56 on
On-Semi
Footprint
LFPAK56 on
FST Footprint
LFPAK56 on
Renesas LFPAK Footprint
solder lands
solder paste
125 µm stencil
solder resist
occupied area
sot669_fr
Universal footprint for reflow soldering
Recommended universal Power-SO8 and LFPAK footprint allows the following device types
to be mounted to a single PCB design:
 NXP LFPAK (SOT669 & SOT1023)
 Infineon PG-TDSON-8
 Fairchild Power 56
 Vishay PowerPAK SO-8
 NEC 8-pin HVSON
 ON Semi SO−8 FL
 STM PowerFLAT (6x5)
 Renesas LFPAK
Comprehensive study reports are available on request for LFPAK56 and LFPAK33 packages showing more detailed proof of
compatibility with competitor footprints.
The original document can be downloaded at:
http://www.nxp.com/documents/reflow_soldering/sot669_fr.pdf
LFPAK56 Wave Soldering
LFPAK33 (SOT1210) soldering and footprint compatibility
Due to its exposed, gull-wing leads, LFPAK56 is the only Power-S08 package that can be wave soldered.
The wave soldering footprint can be downloaded at: http://www.nxp.com/documents/wave_soldering/sot669_fw.pdf
3.3 x 3.3 mm PCB footprints with package mounted
Through careful design of the PCB footprint, it is possible to design a universal footprint, such as the one shown below, that
meets the requirements of various Power-SO8 manufacturers. This universal footprint example shows the solder resist and
solder stencil details that allow a PCB designer to create a footprint compatible the majority of Power-SO8 types.
NXP
LFPAK33
AOS
DFN3.3x3.3
EMC
EDFN 3x3
Fairchild
MLP08S
Fairchild
PQFN08B
Infineon
TSDSON-8
On Semi
Micro8 Leadless
Vishay
PowerPak 1212-8
An independent study has been performed by Norcott Technologies (www.norcott.co.uk) to check compatibility:
 Placement of competitors on NXP universal SOT1210 footprint
 Placement of SOT1210 package on competitor footprints
The conclusion of the study is that LFPAK33 is compatible in both scenarios above. The report is available upon request.
NXP has worked with an independent consultancy to determine a recommended wave soldering process and associated
parameters. This document is available upon request.
LFPAK33 Soldering & Footprint Compatibility
NXP LFPAK33 on competitors’ 3.3x3.3 package footprints
LFPAK33 universal footprint design
The LFPAK33 footprint allows for one PCB design to accommodate:
 NXP - LFPAK33 (SOT1210)
NXP
AOS
EMC
Fairchild
 NXP - DFN3333-8 (SOT873)
 Fairchild - MLP 3.3x3.3
 Vishay - POWERPAK® 1212-8
 Infineon - PG-TSDSON-8 3.3x3.3
 ON SEMI - WDFN8 3.3x3.3
 STM - POWERFlat® 3.3x3.3
 IR - PQFN 3x3
Infineon
On Semi
Vishay
Other manufacturers’ devices may also be compatible, but have not been verified by this trial.
2.35
2.25
0.635 0.617
0.75 0.62
Competitors’ 3.3x3.3 package on NXP LFPAK33 footprint
NXP LFPAK33
AOS
DFN3.3x3.3
EMC
EDFN 3x3
0.05 (all around)
Fairchild
MLP08S
1.05
1.91
2.47
0.51
3.9
0.51
0.6
0.83
0.4 (x8)
Fairchild
PQFN08B
Infineon
TSDSON-8
On Semi
Vishay
Micro8 Leadless PowerPak 1212-8
solder land
solder paste
aperture
occupied area
solder resist
0.3 (x8)
0.65 (x6)
0.25 (x6)
Notes : 1. Dimensions in mm
2. Stencil Thickness - 125 μm
sot1210_fr
How to order standard MOSFETs
Two sizes – One performance
Prefix
LFPAK’s unique construction means that miniaturization does not require a compromise on performance. Thermal simulations
show that LFPAK33 can replace LFPAK56 in a typical application with only a small resultant temperature rise in the silicon.
P
S
N-channel
M
40
m
40
m
L
D
25 = 25 V
B = D2PAK
L=
Logic-level
(16 V Vgs)
C = NextPower
4R0 =
4.0mΩ
-
30 = 30 V
D = DPAK
S=
Standardlevel
(<20 V Vgs)
D = NextPowerS3
014 =
14mΩ
-
40 = 40 V
E = I2PAK
125 =
125mΩ
-
60 = 60 V
K = SO8
-
80 = 80 V
M = LFPAK33
-
100 = 100 V
N = QFN2020
-
110 = 110 V
P = TO220
-
120 = 120 V
X = TO220F
(FULLPACK)
-
150 = 150 V
Y = LFPAK56
-
200 = 200 V
LFPAK56
m
0
35
LFPAK33
E = NextPower
Live
20
• Tj = 43.8°C
Tambient = 25°C
How to order automotive MOSFETs
Efficiency – LFPAK33 versus LFPAK56
Where space is at a premium, LFPAK33 offers similar efficiency to the LFPAK56.
Efficiency
Y
-
mm
m
Technology
family
50
• Tj = 41.1°C
Tambient = 25°C
40
3
Gate
threshold
voltage
R95 =
0.95mΩ
Power Silicon Max
40
-
Package
Type
N = N-ch
Temperature (degC)
0
BVDSS Voltage
4
The PCB’s stack-up and copper pad dimensions remain as the dominant factor for system thermal resistance.
R
-
N
The following images show relative junction temperatures when the MOSFET is mounted on a 10 x 10 mm copper pad, with
power dissipation of 0.5 W in the MOSFET.
mm
RDSon with Vgs = 10 V
Prefix
B
U
K
88%
Gate
threshold
voltage
Package
Type
7
7 = Standard
Level
86%
PSMN9R0-25MLC PSMN3R0-30MLC
82%
9 = Logic
Level
PSMN9R8-30MLC PSMN3R0-30MLC
80%
PSMN9R5-30YLC PSMN3R2-30YLC
0
5
10
15
20
25
30
Load Current in Amp
88%
86%
84%
PSMN3R9-25MLC PSMN3R0-30MLC
82%
PSMN4R4-30MLC PSMN3R0-30MLC
PSMN3R0-30MLC PSMN3R0-30MLC
80%
PSMN4R5-30YLC PSMN3R2-30YLC
78%
-
Y
7
-
M=
LFPAK33
SOT1210
7R6 =
7.6mΩ
-
30 = 30 V
A = Generation 2
12 =
12mΩ
-
40 = 40 V
B = Generation 3
150 =
150mΩ
-
55 = 55 V
C = Generation 4
8 = SOT223
-
60 = 60 V
E = Generation 6
2 = DPAK
SOT428
-
75 = 75 V
6 = D2PAK
SOT404
-
80 = 80 V
E = I2PAK
SOT226
-
100 = 100 V
5 = TO220
SOT78
-
150 = 150 V
6=
Y =LFPAK56
Intermediate
SOT669
Level
84%
78%
MOSFET on-resistance
RDSon
0
5
10
15
20
25
30
K=
LFPAK56D
SOT1205
R
6
Trench
Generation
BVDSS Voltage
4
NXP Automotive MOSFET
0
E
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© 2015 NXP Semiconductors N.V.
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Date of release: May 2015
Document order number: 9397 750 17659
Printed in the Netherlands