The following document contains information on Cypress products. S6J3200 Series 32-bit Microcontroller with Graphics Traveo™ MCU Family Fact Sheet ® TM ® ® The Spansion Traveo MCU family S6J3200 features 32-bit RISC microcontrollers with an ARM Cortex - R5 core and operates at 240MHz. This microcontroller comes with highly-efficient 2D/3D graphic engines with advanced feature-sets for memory savings, safety and high image quality to help manufacturers take advantage of the lower overall system costs while meeting the increasingly high levels of performance and quality that industrial, consumer and automotive applications demand. In addition, this microcontroller offers support for Spansion TM HyperBus memory interface, a breakthrough that dramatically improves read performance while reducing the number of pins. This microcontroller comes with Ethernet AVB, CAN-FD, a high-speed communication protocol compatible with the conventional CAN, and SHE(Secure Hardware Extension) as security function. 1. FEATURES 2. System − 32bit ARM Cortex-R5F CPU core at up to 240MHz − General purpose I/O port：up to 120 − 12-bit A/D converter：up to 50 channels − External interrupt：up to 16 channels − Base timer：up to 24 channels − 32-bit free-run timer：up to 12 channels − Built-in CR oscillator − Real-time clock − Input capture unit：up to 24 channels − Output compare unit：up to 24 channels − DMA controller：16 channels − Stepper motor controller (SMC): 6 Units − JTAG debug interface Graphics and Display − 2D graphic engine − 3D graphic engine (optional) − Timing generator - TCON − TTL/RSDS − FPD-Link – LVDS (optional) − Video capture − Communication: Ethernet AVB MAC − CAN-FD：up to 4 channels − Multi-function serial interface：up to 12 channels, 2 selectable protocol: UART, CSIO, LIN and I C − MediaLB : up to 1 channel Memory − Spansion HyperBus™ Memory interface − Dual quad double data rate SPI Flash Interface Multimedia − I2S input/output: up to 2 Units − PCM to PWM output unit − Sound mixer (optional): 1 unit x 10 inputs − Stereo audio DAC (optional) Security and Safety − Secure Hardware Extension - SHE − Safety features, such as MPU, TPU, ECC and others − CRC generator: 1 channel − Watchdog timer with window function − Low voltage detector − Clock supervisor for all source clocks PRODUCT LINEUP Parameter S6J323CxSA S6J324CxSA S6J325CxSA S6J326CxSA Main Flash (Byte) 2112K 2112K 2112K 2112K RAM (Byte) 256K 256K 256K 256K Video RAM (Byte) 2048K 2048K 2048K 2048K Graphic Engines 2D 2D 2D/3D 2D/3D Sound Mixer Audio DAC - 1 unit - 1 unit FPD-Link - - - 1ch 3. ORDERING INFORMATION Package Part number S6J324CKSASEx0000 Plastic・TEQFP(0.5mm pitch), 208pin S6J326CKSASEx0000 S6J324CLSASEx0000 Plastic・TEQFP(0.4mm pitch), 216pin S6J326CLSASEx0000 4. PACKAGE EXAMPLE OF REFERENCE Plastic TEQFP-208 Publication Number S6J3200_NP708-00002 ® Revision 1.0 ® Issue Date October 3, 2014 Copyright © 2014 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , Traveo and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. F a c t S h e e t To Trace Bus TCM B TCM A TCM-64 TCMSRAM Core Group FP MPU ETM I$ D$ AHB-32 Flash Group AXI-64 Prefetch + ECC + Security AHB-32 Common PERI #0 APB-32 SHE AHB-32 Interrupt signals from Peripherals Int Control Timing Protection (TPU) BootROM Memory and Config AHB-64 AHB-32 AHB-32 Common PERI #1 MPU AXI-64 AXI-64 MPU AHB-64 DMAC AXI-64 Scratch RAM APB-32 64-Bit Multi-Layer AXI (HPM) EAM Mem-Map 1ch DDRHS-SPI AHB-32 AXI-32 Mem-Map 1ch DDRHS-SPI AXI-64 Subsystem AXI-64 Apps#8 Apps#10 Apps#11 Apps#9 AXI-32 RPC2 AXI-64 PRGCRC0 MDIO RPC2 RPC2_ CONV LVDS APB-32 Format CONV Port Mux PPU PPU PPU PPU PPU async PPU Backup RAM_0 (PD4_0) Connection to PERIPHERAL SOUND SYSTEM_MOD AHB-32 I2S0 PCM_PWM Audio DAC MIXER WFG （From Common Peri#0） Apps#4 AHB-32 Apps#3 PPU Ethernet MII I2S1 MediaLB APPLGRP_MASTER MPU MPU AHB-32 Apps#2 Apps#0,#1 AHB-32 TIC Always ON Domain (PD1) Backup RAM_1 (PD4_1) Fastrada delivery Timer & Comm (PD6) nested in PD1 Power Domains PPU RLT 4x BT 0x Port Config PPU APB-Selector Secure Bridge DAP PPU RLT 4x BT 12x FRT 4x ICU 4x OCU 4x QPRC 2x MFS 5x CRC PPU Master GPIO / PPC / PPU master / RIC DMAC complex APB-32 APPLPGRP _SLAVE1 (APPS #7) General purpose communicati on Debug Group - Coresight AHB2AXI SG 4x APPLPGR P_SLAVE0 (APPS #5) M-CAN 2x RLT 4x BT 12x FRT 8x ICU 8x OCU 8x QPRC 0x MFS 5x APB-32 (APPS #4) FPD_LINK CONV ADC12B SMC 6x SMC_trg LCDC Common PERI #2 Low Latency Peripheral Bus Matrix LLPBM AHB-32 AHB-32 AXI-64 Cortex-R5F AXI-64 SCU PPU AHB2APB ・PWM ・LCDE SWJ TCM-64 AHB-32(PD1_Application) Fastrada_MCUCONFIG Group Backup RAM_1 Backup RAM_0 M-CAN 2ch M-CAN RAM MFS 2 ch RLT 2ch EICU Clock / Power / Mode / State / Timer / LVDET / WakeUp / CSV / RTC/ HW-WDT / SWWDT / ext IRQ AXI-32 Fastrada_MICON Group 32Bit Single-Layer APB (Debug) Debug I/F APB-32 3.3V IO 5V IO Peripherals (PD2) S6J3200_NP708-00002-1v0-E, October 3, 2014 2 BLOCK DIAGRAM 5. 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