DESIGN FEATURES A 7ns, 6mA, Single-Supply Comparator Fabricated on Linear’s 6GHz Complementary Bipolar Process by Jim Williams and Brian Hamilton Introduction The LT1394 is an ultrafast (7ns), low power (6mA), single-supply comparator designed to operate on either 5V or ±5V supplies. It has a maximum offset voltage of 2.5mV, complementary TTL compatible outputs and output latch capability. The LT1394 is the first product made with Linear Technology’s 6GHz complementary bipolar technology. This fine-line geometry process results in a product with dramatically improved speed and power compared to industry-standard comparators developed in slower NPNonly technologies. These features combine to make the LT1394 well suited for applicaVCC I1 I2 I3 I4 D15 VCC VEE D2 R4 tions such as high performance NTSC crystal oscillators, single-supply voltage-to-frequency converters and high speed, high accuracy level detectors. The LT1394 is offered in SO-8 and is pin compatible with the industrystandard LT1016 and L T1116 comparators. Circuit Description A simplified schematic of the LT1394 can be seen in Figure 1. There are differential inputs (+IN/–IN), differential outputs (OUT/OUT), a latch input (LATCH) and three power supply pins (VEE, VCC and GND). The circuit topology consists of a differential input R3 D1 R6 I5 R5 Q8 Q2 D17 VEE D11 I7 R9 R11 R12 Q12 Q1 Q6 Q5 VCC R8 Q11 Q7 D16 IN– I6 stage, a level-shifting gain stage, a latch stage and complementary output stages. The complementary output stages offer improved flexibility for the user; the latch stage provides superior sampling accuracy of the input signal without the need for an external latch. The input stage of the LT1394 uses a PNP differential pair (Q1–Q2) with Schottky diodes in the emitters (D1– D2) and resistive loads (R1–R2). The Schottky diodes in series with the emitters allow differential input voltages that are greater than the base-emitter breakdown of the input transistors. Two additional Schottky D9 D4 Q13 D12 Q14 D10 D18 D3 IN+ Q10 Q9 Q4 D19 Q3 VEE Q34 Q30 D8 Q15 Q16 Q35 Q21 Q24 Q25 R7 VCC R10 Q31 Q22 D25 OUT D5 VEE D6 D27 Q19 VCC R2 R1 D7 D26 VCC I8 I9 I10 I11 I12 Q28 Q23 OUT Q32 I13 Q17 Q18 Q20 Q26 Q27 D28 Q29 D20 VEE GND VCC D21 D22 VEE Q33 LATCH D23 VCC Authors can be contacted at (408) 432-1900 VEE D24 VEE 1394_01.eps Figure 1. LT1394 simplified schematic 20 Linear Technology Magazine • May 1998 DESIGN FEATURES diodes (D11–D12) prevent output phase reversal when either input is taken far enough below VEE to forward bias the base-collector junction of its corresponding PNP input transistor. To allow single-supply operation, the input stage has been designed to have small voltage swings across load resistors R1 and R2. This ensures that the input PNPs will not saturate with the LT1394 inputs at VEE. The signal path remains differential as it is buffered and level shifted via transistors Q3–Q4 and diodes D3– D4. The level shift prevents current source I8 from saturating. The second gain stage, comprising transistors Q5– Q6 and resistors R3–R4, takes additional gain while level shifting the signal back to VCC. The differential output of the second gain stage is buffered by transistors Q7–Q8, which then drive the latch stage. In the latch stage, transistors Q9– Q10 and resistors R5–R6 act as a third gain stage. Q11–Q12 buffer the signal at resistors R5–R6, driving another differential pair (Q13–Q14). Q13 and Q14, when activated, provide positive feedback to resistors R5–R6, creating the latch. When the LATCH pin is low, the LT1394 is in flow-through or GAIN mode. Current I11 is steered through Q34, activating the Q9–Q10 differential pair. When the LATCH pin is high, the LT1394 is in LATCH mode. Current I11 is steered through Q35, activating the Q13–Q14 differential pair. The output of the gain/latch stage has additional level shifting from the emitters of transistors Q11–Q12 via diodes D9–D10. This level shifting prevents the output stage current sources I6 and I7 from saturating. The LT1394 provides complementary outputs by using two identical output stages connected in opposite phases. Examining the output circuitry for the OUT pin, a PNP differential pair (Q15–Q16) is driven from the outputs of the latch stage. When I6’s current is steered through Q16, it drives R7 and the base of Q19. R7 improves switching speed by reducing the gain of the differential Linear Technology Magazine • May 1998 pair Q15–Q16 and lowering the impedance at the base of Q19. Q19’s emitter current then drives the base of Q23, turning it on until the OUT pin has been pulled low and Q23’s Schottky clamp diode has turned on. Conversely, if I6’s current is steered through Q15, it allows R8 to pull up the Darlington-connected output transistors Q21 and Q22, bringing the OUT pin high. For faster output switching times, Q15’s collector current flows into the Q17/Q18/Q20 current mirror. Q20’s collector current helps turn off Q23, whereas the collector current of Q18 helps turn off Q19. Linear Technology’s 6GHz Complementary Bipolar Technology Linear Technology’s 6GHz complementary bipolar technology (6GHz ComBi) features vertical NPN and PNP transistors with similar frequency response and gain characteristics. Both the NPN and PNP transistors feature polysilicon emitters for improved gain, a collector-to-emitter breakdown voltage (BVCEO) greater than 12V and a unity gain frequency (fT) of 6GHz. The PNP transistors have a nominal current gain (β) of about 45, while the NPNs have a β of about 100. In addition to the transistors, the 6GHz ComBi technology includes diode, resistor and capacitor structures. Schottky barrier diodes with low parasitic capacitance and high breakdown voltage are included for high speed voltage clamping and breakdown protection of transistors. Low parasitic capacitance polysilicon resistors are included for use in high speed signal paths. High resistivity diffused resistors are used for biasing and low power circuitry. Polysiliconoxide-metal capacitors offer low parasitic capacitance, high capacitance density and low series resistance for good high frequency performance. When compared to a typical 30V complementary bipolar process, the reduction of transistor BVCEO from 30V to 12V has many benefits for applications that do not require higher supply voltages. Dramatically reduced depletion widths within the transistor allow a 50% decrease in area. This area reduction improves speed by lowering parasitic capacitances associated with the transistor. The reduced voltage requirement also allows a thinner, richer epitaxial (epi) region. This change to the epi region dramatically reduces the collector resistance of the transistors, resulting in smaller 5V 47k* 1N4148 CSELECT 0.05µF (SEE TEXT) 1M 1M 5V 2k 390Ω 100pF MV-209 VARACTOR DIODE 1M* LT1004-2.5 3.9k* VIN 0V TO 5V 1k* 1M Y1** 15pF 100pF + LT1394 – FREQUENCY OUTPUT 2k 200pF AN70 F51 * 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz Figure 2. A 4× NTSC subcarrier voltage tunable crystal oscillator; tuning range and bandwidth accommodate a variety of phase-locked loops. 21 DESIGN FEATURES 9 5V 14.3217MHz FREQUENCY DEVIATION (kHz) 8 82Ω 7 5V 6 + 4.7µF Q3 5 4.7k 14.31818MHz Q1 10pF † 4 Q2 3 Q4 2 LT1004-2.5 1 INPUT 0V TO 2.5V 14.3140MHz 0 0 1 3 2 INPUT VOLTAGE (V) 4 15k* 10k 82pF 5 AN70 F52 Figure 3. Control voltage vs output frequency for Figure 2; tuning deviation from the center frequency exceeds ±240ppm. Q + LT1394 Q – FREQUENCY OUTPUT = 2N2369 UNLESS NOTED 8pF 1k = 1N4148 = 1N5712 transistors for a given current level. 10k 1M = 74HC04 Q5 With this significant reduction in tran2N2222 1000pF * 1% FILM RESISTOR sistor size, interconnects using a single † POLYPROPYLENE, 5% metallization layer becomes much more difficult and would generate Figure 4. This simple charge pump–based 10MHz voltage-to-frequency converter has 40dB significant parasitic capacitance. dynamic range and operates from a 5V supply. Because of this, the 6GHz ComBi The resistors at the LT1394’s posi- so that a 0V to 5V drive provides a process utilizes two levels of tive input set a DC bias point of reasonably symmetric, broad tuning metallization. 840mV. The 2kΩ– 200pF path sets up range around the 14.31818MHz cenApplications phase-shifted negative feedback, put- ter frequency. The capacitor labeled ting the DC output in the active region CSELECT sets the tuning bandwidth. It 4× NTSC Voltage-Tunable with a gain of 35 at the oscillation should be picked to complement loop frequency. The crystal’s path pro- response in phase-locking applicaCrystal Oscillator The first of three representative vides resonant positive feedback and tions. Figure 3 is a plot of frequency applications for the LT1394 can be stable oscillation occurs. The varac- deviation versus tuning input voltage. seen in Figure 2. This circuit is a tor diode is biased from the tuning Tuning deviation from the 4× NTSC crystal oscillator with voltage tuning input. The tuning network is arranged 14.31818MHz center frequency exof the output frequency. This applica5V tion makes use of the LT1394’s high + speed, complementary outputs and A2 200pF 1/2 LT1126 single-supply 5V operation. Such volt2k – 10k age controlled crystal oscillators (VCXO) are often employed where slight variation of a stable carrier is 200Ω required. This example is specifically intended to provide a 4× NTSC sub10k – carrier tunable oscillator suitable for A3 1/2 LT1126 phase locking. AN70 F55 + A= 0.1V/DIV –5V 2k B = 2V/DIV 200pF 5V +INPUT C = 1V/DIV –INPUT D = 10mA/DIV 20ns/DIV + + 1µF 1k + A1 LM733 –A = 100 – LT1394 OUTPUT – 1µF 1k –5V AN70 F60 Figure 5. Waveforms for the 10MHz voltage-to-frequency converter; charge pump–based feedback provides linearity and fast response to input. 22 Figure 6. Parallel preamplified paths allow 18ns response to 500µV overdrive. Linear Technology Magazine • May 1998 DESIGN FEATURES A = 1mV/DIV B = 0.1V/DIV (AC-COUPLED) C = 0.1V/DIV A = 1mV/DIV D = 0.1V/DIV B = 1V/DIV E = 5V/DIV 10ns/DIV 5µs/DIV Figure 7. 500µV input (Trace A) is split into wideband and low frequency gain paths (Traces B and C) and recombined (Trace D). Trace E is the level-detector output. Figure 8. Parallel-path level detector shows 18ns response (Trace B) to 500µV overdrive (Trace A). 18ns 500µV Level Detector ceeds ±240ppm for a 0V to 5V tuning capacitor at the input via the Q1– range. 10pF route (Trace D). This current removal resets the LT1394’s positive Simple 10MHz input ramp to a potential slightly Single-Supply V/F Converter below ground, forcing the Q output A second application for the LT1394 low and the paralleled inverters high. is shown in Figure 4. It is a simple The 8pF capacitor at the LT1394’s 10MHz single-supply voltage-to-fre- inverting output furnishes AC posiquency converter that makes use of tive feedback to the negative input the LT1394’s speed, single-supply (Trace C). This ensures that the Q operation and complementary out- output remains high long enough for puts. A 0V to 2.5V input produces a a complete discharge of the 10pF 0Hz to 10MHz output with 40dB of capacitor. The Schottky diode predynamic range, 1% linearity and 400 vents the LT1394’s input from being ppm/°C gain drift. Power supply driven outside its negative common rejection is 0.5% for 4.75V to 5.25V mode limit. When the 8pF capacitor’s feedback decays, the LT1394 again supply excursions. To understand circuit operation, switches and the entire cycle repeats. assume the LT1394’s positive input The oscillation frequency depends is slightly below its negative input. entirely upon the input-derived curThe circuit’s input voltage causes a rent. The LT1004 is the circuit’s positive-going ramp at the com- voltage reference, with Q1 and Q2 parator’s positive input (Trace A, temperature compensating Q3 and Figure 5). The Q output is low, forcing Q4. Start-up or overdrive can cause the CMOS inverter outputs high. This the circuit’s AC-coupled feedback to allows current flow from diode Q1’s latch. If this occurs, the LT1394’s collector, through the CMOS inverter output goes high, causing the paralsupply pin, to the 10pF capacitor. The leled inverters to go low. After a time 4.7µF capacitor provides high fredetermined by the 1MΩ–1000pF RC, quency bypass, maintaining low the associated lone inverter goes high. impedance at Q1’s collector. Diode This lifts the LT1394’s negative input connected Q3 provides a path to and grounds the positive input with ground. The voltage to which the 10pF Q5, initiating normal circuit action. capacitor charges is a function of To calibrate this circuit, apply 2.5V Q1’s collector potential and Q3’s drop. and adjust the 10k potentiometer for When the ramp at the comparator’s a 10MHz output. positive input goes high enough, the Q output goes high and the paralleled inverters switch low (Trace B). This action pulls current from the 82pF Linear Technology Magazine • May 1998 The ultimate limitation on comparator sensitivity is available gain. Unfortunately, increasing gain invariably involves giving up speed. The gain vs speed trade-off in fast comparators is usually a practical compromise designed to satisfy most applications. Some situations, however, require more sensitivity (that is, higher gain) with minimal effect on speed. Figure 6’s circuit adds a differential preamplifier ahead of the LT1394, increasing gain. This permits 500µV comparisons in 18ns. A parallel-path DC stabilization approach eliminates preamplifier drift as an error source. A1 is the differential amplifier, operating at a gain of 100. Its output is AC coupled to the LT1394. A1 has poorly defined DC characteristics, necessitating some form of DC correction. A2 and A3, operating at a differential gain of 100, provide this function. They differentially sense a band-limited version of A1’s inputs and feed DC and low frequency amplified information to the comparator. The low frequency roll-off of A1’s signal path complements A2–A3’s high frequency roll-off. The summation of these two signal channels at the LT1394’s inputs results in flat response from DC to high frequency. Figure 7 shows waveforms for the high sensitivity level detector. Trace A is a 500µV overdrive on a 1mV step applied to the circuit’s positive input (negative input grounded). Trace B shows the resulting amplified step at A1’s positive output. Trace C is A2’s 23 DESIGN FEATURES 1100 Conclusion 1000 Innovative circuit design, coupled with Linear Technology’s 6GHz complementary bipolar process simultaneously achieves the seemingly contradictory goals of high speed and low power. The LT1394 is easy to use, thanks to its single-supply capability and complementary outputs. Additional LT1394 applications appear in the forthcoming Linear Technology Application Note, A Seven Nanosecond Comparator for Single Supply Operation. 900 OVERDRIVE (µV) band-limited output. A1’s wideband output combines with A2’s DC-corrected information to yield the correct, amplified composite signal at the LT1394’s positive input in Trace D. The LT1394’s output is Trace E. Figure 8 details circuit propagation delay. The output responds in 18ns to a 500µV overdrive on a 1mV step. Figure 9 plots response time versus overdrive. As might be expected, propagation delay decreases at higher overdrives. A1’s noise limits usable sensitivity. 800 700 600 500 15 16 17 RESPONSE TIME (ns) 18 AN70 F68 Figure 9. Response time vs overdrive for the composite level detector LTC1401/LTC1404, continued from page 19 0 1.0 –40 –60 –80 –100 –120 0 60 120 180 FREQUENCY (kHz) 240 300 1.0 UNIPOLAR INL ERROR (LSB) BIPOLAR AMPLITUDE (dB) –20 UNIPOLAR DNL ERROR (LSB) fSAMPLE = 600kHz fIN = 298.68kHz SINAD = 71dB THD = –84dB 0.5 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0.5 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1401_06a.EPS Figure 6a. LTC1404 FFT CODE 1401_06b.EPS Figure 6b. LTC1404 DNL error 1401_06c. EPS Figure 6c. LTC1404 INL error Applications The LTC1401 and LTC1404 will find applications in telecommunications, digital signal processing, portablecomputer data acquisition boards and high speed or multiplexed data acquisition. In telecommunication applications such as HDSL (high-bit-rate digital subscriber line interface), high speed and low power dissipation are a must because the systems are usually powered by the phone line itself. Excellent dynamic performance is required of the ADC’s sample-and-hold. The serial interface minimizes the number of signal lines that must be routed, thereby saving significant board 24 space. The 600ksps LTC1404, with its SO-8 footprint, is an excellent choice for HDSL applications. At 584ksps, with 2B1Q coding, the LTC1404 receives at 2.048Mbps over two wires. Another common use of ADCs is in data acquisition applications. System designers have always faced problems in optimizing data acquisition applications for speed, size, power and cost, especially in the case of portable designs. The high sample rate, the high level of functional integration and the low cost of these converters make them ideal choices for these applications. The LTC1401 and LTC1404 can be easily interfaced to a low cost MUX (for example, a CD4051, 74HC4051 or LTC1391) through their high impedance inputs. The high input impedance of these ADCs eliminates the need for a buffer between the MUX and the ADC, resulting in savings of both cost and board space. Conclusion The new LTC1401 and LTC1404 come with full ADC performance and an easy-to-use serial interface. These complete, stand alone, high speed, low power devices will simplify the job of system designers. Linear Technology Magazine • May 1998