46r73d_1av110.pdf

HT46R73D-1A
Dual Slope A/D Type MCU with LCD
Features
· Operating voltage:
· On-chip RC or crystal oscillator
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· HALT function and wake-up feature reduce power
consumption
· 12 bidirectional I/O lines and two ADC input
· Voltage regulator (3.3V) and charge pump
· One external interrupt input shard with an I/O lines
· Embeded voltage reference generator (1.5V)
· One 8-bit and one 16-bit programmable timer/event
· 4-level subroutine nesting
counter with overflow interrupt a 8-stage pre-scalar
· Bit manipulation instruction
· LCD driver with 16´4, 17´3 or 17´2 segments
· 14-bit table read instruction
· 4K´15 program memory with partial lock function
· Up to 0.5ms instruction cycle with 8MHz system clock
· 96´8 data memory RAM
at VDD=5V
· Single differential input channel dual slope Analog to
· 63 powerful instructions
Digital Converter with Operational Amplifier.
· All instructions in 1 or 2 machine cycles
· Watchdog Timer with regulator power
· Low voltage reset/detector function
· Buzzer output
· 52-pin LQFP package
· Internal 12kHz RC oscillator
General Description
converter, LCD display, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versatility of these devices to suit for a wide range of AD with
LCD application possibilities such as sensor signal processing, scales, consumer products, subsystem controllers, etc.
The HT46R73D-1A is an 8-bit high performance, RISC
architecture microcontroller device specifically designed for A/D with LCD applications that interface directly to analog signals, such as those from sensors.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Dual slope A/D
Rev. 1.10
1
March 29, 2016
HT46R73D-1A
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
R O M
S T A C K
P ro g ra m
C o u n te r
In s tr u c tio n
R e g is te r
IN T C
M
M P
U
T M R 0 C
T M R 0
M
T M R 1 C
T M R 1
M
X
M U X
P B C
X
P r e s c a le r
M
W D T
P o rt B
V D D
O S
R E
V D
V S
S
D
S
C 1
A C C
R e g u la to r
L C D D r iv e r
C O M 0 ~ C O M 2
C O M 3 /S E G 1 6
O S C
U
Y S
M
U
fS
X
Y S
/4
In t. R C O S C
/4
In t. R C O S C
X
/B Z
/B Z
/T M R 0
/T M R 1
/IN T
L V D /L V R
D O
D O
D O
D C
D S
D S
D S
1 -C h a n n e l
D u a l- S lo p e
C o n v e rte r
w ith O P
V O C H P
V O R E G
E N /D IS
H A L T
L C D
M e m o ry
C h a rg e
P u m p
P o rt A
P A
B P
O S C 2
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
S h ifte r
P A C
Y S
In t. R C
P B 0 ~ P B 3
S T A T U S
A L U
fS
X
P A 5 /T M R 1
U
P B
T im in g
G e n e r a tio n
U
P A 4 /T M R 0
fS
W D T
P r e s c a le r
In s tr u c tio n
D e c o d e r
U
D a ta
M e m o ry
X
M
P r e s c a le r
S E G 0 ~ S E G 1 5
P A
P A
P A
H O
R R
R C
C C
O
N
P
P
Pin Assignment
P A
P A
P A 4 /T
P A 5 /T
P A 6
O
O
S C
S C
R E
0 /B
1 /B
P A
P A
M R
M R
/IN
P A
V S
V D
D
S
S
Z
Z
T
S
O
N
C
3 9
3 8
3
3 7
2
2
3 6
4
5
3 5
6
H T 4 6 R 7 3 D -1 A
5 2 L Q F P -A
P
7
8
9
P
R
1
1
P
G
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
P
2
D
2
3
0
V D
B G
P C
P C
C H
R E
V S
P A
P A
P A
H O
S R
S R
1
7
A
V O
C H
C H
V O
V O
A
D O
D O
D O
D C
D
D
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
G 0
G 1
G 2
G 3
G 4
G 5
G 6
G 7
G 8
G 9
G 1 0
G 1 1
G 1 2
S E
S E
S E
C O
C O
C O
C O
V L
P B
P B
P B
P B
D S
2
G 1
G 1
G 1
M 3
M 2
M 1
M 0
C D
3
1
0
C C
3
4
5
/S E G 1 6
Rev. 1.10
2
March 29, 2016
HT46R73D-1A
Pin Description
Pin Name
I/O
Options
Description
PA0/BZ
PA1/BZ
PA2
PA3
PA4/TMR0
PA5/TMR1
PA6/INT
PA7
I/O
Wake-up
Pull-high
Buzzer
Bidirectional 8-bit input/output port. Each individual bit on this port can
be configured to have a wake-up function using a configuration option.
Software instructions determine if the pin is a CMOS output or Schmitt
trigger input. Configuration options determine which pins on this port
have pull-high resistors. The BZ, BZ, TMR0, TMR1 and INT are
pin-shared with PA0, PA1, PA4, PA5 and PA6 respectively.
PB0~PB3
I/O
Pull-high
Bidirectional 4-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors.
VLCD
I
¾
COM0~COM2
COM3/SEG16
O
1/2, 1/3 or 1/4
Duty
SEG0~SEG15
O
Segment
Output
VOBGP
AO
¾
Band gap voltage output pin. (for internal use)
VOREG
O
¾
Regulator output 3.3V
VOCHP
O
¾
Charge pump output (a capacitor is required to be connected)
CHPC1
¾
¾
Charge pump capacitor, positive
CHPC2
¾
¾
Charge pump capacitor, negative
DOPAN,
DOPAP,
DOPAO,
DCHOP
AI/AO
¾
Dual Slope converter pre-stage OPA related pins. DOPAN is the OPA
Negative input pin, DOPAP is the OPA Positive input pin, DOPAO is
the OPA output pin and DCHOP is the OPA Chopper pins.
DSRR,
DSRC,
DSCC
AI/AO
¾
Dual slope AD converter main function RC circuit. DSRR is the input or
reference signal, DSRC is the Integrator negative input, and DSCC is
the comparator negative input.
OSC1
OSC2
I
O
Crystal or RC
OSC1, OSC2 are connected to an external RC network or crystal for
the internal system clock. The OSC2 pin can be used to monitor the
system clock at 1/4 frequency.
LCD power supply
COM0~COM3 are the LCD common outputs. An LCD duty-cycle configuration option determines. When 1/3, 1/2 duty is selected, the
COM3/SEG16 is configured as SEG16.
LCD driver outputs for the LCD panel segments.
RES
I
¾
Schmitt trigger reset input, active low
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
AVDD
¾
¾
Analog positive power supply
AVSS
¾
¾
Analog negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
3
March 29, 2016
HT46R73D-1A
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Operating Voltage
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
No load, fSYS=8MHz,
analog block off
¾
4
8
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
0.5
1
mA
¾
1.5
3
mA
¾
3
5
mA
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
¾
8
15
mA
¾
2
5
mA
¾
6
10
mA
IDD2
Operating Current
(Crystal OSC or RC OSC)
3V
Operating Current
(Crystal OSC or RC OSC)
3V
ISTB1
Standby Current
(WDT Disable)
ISTB2
ISTB3
ISTB4
ISTB5
Standby Current
(WDT Enable)
Unit
2.2
5V
Operating Current
(Crystal OSC or RC OSC)
Max.
fSYS=4MHz
Operating Current (Crystal)
IDD4
Typ.
¾
IDD1
IDD3
Min.
Conditions
VDD
5V
5V
5V
3V
5V
3V
No load, fSYS=4MHz,
ADC block off
No load, fSYS=2MHz,
ADC block off
VREGO=3.3V, fSYS=4MHz,
ADC on, ADCCCLK=
125kHz (all other analog devices off)
No load, system HALT,
LCD off at HALT
5V
No load, system HALT,
LCD off at HALT, ADC off
Standby Current (WDT Disable In- 3V
ternal RC 12kHz OSC ON)
5V
No load, system HALT,
LCD off at HALT, ADC off
3V
Standby Current (WDT Disable Internal RC 12kHz OSC ON)
5V
No load, system HALT,
LCD on at HALT, 1/2 bias,
VLCD=VDD
¾
40
60
mA
¾
70
105
mA
3V
Standby Current (WDT Disable Internal RC 12kHz OSC ON)
5V
No load, system HALT
LCD on at HALT, 1/3 bias,
VLCD=VDD
¾
30
45
mA
¾
50
75
mA
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1 and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1 and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLCD
LCD Highest Voltage
¾
¾
0
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2
2.1
2.2
V
VLVD
Low Voltage Detector
¾
¾
2.2
2.3
2.4
V
IOL1
I/O Port Segment Logic Output
Sink Current
3V
4
8
¾
mA
10
20
¾
mA
I/O Port Segment Logic Output
Source Current
3V
-2
-4
¾
mA
-5
-10
¾
mA
210
420
¾
mA
350
700
¾
mA
IOH1
IOL2
Rev. 1.10
LCD Common and Segment
Current
VOL=0.1VDD
5V
VOH=0.9VDD
5V
3V
VOL=0.1VDD
5V
4
March 29, 2016
HT46R73D-1A
Test Conditions
Symbol
Parameter
IOH2
RPH
LCD Common and Segment
Current
3V
Min.
Typ.
Max.
Unit
-80
-160
¾
mA
-180
-360
¾
mA
Conditions
VDD
VOH=0.9VDD
5V
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Charge pump on
2.2
¾
3.6
V
Charge pump off
3.7
¾
5.5
V
Pull-high Resistance of I/O Ports
Charge Pump and Regulator
VCHPI
VREGO
Input Voltage
Output Voltage
VREGDP1
¾
¾
No load
3
3.3
3.6
V
¾
VDD=3.7V~5.5V
Charge pump off
Current£10mA
¾
100
¾
mV
¾
VDD=2.4V~3.6V
Charge pump on
Current£6mA
¾
100
¾
mV
Regulator Output Voltage Drop
(Compare with No Load)
VREGDP2
Dual Slope AD, Amplifier and Band Gap
VRFGO
Reference Generator Output
¾
@3.3V
1.45
1.5
1.55
V
VRFGTC
Reference Generator
Temperature Coefficient
¾
@3.3V
¾
50
¾
Ppm/C
VADOFF
Input Offset Range
¾
¾
500
800
mV
VICMR
Common Mode Input Range
¾
¾
Amplifier, no load
0.2
¾
VREGO-1
V
¾
Integrator, no load
1
¾
VREGO-0.2
V
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
System Clock (RC OSC)
fSYS
System Clock (Crystal OSC)
fINRC
Unit
400
¾
4000
kHz
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
12
¾
kHz
¾
15
¾
kHz
0
¾
4000
kHz
3V
tWDTOSC Watchdog Oscillator Period
Max.
2.2V~5.5V
¾
Internal RC OSC
Timer I/P Frequency
(TMR0/TMR1)
Typ.
¾
5V
fTIMER
Min.
Conditions
VDD
¾
2.2V~5.5V
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up from
HALT
¾
1024
¾
tSYS
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: tSYS= 1/fSYS
Rev. 1.10
5
March 29, 2016
HT46R73D-1A
Functional Description
Execution Flow
The PC then points to the memory word containing the
next instruction code.
The system clock is derived from either a crystal or an
external RC oscillator. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two
cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
The program counter (PC) is 12 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 4096 addresses.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
ADC Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Loading PCL
*11
0
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
0
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S11
0
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.10
S11~S0: Stack register bits
@[email protected]: PCL bits
6
March 29, 2016
HT46R73D-1A
· Location 010H
Program Memory - EPROM
Location 010H is reserved for the ADC interrupt service program. If an ADC interrupt occurs, and if the interrupt is enabled and the stack is not full, the program
begins execution at this location.
The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 4096´15 bits which are addressed by the program
counter and table pointer.
· Table location
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH. The TBLH is read only, and the table pointer
(TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location
should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation.
These areas may function as a normal ROM depending upon the user¢s requirements.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 4 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
· Location 00CH
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
0 0 C H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 0 H
A D C In te r r u p t S u b r o u tin e
1 0 0 H
1 F F H
P ro g ra m
M e m o ry
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 4 return addresses are stored).
L o o k - u p T a b le ( 2 5 6 W o r d s )
n F F H
F 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
1 to E
Program Memory
Instruction(s)
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@[email protected]: Table pointer bits
Rev. 1.10
P11~P8: Current program counter bits
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March 29, 2016
HT46R73D-1A
Data Memory - RAM
Bank 1 contains the LCD Data Memory locations. After
first setting up BP to the value of ²01H² to access Bank 1
this bank must then be accessed indirectly using the
Memory Pointer MP1. With BP set to a value of ²01H²,
using MP1 to indirectly read or write to the data memory
areas with addresses from 40H~50H will result in operations to Bank 1. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective
of the value of BP.
Bank 0 of the data memory has a capacity of 123´8 bits,
and is divided into two functional groups, namely the
special function registers of 27´8 bit capacity and the
general purpose data memory of 96´8 bit capacity. Most
locations are readable/writable, although some are read
only. The special function register are overlapped in all
banks.
Any unused space before 20H is reserved for future expanded usage, reading these locations will get ²00H².
The general purpose data memory, addressed from 20H
to 7FH , is used for data and control information under
instruction commands. All of the data memory areas can
handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits,
each bit in the data memory can be set and reset by the
²SET [m].i² and ²CLR [m].i² instructions. They are also
indirectly accessible through the memory pointer registers, MP0 and MP1.
0 0 H
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
memory pointer register (MP0, MP1) are 7-bit registers.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
M O D E
0 A H
S T A T U S
0 B H
IN T C 0
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
Arithmetic and Logic Unit - ALU
S p e c ia l P u r p o s e
D a ta M e m o ry
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
1 6 H
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
1 7 H
1 8 H
A D C R
1 9 H
R e s e rv e d
1 A H
A D C D
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
1 B H
1 C H
W D T C
1 D H
W D T D
1 E H
IN T C 1
1 F H
C H P R C
2 0 H
7 F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
: U n u s e d
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
R e a d a s "0 0 "
RAM Mapping
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March 29, 2016
HT46R73D-1A
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Interrupts
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status
of the latest operations.
The device provides one external interrupts, two internal
timer/event counter interrupts and the ADC interrupt.
The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/
disable status and interrupt request flags.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Once an interrupt subroutine is serviced, other interrupts are all blocked, by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI
Controls the external interrupt (1=enabled; 0=disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC 0 (0BH) Register
Bit No.
Label
0
EADI
1~3, 5~7
¾
4
ADF
Function
Controls the ADC interrupt (1=enabled; 0:disabled)
Unused bit, read as ²0²
ADC request flag (1=active; 0=inactive)
INTC 1 (1EH) Register
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HT46R73D-1A
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becoming full.
Interrupt Source
All interrupts will provide a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing
the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents of the
program counter is pushed onto the stack. If the contents of the register or of the status register is altered by
the interrupt service program which corrupts the desired
control sequence, the contents should be saved in advance.
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
ADC interrupt
4
10H
Once the interrupt request flags (ADF, T0F, T1F, EIF)
are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a
software instruction.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
An external interrupt is triggered by an edge transition
on INT (A configuration option selects: high to low, low to
high, both low to high and high to low), and the related
interrupt request flag (EIF; bit 4 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to location 04H occurs. The interrupt request flag (EIF) and
EMI bits are all cleared to disable other maskable interrupts.
Oscillator Configuration
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
The device provides three oscillator circuits, an external
RC oscillator, a crystal oscillator and an internal RC
12kHz oscillator (Int. RCOSC). The external RC oscillator and a crystal oscillator signal are used for the system
clock and the internal 12kHz RC oscillator is designed
for timing purposes.
In the IDLE mode, the IRC clock source is enabled
(IRCC=0), the system oscillator stop running, but the internal RC oscillator (Int.RCOSC) still continuously keep
free running. In HALT mode, if the WDT is disabled, the
IRC clock source is disabled (IRCC=1), both the system
oscillator and internal RC oscillator stop running, but if
the WDT is enabled, the internal RC oscillator will always keep free running. The system can be woken-up
from either the IDLE or HALT mode by the occurrence of
an interrupt, a high to low transition on any of the Port A
pins, a WDT overflow or a timer overflow and request
flag is set (0®1).
The A/D Converter interrupt is initialized by setting the
A/D Converter clock interrupt request flag (ADF; bit 4 of
INTC1), that is caused by an A/D conversion done signal. After the interrupt is enabled, and the stack is not
full, and the ADF bit is set, a subroutine call to location
10H occurs. The related interrupt request flag (ADF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
V
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
C 1
O S C 1
R
D D
O S C
O S C 1
4 7 0 p F
C 2
R 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S o p e n d r a in
O S C 2
R C
O s c illa to r
System Oscillator
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HT46R73D-1A
clock/4. The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The watchdog timer can
be disabled by a configuration option. If the watchdog
timer is disabled, the WDT timer will have the same
manner as in the enable-mode except that the timeout
signal will not generate a chip reset. So in the watchdog
timer disable mode, the WDT timer counter can be read
out and can be cleared. This function is used for the application program to access the WDT frequency to get
the temperature coefficient for analog component adjustment. The WDT oscillator needs to be disabled/enabled by the special function registers(WDTC
:WDTOSC), for power saving reasons.
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors in
OSC1 and OSC2 are required (if the oscillator can be
disabled by options to conserve power).
If an external RC oscillator is used, an external resistor
between OSC1 and VSS is required to achieve oscillation, the value of which must be between 100kW to
2.4MW. The system clock divided by 4, which can be
monitored on pin OSC2, can be used for external logic
synchronization purposes.
There are 2 registers related to the WDT function,
WDTC and WDTD. The WDTC register can control the
WDT oscillator enable/disable and the WDT power
source. WDTD is the WDT counter readout register.
The Internal RC oscillator (Int.RCOSC) is a free running
on-chip RC oscillator, requiring no external components. Even if the system enters the Power Down Mode,
and the system clock is stopped, the internal RC oscillator continues to run with a period of approximately 65ms
at 5V if either the WDT or IRC clock is enabled. The internal RC oscillator can be disabled by a configuration
option and by setting the IRCC bit to ²1² to conserve
power.
WDTPWR can be used to choose the WDT power
source, the default source is VOCHP. The main purpose
of the regulator is to be used for the WDT Temperature-coefficient adjustment. In this case, the application
program should enable the regulator before switching to
the Regulator source. The WDTOSC can be used to enable or disable the WDT OSC (12kHz). If the application
does not use the WDT OSC, then it needs to disable it in
order to save power. When WDTOSC is disabled, then it
is actually turned off, regardless of the IRCC setting.
When the WDTOSC is enabled, the Power Down mode
situation will be defined by the IRCC registers.
Watchdog Timer - WDT
The WDT is implemented using a dedicated internal RC
oscillator (Int. RCOSC, note: the WDTOSC described in
this document represents the same oscillator as the
Int.RCOSC) or the instruction clock which is the system
Bit No.
Label
Function
0~1
The WDT Power source selection. (WDTPWR1:0)=
01: WDT power comes from VOCHP
WDTPWR0~
10: WDT power comes from regulator
WDTPWR1
00/11: WDT power comes from VOCHP strongly recommend use to use 01 for VOCHP
prevent the noise to let the WDT lose the power
2~3
WDTOSC0~
WDTOSC1
4~7
¾
The WDT oscillator enable/disable (WDTOSC1:0)=
01: WDT OSC disable10: WDT OSC enable
00/11: WDT OSC enable strongly recommend use to use 10 for WDT OSC enable
Reserved
WDTC (1CH) Register
Note: WDTOSC registers initial value will be set to enable (1,0), if both ²WDT option enable² and ²WDT clock option
set to WDT², otherwise, it will be set to disable (0,1)
Bit No.
Label
0~7
WDTD0~
WDTD7
Function
The WDT counter data value.
This register is read only. It¢s used for temperature adjusting.
WDTD (1DH) Register
The WDT clock (fS1) is further divided by an internal counter to give longer watchdog time-outs., In this device, the division ratio can be varied by selecting different configuration options to give 213 to 216 division ration range.
Rev. 1.10
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HT46R73D-1A
V O C H P
V O R E G
W D T O S C
E n a b le
W D T
P W R
W D T
O S C
C o n tro l
L o g ic
C L R W D T 1 F la g
C L R W D T 2 F la g
1 /2 In s tr u c tio n s
W D T O S C
fS
Y S
/4
W D T S o u rc e
C o n fig u r a tio n
O p tio n
fS
C L R
1
1 6 - B it C o u n te r
b 0
b 1 5
b 4 ~ b 1 1
W D T D iv is io n
C o n fig u r a tio n O p tio n
fS 1 /2
1 3
~ fS 1 /2
W D T
E N /D IS
W D T T im e - o u t
1 6
D a ta B u s
Watchdog Timer
If the ²CLR WDT² is selected (i.e., CLR WDT times
equal one), any execution of the ²CLR WDT² instruction
clears the WDT. If the ²CLR WDT1² and ²CLR WDT2²
option is chosen (i.e., CLR WDT times equal two), these
two instructions have to be executed to clear the WDT,
otherwise the WDT may reset the chip due to a time-out.
Once an internal RC oscillator (Int.RC oscillator with period 65ms normally) is selected, it is divided by Max 216
to get the time-out period of approximately 4.3s. This
time-out period may vary with temperature, VDD and
process variations.
The WDT clock source may also come from the instruction clock, in which case the WDT will operate in the
same manner except that in the Power Down mode the
WDT may stop counting and lose its protecting purpose.
In this situation the device can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (Int.RC OSC) is
strongly recommended, since the HALT instruction will
stop the system clock.
Buzzer Output
The Buzzer function provides a means of producing a
variable frequency output, suitable for applications such
as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ
pins form a complimentary pair, and are pin-shared with
I/O pins, PA0 and PA1. A configuration option is used to
select from one of three buzzer options. The first option
is for both pins PA0 and PA1 to be used as normal I/Os,
the second option is for both pins to be configured as BZ
and BZ buzzer pins, the third option selects only the PA0
pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is
the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT or
IDLE mode, the overflow initializes a ²warm reset², and
only the PC and SP are reset to zero. There are three
methods to clear the contents of the WDT, an external
reset (a low level on RES), a software instruction or a
²HALT² instruction. There are two types of software instructions; the single ²CLR WDT² instruction, or the pair
of instructions ¾ ²CLR WDT1² and ²CLR WDT2².
The buzzer is driven by the internal clock source, fS,
which then passes through a divider, the division ratio of
which is selected by configuration options to provide a
range of buzzer frequencies from fS/22 to fS/29.
Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option ¾ ²CLR WDT² times selection option.
PAC Register
PAC.0
PAC Register
PAC.1
PA data Register
PA.0
PA data Register
PA.1
0
0
0
X
PA0=0, PA1=0
0
0
1
X
PA0=BZ, PA1=BZ
0
1
0
X
PA0=0, PA1=Input
0
1
1
X
PA0=BZ, PA1=Input
1
0
0
X
PA0=Input, PA1=0
1
1
X
X
PA0=Input, PA1=Input
Output Function
PA0/PA1 Pin Function Control
Note: ²X² stands for don¢t care
Rev. 1.10
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HT46R73D-1A
In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control
pin to be used as both a buzzer pin and as an input pin,
so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by
the application program by programming the appropriate port control register bit.
The clock source that generates fS, which in turn controls the buzzer frequency, can originate from two different sources, the Int.RCOSC (Internal RC oscillator) or
the System oscillator/4, the choice of which is determined by the fS clock source configuration option. Note
that the buzzer frequency is controlled by configuration
options, which select both the source clock for the internal clock fS and the internal division ratio. There are no
internal registers associated with the buzzer frequency.
Note:The above drawing shows the situation where
both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup
as outputs. The data setup on pin PA1 has no effect on
the buzzer outputs.
If the configuration options have selected both pins PA0
and PA1 to function as a BZ and BZ complementary pair
of buzzer outputs, then for correct buzzer operation it is
essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register
to zero. The PA0 data bit in the PA data register must
also be set high to enable the buzzer outputs, if set low,
both pins PA0 and PA1 will remain low. In this way the
single bit PA0 of the PA register can be used as an on/off
control for both the BZ and BZ buzzer pin outputs. Note
that the PA1 data bit in the PA register has no control
over the BZ buzzer pin PA1.
Power Down Operation - HALT
The HALT and IDLE mode is initialized by the ²HALT²
instruction and results in the following.
· The system oscillator turns off but the Internal oscilla-
tor (Int.RCOSC) keeps running (if the Internal oscillator is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and starts recounting (if the WDT
If configuration options have selected that only the PA0
pin is to function as a BZ buzzer pin, then the PA1 pin
can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output
by setting bit PAC0 of the PAC port control register to
zero. The PA0 data bit in the PA data register must also
be set high to enable the buzzer output, if set low pin
PA0 will remain low. In this way the PA0 bit can be used
as an on/off control for the BZ buzzer pin PA0. If the
PAC0 bit of the PAC port control register is set high, then
pin PA0 can still be used as an input even though the
configuration option has configured it as a BZ buzzer
output.
clock source is from the Internal RC oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
· The LCD driver keeps running if the IRC clock is en-
abled; IRCC=0 and LCD on HALT mode set to ON.
The system leaves the HALT or IDLE mode by means of
an external reset, an interrupt, an external falling edge
signal on port A, or a WDT overflow. An external reset
causes device initialisation, and the WDT overflow performs a ²warm reset². After examining the TO and PDF
flags, the reason for chip reset can be determined. The
PDF flag is cleared by system power-up or by executing
the ²CLR WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO flag is set if
WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, and leaves the others
in their original state.
Note that no matter what configuration option is chosen
for the buzzer, if the port control register has setup the
pin to function as an input, then this will override the configuration option selection and force the pin to always
behave as an input pin. This arrangement enables the
Rev. 1.10
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March 29, 2016
HT46R73D-1A
An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the
SST delay.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin
of port A can be independently selected to wake-up the
device using configuration options. After awakening
from an I/O port stimulus, the program will resume execution at the next instruction. However, if awakening
from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the
next instruction. But if the interrupt is enabled, and the
stack is not full, the regular interrupt response takes
place.
The functional unit chip reset status is shown below.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awakened using
that interrupt.
If a wake-up events occur, it takes 1024 tSYS (system
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT
Cleared. After master reset,
WDT starts counting
Timer/Event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
V D D
R E S
tS
C h ip
R e s e t
Reset Timing Chart
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
V
V
D D
1 0 0 k W
1 0 0 k W
There are three ways in which a reset may occur.
R E S
· RES is reset during normal operation
B a s ic
R e s e t
C ir c u it
· WDT time-out is reset during normal operation
The WDT time-out during HALT or IDLE differs from
other chip reset conditions, for it can perform a ²warm
reset² that resets only the program counter and SP and
leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to their initial conditions
once the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different chip resets.
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
1 0 k W
0 .1 m F
H i-n o is e
R e s e t
C ir c u it
Reset Circuit
Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A L T
W a rm
R e s e t
W D T
RESET Conditions
E x te rn a l
R E S
O S C 1
Note: ²u² stands for unchanged
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power-up.
Awaking from the HALT state or system power-up, the
SST delay is added.
Rev. 1.10
R E S
0 .1 m F
· RES is reset during HALT
PDF
D D
0 .0 1 m F
Reset
TO
S T
S S T T im e - o u t
C o ld
R e s e t
R e s e t
Reset Configuration
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March 29, 2016
HT46R73D-1A
The register states are summarized below:
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
MODE
--0- 01--
--0- 01--
--0- 01--
--0- 01--
--u- uu--
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
BP
ACC
Program
Counter
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
ADCR
0000 x000
0000 x000
0000 x000
0000 x000
uuuu xuuu
ADCD
---- -111
---- -111
---- -111
---- -111
---- -uuu
WDTC
---- ss01
---- ss01
---- ss01
---- ss01
---- uuuu
WDTD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CHPRC
Note: ²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
²s² for special case, it depends on the option table (please see the WDT chapter for the detail)
Rev. 1.10
15
March 29, 2016
HT46R73D-1A
tents of the lower-order byte buffer. TMR1C is the
Timer/Event Counter 1 control register, which defines
the operating mode, counting enable or disable and an
active edge.
Timer/Event Counter
Two timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 contains an 8-bit
programmable count-up counter whose clock may
come from an external source or an internal clock
source. An internal clock source comes from fSYS or the
Internal RC. Timer/Event Counter 1 contains a 16-bit
programmable count-up counter whose clock may
come from an external source or an internal clock
source. An internal clock source comes from fSYS/4 or
Internal RC selected by a special function register option. The external clock input allows the user to count
external events, measure time intervals or pulse widths,
or to generate an accurate time base.
The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)
bits define the operation mode. The event count mode is
used to count external events, which means that the
clock source must come from an external (TMR0,
TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count a high or low level duration
of an external signal on TMR0 or TMR1, with the timing
based on the internal selected clock source.
There are two registers related to the Timer/Event
Counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing
to TMR0 puts the starting value in the Timer/Event
Counter 0 register and reading TMR0 reads out the contents of Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which defines some
options. There are three registers related to the
Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H)
and TMR1C (11H). Writing to TMR1L will only put the
written data into an internal lower-order byte buffer
(8-bit) while writing to TMR1H will transfer the specified
data and the contents of the lower-order byte buffer to
both the TMR1H and TMR1L registers, respectively.
In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the
Timer/Event Counter 0 (1) and ends at FFH (FFFFH).
Once an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and generates
an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit6
of INTC0). In the pulse width measurement mode with
the values of the T0ON/T1ON and T0E/T1E bits equal
to 1, after the TMR0 (TMR1) has received a transient
from low to high (or high to low if the TE bit is ²0²), it will
start counting until the TMR0 (TMR1) pin returns to the
original level and resets the T0ON/T1ON bit. The measured result remains in the timer/event counter even if
the activated transient occurs again. Therefore, only a
1-cycle measurement can be made until the
T0ON/T1ON bit is again set. The cycle measurement
will re-function as long as it receives further transient
pulses. In this operation mode, the timer/event counter
The Timer/Event Counter 1 preload register is changed
every time there is a write operation to TMR1H. Reading
TMR1H will latch the contents of TMR1H and TMR1L
counters to the destination and the lower-order byte
buffer, respectively. Reading TMR1L will read the confS
In t. R C
Y S
O S C
M
fT
U
0
8 - s ta g e P r e s c a le r
X
T 0 S
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
f IN
D a ta B u s
T 0
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r
(T M R 0 )
O v e r flo w
to In te rru p t
Timer/Event Counter 0
fS
In t. R C
Y S
/4
O S C
T 1 S
M
U
X
fT
D a ta B u s
1
8 - s ta g e P r e s c a le r
8 -1 M U X
T 1 P S C 2 ~ T 1 P S C 0
f IN
L o w B y te
B u ffe r
T 1
T 1 M 1
T 1 M 0
T M R 1
1 6 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
B y te
1 6 - B it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.10
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HT46R73D-1A
Bit No.
Label
Function
T0PSC0
T0PSC1
T0PSC2
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT0=fT0
001: fINT0=fT0/2
010: fINT0=fT0/4
011: fINT0=fT0/8
100: fINT0=fT0/16
101: fINT0=fT0/32
110: fINT0=fT0/64
111: fINT0=fT0/128
3
T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T0ON
5
T0S
0
1
2
6
7
T0M0
T0M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR0 internal clock source (0=fSYS; 1=Int.RCOSC (Internal RC OSC))
Defines the operating mode T0M1, T0M0=
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR0C (0EH) Register
Bit No.
Label
Function
T1PSC0
T1PSC1
T1PSC2
To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0=
000: fINT1=fT1
001: fINT1=fT1/2
010: fINT1=fT1/4
011: fINT1=fT1/8
100: fINT1=fT1/16
101: fINT1=fT1/32
110: fINT1=fT1/64
111: fINT1=fT1/128
3
T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T1ON
5
T1S
0
1
2
6
7
T1M0
T1M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR1 internal clock source (0=fSYS/4; 1=Int.RCOSC (Internal RC OSC))
Defines the operating mode T1M1, T1M0=
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR1C (11H) Register
Rev. 1.10
17
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HT46R73D-1A
put, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
begins counting not according to the logic level but to
the transient edges. In the case of counter overflows,
the counter is reloaded from the timer/event counter
register and issues an interrupt request, as in the other
two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(T0ON; bit 4 of TMR0C or T1ON bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON (T1ON) is automatically cleared after the measurement cycle is completed. But in the other two
modes, the T0ON (T1ON) can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
and 15H.
After a chip reset, these input/output lines remain at high
levels or in a floating state, depending upon the pull-high
configuration options. Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² (m=12H or 14H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register also
reloads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Each line of port A has the capability of waking-up the
device.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, however as
this may result in a counting error, it should be taken into
account by the programmer. It is strongly recommended
to load a desired value into the TMR0/TMR1 register
first, before turning on the related timer/event counter,
for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/ event counter scheme, the programmer should pay special attention to the instructions which enables then disables the
timer for the first time, whenever there is a need to use
the timer/event counter function, to avoid unpredictable
results. After this procedure, the timer/event function
can be operated normally.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor
connected. Take note that a non-pull-high I/O port setup
as an input mode will be in a floating condition.
Pins PA0, PA1, PA4, PA5 and PA6 are pin-shared with
BZ, BZ, TMR0, TMR1 and INT pins respectively.
PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ configuration option is selected,
the output signals in the output mode of PA0/PA1 can be
the buzzer signal. The input mode always retains its
original function. Once the BZ/BZ configuration option is
selected, the buzzer output signals are controlled by the
PA0 data register.
The bit0~bit2 of the TMR0C/TMR1C can be used to define the pre-scaling stages of the internal clock sources
of Timer/Event Counter 0/1.
The PA0/PA1 I/O function is shown below.
PA0 I/O
I
I
O O O O O O O O
Input/Output Ports
PA1 I/O
I
O
I
There are 12 bidirectional input/output lines in the
microcontroller, labeled as PA and PB, which are
mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H or 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
PA0 Mode
X X C B B C B B B B
PA1 Mode
X C X X X C C C B B
PA0 Data
X X D 0
PA1 Data
X D X X X D1 D D X X
PA0 Pad Status
I
I
D 0
B D0 0
0
B
PA1 Pad Status
I
D
I
I D1 D D 0
B
I
I
O O O O O
1 D0 0
1
B
0
1
Note: ²I² input; ²O² output
²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care
²C² CMOS output
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS outputs or Schmitt trigger inputs with or
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an in-
Rev. 1.10
I
18
March 29, 2016
HT46R73D-1A
V
D a ta B u s
C o n tr o l B it
Q
D
W r ite C o n tr o l R e g is te r
P U
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P A 0 /P A 1
B Z /B Z
M
R e a d D a ta R e g is te r
S y s te m
D D
U
U
/B Z
/B Z
/T M R 0
/T M R 1
/IN T
~ P B 3
X
E N
X
W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
T M R 0 fo r P A 4 o n ly
T M R 1 fo r P A 5 o n ly
IN T fo r P A 6 o n ly
Input/Output Ports
Additionally, the device also includes a band gap voltage generator for the 1.5V low temperature sensitive
reference voltage. This reference voltage is used as the
zero adjustment and for a single end type reference voltage.
It is recommended that unused or not bonded out I/O
lines should be set as output pins using software instructions to avoid consuming power when in an input
floating state.
Charge Pump and Voltage Regulator
There is one charge pump and one voltage regulator implement in this device.
R e g u la to r
R E F
B a n d G a p
E n h a n c e
The charge pump can be enabled/disabled by the application program. The charge pump uses VDD as its input, and has the function of doubling the VDD voltage.
The output voltage of the charge pump will be VDD´2.
The regulator can generate a stable voltage of 3.3V, for
internal WDT, ADC and also can provide an external
bridge sensor excitation voltage or supply a reference
voltage for other applications. The user needs to guarantee the charge pump output voltage is greater than
3.6V to ensure that the regulator generates the required
3.3V voltage output. The block diagram of this module is
shown below.
C H P C 2
V D D
C H P C 1
C h a rg e P u m p
( V o lta g e D o u b le r )
fS
D iv id e r
C H P C K D
Rev. 1.10
C H P E N
V D D
V D D x 2
R e g u la to r
(3 .3 V )
3 .3 V
I
V O B G P
F IL
B G
(S F
0 : O
1 : O
P Q S T
R b its )
ff (s h o rt)
n
C
F IL
RFIL is about 100kW and the recommend CFIL is 10mF.
Note: VOBGP signal is only for chip internal used.
Don¢t connect to external component except the
recommend CFIL
There is a single register associated with this module
named CHPRC. The CHPRC is the Charge Pump/Regulator Control register, which controls the charge pump
on/off, regulator on/off functions as well as setting the
clock divider value to generate the clock for the charge
pump.
V O R E G
V O C H P
R
The CHPCKD4~CHPCKD0 bits are use to set the clock
divider to generate the desired clock frequency for
proper charge pump operation. The actual frequency is
determined by the following formula.
W D T
A D C
Actual Charge Pump Clock= (fSYS/16)/(CHPCKD +1).
R E G C E N
19
March 29, 2016
HT46R73D-1A
Bit No.
Label
0
REGCEN
1
CHPEN
2
3~7
Function
Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable)
Charge Pump Enable/disable setting. (1=enable; 0=disable)
Note: this bit will be ignore if the REGCEN is disable
BGPQST
Band gap quickly start-up function
0: R short, quickly start
1: R connected, normal RC filter mode
Every time when REGCEN change from 0 to 1 (Regulator turn on) This bit should be set
to 0 and then set to 1 to make sure the quickly stable. (the minimum 0 keeping time is
about 2ms now )
The Charge pump clock divider. This 5 bits can form the clock divide by 1~32.
CHPCKD0~
Following the below equation:
CHPCKD4
Charge Pump clock = (fSYS/16) / (CHPCKD+1)
CHPRC (1FH) Register
REGCEN CHPEN
Charge
Pump
VOCHP
Regulator
Pin
VOREG Pin OPA ADC
Description
The whole module is disable,
OPA/ADC will lose the Power
0
X
OFF
VDD
OFF
Hi-Impedance
Disable
1
0
OFF
VDD
ON
3.3V
Active
Use for VDD is greater than 3.6V
(VDD>3.6V)
1
1
ON
2´VDD
ON
3.3V
Active
Use for VDD is less than 3.6V
(VDD=2.2V~3.6V)
It is necessary to take care of the VDD voltage. If the voltage is less than 3.6V, then CHPEN should be set to 1 to
enable the charge pump, otherwise CHPEN should be
set to zero. If the Charge pump is disabled and VDD is
less than 3.6V then the output voltage of the regulator
will not be guaranteed.
The suggested charge pump clock frequency is 20kHz.
The application needs to set the correct value to get the
desired clock frequency. For a 4MHz application, the
CHPCKD bits should be set to the value 11, and for a
2MHz application, the bits should be set to 5.
The REGCEN bit in the CHPRC register is the Regulator/ Charge-pump module enable/disable control bit. If
this bit is disabled, then the regulator will be disabled
and the charge pump will be also be disabled to save
power. When REGCEN = 0, the module will enter the
Power Down Mode ignoring the CHPEN setting. The
ADC and OPA will also be disabled to reduce power.
ADC - Dual Slope
A Dual Slope A/D converter is implemented in this
microcontroller. The dual slope module includes an Operational Amplifier and a buffer for the amplification of
differential signals, an Integrator and a comparator for
the main dual slope AD converter.
If REGCEN is set to ²1², the regulator will be enabled. If
CHPEN is enabled, the charge pump will be active and
will use VDD as its input to generate the double voltage
output. This double voltage will be used as the input voltage for the regulator. If CHPEN is set to ²0², the charge
pump is disabled and the charge pump output will be
equal to the charge pump input, VDD.
Rev. 1.10
There are 2 special function registers related to this
function known as ADCR and ADCD. The ADCR register is the A/D control register, which controls the ADC
block power on/off, the chopper clock on/off, the
charge/discharge control and is also used to read out
the comparator output status. The ADCD register is the
A/D Chopper clock divider register, which defines the
chopper clock to the ADC module.
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HT46R73D-1A
V D S O
P W R
C o n tro l
V O R E G
R v f1
V
D O P A P
-
D O P A N
R v f2
M
V
+
+
U
-
A m p lifie r
A D P W R E N
IN T
X
C M P
-
+
B u ffe r
A D C M P O
+
-
C o m p a ra to r
In te g ra to r
R
A D D IS C H 0
A D D IS C H 1
O n C h ip
O ff C h ip
D O P A O
D C H O P
D S R R
D S R C
D S C C
Note: VINT, VCMP signal can come from different R groups which are selected by software registers.
2 7 n F
1 0 0 k W
2 5 k W
D O P A O
V O R E G
D C H O P
B u ffe r
D O P A N
V B
B r id g e
S e n s o r
C h o p p e r
A m p lifie r
V A
D O P A P
N o te : A ll " R " a n d " C " v a lu e s h e r e a r e fo r r e fe r e n c e o n ly
O ff C h ip
O n C h ip
The following descriptions are based the fact that
ADRR0=0
The ADPWREN bit, defined in ADCR register, is used to
control the ADC module on/off function. The ADCCKEN
bit defined in the ADCR register is used to control the
chopper clock on/off function. When ADCCKEN is set to
²1² it will enable the Chopper clock, with the clock frequency defined by the ADCD registers. The ADC module includes the OPA, buffer, integrator and comparator,
however the Bandgap voltage generator is independent
of this module. It will be automatically enabled when the
regulator is enabled, and also be disabled when the regulator is disabled. The application program should enable the related power to permit them to function and
disable them when idle to conserve power. The
charge/discharge control bits, ADDISCH1~ ADDISCH0,
are used to control the Dual slope circuit charging and
discharging behavior. The ADCMPO bit is read only for
the comparator output, while the ADINTM bits can set
the ADCMPO trigger mode for interrupt generation.
Rev. 1.10
C o m p a ra to r
4 /6 V D S O
1 /6 V D S O
+
A D C M P O
In te g r a to r
D S R R
V
D S C C
D S R C
V
A
R
D S
C
C
D S
The amplifier and buffer combination, form a differential
input pre-amplifier which amplifies the sensor input signal.
The combination of the Integrator, the comparator, the
resistor Rds, between DSRR and DSRC and the capacitor Cds, between DSRC and DSCC form the main body
of the Dual slope ADC.
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March 29, 2016
HT46R73D-1A
The Integrator integrates the output voltage increase or
decrease and is controlled by the ²Switch Circuit² - refer
to the block diagram. The integration and de-integration
curves are illustrated by the following.
than 1/6VDSO. At this point the comparator will change
state and store the time taken, Tc, which is the de-integrating time. The following formula 1 can then be used
to calculate the input voltage VA.
The ²comparator² will switch the state from high to low
when VC, which is the DSCC pin voltage,drops to less
than 1/6 VDSO.
formula 1: VA= (1/3)´VDSO´(2-Tc/Ti).
(Based on ADRR0=0)
In user applications, it is required to choose the correct
value of RDS and CDS to determine the Ti value, to allow
the V C value to operate between 5/6VDSO and
1/6VDSO. Vfull cannot be greater than 5/6VDSO and
Vzero cannot be less than 1/6VDSO
In general applications, the application program will
switch the ADC to the charging mode for a fixed time
called Ti, which is the integrating time. It will then switch
to the dis-charging mode and wait for Vc to drop to less
V
C
V fu ll
V
V z e ro
1 /6 V D S O
T i
T c (z e ro )
T c
T c ( fu ll)
In te g r a te tim e
Bit No.
0
1~2
D e - In te g r a te tim e
Label
ADPWREN
Function
Dual slope block (including input OP) power on/off switching.
0: disable Power
1: Power source comes from the regulator.
Defines the ADC discharge/charge. (ADDISCH1:0)
00: reserved
ADDISCH0~
01: charging. (Integrator input connect to buffer output)
ADDISCH1
10: discharging. (Integrator input connect to VDSO)
11: reserved
ADCMPO
Dual Slope ADC - last stage comparator output.
Read only bit, write data instructions will be ignored.
During the discharging state, when the integrator output is less than the reference voltage,
the ADCMPO will change from high to low.
4~5
ADINTM0~
ADINTM1
ADC integrator interrupt mode definition. These two bit define the ADCMPO data interrupt
trigger mode: (ADINTM1:0)=
00: no interrupt
01: rising edge
10: falling edge
11: both edge
6
ADCCKEN
ADC OP chopper clock source on/off switching.
0: disable
1: enable (clock value is defined by ADCD register)
7
ADRR0
3
ADC resisters selection
0: (VINT, VCMP)= (4/6 VOREG, 1/6 VOREG)
1: (VINT, VCMP)= (4.4/6 VOREG, 1/6 VOREG)
ADCR (18H) Register
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Bit No.
Label
Function
0
1
2
ADCD0
ADCD1
ADCD2
Define the chopper clock (ADCCKEN should be enable), the suggestion clock is around
10kHz.
The chopper clock define :
0: clock= (fSYS/32)/1
1: clock= (fSYS/32)/2
2: clock= (fSYS/32)/4
3: clock= (fSYS/32)/8
4: clock= (fSYS/32)/16
5: clock= (fSYS/32)/32
6: clock= (fSYS/32)/64
7: clock= (fSYS/32)/128
3~7
¾
Reserved
ADCD (1AH) Register
LCD Display Memory
The device provides an area of embedded data memory
for the LCD display. This area is located at 40H to 50H in
Bank 1 of the Data Memory. The bank pointer BP, enables either the General Purpose Data Memory or LCD
Memory to be chosen. When BP is set to ²1², any data
written into location range 40H~50H will affect the LCD
display. When the BP is cleared to ²0², any data written
into 40H~50H will access the general purpose data
memory. The LCD display memory can be read and written to only indirectly using MP1. When data is written
into the display data area, it is automatically read by the
LCD driver which then generates the corresponding
LCD driving signals. To turn the display on or off, a ²1² or
a ²0² is written to the corresponding bit of the display
memory, respectively. The figure illustrates the mapping
between the display memory and LCD pattern for the
device.
LCD frequencies from Int.RCOSC/3 to Int.RCOSC/4.
Note that the LCD frequency is controlled by configuration options, which select the internal division ratio.
4 1 H
4 2 H
4 3 H
4 E H
4 F H
5 0 H
B it
0
0
1
1
2
2
3
S E G M E N T
3
0
1
2
3
1 4
1 5
1 6
Display Memory
LCD Driver Output
The output structure of the device LCD driver can be either 16´4, 17´3 or 17´2 selectable via configuration option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type
LCD driver is R type only. The LCD driver bias voltage
can be 1/2 bias or 1/3 bias by option.
The LCD clock is driven by the IRC clock, which then
passes through a divider, the division ratio of which is
selected by configuration options to provide a range of
Rev. 1.10
4 0 H
C O M
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HT46R73D-1A
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
C O M 0 , C O M 1 , C O M 2
A ll lc d d r iv e r o u tp u ts
V L C D
S
C D
V L C D
S
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V
S
C D
V
S
C D
V
S
C D
V
S
C D
V
S
C D
V
S
L C D
L C D
L C D
L C D
L C D
L C D
C D
V L C D
S
C D
S
V L C D
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Duty, R Type)
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HT46R73D-1A
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
N o te : 1 /4 d u ty , 1 /3 b ia s , R
ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D
LCD Driver Output (1/4 Duty)
Low Voltage Reset/Detector Functions
There is a low voltage detector, LVD, and a low voltage reset circuit,LVR, implemented in the microcontroller. These
two functions can be enabled/disabled by configuration options. Once the LVD option is enabled, the user can use the
MODE.3 bit to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from bit MODE.5.
The MODE register definitions are listed below.
Bit No.
Label
Function
0~1, 4, 6~7
¾
2
IRCC
In HALT mode, IRC clock enable or disable selection bit.
0: IRC clock enable and Int.RCOSC on. 1: IRC clock disabled.
3
LVDC
LVD enable/disable (1/0)
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only. 0: low voltage not detected.
Unused bit, read as ²unknown²
MODE (09H) Register
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HT46R73D-1A
The LVR includes the following specifications:
The LVR has the same effect or function as the external
RES signal which performs a device reset. When in the
Power Down Mode, both LVR and LVD are disabled.
· The low voltage, which is specified as 0.9V~VLVR, has
to remain within this range for a period of time greater
than 1ms. If the low voltage state does not exceed
1ms, the LVR will ignore it will not perform a reset
function.
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as what might happen when changing
a battery, the LVR will automatically reset the device internally.
V
· The LVR has an ²OR² function with the external RES
signal to perform a chip reset.
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Operation Mode
The device has three operational modes. The system clock comes from external RC or crystal oscillator, and whose operational modes can be either Normal, IDLE or HALT mode. These are all selected by the software.
HALT
Instruction
IRCC
WDT
System
Oscillator
IRC Clock
System Clock
Mode
Not executed
x
¾
On
Enabled
External RC or
Crystal Oscillator
Normal
0
x
Off
Enabled and Int.
RCOSC ON
Off
Idle
Enabled
Off
Disabled and Int.
RCOSC ON
Off
HALT
Disabled
Off
Disabled and Int.
RCOSC OFF
Off
HALT
Executed
1
Note: The WDTOSC0:1 register should be set to enable, otherwise, the Int.RCOSC will always be disabled. Refer to
the WDT section for the WDTOSC setup details.
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Options
The following shows the options in the device. All these options should be defined in order to ensure proper functioning
system.
Options
OSC type selection.
There are two types selection: Crystal OSC or RC OSC
fS clock source.
There are two types of selections: Int.RCOSC or fSYS/4
WDT clock source selection.
There are two types of selections: system clock/4 or Int.RCOSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 216/fS, 215/fS, 214/fS or 213/fS
CLR WDT times selection.
This option selects the instruction method of clearing the WDT. ²One time² means that the ²CLR WDT² instruction
can clear the WDT. ²Two times² means only if both the ²CLR WDT1² and ²CLR WDT2² instructions have been executed, can the WDT be cleared.
Buzzer output frequency selection.
There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS² means the configuration option
selected clock source.
Wake-up selection.
This option defines the wake-up capability. A falling edge on each external pin on PA has the capability to wake-up
the device from a Power Down condition. Bit option.
Pull-high selection.
Selects pull-high resistors when the I/O in in the input mode. PA and PB ports are bit options.
I/O pins shared with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
LCD common selection.
There are three types of selections: 2 common (1/2 duty), 3 common (1/3 duty) or 4 common (1/4 duty).
LCD bias selection.
This option is to determine what kind of bias is selected, 1/2 bias or 1/3 bias.
LCD driver clock frequency selection.
There are two types of frequency signals for the LCD driver circuits: Int.RCOSC/3~Int.RCOSC/4.
LCD ON/OFF when in Power Down Mode selection
LVR selection.
LVR enable or disable option
LVD selection.
LVD enable or disable option
INT trigger edge selection: disable; high to low; low to high; low to high or high to low
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HT46R73D-1A
Application Circuits
V
D D
C O M 0 ~ C O M 3 /S E G 1 6
S E G 0 ~ S E G 1 5
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
P A 0 /B Z
R E S
L C D
P o w e r
S u p p ly
P A 2
P A 4 /T M R 0
O S C 1
P A 5 /T M R 1
P A 6 /IN T
P A 7
O S C 2
D D
O S C
4 7 0 p F
P A 3
V S S
V
R
P A 1 /B Z
0 .1 m F
O S C
C ir c u it
V L C D
L C D
P A N E L
O S C 1
R C S y s te m
1 0 0 k W < R O
S C
O s c illa to r
< 2 .4 M W
O S C 2
N M O S o p e n d r a in
C 1
C 2
P B 0 ~ P B 3
O S C 1
R 1
O S C 2
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
O S C C ir c u it
H T 4 6 R 7 3 D -1 A
Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not
necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when
VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be
selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
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HT46R73D-1A
Example
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
0 .1 m F
V S S
V L C D
O S C 1
O S C
C ir c u it
V R E G
C O M 0 ~ C O M 3 /S E G 1 6
S E G 0 ~ S E G 1 5
O S C 2
S e n s o r
L C D
P a n e l
L C D P o w e r S u p p ly
P A 0 /B Z
D O P A P
P A 1 /B Z
D O P A N
2 5 k W
D O P A O
P A 2
D C H O P
P A 3
D S R R
P A 4 /T M R 0
3 0 0 k W
D S R C
4 7 m F
V R E G
P A 6 /IN T
V O R E G
4 7 m F
1 0 m F
P A 5 /T M R 1
D S C C
V S S
V O B G P
1 0 m F
1 0 m F
V O C H P
V O B G P
P A 7
C H P C 1
P B 0 ~ P B 3
C H P C 2
H T 4 6 R 7 3 D -1 A
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s u c c e s s f u l oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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HT46R73D-1A
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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HT46R73D-1A
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine
will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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HT46R73D-1A
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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HT46R73D-1A
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT46R73D-1A
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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HT46R73D-1A
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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HT46R73D-1A
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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HT46R73D-1A
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated
at regular intervals users are reminded to consult the Holtek website for the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page.
· Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
· Packing Meterials Information
· Carton information
Rev. 1.10
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HT46R73D-1A
52-pin LQFP (14mm´14mm) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.622
0.630
0.638
B
0.547
0.551
0.555
C
0.622
0.630
0.638
D
0.547
0.551
0.555
E
¾
0.039 BSC
¾
F
0.015
¾
0.019
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.008
J
0.018
¾
0.030
K
0.005
¾
0.007
a
0°
¾
7°
Symbol
Rev. 1.10
1 3
Dimensions in mm
Min.
Nom.
Max.
A
15.80
16.00
16.20
B
13.90
14.00
14.10
C
15.80
16.00
16.20
D
13.90
14.00
14.10
E
¾
1.0 BSC
¾
F
0.39
¾
0.48
G
1.35
1.40
1.45
H
¾
¾
1.60
I
0.05
¾
0.20
J
0.45
¾
0.75
K
0.13
¾
0.18
a
0°
¾
7°
44
March 29, 2016
HT46R73D-1A
Copyright Ó 2016 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and
Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web
site at http://www.holtek.com.tw.
Rev. 1.10
45
March 29, 2016
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