Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
UDA1334BT
Low power audio DAC
Product specification
2002 May 22
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
CONTENTS
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
14.1
14.2
14.3
2.0 V supply voltage
3.0 V supply voltage
Timing
15
APPLICATION INFORMATION
PACKAGE OUTLINE
1
FEATURES
1.1
1.2
1.3
1.4
General
Multiple format data interface
DAC digital sound processing
Advanced audio configuration
2
APPLICATIONS
16
3
GENERAL DESCRIPTION
17
SOLDERING
4
ORDERING INFORMATION
17.1
5
QUICK REFERENCE DATA
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
System clock
Interpolation filter
Noise shaper
Filter stream DAC
Power-on reset
Feature settings
Digital interface format select
Mute control
De-emphasis control
Power control and sampling frequency select
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
9
LIMITING VALUES
10
HANDLING
11
THERMAL CHARACTERISTICS
12
QUALITY SPECIFICATION
2002 May 22
17.2
17.3
17.4
17.5
2
18
DATA SHEET STATUS
19
DISCLAIMERS
NXP Semiconductors
Product specification
Low power audio DAC
1
1.1
UDA1334BT
FEATURES
General
• 1.8 to 3.6 V power supply voltage
• Integrated digital filter plus DAC
• Supports sample frequencies from 8 to 100 kHz
• Automatic system clock versus sample rate detection
• Low power consumption
• No analog post filtering required for DAC
2
• Slave mode only applications
This audio DAC is excellently suitable for digital audio
portable application, such as portable MD, MP3 and
DVD players.
• Easy application
• SO16 package.
1.2
Multiple format data interface
3
• I2S-bus and LSB-justified format compatible
DAC digital sound processing
The UDA1334BT has basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.
• Digital de-emphasis for 44.1 kHz sampling rate
• Mute function.
1.4
GENERAL DESCRIPTION
The UDA1334BT supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
• 1fs input data rate.
1.3
APPLICATIONS
Advanced audio configuration
• High linearity, wide dynamic range and low distortion
• Standby or Sleep mode in which the DAC is powered
down.
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
UDA1334BT
SO16
2002 May 22
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
3
VERSION
SOT109-1
NXP Semiconductors
Product specification
Low power audio DAC
5
UDA1334BT
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
1.8
2.0
3.6
V
Supplies
VDDA
DAC analog supply voltage
VDDD
digital supply voltage
IDDA
DAC analog supply current
IDDD
digital supply current
1.8
2.0
3.6
V
normal operating mode
−
2.3
−
mA
Sleep mode
−
125
−
μA
normal operating mode
−
1.4
−
mA
clock running
−
250
−
μA
no clock running
−
20
−
μA
−40
−
+85
°C
at 0 dB (FS) digital input; note 1
−
600
−
mV
Sleep mode
Tamb
ambient temperature
Digital-to-analog converter (VDDA = VDDD = 2.0 V)
Vo(rms)
output voltage (RMS value)
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
fs = 44.1 kHz; at 0 dB
−
−80
−
dB
fs = 44.1 kHz; at −60 dB; A-weighted
−
−37
−
dB
fs = 96 kHz; at 0 dB
−
−75
−
dB
fs = 96 kHz; at −60 dB; A-weighted
−
−35
−
dB
S/N
fs = 44.1 kHz; code = 0; A-weighted
−
97
−
dB
fs = 96 kHz; code = 0; A-weighted
−
95
−
dB
−
100
−
dB
at 0 dB (FS) digital input; note 1
−
900
−
mV
fs = 44.1 kHz; at 0 dB
−
−90
−
dB
fs = 44.1 kHz; at −60 dB; A-weighted
−
−40
−
dB
fs = 96 kHz; at 0 dB
−
−85
−
dB
fs = 96 kHz; at −60 dB; A-weighted
−
−37
−
dB
fs = 44.1 kHz; code = 0; A-weighted
−
100
−
dB
fs = 96 kHz; code = 0; A-weighted
−
98
−
dB
−
100
−
dB
at 2.0 V supply voltage
−
7.4
−
mW
at 3.0 V supply voltage
−
17
−
mW
clock running
−
0.75
−
mW
no clock running
−
0.3
−
mW
αcs
signal-to-noise ratio
channel separation
Digital-to-analog converter (VDDA = VDDD = 3.0 V)
Vo(rms)
output voltage (RMS value)
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
S/N
αcs
signal-to-noise ratio
channel separation
Power dissipation (at fs = 44.1 kHz)
P
power dissipation
playback mode
Sleep mode; at 2.0 V supply voltage
Note
1. The DAC output voltage scales proportionally to the power supply voltage.
2002 May 22
4
NXP Semiconductors
Product specification
Low power audio DAC
6
UDA1334BT
BLOCK DIAGRAM
VSSD
VDDD
handbook, full pagewidth
4
BCK
WS
DATAI
1
2
3
5
DIGITAL INTERFACE
UDA1334BT
SYSCLK
MUTE
DEEM
PCS
DE-EMPHASIS
6
7
8
11
INTERPOLATION FILTER
9
SFOR1
SFOR0
10
NOISE SHAPER
VOUTL
15
13
VDDA
VSSA
Fig.1 Block diagram.
2002 May 22
16
DAC
DAC
14
5
12
Vref(DAC)
VOUTR
MGU676
NXP Semiconductors
Product specification
Low power audio DAC
7
UDA1334BT
PINNING
SYMBOL
PIN
PAD TYPE
DESCRIPTION
BCK
1
5 V tolerant digital input pad; note 1
bit clock input
WS
2
5 V tolerant digital input pad; note 1
word select input
DATAI
3
5 V tolerant digital input pad; note 1
serial data input
VDDD
4
digital supply pad
digital supply voltage
VSSD
5
digital ground pad
digital ground
SYSCLK
6
5 V tolerant digital input pad; note 1
system clock input
SFOR1
7
5 V tolerant digital input pad; note 1
serial format select 1
MUTE
8
5 V tolerant digital input pad; note 1
mute control
DEEM
9
5 V tolerant digital input pad; note 1
de-emphasis control
PCS
10
3-level input pad; note 2
power control and sampling frequency select
SFOR0
11
digital input pad; note 2
serial format select 0
Vref(DAC)
12
analog pad
DAC reference voltage
VDDA
13
analog supply pad
DAC analog supply voltage
VOUTL
14
analog output pad
DAC output left
VSSA
15
analog ground pad
DAC analog ground
VOUTR
16
analog output pad
DAC output right
Notes
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages
this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.
handbook, halfpage
BCK 1
16 VOUTR
WS 2
15 VSSA
DATAI 3
VDDD 4
14 VOUTL
UDA1334BT
VSSD 5
13 VDDA
12 Vref(DAC)
SYSCLK 6
11 SFOR0
SFOR1 7
10 PCS
MUTE 8
9
DEEM
MGU675
Fig.2 Pin configuration.
2002 May 22
6
NXP Semiconductors
Product specification
Low power audio DAC
8
UDA1334BT
FUNCTIONAL DESCRIPTION
8.1
Table 2
System clock
Example using a 12.228 MHz system clock
CLOCK MODE
SAMPLING FREQUENCY
128fs
96 kHz
192fs
64 kHz(1)
The UDA1334BT operates in slave mode only; this means
that in all applications the system must provide the system
clock and the digital audio interface signals
(BCK and WS).
The system clock must be locked in frequency to the digital
interface signals.
The UDA1334BT automatically detects the ratio between
the SYSCLK and WS frequencies.
256fs
48 kHz
384fs
32 kHz
512fs
24 kHz
768fs
16 kHz
Note
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in 192fs
mode the sampling frequency should be limited to
55 kHz.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS.
Remarks:
8.2
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
The interpolation digital filter interpolates from 1fs to 64fs
by cascading FIR filters (see Table 3).
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
Table 3
The modes which are supported are given in Table 1.
Table 1
Interpolation filter
Supported sampling ranges
Interpolation filter characteristics
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.02
>0.55fs
−50
0 to 0.45fs
>114
Stop band
CLOCK MODE
SAMPLING RANGE
768fs
8 to 55 kHz
512fs
8 to 100 kHz
8.3
384fs
8 to 100 kHz
256fs
8 to 100 kHz
192fs
8 to 100 kHz(1)(2)
128fs
8 to 100 kHz(2)
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
Dynamic range
Notes
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in
192fs mode the sampling frequency should be limited
to 55 kHz.
2. Not supported in the low sampling frequency mode.
An example is given in Table 2 for a 12.228 MHz system
clock input.
2002 May 22
7
Noise shaper
NXP Semiconductors
Product specification
Low power audio DAC
8.4
UDA1334BT
Filter stream DAC
8.5
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. No post-filter is needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
Power-on reset
The UDA1334BT has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 μs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
3.0
VDDD
(V)
handbook, halfpage
1.5
0
t
handbook, halfpage
3.0 V
3.0
VDDA
VDDA 13
(V)
50 kΩ
C1 >
10 μF
1.5
RESET
CIRCUIT
Vref(DAC)
12
0
50 kΩ
t
UDA1334BT
3.0
Vref(DAC)
MGU678
(V)
1.5
1.25
0.75
0
>1 μs
t
MGL984
Fig.3 Power-on reset circuit.
2002 May 22
Fig.4 Power-on reset timing.
8
NXP Semiconductors
Product specification
Low power audio DAC
8.6
UDA1334BT
Feature settings
8.6.4
The features of the UDA1334BT can be set by control
pins SFOR1, SFOR0, MUTE, DEEM and PCS.
8.6.1
Pin PCS is a 3-level pin and is used to set the mode of the
UDA1334BT. The definition is given in Table 7.
DIGITAL INTERFACE FORMAT SELECT
Table 7
The digital audio interface formats (see Fig.5) can be
selected via the pins SFOR1 and SFOR0 as shown in
Table 4.
Table 4
SFOR0
LOW
LOW
I2S-bus input
LOW
HIGH
LSB-justified 16 bits input
HIGH
LOW
LSB-justified 20 bits input
HIGH
HIGH
LSB-justified 24 bits input
Mute control
FUNCTION
LOW
mute off
HIGH
mute on
8.6.3
DE-EMPHASIS CONTROL
De-emphasis can be switched on for fs = 44.1 kHz by
setting pin DEEM at HIGH level. The function description
of pin DEEM is given in Table 6.
Table 6
De-emphasis control
DEEM
FUNCTION
LOW
de-emphasis off
HIGH
de-emphasis on
Remark: the de-emphasis function in only supported in the
normal operating mode, not in the low sampling frequency
mode.
2002 May 22
normal operating mode
MID
low sampling frequency mode
Power-down or Sleep mode
The low sampling frequency mode is required to have a
higher oversampling rate in the noise shaper in order to
improve the signal-to-noise ratio. In this mode the
oversampling ratio of the noise shaper will be 128fs instead
of 64fs.
The output signal can be soft muted by setting pin MUTE
to HIGH level as shown in Table 5.
MUTE
FUNCTION
LOW
HIGH
INPUT FORMAT
MUTE CONTROL
Table 5
PCS function definition
PCS
Data format selection
SFOR1
8.6.2
POWER CONTROL AND SAMPLING FREQUENCY
SELECT
9
2
>=8
3
1
2
3
MSB
B2
>=8
BCK
DATA
MSB
B2
MSB
I2S-BUS FORMAT
WS
LEFT
NXP Semiconductors
1
Low power audio DAC
handbook, full pagewidth
2002 May 22
RIGHT
LEFT
WS
RIGHT
16
15
1
16
B15 LSB
MSB
2
15
2
1
BCK
DATA
MSB
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
10
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
24
23
22
21
20
RIGHT
19
18
17
16
15
2
1
24
B23 LSB
MSB
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGS752
Product specification
Fig.5 Digital audio formats
UDA1334BT
LSB-JUSTIFIED FORMAT 24 BITS
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
4.0
V
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
human body model
−2000
+2000
V
machine model
−200
+200
V
output short-circuited to VSSA
−
450
mA
output short-circuited to VDDA
−
300
mA
VDD
supply voltage
Txtal(max)
note 1
short-circuit current of DAC
Isc(DAC)
note 2
Note
1. All supply connections must be made to the same power supply.
2. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth(j-a)
CONDITIONS
VALUE
UNIT
145
K/W
thermal resistance from junction to ambient in free air
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-D”.
13 DC CHARACTERISTICS
VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
DAC analog supply voltage note 1
1.8
2.0
3.6
V
VDDD
digital supply voltage
1.8
2.0
3.6
V
IDDA
DAC analog supply current normal operating mode
at 2.0 V supply voltage
−
2.3
−
mA
at 3.0 V supply voltage
−
3.5
−
mA
note 1
Sleep mode
2002 May 22
at 2.0 V supply voltage
−
125
−
μA
at 3.0 V supply voltage
−
175
−
μA
11
NXP Semiconductors
Product specification
Low power audio DAC
SYMBOL
IDDD
PARAMETER
digital supply current
UDA1334BT
CONDITIONS
MIN.
TYP.
MAX.
UNIT
normal operating mode
at 2.0 V supply voltage
−
1.4
−
mA
at 3.0 V supply voltage
−
2.1
−
mA
Sleep mode;
at 2.0 V supply voltage
clock running
−
250
−
μA
no clock running
−
20
−
μA
Sleep mode;
at 3.0 V supply voltage
clock running
−
375
−
μA
no clock running
−
30
−
μA
Digital input pins; note 2
VIH
HIGH-level input voltage
at 2.0 V supply voltage
1.3
−
3.3
V
at 3.0 V supply voltage
2.0
−
5.0
V
at 2.0 V supply voltage
−0.5
−
+0.5
V
VIL
LOW-level input voltage
−0.5
−
+0.8
V
⎪ILI⎪
input leakage current
−
−
1
μA
Ci
input capacitance
−
−
10
pF
at 3.0 V supply voltage
3-level input: pin PCS
VIH
HIGH-level input voltage
0.9VDDD
−
VDDD + 0.5
V
VIM
MID-level input voltage
0.4VDDD
−
0.6VDDD
V
VIL
LOW-level input voltage
−0.5
−
+0.5
V
DAC
Vref(DAC)
reference voltage
Ro(ref)
output resistance on
pin Vref(DAC)
Io(max)
maximum output current
RL
load resistance
CL
load capacitance
with respect to VSSA
(THD + N)/S < 0.1%;
RL = 800 Ω
note 3
0.45VDDA
0.5VDDA
0.55VDDA
V
−
25
−
kΩ
−
1.6
−
mA
3
−
−
kΩ
−
−
50
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
2002 May 22
12
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
14 AC CHARACTERISTICS
14.1 2.0 V supply voltage
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ.; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DAC
Vo(rms)
output voltage (RMS value)
ΔVo
unbalance between channels
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
S/N
signal-to-noise ratio
−
600
−
mV
−
0.1
−
dB
fs = 44.1 kHz; at 0 dB
−
−80
−
dB
fs = 44.1 kHz; at −60 dB;
A-weighted
−
−37
−
dB
fs = 96 kHz; at 0 dB
−
−75
−
dB
fs = 96 kHz; at −60 dB; A-weighted
−
−35
−
dB
fs = 44.1 kHz; code = 0; A-weighted −
97
−
dB
−
95
−
dB
−
100
−
dB
−
60
−
dB
at 0 dB (FS) digital input
fs = 96 kHz; code = 0; A-weighted
αcs
channel separation
PSRR
power supply rejection ratio
fripple = 1 kHz; Vripple = 30 mV (p-p)
14.2 3.0 V supply voltage
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DAC
Vo(rms)
output voltage (RMS value)
ΔVo
unbalance between channels
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
S/N
signal-to-noise ratio
αcs
channel separation
PSRR
power supply rejection ratio
2002 May 22
at 0 dB (FS) digital input
−
900
−
mV
−
0.1
−
dB
fs = 44.1 kHz; at 0 dB
−
−90
−
dB
fs = 44.1 kHz; at −60 dB;
A-weighted
−
−40
−
dB
fs = 96 kHz; at 0 dB
−
−85
−
dB
fs = 96 kHz; at −60 dB; A-weighted
−
−37
−
dB
fs = 44.1 kHz; code = 0; A-weighted −
100
−
dB
98
−
dB
fs = 96 kHz; code = 0; A-weighted
−
−
100
−
dB
fripple = 1 kHz; Vripple = 30 mV (p-p)
−
60
−
dB
13
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
14.3 Timing
VDDD = VDDA = 1.8 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing (see Fig.6)
Tsys
system clock cycle time
tCWH
system clock HIGH time
tCWL
system clock LOW time
fsys = 256fs
35
88
780
ns
fsys = 384fs
23
59
520
ns
fsys = 512fs
17
44
390
ns
fsys < 19.2 MHz
0.3Tsys −
0.7Tsys ns
fsys ≥ 19.2 MHz
0.4Tsys −
0.6Tsys ns
fsys < 19.2 MHz
0.3Tsys −
0.7Tsys ns
fsys ≥ 19.2 MHz
0.4Tsys −
0.6Tsys ns
Reset timing
treset
reset time
1
−
−
μs
Serial interface timing (see Fig.7)
fBCK
bit clock frequency
−
−
64fs
Hz
tBCKH
bit clock HIGH time
50
−
−
ns
tBCKL
bit clock LOW time
50
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tsu(DATAI)
set-up time data input
20
−
−
ns
th(DATAI)
hold time data input
0
−
−
ns
tsu(WS)
set-up time word select
20
−
−
ns
th(WS)
hold time word select
10
−
−
ns
Note
1. The typical value of the timing is specified at fs = 44.1 kHz (sampling frequency).
2002 May 22
14
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
t CWH
handbook, full pagewidth
MGR984
t CWL
Tsys
Fig.6 System clock timing.
handbook, full pagewidth
WS
th(WS)
tBCKH
tr
tsu(WS)
tf
BCK
tsu(DATAI)
tBCKL
Tcy(BCK)
th(DATAI)
DATAI
MGL880
Fig.7 Serial interface timing.
2002 May 22
15
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
15 APPLICATION INFORMATION
R7
1Ω
C9
system
clock
digital
supply voltage
analog
supply voltage
handbook, full pagewidth
R5
SYSCLK
47 Ω
47 μF
(16 V)
47 μF
(16 V)
C10
C6
100 nF
(63 V)
VSSA
100 nF
(63 V)
15
VDDA
13
R6
1Ω
C5
VSSD
5
VDDD
4
6
14
BCK
WS
DATAI
SFOR1
SFOR0
MUTE
DEEM
PCS
VOUTL C3
47 μF
(16 V)
1
2
R3
R1
220 kΩ
C1
3
7
11
UDA1334BT
16
8
9
VOUTR C4
47 μF
(16 V)
12
left
output
100 Ω
10 nF
(63 V)
R4
right
output
100 Ω
R2
220 kΩ
C2
10 nF
(63 V)
Vref(DAC)
C8
100 nF
(63 V)
10
C7
47 μF
(16 V)
MGU677
Fig.8 Typical application diagram.
2002 May 22
16
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
16 PACKAGE OUTLINE
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
2002 May 22
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
17
o
8
o
0
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
17 SOLDERING
17.1
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
17.2
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
17.3
17.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 May 22
Manual soldering
18
NXP Semiconductors
Product specification
Low power audio DAC
17.5
UDA1334BT
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your NXP Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 22
19
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
18 DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
19 DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2002 May 22
20
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BT
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2002 May 22
21
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp22
Date of release: 2002 May 22
Document order number:
9397 750 0974
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