Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
UDA1344TS
Low-voltage low-power stereo
audio CODEC with DSP features
Product specification
Supersedes data of 2001 Mar 27
2001 Jun 29
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
FEATURES
General
• Low power consumption
• 3.0 V power supply
• System clock of 256fs, 384fs and 512fs
• Supports sampling frequencies from 8 to 55 kHz
• Non-inverting ADC plus integrated high-pass filter to
cancel DC offset
Advanced audio configuration
• ADC supports 2 V (RMS) input signals
• Stereo single-ended input configuration
• Overload detector for easy record level control
• Separate power control for ADC and DAC
• Stereo line output (under microcontroller volume
control), no post filter required
• Integrated digital interpolation filter plus non-inverting
DAC
• High linearity, dynamic range and low distortion.
• Functions controllable either via L3 microcontroller
interface or via static pins
GENERAL DESCRIPTION
The UDA1344TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
• UDA1344TS is pin and function compatible with
UDA1340M
• Small package size (SSOP28)
• Easy application.
Multiple format input interface
• I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
The UDA1344TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
data format with word lengths of 16, 18 and 20 bits. The
UDA1344TS also supports three combined data formats
with MSB-justified data output and LSB-justified
16, 18 and 20 bits data input.
• Three combined data formats with MSB-justified output
and LSB-justified 16, 18 and 20 bits input
• 1fs input and output format data rate.
DAC digital sound processing
The sound processing features of the UDA1344TS can be
used in the L3 mode only:
The UDA1344TS can be controlled either via static pins or
via the L3 interface. In the L3 mode the UDA1344TS has
special Digital Sound Processing (DSP) features in
playback mode such as de-emphasis, volume control,
bass boost, treble and soft mute.
• Digital tone control, bass boost and treble
• Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller
• Digital de-emphasis for 32, 44.1 and 48 kHz
• Soft mute.
ORDERING INFORMATION
TYPE
NUMBER
UDA1344TS
2001 Jun 29
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
2
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA(ADC)
ADC analog supply voltage
VDDA(DAC)
DAC analog supply voltage
2.7
3.0
3.6
V
VDDO
operational amplifier supply voltage
2.7
3.0
3.6
V
VDDD
digital supply voltage
2.7
3.0
3.6
V
IDDA(ADC)
ADC analog supply current
operating
−
9.0
11.0
mA
ADC power-down
−
3.5
5.0
mA
operating
−
4.0
6.0
mA
DAC power-down
−
25
75
μA
operating
−
4.0
6.0
mA
DAC power-down
−
250
350
μA
operating
−
6.0
9.0
mA
DAC power-down
−
2.5
4.0
mA
ADC power-down
−
3.5
5.0
mA
−40
−
+85
°C
IDDA(DAC)
IDDO
IDDD
Tamb
DAC analog supply current
operational amplifier supply current
digital supply current
2.7
ambient temperature
3.0
3.6
V
Analog-to-digital converter
Vi(rms)
input voltage (RMS value)
notes 1 and 2
−
1.0
−
V
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
−
−85
−80
dB
at −60 dB; A-weighted
−
−35
−30
dB
S/N
signal-to-noise ratio
Vi = 0 V; A-weighted
−
95
−
dB
αcs
channel separation
−
100
−
dB
Digital-to-analog converter
Vo(rms)
output voltage (RMS value)
notes 3 and 4
−
900
−
mV
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
−
−90
−85
dB
at −60 dB; A-weighted
−
−37
−
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
−
100
−
dB
αcs
channel separation
−
100
−
dB
Power performance
PADDA
power consumption in record and
playback mode
−
69
−
mW
PDA
power consumption in playback mode
−
42
−
mW
PAD
power consumption in record mode
−
37.5
−
mW
PPD
power consumption in power-down mode
−
17
−
mW
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC is inversely proportional to the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply voltage.
2001 Jun 29
3
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
BLOCK DIAGRAM
VDDA(ADC) VSSA(ADC)
handbook, full pagewidth
2
3
VINL
VADCP
1
VADCN
7
Vref(A)
6
0 dB/6 dB
SWITCH
4
5
0 dB/6 dB
SWITCH
ADC
ADC
8
VDDD
VSSD
DATAO
BCK
WS
DATAI
10
21
DECIMATION FILTER
20
11
MC1
MC2
MP5
DC-CANCELLATION FILTER
18
13
16
DIGITAL INTERFACE
17
14
L3-BUS
INTERFACE
15
19
12
MP1
VINR
9
MP2
MP3
MP4
SYSCLK
DSP FEATURES
INTERPOLATION FILTER
UDA1344TS
NOISE SHAPER
DAC
DAC
VOUTL
26
24
25
27
VDDO
VSSO
23
VDDA(DAC)
22
VSSA(DAC)
Fig.1 Block diagram.
2001 Jun 29
4
28
Vref(D)
VOUTR
MGL441
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
PINNING
SYMBOL
PIN
DESCRIPTION
VSSA(ADC)
1
ADC analog ground
VDDA(ADC)
2
ADC analog supply voltage
VINL
3
ADC input left
Vref(A)
4
ADC reference voltage
VINR
5
ADC input right
VADCN
6
ADC negative reference voltage
VSSA(ADC) 1
28 Vref(D)
VADCP
7
ADC positive reference voltage
VDDA(ADC) 2
27 VSSO
MC1
8
mode control 1 input (pull-down)
MP1
9
multi-purpose pin 1 output
VDDD
10
digital supply voltage
VSSD
11
digital ground
SYSCLK
12
system clock input:
256fs, 384fs or 512fs
handbook, halfpage
26 VOUTL
VINL 3
25 VDDO
Vref(A) 4
24 VOUTR
VINR 5
23 VDDA(DAC)
VADCN 6
VADCP 7
UDA1344TS
22 VSSA(DAC)
MP2
13
multi-purpose pin 2 input
MC1 8
21 MC2
MP3
14
multi-purpose pin 3 input
MP1 9
20 MP5
MP4
15
multi-purpose pin 4 input
BCK
16
bit clock input
WS
17
word select input
DATAO
18
data output
DATAI
19
data input
MP2 13
16 BCK
MP5
20
multi-purpose pin 5 output
(pull-down)
MP3 14
15 MP4
MC2
21
mode control 2 input (pull-down)
VSSA(DAC)
22
DAC analog ground
VDDA(DAC)
23
DAC analog supply voltage
VOUTR
24
DAC output right
VDDO
25
operational amplifier supply voltage
VOUTL
26
DAC output left
VSSO
27
operational amplifier ground
Vref(D)
28
DAC reference voltage
2001 Jun 29
VDDD 10
19 DATAI
VSSD 11
18 DATAO
17 WS
SYSCLK 12
MGL442
Fig.2 Pin configuration.
5
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
FUNCTIONAL DESCRIPTION
Table 1
The UDA1344TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system clock must be
locked in frequency to the digital interface input signals.
Application modes using input gain stage
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present
0 dB
2 V (RMS)
Present
6 dB
1 V (RMS)
RESISTOR
(12 kΩ)
The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: fBCK = < 128 × fWS.
Absent
0 dB
1 V (RMS)
Absent
6 dB
0.5 V (RMS)
Remarks:
1. The WS edge MUST fall on the negative edge of the
BCK clock at all times for proper operation of the digital
I/O data interface
Decimation filter (ADC)
The decimation from 128fs to 1fs is performed in 2 stages.
sin x
The first stage realizes 3rd-order ------------ characteristic. This
x
filter decreases the sample rate by 16.
2. The sampling frequency range is from 8 to 55 kHz
3. For MSB- and LSB-justified formats it is important to
have a WS signal with a duty factor of 50%.
The second stage, a Finite Impulse Response (FIR) filter,
consists of 3 half-band filters, each decimating by a factor
of 2.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1344TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Table 2
In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input signals and can be set, via an external
resistor, to support 2 V (RMS) input signals.
ITEM
CONDITIONS
VALUE (dB)
Pass-band ripple
0 − 0.45fs
±0.05
>0.55fs
−60
0 − 0.45fs
108
DC
−1.16
Stop band
Dynamic range
Overall gain with
0 dB input to the
ADC
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block. The pin to select the gain switch is given
in Section “L3 mode”. This block can be used in
applications in which both 1 V (RMS) and 2 V (RMS) input
signals are available.
DC-cancellation filter (ADC)
An optional Infinite Impulse-Response (IIR) high-pass filter
is provided to remove unwanted DC components.
The operation is selected by the microcontroller via the
L3 interface. The filter characteristics are given in Table 3.
In applications in which a 2 V (RMS) input signal is used,
a 12 kΩ resistor must be connected in series with the input
of the ADC. This makes a voltage divider with the internal
ADC resistor and makes sure only 1 V (RMS) maximum is
input to the IC. Using this application for a 2 V (RMS) input
signal, the gain switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
Table 3
DC-cancellation filter characteristics
ITEM
Pass-band ripple
Pass-band gain
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1.
2001 Jun 29
Decimation filter characteristics
Droop
Attenuation at DC
Dynamic range
6
CONDITIONS
VALUE (dB)
−
none
−
0
at 0.00045fs
0.031
at 0.00000036fs
>40
0 − 0.45fs
>110
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Mute (ADC)
Multiple format input/output interface
On recovery from power-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether the
DC-cancellation filter is selected:
The UDA1344TS supports the following data input/output
formats:
• I2S-bus format with data word length of up to 20 bits
• MSB-justified serial format with data word length of up to
20 bits
• DC cancel off:
1024
t = ------------- ; t = 23.2 ms at fs = 44.1 kHz
fs
• LSB-justified serial format with data word lengths of
16, 18 or 20 bits (in L3 mode only)
• Combined data formats:
• DC cancel on:
t = 12288
---------------- ; t = 279 ms at fs = 44.1 kHz.
fs
– L3 mode: MSB-justified data output and
LSB-justified 16, 18 and 20 bits data input
– Static pin mode: MSB-justified data output and
LSB-justified 16 and 20 bits data input.
Interpolation filter (DAC)
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
The digital filter interpolates from 1fs to 128fs by means of
a cascade of a recursive filter and an FIR filter.
Table 4
Control mode selection
Interpolation filter characteristics
ITEM
CONDITIONS
VALUE (dB)
Pass-band ripple
0 − 0.45fs
±0.03
Stop band
Dynamic range
Gain
>0.55fs
−50
0 − 0.45fs
108
DC
−3.5
The UDA1344TS can be used under L3 microcontroller
interface control or static pin control. The mode can be set
via the mode control pins MC1 and MC2 (see Table 5).
Table 5
Mode control pins
PIN MC2
PIN MC1
MODE
LOW
LOW
L3 mode
Noise shaper (DAC)
LOW
HIGH
Test mode
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).
HIGH
LOW
HIGH
HIGH
Important: in the L3 mode the UDA1344TS is completely
pin and function compatible with the UDA1340M.
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. A post-filter is not needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
2001 Jun 29
Static pin mode
7
2
>=8
3
1
2
3
MSB
B2
>=8
MSB
DATA
B2
MSB
I2S-BUS FORMAT
LEFT
WS
1
2
RIGHT
>=8
3
1
2
>=8
3
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
8
1
16
B15 LSB
MSB
15
2
1
NXP Semiconductors
1
BCK
Low-voltage low-power stereo audio
CODEC with DSP features
ndbook, full pagewidth
2001 Jun 29
RIGHT
LEFT
WS
BCK
DATA
MSB
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
RIGHT
18
17
16
15
2
1
18
B17 LSB
MSB
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
B2
B3
B4
B5
B6
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface formats.
B2
B3
B4
B5
B6
B19 LSB
MBL140
Product specification
MSB
UDA1344TS
DATA
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Static pin mode
MUTE AND DE-EMPHASIS
The UDA1344TS is set to static pin mode by setting both
pins MC1 and MC2 to HIGH level.
The level definition of pin MP2 pin is given in Table 8.
Table 8
The controllable features in this mode are:
• System clock frequency selection
Levels for pin MP2
PIN MP2
• Data input/output format selection
LOW
• De-emphasis and mute control
no de-emphasis and mute
0.5VDDD
HIGH
• Power-down and ADC input level selection.
SELECTION
de-emphasis 44.1 kHz
mute
PINNING DEFINITION
INPUT/OUTPUT DATA FORMAT SELECTION
The pinning definition in the static pin mode is given in
Table 6.
The input/output data format can be selected using
pins MP1 and MP5 as given in Table 9.
Table 6
Table 9
Pinning definition in static pin model
PIN
Data format selection
PIN MP1 PIN MP5
DESCRIPTION
SELECTION
MP1
data input/output setting
LOW
LOW
input: MSB-justified
MP2
three-level pin to select no
de-emphasis, de-emphasis or mute
LOW
HIGH
input: I2S-bus
HIGH
LOW
MP3
256fs or 384fs system clock selection
input: LSB-justified 20 bits;
output: MSB-justified
MP4
three-level pin to select
ADC power-down, ADC input
1 V (RMS) or ADC input 2 V (RMS)
HIGH
HIGH
input: LSB-justified 16 bits;
output: MSB-justified
MP5
data input/output setting
ADC INPUT VOLTAGE SELECTION AND POWER-DOWN
SYSTEM CLOCK
In the static pin mode the three-level pin MP4 is used to
select 0 or 6 dB gain and power-down.
In the static pin mode the options are 256fs and 384fs as
given in Table 7.
Table 10 Levels for pin MP4
PIN MP4
Table 7
System clock selection
PIN MP3
LOW
SELECTION
LOW
256fs clock frequency
HIGH
384fs clock frequency
2001 Jun 29
9
SELECTION
ADC power-down
0.5VDDD
6 dB gain
HIGH
0 dB gain
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
L3 mode
ADC OUTPUT OVERLOAD DETECTION
The UDA1344TS is set to the L3 mode by setting both
pins MC1 and MC2 to LOW level.
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected
pin MP1 is forced to HIGH level for at least 512fs cycles
(11.6 ms at fs = 44.1 kHz). This time-out is reset for each
infringement.
The static pins in this mode are used for:
• ADC output overload detection
• L3 interface signal input
• ADC input voltage selection.
The controllable features via the L3 interface and the
definition of the control registers are given in
Section “L3 interface”.
ADC INPUT VOLTAGE SELECTION
In the L3 mode pin MP5 is used to select 0 or 6 dB gain.
Table 12 Levels for pin MP5
PINNING DEFINITION
PIN MP4
The pinning definition in the L3 mode is given in Table 11.
Table 11 Pinning definition in L3 mode
PIN
FUNCTION
MP1
ADC output overload detection
MP2
L3MODE input
MP3
L3CLOCK input
MP4
L3DATA input
MP5
ADC input voltage selection:
1 V (RMS) or 2 V (RMS)
2001 Jun 29
10
SELECTION
LOW
0 dB gain
HIGH
6 dB gain
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
L3 INTERFACE
Data bits 1 and 0 indicate the type of subsequent data
transfer as given in Table 13.
The UDA1344TS has a microcontroller input mode. In the
microcontroller control mode, all the digital sound
processing features and the system controlling features
can be controlled by the microcontroller. The controllable
features are:
Table 13 Selection of data transfer
BIT 1
BIT 0
TRANSFER
0
0
data (volume, bass boost, treble,
de-emphasis, mute, mode and
power control)
• Power control
0
1
not used
• DC filtering
1
0
status (system clock frequency,
data input/output format and
DC filter)
1
1
not used
• System clock frequency
• Data input format
• De-emphasis
• Volume
• Flat/min./max. switch
• Bass boost
In the event that the UDA1344TS receives a different
address, it will deselect its microcontroller interface logic.
• Treble
• Mute.
Data transfer mode
The exchange of data and control information between the
microcontroller and the UDA1344TS is accomplished
through a serial hardware interface comprising the
following lines:
The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1344TS receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode and is shown in Fig.5.
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
The maximum input clock and data rate is 64fs.
All transfers are byte wise, i.e. they are based on groups of
8 bits. Data will be stored in the UDA1344TS after the
eighth bit of a byte has been received.
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is LSB first
and is organized in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: address mode and data transfer mode.
A multibyte data transfer is illustrated in Fig.6.
The address mode is required to select a device
communicating via the L3 interface and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1344TS can only be in one direction:
input to the UDA1344TS to program its sound processing
and other functional features.
Programming the sound processing and other
features
The sound processing and other feature values are stored
in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred. This is performed in the
address mode by bit 1 and bit 0 (see Table 13).
Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits.
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6).
The other bits in the data byte (bits 5 to 0) is the value that
is placed in the selected registers.
The fundamental timing is shown in Fig.4.
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1344TS is 000101 (bits 7 to 2).
2001 Jun 29
11
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
handbook, full pagewidth
L3MODE
tsu(L3)A
th(L3)A
tCLK(L3)L
tsu(L3)A
tCLK(L3)H
th(L3)A
L3CLOCK
Tcy(CLK)(L3)
tsu(L3)DA
th(L3)DA
BIT 0
L3DATA
BIT 7
MGL723
Fig.4 Timing in address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE
tCLK(L3)L
Tcy(CLK)L3
tCLK(L3)H
tsu(L3)D
th(L3)D
L3CLOCK
th(L3)DA
tsu(L3)DA
L3DATA
WRITE
BIT 7
BIT 0
MGL882
Fig.5 Timing in data transfer mode.
2001 Jun 29
12
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
tstp(L3)
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.6 Multibyte data transfer.
L3 interface registers
When the data transfer of type ‘status’ is selected, the features system clock frequency, data input format and DC filter
can be controlled.
Table 14 Data transfer of type ‘status’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
SC1
SC0
IF2
IF1
IF0
DC
SC = system clock frequency (2 bits); see Table 16
IF = data input format (3 bits); see Table 17
DC = DC filter (1 bit); see Table 18
When the data transfer of type ‘data’ is selected, the features volume, bass boost, treble, de-emphasis, mute, mode and
power control can be controlled.
Table 15 Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
VC5
VC4
VC3
VC2
VC1
VC0
VC = volume control (6 bits); see Table 19
0
1
BB3
BB2
BB1
BB0
TR1
TR0
BB = bass boost (4 bits); see Table 20
1
0
0
DE1
DE0
MT
M1
M0
DE = de-emphasis (2 bits); see Table 22
TR = treble (2 bits); see Table 21
MT = mute (1 bit); see Table 23
M = filter mode (2 bits); see Table 24
1
1
2001 Jun 29
0
0
0
0
PC1
PC0
13
PC = power control (2 bits); see Table 25
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
SYSTEM CLOCK FREQUENCY
VOLUME CONTROL
A 2-bit value to select the used external clock frequency.
A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to −∞ dB in steps of 1 dB.
Table 16 System clock frequency settings
Table 19 Volume settings
SC1
SC0
SELECTION
0
0
512fs
0
1
384fs
0
0
0
0
0
0
0
0
0
0
0
1
0
VC5 VC4 VC3 VC2 VC1 VC0
VOLUME (dB)
1
0
256fs
0
1
1
not used
0
0
0
0
1
0
−1
0
0
0
0
1
1
−2
DATA INPUT FORMAT
:
:
:
:
:
:
:
A 3-bit value to select the used data format.
1
1
1
0
1
1
−58
1
1
1
1
0
0
−59
1
1
1
1
0
1
−60
1
1
1
1
1
0
−∞
1
1
1
1
1
1
−∞
Table 17 Data format settings
IF2
IF1
IF0
FORMAT
0
0
0
I2S-bus
0
0
1
LSB-justified 16 bits
0
1
0
LSB-justified 18 bits
0
1
1
LSB-justified 20 bits
1
0
0
MSB-justified
1
0
1
input: LSB-justified 16 bits;
output: MSB-justified
1
1
0
input: LSB-justified 18 bits;
output: MSB-justified
1
1
1
BASS BOOST
A 4-bit value to program the bass boost setting. The used
set depends on the mode bits M1 and M0.
Table 20 Bass boost settings
BASS BOOST SETTING
BB3 BB2 BB1 BB0
input: LSB-justified 20 bits;
output: MSB-justified
DC FILTER
A 1-bit value to enable the digital DC filter.
Table 18 DC filtering
DC
2001 Jun 29
SELECTION
0
no DC filtering
1
DC filtering
14
FLAT
(dB)
MIN.
(dB)
MAX.
(dB)
0
0
0
0
0
0
0
0
0
0
1
0
2
2
0
0
1
0
0
4
4
0
0
1
1
0
6
6
0
1
0
0
0
8
8
0
1
0
1
0
10
10
0
1
1
0
0
12
12
0
1
1
1
0
14
14
1
0
0
0
0
16
16
1
0
0
1
0
18
18
1
0
1
0
0
18
20
1
0
1
1
0
18
22
1
1
0
0
0
18
24
1
1
0
1
0
18
24
1
1
1
0
0
18
24
1
1
1
1
0
18
24
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
TREBLE
MODE
A 2-bit value to program the treble setting. The used set
depends on the mode bits M1 and M0.
A 2-bit value to program the mode of the sound processing
filters of bass boost and treble.
Table 21 Treble settings
Table 24 Flat/min./max. switch
M1
M0
MAX. (dB)
0
0
flat
1
min.
TREBLE SETTING
TR1
TR0
FLAT (dB)
MIN. (dB)
SELECTION
0
0
0
0
0
0
0
1
0
2
2
1
0
min.
1
0
0
4
4
1
1
max.
1
1
0
6
6
POWER CONTROL
A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.
DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.
Table 25 Power control settings
Table 22 De-emphasis settings
SELECTION
DE1
DE0
SELECTION
0
0
no de-emphasis
0
1
de-emphasis 32 kHz
0
1
0
de-emphasis 44.1 kHz
1
1
de-emphasis 48 kHz
PC1
MUTE
A 1-bit value to enable the digital mute.
Table 23 Mute
MT
SELECTION
0
no muting
1
muting
2001 Jun 29
15
PC0
ADC
DAC
0
off
off
0
1
off
on
1
0
on
off
1
1
on
on
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−
5.0
V
Txtal(max)
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
note 1
−3000 +3000 V
note 2
−300
+300
V
−
200
mA
output short-circuited to VSSA(DAC)
−
482
mA
output short-circuited to VDDA(DAC)
−
346
mA
Ilu(prot)
latch-up protection current
Tamb = 25 °C; VDD = 3.6 V
Isc(DAC)
DAC short-circuit current:
Tamb = 0 °C; VDDA = 3.0 V; note 3
Notes
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
2. Equivalent to discharging a 200 pF capacitor via a 2.5 μH series inductor.
3. DAC operation cannot be guaranteed after a short-circuit has occurred.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
90
K/W
in free air
DC CHARACTERISTICS
VDDD = VDDA = VDDO = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies; note 1
VDDA(ADC) ADC analog supply voltage
2.7
3.0
3.6
V
VDDA(DAC) DAC analog supply voltage
2.7
3.0
3.6
V
VDDO
operational amplifier supply voltage
2.7
3.0
3.6
V
VDDD
digital supply voltage
IDDA(ADC)
ADC analog supply current
IDDA(DAC)
DAC analog supply current
2.7
3.0
3.6
V
operating
−
9.0
11.0
mA
ADC power-down
−
3.5
5.0
mA
operating
−
4.0
6.0
mA
DAC power-down
−
25
75
μA
−
4.0
6.0
mA
IDDO
operational amplifier supply current operating
IDDD
digital supply current
2001 Jun 29
DAC power-down
−
250
300
μA
operating
−
6.0
9.0
mA
DAC power-down
−
2.5
4.0
mA
ADC power-down
−
3.5
5.0
mA
16
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
SYMBOL
PARAMETER
UDA1344TS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs
VIH
HIGH-level input voltage
0.8VDDD
−
VDDD + 0.5
V
VIL
LOW-level input voltage
−0.5
−
0.2VDDD
V
⎪ILI⎪
input leakage current
−
−
10
μA
Ci
input capacitance
−
−
10
pF
Digital outputs
VOH
HIGH-level output voltage
IOH = −2 mA
0.85VDDD
−
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
−
0.4
V
Three-level inputs: pins MP2 and MP4
VIH
HIGH-level input voltage
0.9VDDD
−
VDDD + 0.5
V
VIM
MIDDLE-level input voltage
0.4VDDD
−
0.6VDDD
V
VIL
LOW-level input voltage
−0.5
−
0.1VDDD
V
0.45VDDA
0.5VDDA
0.55VDDA
V
−
24
−
kΩ
−
9.8
−
kΩ
−
20
−
pF
0.45VDDA
0.5VDDA
0.55VDDA
V
−
28
−
kΩ
−
0.13
3.0
Ω
(THD + N)/S < 0.1 −
%; RL = 5 kΩ
0.22
−
mA
3
−
−
kΩ
−
−
200
pF
Analog-to-digital converter
Vref(A)
reference voltage
Ro(refA)
output resistance on pin Vref(A)
Ri
input resistance
Ci
input capacitance
refererred to
VSSA(ADC)
fi = 1 kHz
Digital-to-analog converter
Vref(D)
reference voltage
Ro(refD)
output resistance on pin Vref(D)
Ro
output resistance of DAC
Io(max)
maximum output current
RL
load resistance
CL
load capacitance
refererred to
VSSA(DAC)
note 2
Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.
2. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in
order to prevent oscillations in the output operational amplifier.
2001 Jun 29
17
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
AC CHARACTERISTICS
VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Analog-to-digital converter
Vi(rms)
input voltage (RMS value)
notes 1 and 2
1.0
−
V
ΔVi
unbalance between channels
0.1
−
dB
(THD + N)/S
total harmonic distortion-plus-noise to signal ratio at 0 dB
−85
−80
dB
−35
−30
dB
at −60 dB; A-weighted
S/N
signal-to-noise ratio
αcs
channel separation
PSRR
power supply rejection ratio
95
−
dB
100
−
dB
fripple = 1 kHz;
Vripple = 300 mV (p-p)
30
−
dB
notes 3 and 4
900
−
mV
0.1
−
dB
Vi = 0 V; A-weighted
Digital-to-analog converter
Vo(rms)
output voltage (RMS value)
ΔVo
unbalance between channels
(THD + N)/S
total harmonic distortion-plus-noise to signal ratio at 0 dB
S/N
signal-to-noise ratio
αcs
channel separation
PSRR
power supply rejection ratio
−90
−85
dB
at −60 dB; A-weighted
−37
−
dB
code = 0; A-weighted
100
−
dB
100
−
dB
50
−
dB
fripple = 1 kHz;
Vripple = 300 mV (p-p)
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC is inversely proportional with the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply voltage.
2001 Jun 29
18
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
TIMING
VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages referenced to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock input (see Fig.7)
Tsys
system clock cycle time
tCWH
system clock HIGH time
tCWL
system clock LOW time
fsys = 256fs
78
88
−
ns
fsys = 384fs
52
59
−
ns
fsys = 512fs
39
44
−
ns
fsys < 19.2 MHz
0.30Tsys −
0.70Tsys ns
fsys ≥ 19.2 MHz
0.40Tsys −
0.60Tsys ns
fsys < 19.2 MHz
0.30Tsys −
0.70Tsys ns
fsys ≥ 19.2 MHz
0.40Tsys −
0.60Tsys ns
−
−
64fs
Hz
−
−
ns
−
−
ns
Serial interface input/output data (see Fig.8)
fBCK
bit clock frequency
Tcy(BCK)
bit clock cycle time
tBCKH
bit clock HIGH time
tBCKL
bit clock LOW time
100
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tsu(WS)
word select set-up time
20
−
−
ns
th(WS)
word select hold time
10
−
−
ns
tsu(DATAI)
data input set-up time
20
−
−
ns
th(DATAI)
data input hold time
0
−
−
ns
th(DATAO)
data output hold time
td(DATAO−BCK) data output to bit clock delay
td(DATAO−WS)
data output to word select delay
Tcy(s) = cycle time of
sample frequency
T cy(s)
-----------64
100
0
−
−
ns
from BCK falling edge −
−
80
ns
−
−
80
ns
from WS edge for
MSB-justified format
L3 interface input (see Figs 4 and 5)
Tcy(CLK)L3
L3CLOCK cycle time
500
−
−
ns
tCLK(L3)H
L3CLOCK HIGH time
250
−
−
ns
tCLK(L3)L
L3CLOCK LOW time
250
−
−
ns
tsu(L3)A
L3MODE set-up time for address mode
190
−
−
ns
th(L3)A
L3MODE hold time for address mode
190
−
−
ns
tsu(L3)D
L3MODE set-up time for data transfer
mode
190
−
−
ns
th(L3)D
L3MODE hold time for data transfer mode
190
−
−
ns
tstp(L3)
L3MODE stop time
190
−
−
ns
tsu(L3)DA
L3DATA set-up time in data transfer and
address mode
190
−
−
ns
th(L3)DA
L3DATA hold time in data transfer and
address mode
30
−
−
ns
2001 Jun 29
19
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
tCWH
handbook, full pagewidth
tCWL
MGL443
Tsys
Fig.7 System clock timing.
handbook, full pagewidth
WS
tr
t BCKH
t d(DATAO-BCK)
t h(WS)
tf
t su(WS)
BCK
t BCKL
Tcy(BCK)
t d(DATAO-WS)
t h(DATAO)
DATAO
t su(DATAI)
t h(DATAI)
DATAI
MGS756
Fig.8 Serial interface timing.
2001 Jun 29
20
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
APPLICATION INFORMATION
VDD1
BLM32A07
R21
1Ω
L2
VDD2
BLM32A07
C12
100 μF
(16 V)
ground
C2
C11
100 μF
(16 V)
R24
system
clock
SYSCLK
47 Ω
DATAO
BCK
WS
DATAI
MP1
overload
flag
left
input
VDD2
100 μF
(16 V)
C21
C25
C29
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
VSSD
2
1
R28
1Ω
C9
10 Ω
100 μF
(16 V)
VSSA(ADC) VDDA(ADC)
R30
handbook, full pagewidth
VDD1
L1
3V
VADCN
VADCP
6
7
VDDD
10
11
12
18
4
C22
100 nF
(63 V)
16
17
C1
VINL
9
UDA1344TS
3
24
right
input
C6
VOUTR
X2
left
output
R22
10 kΩ
C8
47 μF
(16 V)
VINR 5
R23
100 Ω
R26
100 Ω
X3
right
output
R27
10 kΩ
47 μF
(16 V)
MP2
MP3
MP4
13
28
14
25
27
23
22
VDDO
VSSA(DAC)
C26
C27
100 nF
(63 V)
100 nF
(63 V)
C7
C10
100 μF
(16 V)
R25
1Ω
100 μF
(16 V)
VDD1
Fig.9 Application diagram.
21
Vref(D)
C23
100 nF
(63 V)
15
VSSO
2001 Jun 29
C5
VOUTL
47 μF
(16 V)
47 μF
(16 V)
X5
C3
47 μF
(16 V)
19
26
X4
Vref(A)
C4
47 μF
(16 V)
MGL444
VDDA(DAC)
R29
1Ω
VDD1
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
SOT341-1
E
A
X
c
HE
y
v M A
Z
28
15
Q
A2
pin 1 index
A
(A 3)
A1
θ
Lp
L
1
14
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.1
0.7
8
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT341-1
2001 Jun 29
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
22
o
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2001 Jun 29
23
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2001 Jun 29
24
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2001 Jun 29
25
NXP Semiconductors
Product specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2001 Jun 29
26
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/05/pp27
Date of release: 2001 Jun 29
Document order number:
9397 750 08498
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