Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
UDA1361TS
96 kHz sampling 24-bit stereo audio
ADC
Product specification
Supersedes data of 2001 Jan 17
2002 Nov 25
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio
ADC
UDA1361TS
FEATURES
General
• Low power consumption
• 256, 384, 512 and 768fs system clock
• 2.4 to 3.6 V power supply
• Supports sampling frequency of 5 to 110 kHz
• Small package size (SSOP16)
• Integrated high-pass filter to cancel DC offset
GENERAL DESCRIPTION
• Power-down mode
The UDA1361TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use in
low-voltage low-power portable digital audio equipment
which incorporates recording functions.
• Supports 2 V (RMS) input signals
• Easy application
• Master or slave operation.
Multiple format output interface
• I2S-bus and MSB-justified format compatible
The UDA1361TS supports the I2S-bus data format and the
MSB-justified data format with word lengths of up to
24 bits.
• Up to 24 significant bits serial output.
Advanced audio configuration
• Stereo single-ended input configuration
• High linearity, dynamic range and low distortion.
ORDERING INFORMATION
TYPE
NUMBER
UDA1361TS
2002 Nov 25
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
VDDD
digital supply voltage
IDDA
analog supply current
IDDD
Tamb
digital supply current
2.4
3.0
3.6
V
2.4
3.0
3.6
V
operating mode
−
10.5
−
mA
Power-down mode
−
0.5
−
mA
operating mode
−
3.5
−
mA
Power-down mode
−
0.45
−
mA
−40
−
+85
°C
at 0 dB(FS) equivalent
−
1.1
−
V
at −1 dB(FS) signal output
−
1.0
−
V
fs = 48 kHz
fs = 48 kHz
ambient temperature
Analog
Vi(rms)
(THD + N)/S
input voltage (RMS value)
total harmonic distortion-plus-noise fs = 48 kHz
to signal ratio
at −1 dB
−
−88
−83
dB
−
−40
−34
dB
at −1 dB
−
−85
−80
dB
at −60 dB; A-weighted
−
−40
−37
dB
−
100
−
dB
at −60 dB; A-weighted
fs = 96 kHz
S/N
signal-to-noise ratio
Vi = 0 V; A-weighted
fs = 48 kHz
fs = 96 kHz
αcs
2002 Nov 25
channel separation
3
−
100
−
dB
−
100
−
dB
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
BLOCK DIAGRAM
handbook, full pagewidth
VDDA
VSSA
VRP
VRN
Vref
16
15
5
4
2
SYSCLK
8
9
10
UDA1361TS
VINL
ADC
ΣΔ
14
DATAO
BCK
WS
VSSD
1
DECIMATION
FILTER
VINR
VDDD
CLOCK
CONTROL
7
MSSEL
PWON
3
ADC
ΣΔ
13
11
DIGITAL
INTERFACE
12
6
DC-CANCELLATION
FILTER
SFOR
MGT451
Fig.1 Block diagram.
PINNING
SYMBOL
PIN
DESCRIPTION
VINL
1
left channel input
Vref
2
reference voltage
VINR
3
right channel input
VRN
4
VRP
handbook, halfpage
VINL 1
16 VDDA
negative reference voltage
Vref 2
15 VSSA
5
positive reference voltage
VINR 3
SFOR
6
data format selection input
PWON
7
power control input
SYSCLK
8
system clock 256, 384, 512 or 768fs
VDDD
9
digital supply voltage
VSSD
10
digital ground
BCK
11
bit clock input/output
WS
12
word select input/output
DATAO
13
data output
MSSEL
14
master/slave select
VSSA
15
analog ground
VDDA
16
analog supply voltage
2002 Nov 25
14 MSSEL
VRN 4
13 DATAO
UDA1361TS
VRP 5
12 WS
SFOR 6
11 BCK
10 VSSD
PWON 7
SYSCLK 8
9
VDDD
MGT452
Fig.2 Pin configuration.
4
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
FUNCTIONAL DESCRIPTION
UDA1361TS
Table 1
Application modes using input gain stage
System clock
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
(RMS)
Present
0 dB
2V
Present
0 dB
1V
Absent
0 dB
1V
Absent
6 dB
0.5 V
RESISTOR
(12 kΩ)
The UDA1361TS accommodates master and slave
modes. The system devices must provide the system clock
regardless of master or slave mode. In the master mode a
system clock frequency of 256fs is required. In the slave
mode a system frequency of 256, 384, 512 or 768fs is
automatically detected (for a system clock of 768fs the
sampling frequency must be limited to 55 kHz). The
system clock must be locked in frequency to the digital
interface input signals.
Multiple format output interface
Input level
The serial interface provides the following data output
formats in both master and slave modes
(see Figs 3, 4 and 5):
The overall system gain is proportional to VDDA, or more
accurately the potential difference between the reference
voltages VVRP and VVRN. The −1 dB input level at which
THD + N/S is specified corresponds to −1 dB(FS) digital
output (relative to the full-scale swing). With an input gain
switch, the input level can be calculated as follows:
• I2S-bus with data word length of up to 24 bits
• MSB-justified serial format with data word length of up to
24 bits.
V VRP – V VRN
at 0 dB gain: V i ( – 1 dB ) = --------------------------------- = V (RMS)
3
The master mode drives pins WS (word select; 1fs) and
BCK (bit clock; 64fs). WS and BCK are received in slave
mode.
V VRP – V VRN
at 6 dB gain: V i ( – 1 dB ) = --------------------------------- = V (RMS)
2×3
Table 2
Master/slave select
MSSEL
In applications where a 2 V (RMS) input signal is used, a
12 kΩ resistor must be connected in series with the input
of the ADC. This forms a voltage divider together with the
internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC.
Using this application for a 2 V (RMS) input signal, the gain
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application the gain switch
must be set to 6 dB.
Table 3
L
slave mode
H
master mode
M
(reserved for digital test)
Select data format
SFOR
An overview of the maximum input voltage allowed against
the presence of an external resistor and the setting of the
gain switch is given in Table 1. The power supply voltage
is assumed to be 3 V.
MASTER/SLAVE
SELECT
DATA FORMAT
L
I2S-bus
H
MSB-justified data format
M
(reserved for analog test)
data format
Decimation filter
The decimation from 64fs is performed in two stages. The
first stage realizes a 4th-order sinx/x characteristic. This
filter decreases the sample rate by 8.
The second stage, a FIR filter, consists of 3 half-band
filters, each decimating by a factor of 2.
2002 Nov 25
5
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
Table 4
Decimation filter characteristic
ITEM
CONDITION
Pass-band ripple
0 to 0.45fs
Mute
On recovery from Power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
VALUE (dB)
±0.01
Pass-band droop 0.45fs
−0.2
Stop band
>0.55 fs
−70
Dynamic range
0 to 0.45 fs
>135
12288
t = ---------------- , t = 256 ms when fs = 48 kHz.
fs
DC cancellation filter
Power-down mode/input voltage control
A IIR high-pass filter is provided to remove unwanted
DC components. The filter characteristics are given in
Table 5.
Table 5
The PWON pin can control the power saving together with
the optional gain switch for 2 or 1 V (RMS) input.
The UDA1361TS supports 2 V (RMS) input using a series
resistor of 12 kΩ. For the definition of the pin settings for
1 or 2 V (RMS) mode, it is assumed that this resistor is
present as a default component.
DC cancellation filter characteristic
ITEM
UDA1361TS
CONDITION
VALUE (dB)
Pass-band ripple
−
none
Pass-band gain
−
0
Droop
at 0.00045fs
−0.031
Attenuation
at DC
at 0.00000036fs
>40
Dynamic range
0 to 0.45fs
Table 6
Power-down/input voltage control
PWON
>135
POWER-DOWN OR GAIN
L
Power-down mode
M
0 dB gain
H
6 dB gain
Serial interface formats
LEFT
handbook, full pagewidth
WS
1
2
3
RIGHT
≥8
1
2
LSB
MSB
3
≥8
BCK
DATA
MSB
B2
B2
LSB
MSB
INPUT FORMAT I2S-BUS
WS
RIGHT
LEFT
1
2
3
≥8
1
2
3
≥8
BCK
DATA
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
Fig.3 Serial interface formats.
2002 Nov 25
6
LSB
MSB
B2
MGT453
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
4.0
V
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
VDD
supply voltage
Txtal(max)
note 1
HBM; note 2
−3000 +3000 V
MM; note 2
−300
+300
V
Notes
1. All supply connections must be made to the same power supply.
2. ESD behaviour is tested in accordance with JEDEC II standard:
a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75 μH series inductor.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
130
K/W
thermal resistance from junction to ambient in free air
DC CHARACTERISTICS
VDDD = VDDA = 3 V; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
note 1
2.4
3.0
3.6
V
VDDD
digital supply voltage
note 1
2.4
3.0
3.6
V
IDDA
analog supply current
fs = 48 kHz
operating mode
−
Power-down mode −
10.5
−
mA
0.5
−
mA
fs = 96 kHz
operating mode
−
Power-down mode −
IDDD
digital supply current
10.5
−
mA
0.5
−
mA
fs = 48 kHz
operating mode
−
Power-down mode −
3.5
−
mA
0.45
−
mA
fs = 96 kHz
operating mode
−
Power-down mode −
2002 Nov 25
7
7.0
−
mA
0.65
−
mA
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
SYMBOL
PARAMETER
UDA1361TS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pin (SYSCLK)
VIH
HIGH-level input voltage
2.0
−
5.5
V
VIL
LOW-level input voltage
−0.5
−
+0.8
V
|ILI|
input leakage current
−
−
1
μA
Ci
input capacitance
−
−
10
pF
Digital 3-level input pins (PWON, SFOR, MSSEL)
VIH
HIGH-level input voltage
0.9VDD
−
VDD + 0.5
V
VIM
MIDDLE-level input
voltage
0.4VDD
−
0.6VDD
V
VIL
LOW-level input voltage
−0.5
−
+0.4
V
Digital input/output pins (BCK, WS)
VIH
HIGH-level input voltage
2.0
−
5.5
V
VIL
LOW-level input voltage
−0.5
−
+0.8
V
|ILI|
input leakage current
−
−
1
μA
Ci
input capacitance
−
−
10
pF
VOH
HIGH-level output voltage IOH = −2 mA
0.85VDDD
−
−
V
VOL
LOW-level output voltage
−
−
0.4
V
IOL = 2 mA
Digital output pin (DATAO)
VOH
HIGH-level output voltage IOH = −2 mA
0.85VDDD
−
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
−
0.4
V
Vref
reference voltage
with respect to VSSA
0.45VDDA
0.5VDDA
0.55VDDA
V
Ri
input resistance
−
12
−
kΩ
Ci
input capacitance
−
20
−
pF
Analog
Note
1. All power supply connections must be connected to the same external power supply unit.
2002 Nov 25
8
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
AC CHARACTERISTICS (ANALOG)
VDDD = VDDA = 3 V; fi = 1 kHz; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise
specified.
SYMBOL
Vi(rms)
PARAMETER
input voltage (RMS value)
⎪ΔVi⎪
unbalance between channels
(THD + N)/S
total harmonic
distortion-plus-noise to signal
ratio
CONDITIONS
TYP.
MAX.
UNIT
at 0 dB(FS) equivalent
1.1
−
V
at −1 dB(FS) signal output
1.0
−
V
<0.1
0.4
dB
at −1 dB
−88
−83
dB
at −60 dB; A-weighted
−40
−34
dB
at −1 dB
−85
−80
dB
at −60 dB; A-weighted
−40
−37
dB
fs = 48 kHz
100
−
dB
fs = 96 kHz
100
−
dB
fs = 48 kHz
fs = 96 kHz
S/N
signal-to-noise ratio
αcs
channel separation
PSRR
power supply rejection ratio
2002 Nov 25
Vi = 0 V; A-weighted
fripple = 1 kHz; Vripple = 30 mV (p-p)
9
100
−
dB
30
−
dB
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = 2.4 to 3.6 V; Tamb = −40 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing
Tsys
system clock cycle
fsys = 256fs
35
88
780
ns
fsys = 384fs
23
59
520
ns
fsys = 512fs
17
44
390
ns
fsys = 768fs
17
30
260
ns
tCWL
LOW-level system clock pulse width
0.40Tsys −
0.60Tsys ns
tCWH
HIGH-level system clock pulse width
0.40Tsys −
0.60Tsys ns
Serial data timing; see Figs 4 and 5
Tcy(CLK)(bit) bit clock period
64fs
1
f cy = -------- ; master mode
T cy
1
f cy = -------- ; slave mode
T cy
64fs
64fs
Hz
−
−
64fs
Hz
tBCKH
bit clock HIGH time
50
−
−
ns
tBCKL
bit clock LOW time
50
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
−
−
40
ns
−
−
40
ns
td(o)(D)(BCK) data output delay time
(from BCK falling edge)
td(o)(D)(WS)
data output delay time
(from WS edge)
th(o)(D)
data output hold time
0
−
−
ns
tr(WS)
word select rise time
−
−
20
ns
tf(WS)
word select fall time
−
−
20
ns
fWS
word select period
1
1
1
fs
td(WS)(BCK)
word select delay from BCK
master mode
−40
−
+40
ns
tsu(WS)
word select set-up time
slave mode
20
−
−
ns
th(WS)
word select hold time
slave mode
10
−
−
ns
2002 Nov 25
MSB-justified format
10
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
handbook, full pagewidth
WS
tr
t BCKH
t d(WS)(BCK)
tf
BCK
t BCKL
t d(o)(D)(BCK)
t h(o)(D)
Tcy(CLK)(bit)
DATAO
MGT454
Fig.4 Serial interface master mode timing.
handbook, full pagewidth
WS
tr
t BCKH
t h(WS)
tf
t su(WS)
BCK
t BCKL
Tcy(CLK)(bit)
t d(o)(D)(WS)
t d(o)(D)(BCK)
t h(o)(D)
DATAO
MGT455
Fig.5 Serial interface slave mode timing.
2002 Nov 25
11
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
APPLICATION INFORMATION
The application information illustrated in Fig.6, is an optimum application environment. Simplification is possible at the
cost of some performance degradation.
handbook, full pagewidth
C11
X5
1 nF
(63 V)
1
47 μF
(16 V)
C6
47 μF
(16 V)
2
C3
47 μF
(16 V)
VDDA
C10
100 nF
(63 V)
15
C7
100 nF
(63 V)
VDDD
R7
47 kΩ
C12
X6
1 nF
(63 V)
X3-2
47 μF
(16 V)
R1
220 Ω
C4
47 μF
(16 V)
X3-1
14
3
R6
47 kΩ
4
VDDA
R3
1Ω
16
C8
100 nF
(63 V)
X3-3
13
X1-1
X1-2
UDA1361TS
X1-3
X1-4
5
12
X1-5
X1-6
VDDD
X4-1
X2-1
X4-3
11
X1-9
R13
47 kΩ
X1-10
R4
47 kΩ
7
X2-2
X2-3
X1-8
6
X4-2
VDDD
X1-7
R12
47 kΩ
10
C5
47 μF
(16 V)
R5
47 kΩ
SYSCLK
8
C9
100 nF
(63 V)
9
R10
47 Ω
R2
1Ω
VDDD
L1 BLM32A07
VD
R11
47 Ω
L2 BLM32A07
C1
100 μF
MGU297
(16 V)
VDDD
VDDA
C2
100 μF
(16 V)
The value of capacitors C11 and C12 can be reduced. Note that changing their value will change the cut-off frequency determined by the capacitor
value and the12 kΩ input resistance of the ADC.
Fig.6 Application diagram.
2002 Nov 25
12
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
D
SOT369-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0.00
1.4
1.2
0.25
0.32
0.20
0.25
0.13
5.3
5.1
4.5
4.3
0.65
6.6
6.2
1
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT369-1
2002 Nov 25
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-152
13
o
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2002 Nov 25
UDA1361TS
14
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your NXP Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 25
15
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2002 Nov 25
16
NXP Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2002 Nov 25
UDA1361TS
17
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp18
Date of release: 2002 Nov 25
Document order number:
9397 750 10479
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