Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
UDA1380
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
Supersedes data of 2003 Apr 04
2004 Apr 22
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
CONTENTS
1
FEATURES
1.1
1.2
1.3
1.4
1.5
General
Multiple format data input interface
Multiple format data output interface
ADC front-end features
DAC features
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
Clock modes
ADC analog front-end
Decimation filter (ADC)
Interpolation filter (DAC)
Noise shaper
FSDAC
Headphone driver
Digital and analog mixers (DAC)
Application modes
Power-on reset
Power-down requirements
Plop prevention
Digital audio data input and output
9
L3-BUS INTERFACE DESCRIPTION
9.1
9.2
9.3
9.4
9.5
9.6
Introduction
Device addressing
Slave address
Register addressing
Data write mode
Data read mode
10
I2C-BUS INTERFACE DESCRIPTION
10.1
10.2
10.3
Addressing
WRITE cycle
READ cycle
11
REGISTER MAPPING
2004 Apr 22
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.17
Evaluation modes and clock settings
I2S-bus input and output settings
Power control settings
Analog mixer settings
Headphone amplifier settings
Master volume control
Mixer volume control
Mode, bass boost and treble
Master mute, channel de-emphasis and mute
Mixer, silence detector and oversampling
settings
Decimator volume control
PGA settings and mute
ADC settings
AGC settings
Restore L3 default values (software reset)
Headphone driver and interpolation filter
(read-out)
Decimator read-out
12
LIMITING VALUES
13
HANDLING
14
THERMAL CHARACTERISTICS
15
QUALITY SPECIFICATION
16
DC CHARACTERISTICS
17
AC CHARACTERISTICS
18
TIMING
19
APPLICATION INFORMATION
20
PACKAGE OUTLINES
21
SOLDERING
21.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
11.11
11.12
11.13
11.14
11.15
11.16
21.2
21.3
21.4
21.5
2
22
DATA SHEET STATUS
23
DISCLAIMERS
24
TRADEMARKS
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
1
UDA1380
FEATURES
1.1
General
• 2.4 to 3.6 V power supply
• 5 V tolerant digital inputs (at 2.7 to 3.6 V power supply)
• 24-bit data path for Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
• Selectable control via L3-bus microcontroller interface
or I2C-bus interface; choice of 2 device addresses in
L3-bus and I2C-bus mode
1.2
Multiple format data input interface
• Slave BCK and WS signals
Remark: This device does not have a static mode.
• Supports sample frequencies from 8 to 55 kHz for the
ADC part, and 8 to 100 kHz for the DAC part. The ADC
does not support DVD audio (96 kHz audio), only
Mini-Disc (MD), Compact-Disc (CD) and Moving Picture
Experts Group Layer-3 Audio (MP3). For playback
8 to 100 kHz is specified. DVD playback is supported
• I2S-bus format
• Power management unit:
• Select option for digital output interface: either the
decimator output (ADC signal) or the output signal of the
digital mixer which is in the interpolator DSP
• MSB-justified format compatible
• LSB-justified format compatible.
1.3
– Separate power control for ADC, Automatic Volume
Control (AVC), DAC, Phase Locked Loop (PLL) and
headphone driver
Multiple format data output interface
• Selectable master or slave BCK and WS signals for
digital ADC output
– Analog blocks like ADC and Programmable Gain
Amplifier (PGA) have a block to power-down the bias
circuits
Remark: SYSCLK must be applied in WSPLL mode and
master mode
• I2S-bus format
– When ADC and/or DAC are powered-down, the
clocks to these blocks are also stopped to save
power.
• MSB-justified format compatible
• LSB-justified format compatible.
Remark: By default, when the IC is powered-up, the
complete chip will be in the Power-down mode.
1.4
ADC front-end features
• ADC part and DAC part can run at different frequencies,
either system clock or Word Select PLL (WSPLL)
• ADC plus decimator can run at either WSPLL,
regenerating the clock from WSI signal, or on SYSCLK
• ADC and PGA plus integrated high-pass filter to cancel
DC offset
• Stereo line input with PGA: gain range from 0 to 24 dB
in steps of 3 dB
• The decimation filter is equipped with a digital Automatic
Gain Control (AGC)
• LNA with 29 dB fixed gain for mono microphone input,
including VGA with gain from 0 to 30 dB in steps of 2 dB
• Mono microphone input with Low Noise Amplifier (LNA)
of 29 dB fixed gain and Variable Gain Amplifier (VGA)
from 0 to 30 dB in steps of 2 dB
• Digital left and right independent volume control and
mute from +24 to −63.5 dB in steps of 0.5 dB.
• Integrated digital filter plus DAC
• Separate single-ended line output and one stereo
headphone output, capable of driving a 16 Ω load. The
headphone driver has a built-in short-circuit protection
with status bits which can be read out from the
L3-bus or I2C-bus interface
• Digital silence detection in the interpolator (playback)
with read-out status via L3-bus or I2C-bus interface
• Easy application.
2004 Apr 22
3
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
1.5
UDA1380
DAC features
The DAC part is equipped with a stereo line output and a
headphone driver output. The headphone driver is capable
of driving a 16 Ω load. The headphone driver is also
capable of driving a headphone without the need for
external DC decoupling capacitors, since the headphone
can be connected to a pin VREF(HP) on the chip.
• DAC plus interpolator can run at either WSPLL
(regenerating the clock from WSI) or at SYSCLK
• Separate digital logarithmic volume control for left and
right channels via L3-bus or I2C-bus from 0 to −78 dB in
steps of 0.25 dB
In addition, there is a built-in short-circuit protection for the
headphone driver output which, in case of short-circuit,
limits the current through the operational amplifiers and
signals the event via its L3-bus or I2C-bus register.
• Digital tone control, bass boost and treble via L3-bus or
I2C-bus interface
• Digital de-emphasis for sample frequencies of:
32, 44.1, 48 and 96 kHz via L3-bus or I2C-bus interface
The UDA1380 also supports an application mode in which
the coder-decoder itself is not running, but an analog
signal, for instance coming from an FM tuner, can be
controlled in gain and applied to the output via the
headphone driver and line outputs.
• Cosine roll-off soft mute function
• Output signal polarity control via L3-bus or I2C-bus
interface
• Digital mixer for mixing ADC output signal and digital
serial input signal, if they run at the same sampling
frequency.
2
The UDA1380 supports the I2S-bus data format with word
lengths of up to 24 bits, the MSB-justified data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 18, 20 or 24 bits
(LSB-justified 24 bits is only supported for the output
interface).
APPLICATIONS
This audio coder-decoder is suitable for home and
portable applications like MD, CD and MP3 players.
3
The UDA1380 has sound processing features in playback
mode, de-emphasis, volume, mute, bass boost and treble
which can be controlled by the L3-bus or I2C-bus interface.
GENERAL DESCRIPTION
The UDA1380 is a stereo audio coder-decoder, available
in TSSOP32 (UDA1380TT) and HVQFN32 (UDA1380HN)
packages. All functions and features are identical for both
package versions. The term ‘UDA1380’ in this document
refers to both UDA1380TT and UDA1380HN, unless
particularly specified.
The front-end of the UDA1380 is equipped with a stereo
line input, which has a PGA control, and a mono
microphone input with an LNA and a VGA. The digital
decimation filter is equipped with an AGC which can be
used in case of voice-recording.
2004 Apr 22
4
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
4 QUICK REFERENCE DATA
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA(AD)
ADC analog supply voltage
VDDA(DA)
DAC analog supply voltage
VDDA(HP)
headphone analog supply
voltage
VDDD
IDDA(AD)
2.4
IDDD
IDD(tot)
Tamb
2004 Apr 22
V
2.4
3.0
3.6
V
3.0
3.6
V
digital supply voltage
2.4
3.0
3.6
V
ADC analog supply current one ADC and microphone amplifier
enabled; fs = 48 kHz
−
4.5
−
mA
−
7.0
−
mA
all ADCs and PGAs power-down, but −
AVC activated; fs = 48 kHz
3.3
−
mA
−
1.0
−
μA
−
3.4
−
mA
Power-down mode; fs = 48 kHz
−
0.1
−
μA
headphone analog supply
current
no signal applied (quiescent current)
−
0.9
−
mA
Power-down mode
−
0.1
−
μA
digital supply current
operating mode; fs = 48 kHz
−
10.0
−
mA
all ADCs, PGAs and LNA
power-down; fs = 48 kHz
IDDA(HP)
3.6
2.4
note 1
two ADCs and PGA enabled;
fs = 48 kHz
IDDA(DA)
3.0
DAC analog supply current operating mode; fs = 48 kHz
total supply current
playback mode; fs = 48 kHz
−
5.0
−
mA
record mode; fs = 48 kHz
−
6.0
−
mA
Power-down mode; fs = 48 kHz
−
1.0
−
μA
playback mode (without headphone); −
fs = 48 kHz
8
−
mA
playback mode (with headphone); no −
signal; fs = 48 kHz
9
−
mA
record mode (audio); fs = 48 kHz
−
13
−
mA
record mode (speech); fs = 48 kHz
−
10
−
mA
record mode (audio and speech);
fs = 48 kHz
−
13
−
mA
fully operating; fs = 48 kHz
−
23
−
mA
signal mix-in operating, using
FSDAC, AVC (with headphone); no
signal; fs = 48 kHz
−
12
−
mA
Power-down mode; fs = 48 kHz
−
2
−
μA
−40
−
+85
°C
ambient temperature
5
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
SYMBOL
UDA1380
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital converter (supply voltage 3.0 V)
Do
digital output level
(THD+N)/S48
at −1 dBFS
total harmonic distortionplus-noise to signal ratio at at −60 dBFS; A-weighted
fs = 48 kHz
S/N48
signal-to-noise ratio at
fs = 48 kHz
αcs
channel separation
at 0 dB setting; Vi(rms) = 1.0 V
Vi = 0 V; A-weighted
−1.5
−1
−0.5
dBFS
−
−85
−80
dB
−
−37
−32
dB
92
97
−
dB
−
100
−
dB
LNA input plus analog-to-digital converter (supply voltage 3.0 V)
Vi(rms)
input voltage (RMS value)
at 0 dBFS digital output; 2.2 kΩ
source impedance
−
−
35
mV
(THD+N)/S48
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
at 0 dB
−
−74
−
dB
at −60 dB; A-weighted
−
−25
−
dB
S/N48
signal-to-noise ratio at
fs = 48 kHz
Vi = 0 V; A-weighted
−
85
−
dB
αcs
channel separation
−
70
−
dB
Digital-to-analog converter (supply voltage 3.0 V)
Vo(rms)
output voltage
(RMS value)
at 0 dBFS digital input; note 2
−
0.9
−
V
(THD+N)/S48
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
at 0 dB
−
−85
−80
dB
at −60 dB; A-weighted
−
−40
−35
dB
at 0 dB
−
−80
−75
dB
at −60 dB; A-weighted
−
−37
−32
dB
(THD+N)/S96
total harmonic
distortion-plus-noise to
signal ratio at fs = 96 kHz
S/N48
signal-to-noise ratio at
fs = 48 kHz
code = 0; A-weighted
95
100
−
dB
S/N96
signal-to-noise ratio at
fs = 96 kHz
code = 0; A-weighted
92
97
−
dB
αcs
channel separation
−
90
−
dB
AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V)
Vi(rms)
input voltage (RMS value)
(THD+N)/S48
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
2004 Apr 22
−
150
−
mV
at 0 dB
−
−80
−
dB
at −60 dB; A-weighted
−
−28
−
dB
6
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
SYMBOL
S/N48
PARAMETER
signal-to-noise ratio at
fs = 48 kHz
UDA1380
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vi = 0 V; A-weighted
−
87
−
dB
Headphone driver (supply voltage 3.0 V)
Po(rms)
output power (RMS value)
at 0 dBFS digital input; RL = 16 Ω
30
35
40
mW
(THD+N)/S48
total harmonic
distortion-plus-noise to
signal ratio at fs = 48 kHz
at 0 dB; RL = 16 Ω; note 1
−
−60
−52
dB
at 0 dB; RL = 5 kΩ
−
−82
−77
dB
at −60 dB; A-weighted
−
−33
−27
dB
S/N48
signal-to-noise ratio at
fs = 48 kHz
code = 0; A-weighted
87
93
−
dB
αcs
channel separation
RL = 16 Ω using pin VREF(HP); no DC
decoupling capacitors; note 3
55
60
−
dB
RL = 16 Ω single-ended application
with DC decoupling capacitors
(100 μF typical)
63
68
−
dB
RL = 32 Ω single-ended application
with DC decoupling capacitors
(100 μF typical)
69
74
−
dB
playback mode (without headphone)
−
24
−
mW
playback mode (with headphone)
−
27
−
mW
record mode (audio)
−
39
−
mW
record mode (speech)
−
30
−
mW
record mode (audio and speech)
−
40
−
mW
full operation
−
69
−
mW
Power-down mode
−
6
−
μW
Power consumption (supply voltage 3.0 V; fs = 48 kHz)
Ptot
total power dissipation
Notes
1. When the supply voltages are below 2.7 V and the headphone load impedance is 16 Ω, it is recommended to limit
the DAC and the headphone output to less than -2dB; otherwise clipping may occur.
2. The output voltage of the DAC is proportional to the DAC power supply voltage.
3. Channel separation performance is measured at the IC pin.
5
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1380TT
TSSOP32
plastic thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm
SOT487-1
UDA1380HN
HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617-1
2004 Apr 22
7
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
6
UDA1380
BLOCK DIAGRAM
VDDA(AD)
handbook, full pagewidth
30 (26)
32 (28)
VINL
VADCP
VSSA(AD)
VADCN
4 (32)
2 (30)
31 (27)
PGA
3 (31)
VINM
VREF
29 (25)
SDC
SDC
VDDD
VDDA(DA)
26 (22)
6 (2)
1 (29)
VINR
PGA
+29 dB
MIC AMP
SDC
n.c.
ADC
UDA1380TT
(UDA1380HN)
ADC
5 (1)
RESET
DECIMATION FILTER
AGC
DC-CANCELLATION FILTER
13 (9)
SYSCLK
DATAO
BCKO
WSO
BCKI
WSI
DATAI
9 (5)
7 (3)
8 (4)
17 (13)
DATA OUTPUT
INTERFACE
10 (6)
11 (7)
12 (8)
L3 or I2C-BUS
INTERFACE
DATA INPUT
INTERFACE
16 (12)
18 (14)
19 (15)
15 (11)
DSP FEATURES
L3CLOCK/SCL
L3MODE
L3DATA/SDA
SEL_L3_IIC
RTCB
INTERPOLATION FILTER
WSPLL
NOISE SHAPER
FSDAC
ANA VC
VOUTL
FSDAC
ANA VC
25 (21)
27 (23)
HEADPHONE
DRIVER
23 (19)
VOUTLHP
24 (20)
22 (18)
20 (16)
21 (17)
28 (24)
14 (10)
VREF(HP)
VSSD
VOUTRHP
VSSA(DA)
VSSA(HP)
VDDA(HP)
Pin numbers for UDA1380HN in parentheses.
Fig.1 Block diagram.
2004 Apr 22
VOUTR
HEADPHONE
DRIVER
8
MGU526
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
7
UDA1380
PINNING
PIN
SYMBOL
VINR
TYPE
UDA1380TT
UDA1380HN
1
29
analog pad
DESCRIPTION
ADC input right, also connected
to the mixer input of the FSDAC
VADCN
2
30
analog pad
ADC reference voltage
VINM
3
31
analog pad
microphone input
VADCP
4
32
analog pad
ADC reference voltage
RESET
5
1
5 V tolerant digital input pad;
push-pull; TTL with hysteresis;
pull-down
pin RESET with pull-down, for
making Power-On Reset (POR)
VDDD
6
2
digital supply pad
digital supply voltage
BCKO
7
3
bit clock output
WSO
8
4
5 V tolerant digital bidirectional
pad; push-pull input; 3-state
output; 5 ns slew-rate control;
TTL with hysteresis
DATAO
9
5
output pad; push-pull; 5 ns
slew-rate control; CMOS
data output
BCKI
10
6
bit clock input
WSI
11
7
5 V tolerant digital input pad;
push-pull; TTL with hysteresis
word select output
word select input
DATAI
12
8
data input
SYSCLK
13
9
system clock 256fs, 384fs,
512fs or 768fs input
VSSD
14
10
digital ground pad
digital ground
RTCB
15
11
5 V tolerant digital input pad;
push-pull; TTL with hysteresis;
pull-down
test control input, to be connected
to digital ground in the application
L3MODE
16
12
5 V tolerant digital bidirectional
pad; push-pull input; 3-state
output; 5 ns slew-rate control;
TTL with hysteresis
L3-bus mode input or pin A1 for
I2C-bus slave address setting
L3CLOCK/SC
L
17
13
5 V tolerant digital input pad;
push-pull; TTL with hysteresis
L3-bus or I2C-bus clock input
L3DATA/SDA
18
14
I2C-bus pad; 400 kHz I2C-bus
specification
L3-bus or I2C-bus data input and
output
SEL_L3_IIC
19
15
5 V tolerant digital input pad;
push-pull; TTL with hysteresis
input channel select
VSSA(HP)
20
16
analog ground pad
headphone ground
VOUTRHP
21
17
analog pad
headphone output right
VREF(HP)
22
18
analog pad
headphone reference voltage
VOUTLHP
23
19
analog pad
headphone output left
VDDA(HP)
24
20
analog supply pad
headphone supply voltage
VOUTR
25
21
analog pad
DAC output right
VDDA(DA)
26
22
analog supply pad
DAC analog supply voltage
VOUTL
27
23
analog pad
DAC output left
2004 Apr 22
9
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
PIN
SYMBOL
TYPE
UDA1380TT
DESCRIPTION
UDA1380HN
26
analog ground pad
ADC analog ground
VINL
31
27
analog pad
ADC input left, also connected to
the mixer input of the FSDAC
VDDA(AD)
32
28
analog supply pad
ADC analog supply voltage
VINM
3
30 VSSA(AD)
VADCP
4
29 VREF
RESET
5
28 VSSA(DA)
VDDD
6
27 VOUTL
25 VOUTR
8
UDA1380TT
DATAO
9
24 VDDA(HP)
BCKI 10
23 VOUTLHP
WSI 11
22 VREF(HP)
DATAI 12
21 VOUTRHP
SYSCLK 13
20 VSSA(HP)
VSSD 14
19 SEL_L3_IIC
RTCB 15
18 L3DATA/SDA
1
24 VSSA(DA)
VDDD
2
23 VOUTL
BCKO
3
22 VDDA(DA)
WSO
4
DATAO
5
BCKI
6
19 VOUTLHP
WSI
7
18 VREF(HP)
DATAI
8
17 VOUTRHP
21 VOUTR
UDA1380HN
9
WSO
26 VDDA(DA)
7
RESET
SYSCLK
BCKO
terminal 1
index area
20 VDDA(HP)
VSSA(HP) 16
31 VINL
SEL_L3_IIC 15
2
L3DATA/SDA 14
VADCN
L3CLOCK/SCL 13
32 VDDA(AD)
L3MODE 12
1
RTCB 11
VINR
VSSD 10
handbook, halfpage
25 VREF
30
26 VSSA(AD)
VSSA(AD)
27 VINL
ADC and DAC reference voltage
28 VDDA(AD)
DAC analog ground
analog pad
29 VINR
analog ground pad
25
30 VADCN
24
29
31 VINM
28
32 VADCP
VSSA(DA)
VREF
mgw778
Transparent top view
17 L3CLOCK/SCL
L3MODE 16
MGU525
Fig.2 Pin configuration UDA1380TT.
2004 Apr 22
Fig.3 Pin configuration UDA1380HN.
10
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8
UDA1380
FUNCTIONAL DESCRIPTION
8.1
8.1.1
WSPLL REQUIREMENTS
The WSPLL is meant to lock onto the WSI input signal, and
regenerates 256fs and 128fs signals for the FSDAC and
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
given in Table 1, using Fig.4 as a reference. This means
that the user must set the input range of the WSI input
signal.
Clock modes
There are two clock systems:
• A SYSCLK signal, coming from the system
• A WSPLL which generates the internal clocks from the
incoming WSI signal.
The system frequency applied to pin SYSCLK is
selectable. The options are 256fs, 384fs, 512fs and 768fs.
The system clock must be locked in frequency to the digital
interface signals.
In case the SYSCLK is used for clocking the complete
system (decimator including interpolator) the WSPLL must
be powered-down with bit ADC_CLK via the L3-bus
or I2C-bus.
Remark: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
system the IC is in, there is no auto sample rate conversion
detection circuitry.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I2C-bus register.
The system can run in several modes, using the two clock
systems:
• Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
handbook, halfpage
WSI
VCO
• The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
DIV1
• The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
PRE1
128fs
(digital parts)
256fs
(ADC and FSDAC)
MGU527
Fig.4 WSPLL set-up.
Table 1
WSPLL divider settings
WORD SELECT
FREQUENCY (kHz)
6.25 to 12.5
SEL_LOOP_DIV[1:0]
PRE1
DIV1
00
8
1536
12.5 to 25
01
4
1536
25 to 50
10
2
1536
50 to 100
11
2
768
2004 Apr 22
11
VCO FREQUENCY
(MHz)
76 to 153
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.1.2
UDA1380
CLOCK DISTRIBUTION
Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain.
For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the
L3-bus and I2C-bus registers (ADC_CLK).
The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only;
the ADC part can run from 8 to 55 kHz.
enable clock
handbook, full pagewidth
256/384/512/768fs
ADC
ADC_CLK
SYSCLK
CLK_DIV
128fs
128fs
DECIMATOR
enable
clock
L3 or I2C-BUS
REGISTER
DECIMATOR
I2S-BUS
OUTPUT BLOCK
I2S-BUS
INPUT BLOCK
enable
clock
256fs
WSI
WSPLL
128fs
128fs
L3 or I2C-BUS
REGISTER
INTERPOLATOR
INTERPOLATOR
DAC_CLK
FSDAC
enable clock
MGU528
Fig.5 Clock routing for the main blocks inside the coder-decoder.
2004 Apr 22
12
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.2
UDA1380
ADC analog front-end
8.2.1
APPLICATIONS AND POWER-DOWN MODES
The following Power-down modes and functional modes
are supported:
The analog front-end of the UDA1380 consists of one
stereo ADC with a selector in front of it (see Fig.6). Using
this selector one can either select the microphone input
with the microphone amplifier (LNA) with a fixed 29 dB
gain and VGA (no PGA, since a real microphone amplifier
is much better with respect to noise), or the line input which
has a PGA for having 0 or 6 dB gain (for supporting 1 and
2 V (RMS) input). The PGA also provides gain control from
0 to 24 dB in steps of 3 dB.
• Power-down mode in which the power consumption is
very low (only leakage currents)
In this mode there is no reference voltage at the line
input
• Line input mode, in which the PGA can be used
Remark:
• Microphone mode, in which the rest of the non-used
PGAs and ADCs are powered-down
• The input impedance of the PGA (line input) is 12 kΩ, for
the LNA this is 5 kΩ
• Mixed PGA and LNA mode: one line input and one
microphone input.
More information on the analog frond-end is given in
Section 8.11.1.
handbook, full pagewidth
SEL_MIC
VINR
1
PGA
SDC
PGA
SDC
ADC
(29)
VINL
31
(27)
ADC
VINM
3
LNA
bitstream
right
bitstream
left
SDC
(31)
SEL_LNA
MGU530
Pin numbers for UDA1380HN in parentheses.
Fig.6 Analog front-end.
8.2.2
LNA WITH VGA
8.2.3
For the line input it is preferable to have 0 dB and 6 dB gain
settings in order to be able to apply both 1 and 2 V (RMS)
input signals, using a series resistance. For this purpose a
PGA is used which has 0 to 24 dB gain, in steps of 3 dB.
The LNA is equipped with a VGA. The function of the VGA
is to have additional variable analog gain from 0 to 30 dB
in steps of 2 dB. This provides more flexibility in the choice
of the microphone.
2004 Apr 22
APPLICATIONS WITH 2 V (RMS) INPUT
13
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
In applications in which a 2 V (RMS) input signal is used,
a 12 kΩ resistor must be used in series with the input of the
ADC (see Fig.7). This forms a voltage divider together with
the internal ADC resistor and ensures that the voltage,
applied to the input of the IC, never exceeds 1 V (RMS).
Using this application for a 2 V (RMS) input signal, the
switch must be set to 0 dB. When a 1 V (RMS) input signal
is applied to the ADC in the same application, the gain
switch must be set to 6 dB.
Table 3
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 2; the power supply
voltage is assumed to be 3 V.
8.3.1
8.3
PGA
0.01
>0.55fs
−70
0 to 0.45fs
>135
at 0 dB input
analog
−1.5
8.3.2
OVERLOAD DETECTION
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
0 dB
2 V (RMS)
6 dB
1 V (RMS)
0 dB
1 V (RMS)
6 dB
0.5 V (RMS)
VOLUME CONTROL
The decimator is equipped with a digital volume control.
This volume control is separate for left and right, and can
be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via
the L3-bus or I2C-bus interface. The range is from +24 dB
to −63.5 dB and mutes in steps of 0.5 dB.
8.3.3
Application modes using input gain stage
MUTE
The decimator is equipped with a dB-linear mute which
mutes the signal in 256 steps of 0.5 dB.
8.3.4
AGC FUNCTION
The decimation filter is equipped with an AGC block. This
function is intended, when enabled, to keep the output
signal at a constant level. The AGC can be used for
microphone applications in which the distance to the
microphone is not always the same.
Decimation filter (ADC)
The AGC can be enabled via an L3-bus or I2C-bus bit by
setting the bit to logic 1. In that case it bypasses the digital
volume control.
The decimation from 128fs is performed in two stages. The
sin x
first stage realizes a ----------- characteristic with a decimation
x
factor of 16. The second stage consists of 3 half-band
filters, each decimating by a factor 2. The filter
characteristics are shown in Table 3.
2004 Apr 22
0 to 0.45fs
In practice the output is used to indicate whenever the
output data, in either the output of the left or right channel,
exceeds −1 dB (the actual figure is −1.16 dB) of the
maximum possible digital swing. When this condition is
detected output bit OVERFLOW in the L3-bus register is
forced to logic 1 for at least 512fs cycles (11.6 ms at
fs = 44.1 kHz). This time-out is reset for each infringement.
Fig.7 ADC front-end with PGA (line input).
Absent
Pass-band ripple
The UDA1380 is equipped with an overload detector which
can be read out from the L3-bus or I2C-bus interface.
Pin numbers for UDA1380HN in parentheses.
Present
VALUE (dB)
Dynamic range
MGU529
RESISTOR
(12 kΩ)
CONDITION
Digital output
level
VDDA = 3 V
Table 2
ITEM
Stop band
handbook, halfpage
external
resistor VINL, 31,
12 kΩ
12 kΩ
VINR 1
input signal
2 V (RMS)
(27,
VREF
29)
Decimation filter characteristics
Via the L3-bus or I2C-bus interface also some other
settings of the AGC, like the attack and decay settings and
the target level settings, can be made.
Remark: The DC filter before the decimation filter must be
enabled by setting the L3-bus or I2C-bus bit SKIP_DCFIL
to logic 0 when AGC is in operation; otherwise the output
will be disturbed by the DC offset added in the ADC.
14
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.4
UDA1380
Interpolation filter (DAC)
8.4.2
SOUND FEATURES
The interpolation digital filter interpolates from 1 to 64fs or
to 128fs, by cascading FIR filters, see Table 4. The
interpolator is equipped with several sound features like
volume control, mute, de-emphasis and tone control.
In addition, there are basic sound features:
Table 4
• De-emphasis for 32, 44.1, 48 and 96 kHz for both
channel 1 and 2 (selectable independently)
• dB-linear volume control using 14-bit coefficients in
steps of 0.25 dB: range 0 to −78 dB maximum
suppression and −∞ dB: applies to both master volume
and mixing volume control
Interpolation filter characteristics
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.025
Stop band
>0.55fs
−60
Dynamic range
0 to 0.45fs
>135
8.4.1
• Treble, which is selectable gain for high frequencies
(positive gain only), the edge frequency of the treble is
fixed (depends on the sampling frequency). Can be set
for left and right independently:
– Two settings: fc = 1.5 kHz and fc = 3 kHz, assuming
sampling frequency is 44.1 kHz
DIGITAL MUTE
Muting the DAC will result in a cosine roll-off soft mute,
using 4 × 32 = 128 samples in normal mode (or 3 ms at
44.1 kHz sampling frequency). The cosine roll-off curve is
illustrated in Fig.8. These cosine roll-off functions are
implemented for both the digital mixer and the master mute
inside the DAC data path, see Section 8.8.
– Both settings have 0 to 6 dB gain range in steps
of 2 dB
• Bass boost, which is selectable gain for low frequencies
(positive gain only). The edge frequency of the bass
boost is fixed and depends on the sampling frequency.
Can be set for left and right independently:
– Two settings: fc = 250 Hz and fc = 300 Hz, assuming
sampling frequency is 44.1 kHz
– First setting: 0 to 18 dB gain range in steps of 2 dB
– Second setting: 0 to 24 dB gain range in steps
of 2 dB.
MGU119
1
handbook, halfpage
mute
factor
8.5
0.8
The noise shaper consists of two mono 3rd-order noise
shapers and one time-multiplexed stereo 5th-order noise
shaper.
0.6
The order of the noise shaper can be chosen between
3rd-order (which runs at 128fs) and 5th-order (which runs
at 64fs) via bit SEL_NS in the L3-bus or I2C-bus register.
The preferable choice for the noise shaper order is:
0.4
• 3rd-order noise shaper is preferred at low sampling
frequencies, for instance between 8 and 32 kHz. This is
for preventing out-of-band noise from the noise shaper
to move into the audio band
0.2
0
0
5
10
15
20
25
t (ms)
Fig.8
Noise shaper
• 5th-order noise shaper is normally used at higher
sampling frequencies, normally from 32 to 100 kHz.
The noise shaper shifts in-band quantization noise to
frequencies well above the audio band. This noise shaping
technique enables high signal-to-noise ratios to be
achieved. The noise shaper output is converted into an
analog signal using an FSDAC.
Mute as a function of raised cosine roll-off,
displayed assuming 44.1 kHz.
2004 Apr 22
15
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.6
UDA1380
FSDAC
8.6.1
8.7
GENERAL INFORMATION
The UDA1380 is equipped with a headphone driver which
can deliver 35 mW (at 3.0 V power supply) into a 16 Ω
load.
The Filter-Stream Digital-to-Analog Converter (FSDAC) is
a semi-digital reconstruction filter that converts the
1-bit data stream (running at either 64fs for the 5th-order
noise shaper or 128fs for the 3rd-order noise shaper) of the
noise shaper into an analog output voltage. The filter
coefficients are implemented as current sources, and are
summed at virtual ground of the output operational
amplifier. In this way very high signal-to-noise
performance and low clock jitter sensitivity are achieved.
A post-filter is not needed due to the inherent filter function
of the DAC. On-board amplifiers convert the FSDAC
output current to an output voltage signal, capable of
driving a line output. The output voltage of the FSDAC
scales proportionally with the power supply voltage.
The headphone driver does not need external
DC decoupling capacitors because it can be DC coupled
with respect to a special headphone output reference
voltage. This saves two external capacitors (which is quite
useful in a portable device).
The headphone driver is equipped with short-circuit
protection on all three operational amplifiers (left, right and
the virtual ground). Each of the operational amplifiers has
a signalling bit which becomes logic 1 in case the limiter is
activated, for instance in case of a short-circuit. This
means the microcontroller in the system can poll the
L3-bus or I2C-bus register of the headphone driver and as
soon as (and for as long as) the short-circuit detection bits
are activated, the microcontroller can signal the user that
something is wrong or power-down the headphone driver
(for instance, for energy-saving purposes).
Remark: When the FSDAC is powered-down, the output
of the FSDAC becomes high impedance.
8.6.2
ANALOG MIXER INPUT
The FSDAC has a mixer input, which makes it possible to
mix an analog signal to the output signal of the FSDAC
itself. In schematic form this is given in Fig.9.
Remark: To improve headphone channel separation
performance, the distance between VREF(HP) and the micro
speaker port must be minimized.
This mixer input can be used for instance for mixing-in a
GSM signal or an FM signal directly to the line output.
In the UDA1380, the mixer input is connected from the
ADC line input via an AVC unit.
8.8
8.8.1
bitstream
to analog mixer input
FSDAC
MGU531
Fig.9
Mixing signals to the FSDAC output
(analog domain).
2004 Apr 22
Digital and analog mixers (DAC)
DIGITAL MIXER
The ADC output signal and digital input signal can be
mixed without external DSP as shown in Fig.10. This mixer
can be controlled via the microcontroller interface, and
must only be enabled when the ADC and the DAC are
running at the same frequency. In addition, the mixer
output signal can also be applied to the I2S-bus output
interface.
Remark: Before the AVC unit can be used stand-alone,
meaning without the digital part running, first the DAC part
must be initialised in order to have the DAC output
generating zero current. Otherwise the signal will be
clipped.
handbook, halfpage
Headphone driver
16
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
from
handbook, data
full pagewidth
decimation
filter
(channel 2)
from
digital
data input
(channel 1)
DE-EMPHASIS
DE-EMPHASIS
VOLUME
AND
MUTE
VOLUME
AND
MUTE
UDA1380
1fs
mixing before
sound features
mixing after
sound features
BASS-BOOST
AND
TREBLE
master
2fs VOLUME
INTERPOLATION
AND
FILTER
MUTE
to
interpolation
filter
MGU532
SEL_SOURCE
I2S-BUS OUTPUT BLOCK
Fig.10 Digital mixer (DAC).
8.8.2
ANALOG MIXER
The analog mixer, which uses the mixer input of the FSDAC, can mix a signal into the FSDAC output signal via an AVC
unit (see Fig.11). The mixer can be used to mix a signal into the FSDAC output signal and play it via the headphone driver
without the complete coder-decoder running. The analog control range is 0 to −64.5 dB with a gain of 16.5 dB, and mutes
in steps of 1.5 dB (so actually the range is from +16.5 dB to −48 dB plus mute).
PON_AVC
handbook, full pagewidth
from analog
front-end
RESISTOR
NETWORK
AVC[5:0] L3 or I2C-bus control bits
Fig.11 Analog mixer configuration.
2004 Apr 22
17
to FSDAC
mixer input
enable mixer
(EN_AVC)
MGU533
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.9
UDA1380
Application modes
The reset timing is determined by the external capacitor
and resistor which are connected to pin RESET, and the
internal pull-down resistor. On Power-on reset, all the
digital sound processing features and the system
controlling features are set to the default setting of the
L3-bus and I2C-bus control modes.
The operation mode can be set with pin SEL_L3_IIC,
either to L3-bus mode (LOW) or to the I2C-bus mode
(HIGH) as given in Table 5.
For all features in microcontroller mode see Chapter 9.
Table 5
Remark: The reset time should be at least 1 μs, and during
the reset time the system clock should be running. In case
the WSPLL is selected as the clock source, a clock must
be connected to the SYSCLK input in order to have a
proper reset of the L3-bus or I2C-bus registers. This is
because the clock source is set to SYSCLK by default.
Pin function in the selected mode
L3-BUS MODE
SEL_L3_IIC = L
I2C-BUS MODE
SEL_L3_IIC = H
L3CLOCK/SCL
L3CLOCK
SCL
L3MODE
L3MODE
A1
L3DATA/SDA
L3DATA
SDA
PIN
8.11
The following blocks have power-down control via the
L3-bus or I2C-bus interface:
Remark: In the I2C-bus mode there is a bit A1 which sets
the LSB bit of the address of the UDA1380. In
L3-bus mode this bit is not available, meaning the device
has only one L3-bus device address.
8.10
• Microphone amplifier (LNA) including its Single-Ended
to Differential Converter (SDC) and VGA
• ADC plus SDC and the PGA, for left and right separate
• Bias generation circuit for the front-end and the FSDAC
Power-on reset
• Headphone driver
The UDA1380 has a dedicated reset pin, which has a
pull-down resistor. This way a Power-on reset circuit can
be made with a capacitor and a resistor at the pin. The
internal pull-down resistor cannot be used because of the
5 V tolerant nature of the pad. The pull-down resistor is
shielded from the outside world by a transmission gate in
order to support 5 V tolerance.
2004 Apr 22
Power-down requirements
• WSPLL
• FSDAC.
Clocks of the decimator, interpolator and the analog blocks
have separate enable and disable controls.
18
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.11.1
UDA1380
ANALOG FRONT-END
Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is
done via separate L3-bus or I2C-bus bits.
PGA_GAINCTRLL
handbook, full pagewidth
PGA_GAINCTRLR
VINR
1
PGA
SDC
PGA
SDC
ADC
bitstream
right
ADC
bitstream
left
(29)
VINL
31
(27)
VINM
3
LNA
(31)
PON_LNA
SDC
PON_BIAS
PON_PGAR
PON_PGAL
PON_ADCR
VREF
PON_ADCL
FE
BIAS
MGU534
Pin numbers for UDA1380HN in parentheses.
Fig.12 Analog front-end power-down.
8.11.2
FSDAC POWER CONTROL
the FSDAC or headphone driver can be powered-down.
In case the FSDAC or headphone driver must be
powered-up, first the analog part is switched on, then the
digital part is demuted
The FSDAC block has power-on pins: one of which shuts
down the DAC itself, but leaves the output still at VREF
voltage (which is half the power supply). This function is
set by the bit PON_DAC in the L3-bus or I2C-bus register.
• When the ADC must be powered-down, a digital mute
sequence must be applied. When the digital output
signal is completely muted, the ADC can be
powered-down. In case the ADC must be powered-up,
first the analog part must be powered-up, then the digital
part must be demuted
A second L3-bus or I2C-bus bit shuts down the complete
bias circuit of the FSDAC, via bit PON_BIAS in the
L3-bus or I2C-bus register. This bit PON_BIAS acts the
same as given in Fig.12 for the analog front-end.
8.12
• When there is a change of, for example, clock divider
settings or clock source (selecting between SYSCLK
and WSPLL clock), then also digital mute for that block
(either decimator or interpolator) should be used.
Plop prevention
Plops are ticks and other strange sounds that can occur
when a part of a device is powered-up or powered-down,
or when switching between modes is done.
Remark: All items mentioned in Section 8.12 are not
‘hard-wired’ implemented, but are to be followed by the
user as a guideline for plop prevention.
Some ways to prevent plops from occurring are:
• When the FSDAC or headphone driver must be
powered-down, first a digital mute is applied. After that
2004 Apr 22
19
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.13
UDA1380
Digital audio data input and output
The slave and master modes can be selected by the
bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus
interface.
The supported audio formats for the control modes are:
• I2S-bus
• MSB-justified
9
• LSB-justified, 16 bits
L3-BUS INTERFACE DESCRIPTION
• LSB-justified, 20 bits
The UDA1380 has an L3-bus microcontroller
interface mode. Controllable system and digital sound
processing features are:
• LSB-justified, 24 bits (only for the output interface).
• Software reset
• LSB-justified, 18 bits
• System clock frequency (selection between 256fs, 384fs,
512fs and 768fs clock divider settings)
The bit clock BCK can be up to 128fs, or in other words the
BCK frequency is 128 times the WS frequency or less:
fBCK ≤ 128fWS.
• Clock mode setting, for instance, which block runs at
which clock, and clock enabling
Remark: The WS edge must coincide with the negative
edge of the BCK at all times, for proper operation of the
digital I/O data interface. Figure 13 shows the interface
signals.
8.13.1
• Power control for the WSPLL
• Data input and data output format control, for input and
output independently including data source selection for
the digital output interface
DIGITAL AUDIO INPUT INTERFACE
• ADC features:
The digital audio input interface is slave only, meaning the
system must provide the WSI and BCKI signals (next to
the DATAI signal).
– Digital mute
– AGC enable and settings
– Polarity control
Either the WSPLL locks onto the WSI signal and provides
the internal clocks for the interpolator and the FSDAC, or
a system clock must be applied which must be in
frequency lock to the digital data input interface signals.
8.13.2
– Input line amplifier control (0 to 24 dB in steps of
3 dB)
– DC filtering control
– Digital gain control (+24 to −63 dB gain in steps of
0.5 dB) for left and right
DIGITAL AUDIO OUTPUT INTERFACE
The digital audio output interface can be either master or
slave. The data source for the data output can be selected
from either the decimator (ADC front-end) or the digital
mixer output.
– Power control
– VGA of the microphone input
– Selection of line or microphone input.
• DAC and headphone driver features:
Remark: The digital mixer output is only valid if both the
decimator and the interpolator run at the same clock:
– Power control FSDAC and headphone driver
• In slave mode the signals on pins BCKO, WSO and
SYSCLK must be applied from the application (signals
must be in frequency lock) and the UDA1380 returns the
DATAO signal from the decimator. The applied signal
from pin BCKO can be for instance: 32fs, 48fs, 64fs,
96fs or 128fs
– Polarity control
– Mixing control (only available when both decimator
and interpolator run at the same speed). This
includes the mixer volumes, mute and mixer position
switch
– De-emphasis control
• In master mode the SYSCLK signal must be applied
from the system, then the UDA1380 returns with the
BCKO, WSO and the DATAO signals. For the BCKO
clock, there are 2 general rules:
– Master volume and balance control
– Flat/minimum/maximum settings for bass boost and
treble
– When the SYSCLK is either 256fs or 512fs, the BCKO
frequency is 64fs
– Tone control: bass boost and treble
– When the SYSCLK is either 384fs or 768fs, the BCKO
signal is 48fs.
– Headphone driver short-circuit protection status bits.
2004 Apr 22
– Master mute control
20
2
>=8
3
1
2
3
MSB
B2
BCK
MSB
DATA
B2
>=8
MSB
I2S-BUS FORMAT
LEFT
WS
1
2
RIGHT
>=8
3
1
2
>=8
3
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
B15 LSB
MSB
15
2
NXP Semiconductors
1
Stereo audio coder-decoder
for MD, CD and MP3
andbook, full pagewidth
2004 Apr 22
RIGHT
LEFT
WS
1
BCK
DATA
MSB
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
21
WS
LEFT
RIGHT
18
17
16
15
2
1
18
B17 LSB
MSB
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
23
22
21
20
RIGHT
19
18
17
16
15
2
1
24
B23 LSB
MSB
23
22
21
20
19
18
17
16
15
2
1
BCK
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
B3
LSB-JUSTIFIED FORMAT 24 BITS
Fig.13 Serial interface input and output formats.
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MBL121
UDA1380
DATA
Product specification
24
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
9.1
UDA1380
Introduction
The device address consists of one byte, which is split-up
in two parts:
The exchange of data and control information between the
microcontroller and the UDA1380, is accomplished
through a serial hardware interface comprising the
following pins:
• Bits 7 to 2 represent a 6-bit device address. In the
UDA1380 this is 000001
• Bits 1 to 0 called Data Operation Mode, or DOM bits,
represent the type of data transfer according to Table 6.
L3DATA/SDA: microcontroller interface data line
L3MODE: microcontroller interface mode line
9.3
L3CLOCK/SCL: microcontroller interface clock line.
The UDA1380 acts as a slave receiver or a slave
transmitter. Therefore the signals L3CLOCK and L3MODE
are only input signals. The data signal L3DATA is a
bidirectional line. The UDA1380 slave address is shown in
Table 7.
Information transfer via the microcontroller bus is
organized LSB first, and in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: address mode and data transfer mode.
Inside the microcontroller interface there is a hand-shake
mechanism which takes care of proper data transfer from
the microcontroller interface clock to the destination clock
domains. This means that when data is sent to the
microcontroller interface, the system clock must be
running.
Table 7
0
Device addressing
DOM
BIT 0
0
0
not used
0
1
not used
1
0
DATA and STATUS write or pre-read
1
1
DATA and STATUS read
0
0
0
1
Register addressing
• Register addressing for L3 write: the first bit is a logic 0
indicating a write action to the destination register,
followed by seven register address bits
• Prepare read addressing: the first bit of the byte is
logic 1; signalling data will be read from the register
indicated
TRANSFER
• The read action itself: in this case the device returns a
register address prior to sending data from that register.
When the first bit of the byte is logic 0, the register
address was valid, in case the first bit is a logic 1 the
register address was invalid.
Remarks:
Table 6 shows that there are two types of data transfers:
DATA and STATUS which can be read and written.
Table 6 also shows that the DATA and STATUS read and
write actions are combined.
2004 Apr 22
0
(LSB)
Basically there are three forms for register addressing:
Selection of data transfer
DOM
BIT 1
BIT
After sending the device address, including the flags (the
DOM bits) whether information is read or written, one byte
is sent with the destination register address using 7 bits,
and one bit which signals whether information will be read
or written. The fundamental timing for L3 is given in Fig.19.
The device addressing mode is used to select a device for
subsequent data transfer. The address mode is
characterized by the signal on pin L3MODE being LOW
and a burst of 8 pulses on pin L3CLOCK/SCL,
accompanied by an 8 bit device address on
pin L3DATA/SDA. The fundamental timing is shown in
Figs 14 and 15.
Table 6
L3 slave address
(MSB)
9.4
9.2
Slave address
• Each time a new destination address needs to be
written, the device address must be sent again
• When addressing the device for the first time after
power-up of the device, at least one L3 clock-cycle must
be given to enable the L3 interface.
22
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
9.5
UDA1380
Data write mode
For writing data to a device, four bytes must be sent. Figure 14 explains the data write mode in a signal diagram:
• One byte with the device address, being ‘00000110’, which is including the LSB code 01 for signalling write to the
device
• One byte starting with a logic 0 for signalling write, followed by 7 bits indicating the destination address
• Two data bytes.
The SYSCLK signal must be applied in data write mode.
Table 8
L3 write data
BIT
L3 MODE
Addressing mode
DATA TYPE
device address
0(1)
1
2
3
4
5
6
7(2)
0
1
1
0
0
0
0
0
Data transfer 1
register address
0
A6
A5
A4
A3
A2
A1
A0
Data transfer 2
MS data byte
D15
D14
D13
D12
D11
D10
D9
D8
Data transfer 3
LS data byte
D7
D6
D5
D4
D3
D2
D1
D0
Notes
1. First bit in time.
2. Last bit in time.
9.6
• One byte with the device address including ‘11’ is sent
to the device, being 00000111. The ‘11’ indicates that
the device must write data to the microcontroller, then
the microcontroller frees the L3DATA-bus so the
UDA1380 can send the register address byte and its
two-byte contents
Data read mode
For reading from the device, first a prepare-read must be
done. After this, the device address is sent again. The
device then returns with the register address, indicating
whether the address was valid or not, and the data of the
register. The following five steps explain this procedure,
and an example of transmission is given in Fig.15.
• The device now writes the requested register address
on the bus, indicating whether the requested register
was valid or not (logic 0 means valid, logic 1 means
invalid)
• One byte with the device address, being ‘00000110’,
which is including the LSB code 01 for signalling write to
the device
• The device writes the data from the requested register
on the bus, being two bytes.
• One byte is sent with the register address from which it
needs to be read. This byte starts with a logic 1, which
indicates that there will be a read action from the register
2004 Apr 22
The SYSCLK signal must be applied in data read mode.
23
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
Table 9
UDA1380
L3 prepare read data
BIT
L3 MODE
DATA TYPE
0(1)
1
2
3
4
5
6
7(2)
Addressing mode
device address
0
1
1
0
0
0
0
0
Data transfer 1
register address
1
A6
A5
A4
A3
A2
A1
A0
Notes
1. First bit in time.
2. Last bit in time.
Table 10 L3 read data
BIT
L3 MODE
DATA TYPE
0(1)
1
2
3
4
5
6
7(2)
Addressing mode
device address
1
1
1
0
0
0
0
0
Data transfer 1;
note 3
register address
0: valid
1: invalid
A6
A5
A4
A3
A2
A1
A0
Data transfer 2;
note 3
MS data byte
D15
D14
D13
D12
D11
D10
D9
D8
Data transfer 3;
note 3
LS data byte
D7
D6
D5
D4
D3
D2
D1
D0
Notes
1. First bit in time.
2. Last bit in time.
3. Data transfer from the UDA1380 to the microcontroller.
2004 Apr 22
24
L3MODE
register address
device address
1
0
L3DATA
data byte 1
data byte 2
0
MGU535
DOM bits
write
NXP Semiconductors
Stereo audio coder-decoder
for MD, CD and MP3
2004 Apr 22
L3CLOCK
Fig.14 Data write mode for L3 version 2.
25
L3CLOCK
L3MODE
register address
device address
L3DATA
1
DOM bits
read
1 1
register address
data byte 1
data byte 2
0/1
valid/non-valid
send by the device
Fig.15 Data read mode for L3 version 2.
MGU536
UDA1380
prepare read
Product specification
0 1
device address
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
DEVICE ADDRESS (PIN A1)
10 I2C-BUS INTERFACE DESCRIPTION
10.1.1
The UDA1380 supports I2C-bus microcontroller interface
mode as well as the L3-bus mode; all features can be
controlled by the microcontroller with the same register
addresses as in the L3-bus mode.
The UDA1380 acts as either a slave receiver or a slave
transmitter. Therefore the clock signal SCL is only an input
signal. The data signal SDA is a bidirectional line. Table 11
shows the device address of the UDA1380.
The exchange of data and control information between the
microcontroller and the UDA1380 in I2C-bus mode is
accomplished through a serial hardware interface
comprising the following pins:
The device can be set to one of the two addresses by using
bit A1 (which is pin L3MODE) to select.
Table 11 I2C-bus device address
L3CLOCK/SCL: microcontroller interface clock line,
SCL
(MSB)
0
L3MODE: sets the bit A1of the I2C-bus device address
L3DATA/SDA: microcontroller interface data line, SDA.
10.1.2
Figure 20 shows the clock and data timing of the I2C-bus
transfer.
10.1
BIT
0
1
1
(LSB)
0
A1
0
R/W
REGISTER ADDRESS
Table 12 shows the register address format of the
UDA1380. The register mapping in I2C-bus mode is the
same as for the L3-bus interface.
Addressing
Table 12 I2C-bus register address
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure. The UDA1380 device address is
[A6 to A0] 00110(A1)0, with bit A1 as the address
selection bit (two addresses possible).
2004 Apr 22
(MSB)
0
26
BIT
A6
A5
A4
(LSB)
A3
A2
A1
A0
Table 13 shows the I2C-bus configuration for a WRITE cycle. The WRITE cycle is used to write the data to the internal registers. The device and register
addresses are one byte each, the setting data is always a pair of two bytes.
The format of the WRITE cycle is as follows:
1. The microcontroller begins by asserting a start condition (S).
2. The first byte (8 bits) contains the device address ‘00110A10’ and the R/W bit is set to logic 0 (WRITE).
3. The UDA1380 asserts an acknowledge (A).
4. The microcontroller writes the 8-bit address (ADDR) of the UDA1380 register to which the data will be written.
5. The UDA1380 acknowledges this register address (A).
6. The microcontroller sends two bytes of data with the Most Significant (MS) byte first, followed by the Least Significant (LS) byte; after each byte the
UDA1380 asserts an acknowledge (A).
7. After each pair of bytes transmitted, the register address is auto-incremented; after each byte the UDA1380 asserts an acknowledge (A).
8. The UDA1380 frees the I2C-bus allowing the microcontroller to generate a stop condition (P).
NXP Semiconductors
WRITE cycle
Stereo audio coder-decoder
for MD, CD and MP3
2004 Apr 22
10.2
Table 13 Master transmitter writes to UDA1380 registers in the I2C-bus mode
INITIAL BYTE
ACKNOWLEDGE FROM UDA1380
27
STAR
T
DEVICE
ADDRESS
R/W
S
00110A10
0
MS data
byte
REGISTER
ADDRESS
A
ADDR
A
MS1
LS data
byte
A
LS1
STOP
A
...
A
...
A
MSn
A
LSn
A
P
auto increment if repeated n groups of 2 bytes are transmitted
Product specification
UDA1380
Table 14 shows the I2C-bus configuration for a READ cycle. The READ cycle is used to read the data values from the internal registers.
The format of the READ cycle is as follows:
1. The microcontroller begins by asserting a start condition (S).
2. The first byte (8 bits) contains the device address ‘00110A10’ and the R/W bit is set to logic 0 (WRITE).
3. The UDA1380 asserts an acknowledge (A).
4. The microcontroller writes the 8-bit address (ADDR) of the UDA1380 register from which the data will be read.
5. The UDA1380 acknowledges this register address (A).
6. The microcontroller generates a repeated start (Sr).
7. The microcontroller generates the device address ‘00110A10’ again, but this time the R/W bit is set to logic 1 (READ).
8. The UDA1380 asserts an acknowledge (A).
9. The UDA1380 sends two bytes of data with the Most Significant (MS) byte first, followed by the Least Significant (LS) byte; after each byte the
microcontroller asserts an acknowledge (A).
NXP Semiconductors
READ cycle
Stereo audio coder-decoder
for MD, CD and MP3
2004 Apr 22
10.3
10. After each pair of bytes transmitted, the register address is auto-incremented; after each byte the microcontroller asserts an acknowledge (A).
11. The microcontroller stops this cycle by generating a negative acknowledge (NA).
12. The UDA1380 frees the I2C-bus allowing the microcontroller to generate a stop condition (P).
28
Table 14 Master transmitter reads from the UDA1380 registers in the I2C-bus mode
INITIAL BYTE
S
ACKNOWLEDGE FROM UDA1380
DEVICE
ADDRESS
R/W
00110A10
0
A
ADDR
A
Sr
REGISTER
ADDRESS
R/W
00110A10
1
ACKNOWLEDGE FROM MICROCONTROLLER
MS data
byte
A
MS1
LS data
byte
A
LS1
A
...
A
...
A
MSn
A
LSn
NA
P
auto increment if repeated n groups of 2 bytes are transmitted
Product specification
UDA1380
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11 REGISTER MAPPING
Table 15 Register map of control settings (write)
REGISTER
ADDRESS
FUNCTION
System settings (running at the L3-bus or I2C-bus clock itself)
00H
evaluation modes, WSPLL settings, clock divider and clock selectors
01H
I2S-bus I/O settings
02H
power control settings
03H
analog mixer settings
04H
headphone amplifier settings
Interpolation filter (running at 128fs interpolator clock)
10H
master volume control
11H
mixer volume control
12H
mode selection, left and right bass boost, and treble settings
13H
master mute, channel 1 and channel 2 de-emphasis and channel mute
14H
mixer, silence detector and interpolation filter oversampling settings
Decimator (running at 128fs decimator clock)
20H
decimator volume control
21H
PGA settings and mute
22H
ADC settings
23H
AGC settings
Software reset
7FH
restore L3-default values
Table 16 Register map of status bits (read-out)
REGISTER
ADDRESS
FUNCTION
Headphone driver and interpolation filter
18H
interpolation filter status
Decimator
28H
2004 Apr 22
decimator status
29
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.1
UDA1380
Evaluation modes and clock settings
Table 17 Register address 00H
BIT
15
14
13
12
11
10
9
8
Symbol
EV2
EV1
Default
0
0
EV0
−
EN_ADC
EN_DEC
EN_DAC
EN_INT
0
0
0
1
0
1
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
ADC_CLK
DAC_CLK
sys_div1
sys_div0
PLL1
PLL0
Default
0
0
0
0
0
0
1
0
Table 18 Description of register bits
BIT
15 to 13
SYMBOL
DESCRIPTION
EV[2:0]
Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for
manufacturer’s evaluation and must always be kept at their default values for
normal operation of UDA1380; default value 000.
12
−
default value 0
11
EN_ADC
ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK
input) to the analog part of the ADC. See Fig.5 for more detailed information.
When this bit is logic 0: clock to ADC disabled and when this bit is logic 1:
clock to ADC running. Default value 0.
10
EN_DEC
Decimator clock enable. A 1-bit value to enable the 128fs clock to the
decimator, the 128fs part of the I2S-bus output block and the clock to the ADC
L3-bus or I2C-bus registers. See Fig.5 for more detailed information. When
this bit is logic 0: clock to the decimator disabled. When this bit is logic 1:
clock to the decimator running. Default value 1.
9
EN_DAC
FSDAC clock enable. A 1-bit value to enable the 256fs clock to the analog
part of the FSDAC. See Fig.5 for more detailed information. When this bit is
logic 0: clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC
running. Default value 0.
8
EN_INT
Interpolator clock enable. A 1-bit value to enable the 128fs clock to the
interpolator, the 128fs part of the I2S-bus input block and the interpolator
registers of the L3-bus or I2C-bus interface. See Fig.5 for more detailed
information. When this bit is logic 0: clock to the interpolator disabled. When
this bit is logic 1: clock to the interpolator running. Default value 1.
−
default value 00
ADC_CLK
ADC clock select. A 1-bit value to select the 128fs clock and the clock of the
analog part for the decimator and the ADC. This can either be the clock
derived from the SYSCLK input or from the WSPLL. When this bit is logic 0:
SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0.
7 and 6
5
2004 Apr 22
30
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
BIT
4
UDA1380
SYMBOL
DESCRIPTION
DAC_CLK
DAC clock select. A 1-bit value to select the clocks for the DAC
(interpolator and FSDAC analog block). In both cases the clocks must be
128fs and 256fs (for the analog part), but in one case the clock is derived from
the WSI clock, and in the other case the clock is derived from the SYSCLK.
When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is
used. Default value 0.
3 and 2
sys_div[1:0]
Dividers for system clock input. A 2-bit value to select the proper division
factor for the SYSCLK input in such a way that a128fs clock will be generated
from the SYSCLK clock signal. The 128fs clock is needed for clocking the
decimator and interpolator. Default value 00, see Table 19.
1 and 0
PLL[1:0]
WSPLL setting. A 2-bit value to select the WSPLL input frequency range.
These set the proper divider setting for the WSPLL. The input is the
WSI signal, the output inside the IC is a 128fs and a 256fs clock. Default
value 10, see Table 20.
Table 19 Dividers for system clock input
sys_div1
sys_div0
INPUT CLOCK ON PIN SYSCLK
0
0
256fs (default)
0
1
384fs
1
0
512fs
1
1
768fs
PLL1
PLL0
INPUT FREQUENCY RANGE (kHz) ON PIN WSI
0
0
6.25 to 12.5
0
1
12.5 to 25
1
0
25 to 50 (default)
1
1
50 to 100
Table 20 WSPLL settings
2004 Apr 22
31
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.2
UDA1380
I2S-bus input and output settings
Table 21 Register address 01H
BIT
15
14
13
12
11
10
9
8
Symbol
−
−
−
−
−
SFORI2
SFORI1
SFORI0
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
SEL_
SOURCE
−
SIM
−
SFORO2
SFORO1
SFORO0
Default
0
0
0
0
0
0
0
0
Table 22 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 to 11
−
default value 00000
10 to 8
SFORI[2:0]
Digital data input formats. A 3-bit value to select the digital input data
format (DATAI input). Default value 000, see Table 23.
7
−
default value 0
6
SEL_SOURCE
Digital output interface mode settings. A 1-bit value SEL_SOURCE to set
the mode of the digital output interface source to either the decimator output
or the digital mixer output. When this bit is logic 0: source digital output
interface mode set to decimator. When this bit is logic 1: source digital output
interface mode set to digital mixer output. Default value 0.
5
−
default value 0
4
SIM
Digital output interface mode settings. A 1-bit value SIM sets the mode of
the digital output interface. The speed of the BCKO pad, being 64fs or 48fs, is
selected by the bits sys_div[1:0]. In case the 384fs or 768fs mode is selected
the output clock is 48fs, in case 256fs or 512fs is selected, the BCKO is 64fs.
When this bit is logic 0: mode of digital output interface is set to slave. When
this bit is logic 1: mode of digital output interface is set to master. Default
value 0.
−
default value 0
SFORO[2:0]
Digital data output formats. A 3-bit value to set the digital data output format
(on pin DATAO). Default value 000, see Table 24.
3
2 to 0
Table 23 Digital data input formats
SFORI2
SFORI1
SFORI0
SERIAL_FORMAT_DAI
0
0
0
I2S-bus (default)
0
0
1
LSB-justified, 16 bits
0
1
0
LSB-justified, 18 bits
0
1
1
LSB-justified, 20 bits
1
0
1
MSB-justified
1
0
0
not used: mapped to I2S-bus
1
1
0
1
1
1
2004 Apr 22
32
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 24 Digital data output formats
SFORO2
SFORO1
SFORO0
SERIAL_FORMAT_DAO
0
0
0
I2S-bus (default)
0
0
1
LSB-justified, 16 bits
0
1
0
LSB-justified, 18 bits
0
1
1
LSB-justified, 20 bits
1
0
0
LSB-justified, 24 bits
1
0
1
MSB-justified
1
1
0
not used: mapped to I2S-bus
1
1
1
11.3
Power control settings
11.3.1
POWER CONTROL SETTING BIAS CIRCUITS
Using a 1-bit value, the power control settings of the bias circuits of the ADC, AVC and FSDAC can be set. When this bit
is set to logic 0, the complete bias circuits of the analog front-end and the FSDAC are shut down. In this case, the
reference voltage disappears from the input of the ADCs and LNA and the output of the FSDAC, this can cause plops
but saves power.
Table 25 Register address 02H
BIT
15
14
13
12
11
10
9
8
Symbol
PON_PLL
−
PON_HP
−
−
PON_DAC
−
PON_
BIAS
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
EN_AVC
PON_AVC
−
PON_LNA
PON_
PGAL
PON_
ADCL
PON_
PGAR
PON_
ADCR
Default
0
0
0
0
0
0
0
0
Table 26 Description of register bits
BIT
SYMBOL
DESCRIPTION
15
PON_PLL
Power-on WSPLL. When this bit is logic 0: power-off; when this bit is logic 1:
power-on. Default value 0.
14
−
13
PON_HP
12 and 11
−
10
PON_DAC
9
−
2004 Apr 22
default value 0
Power-on headphone driver. A 1-bit value to switch the headphone driver
into power-on or Power-down mode. When this bit is logic 0: headphone
driver is powered-off; when this bit is logic 1: headphone driver is powered-on.
Default value 0.
default value 00
Power-on DAC. A 1-bit value to switch the DAC into power-on or
Power-down mode. In this Power-down mode the VREF (half the power supply
voltage) will remain on the FSDAC output. When this bit is logic 0: DAC is
powered-off; when this bit is logic 1: DAC is powered-on. Default value 0.
default value 0
33
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
BIT
SYMBOL
DESCRIPTION
8
PON_BIAS
Power-on BIAS. A 1-bit value to set the power control setting of the ADC,
AVC and FSDAC. When this bit is logic 0: ADC, AVC and FSDAC bias circuits
are powered-off; when this bit is logic 1: Power-on bias for ADC, AVC and
FSDAC. Default value 0.
7
EN_AVC
6
PON_AVC
Enable control AVC. A 1-bit value to enable or disable the analog mixer.
When this bit is logic 0: analog mixer is disabled; when this bit is logic 1:
analog mixer is enabled. Default value 0.
Power-on AVC. A 1-bit value to have power-on control for the analog mixer.
When this bit is logic 0: analog mixer powered-off; when this bit is logic 1:
analog mixer powered-on. Default value 0.
5
−
4
PON_LNA
3
PON_PGAL
Power-on PGAL. A 1-bit value to have power-on control for the PGA left.
When this bit is logic 0: left PGA is powered-off; when this bit is logic 1: left
PGA is powered-on. Default value 0.
2
PON_ADCL
Power-on ADCL. A 1-bit value to have power-on control for the ADC left.
When this bit is logic 0: left ADC is powered-off; when this bit is logic 1: left
ADC is powered-on. Default value 0.
1
PON_PGAR
Power-on PGAR. A 1-bit value to have power-on control for the PGA right.
When this bit is logic 0: right PGA is powered-off; when this bit is logic 1: right
PGA is powered-on. Default value 0.
0
PON_ADCR
Power-on ADCR. A 1-bit value to have power-on control for the ADC right.
When this bit is logic 0: right ADC is powered-off; when this bit is logic 1: right
ADC is powered-on. Default value 0.
2004 Apr 22
default value 0
Power-on LNA. A 1-bit value to power-on the LNA and SDC. When this bit is
logic 0: LNA and SDC are powered-off; when this bit is logic 1: LNA and SDC
are powered-on. Default value 0.
34
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.4
UDA1380
Analog mixer settings
Table 27 Register address 03H
BIT
15
14
13
12
11
10
9
8
Symbol
−
−
AVCL5
AVCL4
AVCL3
AVCL2
AVCL1
AVCL0
Default
0
0
1
1
1
1
1
1
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
AVCR5
AVCR4
AVCR3
AVCR2
AVCR1
AVCR0
Default
0
0
1
1
1
1
1
1
Table 28 Description of register bits
BIT
SYMBOL
DESCRIPTION
−
default value 00
13 to 8
AVCL[5:0]
Analog volume control. A 6-bit value to program the left master volume
attenuation. The range is from +16.5 to −48 and −∞ dB in steps of 1.5 dB. The
16.5 dB gain is there to boost the 150 mV (RMS) which comes from for
instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver
full-swing. Default value 111111, see Table 29.
7 and 6
−
default value 00
AVCR[5:0]
Analog volume control. A 6-bit value to program the right master volume
attenuation. The range is from +16.5 to −48 and −∞ dB in steps of 1.5 dB. The
16.5 dB gain is there to boost the 150 mV (RMS) which comes from for
instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver
full-swing. Default value 111111, see Table 29.
15 and 14
5 to 0
2004 Apr 22
35
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 29 Analog volume control
AVCL5
AVCR5
AVCL4
AVCR4
AVCL3
AVCR3
AVCL2
AVCR2
AVCL1
AVCR1
AVCL0
AVCR0
VOLUME (dB)
0
0
0
0
0
0
16.5
0
0
0
0
0
1
15
0
0
0
0
1
0
13.5
0
0
0
0
1
1
12
0
0
0
1
0
0
10.5
11.5
:
:
:
:
:
:
:
1
0
1
0
1
1
−48
1
0
1
1
0
0
−∞
:
:
:
:
:
:
:
1
1
1
1
1
1
−∞ (default)
Headphone amplifier settings
Using a 1-bit value, it is possible to disable the short-circuit protection of the headphone amplifier. This function is
provided to offer maximum freedom to users, however due to the nature of this function there is the drawback of possible
damage. Bits RSV12, RSV11, RSV10, RSV02, RSV01, and RSV00 are special control bits for manufacturer’s evaluation
and must always be kept at their default values for normal operation of UDA1380.
Table 30 Register address 04H
BIT
15
14
13
12
11
10
9
8
Symbol
−
−
−
−
−
RSV12
RSV11
RSV10
Default
−
−
−
−
−
0
1
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
−
−
−
RSV02
EN_SCP
RSV00
Default
−
−
−
−
−
0
1
0
Table 31 Description of register bits
BIT
SYMBOL
DESCRIPTION
−
not used
10
RSV12
Reserved bit. Default value 0
9
RSV11
Reserved bit. Default value 1
8
RSV10
Reserved bit. Default value 0
−
not used
2
RSV02
Reserved bit. Default value 0
1
EN_SCP
Short circuit protection enable. A 1-bit value to enable the short circuit protection of the
headphone amplifier. When this bit is set to logic 0: short-circuit protection is disabled.
When this bit is set to logic 1: short-circuit protection is enabled. Default value 1.
Short-circuit detection is always enabled regardless of this bit.
0
RSV00
Reserved bit. Default value 0
15 to 11
7 to 3
2004 Apr 22
36
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.6
UDA1380
Master volume control
Table 32 Register address 10H
BIT
15
14
13
12
11
10
9
8
Symbol
MVCR_7
MVCR_6
MVCR_5
MVCR_4
MVCR_3
MVCR_2
MVCR_1
MVCR_0
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
MVCL_7
MVCL_6
MVCL_5
MVCL_4
MVCL_3
MVCL_2
MVCL_1
MVCL_0
Default
0
0
0
0
0
0
0
0
Table 33 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 to 8
MVCR_[7:0]
Master volume control right. An 8-bit value to program the right channel
volume attenuation. The range is from 0 to −78 dB and −∞ dB in steps of
0.25 dB. Default value 00000000, see Table 34.
7 to 0
MVCL_[7:0]
Master volume control left. An 8-bit value to program the left channel
volume attenuation. The range is from 0 to −78 dB and −∞ dB in steps of
0.25 dB. Default value 00000000, see Table 34.
Table 34 Master volume control bits
MVCR_7
MVCL_7
MVCR_6
MVCL_6
MVCR_5
MVCL_5
MVCR_4
MVCL_4
MVCR_3
MVCL_3
MVCR_2
MVCL_2
MVCR_1
MVCL_1
MVCR_0
MVCL_0
VOLUME (dB)
0
0
0
0
0
0
0
0
0 (default)
0
0
0
0
0
0
0
1
−0.25
0
0
0
0
0
0
1
0
−0.50
0
0
0
0
0
0
1
1
−0.75
0
0
0
0
0
1
0
0
−1
:
:
:
:
:
:
:
:
:
1
1
0
0
1
0
0
0
−50
1
1
0
0
1
1
0
0
−51
1
1
0
0
1
1
0
1
−51.25
1
1
0
0
1
1
1
0
−51.50
1
1
0
0
1
1
1
1
−51.75
1
1
0
1
0
0
0
0
−52
1
1
0
1
0
1
0
0
−54
1
1
0
1
1
0
0
0
−56
:
:
:
:
:
:
:
:
:
1
1
1
0
1
1
0
0
−66
1
1
1
1
0
0
0
0
−69
1
1
1
1
0
1
0
0
−72
1
1
1
1
1
0
0
0
−78
1
1
1
1
1
1
0
0
−∞
2004 Apr 22
37
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.7
UDA1380
Mixer volume control
Table 35 Register address 11H
BIT
15
14
13
12
11
10
9
8
Symbol
VC2_7
VC2_6
VC2_5
VC2_4
VC2_3
VC2_2
VC2_1
VC2_0
Default
1
1
1
1
1
1
1
1
BIT
7
6
5
4
3
2
1
0
Symbol
VC1_7
VC1_6
VC1_5
VC1_4
VC1_3
VC1_2
VC1_1
VC1_0
Default
0
0
0
0
0
0
0
0
Table 36 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 to 8
VC2_[7:0]
Digital mixer volume control. An 8-bit value to program the channel 2
volume attenuation. The range is 0 to −72 dB and −∞ dB in steps of 0.25 dB.
Default value for channel 2 is 11111111, see Table 37.
7 to 0
VC1_[7:0]
Digital mixer volume control. An 8-bit value to program the channel 1
volume attenuation. The range is 0 to −72 dB and −∞ dB in steps of 0.25 dB.
Default value for channel 1 is 00000000, see Table 37.
Table 37 Digital mixer volume control
VC2_7
VC1_7
VC2_6
VC1_6
VC2_5
VC1_5
VC2_4
VC1_4
VC2_3
VC1_3
VC2_2
VC1_2
VC2_1
VC1_1
VC2_0
VC1_0
VOLUME
(dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
−0.25
0
0
0
0
0
0
1
0
−0.50
0
0
0
0
0
0
1
1
−0.75
0
0
0
0
0
1
0
0
−1
:
:
:
:
:
:
:
:
:
1
0
1
1
0
1
0
0
−45
1
0
1
1
0
1
0
1
−45.25
1
0
1
1
0
1
1
0
−45.50
1
0
1
1
0
1
1
1
−45.75
1
0
1
1
1
0
0
0
−46
1
0
1
1
1
1
0
0
−48
1
1
0
0
0
0
0
0
−50
:
:
:
:
:
:
:
:
:
1
1
0
1
0
1
0
0
−60
1
1
0
1
1
0
0
0
−63
1
1
0
1
1
1
0
0
−66
1
1
1
0
0
0
0
0
−72
2004 Apr 22
38
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
VC2_7
VC1_7
VC2_6
VC1_6
VC2_5
VC1_5
VC2_4
VC1_4
VC2_3
VC1_3
VC2_2
VC1_2
VC2_1
VC1_1
VC2_0
VC1_0
VOLUME
(dB)
1
1
1
0
0
1
0
0
−∞
11.8
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
0
−∞
Mode, bass boost and treble
Table 38 Register address 12H
BIT
15
14
13
12
11
10
9
8
Symbol
M1
M0
TRL1
TRL0
BBL3
BBL2
BBL1
BBL0
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
TRR1
TRR0
BBR3
BBR2
BBR1
BBR0
Default
0
0
0
0
0
0
0
0
Table 39 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 and 14
M[1:0]
Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound
processing filters of bass boost and treble. Default value 00, see Table 40.
13 and 12
TRL[1:0]
Treble setting left. A 2-bit value to program the mode of the sound processing filter of
treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41.
11 to 8
BBL[3:0]
Bass boost setting left. A 4-bit value to program the bass boost setting, which can be set
for left and right independently. The used set depends on the bits M1 and M0. Default
value 0000, see Table 42.
7 and 6
−
default value 00
5 and 4
TRR[1:0]
Treble setting right. A 2-bit value to program the mode of the sound processing filter of
treble. Default value 00, see Table 41.
3 to 0
BBR[3:0]
Bass boost setting right. A 4-bit value to program the bass boost setting, which can be
set for left and right independently. The used set depends on the mode bits. Default
value 0000, see Table 42.
Table 40 Flat/minimum/maximum setting bits
M1
M0
Mode
0
0
flat (default)
0
1
minimum
1
0
minimum
1
1
maximum
2004 Apr 22
39
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 41 Treble setting bits
TRL1
TRR1
TRL0
TRR0
FLAT SET
(dB)
MINIMUM SET
(dB)
MAXIMUM
SET (dB)
0
0
0 (default)
0 (default)
0 (default)
0
1
0
2
2
1
0
0
4
4
1
1
0
6
6
Table 42 Bass boost setting bits
BBL3
BBR3
BBL2
BBR2
BBL1
BBR1
BBL0
BBR0
FLAT SET
(dB)
MINIMUM SET
(dB)
MAXIMUM
SET (dB)
0
0
0
0
0 (default)
0 (default)
0 (default)
0
0
0
1
0
2
2
0
0
1
0
0
4
4
0
0
1
1
0
6
6
0
1
0
0
0
8
8
0
1
0
1
0
10
10
0
1
1
0
0
12
12
0
1
1
1
0
14
14
1
0
0
0
0
16
16
1
0
0
1
0
18
18
1
0
1
0
0
18
20
1
0
1
1
0
18
22
1
1
0
0
0
18
24
1
1
0
1
0
18
24
1
1
1
0
0
18
24
1
1
1
1
0
18
24
2004 Apr 22
40
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
11.9
UDA1380
Master mute, channel de-emphasis and mute
Table 43 Register address 13H
BIT
15
14
13
12
11
10
9
8
Symbol
−
MTM
−
−
MT2
DE2_2
DE2_1
DE2_0
Default
0
1
0
0
1
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
−
−
MT1
DE1_2
DE1_1
DE1_0
Default
0
0
0
0
0
0
0
0
Table 44 Description of register bits
BIT
SYMBOL
DESCRIPTION
15
−
default value 0
14
MTM
Master mute. A 1-bit value to enable the digital mute for the master. When
this bit is logic 0: no soft mute of master. When this bit is logic 1: soft mute of
master. Default value 1.
−
default value 00
MT2
Channel 2 mute. A 1-bit value to enable the digital mute for channel 2. After
enabling the mixer, bit MT2 must be set to logic 0. When this bit is logic 0: no
soft mute of channel 2. When this bit is logic 1: soft mute of channel 2. Default
value 1 (meaning that channel 2 is always muted, even when the mixer is
enabled).
10 to 8
DE2_[2:0]
De-emphasis. A 3-bit value to enable the digital de-emphasis filter for
channel 2. Default value 000, see Table 45.
7 to 4
−
default value 0000
MT1
Channel 1 mute. A 1-bit value to enable the digital mute for channel 1. When
this bit is logic 0: no soft mute of channel 1. When this bit is logic 1: soft mute
of channel 1. Default value 0.
DE1_[2:0]
De-emphasis. A 3-bit value to enable the digital de-emphasis filter for
channel 1. Default value 000, see Table 45.
13 and 12
11
3
2 to 0
Table 45 De-emphasis selection bits
DE2_2
DE1_2
DE2_1
DE1_1
DE2_0
DE1_0
FUNCTION
0
0
0
off (default)
0
0
1
32 kHz
0
1
0
44.1 kHz
0
1
1
48 kHz
1
0
0
96 kHz
2004 Apr 22
41
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.10 Mixer, silence detector and oversampling settings
Table 46 Register address 14H
BIT
15
14
13
12
11
10
9
8
Symbol
DA_POL_INV
SEL_NS
MIX_POS
MIX
−
−
−
−
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
SILENCE
SDET_ON
SD_VALUE1
SD_VALUE0
−
−
OS1
OS0
Default
0
0
0
0
0
0
0
0
Table 47 Description of register bits
BIT
SYMBOL
DESCRIPTION
15
DA_POL_INV
DAC polarity control. A 1-bit value to control the signal polarity of the
DAC output signal. When this bit is logic 0: DAC output not inverted.
When this bit is logic 1: DAC output inverted. Default value 0.
14
SEL_NS
Noise shaper order select. A 1-bit value to select between the
3rd-order and the 5th-order noise shaper. When this bit is logic 0: select
3rd-order noise shaper. When this bit is logic 1: select 5th-order noise
shaper. Default value 0.
13
MIX_POS
12
MIX
Mixer signal control. A 2-bit value to select the digital mixer settings
inside the interpolation filter. Default value 0. By default the mixer is off,
see Table 48.
−
default value 0000
7
SILENCE
Silence mode. A 1-bit value to force the DAC output to silence. When
this bit is logic 0: no overruling. The setting of the FSDAC silence switch
depends on the status of the digital silence detector circuit and the
master_mute status. When this bit is logic 1: overruling. The FSDAC
silence switch is activated, independent of the status of the digital
silence detector circuit or the master_mute status. Default value 0.
6
SDET_ON
Silence detector enable. A 1-bit value to enable the digital silence
detector. When this bit is logic 0: silence detection circuit disabled.
When this bit is logic 1: silence detection circuit enabled. Default
value 0.
5 and 4
SD_VALUE[1:0]
Silence detector settings. A 2-bit value to program the silence
detector, the number of ‘ZERO’ samples counted before the silence
detector signals whether there has been digital silence. Default
value 00, see Table 49.
3 and 2
−
default value 00
1 and 0
OS[1:0]
Oversampling input settings. A 2-bit value to select the oversampling
input mode. Default value 00, see Table 50.
11 to 8
2004 Apr 22
42
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 48 Mixer signal control setting bits
MIX_POS
MIX
FUNCTION
0
0
no mixing; default
1
0
volume of channel 1 is forced to 0 dB and volume of channel 2 is forced to −∞ dB
0
1
mixing is done before the sound processing: input signals are automatically scaled by
6 dB in order to prevent clipping during adding; after the addition, the 6 dB scaling is
compensated
1
1
mixing is done after the sound processing: input signals are automatically scaled in
order to prevent clipping during adding
Table 49 Silence detector setting bits
SD_VALUE1 SD_VALUE0
FUNCTION
0
0
3200 samples; default
0
1
4800 samples
1
0
9600 samples
1
1
19200 samples
Table 50 Oversampling input setting bits
OS1
OS0
FUNCTION
0
0
single-speed input is normal input; mixing possible; default
0
1
double-speed input is after first half-band; no mixing possible
1
0
quad-speed input is in front of noise shaper; no mixing possible
1
1
reserved
11.11 Decimator volume control
Table 51 Register address 20H
BIT
15
14
13
12
11
10
9
8
Symbol
ML_DEC7
ML_DEC6
ML_DEC5
ML_DEC4
ML_DEC3
ML_DEC2
ML_DEC1
ML_DEC0
Default
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
BIT
Symbol
Default
MR_DEC7 MR_DEC6 MR_DEC5 MR_DEC4 MR_DEC3 MR_DEC2 MR_DEC1 MR_DEC0
0
0
0
0
0
0
0
0
Table 52 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 to 8
ML_DEC[7:0]
ADC volume control left. An 8-bit value to program the gain of the decimator for
left and right independently. The ranges are +24 to −63.5 dB and −∞ dB in steps
of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53.
7 to 0
MR_DEC[7:0]
ADC volume control right. An 8-bit value to program the gain of the decimator
for left and right independently. The ranges are +24 to −63.5 dB and −∞ dB in
steps of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53.
2004 Apr 22
43
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 53 ADC volume control setting bits
ML_DEC7 ML_DEC6 ML_DEC5 ML_DEC4 ML_DEC3 ML_DEC2 ML_DEC1 ML_DEC0
MR_DEC7 MR_DEC6 MR_DEC5 MR_DEC4 MR_DEC3 MR_DEC2 MR_DEC1 MR_DEC0
GAIN (dB)
0
0
1
1
0
0
0
0
24
0
0
1
0
1
1
1
1
23.5
0
0
1
0
1
1
1
0
23
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0.5
0
0
0
0
0
0
0
0
0 (default)
1
1
1
1
1
1
1
1
−0.5
:
:
:
:
:
:
:
:
:
1
0
0
0
0
1
0
0
−62
1
0
0
0
0
0
1
1
−62.5
1
0
0
0
0
0
1
0
−63
1
0
0
0
0
0
0
1
−63.5
1
0
0
0
0
0
0
0
−∞
11.12 PGA settings and mute
Table 54 Register address 21H
BIT
15
14
13
12
11
10
9
8
Symbol
MT_ADC
−
−
−
PGA_GAIN
CTRLR3
PGA_GAIN
CTRLR2
PGA_GAIN
CTRLR1
PGA_GAIN
CTRLR0
Default
1
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
−
−
PGA_GAIN
CTRLL3
PGA_GAIN
CTRLL2
PGA_GAIN
CTRLL1
PGA_GAIN
CTRLL0
Default
0
0
0
0
0
0
0
0
Table 55 Description of register bits
BIT
15
14 to 12
2004 Apr 22
SYMBOL
DESCRIPTION
MT_ADC
Decimator mute. A 1-bit value to enable the digital linear mute. When this bit is
logic 0: no muting. When this bit is logic 1: muting. Default value 1.
−
default value 000
44
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
BIT
UDA1380
SYMBOL
11 to 8
DESCRIPTION
PGA_GAIN
CTRLR[3:0]
ADC input amplifier right gain settings. A 4-bit value to program the gain of the
input amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of
3 dB. The gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
7 to 4
−
default value 0
3 to 0
PGA_GAIN
CTRLL[3:0]
ADC input amplifier left gain settings. A 4-bit value to program the gain of the input
amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB.
The gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
Table 56 ADC input amplifier PGA gain setting bits
PGA_GAINCTRLR3
PGA_GAINCTRLL3
PGA_GAINCTRLR2
PGA_GAINCTRLL2
PGA_GAINCTRLR1
PGA_GAINCTRLL1
PGA_GAINCTRLR0
PGA_GAINCTRLL0
PGA_GAIN (dB)
0
0
0
0
0 (default)
0
0
0
1
3
0
0
1
0
6
0
0
1
1
9
0
1
0
0
12
0
1
0
1
15
0
1
1
0
18
0
1
1
1
21
1
X
X
X
24
11.13 ADC settings
Table 57 Register address 22H
BIT
15
14
13
12
11
Symbol
−
−
−
Default
0
0
0
0
0
BIT
7
6
5
4
Symbol
−
−
−
Default
0
0
0
10
9
8
VGA_CTRL1
VGA_CTRL0
0
0
0
3
2
1
0
−
SEL_LNA
SEL_MIC
SKIP_DCFIL
EN_DCFIL
0
0
0
1
0
ADCPOL_ INV VGA_CTRL3 VGA_CTRL2
Table 58 Description of register bits
BIT
15 to 13
12
11 to 8
2004 Apr 22
SYMBOL
DESCRIPTION
−
default value 000
ADCPOL_INV
ADC polarity control. A 1-bit value to select ADC polarity. When this bit is logic 0:
polarity of ADC non-inverting. When this bit is logic 1: polarity of ADC inverting.
Default value 0.
VGA_CTRL[3:0] Microphone input VGA gain settings. A 4-bit value to program the gain of the LNA
in the microphone input channel. The range is 0 to 30 dB in steps of 2 dB.
Default value 0000, see Table 59.
45
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
BIT
UDA1380
SYMBOL
DESCRIPTION
−
default value 0000
3
SEL_LNA
Line input select. A 1-bit value to set the multiplexer in the analog front-end to select
between the LNA or the enable-in input for the left ADC. When this bit is logic 0: select
line input. When this bit is logic 1: select LNA for the left ADC. Default value 0.
2
SEL_MIC
Microphone input select. A 1-bit value to set the multiplexer at the ADC right
channel output (on bit-stream level) which selects either the right channel data or the
left channel data. In case only the microphone input is used, the microphone signal
can be applied to the decimator for both left and right. When this bit is logic 0: select
right channel ADC. When this bit is logic 1: select left channel ADC (for instance for
microphone input). Default value 0.
1
SKIP_DCFIL
DC filter bypass. A 1-bit value set to skip the DC filter which is just before the
decimator. This DC filter is there to compensate for the DC offset added in the ADC (to
remove idle tones from the audio band). This DC signal added (the DC dither) must
not be amplified in order to prevent clipping. Therefore this DC offset is removed first.
When this bit is logic 0: DC filter enabled. When this bit is logic 1: DC filter bypassed.
Default value 1.
0
EN_DCFIL
DC filter enable. A 1-bit value set to enable the DC filter which is at the output of the
decimator (running at 1fs). When this bit is logic 0: DC filter disabled. When this bit is
logic 1: DC filter enabled. Default value 0.
7 to 4
Table 59 Microphone input VGA gain setting bits
VGA_CTRL3
VGA_CTRL2
VGA_CTRL1
VGA_CTRL0
LNA GAIN (dB)
0
0
0
0
0 (default)
0
0
0
1
2
0
0
1
0
4
0
0
1
1
6
0
1
0
0
8
0
1
0
1
10
0
1
1
0
12
0
1
1
1
14
1
0
0
0
16
1
0
0
1
18
1
0
1
0
20
1
0
1
1
22
1
1
0
0
24
1
1
0
1
26
1
1
1
0
28
1
1
1
1
30
2004 Apr 22
46
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.14 AGC settings
Table 60 Register address 23H
BIT
15
14
13
12
11
10
9
8
Symbol
−
−
−
−
−
AGC_TIME2
AGC_TIME1
AGC_TIME0
Default
0
0
0
0
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
−
−
AGC_LEVEL1
AGC_LEVEL0
−
AGC_EN
Default
0
0
0
0
0
0
0
0
Table 61 Description of register bits
BIT
SYMBOL
DESCRIPTION
15 to 11
−
Default value 00000.
10 to 8
AGC_TIME[2:0]
AGC time constant settings. A 3-bit value to set the AGC time constants, being the
attack and decay time constants. The given constants are for 44.1 and 8 kHz
sampling frequencies, and must be scaled either down or up according to the
sampling frequency used. Default value 000, see Table 62.
7 to 4
−
default value 0000
AGC_LEVEL[1:0]
AGC target level settings. A 2-bit value to set the AGC target level.
Default value 00, see Table 63.
1
−
default value 0
0
AGC_EN
AGC enable control. A 1-bit value to enable or disable the AGC. When the AGC is
enabled, the bit SKIP_DCFIL must be set to logic 0 to avoid disturbance on the
output signal due to the DC offset added in the ADC. When this bit is logic 0: AGC off,
manual gain control via the left and right decimator volume control. When this bit is
logic 1: AGC enabled, with manual microphone gain setting via VGA. Default value 0.
3 and 2
Table 62 AGC time constant setting bits
AGC SETTING
AGC_TIME2
AGC_TIME1
AGC_TIME0
44.1 kHz SAMPLING
8 kHz SAMPLING
ATTACK TIME
(ms)
DECAY TIME
(ms)
ATTACK TIME
(ms)
DECAY TIME
(ms)
551 (default)
0
0
0
11
100
61
0
0
1
16
100
88.2
551
0
1
0
11
200
61
1102
0
1
1
16
200
88.2
1102
1
0
0
21
200
116
1102
1
0
1
11
400
61
2205
1
1
0
16
400
88.2
2205
1
1
1
21
400
116
2205
2004 Apr 22
47
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 63 AGC target level setting bits
AGC_LEVEL1
AGC_LEVEL0
AGC TARGET LEVEL VALUE (dBFS)
0
0
−5.5 (default)
0
1
−8
1
0
−11.5
1
1
−14
11.15 Restore L3 default values (software reset)
Table 64 Register address 7FH
BIT
15
14
13
12
11
10
9
8
Default value
−
−
−
−
−
−
−
−
BIT
7
6
5
4
3
2
1
0
Default value
−
−
−
−
−
−
−
−
11.16 Headphone driver and interpolation filter (read-out)
Table 65 Register address 18H
BIT
Symbol
BIT
Symbol
15
14
13
12
11
10
9
8
−
−
−
−
−
HP_STCTV
HP_STCTL
HP_STCTR
7
6
5
4
3
2
1
0
−
SDETR2
SDETL2
SDETR1
SDETL1
MUTE_
STATE_M
MUTE_
STATE_CH2
MUTE_
STATE_CH1
Table 66 Description of register bits
BIT
SYMBOL
DESCRIPTION
−
not used
10
HP_STCTV
Headphone driver short-circuit detection. When this bit is logic 0:
headphone driver is not short-circuit protected. When this bit is logic 1:
headphone driver short-circuit protection is activated.
9
HP_STCTL
Left headphone driver short-circuit detection. When this bit is logic 0: left
channel headphone driver is not short-circuit protected. When this bit is
logic 1: left channel headphone driver short-circuit protection is activated.
8
HP_STCTR
Right headphone driver short-circuit detection. When this bit is logic 0:
right channel headphone driver not short-circuit protected. When this bit is
logic 1: right channel headphone driver short-circuit protection activated.
7
−
not used
6
SDETR2
Interpolator silence detect channel 2 right. When this bit is logic 0:
interpolator on channel 2 right input has detected no silence. When this bit is
logic 1: interpolator on channel 2 right input has detected silence.
5
SDETL2
Interpolator silence detect channel 2 left. When this bit is logic 0:
interpolator on channel 2 left input has detected no silence. When this bit is
logic 1: interpolator on channel 2 left input has detected silence.
15 to 11
2004 Apr 22
48
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
BIT
UDA1380
SYMBOL
DESCRIPTION
4
SDETR1
Interpolator silence detect channel 1 right. When this bit is logic 0:
interpolator on channel 1 right input has detected no silence. When this bit is
logic 1: interpolator on channel 1 right input has detected silence.
3
SDETL1
Interpolator silence detect channel 1 left. When this bit is logic 0:
interpolator on channel 1 left input has detected no silence. When this bit is
logic 1: interpolator on channel 1 left input has detected silence.
2
MUTE_STATE_M
Interpolator muting. A 1-bit value which signals whether the interpolator has
reached mute or not. When this bit is logic 0: interpolator is not muted. When
this bit is logic 1: interpolator is muted.
1
MUTE_STATE_CH2
Interpolator muting channel 2. When this bit is logic 0: interpolator channel 2
is not muted. When this bit is logic 1: interpolator channel 2 is muted.
0
MUTE_STATE_CH1
Interpolator muting channel 1. When this bit is logic 0: interpolator channel 1
is not muted. When this bit is logic 1: interpolator channel 1 is muted.
11.17 Decimator read-out
Table 67 Register address 28H
BIT
Symbol
BIT
Symbol
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
7
6
5
4
3
2
1
0
−
−
−
AGC_STAT
−
MT_ADC_STAT
−
OVERFLOW
Table 68 Description of register bits
BIT
SYMBOL
DESCRIPTION
−
not used
4
AGC_STAT
AGC gain status. A 1-bit value which signals whether the AGC gain exceeds
8 dB or not. Only valid when the AGC is switched on. When this bit is logic 0:
AGC gain <8 dB. When this bit is logic 1: AGC gain ≥8 dB.
3
−
not used
2
MT_ADC_STAT
Decimator mute. A 1-bit value which signals whether the decimator has
reached mute or not. When this bit is logic 0: decimator has not muted. When
this bit is logic 1: decimator has muted.
1
−
not used
0
OVERFLOW
Digital output overflow detection. A 1-bit value which signals whether the
digital output amplitude exceeds −1.16 dB or not. When this bit is logic 0: no
overflow detected (read-out). When this bit is logic 1: overflow detected
(read-out).
15 to 5
2004 Apr 22
49
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
12 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
4
V
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
note 2
−2000
+2000
V
note 3
−200
+200
V
−
100
mA
output short-circuited to VSSA(DA)
−
450
mA
output short-circuited to VDDA(DA)
−
325
mA
VDD
supply voltage
Txtal(max)
note 1
Ilu(prot)
latch-up protection current
Tamb = 125 °C; VDD = 3.6 V
Isc(DAC)
short-circuit current of DAC
Tamb = 0 °C; VDD = 3 V; note 4
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor via a 0.75 μH series inductor.
4. DAC operation after short-circuiting cannot be warranted.
13 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
advised to take normal precautions appropriate to handling MOS devices.
14 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
UNIT
in free air
TSSOP32 package
115
K/W
HVQFN32 package
35
K/W
15 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611D”.
2004 Apr 22
VALUE
50
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
16 DC CHARACTERISTICS
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies; note 1
VDDA(AD)
ADC analog supply voltage
VDDA(DA)
DAC analog supply voltage
VDDA(HP)
headphone analog supply
voltage
VDDD
IDDA(AD)
IDDA(DA)
IDDA(HP)
IDDD
IDD(tot)
2004 Apr 22
2.4
3.0
3.6
V
2.4
3.0
3.6
V
2.4
3.0
3.6
V
digital supply voltage
2.4
3.0
3.6
V
ADC analog supply current one ADC and microphone
amplifier enabled; fs = 48 kHz
−
4.5
−
mA
two ADCs and PGA enabled;
fs = 48 kHz
−
7.0
−
mA
all ADCs and PGAs power-down,
but AVC activated; fs = 48 kHz
−
3.3
−
mA
all ADCs, PGAs and LNA
power-down; fs = 48 kHz
−
1.0
−
μA
−
3.4
−
mA
Power-down mode; fs = 48 kHz
−
0.1
−
μA
no signal applied (quiescent
current)
−
0.9
−
mA
Power-down mode
−
0.1
−
μA
operating mode; fs = 48 kHz
−
10.0
−
mA
note 2
DAC analog supply current operating mode; fs = 48 kHz
headphone analog supply
current
digital supply current
total supply current
playback mode; fs = 48 kHz
−
5.0
−
mA
record mode; fs = 48 kHz
−
6.0
−
mA
Power-down mode; fs = 48 kHz
−
1.0
−
μA
playback mode
(without headphone); fs = 48 kHz
−
8
−
mA
playback mode (with headphone);
no signal; fs = 48 kHz
−
9
−
mA
record mode (audio); fs = 48 kHz
−
13
−
mA
record mode (speech);
fs = 48 kHz
−
10
−
mA
record mode (audio and speech);
fs = 48 kHz
−
13
−
mA
fully operating; fs = 48 kHz
−
23
−
mA
signal mix-in operating, using
FSDAC, AVC (with headphone);
no signal; fs = 48 kHz
−
12
−
mA
Power-down mode; fs = 48 kHz
−
2
−
μA
51
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
SYMBOL
PARAMETER
UDA1380
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pins (5 V tolerant TTL compatible)
VIH
HIGH-level input voltage
2.0
−
5.5
V
VIL
LOW-level input voltage
−0.5
−
+0.8
V
⎪ILI⎪
input leakage current
−
−
1
μA
Ci
input capacitance
−
−
10
pF
Digital output pins
VOH
HIGH-level output voltage
IOH = −2 mA
0.85VDDD −
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
0.4
V
−
Reference voltage
VREF
reference voltage
Ro(VREF)
output resistance on
pin VREF
with respect to VSSA(AD); note 3
0.45VDDA 0.5VDDA
0.55VDDA V
−
12.5
−
kΩ
Analog-to-digital converter
VADCP
positive reference voltage
of the ADC
−
VDDA(AD)
−
V
VADCN
negative reference voltage
of the ADC
−
0
−
V
Ri
input resistance
−
12
−
kΩ
Ci
input capacitance
−
24
−
pF
3
−
−
kΩ
−
−
50
pF
playback mode
(without headphone)
−
24
−
mW
playback mode (with headphone)
−
27
−
mW
record mode (audio)
−
39
−
mW
record mode (speech)
−
30
−
mW
record mode (audio and speech)
−
40
−
mW
full operation
−
69
−
mW
Power-down mode
−
6
−
μW
Digital-to-analog converter
RL
load resistance
CL
load capacitance
note 4
Power consumption (supply voltage 3.0 V; fs = 48 kHz)
Ptot
total power dissipation
Notes
1. All supply connections must be made to the same power supply unit.
2. When the supply voltages are below 2.7 V and the headphone load impedance is 16 Ω, it is recommended to limit
the DAC and the headphone output to less than -2 dB, otherwise clipping may occur.
3. VDDA = VDDA(DA) = VDDA(AD).
4. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in
order to prevent oscillations in the output operational amplifier.
2004 Apr 22
52
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
17 AC CHARACTERISTICS
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; fi = 1 kHz at −1 dB; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with
respect to ground; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital converter
Do
digital output level
ΔVi
unbalance between channels
(THD + N)/S48
total harmonic
distortion-plus-noise to signal at
fs = 48 kHz
0 dB setting; Vi(rms) = 1.0 V
−1.5
−1
−0.5
dBFS
3 dB setting; Vi(rms) = 708 mV
−1.5
−1
−0.5
dBFS
6 dB setting; Vi(rms) = 501 mV
−1.5
−1
−0.5
dBFS
9 dB setting; Vi(rms) = 354 mV
−1.5
−1
−0.5
dBFS
12 dB setting; Vi(rms) = 252 mV
−1.5
−1
−0.5
dBFS
15 dB setting; Vi(rms) = 178 mV
−1.5
−1
−0.5
dBFS
18 dB setting; Vi(rms) = 125 mV
−1.5
−1
−0.5
dBFS
21 dB setting; Vi(rms) = 89 mV
−1.5
−1
−0.5
dBFS
24 dB setting; Vi(rms) = 63 mV
−1.5
−1
−0.5
dBFS
−
<0.1
−
dB
0 dB setting
−
−85
−80
dB
3 dB setting
−
−85
−
dB
6 dB setting
−
−85
−
dB
9 dB setting
−
−85
−
dB
12 dB setting
−
−84
−
dB
15 dB setting
−
−83
−
dB
18 dB setting
−
−82
−
dB
21 dB setting
−
−80
−
dB
24 dB setting
−
−78
−
dB
0 dB setting
−
−37
−32
dB
3 dB setting
−
−36
−
dB
6 dB setting
−
−36
−
dB
9 dB setting
−
−36
−
dB
12 dB setting
−
−35
−
dB
15 dB setting
−
−34
−
dB
18 dB setting
−
−33
−
dB
21 dB setting
−
−32
−
dB
24 dB setting
−
−30
−
dB
92
97
−
dB
−
100
−
dB
−
80
−
dB
at −1 dBFS
at −60 dBFS; A-weighted
S/N48
signal-to-noise ratio at
fs = 48 kHz
αcs
channel separation
PSRR
power supply rejection ratio
2004 Apr 22
Vi = 0 V; A-weighted
fripple = 1 kHz;
Vripple = 30 mV (p-p)
53
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
SYMBOL
UDA1380
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LNA input plus analog-to-digital converter
Vi(rms)
input voltage (RMS value)
at 0 dBFS digital output; 2.2 kΩ
source impedance
−
−
35
mV
(THD+N)/S48
total harmonic
distortion-plus-noise to signal
ratio at fs = 48 kHz
at 0 dB
−
−74
−
dB
at −60 dB; A-weighted
−
−25
−
dB
S/N48
signal-to-noise ratio at
fs = 48 kHz
Vi = 0 V; A-weighted
−
85
−
dB
αcs
channel separation
−
70
−
dB
−
0.9
−
V
−
<0.1
−
dB
Digital-to-analog converter
Vo(rms)
output voltage (RMS value)
ΔVo
unbalance between channels
(THD+N)/S48
total harmonic
distortion-plus-noise to signal
ratio at fs = 48 kHz
at 0 dB
−
−85
−80
dB
at −60 dB; A-weighted
−
−40
−35
dB
total harmonic
distortion-plus-noise to signal
ratio at fs = 96 kHz
at 0 dB
−
−80
−75
dB
at −60 dB; A-weighted
−
−37
−32
dB
S/N48
signal-to-noise ratio at
fs = 48 kHz
code = 0; A-weighted
95
100
−
dB
S/N96
signal-to-noise ratio at
fs = 96 kHz
code = 0; A-weighted
92
97
−
dB
αcs
channel separation
−
90
−
dB
PSRR
power supply rejection ratio
fripple = 1 kHz;
Vripple = 30 mV (p-p)
−
60
−
dB
(THD+N)/S96
at 0 dBFS digital input; note 1
Headphone driver
Po(rms)
output power (RMS value)
at 0 dBFS digital input,
assuming RL = 16 Ω
30
35
40
mW
(THD+N)/S48
total harmonic
distortion-plus-noise to signal
ratio at fs = 48 kHz
at 0 dB; RL = 16 Ω; note 2
−
−60
−52
dB
at 0 dB; RL = 5 kΩ
−
−82
−77
dB
at −60 dB; A-weighted
−
−33
−27
dB
channel separation
RL = 16 Ω using pin VREF(HP);
no DC decoupling capacitors;
note 3
55
60
−
dB
RL = 16 Ω single-ended
application with DC decoupling
capacitors (100 μF typical)
63
68
−
dB
RL = 32 Ω single-ended
application with DC decoupling
capacitors (100 μF typical)
69
74
−
dB
code = 0; A-weighted
87
93
−
dB
αcs
S/N48
2004 Apr 22
signal-to-noise ratio at
fs = 48 kHz
54
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
SYMBOL
UDA1380
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AVC (line input via ADC input, output on line output and headphone driver)
Vi(rms)
input voltage (RMS value)
−
150
−
mV
(THD+N)/S48
total harmonic
distortion-plus-noise to signal
ratio at fs = 48 kHz
at 0 dB
−
−80
−
dB
at −60 dB; A-weighted
−
−28
−
dB
S/N48
signal-to-noise ratio at
fs = 48 kHz
Vi = 0 V; A-weighted
−
87
−
dB
αcs
channel separation
−
82
−
dB
Notes
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
2. When the supply voltages are below 2.7 V and the headphone load impedance is 16 Ω, it is recommended to limit
the DAC and the headphone output to less than -2 dB, otherwise clipping may occur.
3. Channel separation performance is measured at the IC pin.
2004 Apr 22
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18 TIMING
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages referenced to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing; note 1
Tsys
tCWL
tCWH
system clock cycle time
system clock LOW time
system clock HIGH time
fsys = 256fs
35
81
250
ns
fsys = 384fs
23
54
170
ns
fsys = 512fs
17
41
130
ns
fsys = 768fs
17
27
90
ns
fsys < 19.2 MHz
0.3Tsys
−
0.7Tsys
ns
fsys ≥ 19.2 MHz
0.4Tsys
−
0.6Tsys
ns
fsys < 19.2 MHz
0.3Tsys
−
0.7Tsys
ns
fsys ≥ 19.2 MHz
0.4Tsys
−
0.6Tsys
ns
−
−
128fs
Hz
s
Serial interface input/output data timing (see Fig.17)
fBCK
bit clock frequency
Tcy(BCK)
bit clock cycle time
−
−
(2)
1⁄
128Tcy(s)
tBCKH
bit clock HIGH time
30
−
−
ns
tBCKL
bit clock LOW time
30
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tsu(WS)
word select set-up time
10
−
−
ns
th(WS)
word select hold time
10
−
−
ns
tsu(DATAI)
data input set-up time
10
−
−
ns
th(DATAI)
data input hold time
10
−
−
ns
th(DATAO)
data output hold time
0
−
−
ns
td(DATAO-BCK)
data output to bit clock delay
−
−
30
ns
td(DATAO-WS)
data output to word select delay
−
−
30
ns
L3-bus interface timing (see Figs 18 and 19)
tr
rise time
note 3
−
−
10
ns/V
tf
fall time
note 3
−
−
10
ns/V
Tcy(CLK)L3
L3CLOCK cycle time
note 4
500
−
−
ns
tCLK(L3)H
L3CLOCK HIGH time
note 4
250
−
−
ns
tCLK(L3)L
L3CLOCK LOW time
note 4
250
−
−
ns
tsu(L3)A
L3MODE set-up time in address
mode
190
−
−
ns
th(L3)A
L3MODE hold time in address
mode
190
−
−
ns
tsu(L3)D
L3MODE set-up time in data
transfer mode
190
−
−
ns
th(L3)D
L3MODE hold time in data transfer
mode
190
−
−
ns
2004 Apr 22
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SYMBOL
UDA1380
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tstp(L3)
L3MODE stop time in data transfer
mode
190
−
−
ns
tsu(L3)DA
L3DATA set-up time in address and
data transfer mode
190
−
−
ns
th(L3)DA
L3DATA hold time in address and
data transfer mode
30
−
−
ns
td(L3)R
L3DATA delay time in data transfer
mode
0
−
50
ns
tdis(L3)R
L3DATA disable time for read data
0
−
50
ns
I2C-bus
interface timing; see Fig.20
fSCL
SCL clock frequency
0
−
400
kHz
tLOW
SCL LOW time
1.3
−
−
μs
tHIGH
SCL HIGH time
0.6
−
−
μs
tr
rise time SDA and SCL
note 5
20 + 0.1Cb
−
300
ns
tf
fall time SDA and SCL
note 5
20 + 0.1Cb
−
300
ns
tHD;STA
hold time START condition
note 6
0.6
−
−
μs
tSU;STA
set-up time repeated START
0.6
−
−
μs
tSU;STO
set-up time STOP condition
0.6
−
−
μs
tBUF
bus free time between a STOP and
START condition
1.3
−
−
μs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
μs
tSP
pulse width of spikes
0
−
50
ns
Cb
capacitive load for each bus line
−
−
400
pF
note 7
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency (see Fig.16).
2. Tcy(s) is the cycle time of the sample frequency.
3. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
short as possible.
4. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1⁄64fs cycle.
5. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
6. After this period, the first clock pulse is generated.
7. To be suppressed by the input filter.
2004 Apr 22
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UDA1380
t CWH
handbook, full pagewidth
MGR984
t CWL
Tsys
Fig.16 Timing of system clock.
handbook, full pagewidth
WS
tr
t BCKH
t d(DATAO-BCK)
t h(WS)
tf
t su(WS)
BCK
t BCKL
Tcy(BCK)
t d(DATAO-WS)
t h(DATAO)
DATAO
t su(DATAI)
t h(DATAI)
DATAI
MGS756
Fig.17 Serial interface input data timing.
2004 Apr 22
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UDA1380
handbook, full pagewidth
L3MODE
tsu(L3)A
th(L3)A
tsu(L3)A
tCLK(L3)L
tCLK(L3)H
th(L3)A
L3CLOCK
Tcy(CLK)(L3)
tsu(L3)DA
th(L3)DA
BIT 0
L3DATA
BIT 7
MGL723
Fig.18 Timing of address mode.
tstp(L3)
handbook, full pagewidth
L3MODE
tCLK(L3)L
th(L3)D
Tcy(CLK)L3
tCLK(L3)H
tsu(L3)D
L3CLOCK
tsu(L3)DA
th(L3)DA
L3DATA
write
BIT 7
BIT 0
L3DATA
read
td(L3)R
tdis(L3)R
MGU015
Fig.19 Timing of data transfer mode for write and read.
2004 Apr 22
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SDA
t BUF
t LOW
tr
tf
t HD;STA
t SP
60
SCL
S
t HD;DAT
t HIGH
t SU;DAT
t SU;STA
MBC611
P
Product specification
Fig.20 Timing of the I2C-bus transfer.
t SU;STO
Sr
UDA1380
handbook, full pagewidth
t HD;STA
P
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19 APPLICATION INFORMATION
BLM31A601S
handbook, full pagewidth
+3 V
VDDA
VDDA
BLM31A601S
VDDD
100 μF
(16 V)
ground
left
input
4.7 μF
(16 V)
100 μF
(16 V)
100 nF
(63 V)
100 nF
(63 V)
100 μF
(16 V)
VADCP
2 (30)
VINL
VDDD
100 Ω
100 μF
(16 V)
VADCN
47 μF
VDDA
4 (32)
47 kΩ
VDDA(HP)
VSSA(HP)
20 (16)
RESET
5 (1)
24 (20)
(23) 27
31 (27)
47 μF
(16 V)
(16 V)
right
input
47 μF
VINR
microphone
input
(21) 25
VINM
L3DATA/SDA
L3MODE
system
clock
100 Ω
47 μF
(16 V)
3 (31)
SYSCLK
47 Ω
right
output
10 kΩ
18 (14)
(5) 9
17 (13)
UDA1380TT
(UDA1380HN)
16 (12)
(4) 8
(3) 7
SEL_L3_IIC
10 kΩ
VOUTR
(16 V)
L3CLOCK/SCL
left
output
1 (29)
(16 V)
47 μF
100 Ω
VOUTL
DATAO
WSO
BCKO
19 (15)
(18) 22
13 (9)
VREF(HP)
VOUTLHP
DATAI
WSI
BCKI
RTCB
(19) 23
12 (8)
11 (7)
(17) 21
0Ω
VOUTRHP
15 (11)
30 (26)
(25) 29
32 (28)
VSSA(AD)
14 (10)
VDDA(AD)
6 (2)
VSSD
28 (24)
VDDD
VREF
26 (22)
VSSA(DA)
headphone
0Ω
10 (6)
VDDA(DA)
100 nF
(63 V)
10 μF
(16 V)
MGU537
100 nF
(63 V)
100 nF
(63 V)
100 μF
(16 V)
100 μF
(16 V)
1Ω
10 Ω
VDDA
VDDD
Pin numbers for UDA1380HN in parentheses.
Fig.21 Application diagram.
2004 Apr 22
61
1Ω
VDDA
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20 PACKAGE OUTLINES
TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm;
lead pitch 0.65 mm
SOT487-1
E
D
A
X
c
y
HE
v M A
Z
17
32
A2
(A 3)
A
A1
pin 1 index
θ
Lp
L
1
detail X
16
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.30
0.19
0.20
0.09
11.1
10.9
6.2
6.0
0.65
8.3
7.9
1
0.75
0.50
0.2
0.1
0.1
0.78
0.48
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT487-1
2004 Apr 22
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
62
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HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT617-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
1/2
e b
9
y
y1 C
v M C A B
w M C
16
L
17
8
e
e2
Eh
1/2
1
terminal 1
index area
e
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
2004 Apr 22
63
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
NXP Semiconductors
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21 SOLDERING
21.1
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
21.2
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
The footprint must incorporate solder thieves at the
downstream end.
– for all BGA, HTSSON-T and SSOP-T packages
21.4
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a volume
≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
21.3
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Apr 22
Manual soldering
64
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21.5
UDA1380
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
not
recommended(5)(6)
SSOP, TSSOP, VSO, VSSOP
not
recommended(7)
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not suitable
LQFP, QFP, TQFP
suitable
suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your NXP Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Apr 22
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22 DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
23 DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2004 Apr 22
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Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2004 Apr 22
24 TRADEMARKS
I2C-bus ⎯ logo is a trademark of NXP B.V.
67
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors. No changes were
made to the content, except for the legal definitions and disclaimers.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R30/04/pp68
Date of release: 2004 Apr 22
Document order number:
9397 750 13108
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