Touch 8-Bit Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Revision: V1.40 Date: ������������ May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description ......................................................................................... 7 Selection Table.................................................................................................. 7 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 8 Pin Descriptions............................................................................................. 12 Absolute Maximum Ratings........................................................................... 19 D.C. Characteristics........................................................................................ 19 A.C. Characteristics........................................................................................ 21 Sensor Oscillator Electrical Characteristics................................................ 22 Power-on Reset Characteristics.................................................................... 25 System Architecture....................................................................................... 26 Clocking and Pipelining.......................................................................................................... 26 Program Counter.................................................................................................................... 27 Stack...................................................................................................................................... 28 Arithmetic and Logic Unit – ALU............................................................................................ 28 Flash Program Memory.................................................................................. 29 Structure................................................................................................................................. 29 Special Vectors...................................................................................................................... 30 Look-up Table......................................................................................................................... 30 Table Program Example......................................................................................................... 30 In Circuit Programming – ICP................................................................................................ 31 On-Chip Debug Support – OCDS.......................................................................................... 32 RAM Data Memory.......................................................................................... 33 Structure................................................................................................................................. 33 Special Function Register Description......................................................... 37 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 37 Memory Pointers – MP0, MP1............................................................................................... 37 Bank Pointer – BP.................................................................................................................. 38 Accumulator – ACC................................................................................................................ 39 Program Counter Low Register – PCL................................................................................... 39 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 39 Status Register – STATUS..................................................................................................... 40 EEPROM Data Memory................................................................................... 42 EEPROM Data Memory Structure......................................................................................... 42 EEPROM Registers............................................................................................................... 42 Reading Data from the EEPROM ......................................................................................... 44 Rev. 1.40 2 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Writing Data to the EEPROM................................................................................................. 44 Write Protection...................................................................................................................... 44 EEPROM Interrupt................................................................................................................. 44 Programming Considerations................................................................................................. 45 Oscillator......................................................................................................... 46 Oscillator Overview................................................................................................................ 46 System Clock Configurations................................................................................................. 46 Internal RC Oscillator – HIRC................................................................................................ 47 Internal 32kHz Oscillator – LIRC............................................................................................ 47 External 32.768kHz Crystal Oscillator – LXT......................................................................... 48 LXT Oscillator Low Power Function ...................................................................................... 49 Operating Modes and System Clocks.......................................................... 49 System Clocks....................................................................................................................... 49 System Operation Modes....................................................................................................... 51 Control Register..................................................................................................................... 52 Operating Mode Switching .................................................................................................... 54 NORMAL Mode to SLOW Mode Switching............................................................................ 54 SLOW Mode to NORMAL Mode Switching ........................................................................... 55 Entering the SLEEP Mode..................................................................................................... 55 Entering the IDLE0 Mode....................................................................................................... 56 Entering the IDLE1 Mode....................................................................................................... 56 Standby Current Considerations............................................................................................ 56 Wake-up................................................................................................................................. 57 Programming Considerations................................................................................................. 57 Watchdog Timer.............................................................................................. 58 Watchdog Timer Clock Source............................................................................................... 58 Watchdog Timer Control Register.......................................................................................... 58 Watchdog Timer Operation.................................................................................................... 59 Reset and Initialisation................................................................................... 60 Reset Functions..................................................................................................................... 60 Reset Initial Conditions.......................................................................................................... 62 Input/Output Ports.......................................................................................... 66 I/O Register List..................................................................................................................... 66 Pull-high Resistors................................................................................................................. 67 Port A Wake-up...................................................................................................................... 67 I/O Port Control Registers...................................................................................................... 67 I/O Pin Structures................................................................................................................... 67 Source Current Selection....................................................................................................... 68 Programming Considerations................................................................................................. 69 Timer Modules – TM....................................................................................... 70 Introduction............................................................................................................................ 70 TM Operation......................................................................................................................... 70 TM Clock Source.................................................................................................................... 70 TM Interrupts.......................................................................................................................... 71 Rev. 1.40 3 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver TM External Pins.................................................................................................................... 71 TM Input/Output Pin Control Register.................................................................................... 71 Programming Considerations................................................................................................. 74 Compact Type TM – CTM0............................................................................. 75 Compact TM Operation.......................................................................................................... 75 Compact Type TM Register Description................................................................................ 76 Compact Type TM Operating Modes..................................................................................... 80 Compare Match Output Mode................................................................................................ 80 Timer/Counter Mode.............................................................................................................. 83 PWM Output Mode................................................................................................................. 83 Periodic Type TM – PTM0............................................................................... 86 Periodic TM Operation........................................................................................................... 86 Periodic Type TM Register Description.................................................................................. 87 Periodic Type TM Operating Modes....................................................................................... 91 Compare Match Output Mode................................................................................................ 91 Timer/Counter Mode.............................................................................................................. 94 PWM Output Mode................................................................................................................. 94 Single Pulse Mode................................................................................................................. 96 Capture Input Mode............................................................................................................... 98 Touch Key Function..................................................................................... 100 Touch Key Structure............................................................................................................. 100 Touch Key Register Definition.............................................................................................. 100 Touch Key Operation............................................................................................................ 105 Touch Key Interrupt.............................................................................................................. 108 Programming Considerations............................................................................................... 108 I C Interface .................................................................................................. 109 2 I2C Interface Operation ........................................................................................................ 109 I2C Registers.........................................................................................................................110 I2C Bus Communication .......................................................................................................114 I2C Bus Start Signal ..............................................................................................................114 Slave Address ......................................................................................................................115 I2C Bus Read/Write Signal ...................................................................................................115 I2C Bus Slave Address Acknowledge Signal ........................................................................115 I2C Bus Data and Acknowledge Signal ................................................................................115 UART Interface ..............................................................................................118 UART External Pin Interfacing..............................................................................................118 UART Data Transfer Scheme...............................................................................................119 UART Status and Control Registers.....................................................................................119 Baud Rate Generator........................................................................................................... 125 Calculating the Baud Rate and Error Values........................................................................ 126 UART Setup and Control..................................................................................................... 126 UART Transmitter................................................................................................................ 128 UART Receiver.................................................................................................................... 129 Managing Receiver Errors................................................................................................... 130 Rev. 1.40 4 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UART Module Interrupt Structure......................................................................................... 131 Address Detect Mode........................................................................................................... 132 UART Power Down and Wake-up........................................................................................ 133 Interrupts....................................................................................................... 134 Interrupt Registers................................................................................................................ 134 Interrupt Operation............................................................................................................... 137 External Interrupt.................................................................................................................. 138 Time Base Interrupts............................................................................................................ 139 TM Interrupts........................................................................................................................ 140 EEPROM Interrupt............................................................................................................... 140 LVD Interrupt........................................................................................................................ 141 Touch Key Interrupt.............................................................................................................. 141 I2C Interrupt.......................................................................................................................... 141 UART Interrupt.................................................................................................................... 141 Interrupt Wake-up Function.................................................................................................. 142 Programming Considerations............................................................................................... 142 SCOM and SSEG Function for LCD............................................................ 143 LCD Operation..................................................................................................................... 143 LCD Bias Control................................................................................................................. 145 Low Voltage Detector – LVD........................................................................ 147 LVD Register........................................................................................................................ 147 LVD Operation...................................................................................................................... 148 Configuration Options.................................................................................. 149 Application Circuit........................................................................................ 149 Instruction Set............................................................................................... 150 Introduction.......................................................................................................................... 150 Instruction Timing................................................................................................................. 150 Moving and Transferring Data.............................................................................................. 150 Arithmetic Operations........................................................................................................... 150 Logical and Rotate Operation.............................................................................................. 151 Branches and Control Transfer............................................................................................ 151 Bit Operations...................................................................................................................... 151 Table Read Operations........................................................................................................ 151 Other Operations.................................................................................................................. 151 Instruction Set Summary............................................................................. 152 Table Conventions................................................................................................................ 152 Instruction Definition.................................................................................... 154 Package Information.................................................................................... 163 20-pin SOP (300mil) Outline Dimensions............................................................................ 164 24-pin SOP(300mil) Outline Dimensions............................................................................. 165 SAW Type 24-pin (4mm×4mm) QFN Outline Dimensions................................................... 166 28-pin SOP (300mil) Outline Dimensions............................................................................ 167 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 168 SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions................................................... 169 Rev. 1.40 5 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Features CPU Features • Operating voltage ♦♦ fSYS = 8MHz: VLVR~5.5V ♦♦ fSYS = 12MHz: 2.7V~5.5V ♦♦ fSYS = 16MHz: 4.5V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Three Oscillators ♦♦ High Speed Internal RC -- HIRC: 8/12/16MHz ♦♦ Low Speed Internal RC -- LIRC: 32kHz ♦♦ Low speed External Crystal -- LXT: 32768Hz (only for BS82C16A-3 and BS82D20A-3) • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 2K×16 ~ 8K×16 • RAM Data Memory: 384×8 ~ 768×8 • EEPROM Memory: 64×8 • Fully integrated 12/16/20 touch key functions -- require no external components • Watchdog Timer function • Up to 26 bidirectional I/O lines • PMOS Source Current Adjustable • Software controlled 4-SCOM lines LCD driver with 1/3 bias • One external interrupt line shared with I/O pin • Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function • Dual Time-Base functions for generation of fixed time interrupt signals • I2C Interface Module • UART Interface • Low voltage reset function • Low voltage detect function • Package:20/24/28-pinSOP,24/32-pin QFN, 28-pinSSOP Rev. 1.40 6 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver General Description These devices are a series of Flash Memory type 8-bit high performance RISC architecture microcontrollers with fully integrated touch key functions. With all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, these devices has all the features to offer designers a reliable and easy means of implementing Touch Keyes within their products applications. The touch key functions are fully integrated completely eliminating the need for external components. In addition to the flash program memory, other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HIRC, LIRC and LXT oscillators are provided including a fully intefrated system oscillator which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the fully integrated I2C interface functions, while the inclusion of flexible I/O programming features, Timer Modules and many other features further enhance device functionality and flexibility. The UART module is contained in these devices. It can support the applications such as data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, etc. These touch key devices will find excellent use in a huge range of modern Touch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. Selection Table Most features are common to these devices, the main features distinguishing them are Memory capacity, I/O count, LCD segment count, Touch Key count, stack capacity and package types. The following table summarises the main features of each device. Part No. VDD Program Memory Data Memory Data EEPROM I/O Ext. Int. LCD Driver Timer Module Touch Key I2C UART Time Base Stack Package BS82B12A-3 2.7V~ 5.5V 2K×16 384×8 64×8 22 1 16×4 10-bit CTM×1 10-bit PTM×1 12 √ √ 2 6 20/24SOP 24QFN BS82C16A-3 2.7V~ 5.5V 4K×16 512×8 64×8 26 1 20×4 10-bit CTM×1 10-bit PTM×1 16 √ √ 2 6 24/28SOP 32QFN BS82D20A-3 2.7V~ 5.5V 8K×16 768×8 64×8 26 1 20×4 10-bit CTM×1 10-bit PTM×1 20 √ √ 2 8 24/28SOP 28SSOP Rev. 1.40 7 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Block Diagram Low Voltage Detect Flash/EEPRO� Programming Circuitr� (ICP/OCDS) EEPRO� Data �emor� Flash Program �emor� Watchdog Timer RA� Data �emor� Low Voltage Reset Reset Circuit 8-bit RISC �CU Core Interrupt Controller LXT Oscillator Time Bases HIRC/LIRC Oscillators LED Driver I�C I/O UART Timer �odules LCD Driver Touch Ke�s Note: The LXT oscillator is only for the BS82C16A-3 and BS82D20A-3. Pin Assignment PB0/SSEG0/KEY1 PB1/SSEG1/KEY� 1 �0 PA3/SDA/RX � 19 PB�/SSEG�/KEY3 3 18 PA0/TCK1/SCO��/ICPDA/OCDSDA PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 17 PA7/SCL/TX PB4/SSEG4/KEY� � 1� VDD PB�/SSEG�/KEY� � 1� VSS PC0/SSEG8/KEY9 7 14 PA1/SCO�0 PC1/SSEG9/KEY10 8 13 PA4/INT/TCK0/SCO�1 PC�/SSEG10/KEY11 9 1� PC�/TP0_0/SSEG13 PC3/SSEG11/KEY1� 10 11 PC4/TP1_0/SSEG1� BS82B12A-3/BS82BV12A-3 20 SOP-A PB0/SSEG0/KEY1 1 �4 PA3/SDA/RX PB1/SSEG1/KEY� � �3 PA0/TCK1/SCO��/ICPDA/OCDSDA PB�/SSEG�/KEY3 3 �� PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 �1 PA7/SCL/TX PB4/SSEG4/KEY� � �0 VDD PB�/SSEG�/KEY� � 19 VSS PB�/SSEG�/KEY7 7 18 PA1/SCO�0 PB7/SSEG7/KEY8 8 17 PA4/INT/TCK0/SCO�1 PC0/SSEG8/KEY9 9 1� PC7/TP0_1/SSEG1� PC1/SSEG9/KEY10 10 1� PC�/TP1_1/SSEG14 PC�/SSEG10/KEY11 11 14 PC�/TP0_0/SSEG13 PC3/SSEG11/KEY1� 1� 13 PC4/TP1_0/SSEG1� BS82B12A-3/BS82BV12A-3 24 SOP-A Rev. 1.40 8 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver PA�/SCO�3/ICPCK/OCDSCK PA0/TCK1/SCO��/ICPDA/OCDSDA PA3/SDA/RX PB0/SSEG0/KEY1 PB1/SSEG1/KEY� PB�/SSEG�/KEY3 �4 �3 �� �1 �0 19 18 1 � 17 BS82B12A-3 3 1� BS82BV12A-3 4 24 QFN-A 1� 14 � 13 � 7 8 9 10 11 1� PB3/SSEG3/KEY4 PB4/SSEG4/KEY� PB�/SSEG�/KEY� PB�/SSEG�/KEY7 PB7/SSEG7/KEY8 PC0/SSEG8/KEY9 PA7/SCL/TX VDD VSS PA1/SCO�0 PA4/INT/TCK0/SCO�1 PC7/TP0_1/SSEG1� PC�/TP1_1/SSEG14 PC�/TP0_0/SSEG13 PC4/TP1_0/SSEG1� PC3/SSEG11/KEY1� PC�/SSEG10/KEY11 PC1/SSEG9/KEY10 PB0/SSEG0/KEY1 1 �4 PA3/SDA/RX PB1/SSEG1/KEY� � �3 PA0/TCK1/SCO��/ICPDA/OCDSDA PB�/SSEG�/KEY3 3 �� PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 �1 PA7/SCL/TX PB4/SSEG4/KEY� � �0 VDD PB�/SSEG�/KEY� � 19 VSS PB�/SSEG�/KEY7 7 18 PA1/SCO�0 PB7/SSEG7/KEY8 8 17 PA4/INT/TCK0/SCO�1 PC0/SSEG8/KEY9 9 1� PC7/TP0_1/SSEG1�/KEY1� PC1/SSEG9/KEY10 10 1� PC�/TP1_1/SSEG14/KEY1� PC�/SSEG10/KEY11 11 14 PC�/SSEG13/KEY14 PC3/SSEG11/KEY1� 1� 13 PC4/SSEG1�/KEY13 BS82C16A-3/BS82CV16A-3 24 SOP-A Rev. 1.40 9 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver PB0/SSEG0/KEY1 1 �8 PA3/SDA/RX PB1/SSEG1/KEY� � �7 PA0/TCK1/SCO��/ICPDA/OCDSDA PB�/SSEG�/KEY3 3 �� PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 �� PB4/SSEG4/KEY� � �4 PA7/SCL/TX VDD PB�/SSEG�/KEY� � �3 PD1/TP0_0/SSEG17/XT� PB�/SSEG�/KEY7 7 �� PD0/TP1_0/SSEG1�/XT1 PB7/SSEG7/KEY8 8 �1 VSS PD3/SSEG19 9 �0 PA1/SCO�0 PD�/SSEG18 10 19 PA4/INT/TCK0/SCO�1 PC0/SSEG8/KEY9 11 18 PC7/TP0_1/SSEG1�/KEY1� PC1/SSEG9/KEY10 1� 17 PC�/TP1_1/SSEG14/KEY1� PC�/SSEG10/KEY11 13 1� PC�/SSEG13/KEY14 PC3/SSEG11/KEY1� 14 1� PC4/SSEG1�/KEY13 BS82C16A-3/BS82CV16A-3 28 SOP-A PA�/SCO�3/ICPCK/OCDSCK PA0/TCK1/SCO��/ICPDA/OCDSDA PA3/SDA/RX NC NC PB0/SSEG0/KEY1 PB1/SSEG1/KEY� PB�/SSEG�/KEY3 PB3/SSEG3/KEY4 PB4/SSEG4/KEY� PB�/SSEG�/KEY� PB�/SSEG�/KEY7 PB7/SSEG7/KEY8 PD3/SSEG19 PD�/SSEG18 PC0/SSEG8/KEY9 1 � 3 4 � � 7 8 3� 31 30 �9 �8 �7 �� �� �4 �3 �� BS82C16A-3 �1 BS82CV16A-3 �0 32 QFN-A 19 18 17 9 10111� 13 141� 1� PA7/SCL/TX VDD PD1/TP0_0/SSEG17/XT� PD0/TP1_0/SSEG1�/XT1 VSS PA1/SCO�0 PA4/INT/TCK0/SCO�1 PC7/TP0_1/SSEG1�/KEY1� PC�/TP1_1/SSEG14/KEY1� PC�/SSEG13/KEY14 PC4/SSEG1�/KEY13 NC NC PC3/SSEG11/KEY1� PC�/SSEG10/KEY11 PC1/SSEG9/KEY10 Rev. 1.40 10 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver PB0/SSEG0/KEY1 1 �4 PA3/SDA/RX PB1/SSEG1/KEY� � �3 PA0/TCK1/SCO��/ICPDA/OCDSDA PB�/SSEG�/KEY3 3 �� PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 �1 PA7/SCL/TX PB4/SSEG4/KEY� � �0 VDD PB�/SSEG�/KEY� � 19 VSS PB�/SSEG�/KEY7 7 18 PA1/SCO�0/KEY�0 PB7/SSEG7/KEY8 8 17 PA4/INT/TCK0/SCO�1/KEY19 PC0/SSEG8/KEY11 9 1� PC7/TP0_1/SSEG1�/KEY18 PC1/SSEG9/KEY1� 10 1� PC�/TP1_1/SSEG14/KEY17 PC�/SSEG10/KEY13 11 14 PC�/SSEG13/KEY1� PC3/SSEG11/KEY14 1� 13 PC4/SSEG1�/KEY1� BS82D20A-3/BS82DV20A-3 24 SOP-A PB0/SSEG0/KEY1 1 �8 PA3/SDA/RX PB1/SSEG1/KEY� � �7 PA0/TCK1/SCO��/ICPDA/OCDSDA PB�/SSEG�/KEY3 3 �� PA�/SCO�3/ICPCK/OCDSCK PB3/SSEG3/KEY4 4 �� PA7/SCL/TX PB4/SSEG4/KEY� � �4 VDD PB�/SSEG�/KEY� � �3 PD1/TP0_0/SSEG17/XT� PB�/SSEG�/KEY7 7 �� PD0/TP1_0/SSEG1�/XT1 PB7/SSEG7/KEY8 8 �1 VSS PD3/SSEG19/KEY9 9 �0 PA1/SCO�0/KEY�0 PD�/SSEG18/KEY10 10 19 PA4/INT/TCK0/SCO�1/KEY19 PC0/SSEG8/KEY11 11 18 PC7/TP0_1/SSEG1�/KEY18 PC1/SSEG9/KEY1� 1� 17 PC�/TP1_1/SSEG14/KEY17 PC�/SSEG10/KEY13 13 1� PC�/SSEG13/KEY1� PC3/SSEG11/KEY14 14 1� PC4/SSEG1�/KEY1� BS82D20A-3/BS82DV20A-3 28 SOP-A/SSOP-A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. 2. The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the BS82BV12A-3, BS82CV16A-3 and BS82DV20A-3 devices, which are the OCDS EV chips for the BS82B12A-3, BS82C16A-3 and BS82D20A-3 devices respectively. Rev. 1.40 11 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their Port name, e.g. PA0, PA1, etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Touch Key function, Timer Modules, etc. The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. BS82B12A-3 Pin Name PA0/TCK1/ SCOM2/ ICPDA/ OCDSDA PA1/SCOM0 PA2/ SCOM3/ ICPCK/ OCDSCK PA3/SDA/ RX PA4/INT/ TCK0/ SCOM1 PA7/SCL/TX PB0/ SSEG0/ KEY1 PB1/ SSEG1/ KEY2 Rev. 1.40 Function OP I/T PA0 PAWU PAPU ST O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK1 PTM0C0 ST SCOM2 SLCDC0 — SCOM LCD driver output for LCD panel common — ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD driver output for LCD panel common PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD driver output for LCD panel common ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDA IICC0 ST NMOS I2C Data RX UCR1 ST PA4 PAWU PAPU ST INT INTC0 INTEG ST — External interrupt TCK0 CTM0C0 ST — CTM0 clock input SCOM1 SLCDC0 — SCOM LCD driver output for LCD panel common PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCL IICC0 ST NMOS I2C Clock TX UCR1 — CMOS UART transmitter data output — PTM0 clock input UART receiver data input CMOS General purpose I/O. Register enabled pull-up and wake-up. PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG0 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY1 TKM0C1 NSI PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG1 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY2 TKM0C1 NSI — — Touch key input Touch key input 12 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Name PB2/ SSEG2/ KEY3 Function OP I/T PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. O/T SSEG2 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY3 TKM0C1 NSI ST CMOS General purpose I/O. Register enabled pull-up. CMOS LCD driver output for LCD panel segment — Description Touch key input PB3/ SSEG3/ KEY4 PB3 PBPU SSEG3 SLCDC1 — KEY4 TKM0C1 NSI PB4/ SSEG4/ KEY5 PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG4 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY5 TKM1C1 NSI PB5/ SSEG5/ KEY6 PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG5 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY6 TKM1C1 NSI PB6/ SSEG6/ KEY7 PB6 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG6 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY7 TKM1C1 NSI PB7/ SSEG7/ KEY8 PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG7 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY8 TKM1C1 NSI PC0/ SSEG8/ KEY9 PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG8 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY9 TKM2C1 NSI PC1/ SSEG9/ KEY10 PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG9 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY10 TKM2C1 NSI PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG10 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY11 TKM2C1 NSI PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG11 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY12 TKM2C1 NSI PC2/ SSEG10/ KEY11 PC3/ SSEG11/ KEY12 PC4/TP1_0/ SSEG12 PC5/TP0_0/ SSEG13 PC6/TP1_1/ SSEG14 PC7/TP0_1/ SSEG15 Rev. 1.40 — — — — — — — — — Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input PC4 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_0 TMPC — CMOS PTM0 output SSEG12 SLCDC2 — CMOS LCD driver output for LCD panel segment PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_0 TMPC — CMOS CTM0 output SSEG13 SLCDC2 — CMOS LCD driver output for LCD panel segment PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_1 TMPC — CMOS PTM0 output SSEG14 SLCDC2 — CMOS LCD driver output for LCD panel segment PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_1 TMPC — CMOS CTM0 output SSEG15 SLCDC2 — CMOS LCD driver output for LCD panel segment 13 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Function OP I/T O/T VDD Pin Name VDD — PWR — Power supply Description VSS VSS — PWR — Ground Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register selection PWR: Power; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output; SCOM: SCOM output AN: Analog input; NSI: Non-standard input The PTM pin names and output pin control bits use "1" as their serial number, but other PTM related regiter names or bit names use "0". BS82C16A-3 Pin Name PA0/TCK1/ SCOM2/ ICPDA/ OCDSDA PA1/SCOM0 PA2/ SCOM3/ ICPCK/ OCDSCK PA3/SDA/ RX PA4/INT/ TCK0/ SCOM1 PA7/SCL/TX Function OP I/T O/T Description PA0 PAWU PAPU ST TCK1 PTM0C0 ST SCOM2 SLCDC0 — SCOM LCD driver output for LCD panel common CMOS General purpose I/O. Register enabled pull-up and wake-up. — PTM0 clock input ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD driver output for LCD panel common PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD driver output for LCD panel common ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDA IICC0 ST NMOS I2C Data RX UCR1 ST PA4 PAWU PAPU ST INT INTC0 INTEG ST — UART receiver data input CMOS General purpose I/O. Register enabled pull-up and wake-up. — External interrupt — CTM0 clock input TCK0 CTM0C0 ST SCOM1 SLCDC0 — SCOM LCD driver output for LCD panel common PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCL IICC0 ST NMOS I2C Clock TX UCR1 — CMOS UART transmitter data output PB0/ SSEG0/ KEY1 PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG0 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY1 TKM0C1 NSI PB1/ SSEG1/ KEY2 PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG1 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY2 TKM0C1 NSI Rev. 1.40 — — Touch key input Touch key input 14 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Name PB2/ SSEG2/ KEY3 Function OP I/T PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. O/T SSEG2 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY3 TKM0C1 NSI ST CMOS General purpose I/O. Register enabled pull-up. CMOS LCD driver output for LCD panel segment — Description Touch key input PB3/ SSEG3/ KEY4 PB3 PBPU SSEG3 SLCDC1 — KEY4 TKM0C1 NSI PB4/ SSEG4/ KEY5 PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG4 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY5 TKM1C1 NSI PB5/ SSEG5/ KEY6 PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG5 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY6 TKM1C1 NSI PB6/ SSEG6/ KEY7 PB6 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG6 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY7 TKM1C1 NSI PB7/ SSEG7/ KEY8 PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG7 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY8 TKM1C1 NSI PC0/ SSEG8/ KEY9 PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG8 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY9 TKM2C1 NSI PC1/ SSEG9/ KEY10 PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG9 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY10 TKM2C1 NSI PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG10 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY11 TKM2C1 NSI ST CMOS General purpose I/O. Register enabled pull-up. CMOS LCD driver output for LCD panel segment PC2/ SSEG10/ KEY11 — — — — — — — — Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input PC3/ SSEG11/ KEY12 PC3 PCPU SSEG11 SLCDC2 — KEY12 TKM2C1 NSI PC4/ SSEG12/ KEY13 PC4 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG12 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY13 TKM3C1 NSI PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG13 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY14 TKM3C1 NSI PC5/ SSEG13/ KEY14 PC6/TP1_1/ SSEG14/ KEY15 Rev. 1.40 — — — Touch key input Touch key input Touch key input PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_1 TMPC — CMOS PTM0 output SSEG14 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY15 TKM3C1 NSI — Touch key input 15 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Name PC7/TP0_1/ SSEG15/ KEY16 PD0/TP1_0/ SSEG16/ XT1 PD1/TP0_0/ SSEG17/ XT2 PD2/ SSEG18 PD3/ SSEG19 Function OP I/T PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-up. O/T Description TP0_1 TMPC — CMOS CTM0 output SSEG15 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY16 TKM3C1 NSI — Touch key input PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_0 TMPC — CMOS PTM0 output SSEG16 SLCDC3 — CMOS LCD driver output for LCD panel segment XT1 CO LXT — LXT pin PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_0 TMPC — CMOS CTM0 output SSEG17 SLCDC3 — CMOS LCD driver output for LCD panel segment XT2 CO — LXT LXT pin PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG18 SLCDC3 — CMOS LCD driver output for LCD panel segment PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-up. CMOS LCD driver output for LCD panel segment SSEG19 SLCDC3 — VDD VDD — PWR — Power supply VSS VSS — PWR — Ground Note: I/T: Input type; O/T: Output type; OP: Optional by configuration option (CO) or register selection; PWR: Power; ST: Schmitt Trigger input; CMOS: CMOS output; NMOS: NMOS output; SCOM: SCOM output; AN: Analog input; NSI: Non-standard input; LXT: Low frequency crystal oscillator; The PTM pin names and output pin control bits use "1" as their serial number, but other PTM related regiter names or bit names use "0". BS82D20A-3 Pin Name PA0/TCK1/ SCOM2/ ICPDA/ OCDSDA PA1/ SCOM0/ KEY20 PA2/ SCOM3/ ICPCK/ OCDSCK Rev. 1.40 Function OP I/T PA0 PAWU PAPU O/T Description ST TCK1 PTM0C0 ST SCOM2 SLCDC0 — SCOM LCD driver output for LCD panel common ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD driver output for LCD panel common KEY20 TKM4C1 NSI PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD driver output for LCD panel common ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. CMOS General purpose I/O. Register enabled pull-up and wake-up. — — PTM0 clock input Touch key input 16 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Name PA3/SDA/RX PA4/INT/ TCK0/ SCOM1/ KEY19 PA7/SCL/TX Function OP I/T PA3 PAWU PAPU O/T ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDA IICC0 ST NMOS I2C Data RX UCR1 ST PA4 PAWU PAPU ST INT INTC0 INTEG ST — External interrupt TCK0 CTM0C0 ST — CTM0 clock input SCOM1 SLCDC0 — KEY19 TKM4C1 NSI PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCL IICC0 ST NMOS I2C Clock — Description UART receiver data input CMOS General purpose I/O. Register enabled pull-up and wake-up. SCOM LCD driver output for LCD panel common — Touch key input TX UCR1 — CMOS UART transmitter data output PB0/SSEG0/ KEY1 PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG0 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY1 TKM0C1 NSI PB1/SSEG1/ KEY2 PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG1 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY2 TKM0C1 NSI PB2/SSEG2/ KEY3 PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG2 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY3 TKM0C1 NSI PB3/SSEG3/ KEY4 PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG3 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY4 TKM0C1 NSI PB4/SSEG4/ KEY5 PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG4 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY5 TKM1C1 NSI PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG5 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY6 TKM1C1 NSI PB6/SSEG6/ KEY7 PB6 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG6 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY7 TKM1C1 NSI PB7/SSEG7/ KEY8 PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG7 SLCDC1 — CMOS LCD driver output for LCD panel segment KEY8 TKM1C1 NSI PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG8 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY11 TKM2C1 NSI PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up. SSEG9 SLCDC2 — CMOS LCD driver output for LCD panel segment KEY12 TKM2C1 NSI PB5/SSEG5/ KEY6 PC0/SSEG8/ KEY11 PC1/SSEG9/ KEY12 Rev. 1.40 — — — — — — — — — — Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input Touch key input 17 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pin Name PC2/ SSEG10/ KEY13 Function OP I/T PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment SSEG10 SLCDC2 TKM2C1 NSI PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment SSEG11 SLCDC2 PC4/ SSEG12/ KEY15 SSEG12 SLCDC2 PC6/TP1_1/ SSEG14/ KEY17 PC7/TP0_1/ SSEG15/ KEY18 PD0/TP1_0/ SSEG16/ XT1 PD1/TP0_0/ SSEG17/ XT2 PD2/ SSEG18/ KEY10 PD3/ SSEG19/ KEY9 — Description KEY13 PC3/ SSEG11/ KEY14 PC5/ SSEG13/ KEY16 O/T — Touch key input KEY14 TKM3C1 NSI PC4 PCPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment KEY15 TKM3C1 NSI PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment SSEG13 SLCDC2 KEY16 — Touch key input TKM3C1 NSI PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_1 TMPC — CMOS PTM0 output — CMOS LCD driver output for LCD panel segment SSEG14 SLCDC2 — Touch key input KEY17 TKM4C1 NSI PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_1 TMPC — CMOS CTM0 output — CMOS LCD driver output for LCD panel segment SSEG15 SLCDC2 — Touch key input KEY18 TKM4C1 NSI PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_0 TMPC — CMOS PTM0 output — CMOS LCD driver output for LCD panel segment SSEG16 SLCDC3 — Touch key input XT1 CO LXT PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_0 TMPC — CMOS CTM0 output — CMOS LCD driver output for LCD panel segment SSEG17 SLCDC3 — Touch key input XT2 CO — PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment SSEG18 SLCDC3 LXT LXT pin KEY10 TKM2C1 NSI PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-up. — CMOS LCD driver output for LCD panel segment SSEG19 SLCDC3 — LXT pin Touch key input KEY9 TKM2C1 NSI — Touch key input VDD VDD — PWR — Power supply VSS VSS — PWR — Ground Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register selection PWR: Power; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input; NSI: Non-standard input; SCOM: SCOM output LXT: Low frequency crystal oscillator The PTM pin names and output pin control bits use "1" as their serial number, but other PTM related regiter names or bit names use "0". Rev. 1.40 18 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. D.C. Characteristics Symbol VDD Parameter Operating Voltage (HIRC) Ta=25°C Test Conditions — 3V 5V Operating Current (Normal) (HIRC, fSYS=fH, fS=fSUB) 3V 5V 3V 5V 3V 5V 3V 5V 3V IDD Operating Current (Normal) (HIRC, fSYS=fL, fS=fSUB) 5V 3V 5V 3V 5V 5V 3V 3V 5V Operating Current (Slow) (LXT/LIRC, fSYS=fL, fS=fSUB) 3V 5V 3V 5V Rev. 1.40 Min. Typ. Max. Unit fSYS = 8MHz 2.7 — 5.5 V fSYS = 12MHz 2.7 — 5.5 V fSYS = 16MHz 4.5 — 5.5 V No load, fH = 8MHz, WDT enable — 1.2 1.8 mA — 2.2 3.3 mA No load, fH = 12MHz, WDT enable — 1.6 2.4 mA — 3.3 5.0 mA No load, fH = 16MHz, WDT enable — 2.0 3.0 mA — 4.0 6.0 mA No load, fH =12MHz, fL= fH/2, WDT enable — 1.2 2.0 mA — 2.2 3.3 mA No load, fH =12MHz, fL= fH/4, WDT enable — 1.0 1.5 mA — 1.8 2.7 mA No load, fH =12MHz, fL= fH/8, WDT enable — 0.9 1.4 mA — 1.6 2.4 mA No load, fH =12MHz, fL= fH/16, WDT enable — 0.8 1.2 mA — 1.5 2.3 mA No load, fH =12MHz, fL= fH/32, WDT enable — 0.8 1.2 mA — 1.5 2.3 mA No load, fH =12MHz, fL= fH/64, WDT enable — 0.8 1.2 mA — 1.5 2.3 mA No load, fSYS=LXT, WDT enable, LXTLP=0 — 19 38 μA — 48 96 μA No load, fSYS=LXT, WDT enable, LXTLP=1 — 16 32 μA — 36 72 μA No load, fSYS=LIRC, WDT enable — 10 20 μA — 30 50 μA VDD Conditions 19 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Symbol ISTB Parameter Test Conditions No load, system HALT, WDT enable, fSYS = 12MHz — 0.9 1.4 mA — 1.4 2.1 mA No load, system HALT, WDT enable, fSYS = 12MHz — 1.4 3.0 μA — 2.7 5.0 μA No load, system HALT, WDT enable, fSYS = 12MHz/64 — 0.7 1.1 mA — 1.4 2.1 mA No load, system HALT, WDT enable, fSYS = 12MHz/64 — 1.3 3.0 μA — 2.3 5.0 μA No load, system HALT, WDT enable, fSYS = LIRC — 1.9 4.0 μA — 3.3 7.0 μA No load, system HALT, WDT enable, LXTLP=0 (LXT on) — 5 10 μA — 18 30 μA No load, system HALT, WDT enable, LXTLP=1 (LXT on) — 2.5 5 μA — 6 10 μA No load, system HALT, WDT enable (LIRC on) — 1.3 3.0 μA — 2.4 5.0 μA No load, system HALT, WDT disable (LXT and LIRC off) — 0.1 1 μA — 0.3 2 μA No load, system HALT, WDT disable (LXT and LIRC off) — 0.1 1 μA — 0.3 2 μA 0 — 1.5 V 0 — 0.2VDD V 3.5 — 5.0 V IDLE0 Mode Standby Current (HIRC, fSYS=off, fS=fSUB) 3V IDLE1 Mode Standby Current (HIRC, fSYS= fL, fS=fSUB) 3V IDLE0 Mode Standby Current (HIRC, fSYS=off, fS=fSUB) 3V IDLE1 Mode Standby Current (LIRC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) 3V 5V 5V 5V 5V 5V 3V 3V 5V 5V SLEEP Mode Standby Current (HIRC, fSYS=off, fS=fSUB=off) 3V SLEEP Mode Standby Current (LXT/LIRC, fSYS=off, fS=fSUB=off) 3V VIL Input Low Voltage for I/O Ports or Input Pins 5V VIH Input High Voltage for I/O Ports or Input Pins 5V VLVR Low Voltage Reset Voltage — Rev. 1.40 Unit 3V 3V IOH Max. IDLE1 Mode Standby Current (HIRC, fSYS=fH, fS=fSUB) IDLE0 Mode Standby Current (LXT/LIRC, fSYS=off, fS=fSUB) IOL Typ. Conditions 5V VLVD Min. VDD Low Voltage Detector Voltage I/O Port Sink Current I/O Port Source Current 5V 5V — — — — — 0.8VDD — VDD V LVR enable, 2.55V -5% 2.55 +5% V LVDEN = 1, VLVD = 2.7V -5% 2.7 +5% V LVDEN = 1, VLVD = 3.0V -5% 3.0 +5% V LVDEN = 1, VLVD = 3.3V -5% 3.3 +5% V LVDEN = 1, VLVD = 3.6V -5% 3.6 +5% V LVDEN = 1, VLVD = 4.0V -5% 4.0 +5% V 3V VOL=0.1VDD 16 32 — mA 5V VOL=0.1VDD 32 64 — mA 3V VOH = 0.9VDD, PxPS=00 -1.0 -2.0 — mA 5V VOH = 0.9VDD, PxPS=00 -2.0 -4.0 — mA 3V VOH = 0.9VDD, PxPS=01 -1.75 -3.5 — mA 5V VOH = 0.9VDD, PxPS=01 -3.5 -7.0 — mA 3V VOH = 0.9VDD, PxPS=10 -2.5 -5.0 — mA 5V VOH = 0.9VDD, PxPS=10 -5.0 -10 — mA 3V VOH = 0.9VDD, PxPS=11 -5.5 -11 — mA 5V VOH = 0.9VDD, PxPS=11 -11 -22 — mA 20 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Symbol Parameter RPH Pull-high Resistance for I/O Ports VBG Bandgap Reference with Buffer Voltage Test Conditions Min. Typ. Max. Unit — 20 60 100 kΩ 5V — 10 30 50 kΩ — — -3% 1.09 +3% V VDD Conditions 3V A.C. Characteristics Ta=25°C Symbol fSYS Parameter System Clock (HIRC) Test Conditions VDD Conditions 3V/5V Ta=25°C Typ. Max. Unit -2% 8 +2% MHz -2% 12 +2% MHz -2% 16 +2% MHz 0.3 — — μs -10% 32 +10% kHz — 32768 — Hz tTIMER Timer Input Pulse Width — fLIRC System Clock (32kHz) 5V fLXT System Clock (LXT) — — tINT Interrupt Pulse Width — — 1 5 10 μs tLVR Low Voltage Width to Reset — — 120 240 480 μs tLVD Low Voltage Width to Interrupt — — 60 120 240 μs tLVDS LVDO stable time — — — — 15 μs tEERD EEPROM Read Time — — 1 2 4 tSYS tEEWR EEPROM Write Time — — 1 2 4 ms — — 25 50 100 ms tRSTD System Reset Delay Time (Power on reset, LVR reset, WDT S/W reset (WDTC)) System Reset Delay Time (WDT normal reset) — — 8.3 16.7 33.3 ms System Start-up Timer Period (Wake-up from HALT) — tSST System Start-up Timer Period (Wake-up from HALT, fSYS on at HALT state) — Min. Ta=25°C fSYS=LXT 1024 — — fSYS=HIRC 16 — — fSYS=LIRC 2 — — 2 — — — — tSYS Note: tSYS = 1/fSYS Rev. 1.40 21 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Sensor Oscillator Electrical Characteristics Ta=25°C Touch Key RC OSC = 500kHz Symbol Parameter Test Conditions VDD 3V IKEYOSC Only Sensor (KEY) Oscillator Operating Current Typ. Max. Unit 30 60 — 60 120 — 40 80 — 80 160 *fREFOSC=500kHz, MnTSS=0, MnFILEN=0 — 30 60 — 60 120 *fREFOSC=500kHz, MnTSS=0, MnFILEN=1 — 30 60 — 60 120 *fREFOSC=500kHz, MnTSS=1, MnFILEN=0 — 30 60 — 60 120 — 40 80 5V *fREFOSC=500kHz, MnTSS=1, MnFILEN=1 — 80 160 5V 3V 3V 5V 3V IREFOSC Min. — 5V Only Reference Oscillator Operating Current Condition 5V 3V 5V 3V *fSENOSC=500kHz, MnFILEN=0 *fSENOSC=500kHz, MnFILEN=1 μA μA μA μA μA μA CKEYOSC Sensor (KEY) Oscillator External Capacitance 5V *fSENOSC=500kHz 5 10 20 pF CREFOSC Reference Oscillator Internal Capacitance 5V *fSENOSC=500kHz 5 10 20 pF fKEYOSC Sensor (KEY) Oscillator Operating Frequency 5V *External Capacitance =7,8,9,10,11,12,13,14,15, … 50pF 100 500 1000 kHz fREFYOSC Reference Oscillator Operating Frequency 5V *Internal Capacitance =7,8,9,10,11,12,13,14,15, … 50pF 100 500 1000 kHz Note: *fSENOSC=500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =500kHz. *fREFOSC=500kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =500kHz. Rev. 1.40 22 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key RC OSC = 1000kHz Symbol Parameter Test Conditions VDD 3V IKEYOSC Only Sensor (KEY) Oscillator Operating Current 40 80 — 80 160 — 60 120 — 100 200 *fREFOSC=1000kHz, MnTSS=0, MnFILEN=0 — 40 80 — 80 160 *fREFOSC=1000kHz, MnTSS=0, MnFILEN=1 — 40 80 — 80 160 *fREFOSC=1000kHz, MnTSS=1, MnFILEN=0 — 40 80 — 80 160 — 60 120 5V *fREFOSC=1000kHz, MnTSS=1, MnFILEN=1 — 150 300 3V 3V 5V 3V Only Reference Oscillator Operating Current Min. Typ. Max. Unit — 5V 5V IREFOSC Condition 5V 3V 5V 3V *fSENOSC=1000kHz, MnFILEN=0 *fSENOSC=1000kHz, MnFILEN=1 μA μA μA μA μA μA CKEYOSC Sensor (KEY) Oscillator External Capacitance 5V *fSENOSC=1000kHz 5 10 20 pF CREFOSC Reference Oscillator Internal Capacitance 5V *fSENOSC=1000kHz 5 10 20 pF fKEYOSC Sensor (KEY) Oscillator Operating Frequency 5V *External Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 1000 2500 kHz fREFYOSC Reference Oscillator Operating Frequency 5V *Internal Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 1000 2500 kHz Note: *fSENOSC=1000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1000kHz. *fREFOSC=1000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =1000kHz. Rev. 1.40 23 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key RC OSC =1500kHz Symbol Parameter Test Conditions VDD 3V IKEYOSC Only Sensor (KEY) Oscillator Operating Current 5V 3V 5V 3V 5V 3V IREFOSC Only Reference Oscillator Operating Current 5V 3V 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitance CREFOSC Reference Oscillator Internal Capacitance fKEYOSC Sensor (KEY) Oscillator Operating Frequency fREFYOSC Reference Oscillator Operating Frequency 3V 5V 3V 5V 3V 5V 3V 5V Condition Min. Typ. Max. Unit — 60 120 — 120 240 — 90 180 — 150 300 *fREFOSC=1500kHz, MnTSS=0, MnFILEN=0 — 60 120 — 120 240 *fREFOSC=1500kHz, MnTSS=0, MnFILEN=1 — 60 120 — 120 240 *fREFOSC=1500kHz, MnTSS=1, MnFILEN=0 — 60 120 — 120 240 *fREFOSC=1500kHz, MnTSS=1, MnFILEN=1 — 90 180 — 225 450 4 8 16 5 10 20 4 8 16 5 10 20 *fSENOSC=1500kHz, MnFILEN=0 *fSENOSC=1500kHz, MnFILEN=1 *fSENOSC=1500kHz *fSENOSC=1500kHz *External Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 1500 3000 150 1500 3000 *Internal Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 1500 3000 150 1500 3000 μA μA μA μA μA μA pF pF kHz kHz Note: *fSENOSC=1500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1500kHz. *fREFOSC=1500kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =1500kHz. Rev. 1.40 24 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key RC OSC =2000kHz Symbol Parameter Test Conditions VDD 3V IKEYOSC Only Sensor (KEY) Oscillator Operating Current 5V 3V 5V 3V 5V 3V IREFOSC Only Reference Oscillator Operating Current 5V 3V 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitance 3V CREFOSC Reference Oscillator Internal Capacitance 3V fKEYOSC Sensor (KEY) Oscillator Operating Frequency 3V fREFYOSC Reference Oscillator Operating Frequency 3V 5V 5V 5V 5V Min. Typ. Max. Unit Condition — 80 160 — 160 320 — 120 240 — 200 400 *fREFOSC=2000kHz, MnTSS=0, MnFILEN=0 — 80 160 — 160 320 *fREFOSC=2000kHz, MnTSS=0, MnFILEN=1 — 80 160 — 160 320 *fREFOSC=2000kHz, MnTSS=1, MnFILEN=0 — 80 160 — 160 320 *fREFOSC=2000kHz, MnTSS=1, MnFILEN=1 — 120 240 — 300 600 4 8 16 5 10 20 4 8 16 5 10 20 *fSENOSC=2000kHz, MnFILEN=0 *fSENOSC=2000kHz, MnFILEN=1 *fSENOSC=2000kHz *fSENOSC=2000kHz *External Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 2000 4000 150 2000 4000 *Internal Capacitance =1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, … 50pF 150 2000 4000 150 2000 4000 μA μA μA μA μA μA pF pF kHz kHz Note: *fSENOSC=2000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =2000kHz. *fREFOSC=2000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =2000kHz Power-on Reset Characteristics Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to eEnsure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 1.40 25 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes these devices suitable for lowcost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clock and Pipelining Rev. 1.40 26 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High Byte BS82B12A-3 PCL Register PC10~PC8 BS82C16A-3 PC11~PC8 BS82D20A-3 PC12~PC8 PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.40 27 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k B o tto m S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r o f S ta c k C o u n te r P ro g ra m M e m o ry S ta c k L e v e l N Device Stack Levels BS82B12A-3 6 BS82C16A-3 6 BS82D20A-3 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.40 28 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2K×16 bits to 8K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Capacity BS82B12A-3 2K×16 BS82C16A-3 4K×16 BS82D20A-3 8K×16 BS8�B1�A-3 BS8�C1�A-3 0000H 0004H 0030H 07FFH BS8�D�0A-3 Reset Reset Reset Interrupt Vector Interrupt Vector Interrupt Vector 1� bits 0FFFH 1� bits 1FFFH 1� bits Program Memory Structure Rev. 1.40 29 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 0000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer pair, the table data can be retrieved from the Program Memory using the "TABRD[m]" or "TABRDL[m]" instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "0700H" which refers to the start address of the last page within the 2K words Program Memory of the BS82B12A-3. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0706H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the specific page if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.40 30 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer, ; data at program memory address "0706H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer, ; data at program memory address "F05H" transferred to tempreg2 and TBLH ; in this example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : : org 0700h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins ICPDA PA0 Serial data/address input/output Function ICPCK PA2 Serial Clock input VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. Rev. 1.40 31 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver During the programming process the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There are three EV chips named BS82BV12A-3, BS82CV16A-3 and BS82DV20A-3 which are used to emulate the BS82B12A-3, BS82C16A-3 and BS82D20A-3 devices respectively. Each EV chip device also provides an "On-Chip Debug" function to debug the corresponding MCU device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for the "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HTIDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.40 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground 32 Pin Description May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two types, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks for the devices. The Special Purpose Data Memory registers addressed from 00H~7FH in Data Memory are common and accessible in all banks, with the exception of the EEC register at address 40H which is only accessible in Bank 1. Switching between the different Data Memory sectors is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Memory Type Special Function Data Memory General purpose Data Memory Device Capacity BS82B12A-3 Bank 0~2: 00H~7FH EEC register at 40H only accessible in Bank 1 BS82C16A-3 Bank 0~3: 00H~7FH EEC register at 40H only accessible in Bank 1 BS82D20A-3 Bank 0~5: 00H~7FH EEC register at 40H only accessible in Bank 1 BS82B12A-3 384×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank 2: 80H~FFH BS82C16A-3 512×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank 2: 80H~FFH Bank 3: 80H~FFH 768×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank 2: 80H~FFH Bank 3: 80H~FFH Bank 4: 80H~FFH Bank 5: 80H~FFH BS82D20A-3 Data Memory Sturcture 00H Special Function Data �emor� 40H in Bank 1 EEC 7FH 80H General Purpose Data �emor� FFH Bank 0 Bank 1 Bank N N=� for BS8�B1�A-3; N=3 for BS8�C1�A-3; N=� for BS8�D�0A-3 Data Memory Structure Rev. 1.40 33 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Rev. 1.40 34 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Rev. 1.40 35 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Rev. 1.40 36 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers directly will return a result of "00H" and writing to the registers directly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to the BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.40 37 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bank Pointer – BP Depending upon which device is used, the Data Memory is divided into several banks. Selecting the required Data Memory area is achieved using the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection with the exception of the EEC register in Bank 1, which means that the Special Function Registers can be accessed from within any bank. The EEC register in bank 1 can only be accessed by indirectly addressing the Data Memory. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect Addressing. Device 7 6 5 4 3 2 1 0 BS82B12A-3 — — — — — — DMBP1 DMBP0 BS82C16A-3 — — — — — — DMBP1 DMBP0 BS82D20A-3 — — — — — DMBP2 DMBP1 DMBP0 BP Register List BP Register – BS82B12A-3 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0DMBP1~DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined BP Register – BS82C16A-3 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0DMBP1~DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 Rev. 1.40 38 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver BP Register – BS82D20A-3 Bit 7 6 5 4 3 2 1 0 Name — — — — — DMBP2 DMBP1 DMBP0 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7 ~ 3 Unimplemented, read as "0" Bit 2 ~ 0DMBP2~DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101: Bank 5 11x: Undefined Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.40 39 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.40 40 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.40 41 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver EEPROM Data Memory The devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1. Device Capacity Address 64×8 00H~3FH BS82B12A-3 BS82C16A-3 BS82D20A-3 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Function Register. The EEC register however, being located in Bank 1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Control Registers List Name Bit 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0 42 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Rev. 1.40 43 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initial a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an EEPROM write cycle ends, the DEF request flag will be set. If the global and EEPROM write interrupts is enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced, the EEPROM interrupt flag will be automatically reset. Rev. 1.40 44 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to Sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally completed. Otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer BP MOV BP, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0 ; check for read cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP MOV A, EED ; move read data to register MOV READ_DATA, A • Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.40 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer BP ; set WREN bit, enable write operations ; start Write Cycle - set WR bit – executed immediately ; after set WREN bit ; check for write cycle end ; disable EEPROM read/write 45 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview All the devices include two internal oscillators and the some devices also include an external oscillator. In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer, Time Bases and TMs. External oscillator requiring some external components as well as fully integrated internal oscillators requiring no external components, are provided to form a wide range of both fast and slow system oscillators. For the BS82C16A-3 and BS82D20A-3 devices, the low speed oscillators are selected through the configuration option. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Device BS82B12A-3 BS82C16A-3 BS82D20A-3 BS82C16A-3 BS82D20A-3 Name Freq. Pins Internal High Speed RC Type HIRC 8/12/16MHz — Internal Low Speed RC LIRC 32kHz — External Low Speed Crystal LXT 32768Hz XT1/XT2 Oscillator Types System Clock Configurations There are three methods of generating the system clock, a high speed oscillator and two low speed oscillators. The high speed oscillator is the internal 8MHz, 12MHz, 16MHz RC oscillator. The two low speed oscillators are the internal 32kHz oscillator, LIRC, and the external 32.768kHz crystal oscillator, LXT. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. For two of the three devices, the actual source clock used for the low speed oscillator is chosen via configuration option. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 1.40 46 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Note: The LXT oscillator is only for the BS82C16A-3 and BS82D20A-3. System Clock Configurations Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a power on default frequency of 8 MHz but can be selected to be either 8MHz, 12MHz or 16MHz via a configuration option and the HIRCS1 and HIRCS0 bits in the CTRL register. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is a low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Rev. 1.40 47 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver External 32.768kHz Crystal Oscillator – LXT For the BS82C16A-3 and BS82D20A-3 devices, the External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor, Rp, is required. Note that the wire connected between the 32.768kHz crystal and the XT1/XT2 pins should be kept as short as possible to minimize the stray noise interface. The configuration option determines if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins or other pin-shared functions. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/ O pins or other pin-shared functions. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimize the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5MΩ~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values Rev. 1.40 48 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the CTRL register. LXTLP Bit LXT Mode 0 Quick Start 1 Low-power After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock is sourced from the HIRC oscillator. The low speed system clock source can be sourced from internal clock fSUB. Depending on the devices, if fSUB is selected then it is sourced by the LIRC oscillator or can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.40 49 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver System Clock Configurations Note: The LXT oscillator is only for the BS82C16A-3 and BS82D20A-3. When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.40 50 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver System Operation Modes There are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Description Operating Mode CPU fSYS fSUB NORMAL mode On fH~fH/64 On SLOW mode On fSUB On ILDE0 mode Off Off On IDLE1 mode Off On On SLEEP mode Off Off Off NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP mode the CPU will be stopped, and the fSUB clock will be stopped too, the Watchdog Timer function is automatically disabled by hardware for power saving. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be stop and will therefore be inhibited from driving the CPU. IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator. Rev. 1.40 51 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Control Register The SMOD register is used to control the internal clocks within the devices. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 CKS2 ~ CKS0: The system clock selection when HLCLK is "0" 000: fSUB (LIRC or LXT) 001: fSUB (LIRC or LXT) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0". Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable after a wake-up has occurred. This flag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. Bit 1IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: System Clock Selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. Bit 7 ~ 5 Rev. 1.40 52 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 Unimplemented, read as "0". Bit 5 ~ 4 HIRCS1~HIRCS0: HIRC frequency clock select 00: 8MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz It is recommended that the HIRC frequency selected by these two bits is the same with the frequency determined by the configuration option to keep the HIRC frequency accuracy specified in the A.C. characteristics. Bit 3LXTLP: LXT low power control 0: Quick Start mode 1: Low Power mode Bit 2 LVRF: LVR function reset flag Describe elsewhere Bit 1 Undefined bit This bit can be read or written by user software program Bit 0WRF: WDT Control register software reset flag Describe elsewhere Rev. 1.40 53 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Operating Mode Switching The devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the devices enter the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running. The accompanying flowchart shows what happens when the devices move between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by clearing the HLCLK bit to zero and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register.This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.40 54 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set high or HLCLK bit is low, but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization is 15~16 clock cycles. Entering the SLEEP Mode There is only one way for the devices to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock and the fSUB clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stop counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.40 55 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Entering the IDLE0 Mode There is only one way for the devices to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the low frequency fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the devices to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and the low frequency fSUB will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Rev. 1.40 56 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. System Oscillator Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) HIRC 15~16 HIRC cycles 1~2 HIRC cycles LIRC 1~2 LIRC cycles 1~2 LIRC cycles LXT 1024 LXT cycles 1~2 LXT cycles Wake-Up Time Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP Mode the HIRC oscillator needs to start-up from an off state. If the device is woken up from the SLEEP Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute the first instruction after HTO is high. At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed. Rev. 1.40 57 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal fSUB clock, depending on the devices, the fSUB clock is in turn supplied by the LIRC oscillator or either the LXT or LIRC oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768 kHz crystal. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable operation. The WDTC register is initiated to 01010011B at any reset except WDT time-out hardware warm reset. WDTC Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~ 3 WE4 ~ WE0: WDT function software control 01010B or 10101B: Enabled Other values: Reset MCU (Reset will be active after 2~3 LIRC clock for debounce time.) If the MCU reset is caused by the WE [4:0] in WDTC software reset, the WRF flag of CTRL register will be set. Bit 2~ 0 WS2 ~ WS0: WDT Time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. 58 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as "0" Bit 5~ 4 HIRCS1~HIRCS0: HIRC frequency clock select Describe elsewhere Bit 3LXTLP: LXT low power control Describe elsewhere Bit 2LVRF: LVR function reset flag Describe elsewhere Bit 1 Undefined bit This bit can be read or written by user software program Bit 0WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise, it will reset the microcontroller after 2~3 LIRC clock cycles. After power on these bits will have a value of 01010B. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT software reset, which means a certain value is written into the WE4~WE0 bit filed except 01010B and 10101B, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. Rev. 1.40 59 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Reset �CU WDTC Register WE4~WE0 bits CLR “HALT”Instruction “CLR WDT”Instruction LIRC LXT � U X fSUB 11 stage divider 8-to-1 �UX Configuration Option 7-stage Divider WS�~WS0 (fSUB/�1~fSUB/�11) WDT Time-out WS[�:0]= 000:�8/fSUB 001:�10/fSUB 010:�1�/fSUB 011:�14/fSUB 100:�1�/fSUB 101:�1�/fSUB 110:�17/fSUB 111:�18/fSUB Note: For the BS82B12A-3 device, the fSUB is supplied only by the LIRC oscillator. Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Rev. 1.40 60 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set high. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR is fixed at a voltage value of 2.55V. Note that the LVR function will be automatically disabled when the device enters the SLEEP or IDLE mode. Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as "0". Bit 5 ~ 4 HIRCS1~HIRCS0: HIRC frequency clock select Describe elsewhere Bit 3LXTLP: LXT low power control Describe elsewhere Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set high when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1 Undefined bit This bit can be read or written by user software program Bit 0WRF: WDT Control register software reset flag Describe elsewhere Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Rev. 1.40 61 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC. The tSST is 1~2 clock for the LIRC. The tSST is 1024 clock for the LXT. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Rev. 1.40 62 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver BS82B12A-3 BS82C16A-3 BS82D20A-3 Power On Reset Program Counter ● ● ● 0000H 0000H 0000H 0000H MP0 ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ● ● ---- --00 ---- --00 ---- --00 ---- --uu ● ---- -000 ---- -000 ---- -000 ---- -uuu ACC ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ---- -xxx ---- -uuu ---- -uuu ---- -uuu ---- xxxx ---- uuuu ---- uuuu ---- uuuu Register BP ● TBHP ● LVR Reset WDT Time-out (Normal Operation) (Normal Operation) WDT Time-out (HALT)* ● ---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS ● ● ● --00 xxxx --uu uuuu --1u uuuu - - 11 u u u u SMOD ● ● ● 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu INTEG ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu INTC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 ● ● ● ---- ---0 ---- ---0 ---- ---0 ---- ---u LVDC ● ● ● --00 -000 --00 -000 --00 -000 --uu -uuu PA ● ● ● 1 - - 1 1111 1 - - 1 1111 1 - - 1 1111 u--u uuuu PAC ● ● ● 1 - - 1 1111 1 - - 1 1111 1 - - 1 1111 u--u uuuu PAPU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PAWU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu SLEDC0 ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu ---- 0101 ---- 0101 ---- 0101 ---- uuuu SLEDC1 ● ● ● --01 0101 --01 0101 --01 0101 --uu uuuu WDTC ● ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PSCR ● ● ● --00 --00 --00 --00 --00 --00 --uu --uu EEA ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu EED ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PB ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu I2CTOC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IICC0 ● ● ● ---- 000- ---- 000- ---- 000- ---- uuu- IICC1 ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu IICD ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu IICA ● ● ● 0000 000- 0000 000- 0000 000- uuuu uuu- USR ● ● ● 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu UCR1 ● ● ● 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Rev. 1.40 63 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver BS82B12A-3 BS82C16A-3 BS82D20A-3 Power On Reset TXR_RXR ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMPC ● ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu SLCDC0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu Register SLCDC3 LVR Reset WDT Time-out (Normal Operation) (Normal Operation) WDT Time-out (HALT)* PC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTRL ● ● ● 0-00 0x00 0-00 0x00 0-00 0x00 u-uu uuuu PD ● ● - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu PDC ● ● - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu PDPU ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu TKTMR ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu TK16DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TK16DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC1 ● ● ● ---- --11 ---- --11 ---- --11 ---- --uu TKM016DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM016DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM116DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM116DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM1C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM216DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM216DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2ROH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM2C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM316DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM316DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROH ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM3C0 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu CTM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.40 64 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver BS82B12A-3 BS82C16A-3 BS82D20A-3 Power On Reset CTM0DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu CTM0AL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0AH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu PTM0C0 ● ● ● 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu PTM0AL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0AH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu PTM0RPL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0RPH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM416DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM416DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROH ● ---- --00 ---- --00 ---- --00 ---- --uu TKM4C0 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu Register EEC ● ● LVR Reset WDT Time-out (Normal Operation) (Normal Operation) WDT Time-out (HALT)* Note: "*" stands for "warm reset" "-" not implement "u" stands for "unchanged" "x" stands for "unknown" Rev. 1.40 65 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The devices provide bidirectional input/output lines labeled with port names PA ~ PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Device BS82B12A-3 BS82C16A-3 BS82D20A-3 7 6 5 PAWU PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 — — PA4 PA3 PA2 PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC2 PAC1 PAC0 PBPU PB PBC PCPU BS82C16A-3 BS82D20A-3 Bit Register Name 4 3 2 1 0 PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PDPU — — — — PD — — — — PD3 PD2 PD1 PD0 PDC — — — — PDC3 PDC2 PDC1 PDC0 PDPU3 PDPU2 PDPU1 PDPU0 PAWUn: PA wake-up function control 0: Disable 1: Enable PAn/PBn/PCn/PDn: I/O Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn: I/O Type selection 0: Output 1: Input PAPUn/PBPUn/PCPUn/PDPUn: I/O Pull-high function control 0: Disable 1: Enable Rev. 1.40 66 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PDPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure Rev. 1.40 67 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Source Current Selection The source current of each pin in these devices can be configured with different source current which is selected by the corresponding pin source current select bits. These source current bits are available when the corresponding pin is configured as a CMOS output. Otherwise, these select bits have no effect. Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. SLEDC0 Register Bit 7 6 5 4 3 2 1 0 Name PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 ~ 6 PBPS3~PBPS2: PB7~PB4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 5 ~ 4 PBPS1~PBPS0: PB3~PB0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 3 ~ 2 PAPS3~PAPS2: PA7 and PA4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 1 ~ 0 PAPS1~PAPS0: PA3~PA0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. SLEDC1 Register – BS82B12A-3 Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — PCPS3 PCPS2 PCPS1 PCPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 1 0 1 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 ~ 2 PCPS3~PCPS2: PC7~PC4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. 68 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 1 ~ 0 PCPS1~PCPS0: PC3~PC0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. SLEDC1 Register – BS82C16A-3/BS82D20A-3 Bit 7 6 5 4 3 2 1 0 Name — — PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 1 0 1 0 1 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 4 PDPS1~PDPS0: PD3~PD0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 3 ~ 2 PCPS3~PCPS2: PC7~PC4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 1 ~ 0 PCPS1~PCPS0: PC3~PC0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.40 69 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections. Introduction Each device contains a 10-bit Compact TM, CTM, and a 10-bit Periodic TM, PTM. Although similar in nature, the different TM types vary in their feature complexity. The common features to the Compact and Periodic TMs will be described in this section and the detailed operation will be described in corresponding sections. The main features and differences between the two types of TMs are summarised in the accompanying table. Function CTM PTM Timer/Counter √ √ I/P Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty — 1 Edge Edge Duty or Period Duty or Period TM Function Summary CTM0 PTM0 10-bit CTM 10-bit PTM TM Name/Type Reference TM Operation The two different types of TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" can stand for C or P and "n" is the serial number. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fSUB clock source or the external TCKn pin. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. Rev. 1.40 70 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver TM Interrupts The Compact and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pins, with the label TCKn. The TM input pin, TCKn, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The TM input pin can be chosen to have either a rising or falling active edge. The TCK1 pin is also used as the external trigger input pin in single pulse output mode for the PTM0. The TMs each has two output pins. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. As the TM output pins are pin-shared with other function, the TM output function must first be setup using the associated register. A single bit in the register determines if its associated pin is to be used as an external TM output pin or if it is to have another function. Device CTM0 PTM0 BS82B12A-3 BS82C16A-3 BS82D20A-3 TCK0 TP0_0, TP0_1 TCK1 TP1_0, TP1_1 TM Input/Output Pins TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. BS82B12A-3 CTM Function Pin Control Block Diagram Rev. 1.40 71 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver BS82C16A-3/BS82D20A-3 CTM Function Pin Control Block Diagram P C 4 O u tp u t F u n c tio n 0 P C 4 /T P 1 _ 0 1 0 1 T M 1 P C 0 P C 4 P C 6 O u tp u t F u n c tio n O u tp u t 0 1 0 P C 6 /T P 1 _ 1 1 T M 1 P C 1 P C 6 0 0 C a p tu re In p u t 1 1 T M 1 P C 1 P T 0 C K S 1 0 T M 1 P C 0 T C K In p u t P A 0 /T C K 1 BS82B12A-3 PTM Function Pin Control Block Diagram Rev. 1.40 72 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver P D 0 O u tp u t F u n c tio n 0 P D 0 /T P 1 _ 0 1 0 1 T M 1 P C 0 P D 0 P C 6 O u tp u t F u n c tio n O u tp u t 0 P C 6 /T P 1 _ 1 1 0 1 T M 1 P C 1 P C 6 1 0 0 C a p tu re In p u t 1 T M 1 P C 1 P 0 T C K S 1 0 T M 1 P C 0 T C K In p u t P A 0 /T C K 1 BS82C16A-3/BS82D20A-3 PTM Function Pin Control Block Diagram TMPC Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — TM1PC1 TM1PC0 TM0PC1 TM0PC0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 TM1PC1: TP1_1 pin Control 0: Disabled 1: Enabled Bit 2 TM1PC0: TP1_0 pin control 0: Disabled 1: Enabled Bit 1 TM0PC1: TP0_1 pin Control 0: Disabled 1: Enabled Bit 0 TM0PC0: TP0_0 pin Control 0: Disabled 1: Enabled 73 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these registers is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. xT�n Counter Register (Read onl�) xT�nDL xT�nDH 8-bit Buffer xT�nAL xT�nAH xT�n CCRA Register (Read/Write) PT�nRPL PT�nRPH PT�n CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMnRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMnRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.40 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL ––this step reads data from the 8-bit buffer. 74 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Compact Type TM – CTM0 Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. Compact Type TM Block Diagram Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CT0ON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a CTM0 interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control one output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.40 75 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Compact Type TM Register Description Overall operation of each Compact TM is controlled using several registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Bit Register Name 7 6 5 4 3 CTM0C0 CT0PAU CT0CK2 CT0CK1 CT0CK0 CT0ON CT0RP2 CT0RP1 CTM0C1 CT0M1 CT0M0 CT0IO1 CT0IO0 CT0OC CT0POL CT0DPX CT0CCLR CTM0DL D7 D6 D5 D4 D3 2 1 0 CT0RP0 D2 D1 D0 CTM0DH — — — — — — D9 D8 CTM0AL D7 D6 D5 D4 D3 D2 D1 D0 CTM0AH — — — — — — D9 D8 Compact TM Register List CTM0C0 Register Bit 7 6 5 4 3 2 1 0 Name CT0PAU CT0CK2 CT0CK1 CT0CK0 CT0ON CT0RP2 CT0RP1 CT0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CT0PAU: CTM0 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTM0 will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4CT0CK2~CT0CK0: Select CTM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the CTM0. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Rev. 1.40 76 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 3 CT0ON: CTM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the CTM0. Setting the bit high enables the counter to run, clearing the bit disables the CTM0. Clearing this bit to zero will stop the counter from counting and turn off the CTM0 which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the CTM0 is in the Compare Match Output Mode then the CTM0 output pin will be reset to its initial condition, as specified by the CT0OC bit, when the CT0ON bit changes from low to high. Bit 2~0 CT0RP2~CT0RP0: CTM0 CCRP 3-bit register, compared with the CTM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 CTM0 clocks 001: 128 CTM0 clocks 010: 256 CTM0 clocks 011: 384 CTM0 clocks 100: 512 CTM0 clocks 101: 640 CTM0 clocks 110: 768 CTM0 clocks 111: 896 CTM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CT0CCLR bit is set to zero. Setting the CT0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. CTM0C1 Register Bit 7 6 5 4 3 Name CT0M1 CT0M0 CT0IO1 CT0IO0 CT0OC R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Rev. 1.40 2 1 0 CT0POL CT0DPX CT0CCLR CT0M1~CT0M0: Select CTM0 Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTM0. To ensure reliable operation the CTM0 should be switched off before any changes are made to the CT0M1 and CT0M0 bits. In the Timer/Counter Mode, the CTM0 output pin control must be disabled. CT0IO1~CT0IO0: Select TP0 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined 77 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Timer/counter Mode Unused These two bits are used to determine how the CTM0 output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTM0 is running. In the Compare Match Output Mode, the CT0IO1 and CT0IO0 bits determine how the CTM0 output pin changes state when a compare match occurs from the Comparator A. The CTM0 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTM0 output pin should be setup using the CT0OC bit in the CTM0C1 register. Note that the output level requested by the CT0IO1 and CT0IO0 bits must be different from the initial value setup using the CT0OC bit otherwise no change will occur on the CTM0 output pin when a compare match occurs. After the CTM0 output pin changes state it can be reset to its initial level by changing the level of the CT0ON bit from low to high. In the PWM Mode, the CT0IO1 and CT0IO0 bits determine how the CTM0 output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CT0IO1 and CT0IO0 bits only after the CTM0 has been switched off. Unpredictable PWM outputs will occur if the CT0IO1 and CT0IO0 bits are changed when The CTM0 is running. Rev. 1.40 Bit 3 CT0OC: TP0 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the CTM0 output pin. Its operation depends upon whether CTM0 is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the CTM0 is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTM0 output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 CT0POL: TP0 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the CTM0 output pin. When the bit is set high the CTM0 output pin will be inverted and not inverted when the bit is zero. It has no effect if the CTM0 is in the Timer/Counter Mode. Bit 1 CT0DPX: CTM0 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 CT0CCLR: Select CTM Counter clear condition 0: CTM0 Comparatror P match 1: CTM0 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact CTM0 contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CT0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CT0CCLR bit is not used in the PWM Mode. 78 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CTM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM0 Counter Low Byte Register bit 7 ~ bit 0 CTM0 10-bit Counter bit 7 ~ bit 0 CTM0DH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 CTM0 Counter High Byte Register bit 1 ~ bit 0 CTM0 10-bit Counter bit 9 ~ bit 8 CTM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM0 CCRA Low Byte Register bit 7 ~ bit 0 CTM0 10-bit CCRA bit 7 ~ bit 0 CTM0AH Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 CTM0 CCRA High Byte Register bit 1 ~ bit 0 CTM0 10-bit CCRA bit 9 ~ bit 8 79 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CT0M1 and CT0M0 bits in the CTM0C1 register. Compare Match Output Mode To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CT0CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMA0F and CTMP0F interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CT0CCLR bit in the CTM0C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CT0CCLR is high no CTMP0F interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMA0F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTM0 output pin will change state. The CTM0 output pin condition however only changes state when a CTMA0F interrupt request flag is generated after a compare match occurs from Comparator A. The CTMP0F interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the CTM0 output pin. The way in which the CTM0 output pin changes state are determined by the condition of the CT0IO1 and CT0IO0 bits in the CTM0C1 register. The CTM0 output pin can be selected using the CT0IO1 and CT0IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTM0 output pin, which is setup after the CT0ON bit changes from low to high, is setup using the CT0OC bit. Note that if the CT0IO1 and CT0IO0 bits are zero then no pin change will take place. Rev. 1.40 80 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver 0x3FF CT0CCLR= 0; CT0�[1:0] = 00 Counter overflow Counter Value CCRP > 0 Counter cleared b� CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time CT0ON CT0PAU CT0POL CCRP Int. Flag CT�P0F CCRA Int. Flag CT�A0F CT�0 O/P Pin Output Pin set to Initial Level Low if CT0OC= 0 Output Toggle with CT�A0F flag Now CT0IO[1:0] = 10 Active High Output Select Output inverts when CT0POL is high Output Pin Reset to initial value Output not affected b� CT�A0F flag. Remains High until reset b� CT0ON bit Output controlled b� other pin-shared function Here CT0IO[1:0] = 11 Toggle Output Select Compare Match Match Output - CT0CCLR=0 Compare OutputMode Mode - CT0CCLR= 0 Note: 1. With CT0CCLR = 0, a Comparator P match will clear the counter 2. The CTM0 output pin controlled only by the CTMA0F flag 3. The output pin reset to initial state by a CT0ON bit rising edge Rev. 1.40 81 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CT0CCLR = 1; CT0�[1:0] = 00 Counter Value CCRA > 0 Counter cleared b� CCRA value 0x3FF Resume CCRA CCRA = 0 Counter overflow CCRA = 0 Pause CCRP Stop Counter Reset Time CT0ON CT0PAU CT0POL No CT�A0F flag generated on CCRA overflow CCRA Int. Flag CT�A0F CCRP Int. Flag CT�P0F CT�0 O/P Pin Output does not change CT�P0F not generated Output not affected b� Output Pin set to Initial Level Low if CT0OC= 0 Output Toggle with CT�A0F flag Output inverts when CT0POL is high Output Pin Reset to initial value Output controlled b� other pin- shared function CT�A0F flag. Remains High Now CT0IO[1:0] = 10 Active High Output Select Here CT0IO[1:0] = 11 Toggle Output Select until reset b� CT0ON bit Compare Match Output Mode - CT0CCLR=1 Compare Match Output Mode - C0TCCLR = 1 Note: 1. With CT0CCLR = 1, a Comparator A match will clear the counter 2. The CTM0 output pin controlled only by the CTMA0F flag 3. The output pin reset to initial state by a CT0ON rising edge 4. The CTMP0F flags is not generated when CT0CCLR = 1 Rev. 1.40 82 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Timer/Counter Mode To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM0 output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTM0 output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register should be set to 10 respectively. The PWM function within the CTM0 is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTM0 output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CT0CCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CT0DPX bit in the CTM0C1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CT0OC bit In the CTM0C1 register is used to select the required polarity of the PWM waveform while the two CT0IO1 and CT0IO0 bits are used to enable the PWM output or to force the CTM0 output pin to a fixed high or low level. The CT0POL bit is used to reverse the polarity of the PWM output waveform. CTM, PWM Mode, Edge-aligned Mode, CT0DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, CTM0 clock source is fSYS/4, CCRP = 100b, CCRA =128, The CTM0 PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, CT0DPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the CTM0 clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.40 83 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value CT0DPX=0;CT0M[1:0]=10 CounterCleared byCCRP Counterresetwhen CT0ONreturnshigh CCRP Pause Resume CCRA CounterStopIf CT0ONbitlow Time CT0ON CT0PAU CT0POL CCRAInt. FlagCTMA0F CCRPInt. FlagCTMP0F CTM0O/PPin (CT0OC=1) CTM0O/PPin (CT0OC=0) PWMDutyCycle setbyCCRA Outputcontrolledby Otherpin-sharedfunction PWMresumes operation OutputInverts WhenCT0POL=1 PWMPeriod setbyCCRP PWM ModeMode – CT0DPX =0 =0 PWM –CT0DPX Note: 1. Here CT0DPX = 0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when CT0IO[1:0] = 00 or 01 4. The CT0CCLR bit has no influence on PWM operation Rev. 1.40 84 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value CT0DPX=1;CT0M[1:0]=10 CounterCleared byCCRA Counterresetwhen CT0ONreturnshigh CCRA Pause Resume CCRP CounterStopIf CT0ONbitlow Time CT0ON CT0PAU CT0POL CCRPInt. FlagCTMP0F CCRAInt. FlagCTMA0F CTM0O/PPin (CT0OC=1) CTM0O/PPin (CT0OC=0) PWMDutyCycle setbyCCRP Outputcontrolledby Otherpin-sharedfunction PWMresumes operation OutputInverts WhenCT0POL=1 PWMPeriod setbyCCRA PWM Mode – CT0DPX = 1 PWM Mode–CT0DPX = 1 Note: 1. Here CT0DPX = 1 - Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CT0IO[1:0] = 00 or 01 4. The CT0CCLR bit has no influence on PWM operation Rev. 1.40 85 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Periodic Type TM – PTM0 The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with one external input pin and can drive two external output pins. Periodic Type TM Block Diagram Periodic TM Operation At the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bit wide. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PT0ON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM0 interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.40 86 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA value and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTM0C0 PT0PAU PT0CK2 PT0CK1 PT0CK0 PT0ON — — — PTM0C1 PT0M1 PT0M0 PT0IO1 PT0IO0 PT0OC PT0POL PT0CKS PT0CCLR PTM0DL D7 D6 D5 D4 D3 D2 D1 D0 PTM0DH — — — — — — D9 D8 PTM0AL D7 D6 D5 D4 D3 D2 D1 D0 PTM0AH — — — — — — D9 D8 PTM0RPL D7 D6 D5 D4 D3 D2 D1 D0 PTM0RPH — — — — — — D9 D8 10-bit Periodic TM Register List PTM0C0 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PT0PAU PT0CK2 PT0CK1 PT0CK0 PT0ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PT0PAU: PTM0 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM1 will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6 ~ 4 PT0CK2 ~ PT0CK0: Select PTM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the PTM0. The external pin clock source can be chosen to be active on the rasing or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. 87 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 3 PT0ON: PTM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTM0. Setting the bit high enables the counter to run, clearing the bit disables the PTM0. Clearing this bit to zero will stop the counter from counting and turn off the PTM0 which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM0 is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PT0OC bit, when the PT0ON bit changes from low to high. Bit 2 ~ 0 Unimplemented, read as "0" PTM0C1 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PT0M1 PT0M0 PT0IO1 PT0IO0 PT0OC PT0POL PT0CKS PT0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6 PT0M1~PT0M0: Select PTM0 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM0. To ensure reliable operation the PTM0 should be switched off before any changes are made to the bits. In the Timer/Counter Mode, the PTM0 output pin state is undefined. Bit 5 ~ 4 PT0IO1~PT0IO0: Select TP1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0, TP1_1 or TCK1 01: Input capture at falling edge of TP1_0, TP1_1 or TCK1 10: Input capture at falling/rising edge of TP1_0, TP1_1 or TCK1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the PTM0 output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM0 is running. 88 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver In the Compare Match Output Mode, the PT0IO1~PT0IO0 bits determine how the PTM0 output pin changes state when a compare match occurs from the Comparator A. The PTM0 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the PT0IO1~PT0IO0 bits are both zero, then no change will take place on the output. The initial value of the PTM0 output pin should be setup using the PT0OC bit in the PTM0C1 register. Note that the output level requested by the PT0IO1~PT0IO0 bits must be different from the initial value setup using the PT0OC bit otherwise no change will occur on the PTM1 output pin when a compare match occurs. After the PTM0 output pin changes state it can be reset to its initial level by changing the level of the PT0ON bit from low to high. In the PWM Mode, the PT0IO1 and PT0IO0 bits determine how the PTM0 output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the PT0IO1 and PT0IO0 bits only after the PTM0 has been switched off. Unpredictable PWM outputs will occur if the PT0IO1 and PT0IO0 bits are changed when the PTM0 is running. Rev. 1.40 Bit 3 PT0OC: TP1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM0 output pin. Its operation depends upon whether PTM0 is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the PTM0 is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM0 output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 PT0POL: TP1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTM0 output pin. When the bit is set high the PTM0 output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM0 is in the Timer/Counter Mode. Bit 1 PT0CKS: PTM0 capture trigger source select 0: From TP1_0, TP1_1 1: From TCK1 Bit 0 PT0CCLR: Select PTM0 Counter clear condition 0: PTM0 Comparatror P match 1: PTM0 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PT0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PT0CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. 89 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver PTM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 PTM0 Counter Low Byte Register bit 7 ~ bit 0 PTM0 10-bit Counter bit 7 ~ bit 0 PTM0DH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 Counter High Byte Register bit 1 ~ bit 0 PTM0 10-bit Counter bit 9 ~ bit 8 PTM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 PTM0 CCRA Low Byte Register bit 7 ~ bit 0 PTM0 10-bit CCRA bit 7 ~ bit 0 PTM0AH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 CCRA High Byte Register bit 1 ~ bit 0 PTM0 10-bit CCRA bit 9 ~ bit 8 PTM0RPL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 Rev. 1.40 PTM0 CCRP Low Byte Register bit 7 ~ bit 0 PTM0 10-bit CCRP bit 7 ~ bit 0 90 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver PTM0RPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 CCRP High Byte Register bit 1 ~ bit 0 PTM0 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PT0M1 and PT0M0 bits in the PTM0C1 register. Compare Match Output Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PT0CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMA0F and PTMP0F interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PT0CCLR bit in the PTM0C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PT0CCLR is high no PTMP0F interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMA0F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTM0 output pin, will change state. The PTM0 output pin condition however only changes state when a PTMA0F interrupt request flag is generated after a compare match occurs from Comparator A. The PTMP0F interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM0 output pin. The way in which the PTM0 output pin changes state are determined by the condition of the PT0IO1 and PT0IO0 bits in the PTM0C1 register. The PTM0 output pin can be selected using the PT0IO1 and PT0IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM0 output pin, which is setup after the PT0ON bit changes from low to high, is setup using the PT0OC bit. Note that if the PT0IO1 and PT0IO0 bits are zero then no pin change will take place. Rev. 1.40 91 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value Counter overflow CCRP=0 0x3FF PT0CCLR = 0; PT0� [1:0] = 00 CCRP > 0 Counter cleared b� CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time PT0ON PT0PAU PT0POL CCRP Int. Flag PT�P0F CCRA Int. Flag PT�A0F PT�0 O/P Pin Output pin set to initial Level Low if PT0OC=0 Output not affected b� PT�A0F flag. Remains High until reset b� PT0ON bit Output Toggle with PT�A0F flag Here PT0IO [1:0] = 11 Toggle Output select Note PT0IO [1:0] = 10 Active High Output select Output Inverts when PT0POL is high Output Pin Reset to Initial value un-defined Compare Match Output Mode – PT0CCLR=0 Note: 1. With PT0CCLR=0 a Comparator P match will clear the counter 2. The PTM0 output pin is controlled only by the PTMA0F flag 3. The output pin is reset to itsinitial state by a PT0ON bit rising edge Rev. 1.40 92 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value PT0CCLR = 1; PT0� [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared b� CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PT0ON PT0PAU PT0POL No PT�A0F flag generated on CCRA overflow CCRA Int. Flag PT�A0F CCRP Int. Flag PT�P0F PT�0 O/P Pin PT�P0F not generated Output pin set to initial Level Low if PT0OC=0 Output does not change Output Toggle with PT�A0F flag Here PT0IO [1:0] = 11 Toggle Output select Output not affected b� PT�A0F flag. Remains High until reset b� PT0ON bit Note PT0IO [1:0] = 10 Active High Output select Output Inverts when PT0POL is high Output Pin Reset to Initial value Output controlled b� other pin-shared function Compare Match Output Mode – PT0CCLR=1 Note: 1. With PT0CCLR=1 a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMA0F flag 3. The output pin is reset to its initial state by a PT0ON bit rising edge 4. A PTMP0F flag is not generated when PT0CCLR=1 Rev. 1.40 93 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Timer/Counter Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM0 output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. PWM Output Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 10 respectively. The PWM function within the PTM0 is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM0 output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PT0CCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PT0OC bit in the PTM0C1 register is used to select the required polarity of the PWM waveform while the two PT0IO1 and PT0IO0 bits are used to enable the PWM output or to force the PTM0 output pin to a fixed high or low level. The PT0POL bit is used to reverse the polarity of the PWM output waveform. 10-bit PTM, PWM Mode, Edge-aligned Mode CCRP 1~1023 Period 1~1023 Duty 0 1024 CCRA If fSYS = 16MHz, PTM0 clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM0 PWM output frequency = (fSYS/4) /512 = fSYS/2048 =7.8125kHz, duty = 128/512 = 25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.40 94 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value PT0� [1:0] = 10 Counter cleared b� CCRP Counter Reset when PT0ON returns high CCRP Pause Resume CCRA Counter Stop if PT0ON bit low Time PT0ON PT0PAU PT0POL CCRA Int. Flag PT�A0F CCRP Int. Flag PT�P0F PT�0 O/P Pin (PT0OC=1) PT�0 O/P Pin (PT0OC=0) PW� Dut� C�cle set b� CCRA PW� Period set b� CCRP PW� resumes operation Output controlled b� Output Inverts other pin-shared function When PT0POL = 1 PWM Output Mode Note: 1. A counter clear sets the PWM Period 2. The internal PWM function continues running even when PT0IO [1:0] = 00 or 01 3. The PT0CCLR bit has no influence on PWM operation Rev. 1.40 95 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Single Pulse Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 10 respectively and also the PT0IO1 and PT0IO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM0 output pin. The trigger for the pulse output leading edge is a low to high transition of the PT0ON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PT0ON bit can also be made to automatically change from low to high using the external TCK1 pin, which will in turn initiate the Single Pulse output. When the PT0ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PT0ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PT0ON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PT0ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM0 interrupt. The counter can only be reset back to zero when the PT0ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PT0CCLR bit is not used in this Mode. Single Pulse Generation Rev. 1.40 96 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value PT0� [1:0] = 10 ; PT0IO [1:0] = 11 Counter stopped b� CCRA Counter Reset when PT0ON returns high CCRA Pause Counter Stops b� software Resume CCRP Time PT0ON Software Trigger Auto. set b� TCK1 pin Cleared b� CCRA match TCK1 pin Software Trigger Software Trigger Software Software Trigger Clear TCK1 pin Trigger PT0PAU PT0POL No CCRP Interrupts generated CCRP Int. Flag PT�P0F CCRA Int. Flag PT�A0F PT�0 O/P Pin (PT0OC=1) PT�0 O/P Pin (PT0OC=0) Output Inverts when PT0POL = 1 Pulse Width set b� CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCK1 pin or by setting the PT0ON bit high 4. A TCK1 pin active edge will automatically set the PT0ON bit hight 5. In the Single Pulse Mode, PT0IO [1:0] must be set to "11" and can not be changed. Rev. 1.40 97 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Capture Input Mode To select this mode bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TP1_0, TP1_1 or TCK1 pin which is selected using the PT0CKS bit in the PTM0C1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PT0IO1 and PT0IO0 bits in the PTM0C1 register. The counter is started when the PT0ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TP1_0, TP1_1 or TCK1 pin the present value in the counter will be latched into the CCRA registers and a PTM0 interrupt generated. Irrespective of what events occur on the TP1_0, TP1_1 or TCK1 pin, the counter will continue to free run until the PT0ON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM0 interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PT0IO1 and PT0IO0 bits can select the active trigger edge on the TP1_0, TP1_1 or TCK1 pin to be a rising edge, falling edge or both edge types. If the PT0IO1 and PT0IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TP1_0, TP1_1 or TCK1 pin, however it must be noted that the counter will continue to run. As the TP1_0, TP1_1 or TCK1 pin is pin shared with other functions, care must be taken if the PTM0 is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PT0CCLR, PT0OC and PT0POL bits are not used in this Mode. Rev. 1.40 98 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Counter Value PT0� [1:0] = 01 Counter cleared b� CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time PT0ON PT0PAU PT�0 capture pin TP1_0�TP1_1 or TCK1 Active edge Active edge Active edge CCRA Int. Flag PT�A0F CCRP Int. Flag PT�P0F CCRA Value PT0IO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. PT0M [1:0] = 01 and active edge set by the PT0IO [1:0] bits 2. A PTM0 Capture input pin active edge transfers the counter value to CCRA 3. PT0CCLR bit not used 4. No output function – PT0OC and PT0POL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.40 99 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin shared with the PA ~ PD logic I/O pins, with the desired function chosen via register bits. Keys are organised into several groups, with each group known as a module and having a module number, M0 to Mn. Each module is a fully independent set of four Touch Keys and each Touch Key has its own oscillator. Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device BS82B12A-3 BS82C16A-3 BS82D20A-3 Keys - n Touch Key Module Touch Key Shared I/O Pin M0 Key1~Key4 PB0~PB3 M1 Key5~Key8 PB4~PB7 M2 Key9~Key12 PC0~PC3 M0 Key1~Key4 PB0~PB3 M1 Key5~Key8 PB4~PB7 M2 Key9~Key12 PC0~PC3 M3 Key13~Key16 PC4~PC7 M0 Key1~Key4 PB0~PB3 M1 Key5~Key8 PB4~PB7 M2 Key9~Key12 PD3, PD2, PC0, PC1 M3 Key13~Key16 PC2~PC5 Key17~Key20 PC6, PC7, PA4, PA1 12 16 20 M4 Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the Touch Key module number, the BS82B12A-3 has a range of M0 to M2, the BS82C16A-3 has a range of M0 to M3, the BS82D20A-3 has a range of M0 to M4. Name TKTMR TKC0 Usage Touch Key 8-bit timer/counter register Counter on-off and clear control/reference clock control/Start bit TK16DL Touch key module 16-bit counter low byte contents TK16DH Touch key module 16-bit counter high byte contents TKC1 Touch key OSC frequency select TKMn16DL Module n 16-bit counter low byte contents TKMn16DH Module n 16-bit counter high byte contents TKMnROL Reference OSC internal capacitor select TKMnROH Reference OSC internal capacitor select TKMnC0 Control Register 0 Multiplexer Key Select TKMnC1 Control Register 1 Key oscillator control/Reference oscillator control/ Touch key or I/O select Register Listing (n=0~4) Rev. 1.40 100 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit Register Name 7 6 5 4 3 2 1 0 TKTMR D7 D6 D5 D4 D3 D2 D1 D0 TKC0 — TKRCOV TKST TSCS TK16S1 TK16S0 TK16DL D7 D6 D5 TKCFOV TK16OV D4 D3 D2 D1 D0 TK16DH D15 D14 D13 D12 D11 D10 D9 D8 TKC1 — — — — — — TKFS1 TKFS0 TKMn16DL D7 D6 D5 D4 D3 D2 D1 D0 TKMn16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMnROL D7 D6 D5 D4 D3 D2 D1 D0 TKMnROH — — — — — — D9 D8 TKMnC0 MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 TKMnC1 MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnK2IO MnK1IO Touch Key Module (n=0~4) TKTMR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch Key 8-bit timer/counter register Time slot counter overflow set-up time is (256-TKTMR[7:0])×32 TKC0 Register Bit 7 6 5 4 3 2 1 0 Name — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6TKRCOV: Time slot counter overflow flag 0: No overflow 1: Overflow If module 0 or all module time slot counter, selected by the TSCS bit, is overflow, the Touch Key Interrupt request flag, TKMF, will be set and all module key OSCs and ref OSCs auto stop. All module 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched off. Bit 5TKST: Start Touch Key detection control bit 0: Stopped 0->1: Started In all modules the16-bit C/F counter, 16-bit counter, 5-bit time slot counter will be automatically cleared when this bit is cleared to zero (8-bit programmable time slot counter will not be cleared, which overflow time is setup by user). When this bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key OSC and ref OSC output clock input to these counters. Bit 4TKCFOV: Touch key module 16-bit C/F counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by application program. Rev. 1.40 101 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 3TK16OV: Touch key module 16-bit counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by application program. Bit 2TSCS: Touch Key time slot counter select 0: Each Module uses its own time slot counter. 1: All Touch Key Module use Module 0 time slot counter. Bit 1~0 TK16S1~ TK16S0: The touch key module 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 TKC1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — TKFS1 TKFS0 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit 7 ~2 Unimplemented, read as "0" Bit 1~0TKFS1~TKFS0: Touch key OSC frequency select 00: 500kHz 01: 1000 kHz 10: 1500 kHz 11: 2000 kHz TK16DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter low byte contents TK16DH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter high byte contents TKMn16DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 Module n 16-bit counter low byte contents 102 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver TKMn16DH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Module n 16-bit counter high byte contents TKMnROL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Reference OSC inernal capacitor select OSC inernal capacitor select : (TKMnRO[9:0] × 50pF) / 1024 TKMnROH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 Reference OSC inernal capacitor select OSC inernal capacitor select: (TKMnRO[9:0] × 50pF) / 1024 TKMnC0 Register Bit Name 7 6 5 4 3 2 MnSOF1 MnSOF0 R/W MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~6MnMXS1~MnMXS0: Multiplexer Key Select Bit Module Number MnMXS1 MnMXS0 M0 M1 M2 M3 M4 0 0 Key 1 Key 5 Key 9 Key 13 Key 17 0 1 Key 2 Key 6 Key 10 Key 14 Key 18 1 0 Key 3 Key 7 Key 11 Key 15 Key 19 1 1 Key 4 Key 8 Key 12 Key 16 Key 20 Bit 5MnDFEN: Multi-frequency control 0: Disable 1: Enable Bit 4MnFILEN: Filter function control 0: Disable 1: Enable Bit3MnSOFC: C to F OSC frequency hopping function control 0: The frequency hopping function is controlled by MnSOF2 ~ MnSOF0 bits 1: The frequency hopping function is controlled by hardware regardless of what is the state of MnSOF2~ MnSOF0 bits Rev. 1.40 103 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 2~0 MnSOF2 ~ MnSOF0: Slelecting key OSC and ref OSC frequency as C to F OSC is controlled by software 000: 1380kHz 001: 1500kHz 010: 1670kHz 011: 1830kHz 100: 2000kHz 101: 2230kHz 110: 2460kHz 111: 2740kHz The frequency which is mentioned here willl be changed when the external or internal capacitor is with different value. If the touch key operates at a frequency of 2MHz, users can adjust the frequency in scale when select other frequency. TKMnC1 Register Bit 7 6 Name MnTSS — 5 4 R/W R/W — R/W POR 0 — 0 3 2 1 0 MnK4IO MnK3IO MnK2IO MnK1IO R/W R/W R/W R/W R/W 0 0 0 0 0 MnROEN MnKOEN Bit 7 MnTSS: Time slot counter clock select 0: Reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5MnROEN: Reference OSC control 0: Disable 1: Enable Bit 4 MnKOEN: Key OSC control 0: Disable 1: Enable Bit 3~0 MnK4IO~ MnK1IO: I/O pin or touch key function select MnK4IO M1 M2 PC3/Key 12 PB3/Key 4 PB7/Key 8 or PC1/Key 12 0 I/O 1 Touch key MnK3IO M0 M1 I/O 1 Touch key M0 M1 0 I/O Touch key M0 M1 PB0/Key 1 PB4/Key 5 M4 PA1/Key 20 M3 M4 PC6/Key15 or PC4/Key 15 PA4/Key 19 M3 M4 M2 PC1/Key 10 PB1/Key 2 PB5/Key 6 or PD2/Key 10 1 MnK1IO M3 PC7/Key 16 or PC5/Key 16 M2 PC2/Key 11 PB2/Key 3 PB6/Key 7 or PC0/Key 11 0 MnK2IO Rev. 1.40 M0 PC5/Key 14 PC7/Key 18 or PC3/Key 14 M2 PC0/Key 9 or PD3/Key 9 M3 0 I/O 1 Touch key input 104 M4 PC4/Key 13 PC6/Key 17 or PC2/Key 13 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. Each touch key module contains four touch key inputs which are shared logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be generated. Using the TSCS bit in the TKC0 register can select the module 0 time slot counter as the time slot counter for all modules. All modules use the same started signal. The16-bit C/F counter, 16-bit counter, 5-bit time slot counter in all modules will be automatically cleared when this bit is cleared to zero, but the 8-bit programmable time slot counter will not be cleared. The overflow time is setup by user. When this bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched off when the 5-bit time slot counter overflows. The clock source for the time slot counter and 8+5 bit counter, is sourced from the reference oscillator or fSYS/4. The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, Key1 ~ Key4 are contained in module 0, Key5 ~ Key8 are contained in module 1, Key9 ~ Key12 are contained in module 2, Key13 ~ Key16 are contained in the module 3 and Key17 ~ Key20 are contained in the module 4. Each touch key module has an identical structure. Rev. 1.40 105 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver KEY 1 KEY OSC KEY � KEY OSC �UX. KEY 3 KEY OSC KEY 4 KEY OSC fSYS�fSYS/��fSYS/4�fSYS/8 Filter 1�-bit C/F counter �ultifrequenc� Overflow Overflow 1�-bit counter TK1�S1~TK1�S0 �nTSS üüü �UX. fSYS/4 8-bit time slot timer counter �-bit time slot counter 8-bit time slot timer counter preload register Overflow Overflow Note: 1. Each touch key module contains the content in the red dash line. 2. The content in the black dash line is the module number (0~n). Each module contains 4 touch keys. Touch Key Module Block Diagram Rev. 1.40 106 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver The touch key sense oscilltor and reference oscillator timing diagram is shown in the following figure: TKST �nKOEN �nROEN Hardware clear to "0" KEY OSC CLK Reference OSC CLK (���-TKT�R) overflow *3� fCFT�CK enable fCFT�CK (�nDFEN=0) fCFT�CK (�nDFEN=1) TKRCOV Set Touch Ke� interrupt request flag Touch Key or I/O Function Select Rev. 1.40 107 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Touch Key Interrupt The touch key only has single interrupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot counter in all modules will be automatically cleared. The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the Touch Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. Module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter overflow flag, will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. More details regarding the touch key interrupt is located in the interrupt section of the datasheet. Programming Considerations After the relevant registers are setup, the touch key detection process is initiated the changing the TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag, which is the time slot counter flag will go high and remain high until the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. Rev. 1.40 108 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master/Slave Bus Connection I C Block Diagram 2 I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. It is suggested that the user shall not enter the micro processor to HALT status by application program during processing I2C communication. If the pin is configured to SDA or SCL function of I2C interface, the pin is configured to open-collect Input/Output port and its Pull-high function can be enabled by programming the related Generic Pull-high Control Register. Rev. 1.40 109 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r The I2CDBNC1 and I2CDBNC0 Bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Debounce fSYS > 2MHz fSYS > 5MHz 2 system clock debounce fSYS > 4MHz fSYS > 10MHz 4 system clock debounce fSYS > 8MHz fSYS > 20MHz I C Minimum fSYS Frequency 2 I2C Registers There are four control registers associated with the I2C bus, IICC0, IICC1, IICA and I2CTOC and one data register, IICD. The IICD register is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register. After the data is received from the I2C bus, the microcontroller can read it from the IICD register. Any transmission or reception of data from the I2C bus must be made via the IICD register. Bit Register Name 7 6 5 4 IICC0 — — — — IICC1 IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICD IICD7 IICD6 IICD5 IICD4 IICD3 IICD2 IICA IICA6 IICA5 IICA4 IICA3 I2CTOC I2CTOEN I2CTOF I2CTOS5 I2CTOS4 3 2 I2CDBNC1 I2CDBNC0 IICA2 IICA1 I2CTOS3 I2CTOS2 1 0 IICEN — IICAMWU IICRXAK IICD1 IICD0 IICA0 — I2CTOS1 I2CTOS0 I2C Registers List Rev. 1.40 110 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver IICC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — I2CDBNC1 I2CDBNC0 IICEN — R/W — — — — R/W R/W R/W — POR — — — — 0 0 0 — Bit 7~4 Unimplemented, read as "0" Bit 3~2I2CDBNC1~I2CDBNC0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce Bit 1 Bit 0 IICEN: I2C Control 0: Disable 1: Enable Unimplemented, read as "0" The I2C function could be turned off or turned on by controlling the bit IICEN. When the pinshared I/O ports are chosen to be the functions other than SDA and SCL by clearing the IICEN bit to zero, the I2C function is turned off and its operating current will be reduced to a minimum value. In contrary, the I2C function is turned on when the pin-shared I/O ports are chosen to be the SDA and SCL pins by setting the IICEN bit high. IICC1 Register Bit 7 6 5 4 3 2 Name IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW 1 0 R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 IICAMWU IICRXAK Bit 7 IICHCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The IICHCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Below is an example of the flow of a two-byte I2C data transfer. First, the I2C slave device receives a start signal from the I2C master and then the IICHCF bit is automatically cleared to zero. Second, the I2C slave device finishes receiving the 1st data byte and then the IICHCF bit is automatically set to one. Third, users read the 1st data byte from the IICD register by the application program and then the IICHCF bit is automatically cleared to zero. Fourth, the I2C slave device finishes receiving the 2nd data byte and then the IICHCF bit is automatically set high and so on. Finally, the I2C slave device receives a stop signal from the I2C master and then the IICHCF bit is automatically set high. Bit 6IICHAAS: I2C Bus address match flag 0: Not address match 1: Address match The IICHASS flag is the address match flag. This flag is used to determine if the slave device address is same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Rev. 1.40 111 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 5IICHBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The IICHBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4IICHTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 IICTXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The IICTXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always clear the IICTXAK bit to zero before further data is received. Bit 2 IICSRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The IICSRW flag is the I2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the IICHAAS flag is set high, the slave device will check the IICSRW flag to determine whether it should be in transmit mode or receive mode. If the IICSRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the IICSRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IICAMWU: I2C Address Match Control 0: Disable 1: Enable – must be cleared by the application program after wake-up. This Bit should be set to “1” to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU Bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this Bit must be cleared by application program after wake-up to ensure correction device operation. Bit 0 Rev. 1.40 IICRXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The IICRXAK flag is the receiver acknowledge flag. When the IICRXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the IICRXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the IICRXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. 112 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver I2CTOC Register Bit 7 6 Name I2CTOEN I2CTOF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 5 4 3 2 1 0 I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 I2CTOEN: I2C Time-out Countrol 0: Disable 1: Enable Bit 6IICTOF: I2C Time-out flag 0: No time-out occurred 1: Time-out occurred This bit is set high when time-out occurs and can only be cleared by application program. Bit 5~0I2CTOS5~I2CTOS0: I2C Time-out period selection I2C time-out clock source is fSUB/32. I2C time-out period is equal to (I2CTOS[5 : 0]+1) × (32/fSUB) The IICD register is used to store the data being transmitted and received. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register. After the data is received from the I2C bus, the device can read it from the IICD register. Any transmission or reception of data from the I2C bus must be made via the IICD register. IICD Register Bit 7 6 5 4 3 2 1 0 Name IICD7 IICD6 IICD5 IICD4 IICD3 IICD2 IICD1 IICD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown IICA Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — Bit 7~1 IICA6~IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6 ~ bit 0. The IICA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. Bit 0 Unimplemented, read as "0" 113 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the IICHAAS bit in the IICC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the IICHAAS and I2CTOF bits to determine whether the interrupt source originates from an address match or from an I2C communication time-out or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the IICSRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the IICEN bit in the IICC0 register high to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register IICA. • Step 3 Set the IICE interrupt enable bit of the interrupt control register to enable the I2C interrupt. I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the IICHBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Rev. 1.40 114 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the IICSRW bit of the IICC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag IICHAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the IICHAAS and I2CTOF bits should be examined to see whether the interrupt source has come from a matching slave address or from an I2C communication time-out or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Bus Read/Write Signal The IICSRW bit in the IICC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the IICSRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the IICSRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the IICHAAS flag is high, the addresses have matched and the slave device must check the IICSRW flag to determine if it is to be a transmitter or a receiver. If the IICSRW flag is high, the slave device should be setup to be a transmitter so the IICHTX bit in the IICC1 register should be set high. If the IICSRW flag is low, then the microcontroller slave device should be setup as a receiver and the IICHTX bit in the IICC1 register should be cleared to zero. I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the IICD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the IICD register. If setup as a receiver, the slave device must read the transmitted data from the IICD register. Rev. 1.40 115 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver When the slave receiver receives the data byte, it must generate an acknowledge bit, known as IICTXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the IICRXAK bit in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Communication Timing Diagram I2C Bus ISR Flow Chart Rev. 1.40 116 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver I2C Interface Time-out Function In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, clock, a time-out function is provided. If the clock source to the I2C is not received then after a fixed time period, the I2C circuitry and registers will be reset. I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the I2CTOEN bit will be cleared to zero and the I2CTOF bit will be set high to indicate that a time-out condition as occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out IICD, IICA, IICC0 No change IICC1 Reset to POR condition I2C Registers After Time-out The I2CTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using bits in the I2CTOC register. The time-out time is given by the formula: ((1~64) × 32) / fSUB This gives a range of about 1ms to 64ms. Rev. 1.40 117 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UART Interface The devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Transmitter and receiver enabled independently • 2-byte Deep FIFO Receive Data Buffer • Transmit and Receive Multiple Interrupt Generation Sources: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect ♦♦ RX pin wake-up interrupt (RX enable, RX falling edge) UART External Pin Interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX or RX pins. When the TX or RX pin function is disabled by clearing the UARTEN and TXEN or RXEN bit, the TX or RX pin can be used as a general purpose I/O or other pin-shared functional pin. Rev. 1.40 118 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. �SB Transmitter Shift Register ………………………… LSB TX Pin CLK RX Pin �SB LSB CLK Baud Rate Generator TXR Register Receiver Shift Register ………………………… RXR Register Buffer �CU Data Bus UART Data Transfer Scheme UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR_ RXR data register. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR_RXR TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 BRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 UART Register List Rev. 1.40 119 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below. Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Rev. 1.40 120 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty. When the flag is "1", it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. Rev. 1.40 121 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x" unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be as General Purpose I/ O or other pin-shared functional pins. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Note: 1. If BNO=1 (9-bit data transfer), parity function is enabled, the 9th bit of data is the parity bit which will not be transferred to RX8. 2. If BNO=0 (8-bit data transfer), parity function is enabled, the 8th bit of data is the parity bit which will not be transferred to RX7. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. Bit 3STOPS: Number of stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used for the TX pin. When this bit is equal to "1", two stop bits are used. If this bit is equal to "0", then only one stop bit is used. Rev. 1.40 122 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is "0", there are no break characters and the TX pin operates normally. When the bit is "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE R/W R/W R/W R/W R/W R/W RIE TIIE TEIE R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin. Rev. 1.40 123 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to "1", the high speed mode is selected. If the bit is equal to "0", the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to "1", the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to "1" and the device is in the IDLE0 or SLEEP mode, a falling edge on the RX input pin will wake-up the device. If this bit is equal to "0" and the device is in the IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to "1" and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TXIF flag. Rev. 1.40 124 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver TXR_RXR register The TXR_RXRn register is the data register which is used to store the data to be transmitted on the TXn pin or being received from the RXn pin. Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bit 7 ~ bit 0 Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS / [64 (N+1)] fSYS / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Rev. 1.40 125 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to "0" determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = fSYS / [64 (N+1)] Re-arranging this equation gives N = [fSYS / (BR×64)] - 1 Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR = 4000000 / [64× (12 + 1)] = 4808 Therefore the error is equal to (4808 - 4800) / 4800 = 0.16% The following table shows actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS fSYS=8MHz Baud Rates for BRGH=0 BRG Kbaud Baud Rates for BRGH=1 Error (%) BRG Kbaud Error (%) 0.3 — — — — — — 1.2 103 1.202 0.16 — — — 2.4 51 2.404 0.16 207 2.404 0.16 4.8 25 4.808 0.16 103 4.808 0.16 9.6 12 9.615 0.16 51 9.615 0.16 19.2 6 17.8857 -6.99 25 19.231 0.16 38.4 2 41.667 8.51 12 38.462 0.16 57.6 1 62.500 8.51 8 55.556 -3.55 115.2 0 125 8.51 3 125 8.51 250 — — — 1 250 0 Baud Rates and Error Values UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Rev. 1.40 126 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length and are only to be used for Transmitter. There is only one stop bit for Receiver. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. 8-Bit Data Format 9-Bit Data Format Rev. 1.40 127 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/ O or other pin-shared function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF is "0", data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: • A USR register access • A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: • A USR register access • A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Rev. 1.40 128 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR register. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT and PREN bits to define the word length and parity type. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set when RXR register has data available, at least one character can be read. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. • The RXIF bit can be cleared using the following software sequence: • A USR register access • An RXR register read execution Rev. 1.40 129 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Receive Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and one STOPS bit. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and one STOP bit. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE bit is "1", when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE is "1". Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Rev. 1.40 130 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Noise Error – NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, only the first stop bit is detected, it must be high. If the first stop bit is low, the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error – PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN bit is "1", and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Rev. 1.40 131 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. USR Register UCR2 Register Transmitter Empty Flag TXIF TEIE Transmitter Idle Flag TIDLE TIIE 0 1 RIE 0 1 Receiver Overrun Flag OERR OR Receiver Data Available RXIF RX Pin Wake-up ADDEN WAKE 0 1 UART Interrupt Request Flag UARTF INTC0 Register INTC2 Register EMI UARTE 0 1 0 1 0 1 RX7 if BNO=0 RX8 if BNO=1 UCR2 Register UART Interrupt Scheme Address Detect Mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is "1", then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO bit is "1" or the 8th bit if BNO bit is "0". If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is "0", then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit PREN to zero. ADDEN 0 1 Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function Rev. 1.40 132 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver UART Power Down and Wake-up When the the device system clock is switched off, the UART will cease to function. If the device executes the "HALT" instruction and switches off the system clock while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the device executes the "HALT" instruction and switches off the system clock while receiving data, then the reception of data will likewise be paused. When the device enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the IDLE or SLEEP mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the device enters the IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the device from the IDLE0 or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, UARTE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.40 133 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Touch Action or Timer/Event Counter overflow requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The devices contain several external interrupt and internal interrupt functions. The external interrupt is generated by the action of the external INT pin and Touch Keys, while the internal interrupts are generated by various internal functions such as Timer Modules, Time Bases, I2C, LVD, EEPROM and UART. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The registers fall into two categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Notes Global EMI — — INT Pin INTE INTF — Touch Key Module TKME TKMF — IC IICE IICF — UART UARTE UARTF — EEPROM DEE DEF — LVD LVDE LVDF — Time Base TBnE TBnF n=0 or 1 CTMPnE CTMPnF n=0 PTMPnE PTMPnF n=0 CTMAnE CTMAnF n=0 PTMAnE PTMAnF n=0 2 TM Interrupt Register Bit Naming Conventions Interrupt Register Contents Rev. 1.40 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTEG — — — — — — INTS1 INTS0 TKME INTE EMI INTC0 — TB0F TKMF INTF TB0E INTC1 PTMA0F PTMP0F CTMA0F CTMP0F PTMA0E INTC2 UARTF DEF IICF TB1F UARTE DEE IICE TB1E INTC3 — — — LVDF — — — LVDE 134 PTMP0E CTMA0E CTMP0E May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — INTS1 INTS0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 INTS1, INTS0: Defines INT interrupt active edge 00: Disabled interrupt 01: Rising Edge interrupt 10: Falling Edge interrupt 11: Dual Edge interrupt INTC0 Register Bit 7 6 5 4 3 2 1 Name — TB0F TKMF INTF TB0E TKME INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 2 1 0 Bit 7 Unimplemented, read as "0" Bit 6 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 TKMF: Touch key module interrupt request flag 0: No request 1: Interrupt request Bit 4 INTF: INT pin interrupt request flag 0: No request 1: Interrupt request Bit 3 TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 2 TKME: Touch key module interrupt control 0: Disable 1: Enable Bit 1 INTE: INT pin interrupt control 0: Disable 1: Enable Bit 0EMI: Global Interrupt control 0: Disable 1: Enable INTC1 Register Rev. 1.40 Bit 7 6 5 4 3 Name PTMA0F PTMP0F CTMA0F CTMP0F PTMA0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTMP0E CTMA0E CTMP0E Bit 7 PTMA0F: PTM0 CCRA comparator interrupt request flag 0: No request 1: Interrupt request Bit 6 PTMP0F: PTM0 CCRP comparator interrupt request flag 0: No request 1: Interrupt request 135 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 5 CTMA0F: CTM0 CCRA comparator interrupt request flag 0: No request 1: Interrupt request Bit 4 CTMP0F: CTM0 CCRP comparator interrupt request flag 0: No request 1: Interrupt request Bit 3PTMA0E: PTM0 CCRA comparator interrupt control 0: Disable 1: Enable Bit 2PTMP0E: PTM0 CCRP comparator interrupt control 0: Disable 1: Enable Bit 1CTMA0E: CTM0 CCRA comparator interrupt control 0: Disable 1: Enable Bit 0CTMP0E: CTM0 CCRP comparator interrupt control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name UARTF DEF IICF TB1F UARTE DEE IICE TB1E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 UARTF: UART interrupt request flag 0: No request 1: Interrupt request Bit 6 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 5 IICF: I2C interrupt request flag 0: No request 1: Interrupt request Bit 4 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 UARTE: UART interrupt request control 0: Disable 1: Enable Rev. 1.40 Bit 2 DEE: Data EEPROM control 0: Disable 1: Enable Bit 1 IICE: I2C interrupt control 0: Disable 1: Enable Bit 0 TB1E: Time Base 1 interrupt control 0: Disable 1: Enable 136 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver INTC3 Register Bit 7 6 5 4 3 2 1 0 Name — — — LVDF — — — LVDE R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as "0" Bit 4 LVDF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3~1 Unimplemented, read as "0" Bit 0 LVDE: LVD interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a Touch Key Counter overflow, a TM Comparator P or Comparator A match, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Every interrupt source has its own individual vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.40 137 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver E�I auto disabled in ISR Legend xxF Request Flag� auto reset in ISR xxE Enable Bits Interrupt Name Request Flags Enable Bits �aster Enable Vector INT Pin INTF INTE E�I 04H Touch Ke� �odule TK�F TK�E E�I 08H Time Base 0 TB0F TB0E E�I 0CH CT�0 P CT�P0F CT�P0E E�I 10H CT�0 A CT�A0F CT�A0E E�I 14H PT�0 P PT�P0F PT�P0E E�I 18H PT�0 A PT�A0F PT�A0E E�I 1CH Time Base 1 TB1F TB1E E�I �0H I�C IICF IICE E�I �4H EEPRO� DEF DEE E�I �8H UART UARTF UARTE E�I �CH LVD LVDF LVDE E�I 30H Priorit� High Low Interrupt Structure External Interrupt The external interrupt is controlled by signal transitions on the pin INT. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.40 138 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Time Base Interrupts The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its timer function. When this happens its interrupt request flags TBnF will be set. To allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Each Time Base clock source originates from an independent internal prescaler. Each 15-bit prescaler can source from fSYS, fSYS/4, fSUB or fH, selected by CLKSELn1~CLKSELn0 bits in the PSCR register. PSCR Register Bit 7 6 Name — — R/W — — R/W POR — — 0 Bit 7~6 5 4 3 2 1 0 — — CLKSEL01 CLKSEL00 R/W — — R/W R/W 0 — — 0 0 CLKSEL11 CLKSEL10 Unimplemented, read as "0" Bit 5~4CLKSEL11 ~ CLKSEL10: Time Base 1 prescaler clock source selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH Bit 3~2 Unimplemented, read as "0" Bit 1~0CLKSEL01 ~ CLKSEL00: Time Base 0 prescaler clock source selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH TBC Register Bit 7 6 5 4 3 2 1 0 Name TB1ON TB12 TB11 TB10 TB0ON TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TB1ON: Time Base 1 enable/disable control 0: Disable 1: Enable Bit 6~4 Rev. 1.40 TB12 ~ TB10: Select Time Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC 139 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Bit 3 TB0ON: Time Base 0 enable/disable control 0: Disable 1: Enable Bit 2~0 TB02 ~ TB00: Select Time Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC fSUB fSYS Prescaler fSYS/4 fPSC TimeBasenInterrupt fH CLKSELn[1:0] TBnON TBn[2:0] Time Base Structure (n=0 or 1) TM Interrupts The Compact and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generates a TM interrupt when a compare match condition occurs. For each of the Compact and Periodic Type TMs, there are two interrupt request flags, CTMP0F/CTMA0F and PTMP0F/PTMA0F, and two enable bits, CTMP0E/CTMA0E and PTMP0E/PTMA0E. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A macth situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the respective TM interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM interrupt vector location, will take place. When the TM interrupt is serviced, the TM interrupt request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.40 140 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver LVD Interrupt An LVD Interrupt request will take place when the LVD Interrupt request flag, LVDF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low Voltage Interrupt enable bit, LVDE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the LVDF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Touch Key Interrupt For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt enable TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key request flag. TKMF, is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. I2C Interrupt An I2C Interrupt request will take place when the I2C Interrupt request flag, IICF, is set, which occurs when an address match occurs, or an I2C communication time-out occurs, or a byte of data has been received or transmitted by the I2C interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the I2C Interface Interrupt enable bit, IICE, must first be set. When the interrupt is enabled, the stack is not full and any these conditions are created, a subroutine call to the respective interrupt vector, will take place. When the I2C Interface Interrupt is serviced, the I2C interrupt request flag, IICF, will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. UART Interrupt Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, and UART interrupt enable bit, UARTE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the UART Interrupt vector will take place. When the interrupt is serviced, the UART Interrupt flag, UARTF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. Rev. 1.40 141 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin or a low power supply voltage may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.40 142 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SCOM and SSEG Function for LCD The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, SSEG0~SSEG19, are pin shared with certain pins on the I/O ports. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using the devices by configuring the I/O pins as common pins and configuring the I/O pins as segment pins. The LCD driver function is controlled using the LCD control registers which in addition to controlling the overall on/off function also controls the SCOM and SSEG operating current. This enables the LCD COM and SEG driver to generate the necessary VSS, (1/3)VDD, (2/3)VDD voltage and VDD levels for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver, however this bit is used in conjunction with the COMnEN and SEGnEN bits to select which I/O Port pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. LCD Driver Structure Rev. 1.40 143 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver The accompanying waveform diagram shows a typical 1/3 Bias LCD waveform generated using the application program. Note that the depiction of a "1" in the diagram illustrates an illuminated LCD pixel. The COM signal polarity generated on pins SCOM0~SCOM3, whether 0 or 1, are generated using the corresponding I/O data register bits, which are bits PA0~PA2, PA4 in the PA register. Note: The logical values shown in the diagram are the PA I/O register bit values, PA0~PA2, PA4. 1/3 Bias LCD Waveform Rev. 1.40 144 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver A cyclic LCD waveform includes two frames, known as Frame 0 and Frame 1 for which the following offers a functional explanation. In Frame 0 To select Frame 0 clear the FRAME bit to 0. In frame 0, the COM signal output can have a value of VDD, or have a Vbias value of (1/3)VDD. The SEG signal can have a value of VSS, or have a Vbias value of (2/3)VDD. In Frame 1 In frame 1, the COM signal output can have a value of VSS, or have a Vbias value of (2/3)VDD. The SEG signal can have a value of VDD have a Vbias value of (1/3)VDD. The COM0~COMn waveform is controlled by the application program using the FRAME bit, and the corresponding I/O data register for the respective COM pin to determine whether the COM0~COMn output has a value of either VDD, VSS or Vbias. The SEG0~SEGm waveform is controlled in a similar way using the FRAME bit and the corresponding I/O data register for the respective SEG pin to determine whether the SEG0~SEGn output has a value of either VDD, VSS or Vbias. LCD Bias Control The LCD COM and SEG driver enable a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SLCDC0 register. SLCDC0 Register Bit 7 6 5 4 Name FRAME ISEL1 ISEL0 LCDEN 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 COM3EN COM2EN COM1EN COM0EN FRAME: Fram 0 or Frame 1 output selection 0: Frame 0 1: Frame 1 Bit 6~5ISEL1~ISEL0: SCOM and SSEG operating current selection (VDD=5V) 00: 8.3μA 01: 16.7μA 10: 50μA 11: 100μA Bit 4LCDEN: SCOM and SSEG module on/off control 0: Disable 1: Enable The SCOMn and SSEGm lines can be enabled using COMnEN and SEGmEN if LCDEN=1. When LCDEN=0, then the SCOMn and SSEGm outputs will be fixed at a VSS level. Bit 3COM3EN: SCOM3 or other function selection 0: Other function 1: SCOM3 Bit 2COM2EN: SCOM2 or other function selection 0: Other function 1: SCOM2 Bit 1COM1EN: SCOM1 or other function selection 0: Other function 1: SCOM1 Bit 0COM0EN: SCOM0 or other function selection 0: Other function 1: SCOM0 Bit 7 Rev. 1.40 145 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SLCDC1 Register Bit Name 7 6 5 4 3 2 1 0 SEG7EN SEG6EN SEG5EN SEG4EN SEG3EN SEG2EN SEG1EN SEG0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0SEG7EN~SEG0EN: SSEG7 ~ SSEG0 or other function selection 0: Other function 1: SSEG7~SSEG0 SLCDC2 Register Bit Name 7 6 5 4 3 2 1 0 SEG15EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0SEG15EN~SEG8EN: SSEG15 ~ SSEG8 or other function selection 0: Other function 1: SSEG15~SSEG8 SLCDC3 Register – BS82C16A-3/BS82D20A-3 Bit 7 6 5 4 Name — — — — R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 3 2 1 0 SEG19EN SEG18EN SEG17EN SEG16EN Unimplemented, read as "0" Bit 3~0SEG19EN~SEG16EN: SSEG19 ~ SSEG16 or other function selection 0: Other function 1: SSEG19~SSEG16 Rev. 1.40 146 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enables the device to monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of five fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Rev. 1.40 Bit 3 Unimplemented, read as "0" Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Note: The VLVR of these three devices is fixed at 2.55V, so the VLVD should be set to 2.7V~4.0V. 147 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.7V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in SLEEP mode the low voltage detector will be automatically disabled even if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. In this case, the LVDF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVDF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.40 148 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Option 1 Low Speed System Oscillator Selection – fSUB: LIRC LXT 2 HIRC frequency selection: 8MHz 12MHz 16MHz Note: 1. The low speed system oscillator selection is only for the BS82C16A-3 and BS82D20A-3. 2. When the HIRC has been configurated at a frequency shown in this table, the HIRCS1 and HIRCS0 bits is recommended to be setup to select the same frequency to keep the HIRC frequency accuracy spedified in the A.C. characteristics. Application Circuit VDD VDD I/O Pins 0.1uF I�C Pins VSS KEY1 UART Pins SCO�&SSEG Pins KEY� XT1 XT� See Oscillator Section KEYn Rev. 1.40 OSC Circuit 149 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.40 150 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.40 151 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.40 152 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.40 153 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.40 154 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.40 155 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.40 156 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.40 157 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.40 158 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.40 159 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.40 160 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.40 161 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.40 162 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.40 163 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver 20-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.504 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.50 BSC — C 0.31 — 0.51 C’ — 12.8 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 164 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver 24-pin SOP(300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.606 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.5 BSC — C 0.31 — 0.51 C’ — 15.4 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 165 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SAW Type 24-pin (4mm×4mm) QFN Outline Dimensions Symbol Min. Nom. Max. A 0.028 0.030 0.031 A1 0.000 0.001 0.002 A3 — 0.008 BSC — b 0.007 0.010 0.012 D 0.156 0.157 0.159 E 0.156 0.157 0.159 e — 0.020 BSC — D2 0.102 0.106 0.110 E2 0.102 0.106 0.110 L 0.014 0.016 0.018 K 0.008 — — Symbol Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 — 0.200 BSC — b 0.180 0.250 0.300 D 3.950 4.000 4.050 E 3.950 4.000 4.050 e — 0.500 BSC — D2 2.600 2.700 2.800 E2 2.600 2.700 2.800 L 0.350 0.400 0.450 K 0.200 — — 166 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver 28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.705 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. — A — 10.30 BSC B — 7.5 BSC — C 0.31 — 0.51 C’ — 17.9 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 167 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.390 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. — A — 6.0 BSC B — 3.9 BSC — C 0.20 — 0.30 C’ — 9.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 168 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions Symbol Min. Nom. Max. A 0.028 0.030 0.031 A1 0.000 0.001 0.002 A3 — 0.008 BSC — b 0.007 0.010 0.012 D 0.193 0.197 0.201 E 0.193 0.197 0.201 e — 0.020 BSC — D2 0.122 0.126 0.130 E2 0.122 0.126 0.130 L 0.014 0.016 0.018 K 0.008 — — Symbol Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 — 0.203 BSC — b 0.180 0.250 0.300 D 4.900 5.000 5.100 E 4.900 5.000 5.100 e — 0.50 BSC — D2 3.10 3.20 3.30 E2 3.10 3.20 3.30 L 0.35 0.40 0.45 K 0.20 — — 169 May 05, 2016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch 8-Bit Flash MCU with LED/LCD Driver Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 170 May 05, 2016