Data Sheet

Document Number: MMA16xxKW
Rev. 5.1, 03/2013
Freescale Semiconductor
Data Sheet: Technical Data
Xtrinsic MMA16xxKW
DSI Inertial Sensor
MMA16xxKW
The MMA16xxKW family, a SafeAssure solution, includes the DSI2.5 compatible
overdamped Z-axis satellite accelerometers.
Features
Bottom View
•
•
•
•
•
•
•
•
16-PIN QFN
CASE 2086-01
±50g to ±312.5g Nominal Full-Scale Range
Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF
DSI2.5 Compatible with full support of Mandatory Commands
Internal High Side Bus Switch for DSI2.5 Daisy Chain Applications
16 μs internal sample rate, with interpolation to 1 ms
-40°C to 125°C Operating Temperature Range
Pb-Free 16-Pin QFN, 6 by 6 Package
Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
Typical Applications
Top View
TEST5
TEST6
TEST7
VSS
• Airbag Front and Side Crash Detection
16 15 14 13
TEST2 1
ORDERING INFORMATION
12 VSSA
17
Device
Axis
Range
Package
Shipping
TEST3 2
11 CREGA
MMA1605KW
Z
50g
2086-01
Tubes
TEST1 3
10 TEST4
BUSRTN 4
Tubes
MMA1612KW
Z
125g
2086-01
Tubes
MMA1618KW
Z
187g
2086-01
Tubes
MMA1631KW
Z
312g
2086-01
Tubes
MMA1605KWR2
Z
50g
2086-01
Tape & Reel
MMA1606KWR2
Z
62.5g
2086-01
Tape & Reel
MMA1612KWR2
Z
125g
2086-01
Tape & Reel
MMA1618KWR2
Z
187g
2086-01
Tape & Reel
MMA1631KWR2
Z
312g
2086-01
Tape & Reel
For user register array programming, please consult your Freescale representative.
© 2010-2013 Freescale Semiconductor, Inc. All rights reserved.
9 CREG
5
6
7
8
HCAP
2086-01
BUSIN
62.5g
BUSOUT
Z
PCM
MMA1606KW
PIN CONNECTIONS
Application Diagram
TEST2
BUSIN
BUSIN
VCC
TEST1
TEST3
TEST4
TEST5
MMA16xx
C1
BUSRTN
VSS
BUSRTN
TEST6
C2
TEST7
CREG
BUSOUT
BUSOUT
CREGA
HCAP
C4
C5
C3
VSSA
PCM
VSS
Figure 1. Application Diagram
Table 1. External Component Recommendations
Ref Des
Type
Description
Purpose
C1
Ceramic
100 pF ≤ C1 ≤ 1500 pF 10%, 50V, X7R BUSIN Power Supply Decoupling, ESD
C2
Ceramic
100 pF ≤ C2 ≤ 1500 pF, 10%, 50V, X7R BUSOUT Power Supply Decoupling, ESD
C3
Ceramic, Tantalum
1 μF ≤ C3 ≤ 100 μF, 10%, 50V, X7R
C4
Ceramic
1 μF, 10%, 10V, X7R
Voltage Regulator Output Capacitor (CREG)
C5
Ceramic
1 μF, 10%, 10V, X7R
Voltage Regulator Output Capacitor (CREGA)
Reservoir Capacitor for Keep Alive during Signaling
xxxxxxx
xxxxxxx
Z: 0 g
Z: 0 g
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
Device Orientation
Z: 0 g
xxxxxxx
xxxxxxx
Z: 0 g
Z: +1 g
Z: -1 g
EARTH GROUND
Figure 2. Device Orientation Diagram
MMA16xxKW
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Freescale Semiconductor, Inc.
Internal Block Diagram
HCAP
BUSIN
HCAP
VDSI_REF
ANALOG
VREGA
VOLTAGE
REGULATOR
CREGA
VREF
VSSA
LOW-VOLTAGE
RESET
BUSRTN
TEST3
CONTROL
LOGIC
SERIAL
ENCODER
VSS
CREG
REFERENCE
VOLTAGE
VDSI_REF
BUSOUT
DIGITAL
VREG
VOLTAGE
REGULATOR
TEST
OTP
FUSE
ARRAY
OSCILLATOR
TEST4
TEST5
TEST6
VREG
SELF-TEST
INTERFACE
g-CELL
VREGA
CONTROL
IN
VREG
DSP
SINC Filter
ΣΔ
CONVERTER
STATUS
OUT
3
1 – z –D
--------------------------------D × ( 1 – z–1 )
IIR
Low-Pass Filter Compensation
PCM Encoder
PCM
Figure 3. Block Diagram9
MMA16xxKW
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Freescale Semiconductor, Inc.
3
TEST5
TEST6
TEST7
Pin Connections
VSS
1
16 15 14 13
TEST2 1
12 VSSA
17
TEST3 2
11 CREGA
TEST1 3
10 TEST4
5
6
7
8
BUSIN
HCAP
9 CREG
BUSOUT
4
PCM
BUSRTN
Figure 4. Pinout
Table 2. Pin Description
Pin
Pin
Name
Formal Name
1
TEST2
Test Pin
This pin must be left unconnected in the application.
2
TEST3
Test Pin
This pin must be grounded in the application.
3
TEST1
Test Pin
This pin must be grounded in the application.
4
BUSRTN
Ground
This pin is the common return for power and signalling.
5
PCM
PCM
Output
This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled or
disabled via OTP. If unused, this pin must be left unconnected in the application. Reference Section 3.5.3.6.
6
BUSOUT
BUS output
This pin is internally connected to BUSIN through a switch. For daisy chain configurations, this pin is connected to the BUSIN
pin of the next slave on the DSI bus. The internal bus switch is open following reset, and is closed when an Initialization command is received.
7
BUSIN
Supply /
Comm
This pin is connected to the DSI positive bus node and provides the power supply and communication to the system master.
An external capacitor must be connected to between this pin and the BUSRTN pin. Reference Figure 1.
8
HCAP
Hold Capacitor
This pin rectifies the supply voltage on the BUSIN pin to create the supply voltage for the device. An external capacitor must
be connected between this pin and the BUSRTN pin to store energy for operation during master communication signalling.
Reference Figure 1.
9
CREG
Digital
Supply
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
this pin and VSS. Reference Figure 1.
10
TEST4
Test Pin
This pin must be grounded in the application.
11
CREGA
Analog
Supply
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between
this pin and VSSA. Reference Figure 1.
12
VSSA
Analog GND
13
TEST5
Test Pin
This pin enables test mode, and provides the SPI programming voltage in test mode. This pin is must be grounded in the
application.
14
TEST6
Test Pin
This pin must be grounded in the application.
15
TEST7
Test Pin
This pin must be grounded in the application.
16
VSS
Digital GND
PAD
Die Attach Pad
Corner
Pads
Corner Pads
17
Definition
This pin is the power supply return node for analog circuitry.
This pin is the power supply return node for the digital circuitry.
This pin is the die attach flag, and should be connected to VSS in the application. Reference Section 5.
The corner pads are internally connected to VSS.
MMA16xxKW
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2
Electrical Characteristics
2.1
Maximum Ratings
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. Do not apply
voltages higher than those shown in the table below.
#
Rating
Symbol
Value
Unit
1
2
Supply Voltage (continuous) (BUSIN,BUSOUT, HCAP)
Supply Voltage (pulsed < 400 ms, repetition rate 60s) (BUSIN,BUSOUT, HCAP)
VCC
VCC
-0.3 to +30.0
-0.3 to +34.0
V
V
(3)
(3)
3
CREG, CREGA, PCM, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
-0.3 to +3.0
V
(3)
4
5
BUSIN,BUSOUT, BUSRTN and HCAP Current
Maximum duration 1s
Continuous
IIN
IIN
400
75
mA
mA
(3)
(3)
6
Powered Shock (six sides, 0.5 ms duration)
gpms
±2000
g
(5)
7
Unpowered Shock (six sides, 0.5 ms duration)
gshock
±2000
g
(5)
8
Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation)
hDROP
1.2
m
(5)
9
10
11
Electrostatic Discharge (per AEC100)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0Ω)
MM (200 pF, 0Ω)
VESD
VESD
VESD
±2000
±500
±200
V
V
V
(5)
(5)
(5)
12
13
Temperature Range
Storage
Junction
Tstg
TJ
-40 to +125
-40 to +150
°C
°C
(3)
(3)
14
Thermal Resistance
θJC
2.5
°C/W
(11)
2.2
Operating Range
The operating ratings are the limits normally expected in the application.
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
VHCAP
VBUS
VL
6.3
-0.3
⎯
⎯
VH
30
30
V
V
(1,12)
(1,12)
15
16
Supply Voltage
VHCAP
BUSIN
17
Programming Voltage
Applied to BUSIN (DSI)
VPP
14.0
⎯
30.0
V
(3)
18
Programming Current
BUSIN
IPP
85
⎯
⎯
mA
(3)
TA
TA
TL
-40
-40
⎯
⎯
TH
+105
+125
°C
°C
(1)
(3)
Operating Temperature Range
19
20
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Freescale Semiconductor, Inc.
5
2.3
Electrical Characteristics - Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
21 Quiescent Supply Current
*
Symbol
Min
Typ
Max
Units
IDD
⎯
⎯
8.0
mA
(1)
22
Inrush Current (excluding HCAP Capacitor charge current)
Power On until VREG Stable
IINRUSH
⎯
⎯
20
mA
(3)
23
24
Internally Regulated Voltages
VREG
VREGA
VREG
VREGA
2.425
2.425
2.50
2.50
2.575
2.575
V
V
(1)
(1)
25
26
27
VHCAP Under-Voltage Detection (See Figure 5)
Under-Voltage Detection Threshold
VHCAP Recovery Threshold
Hysteresis (VPORHCAP_r - VPORHCAP_f)
VPORHCAP_f
VPORHCAP_r
VHYST_HCAP
5.8
⎯
70
6.0
⎯
100
6.2
6.3
140
V
V
mV
(3,6)
(3,6)
(3)
VPORVREG_f
VPORVREGA_f
2.15
2.15
2.25
2.25
2.40
2.40
V
V
(3.6)
(3.6)
VHYST_VREG
VHYST_VREGA
0.05
0.05
0.10
0.10
0.15
0.15
V
V
(3)
(3)
CREG, CREGA
RCREGESR,
RCREGAESR
500
⎯
1000
⎯
1500
200
nF
mΩ
(9)
(9)
Output High Voltage (PCM)
34 ILoad = 100 μA
VOH
VREG - 0.1
⎯
⎯
V
(9)
Output Low Voltage (PCM)
35 ILoad = 100 μA
VOL
⎯
⎯
0.1
V
(9)
Internal Regulator Low Voltage Detection Threshold
VREG Falling
VREGA Falling
Hysteresis
VREG
30
VREGA
31
28
29
32
33
2.4
External Capacitor (CREG, CREGA)
Capacitance
ESR (including interconnect resistance)
Electrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
36
BUSOUT Bus Switch Resistance
0V ≤ VBUSIN ≤ 30 V, ISW = 160 mA
*
RSW
⎯
4.0
8.0
Ω
(1)
37
HCAP Rectifier Leakage Current
VBUSIN = 0 V, VHCAP = 9.0V
*
IRLKG
⎯
⎯
100
μA
(1)
38
39
BUSIN to HCAP Rectifier Voltage Drop (VBUSIN = 7 V)
IHCAP = -15 mA
IHCAP = -100 mA
*
*
VRECT
VRECT
⎯
⎯
0.75
0.9
1.0
1.2
V
V
(1)
(1)
40
41
BUSIN Bias Current
VBUSIN = 8.0V, VHCAP = 9.0V
VBUSIN = 4.5V, VHCAP = 24V, No Response Current
*
IBUSIN_BIAS
IBUSIN_BIAS
0
0
⎯
⎯
100
100
μA
μA
(1)
(1)
42
43
BUSOUT Bias Current
VBUSOUT = 8.0V, VHCAP = 9.0V
VBUSOUT = 4.5V, VHCAP = 24 V, No Response Current
*
IBUSOUT_BIAS
IBUSOUT_BIAS
0
0
⎯
⎯
100
100
μA
μA
(1)
(1)
RBUSOUT_Discharge
3500
⎯
8000
Ω
(3)
IRESP
9.9
11
12.1
mA
(1)
*
ISW_Leak
IRSW_Leak
-20
-20
⎯
⎯
20
20
μA
μA
(1)
(1)
44 BUSOUT Discharge Resistance
45
BUSIN Response Current
VBUSIN = 4.0 V
BUSIN to BUSOUT Leakage Current (BUS SWITCH open)
46
VBUSIN = 24.0V, VBUSOUT = 0V
47
VBUSIN = 0V, VBUSOUT = 16V
*
48
49
BUSIN Logic Thresholds
Signal Threshold
Frame Threshold
*
*
VTHS
VTHF
2.8
5.5
3.0
6.0
3.2
6.5
V
V
(1)
(1)
50
51
BUSIN Logic Hysteresis
Signal
Frame
*
*
VHYSS
VHYSF
30
100
⎯
⎯
90
300
mV
mV
(3)
(3)
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Freescale Semiconductor, Inc.
2.5
Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Sensitivity (10-bit @ 100Hz referenced to 0 Hz)
50g Range
62.5g Range
125g Range
187g Range
312g Range
Total Sensitivity Error (including non-linearity)
57
TA = 25°C
58
TL ≤ T A ≤ TH
52
53
54
55
56
59
Digital Offset
10-bit output
60
61
Range of Output (10-Bit Mode)
Acceleration
Internal Error
62
63
Cross-Axis Sensitivity
X-axis to Z-axis
Y-axis to Z-axis
64 ADC Output Noise Peak (1 Hz - 1 kHz, 10-Bit)
65 System Output Noise (10-Bit, RMS, All Ranges)
66 Non-linearity (all ranges)
Symbol
Min
Typ
Max
Units
*
SENS
SENS
SENS
SENS
SENS
⎯
⎯
⎯
⎯
⎯
10.24
8.192
4.096
2.731
1.638
⎯
⎯
⎯
⎯
⎯
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
(1,14)
(1,14)
(1,14)
(1,14)
(1,14)
*
*
ΔSENS_25
ΔSENS
-5
-7
⎯
⎯
+5
+7
%
%
(1)
(1)
*
OFF10Bit
460
512
564
LSB
(1)
RANGEACC
RANGEERR
1
⎯
⎯
0
1023
⎯
LSB
LSB
(3)
(3)
VXZ
VYZ
-5
-5
—
—
+5
+5
%
%
(3)
(3)
*
*
*
*
nSD
-4
—
+4
LSB
(3)
nRMS
⎯
⎯
+1.2
LSB
(3)
NLOUT
-2
⎯
+2
%
(3)
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2.6
Electrical Characteristics - Self-Test and Overload
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Symbol
Min
Typ
Max
Units
Acceleration (without hitting internal g-cell stops)
67
±50g, ±62.5g, ±125g Positive
68
±50g, ±62.5g, ±125g Negative
Characteristic
gg-cell_Clip60ZP
gg-cell_Clip60ZN
425
-1205
642
-720
980
-512
g
g
(9)
(9)
69
70
Acceleration (without hitting internal g-cell stops)
±187g, ±312g Positive
±187g, ±312g Negative
gg-cell_Clip240ZP
gg-cell_Clip240ZN
1450
-3100
2180
-2210
2800
-1800
g
g
(9)
(9)
71
72
ΣΔ and Sinc Filter Clipping Limit
±50g Range Positive
±50g Range Negative
gADC_Clip60ZP
gADC_Clip60ZN
160
-333
238
-274
335
-216
g
g
(9)
(9)
73
74
ΣΔ and Sinc Filter Clipping Limit
±62.5g Range Positive
±62.5g Range Negative
gADC_Clip60ZP
gADC_Clip60ZN
160
-333
238
-274
335
-216
g
g
(9)
(9)
75
76
ΣΔ and Sinc Filter Clipping Limit
±125g Range Positive
±125g Range Negative
gADC_Clip120ZP
gADC_Clip120ZN
306
-693
433
-544
577
-415
g
g
(9)
(9)
77
78
ΣΔ and Sinc Filter Clipping Limit
±187g Range Positive
±187g Range Negative
gADC_Clip240ZP
gADC_Clip240ZN
836
-1909
1178
-1566
1599
-1245
g
g
(9)
(9)
79
80
ΣΔ and Sinc Filter Clipping Limit
±312g Range Positive
±312g Range Negative
gADC_Clip480ZP
gADC_Clip480ZN
836
-1909
1178
-1566
1599
-1245
g
g
(9)
(9)
81
82
83
84
85
Deflection, 10-Bit, Self-Test - Offset, 30 sample ave, TA = 25°C)
±50g Range
±62.5g Range
±125g Range
±187g Range
±312g Range
ΔDFLCT_Z50
ΔDFLCT_Z62
ΔDFLCT_Z125
ΔDFLCT_Z187
ΔDFLCT_Z312
⎯
⎯
⎯
⎯
⎯
307
245
299
205
123
⎯
⎯
⎯
⎯
⎯
LSB
LSB
LSB
LSB
LSB
(1)
(1)
(1)
(1)
(1)
86 Self-Test deflection range, TA = 25 °C
ΔDFLCT
-10
⎯
+10
%
(1)
87 Self-Test deflection range, TL ≤ TA ≤ TH
ΔDFLCT
-20
⎯
+20
%
(1)
*
*
*
*
*
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2.7
Dynamic Electrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
#
Symbol
Min
Typ
Max
Units
tDSI_INIT
tDSP_INIT
tDSI_INIT
tDSP_INIT
⎯
⎯
⎯
⎯
400 / fOSC
⎯
400 / fOSC
⎯
⎯
10000 /
fOSC
⎯
10000 /
fOSC
s
s
s
s
(7)
(7)
(7)
(7)
HCAP Under-Voltage Reset Delay (See Figure 5)
92 VHCAP < VPORHCAP_f to POR assertion
tHCAP_POR
⎯
880 / fOSC
⎯
s
(7)
VREG Under-Voltage Reset Delay (See Figure 6)
93 VREG < VPORVREG_f to POR assertion
tVREG_POR
⎯
⎯
5
μs
(3)
VREGA Under-Voltage Reset Delay (See Figure 7)
94 VREGA < VPORVREGA_f to POR assertion
tVREGA_POR
⎯
⎯
5
μs
(3)
tPOR_CAPTEST
tCAPTEST_TIME
tCAPTEST_RATE
⎯
⎯
⎯
12000 /
fOSC
6 / fOSC
256 / fOSC
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
tBS
89
⎯
138
μs
(7)
tBUSOUT_Discharge
9.5
10
10.5
μs
(3)
88
89
90
91
95
96
97
Characteristic
Reset Recovery (See Figure 20)
POR negated to 1st DSI Command (Initialization Command)
POR negated to Acceleration Data Valid (Including LPF Init)
DSI Clear Command to 1st DSI Command (Initialization Command)
DSI Clear Command to Acceleration Data Valid (Including LPF Init)
VREG, VREGA Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Time ()
Disconnect Rate ()
98 Initialization to Bus Switch Closing
99
BUSOUT Discharge Resistance
Activation Time
DRATE
100
⎯
200
kbps
(7)
Loss of Signal Reset Time
101
Maximum time below frame threshold
tTO
2.00
⎯
4.00
ms
(7)
102
BUSIN Response Current Slew Rate
1.0 mA to 9.0 mA, 9.0 to 1.0 mA
tITR
0.33
⎯
10.0
mA/μs
(3)
103
104
BUSIN Timing to Response Current
BUSIN Negative Voltage Transition = 3.0V to IRSP = 7.0 mA rise
BUSIN Negative Voltage Transition = 3.0V to IRSP = 5.0 mA fall
tRSP_R
tRSP_F
⎯
⎯
⎯
⎯
2.50
2.50
μs
μs
(7)
(7)
105
106
DSI BUSIN Signal Duty Cycle
Logic ‘0’
Logic ‘1’
DCL
DCH
10
60
33
67
40
90
%
%
(7)
(7)
107
108
109
110
Inter-frame Separation Time (See Figure 8)
Following Read Write NVM Command
Following Initialization, BS = 1
Following Initialization, BS = 0
Following other DSI bus commands
tIFS
tIFS
tIFS
tIFS
12
200
20
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ms
μs
μs
μs
(7)
(7)
(7)
(7)
tLAT_DSI
4 / fOSC
⎯
5 / fOSC
s
(7)
tBSOPEN
⎯
⎯
500
μs
(3)
tST_ACT_180
tST_DEACT_180
tST_ACT_400
tST_DEACT_400
tST_ACT_800
tST_DEACT_800
2.00
2.00
1.00
1.00
0.50
0.50
⎯
⎯
⎯
⎯
⎯
⎯
5.00
5.00
2.50
2.50
1.75
1.75
ms
ms
ms
ms
ms
ms
(7)
(7)
(7)
(7)
(7)
(7)
tCRC_Err
⎯
75 / fOSC
⎯
s
(7)
100 Communication Data Rate
111 DSI Data Latency
112
Bus Switch Open Time
Reset Asserted to ISW_LEAK ≤ 20 μA
113
114
115
116
117
118
Self-Test Response Time
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 800 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 800 Hz LPF)
119
Error Detection Response Time
Mirror Register CRC Error to Status Flag (S) set (Factory or User Array)
*
*
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2.8
Dynamic Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
fOSC
3.80
4
4.20
MHz
(1)
tLAT_INTERP
64 / fOSC
⎯
65 / fOSC
s
(7)
fC_LPF0
OLPF0
fC_LPF1
OLPF1
fC_LPF2
OLPF2
171
⎯
380
⎯
760
⎯
180
2
400
4
800
4
189
⎯
420
⎯
840
⎯
Hz
1
Hz
1
Hz
1
(7)
(7)
(7)
(7)
(7)
(7)
fgcell_3dB_zlo
fgcell_3dB_zhi
798
1437
⎯
⎯
2211
2425
Hz
Hz
(9)
(9)
Sensing Element Natural Frequency
±50g, ±62.5g, ±125g
±187g, ±312g
fgcell_zlo
fgcell_zhi
7000
13600
⎯
⎯
8000
15100
Hz
Hz
(9)
(9)
132
133
Sensing Element Damping Ratio
±50g, ±62.5g, ±125g
±187g, ±312g
ζgcell_zlo
ζgcell_zhi
1.870
2.040
⎯
⎯
4.610
7.580
⎯
⎯
(9)
(9)
134
135
Sensing Element Delay (@100 Hz)
±50g, ±62.5g, ±125g
±187g, ±312g
fgcell_delay100_zlo
fgcell_delay100_zhi
77
47
⎯
⎯
200
160
μs
μs
(9)
(9)
136
Package Resonance Frequency
fPackage
100
⎯
⎯
kHz
(9)
120
Internal Oscillator Frequency
121
Data Interpolation Latency
122
123
124
125
126
127
DSP Low-Pass Filter
Cutoff frequency LPF0 (referenced to 0 Hz)
Filter Order LPF0
Cutoff frequency LPF1 (referenced to 0 Hz)
Filter Order LPF1
Cutoff frequency LPF2 (referenced to 0 Hz)
Filter Order LPF2
128
129
Sensing Element Rolloff Frequency (-3 db)
±50g, ±62.5g, ±125g
±187g, ±312g
130
131
*
Notes:
1. Parameters tested 100% at final test at -40°C, 25°C, and 105°C.
2. Parameters tested 100% at probe.
3. Verified by characterization.
4. * Indicates critical characteristic.
5. Verified by qualification testing, not tested in production.
6. Parameters verified by pass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8. Verified by user system level characterization, not tested in production, or at component level.
9. Verified by Simulation.
10.Measured at final test. Self-Test activation occurs under control of the test program.
11.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
12.Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24V at final test.
13.N/A.
14.Sensitivity, and overload capability specifications will be reduced when 800 Hz filter is selected.
15.Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
16.Target values. Actual values to be determined during device characterization.
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UV: UNDER-VOLTAGE CONDITION
EXISTS
VPORHCAP_r
VPORHCAP_f
VHCAP
VHYST_HCAP
UV
UV
tHCAP_POR
POR
Figure 5. VHCAP Under-Voltage Detection
VREG
VPORVREG_r
VPORVREG_f
VHYST_VREG
tVREG_POR
POR
Figure 6. VREG Under-Voltage Detection
VREGA
VPORVREGA_r
VPORVREGA_f
VHYST_VREGA
tVREGA_POR
POR
Figure 7. VREGA Under-Voltage Detection
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tSTART_master
VTHF
VTHS
BUSIN’
tIFS_master
tIFS_slave
LOGIC ‘1’
LOGIC ‘0’
tSTART_slave
9mA
EOFslave
1mA
IRESPONSE
tITR
tRSP_F
tITR
tRSP_R
tLAT_DSI
tLAT_INTERP
DSP_OUT
Figure 8. DSI Bus Inter-frame Timing
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3
Functional Description
3.1
User Accessible Data Array
A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable
array, an OTP user programmable array, and read-only registers for device status. The OTP arrays incorporate independent error
detection for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-programmed trim values. The user accessible data is shown in the table below.
Table 3. User Accessible Data
Byte
Addr
RA[3:0]
Register
$00
SN0
SN[7]
SN[6]
SN[5]
SN[4]
SN[3]
SN[2]
SN[1]
SN[0]
$01
SN1
SN[15]
SN[14]
SN[13]
SN[12]
SN[11]
SN[10]
SN[9]
SN[8]
$02
SN2
SN[23]
SN[22]
SN[21]
SN[20]
SN[19]
SN[18]
SN[17]
SN[16]
$03
SN3
SN[31]
SN[30]
SN[29]
SN[28]
SN[27]
SN[26]
SN[25]
SN[24]
$04
TYPE
LPF[1]
LPF[0]
0
0
RNG[3]
RNG[2]
RNG[1]
RNG[0]
$05
DEVCFG
DEVID
0
0
0
0
0
0
0
$06
DEVCFG1
0
0
0
0
0
0
$07
DEVCFG2
LOCK_U
0
PCM
0
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
$08
UD01
UD01[7]
UD01[6]
UD01[5]
UD01[4]
UD01[3]
UD01[2]
UD01[1]
UD01[0]
$09
UD02
UD02[7]
UD02[6]
UD02[5]
UD02[4]
UD02[3]
UD02[2]
UD02[1]
UD02[0]
$0A
UD03
UD03[7]
UD03[6]
UD03[5]
UD03[4]
UD03[3]
UD03[2]
UD03[1]
UD03[0]
Nibble Addr
WA[3:0]
Reference
Table 40
Bit Function
7
6
5
Nibble Addr
(WA[3:0])
4
Reference
Table 40
Bit Function
3
2
1
0
Type
F
AT_OTP[1] AT_OTP[0]
$0B
UD04
UD04[7]
UD04[6]
UD04[5]
UD04[4]
UD04[3]
UD04[2]
UD04[1]
UD04[0]
$0C
UD05
UD05[7]
UD05[6]
UD05[5]
UD05[4]
UD05[3]
UD05[2]
UD05[1]
UD05[0]
$0D
UD06
UD06[7]
UD06[6]
UD06[5]
UD06[4]
UD06[3]
UD06[2]
UD06[1]
UD06[0]
$0E
UD07
UD07[7]
UD07[6]
UD07[5]
UD07[4]
UD07[3]
UD07[2]
UD07[1]
UD07[0]
$0F
UD08
UD08[7]
UD08[6]
UD08[5]
UD08[4]
0
0
0
0
U/F
Type codes
F:
Freescale programmed OTP location
U/F:
User and/or Freescale programmed OTP location.
Note: Unused and Unprogrammed Spare bits always read ‘0’.
3.1.1
Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial number is composed of the following information:
Bit Range
Content
SN[12:0]
SN[31:13]
Serial Number
Lot Number
Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on
lot size and quantities, all possible lot numbers and serial numbers may not be assigned.
The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details
regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or
performance, and are only used for traceability purposes.
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3.1.2
Device Type Register (TYPE)
The Device Type Register is an OTP configuration register which contains device configuration information. Bit 5 - Bit 0 are
factory programmed and are included in the factory programmed OTP CRC verification. These bits are read only to the user.
Bit 7 - Bit 6 are user programmable OTP bits and are included in the user programmable OTP error detection.
Table 4. Factory Configuration Register
Location
RA[3:0]
Register
$04
TYPE
7
6
5
4
3
2
1
0
Bnk0 $08
LPF[1]
LPF[0]
0
0
RNG[3]
RNG[2]
RNG[1]
RNG[0]
0
0
0
0
0
0
0
0
Factory Default
3.1.2.1
Bit
WA[3:0]
WA[3:0]
Low-Pass Filter Selection Bits (LPF[1:0]) (TYPE[7:6])
The Low-Pass Filter selection bit selects between one of three low-pass filter options. These bits can be factory or user programmed.
LPF[1]
LPF[0]
Low-Pass Filter Selected
0
0
400 Hz, 4-Pole
0
1
Not Enabled1
1
0
180 Hz, 2-Pole
1
1
800 Hz, 4-Pole
This filter option is not implemented. LPF[1:0] must not be set to this value to guarantee proper operation and performance.
3.1.2.2
Range Selection Bits (RNG[3:0]) (TYPE[3:0])
The Range Selection Bits indicate the full-scale range of the device, as shown below. These bits are factory programmed.
RNG[3]
RNG[2]
RNG[1]
RNG[0]
Full-Scale Range
g-Cell Design
0
0
0
0
N/A
N/A
0
0
0
1
N/A
N/A
0
0
1
0
50g
Medium-g
0
0
1
1
62g
Medium-g
0
1
0
0
125g
Medium-g
0
1
0
1
187g
High-g
0
1
1
0
312g
High-g
0
1
1
1
N/A
N/A
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Reserved
N/A
1
1
0
1
1
1
1
0
1
1
1
1
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3.1.3
Device Configuration Register (DEVCFG)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register error detection. Refer to Section 3.2.2 for details regarding user programmable OTP array
error detection.
Table 5. Device Configuration Register
Location
RA[3:0]
Register
$05
DEVCFG
WA[3:0]
7
6
5
4
Bnk0 $0A
DEVID
0
0
0
1
0
0
0
Factory Default
3.1.3.1
Bit
WA[3:0]
3
2
1
0
0
0
0
0
0
0
0
0
Bnk0 $09
Device ID Bit (DEVCFG[7])
The Device ID Bit is a user programmable bit which allows the user to select between 2 device IDs. The Device ID is transmitted in response to the Request ID DSI command. Reference Section 4.2.1.5 for more information regarding the Request ID
DSI command. This bit can be factory or user programmed.
3.1.4
DEVID
Device ID
0
‘00110’
1
‘00100’
Device Configuration Register 1 (DEVCFG1)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register error detection. Refer to Section 3.2.2 for details regarding the user programmable OTP
array error detection.
Table 6. Device Configuration Register 1
Location
RA[3:0]
Register
$06
DEVCFG1
WA[3:0]
7
6
5
4
Bnk2 $06
0
0
0
0
0
0
0
0
Factory Default
3.1.4.1
Bit
WA[3:0]
Bnk1 $06
3
2
0
0
0
0
1
0
AT_OTP[1] AT_OTP[0]
0
0
Attribute Bits (AT_OTP[1:0], DEVCFG1[1:0])
The Attribute Bits are user defined bits which are transmitted in response to the Request Status, Disable Self-Test Stimulus or
Enable Self-Test Stimulus DSI commands. The transmitted values are qualified by the LOCK_U bit as shown in the table below.
These bits can be factory or user programmed.
LOCK_U
0
1
DEVCFG1 Values
AT_OTP[1]
AT_OTP[0]
DSI Transmitted Values
AT[1]
AT[0]
X
X
1
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
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3.1.5
Device Configuration Register 2 (DEVCFG2)
Device configuration register 2 is a user programmable OTP register which contains device configuration information. This
register is included in the user register error detection. Refer to Section 3.2.2 for details regarding the user programmable OTP
array error detection.
Table 7. Device Configuration Register 2
Location
RA[3:0]
Register
$07
DEVCFG2
WA[3:0]
7
6
5
4
Bnk0 $07
Bnk2 $07
Bnk3 $07
Bnk3 $0F
LOCK_U
0
PCM
0
0
0
0
0
Factory Default
3.1.5.1
Bit
WA[3:0]
Bnk1 $07
3
2
1
0
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
0
0
0
0
User Configuration Lock Bit (LOCK_U, DEVCFG2[7])
The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active.
Reference Section 3.2.2 for details regarding the LOCK_U bit and error detection.
3.1.5.2
PCM Bit (DEVCFG2[5])
The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.6 for more information regarding the PCM
output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.
3.1.5.3
Device Address (ADDR[3:0], DEVCFG2[3:0])
The Device Address bits define the preprogrammed DSI Bus device address. If the Device Address bits are programmed to
‘0000’, there is not preprogrammed address, and the address must be assigned via the Initialization DSI command. Reference
Section 4.2.1.1 for more details regarding the Initialization DSI command. These bits can be factory or user programmed.
3.1.6
User Data Registers (UDx)
The User Data Registers are user programmable OTP register which can be programmed with user or assembly specific information. These registers have no impact on the device performance, but are included in the user register error detection. Refer
to Section 3.2.2 for details regarding the user register error detection.
Location
RA[3:0]
Register
$08
UD01
WA[3:0]
7
6
5
4
Bnk2 $08
UD01[7]
UD01[6]
UD01[5]
UD01[4]
Bit
WA[3:0]
3
2
1
0
Bnk1 $08
UD01[3]
UD01[2]
UD01[1]
UD01[0]
$09
UD02
Bnk2 $09
UD02[7]
UD02[6]
UD02[5]
UD02[4]
Bnk1 $09
UD02[3]
UD02[2]
UD02[1]
UD02[0]
$0A
UD03
Bnk2 $0A
UD03[7]
UD03[6]
UD03[5]
UD03[4]
Bnk1 $0A
UD03[3]
UD03[2]
UD03[1]
UD03[0]
$0B
UD04
Bnk2 $0B
UD04[7]
UD04[6]
UD04[5]
UD04[4]
Bnk1 $0B
UD04[3]
UD04[2]
UD04[1]
UD04[0]
$0C
UD05
Bnk2 $0C
UD05[7]
UD05[6]
UD05[5]
UD05[4]
Bnk1 $0C
UD05[3]
UD05[2]
UD05[1]
UD05[0]
$0D
UD06
Bnk2 $0D
UD06[7]
UD06[6]
UD06[5]
UD06[4]
Bnk1 $0D
UD06[3]
UD06[2]
UD06[1]
UD06[0]
$0E
UD07
Bnk2 $0E
UD07[7]
UD07[6]
UD07[5]
UD07[4]
Bnk1 $0E
UD07[3]
UD07[2]
UD07[1]
UD07[0]
$0F
UD08
Bnk2 $0F
UD08[7]
UD08[6]
UD08[5]
UD08[4]
0
0
0
0
0
0
0
0
0
0
0
0
Factory Default
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3.2
OTP Array Lock and Error Detection
3.2.1
Factory Programmed OTP Array Lock and Error Detection
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the
Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which
the internal lock bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.
Factory Lock Bit Value in Fuse Array
Lock Bit Value in Mirror Register After
Automatic Readout
0
N/A
NO
NO
1
0
NO
NO
1
1
YES
YES
Lock Bit Active?
CRC Verification
Enabled?
The Factory programmed OTP array is locked by Freescale and will always be active after POR. The CRC is continuously
calculated on the factory programmed OTP array, which includes the registers listed below:
Register Name
Register Addresses
Included in Factory CRC?
Serial Number Registers
SN0, SN1, SN2, SN3
Yes
Type Register
TYPE[5:0]
Yes
Factory Programmable Device Configuration Bits
Internal Register Map
Yes
Factory OTP Array CRC
CRC_F[2:0]
No
Factory OTP Array Lock Bit
LOCK_F
No
Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification
uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. The calculated CRC is compared against the
CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not
the fuse array values.
3.2.2
User Programmable OTP Array Lock and Error Detection
The user programmable OTP array is independently verified for errors. The error detection is enabled only when the user programmable OTP array is locked as shown below.
Factory Lock Bit Value in Fuse Array
Lock Bit Value in Mirror Register After
Automatic Readout
0
N/A
NO
NO
1
0
NO
NO
1
1
YES
YES
Lock Bit Active?
CRC Verification
Enabled?
When the LOCK_U bit is set, the error detection code is calculated on the user programmable OTP Array registers listed below
and stored to NVM.
Register Name
Register Addresses
Type Register
TYPE[7:6]
Device ID Bit
DEVCFG[7]: DEVID
Attribute Bits
DEVCFG1[1:0]: AT_OTP[1:0]
PCM Bit
DEVCFG2[5]: PCM
Device Address
DEVCFG2[3:0]: ADDR[3:0]
User Data Registers 1 - 8
UD01 - UD08
During normal operation, the error detection code is continuously compared against the stored error detection code. If a mismatch is detected, an internal data error is set, and the device responds to DSI messages as specified in Section 4.3. The error
detection code is calculated on the memory registers which hold a copy of the fuse array values, not the fuse array values.
Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a
change to the error detection code regardless of the state of the LOCK_U bit. An error detection mismatch will only be detected
if the LOCK_U bit is active.
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3.3
Voltage Regulators
The device derives its internal supply voltage from the HCAP supply voltage. The device includes separate internal voltage
regulators for the analog (VREGA) and digital circuitry (VREG). External filter capacitors are required, as shown in Figure 1.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
HCAP and internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the
HCAP supply or internally regulated voltages fall below predetermined levels. A reference generator provides a stable voltage
which is used by the ΣΔ converter.
VOLTAGE VBUF
REGULATOR
HCAP
VREGA = 2.50 V
VOLTAGE
REGULATOR
BIAS
GENERATOR
BANDGAP
REFERENCE
VREF
TRIM
REFERENCE VREF_MOD = 1.250 V
GENERATOR
VBUF
VREGA
VOLTAGE
REGULATOR
CREGA
OSCILLATOR
TRIM
ΣΔ
CONVERTER
OTP
ARRAY
VREG = 2.50 V
CREG
DIGITAL
LOGIC
DSP
HCAP
VREG
VREGA
VREF
COMPARATOR
Digital Delay
tHCAP_POR
COMPARATOR
Analog Filter Delay
tVREG_POR
COMPARATOR
Analog Filter Delay
tVREG_POR
POR
Figure 9. Voltage Regulation and Monitoring
3.3.1
CREG and CREGA Regulator Capacitor
The internal regulator requires an external capacitor between the CREG pin and VSS pin, and the CREGA pin and VSSA pin for
stability. Figure 1 shows the recommended types and values for each of these capacitors.
3.3.2
VHCAP Voltage Monitor
The device includes a circuit to monitor the voltage on the HCAP pin. If the voltage falls below the specified threshold in
Section 2, the device will be reset within the reset delay time (tHCAP_POR) specified in Section 2.7.
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3.3.3
VREG, and VREGA Under-Voltage Monitor
The device includes a circuit to monitor the internally regulated voltages (VREG and VREGA). If either of the internal regulator
voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (tVREG_POR,
tVREGA_POR) specified in Section 2.7.
3.3.4
VREG and VREGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external CREG or CREGA capacitor
becomes open. At a continuous rate specified in Section 2.7 (tCAPTEST_RATE), both regulators are simultaneously disabled for a
short duration (tCAPTEST_TIME). If either of the external capacitors are not present, the associated regulator voltage will fall below
the internal reset threshold, forcing a device reset.
tCAPTEST_RATE
tCAPTEST_TIME
CAP_Test
VREG
Capacitor Present
Capacitor Open
VPORVREG_f
POR
Time
Figure 10. VREG Capacitor Monitor
tCAPTEST_RATE
tCAPTEST_TIME
CAP_Test
VREGA
Capacitor Present
Capacitor Open
VPORREGA_f
POR
Time
Figure 11. VREGA Capacitor Monitor
3.4
Internal Oscillator
The device includes a factory trimmed oscillator as specified in Section 2.8.
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3.5
Acceleration Signal Path
3.5.1
Transducer
The device transducer is an overdamped mass-spring-damper system described by the following transfer function:
2
ωn
H ( s ) = -----------------------------------------------------2
2
s + 2 ⋅ ξ ⋅ ωn ⋅ s + ωn
where:
ζ = Damping Ratio
ωn = Natural Frequency = 2∗Π∗fn
Reference Section 2.8 for transducer parameters.
3.5.2
ΣΔ Converter
The sigma delta converter provides the interface between the g-cell and the DSP block. The output of the ΣΔ converter is a
data stream at a nominal frequency of 1 MHz.
g-cell
α1=
CTOP
VX
FIRST
INTEGRATOR
CINT1
z-1
α2
z-1
1 - z-1
CBOT
1-BIT
QUANTIZER
SECOND
INTEGRATOR
ΣΔ_OUT
1 - z-1
V = ΔC x VX / CINT1
ΔC = CTOP - CBOT
ADC
β1
β2
DAC
V = ±2 × VREF
Figure 12. ΣΔ Converter Block Diagram
3.5.3
Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating
the signal processing flow within the DSP block is shown in Figure 13.
ΣΔ_OUT
A
Sinc Filter
1 – z –D
--------------------------------D × ( 1 – z –1 )
3
B
Low-Pass Filter
n + ( n ⋅ z –1 ) + ( n ⋅ z –2 ) n + ( n ⋅ z –1 ) + ( n ⋅ z –2 )
11
12
13
21
22
23
a ⋅ ----------------------------------------------------------------------------- ⋅ ----------------------------------------------------------------------------0
d + ( d ⋅ z –1 ) + ( d ⋅ z –2 ) d + ( d ⋅ z –1 ) + ( d ⋅ z –2 )
11
12
13
21
22
23
D
C
Compensation
Output
Scaling
E
F
Interpolation OUTPUT
Figure 13. Signal Chain Diagram
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Table 8. Signal Chain Characteristics
Description
Sample Time
(μs)
Data Width
(Bits)
Over Range
(Bits)
Signal Width
(Bits)
Signal Noise Signal Margin
(Bits)
(Bits)
Typical Block
Latency
Reference
A
ΣΔ
1
1
1
B
SINC Filter
16
20
12
4
C
Low-Pass Filter
16
26
1
12
4
9
Reference
Section 3.5.3.2
Section 3.5.3.2
D
Compensation
16
26
4
10
3
9
24/fosc
Section 3.5.3.3
E
F
DSP Sampling
10-Bit Output Scaling
Interpolation
3.5.3.1
112/fosc
Section 3.5.2
Section 3.5.3.1
16
10
4/fosc
Section 3.5.3.5
1
10
64/fosc
Section 3.5.3.5
Decimation Sinc Filter
The serial data stream produced by the ΣΔ converters is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 16.
3
1 – z – 16 ---------------------------------H(z) =
16 × ( 1 – z – 1 )
Figure 14. Sinc Filter Response, tS = 16 μs
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3.5.3.2
Low-Pass Filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
( n 11 ⋅ z 0 ) + ( n 12 ⋅ z – 1 ) + ( n 13 ⋅ z – 2 ) ( n 21 ⋅ z 0 ) + ( n 22 ⋅ z – 1 ) + ( n 23 ⋅ z – 2 )
H ( z ) = a 0 ⋅ -------------------------------------------------------------------------------------------- ⋅ -------------------------------------------------------------------------------------------( d 11 ⋅ z 0 ) + ( d 12 ⋅ z – 1 ) + ( d 13 ⋅ z – 2 ) ( d 11 ⋅ z 0 ) + ( d 22 ⋅ z – 1 ) + ( d 23 ⋅ z – 2 )
The device provides the option for one of three low-pass filters. The filter is selected with the LPF[1:0] bits in the TYPE register.
The filter selection options are listed in Section 3.1.2.1, Table 9. Response parameters for the low-pass filter are specified in
Section 2.8. Filter characteristics are illustrated in the figures below.
Table 9. Low-Pass Filter Coefficients
Description
180 Hz LPF
400 Hz LPF
800 Hz LPF
Filter Coefficients
a0
n11
n12
n13
n21
n22
n23
a0
n11
n12
n13
n21
n22
n23
a0
n11
n12
n13
n21
n22
n23
0.000534069200512
0.25
0.499999985098839
0.25
1
0
0
0.003135988372378
0.000999420881271
0.001998946070671
0.000999405980110
0.250004753470421
0.499986037611961
0.250009194016457
0.011904109735042
0.003841564059258
0.007683292031288
0.003841534256935
0.250001862645149
0.499994158744812
0.250003993511200
Group Delay
d11
d12
d13
d21
d22
d23
1
-1.959839582443237
0.960373640060425
1
0
0
d11
d12
d13
d21
d22
d23
1.0
-1.892452478408814
0.89558845758438
1.0
-1.919075012207031
0.923072755336761
d11
d12
d13
d21
d22
1.0
-1.790004611015320
0.801908731460571
1.0
-1.836849451065064
d23
0.852215826511383
4608/fosc
3392/fosc
1728/fosc
Note: Low-Pass Filter Figures do not include g-cell frequency response.
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Figure 15. Low-Pass Filter Characteristics: fC = 180 Hz, 2-Pole, tS = 16 μs
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Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 μs
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Figure 17. Low-Pass Filter Characteristics: fC = 800 Hz, 4-Pole, tS = 16 μs
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3.5.3.3
Compensation
The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.
3.5.3.4
Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is delayed one sample time. On reception of an acceleration data request, the transmitted data is interpolated from the two previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample
time. Reference Figure 8 for more information regarding interpolation and data latency.
3.5.3.5
Output Scaling
The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-Bit word which covers the acceleration range of
the device. Figure 18 shows the method used to establish the acceleration data word from the 26-bit DSP output.
Over Range
D25
D24
D23
Signal
D22
Noise
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
10-Bit Data Word
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
9-Bit Data Word
D21
D20
D19
D18
D17
D16
D15
D14
D13
8-Bit Data Word
D21
D20
D19
D18
D17
D16
D15
D14
D11
D10
Margin
D9
D8
...
D2
D1
D0
Using Truncation
Using Truncation
Using Truncation
Figure 18. Output Scaling Diagram
3.5.3.6
PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2
register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the acceleration response is output onto the PCM pin. The PCM output is intended for test use only. A block diagram of the PCM output
is shown in Figure 19.
Output Scaling
D_x[9:1]
A
CARRY
PCM
9
9 Bit ADDER
9
Sample updated every 16μS
B
SUM
fCLK = 4 MHz
9
DD
QQ
DD
QQ
DD
QQ
DDFF
QQ
DFF
Q
FF
FF
FF
FF
FF
FF
FF
CLK
QQ
CLK
CLK
QQ
CLK
CLK
QQ
CLK
CLK
QQ
CLK
CLK
Q
Figure 19. PCM Output Function Block Diagram
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3.6
Device Initialization
Following powerup, under-voltage reset or reception of a DSI Clear Command, the device proceeds through an initialization
process as described in the following tables:
Table 10. Power-up or Under-Voltage Reset Initialization Process
#
Description
Time
1 Power up to a Known State
0
3 Read Fuse Array and Copy to Memory Array (Mirror Registers)
S Flag ST Flag
DSI Response
N/A
N/A
1
0
No Response
No Response
4 Initialize DSI State Machine (the device is ready for DSI Messages)
tDSI_INIT
1
0
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
5 Initialize the DSP (Acceleration Data is Valid)
tDSP_INIT
0
0
Normal
Table 11. DSI Clear Command Initialization Process
#
Description
Time
1 the device logic comes out of reset
0
3 Read Fuse Array and Copy to Memory Array (Mirror Registers)
S Flag ST Flag
DSI Response
1
0
No Response
1
0
No Response
4 Initialize DSI State Machine (the device is ready for DSI Messages)
tDSI_INIT
1
0
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
5 Initialize the DSP (Acceleration Data is Valid)
tDSP_INIT
0
0
Normal
BUSIN’
VPORHCAP_r
VHCAP
VPORVREG_r
VREG
VPORVREGA_r
VREGA
POR
Internal Delay
tINT_INIT
DSI Ready
DSP_OUT
tDSI_INIT
tDSP_INIT
Figure 20. Initialization Timing
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3.7
Overload Response
3.7.1
Overload Performance
The device is designed to operate within a specified range. However, acceleration beyond that range (overload) impacts the
operating range output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the
device that is dependent upon the overload frequency and amplitude. The device g-cell is overdamped, providing the optimal
design for overload performance. However, the performance of the device during an overload condition is affected by many other
parameters, including:
• g-cell damping
• Non-linearity
• Clipping limits
• Symmetry
Figure 21 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are specified in Section 2.
Acceleration (g)
g-cellRolloff
Region Clipped
by Output
LPFRolloff
io
Reg
nC
ed b
lipp
y g-
cell
Determined by g-cell
roll-off and ADC clipping
to
due
ADC
tion inearity
y
r
b
o
t
is
L
ped
al D NonClip
Sign y and
io n
f
g
o
e
R
etr
io n
Reg Asymm
gg-cell_Clip
gADC_Clip
Determined by g-cell
roll-off and full-scale range
gRange_Norm
Region of Interest
fLPF
Region of No Signal Distortion Beyond
Specification
fg-Cell
5kHz
10kHz
Frequency (kHz)
Figure 21. Output Clipping Vs. Frequency
3.7.2
Sigma Delta Overrange Response
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predictably under all cases of overrange, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor.
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4
DSI Protocol Layer
4.1
Communication Interface Overview
The device is compatible with the DSI Bus Standard V2.5.
4.1.1
DSI Physical Layer
Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer.
4.1.2
DSI Data Link Layer
Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe
the DSI data link layer features supported.
4.2
DSI Protocol
4.2.1
DSI Bus Commands
DSI Bus Commands are summarized in Table 12. The device supports only the command formats specified in Section 4.2.1.
The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is
received, the device will not respond.
Following all messages, the device requires a minimum inter-frame separation (tIFS). As long as the minimum inter-frame separation times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will be
ready for the next message. The device will respond as appropriate during the subsequent DSI transfer. Exactly one response
is attempted.
Table 12. DSI Bus Command Summary
Command
Command Format
Description
Data
C3
C2
C1
C0
Hex
D7
D6
D5
D4
0
0
0
0
$0
Initialization
D3
D2
D1
D0
Standard Long Only
NV
BS
Bnk[1]
Bnk[0]
PA[3]
PA[2]
PA[1]
PA[0]
0
0
0
1
$1
0
0
1
0
$2
Request Status
Standard/Enhanced L/S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Read Acceleration Data
Standard/Enhanced L/S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0
1
1
$3
Not Implemented
⎯
0
1
0
0
$4
Request ID Information
0
1
0
1
$5
Not Implemented
⎯
⎯
⎯
0
1
1
0
$6
Not Implemented
0
1
1
1
$7
Clear
1
0
0
0
$8
Not Implemented
Not Implemented
⎯
⎯
⎯
1
0
0
1
$9
Read Write NVM
Standard/Enhanced L
WA[3]
WA[2]
WA[1]
WA[0]
1
0
1
0
$A
Format Control
Standard/Enhanced L
R/W
FA[2]
FA[1]
FA[0]
RD[3]
RD[2]
RD[1]
RD[0]
FD[3]
FD[2]
FD[1]
1
0
1
1
$B
Read Register Data
Standard/Enhanced L
0
0
0
FD[0]
0
RA[3]
RA[2]
RA[1]
RA[0]
1
1
0
0
$C
Disable Self-Test
Standard/Enhanced L/S
⎯
⎯
1
1
0
1
$D
Activate Self-Test
Standard/Enhanced L/S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
1
1
0
$E
Not Implemented
Not Implemented
Not Implemented
⎯
1
1
1
1
$F
Reverse Initialization
Not Implemented
Not Implemented
Not Implemented
Standard/Enhanced L/S
Not Implemented
⎯
⎯
⎯
Not Implemented
Not Implemented
Standard/Enhanced L/S
⎯
⎯
Not Implemented
Not Implemented
⎯
⎯
⎯
⎯
⎯
Not Implemented
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4.2.1.1
Initialization Command
The initialization command conforms to the description provided in Section 6.1.1 of the DSI Bus Standard V2.5. The initialization command is only supported as a standard long command. No other commands are recognized by the device until a valid
standard long initialization command is received.
Table 13. Initialization Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
NV
BS
Bnk[1]
Bnk[0]
PA[3]
PA[2]
PA[1]
PA[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
CRC
4 bits
Table 14. Initialization Command Bit Definitions
Bit Field
Definition
C[3:0]
Initialization Command = ‘0000’
A[3:0]
DSI device address. This address is set to the preprogrammed device address following reset, or to ‘0000’ if no preprogrammed address
has been assigned.
PA[3:0]
DSI Address to be programmed.
Bnk[1:0]
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for further details regarding register programming and bank selection.
BS
Bus Switch state. This bit controls the state of the DSI bus switch.
1 - Close the bus switch.
0 - Do not close the bus switch.
NV
NVM Program Enable. This bit enables programming of the user-programmed OTP locations. Data to be programmed is transferred to the
device during subsequent Read Write NVM commands.
1 - Enable OTP programming
0 - Disable OTP programming
Figure 22 illustrates the sequence of operations performed following negation of internal power-on reset (POR) and execution
of a DSI Initialization command. The BUSOUT node is tested for a bus short to high voltage condition, and the bus fault (BF) flag
is set if an error condition is detected. If no bus fault condition is detected and the BS bit is set in the Initialization command message, the bus switch will be closed. The device implements a blanking time (tDSI_BLANK_INIT) to allow for the bus voltage to recover following closure of the bus switch.
If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address.
If no device address has been previously programmed into the OTP array, PA[3:0] contains the device address, and A[3:0]
must be zero. If either addressing condition is not met, the device address is not assigned, the bus switch will remain open and
the device will not respond to the Initialization command. If the addressing conditions are met, the new device address is assigned to A[3:0]. Once the device address is assigned, the new address (A[3:0]) is not protected by the user programmable OTP
array error detection. The user programmable OTP array error detection is calculated and verified using the OTP programmed
values of A[3:0] = ‘0000’.
Once initialized, the device will no longer recognize or respond to Initialization commands.
Table 15. Initialization Command Response
Response
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
PA[3]
PA[2]
PA[1]
PA[0]
0
0
0
BF
NV
BS
Bnk[1]
Bnk[0]
PA[3]
PA[2]
PA[1]
PA[0]
CRC
4 bits
Table 16. Initialization Response Bit Definitions
Bit Field
Definition
PA[3:0]
DSI device address. This field contains the device address. If the device is unprogrammed when the initialization command is issued, the
device address is assigned. This field contains the programmed address. An Initialization command which attempts to assign a device
address of zero is ignored.
Bnk[1:0]
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for further details regarding register programming and bank selection.
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
NV
NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
BF
This bit indicates the success or failure of the bus test performed as part of the Initialization command.
1 - Bus fault detected
0 - Bus test passed
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N
INITIALIZATION
COMMAND?
Y
N
BS == 1?
Y
ENABLE IRESP CURRENT
Delay tBUSOUT_DISCHARGE
MEASURE VBUSOUT
VBUSOUT < VTHH?
N
SET BF FLAG
Y
CLOSE BUS SWITCH
DELAY
WAIT FOR NEXT DSI
BUS COMMAND
Figure 22. Initialization Sequence
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4.2.1.2
Request Status Command
The Request Status command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 17. Request Status Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
0
0
1
CRC
0 to 8 bits
Table 18. Request Status Command Bit Definitions
Bit Field
Definition
C[3:0]
Request Status Command = ‘0001’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0]
Used for CRC calculation only
Table 19. Short Response - Request Status Command
Response
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
0 to 8 bits
Table 20. Long Response - Request Status Command
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
0 to 8 bits
Table 21. Request Status Response Bit Definitions
Bit Field
S
AT[1:0]
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
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4.2.1.3
Read Acceleration Data Command
The Read Acceleration Data command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Form at Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 22. Read Acceleration Data Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
0
1
0
CRC
0 to 8 bits
Table 23. Read Acceleration Data Command Bit Definitions
Bit Field
Definition
C[3:0]
Read Acceleration Data Command = ‘0010’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0]
Used for CRC calculation only
Table 24. Short Response - Read Acceleration Data Command
Response
Response
Length
D[14]
D[13]
D[12] D[11] D[10]
D[9]
D[8]
8
9
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
AD[9]
AD[8]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[9]
AD[8]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[8]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
CRC
10
11
0 to 8 bits
12
13
14
15
AT_OTP[1]
ST
AT_OTP[0]
0
S
AD[9]
Table 25. Long Response - Read Acceleration Data Command
Response
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
S
AD[9]
AD[8]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
CRC
0 to 8 bits
Table 26. Read Acceleration Response Bit Definitions
Bit Field
AD[9:0]
S
ST
A[3:0]
AT_OTP[1:0]
Definition
Ten-bit acceleration result produced by the device.
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
DSI device address. This field contains the device address.
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
Shaded bits are transmitted to meet the response message length of the received message
The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the
minimum acceleration value is transmitted as defined in Table 27.
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Table 27. Acceleration Data Values
8-Bit Data Value
9-Bit Data Value
10-Bit Data Value
Decimal
Hex
Decimal
Hex
Decimal
Hex
255
0xFF
511
0x1FF
1023
0x3FF
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
131
0x83
259
0x103
515
0x203
130
0x82
258
0x102
514
0x202
129
0x81
257
0x101
513
0x201
128
0x80
256
0x100
512
0x200
127
0x7F
127
0x0FF
511
0x1FF
Description
Maximum positive acceleration value
Positive acceleration values
Typical 0 g level
126
0x7E
126
0x0FE
510
0x1FE
125
0x7D
125
0x0FD
509
0x1FD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
Maximum negative acceleration value
0
0
0
0
0
0
Sensor Error
4.2.1.4
Negative acceleration values
DSI Command #3
DSI Command ‘0011’ is not implemented. The device ignores all command formats with a command ID of ‘0011’.
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4.2.1.5
Request ID Information Command
The Request ID Information command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address
of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation.
Table 28. Request ID Information Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
1
0
0
CRC
0 to 8 bits
Table 29. Request ID Information Command Bit Definitions
Bit Field
Definition
C[3:0]
Request ID Information Data Command = ‘0100’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0]
Used for CRC calculation only
Table 30. Short Response - Request ID Information Command
Response
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
V2
V1
V0
0
DEVID
1
0
0
CRC
0 to 8 bits
Table 31. Long Response - Request ID Information Command
Response
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
V[2]
V[1]
V[0]
0
DEVID
1
0
0
CRC
0 to 8 bits
Table 32. Request ID Response Bit Definitions
Bit Field
D[4:0] = {1’b0,DEVID, 3’b100}
Definition
Device Identifier:‘00100’, or ‘01100’
DEVID: Bit 7 of the DEVCFG regIster
V[2:0]
Version ID. This field indicates the device / silicon revision of the device.
A[3:0]
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
4.2.1.6
DSI Command #5
DSI Command ‘0101’ is not implemented. The device ignores all command formats with a command ID of ‘0101’.
4.2.1.7
DSI Command #6
DSI Command ‘0110’ is not implemented. The device ignores all command formats with a command ID of ‘0110’.
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4.2.1.8
Clear Command
The Clear command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
When the device successfully decodes a Clear Command, and the address field matches either the assigned device address
(PA[3:0]) or the DSI Global address of ‘0000’, the bus switch is opened within TBSOPEN, and the device logic is reset. Reference
Section 3.6 for the initialization sequence following a Clear Command. The data bits D[7:0] in the command are only used in the
CRC calculation. There is no response to the Clear Command.
Table 33. Clear Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
1
1
1
CRC
0 to 8 bits
Table 34. Clear Command Bit Definitions
Bit Field
Definition
C[3:0]
Clear Command = ‘0111’.
When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI Global
Device Address of ‘0000’, the bus switch is opened within tBSOPEN, and the device logic is reset. Reference Section 3.6 for the initialization
sequence following a Clear Command.
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field or the Global
Device Address of ‘0000’. Otherwise, the command is ignored.
D[7:0]
Used for CRC calculation only
4.2.1.9
DSI Command #8
DSI Command ‘1000’ is not implemented. The device ignores all command formats with a command ID of ‘1000’.
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4.2.1.10
Write NVM Command
The Write NVM command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the
DSI Global Device Address of ‘0000’.
The Write NVM command uses the nibble address definitions in Table 3 and summarized in Table 40.
Table 35. Write NVM Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
WA[3]
WA[2]
WA[1]
WA[0]
RD[3]
RD[2]
RD[1]
RD[0]
A[3]
A[2]
A[1]
A[0]
1
0
0
1
CRC
0 to 8 bits
Table 36. Write NVM Command Bit Definitions
Bit Field
Definition
C[3:0]
Write NVM Command = ‘1001’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0]
RD[3:0] contains the data to be written to the OTP location addressed by WA[3:0] when the NV bit is set.
WA[3:0]
WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
Table 37. Long Response - Write NVM Command (NV = 1)
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
WA[3]
WA[2]
WA[1]
WA[0]
1
1
Bnk[1]
Bnk[0]
RD[3]
RD[2]
RD[1]
RD[0]
CRC
0 to 8 bits
Table 38. Long Response - Write NVM Command (NV = 0)
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
1
1
1
1
A[3]
A[2]
A[1]
A[0]
CRC
0 to 8 bits
Table 39. Write NVM Response Bit Definitions
Bit Field
Bnk[1:0]
A[3:0]
Definition
These bits provide the bank address selected in the Initialization command.
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0]
RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write.
WA[3:0]
WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization command (reference Section 4.2.1.1). If the
NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of
RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to
change the Device Address, the new Device Address is returned.
The DSI Bus idle voltage must exceed the minimum VPP voltage when programming the OTP array. No internal verification of
the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back
after writes to verify proper contents. The total execution time for the Write NVM command is tPROG_BIT times the number of bits
being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must
accommodate this timing.
Writes to the user programmable OTP array using the Write NVM command will update the mirror registers and result in a
change to the error detection calculation regardless of the state of the NV bit and the LOCK_U bit. An error detection mismatch
will only be detected if the LOCK_U bit is active (reference Section 3.2.2).
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Table 40. OTP Register Nibble Address Assignments
Bank Address
Bnk[1] Bnk[0]
Register Address (Nibble)
WA[3]
WA[2]
WA[1]
WA[0]
x
x
0
0
0
0
x
x
0
0
0
1
x
x
0
0
1
0
x
x
0
0
1
1
x
x
0
1
0
0
Register
Description
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
Only RD[3] is written to the LOCK_U bit
x
x
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
DEVCFG2[7]
0
0
1
0
0
0
TYPE[7:6]
Only RD[3:2] is written to LPF[1:0]
0
0
1
0
0
1
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
0
0
1
0
1
0
DEVCFG[7:4]
Only RD[3] is written to the DEVID bit
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
0
DEVCFG1[3:0]
Only RD[1:0] is written to AT[1:0]
0
1
0
1
1
1
DEVCFG2[3:0]
RD[3:0] is written to ADDR[3:0]
0
1
1
0
0
0
UD01[3:0]
RD[3:0] is written to UD01[3:0]
0
1
1
0
0
1
UD02[3:0]
RD[3:0] is written to UD02[3:0]
0
1
1
0
1
0
UD03[3:0]
RD[3:0] is written to UD03[3:0]
0
1
1
0
1
1
UD04[3:0]
RD[3:0] is written to UD04[3:0]
0
1
1
1
0
0
UD05[3:0]
RD[3:0] is written to UD05[3:0]
0
1
1
1
0
1
UD06[3:0]
RD[3:0] is written to UD06[3:0]
0
1
1
1
1
0
UD07[3:0]
RD[3:0] is written to UD07[3:0]
0
1
1
1
1
1
1
0
0
1
1
0
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
1
0
0
1
1
1
DEVCFG2[5]
Only RD[1] is written to the PCM bit
1
0
1
0
0
0
UD01[7:4]
RD[3:0] is written to UD01[7:4]
1
0
1
0
0
1
UD02[7:4]
RD[3:0] is written to UD02[7:4]
1
0
1
0
1
0
UD03[7:4]
RD[3:0] is written to UD03[7:4]
1
0
1
0
1
1
UD04[7:4]
RD[3:0] is written to UD04[7:4]
1
0
1
1
0
0
UD05[7:4]
RD[3:0] is written to UD05[7:4]
1
0
1
1
0
1
UD06[7:4]
RD[3:0] is written to UD06[7:4]
1
0
1
1
1
0
UD07[7:4]
RD[3:0] is written to UD07[7:4]
1
0
1
1
1
1
UD08[7:4]
RD[3:0] is written to UD08[7:4]
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
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4.2.1.11
Format Control Command
The Format Control command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Format Control command if the command is in any other format. The device supports the Format Control command with the DSI Global Address of ‘0000’, but does not provide a response.
Table 41. Format Control Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
R/W
FA[2]
FA[1]
FA[0]
FD[3]
FD[2]
FD[1]
FD[0]
A[3]
A[2]
A[1]
A[0]
1
0
1
0
CRC
0 to 8 bits
Table 42. Format Control Command Bit Definitions
Bit Field
Definition
C[3:0]
Format Control Command = ‘1010’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
FD[3:0]
Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to ‘1’.
FA[2:0]
The Address of the Format Control Register to read or written.
Read/Write determines if the register at address FA[2:0] is to be read or written.
1 - Write FD[3:0] to the Format Control Register addressed by FA[2:0]
0 - Read the Format Control Register addressed by FA[2:0]
R/W
Table 43. Long Response - Format Control Command
Response
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
1
1
0
R/W
FA[2]
FA[1]
FA[0]
FD[3]
FD[2]
FD[1]
FD[0]
CRC
0 to 8 bits
Table 44. Format Control Response Bit Definitions
Bit Field
FD[3:0]
FA[2:0]
Definition
The contents of the Format Control Register addressed by FA[2:0].
The Address of the Format Control Register that was read or written.
Read/Write indicates if the register at address FA[2:0] was read or written.
1 - FD[3:0] contains the data written to the Format Control Register addressed by FA[2:0]
0 - FD[3:0] contains the contents for the Format Control Register addressed by FA[2:0]
R/W
A[3:0]
DSI device address. This field contains the device address.
The format control registers defined in the DSI Bus Standard V2.5 are shown in Table 45. The reset values assigned to each
register are also indicated.
Table 45. Format Control Register Values
Format Control Register
Register Address
Reset Values
DSI Standard Values
FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] FD[3] FD[2] FD[1] FD[0]
CRC Polynomial - Low Nibble
0
0
0
0
0
0
1
0
0
0
1
CRC Polynomial - High Nibble
0
0
1
0
0
0
1
0
0
0
1
Seed - Low Nibble
0
1
0
1
0
1
0
1
0
1
0
Seed - High Nibble
0
1
1
0
0
0
0
0
0
0
0
Definition
CRC Polynomial = X4+1
Seed = ‘1010’
CRC Length (0 to 8)
1
0
0
0
1
0
0
0
1
0
0
CRC Length = 4
Short Word Data Length (8 to 15)
1
0
1
1
0
0
0
1
0
0
0
Short Command Length = 8
Reserved
1
1
0
0
0
0
0
0
0
0
0
N/A
Format Selection
1
1
1
0
0
0
0
0
0
0
0
N/A
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The following restrictions apply to format control register operations:
• Writes to the CRC Length Register of values greater than 8 are ignored. The contents of the register are
unchanged.
• Writes to the Short Word Data Length register of values less than 8 are ignored. The contents of the register are
unchanged.
The contents of the Format Selection register determine whether the standard DSI values or the values in the format control
registers are used. If the Format Selection register contains ‘1111’, the Format Control register values are active. Any write to the
Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Command will maintain the format of the previous command resulting in an invalid response.
A write of ‘0000’ to the Format Selection register activates the standard DSI values.
A write to the Format Selection register of any other value is ignored.
4.2.1.12
Read Register Data Command
The Read Register Data command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to
the DSI Global Device Address of ‘0000’.
The read register command uses the byte address definitions shown in Table 3. Readable registers along with their Byte addresses are shown in Table 3.
Table 46. Read Register Data Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
0
0
0
0
RA[3]
RA[2]
RA[1]
RA[0]
A[3]
A[2]
A[1]
A[0]
1
0
1
1
CRC
0 to 8 bits
Table 47. Read Register Data Command Bit Definitions
Bit Field
Definition
C[3:0]
Read Register Data Command = ‘1011’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
RA[3:0]
RA[3:0] contains the byte address of the register to be read.
Table 48. Long Response - Read Register Data Command
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
RA[3]
RA[2]
RA[1]
RA[0]
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
CRC
0 to 8 bits
Table 49. Read Register Data Response Bit Definitions
Bit Field
Definition
RD7:0]
RD[7:0] contains the data of the register addressed by RA[3:0].
RA[3:0]
RA[3:0] contains the byte address of the register to be read.
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
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4.2.1.13
Disable Self-Test Command
The Disable Self-Test command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-Test command
with the DSI Global Address of ‘0000’, but does not provide a response.
The Disable Self-Test Command removes the voltage from the self-test plate of the transducer which results in the acceleration
output value returning to the 0g offset value within tST_DEACT_xxx, as specified in Section 2.
Table 50. Disable Self-Test Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
1
1
0
0
CRC
0 to 8 bits
Table 51. Disable Self-Test Command Bit Definitions
Bit Field
Definition
C[3:0]
Disable Self-Test Command = ‘1100’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0]
Used for CRC calculation only
Table 52. Short Response - Disable Self-Test Command
Response
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
0 to 8 bits
Table 53. Long Response - Disable Self-Test Command
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
0 to 8 bits
Table 54. Disable Self-Test Response Bit Definitions
Bit Field
S
AT[1:0]
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout
is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:
• HCAP under-voltage
• A Clear command is received
• Internal regulator under-voltage resulting in a reset.
• A Frame Timeout resulting in a reset.
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4.2.1.14
Enable Self-Test Command
The Enable Self-Test command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command
when it is sent to the DSI Global Address of ‘0000’.
The Enable Self-Test Command applies a voltage to the self-test plate of the transducer which results in a delta in the acceleration output value of ΔDFLCT_xxx within tST_ACT_xxx, as specified in Section 2. This remains present until the Disable Self-Test
command is received.
Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal
self-test circuitry remains disabled, and the ST bit is cleared in the response. Self-Test locking is described in Section 4.2.1.13.
Table 55. Enable Self-Test Command
Data
Address
Command
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
1
1
0
1
CRC
4 bits
Table 56. Enable Self-Test Command Bit Definitions
Bit Field
Definition
C[3:0]
Enable Self-Test Command = ‘1101’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0]
Used for CRC calculation only
Table 57. Short Response - Enable Self-Test Command
Response
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
4 bits
Table 58. Long Response - Enable Self-Test Command
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
BS
AT[1]
AT[0]
S
0
CRC
4 bits
Table 59. Enable Self-Test Response Bit Definitions
Bit Field
S
AT[1:0]
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
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4.2.1.15
DSI Command #14
DSI Command ‘1110’ is not implemented. The device ignores all command formats with a command ID of ‘1110’.
4.2.1.16
Reverse Initialization Command
The Reverse Initialization Command is not implemented. The device ignores all command formats with a command ID of
‘1111’. The device ignores all command received on the BUSOUT pin.
4.3
Exception Handling
Table 60 summarizes the exception conditions detected by the device and the response for each exception.
Table 60. Exception Handling
Condition
Description
S ST U
Response
Exception
Self-Test
Request
Power On
Reset
N/A
Power Applied
Clear Command
VREG
Under-Voltage
N/A
VREG < VPORCREG_f
–
–
–
–
Device held in Reset.
No response to DSI commands.
Bus switch open within tBSOPEN.
Device must be re-initialized when VREG returns above VPORCREG_r
VREGA
Under-Voltage
N/A
VREGA < VPORCREG_f
–
–
–
–
Device held in Reset.
No response to DSI commands.
Bus switch open within tBSOPEN.
Device must be re-initialized when VREGA returns above VPORCREGA_r
1
1
0
– Reference Section 3.6
Disabled
VHCAP < VPORCREG_f for less
than tHCAP_POR, ST Disabled
0
0
1
– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
– Device does not need to be re-initialized if VHCAP returns above
VPORHCAP_r before tHCAP_POR
Enabled
VHCAP < VPORCREG_f for less
than tHCAP_POR, ST Enabled
0
1
1
– DSI Read Acceleration Data Short response = self-test data.
– DSI Read Acceleration Data Long response = self-test data.
– Device does not need to be re-initialized if VHCAP returns above
VPORHCAP_r before tHCAP_POR
VHCAP
Under-Voltage
Transient
VHCAP
Under-Voltage
N/A
Capacitor Test
Failure
N/A
DSI Frame
Timeout
N/A
– Device is Reset and will continue to Reset every tHCAP_POR until VHCAP
returns above VPORHCAP_r, or an internal supply under-voltage condition
occurs.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VHCAP returns above VPORHCAP_r
VHCAP < VPORCREG_f for longer
than tHCAP_POR
– Device is Reset and will continue to be reset every tPOR_CAPTEST until the
capacitor failure is removed.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when capacitor failure is removed.
– Device is Reset and will continue to be reset every tTO until the BUSIN
voltage returns above VTHF or a supply under-voltage condition occurs.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VBUSIN returns above VTHF
VBUSIN < VTHF for longer than tTO
Disabled
CRC failure detected in factory
programmed OTP array and the
LOCK_F bit is set. ST Disabled
1
0
0
– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
Enabled
CRC failure detected in factory
programmed OTP array and the
LOCK_F bit is set. ST Enabled
1
1
0
– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = self-test data.
Disabled
Mismatch detected in User programmed OTP array and the
LOCK_U bit is set. ST Disabled
1
0
0
– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
Enabled
Mismatch detected in User programmed OTP array and the
LOCK_U bit is set. ST Enabled
1
1
0
– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = self-test data.
Self-Test
Enabled
Enabled
ST Enabled
1
1
0
– Internal self-test circuitry enabled.
– DSI Read Acceleration Data Short response = self-test data.
– DSI Read Acceleration Data Long response = self-test data.
Self-Test
Lockout
Disabled
Two consecutive Disable SelfTest DSI commands received.
0
0
0
– Internal self-test circuitry disabled.
– Enable Self-Test DSI command does not enable Self-Test. Normal
response to Enable Self-Test DSI command except the ST bit is not set.
– DSI Clear command or Reset disables lockout.
Fuse CRC
Fault
(Factory Array)
Fuse Error
Detection Fault
(User Array)
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5
Package
5.1
Case Outline Drawing
Reference Freescale Case Outline Drawing # 98ASA00090D
http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf
5.2
Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Table 61. Revision History
Revision
number
Revision
date
4
03/2012
• Added SafeAssure logo, changed first paragraph and disclaimer to include trademark
information.
5
09/2012
• Section 2.3: Removed Temperature Monitoring Characteristic, lines 36 and 37.
• Section 2.4: Changed Min values for BUSIN Bias Current lines 42 and 43 from -100 to 0 and Min
values BUSOUT Bias Current lines 44 and 53 from “-100” to “0”.
• Section 2.7: updated line109 in table; Following Read Write NVM Command Min value was 2
changed to 12. Deleted line 115 OTP Program Timing.
• Section 3: Global change all instances of “CRC check” to “error detection and several instances
of “CRC verification” to “error detection”.
• Table 2: Updated byte address $05 Bits 6-3 from “UNUSED” to “0”, Bits 2-1 from “CRC_U[x]” to
“0”. $06: Bits 7-2 from “UD00[x]” to “0”. $07; Bit 6 was “UNUSED” changed to “0”. Bit Function 4
was RESERVED, changed to “0”. $0F Bits 3-0 from “UD08[x]” to “0”.
• Table 4: Changed bits 3-0 from “CRC_U[x]” to “0”.
• Deleted Section 3.1.3.2.
• Table 5: Changed bits 7-2 from “UD00[x]” to “0”.
• Deleted Section 3.1.4.1.
• Table 3.1.6: Row $0F, Bits 3-0 from “UD08[x]” to “0”.
• Section 3.2.2: Updated and deleted paragraphs. Deleted “Included In User CRC?” column in
second table, deleted rows “User Data Register 0”, “RESERVED Bit”, “User Programmable OTP
Array CRC” and “User Programmable OTP Array Lock Bit”.
• Table 6: Updated Bit Function 6 was UNUSED changed to “0”. Bit Function 4 was RESERVED,
changed to “0”.
• Table 39: Changed registers for DEVCGF[3:0], DEVCGF[7:4], DEVCGF1[3:0], UDD8[3:0],
DEVCGF1[7:4], DEVCFG2[4], and DEVCGF2[6] and updated descriptions.
• Table 59: Row “Fuse CRC Fault” updated descriptions for Disabled and Enabled. Removed
“Temperature Out of Range” row.
5.1
03/2012
• Table 1: Updated description for C1 and C2.
Description of changes
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Document Number: MMA16xxKW
Rev. 5.1
03/2013
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