SA630
Single-Pole Double-Throw (SPDT) switch
Rev. 3 — 23 July 2014
Product data sheet
1. General description
The SA630 is a wideband RF switch fabricated in BiCMOS technology and incorporating
on-chip CMOS/TTL compatible drivers. Its primary function is to switch signals in the
frequency range DC to 1 GHz from one 50 channel to another. The switch is activated
by a CMOS/TTL compatible signal applied to the enable channel 1 pin (ENCH1).
The extremely low current consumption makes the SA630 ideal for portable applications.
The excellent isolation and low loss makes this device a suitable replacement for PIN
diodes.
The SA630 is available in an 8-pin SO (surface-mounted miniature) package.
2. Features and benefits
Wideband (DC to 1 GHz)
Low through loss (1 dB typical at 200 MHz)
Unused input is terminated internally in 50
Excellent overload capability (1 dB gain compression point +18 dBm at 300 MHz)
Low DC power (170 A from 5 V supply)
Fast switching (20 ns typical)
Good isolation (off channel isolation 60 dB at 100 MHz)
Low distortion (IP3 intercept +33 dBm)
Good 50 match (return loss 18 dB at 400 MHz)
Full ESD protection
Bidirectional operation
3. Applications
Digital transceiver front-end switch
Antenna switch
Filter selection
Video switch
FSK transmitter
SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
4. Ordering information
Table 1.
Ordering information
Type number
SA630D/01
Topside
marking
Package
Name
Description
Version
SA630D
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature
SA630D/01
SA630D/01,112
SO8
Standard marking
*IC’s tube - DSC bulk pack
2000
Tamb = 40 C to +85 C
SA630D/01,118
SO8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
5. Block diagram
Fig 1.
SA630
Product data sheet
input/output
output/input
output/input
ENCH1
aaa-013987
Block diagram
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Rev. 3 — 23 July 2014
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
6. Pinning information
6.1 Pinning
VDD
1
GND
2
8
OUT1
7
AC_GND
SA630D/01
INPUT
3
6
GND
ENCH1
4
5
OUT2
aaa-013986
Fig 2.
Pin configuration for SO8
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VDD
1
supply voltage
GND
2, 6
ground
INPUT
3
input
ENCH1
4
enable channel 1
OUT2
5
output
AC_GND
7
AC ground
OUT1
8
output
7. Equivalent circuit
VDD
+5 V
1
8
OUT1
20 kΩ
CONTROL
LOGIC
50 Ω
7
2
AC bypass
50 Ω
6
INPUT
3
20 kΩ
5
ENCH1
(logic 0 level)
Fig 3.
SA630
Product data sheet
4
OUT2
aaa-013988
Equivalent circuit
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Rev. 3 — 23 July 2014
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
Tamb = 25 C (still air)
[1]
Min
Max
Unit
0.5
+5.5
V
P
power dissipation
-
780
mW
Tj(max)
maximum junction
temperature
-
150
C
Pi(max)
maximum input power
-
+20
dBm
Po(max)
maximum output power
-
+20
dBm
Tstg
storage temperature
65
+150
C
[1]
Maximum dissipation is determined by the operating ambient temperature and the thermal resistance
Rth(j-a).
9. Recommended operating conditions
Table 5.
Operating conditions
Symbol
Parameter
Conditions
VDD
supply voltage
Tamb
ambient temperature
Tj
junction temperature
Min
Max
Unit
3.0
5.5
V
operating
40
+85
C
operating
40
+105
C
10. Thermal characteristics
Table 6.
SA630
Product data sheet
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction
to ambient
SO8 package
158
C/W
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
11. Static characteristics
Table 7.
Static characteristics
VDD = +5 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
IDD
supply current
Conditions
[1]
Min
Typ
Max
Unit
40
170
300
A
Vth
threshold voltage
TTL/CMOS logic
1.1
1.25
1.4
V
VIH
HIGH-level input voltage
logic 1 level;
enable channel 1
2.0
-
VDD
V
VIL
LOW-level input voltage
logic 0 level;
enable channel 2
0.3
-
+0.8
V
IIL(ENCH1)
LOW-level input current on pin ENCH1
ENCH1 = 0.4 V
1
0
+1
A
IIH(ENCH1)
HIGH-level input current on pin ENCH1
ENCH1 = 2.4 V
1
0
+1
A
[1]
The ENCH1 input must be connected to a valid logic level for proper operation of the SA630.
12. Dynamic characteristics
Table 8.
Dynamic characteristics
All measurements include the effects of the SA630 evaluation board (Figure 19). Measurement system impedance is 50 .
Symbol
Parameter
s21, s12
insertion loss (ON channel)
s21, s12
isolation (OFF
channel)[1]
s11, s22
return loss (ON channel)
s11, s22
return loss (OFF channel)
Conditions
Min
Typ
Max
Unit
DC to 100 MHz
-
1
-
dB
500 MHz
-
1.4
-
dB
900 MHz
-
2
2.8
dB
10 MHz
70
80
-
dB
100 MHz
-
60
-
dB
500 MHz
-
50
-
dB
900 MHz
24
30
-
dB
DC to 400 MHz
-
20
-
dB
900 MHz
-
12
-
dB
DC to 400 MHz
-
17
-
dB
900 MHz
-
13
-
dB
td(off)
turn-off delay time
50 % TTL to
(90 % to 10 %) RF
-
20
-
ns
tf(off)
turn-off fall time
90 % to 10 % RF
-
5
-
ns
tr(on)
turn-on rise time
10 % to 90 % RF
-
5
-
ns
Vtrt(p-p)
peak-to-peak transient voltage
switching transients
-
165
-
mV
PL(1dB)
output power at 1 dB gain compression
DC to 1 GHz
-
+18
-
dBm
IP3
third-order intercept point
100 MHz
-
+33
-
dBm
IP2
second-order intercept point
100 MHz
-
+52
-
dBm
NF
noise figure
Zo = 50
100 MHz
-
1.0
-
dB
900 MHz
-
2.0
-
dB
[1]
The placement of the AC bypass capacitor is critical to achieve these specifications. See Section 14 for more details.
SA630
Product data sheet
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
13. Performance curves
DDE
DDE
,''
$
6
G%
9'' 9
9
9
7DPE &
&
&
9''9
I0+]
Tamb = +25 C
Fig 4.
Supply current versus VDD and temperature
Fig 5.
Loss versus frequency and VDD
DDE
DDE
6
G%
6
G%
&+
9'' 9
9
9
&+
I0+]
Tamb = +25 C
Fig 6.
Tamb = +25 C; VDD = 5 V
Loss versus frequency and VDD
Fig 7. Loss matching versus frequency;
CH1 versus CH2
DDE
DDE
6
G%
I0+]
6
G%
7DPE &
&
&
9'' 9
9
9
I0+]
Tamb = +25 C
Fig 8. Loss versus frequency and temperature
Product data sheet
I0+]
VDD = 5 V
SA630
Fig 9.
Isolation versus frequency and VDD
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
DDE
DDE
6
G%
6
G%
9'' 9
9
9
&+
&+
I0+]
Tamb = +25 C; VDD = 5 V
Tamb = +25 C
Fig 10. Isolation matching versus frequency;
CH1 versus CH2
Fig 11. Input match ON-channel versus frequency and
VDD
DDE
I0+]
6
G%
DDE
6
G%
&+9
&+9
&+9
I0+]
Tamb = +25 C; VDD = 5 V
Tamb = +25 C
Fig 12. Output match ON-channel versus frequency
DDE
Fig 13. OFF-channel match versus frequency and VDD
7DPE &
&
&
DDE
3/G%
G%P
6
G%
I0+]
9
9
9
I0+]
Tamb = +25 C
Fig 14. OFF-channel match versus frequency and
temperature
Product data sheet
I0+]
VDD = 5 V
SA630
Fig 15. PL(1dB) versus frequency and VDD
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
DDE
1)
G%
,3
9'' 9
9
9
,3
DDE
LQWHUFHSWSRLQW
G%P
9''9
I0+]
Tamb = +25 C
Tamb = +25 C; Zo = 50
Fig 16. Intercept points versus VDD
Fig 17. Noise Figure versus frequency and VDD
1V
ENCH1 (pin 4)
OUT1 (pin 8)
50 mV
10 nS
aaa-014013
fi = 100 MHz at 6 dBm; VDD = 5 V
Fig 18. Switching speed
SA630
Product data sheet
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Rev. 3 — 23 July 2014
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
14. Application information
The typical application schematic and printed-circuit board layout of the SA630 evaluation
board is shown in Figure 19. The layout of the board is simple, but a few cautions must be
observed. The input and output traces should be 50 . If a symmetric isolation between
the two channels is desired, then the placement of the AC bypass capacitor is extremely
critical. The trace from AC_GND (pin 7) should be drawn back towards the package and
then be routed downwards. The capacitor should be placed straight down as close to the
device as practical.
For better isolation between the two channels at higher frequencies, it is also advisable to
run the two output/input traces at an angle. This arrangement also minimizes any
inductive coupling between the two traces. The power supply bypass capacitor should be
placed close to the device. Figure 5 shows the frequency response of the SA630. The
loss matching between the two channels is excellent to 1.2 GHz, as shown in Figure 7.
VDD
+5 V
0.1 μF
0.01 μF
GND
7
2
SA630
0.01 μF
INPUT
ENCH1
OUT1
8
1
3
6
4
5
AC_GND
GND
0.01 μF
OUT2
0.01 μF
aaa-013989
a. Evaluation board schematic
aaa-013990
b. SA630 board layout
Fig 19. Evaluation board and layout
SA630
Product data sheet
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Rev. 3 — 23 July 2014
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
The isolation and matching of the two channels over frequency is shown in Figure 9 and
Figure 10, respectively.
The SA630 is a very versatile part and can be used in many applications. Figure 20 shows
a block diagram of a typical digital RF transceiver front-end. In this application, the SA630
replaces the duplexer, which is typically very bulky and lossy. Due to the low power
consumption of the device, it is ideally suited for handheld applications such as in CT2
cordless telephones. The SA630 can also be used to generate Amplitude Shift Keying
(ASK) or On-Off Keying (OOK) and Frequency Shift Keying (FSK) signals for digital RF
communications systems. Block diagrams for these applications are shown in Figure 21
and Figure 22, respectively.
For applications that require a higher isolation at 1 GHz than obtained from a single
SA630, several SA630s can be cascaded as shown in Figure 23. The cascaded
configuration has a higher loss, but greater than 35 dB of isolation at 1 GHz and greater
than 65 dB at 500 MHz can be obtained from this configuration. By modifying the enable
control, an RF multiplexer/demultiplexer or antenna selector can be constructed. The
simplicity of SA630 coupled with its ease of use and high performance lends itself to many
innovative applications.
The SA630 switch terminates the OFF channel in 50 . The 50 resistor is internal and
is in series with the external AC bypass capacitor. Matching to impedances other than
50 can be achieved by adding a resistor in series with the AC bypass capacitor (for
example, 25 additional to match to a 75 environment).
5200
602A
IF OUT
MICROCONTROLLER
SA630
KEYPAD
AND
DISPLAY
TX/RX
5200
VCO
modulation
aaa-014009
Fig 20. A typical TDMA/digital RF transceiver system front-end
ASK output
oscillator
f1
FSK output
SA630
SA630
enable
CH1
TTL data
50 Ω
Product data sheet
aaa-014011
Fig 22. Frequency Shift Keying (FSK)
generator
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Rev. 3 — 23 July 2014
enable
CH1
TTL data
aaa-014010
Fig 21. Amplitude Shift Keying (ASK)
generator
SA630
f2
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 20
SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
OUT1/IN1
SA630
IN/OUT
SA630
SA630
OUT2/IN2
enable
aaa-014012
Fig 23. Cascaded configuration
SA630
Product data sheet
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
15. Package outline
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Fig 24. Package outline SOT96-1 (SO8)
SA630
Product data sheet
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Rev. 3 — 23 July 2014
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12 of 20
SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SA630
Product data sheet
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.
SA630
Product data sheet
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering: PCB footprints
î
î
VROGHUODQGV
RFFXSLHGDUHD
SODFHPHQWDFFXUDF\
'LPHQVLRQVLQPP
VRWBIU
Fig 26. PCB footprint for SOT96-1; reflow soldering
SA630
Product data sheet
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Rev. 3 — 23 July 2014
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15 of 20
SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
î
HQODUJHGVROGHUODQG
î
î
î
ERDUGGLUHFWLRQ
VROGHUODQGV
RFFXSLHGDUHD
VROGHUUHVLVW
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Fig 27. PCB footprint for SOT96-1; wave soldering
18. Abbreviations
Table 11.
SA630
Product data sheet
Abbreviations
Acronym
Description
ASK
Amplitude Shift Keying
BiCMOS
Bipolar Complementary Metal-Oxide Semiconductor
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
FSK
Frequency Shift Keying
OOK
On-Off Keying
PCB
Printed-Circuit Board
PIN
Positive-doped/Intrinsic/Negative-doped diode
RF
Radio Frequency
SPDT
Single-Pole Double-Throw
TTL
Transistor-Transistor Logic
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
19. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SA630 v.3
20140723
Product data sheet
-
SA630 v.2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number SA630N is discontinued and removed from this data sheet
Type number SA630D is discontinued and removed from this data sheet
Type number SA630D/01 is added to this data sheet
Added Section 4.1 “Ordering options”
Added Section 6.2 “Pin description”
Added Section 10 “Thermal characteristics”
Deleted (old) “AC ELECTRICAL CHARACTERISTICS - N PACKAGE”
Deleted (old) Figure 4c, “630 N-Package Board Layout”
Deleted (old) Figure 12, “Loss Matching vs. Frequency for N-Package (DIP)”
Deleted (old) Figure 16, “Isolation Matching vs. Frequency for N-Package (DIP)”
Deleted (old) package outline drawing SOT97-1 (DIP8)
Added Section 16 “Soldering of SMD packages”
Added Section 17 “Soldering: PCB footprints”
Added Section 18 “Abbreviations”
SA630 v.2
19971107
Product specification
ECN 853-1577 18666
NE/SA630 v.1
NE/SA630 v.1
19911010
Product specification
ECN 853-1577 04269
-
SA630
Product data sheet
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SA630
NXP Semiconductors
Single-Pole Double-Throw (SPDT) switch
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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22. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
20.1
20.2
20.3
20.4
21
22
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Performance curves . . . . . . . . . . . . . . . . . . . . . 6
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Soldering of SMD packages . . . . . . . . . . . . . . 13
Introduction to soldering . . . . . . . . . . . . . . . . . 13
Wave and reflow soldering . . . . . . . . . . . . . . . 13
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering: PCB footprints. . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 23 July 2014
Document identifier: SA630