Data Sheet

DISCRETE SEMICONDUCTORS
DATA SHEET
dbook, halfpage
MBD128
BF1102; BF1102R
Dual N-channel dual gate
MOS-FETs
Product specification
Supersedes data of 1999 Jul 01
2000 Apr 11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
FEATURES
BF1102; BF1102R
PINNING - SOT363
 Two low noise gain controlled amplifiers in a single
package
DESCRIPTION
PIN
BF1102
 Specially designed for 5 V applications
1
 Superior cross-modulation performance during AGC
 High forward transfer admittance
 High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.
gate 1 (1)
gate 1 (1)
2
gate 2 (1 and 2)
source (1 and 2)
3
drain (1)
drain (1)
4
drain (2)
drain (2)
5
source (1 and 2) gate 2 (1 and 2)
6
gate 1 (2)
gate 1 (2)
g2 (1, 2)
handbook, halfpage
6
DESCRIPTION
BF1102R
5
4
g1 (1)
The BF1102 and BF1102R are both two equal dual gate
MOS-FETs which have a shared source pin and a shared
gate 2 pin. Both devices have interconnected source and
substrate; an internal bias circuit enables DC stabilization
and a very good cross-modulation performance at 5 V
supply voltage; integrated diodes between the gates and
source protect against excessive input voltage surges.
Both devices have a SOT363 micro-miniature plastic
package.
g1 (2)
1
2
3
BF1102 marking code: W1.
BF1102R marking code: W2-.
AMP1
d (1)
d (2)
AMP2
s (1, 2)
MBL029
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Per MOS-FET unless otherwise specified
VDS
drain-source voltage


7
V
ID
drain current (DC)


40
mA
Ptot
total power dissipation
Ts  102 C; note 1


200
mW
yfs
forward transfer admittance
ID = 15 mA
36
43

mS
Cig1-s
input capacitance at gate 1
ID = 15 mA

2.8
3.6
pF
Crss
reverse transfer capacitance
f = 1 MHz

30
50
fF
F
noise figure
f = 800 MHz

2
2.8
dB
Xmod
cross-modulation
input level for k = 1% at 40 dB AGC
100


dBV
Tj
operating junction temperature


150
C
Note
1. Ts is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2000 Apr 11
2
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
VDS
drain-source voltage

ID
drain current (DC)
IG1
gate 1 current
IG2
gate 2 current
Ptot
total power dissipation
Tstg
storage temperature
Tj
operating junction temperature

Ts  102 C
7
V

40
mA

10
mA

10
mA

200
mW
65
+150
C
150
C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-s
PARAMETER
thermal resistance from junction to soldering point
MGS359
250
handbook, halfpage
Ptot
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
2000 Apr 11
3
VALUE
UNIT
240
K/W
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
STATIC CHARACTERISTICS
Tj = 25 C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT

V
Per MOS-FET unless otherwise specified
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0; ID = 10 A
7
V(BR)G1-SS
gate 1-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA
6
15
V
V(BR)G2-SS
gate 2-source breakdown voltage VGS = VDS = 0; IG2-S = 5 mA
6
15
V
V(F)S-G1
forward source-gate 1 voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate 2 voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate 1-source threshold voltage
VDS = 5 V; VG2-S = 4 V; ID = 100 A
0.3
1
V
VG2-S(th)
gate 2-source threshold voltage
VDS = 5 V; VG1-S = 4 V; ID = 100 A
0.3
1.2
V
IDSX
drain-source current
VG2-S = 4 V; VDS = 5 V; RG = 120 k; note 1
12
20
mA
IG1-S
gate 1 cut-off current
VG1-S = 5 V; VG2-S = VDS = 0

50
nA
IG2-S
gate 2 cut-off current
VG2-S = 5 V; VG1-S = VDS = 0

20
nA
MAX.
UNIT
Note
1. RG1 connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
Per MOS-FET unless otherwise specified (note 1)
yfs
forward transfer admittance
Tj = 25 C
36
43
50
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz
2
2.8
3.6
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz; (note 2)


7
pF
Coss
output capacitance
f = 1 MHz

1.6
2.5
pF
Crss
reverse transfer capacitance
f = 1 MHz

30
50
fF
F
noise figure
f = 800 MHz; YS = YS opt

2
2.8
dB
Xmod
cross-modulation
fw = 50 MHz; funw = 60 MHz; (note 3)
input level for k = 1% at 0 dB AGC
85


dBV
input level for k = 1% at 40 dB AGC
100


dBV
Notes
1. Not used MOS-FET: VG1-S = 0; VDS = 0.
2. Gate 2 capacitance of both MOS-FETs.
3. Measured in test circuit of Fig.20.
2000 Apr 11
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
ALL GRAPHS FOR ONE MOS-FET
MGS360
30
handbook, halfpage
VG2-S = 4 V
ID
3.5 V
(mA)
3V
MGS361
30
handbook, halfpage
2.5 V
ID
(mA)
VG1-S = 1.5 V
2V
1.4 V
20
20
1.3 V
1.2 V
1.5 V
10
10
1.1 V
1V
1V
0
0
0.4
0.8
1.2
1.6
0
0
2.0
2.4
VG1-S (V)
VDS = 5 V.
Tj = 25 C.
2
4
6
8
10
VDS (V)
VG2-S = 4 V.
Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGS362
160
handbook, halfpage
IG1
(μA)
MGS363
50
|yfs |
VG2-S = 4 V
handbook, halfpage
3.5 V
VG2-S = 4 V
(mS)
3.5 V
40
120
3V
3V
30
80
2.5 V
2.5 V
20
2V
40
10
2V
0
0
0.5
1
1.5
0
2
2.5
VG1-S (V)
0
10
Tj = 25 C.
VDS = 5 V.
Tj = 25 C.
Fig.5
Fig.6
VDS = 5 V.
Gate 1 current as a function of gate 1
voltage; typical values.
2000 Apr 11
5
20
ID (mA)
30
Forward transfer admittance as a function
of drain current; typical values.
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS364
25
ID
(mA)
MGS365
15
handbook, halfpage
handbook, halfpage
ID
(mA)
20
10
15
10
5
5
0
0
0
20
40
I G1 (μA)
60
0
1
2
3
4
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.7
Fig.8
Drain current as a function of gate 1 current;
typical values.
Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MGS366
30
handbook, halfpage
MGS367
20
68 kΩ
RG1 = 47 kΩ
handbook, halfpage
ID
(mA)
82 kΩ
ID
(mA)
5
VGG (V)
100 kΩ
VG1-S = 5 V
4.5 V
16
4V
120 kΩ
20
3.5 V
150 kΩ
12
3V
180 kΩ
220 kΩ
8
10
4
0
0
2
4
6
0
8
10
VGG = VDS (V)
0
2
4
VG2-S (V)
VG2-S = 4 V; Tj = 25 C.
RG1 connected to VGG; see Fig.20.
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.9
Fig.10 Drain current as a function of gate 2
voltage; typical values.
Drain current as a function of gate 1 (= VGG)
and drain supply voltage; typical values.
2000 Apr 11
6
6
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS368
40
MCD968
0
handbook, halfpage
handbook,
gain halfpage
I G1
(μA)
reduction
(dB)
−10
VG1-S = 5 V
30
4.5 V
−20
4V
20
3.5 V
−30
3V
10
−40
−50
0
0
2
4
VG2-S (V)
6
0
1
2
3
VAGC (V)
4
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C;
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of the
AGC voltage; see Fig.20.
MGS369
120
MCD969
20
handbook, halfpage
handbook, halfpage
ID
(mA)
Vunw
(dB μV)
16
110
12
100
8
90
4
80
0
20
0
40
60
gain reduction (dB)
0
10
20
30
40
50
gain reduction (dB)
VDS = 5 V; VGG = 5 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C;
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C;
RG1 = 120 k (connected to VGG); see Fig.20.
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction;
typical values.
2000 Apr 11
Fig.14 Drain current as a function of gain
reduction; typical values.
7
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS370
102
handbook, halfpage
MCD970
103
handbook, halfpage
yis
(mS)
ϕrs
(deg)
yrs
(mS)
ϕrs
102
10
−103
−102
yrs
bis
1
−10
10
g is
10 −1
10
102
f (MHz)
1
10
103
−1
103
102
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGS372
102
handbook, halfpage
|yfs |
102
yos
(mS)
− ϕ fs
|y fs|
(mS)
MCD971
10
handbook, halfpage
(deg)
bos
ϕ fs
10
10
1
gos
1
10
102
f (MHz)
10−1
10
1
103
102
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2000 Apr 11
8
103
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MCD972
0
handbook, halfpage
crosstalk
level
(dB)
−20
−40
−60
−80
0
200
400
600
800
1000
f (MHz)
Active amplifier: VDS = 5 V; VG2 = 4 V; ID = 15 mA.
Non-active amplifier: VDS = VG1-S = 0 V.
Source and load impedances: 50  (both amplifiers).
Tamb = 25 C.
Fig.19 Crosstalk as a function of frequency:
Output level of non-active amplifier related
to output level of active amplifier; typical
values.
VAGC
handbook, full pagewidth
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
L1
C2
RGEN
50 Ω
VI
R2
50 Ω
DUT
≈ 2.2 μH
RL
50 Ω
C4
4.7 nF
RG1
4.7 nF
VGG
VDS
MGS315
Fig.20 Cross-modulation test set-up (for one MOS-FET).
2000 Apr 11
9
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
Table 1
f
(MHz)
BF1102; BF1102R
Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.987
5.6
4.069
173.5
0.001
95.4
0.986
3.0
100
0.981
11.1
4.042
167.0
0.002
81.3
0.983
6.0
200
0.961
21.9
3.926
154.4
0.005
75.8
0.976
12.0
300
0.933
32.1
3.778
142.4
0.006
69.6
0.960
17.7
400
0.899
42.0
3.593
130.6
0.007
65.6
0.945
23.2
500
0.867
51.1
3.412
119.6
0.007
64.4
0.928
29.1
600
0.834
59.9
3.216
109.2
0.007
67.5
0.914
34.1
700
0.805
67.9
3.010
99.0
0.006
78.7
0.901
39.8
800
0.779
75.7
2.804
89.2
0.007
92.7
0.886
45.1
900
0.758
82.1
2.656
80.3
0.007
120.7
0.889
49.7
1000
0.740
89.0
2.509
69.9
0.009
125.5
0.890
55.7
Table 2
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
opt
f
(MHz)
Fmin
(dB)
(ratio)
(deg)
Rn
()
800
2
0.621
61.61
25.85
2000 Apr 11
10
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
PACKAGE OUTLINE
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
2000 Apr 11
REFERENCES
IEC
JEDEC
JEITA
SC-88
11
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
Right to make changes  NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
DEFINITIONS
Product specification  The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
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not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
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DISCLAIMERS
Limited warranty and liability  Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
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any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
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Semiconductors products, and NXP Semiconductors
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associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
2000 Apr 11
12
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
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described herein may be subject to export control
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national authorities.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
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the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Quick reference data  The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products  Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
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applications.
Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
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In the event that customer uses the product for design-in
and use in automotive applications to automotive
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Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
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Semiconductors products are sold subject to the general
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individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license  Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
2000 Apr 11
BF1102; BF1102R
13
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/03/pp14
Date of release: 2000 Apr 11
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