Data Sheet

DISCRETE SEMICONDUCTORS
DATA SHEET
handbook, halfpage
MBD128
BF1204
Dual N-channel dual gate
MOS-FET
Product specification
Supersedes data of 2001 Apr 25
2010 Sep 16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES
BF1204
PINNING - SOT363
 Two low noise gain controlled amplifiers in a single
package
PIN
 Superior cross-modulation performance during AGC
 High forward transfer admittance
 High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
 Gain controlled low noise amplifiers for VHF and UHF
applications with 3 to 9 V supply voltage, such as digital
and analog television tuners and professional
communications equipment.
DESCRIPTION
1
gate 1 (a)
2
gate 2
3
gate 1 (b)
4
drain (b)
5
source
6
drain (a)
handbook, halfpage
6
5
d (a)
4
s
d (b)
AMP
a
DESCRIPTION
The BF1204 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected. Internal bias
circuits enable DC stabilization and a very good
cross-modulation performance during AGC. Integrated
diodes between the gates and source protect against
excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
1
2
3
g1 (a)
AMP
b
g2
g1 (b)
Top view
MBL252
Marking code: L3*
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Per MOS-FET; unless otherwise specified


VDS
drain-source voltage
10
V
ID
drain current (DC)


30
mA
Ptot
total power dissipation
Ts  102 C; note 1


200
mW
yfs
forward transfer admittance
ID = 12 mA; f = 1 MHz
25
30
40
mS
Cig1-s
input capacitance at gate 1
ID = 12 mA; f = 1 MHz

1.7
2.2
pF
Crss
reverse transfer capacitance
f = 1 MHz

15

fF
NF
noise figure
f = 800 MHz

1.1
1.8
dB
Xmod
cross-modulation
input level for k = 1% at 40 dB AGC 100
105

dBV
Tj
operating junction temperature

150
C

Note
1. Ts is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2010 Sep 16
2
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET; unless otherwise specified
VDS
drain-source voltage

ID
drain current (DC)
IG1
gate 1 current
IG2
gate 2 current
Ts  102 C
10
V

30
mA

10
mA

10
mA
Ptot
total power dissipation

200
mW
Tstg
storage temperature
65
+150
C
Tj
operating junction temperature

150
C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-s
PARAMETER
thermal resistance from junction to soldering point
MGS359
250
handbook, halfpage
Ptot
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
2010 Sep 16
3
VALUE
UNIT
240
K/W
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
STATIC CHARACTERISTICS
Tj = 25 C; per MOS-FET; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
UNIT
10

V
V(BR)G1-SS gate-source breakdown voltage
VGS = VDS = 0; IG1-S = 10 mA
6
10
V
V(BR)G2-SS gate-source breakdown voltage
VGS = VDS = 0; IG2-S = 10 mA
6
10
V
V(BR)DSS
drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 A
MAX.
V(F)S-G1
forward source-gate voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate-source threshold voltage
VDS = 5 V; VG2-S = 4 V; ID = 100 A
0.3
1
V
VG2-S(th)
gate-source threshold voltage
VDS = 5 V; VG1-S = 4 V; ID = 100 A
0.3
1.2
V
IDSX
drain-source current
VG2-S = 4 V; VDS = 5 V; RG = 120 k; note 1
8
16
mA
IG1-S
gate cut-off current
VG1-S = 5 V; VG2-S = VDS = 0

50
nA
IG2-S
gate cut-off current
VG2-S = 4 V; VG1-S = VDS = 0

20
nA
Note
1. RG1 connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; per MOS-FET (1); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
Tj = 25 C
25
30
40
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz

1.7
2.2
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz

3.3

pF
Coss
output capacitance
f = 1 MHz

0.85

pF
Crss
reverse transfer capacitance
f = 1 MHz

15

fF
Gtr
power gain
f = 200 MHz; GS = 2 mS; BS = BS(opt);
GL = 0.5 mS; BL = BL(opt); note 1
30
34
38
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt);
GL = 1 mS; BL = BL(opt); note 1
26
30
34
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 21
GL = 1 mS; BL = BL(opt); note 1
25
29
dB
NF
Xmod
noise figure
cross-modulation
f = 10.7 MHz; GS = 20 mS; BS = 0

9
11
dB
f = 400 MHz; YS = YS(opt)

0.9
1.5
dB
f = 800 MHz; YS = YS(opt)

1.1
1.8
dB
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90


dBV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2

92

dBV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
100
105

dBV
Notes
1. For the MOS-FET not in use: VG1-S = 0; VDS = 0.
2. Measured in Fig.19 test circuit.
2010 Sep 16
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
ALL GRAPHS FOR ONE MOS-FET
MCD952
20
handbook, halfpage
VG2-S = 4 V
ID
(mA)
2.5 V
3.5 V
16
VG1-S = 1.5 V
ID
(mA)
2V
3V
MCD953
24
handbook, halfpage
1.4 V
16
12
1.3 V
1.5 V
8
1.2 V
1.1 V
8
1V
4
1V
0.9 V
0
0.4
0
0.8
1.2
0
1.6
2
VG1-S (V)
0
VDS = 5 V.
Tj = 25 C.
2
4
6
8
10
VDS (V)
VG2-S = 4 V.
Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MCD954
100
handbook, halfpage
VG2-S = 4 V
IG1
(μA)
MCD955
40
handbook, halfpage
3.5 V
3.5 V
yfs
(mS)
3V
80
VG2-S = 4 V
30
3V
60
2.5 V
20
2.5 V
40
2V
10
20
2V
1.5 V
1V
0
0.5
0
1
1.5
0
0
2
2.5
VG1-S (V)
4
VDS = 5 V.
Tj = 25 C.
VDS = 5 V.
Tj = 25 C.
Fig.5
Fig.6
Gate 1 current as a function of gate 1
voltage; typical values.
2010 Sep 16
5
8
12
16
20
ID (mA)
Forward transfer admittance as a function
of drain current; typical values.
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD956
20
MCD957
16
handbook, halfpage
handbook, halfpage
ID
(mA)
ID
(mA)
16
12
12
8
8
4
4
0
0
10
0
20
30
0
40
50
IG1 (μA)
1
2
3
4
5
VGG (V)
VDS = 5 V; VG2-S = 4 V.
Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
Fig.7
Fig.8
Drain current as a function of gate 1 current;
typical values.
Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD958
20
handbook, halfpage
RG1 = 68 kΩ
ID
(mA)
16
MCD959
16
handbook, halfpage
ID
(mA)
82 kΩ
VGG = 5 V
4.5 V
12
12
100 kΩ
4V
120 kΩ
3.5 V
150 kΩ
8
3V
8
180 kΩ
220 kΩ
4
4
0
0
0
2
4
6
VGG = VDS (V)
0
2
4
VG2-S (V)
VG2-S = 4 V; Tj = 25 C.
RG1 connected to VGG; see Fig.19.
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
Fig.9
Fig.10 Drain current as a function of gate 2
voltage; typical values.
Drain current as a function of gate 1 (= VGG)
and drain supply voltage; typical values.
2010 Sep 16
6
6
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD960
40
MCD961
0
handbook,
gain halfpage
handbook, halfpage
IG1
(μA)
reduction
(dB)
−10
VGG = 5 V
30
4.5 V
−20
4V
20
3.5 V
−30
3V
10
−40
−50
0
0
2
4
VG2-S (V)
6
0
1
2
3
VAGC (V)
4
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f = 50 MHz; Tamb = 25 C.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of AGC
voltage; see Fig.19.
MCD962
120
MCD963
16
handbook, halfpage
handbook, halfpage
Vunw
(dBμV)
ID
(mA)
110
12
100
8
90
4
80
0
0
10
20
30
40
50
gain reduction (dB)
0
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f= 50 MHz; funw = 60 MHz; Tamb = 25 C.
20
30
40
50
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f = 50 MHz; Tamb = 25 C.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.19.
2010 Sep 16
10
Fig.14 Drain current as a function of gain
reduction; typical values; see Fig.19.
7
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MLD429
102
handbook, halfpage
MLD430
103
handbook, halfpage
ϕrs
(deg)
yrs
Yis
(mS)
(μS)
ϕrs
102
10
bis
−102
yrs
gis
1
10−1
10
−103
−10
10
102
1
10
103
−1
103
102
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD431
102
handbook, halfpage
yfs
(mS)
−102
ϕfs
(deg)
yfs
MLD432
10
handbook, halfpage
Yos
(mS)
bos
1
−10
10
ϕfs
1
10
102
10−1
f (MHz)
−1
103
10−2
10
gos
102
103
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2010 Sep 16
8
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
VAGC
handbook, full pagewidth
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
L1
C2
RGEN
50 Ω
R2
50 Ω
DUT
≈ 2.2 μH
RL
50 Ω
C4
4.7 nF
RG1
4.7 nF
VGG
VI
VDS
MGS315
Fig.19 Cross-modulation test set-up (for one MOS-FET).
Scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C.
f
(MHz)
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.991
3.29
2.95
175.78
0.00060
85.25
0.995
1.44
100
0.987
7.12
2.90
171.61
0.00119
84.74
0.994
2.90
200
0.981
14.21
2.86
163.45
0.00234
80.85
0.992
5.70
300
0.969
21.22
2.83
155.11
0.00339
75.77
0.989
8.50
400
0.958
28.14
2.79
147.37
0.00429
72.23
0.987
11.25
500
0.939
35.01
2.74
139.04
0.00508
68.24
0.983
13.96
600
0.921
41.75
2.68
131.35
0.00565
64.97
0.981
16.67
700
0.898
48.51
2.62
123.38
0.00611
61.90
0.976
19.36
800
0.874
54.96
2.55
115.74
0.00646
57.77
0.973
22.04
900
0.847
61.62
2.49
107.84
0.00662
55.04
0.969
24.80
1000
0.817
67.84
2.41
100.24
0.00670
52.16
0.966
27.45
2010 Sep 16
9
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
PACKAGE OUTLINE
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
2010 Sep 16
REFERENCES
IEC
JEDEC
JEITA
SC-88
10
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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2010 Sep 16
11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
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extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
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2010 Sep 16
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without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/03/pp13
Date of release: 2010 Sep 16
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