Data Sheet

DISCRETE SEMICONDUCTORS
DATA SHEET
handbook, halfpage
MBD128
BF1205
Dual N-channel dual gate
MOS-FET
Product specification
2003 Sep 30
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES
BF1205
PINNING - SOT363
 Two low noise gain controlled amplifiers in a single
package. One with a fully integrated bias and one with a
partly integrated bias
PIN
DESCRIPTION
1
gate 1 (a)
 Internal switch reduces the number of external
components
2
gate 2
3
gate 1 (b)
 Superior cross-modulation performance during AGC
4
drain (b)
 High forward transfer admittance
5
source
 High forward transfer admittance to input capacitance
ratio.
6
drain (a)
APPLICATIONS
d (a)
handbook, halfpage
 Gain controlled low noise amplifiers for VHF and UHF
applications with 5 V supply voltage, such as digital and
analog television tuners and professional
communications equipment.
6
5
s
d (b)
4
AMP
a
AMP
b
DESCRIPTION
The BF1205 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads
and an integrated switch. The integrated switch is
operated by the gate 1 bias of amplifier b. The source and
substrate are interconnected. Internal bias circuits enable
DC stabilization and a very good cross-modulation
performance during AGC. Integrated diodes between the
gates and source protect against excessive input voltage
surges. The transistor is encapsulated in SOT363
micro-miniature plastic package.
1
2
3
Top view
g1 (a)
g2
g1 (b)
MGX429
Marking code: L4-.
Fig.1 Simplified outline and symbol.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
BF1205
2003 Sep 30

DESCRIPTION
Plastic surface mounted package; 6 leads
2
VERSION
SOT363
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per MOS-FET; unless otherwise specified


VDS
drain-source voltage
10
V
ID
drain current (DC)

Ptot
total power dissipation
Ts  102 C; temperature at the
soldering point of the source lead


30
mA

200
mW
yfs
forward transfer admittance
ID = 12 mA
26
31
40
mS
Cig1-ss
input capacitance at gate 1
amp. a: f = 1 MHz
amp. b: f = 1 MHz

1.8
2.3
pF

2.0
2.5
pF
Crss
reverse transfer capacitance
f = 1 MHz

20

fF
NF
noise figure
amp. a: f = 800 MHz

1.2
1.9
dB
amp. b: f = 800 MHz

1.4
2.1
dB
Xmod
cross-modulation
amp. a: input level for k = 1% at
40 dB AGC
98
102

dBV
amp. b: input level for k = 1% at
40 dB AGC
100
105

dBV


150
C
Tj
junction temperature
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET; unless otherwise specified
VDS
drain-source voltage

10
V
ID
drain current (DC)

30
mA
IG1
gate 1 current

10
mA
IG2
gate 2 current
Ptot
total power dissipation
Tstg
Tj

10
mA

200
mW
storage temperature
65
+150
C
junction temperature

150
C
Ts  102 C; note
Note
1. Ts is the temperature at the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-s
2003 Sep 30
PARAMETER
thermal resistance from junction to soldering point
3
VALUE
UNIT
240
K/W
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGS359
250
Ptot
handbook, halfpage
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
STATIC CHARACTERISTICS
Tj = 25 C; per MOS-FET; unless otherwise specified.
SYMBOL
V(BR)DSS
PARAMETER
drain-source breakdown voltage
CONDITIONS
MIN.
MAX.
UNIT
amp. a: VG1-S = VG2-S = 0 V; ID = 10 A 10

V
amp. b: VG1-S = VG2-S = 0 V; ID = 10 A 7

V
V(BR)G1-SS
gate-source breakdown voltage
VGS = VDS = 0 V; IG1-S = 10 mA
6
10
V
V(BR)G2-SS
gate-source breakdown voltage
VGS = VDS = 0 V; IG2-S = 10 mA
6
10
V
V(F)S-G1
forward source-gate voltage
VG2-S = VDS = 0 V; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate voltage
VG1-S = VDS = 0 V; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate-source threshold voltage
VDS = 5 V; VG2-S = 4 V; ID = 100 A
0.3
1
V
VG2-S(th)
gate-source threshold voltage
VDS = 5 V; VG1-S = 5 V; ID = 100 A
0.4
1.0
V
IDSX
drain-source current
amp. a: VG2-S = 4 V; VDS = 5 V;
RG1 = 150 k; note 1
8
16
mA
amp. b: VG2-S = 4 V; VDS = 5 V;
RG1 = 150 k; note 2
8
16
mA
amp. a: VG1-S = 5 V; VG2-S = VDS = 0 V

50
nA
amp. b: VG1-S = 5 V; VG2-S = VDS = 0 V

50
nA
VG2-S = 4 V; VG1-S = VDS = 0 V

20
nA
IG1-S
gate cut-off current
IG2-S
gate cut-off current
Note
1. RG1 connects gate 1 (b) to VGG = 0 V (see Fig.4).
2. RG1 connects gate 1 (b) to VGG = 5 V (see Fig.4).
2003 Sep 30
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX430
16
handbook, halfpage
ID
(mA)
(1)
handbook, halfpage
12
g1 (a)
(2)
d (a)
g2
s
(3)
8
g1 (b)
d (b)
R G1
4
VGG
(4)
MGX431
(5)
(6)
0
0
1
(1) ID (b); RG1 = 120 k.
(2) ID (b); RG1 = 150 k.
(3) ID (b); RG1 = 180 k.
2
3
4
VGG (V)
5
(4) ID (a); RG1 = 180 k.
(5) ID (a); RG1 = 150 k.
(6) ID (a); RG1 = 120 k.
VGG = 5 V: amplifier a is OFF; amplifier b is ON.
VGG = 0 V: amplifier a is ON; amplifier b is OFF.
Fig.3 Drain currents of MOS-FET a and b as
functions of VGG (see Fig.4).
2003 Sep 30
Fig.4 Functional diagram
5
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
DYNAMIC CHARACTERISTICS AMPLIFIER a
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; note 1
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
Tj = 25 C
26
31
40
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz

1.8
2.3
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz

3.3

pF
Coss
output capacitance
f = 1 MHz

0.75

pF
Crss
reverse transfer capacitance
f = 1 MHz

20

fF
Gtr
power gain
f = 200 MHz; GS = 2 mS; BS = BS(opt);
GL = 0.5 mS; BL = BL(opt)
31
35
39
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt);
GL = 1 mS; BL = BL(opt)
27
31
35
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 22
GL = 1 mS; BL = BL(opt)
26
30
dB
NF
Xmod
noise figure
cross-modulation
f = 10.7 MHz; GS = 20 mS; BS = 0

4

dB
f = 400 MHz; YS = YS(opt)

1.1
1.7
dB
f = 800 MHz; YS = YS(opt)

1.2
1.9
dB
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90


dBV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2

90

dBV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
98
102

dBV
Notes
1. For the MOS-FET not in use: VG1-S (b) = 0 V; VDS (b) = 0 V.
2. Measured in Fig.13 test circuit.
2003 Sep 30
6
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
GRAPHS FOR AMPLIFIER a
MGX432
20
MGX433
24
handbook, halfpage
(3)
ID
(mA)
(4)
handbook, halfpage
(5)
(2)
ID
(mA)
(1)
15
(1)
(2)
16
(3)
(6)
10
(4)
(5)
8
5
(6)
(7)
(7)
0
0
0.4
(1) VG2-S = 4 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
0.8
1.2
0
2
1.6
VG1-S (V)
0
2
(1) VG1-S (a) = 1.4 V.
(2) VG1-S (a) = 1.3 V.
(3) VG1-S (a) = 1.2 V.
(4) VG1-S (a) = 1.1 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
4
6
8
(5) VG1-S (a) = 1 V.
(6) VG1-S (a) = 0.9 V.
(7) VG1-S (a) = 0.8 V.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
VG2-S = 4 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
Fig.5
Fig.6
Transfer characteristics; typical values;
amplifier a.
2003 Sep 30
7
10
VDS (V)
Output characteristics; typical values;
amplifier a.
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX434
40
MGX435
12
handbook, halfpage
handbook, halfpage
yfs
(mS)
(1)
(2)
30
ID (a)
(mA)
(3)
(4)
8
20
4
10
(5)
0
0
0
4
(1) VG2-S = 4 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
8
12
16
20
ID (mA)
0
10
20
30
40
ID (b) (μA)
(4) VG2-S = 2.5 V.
(5) VG2-S = 2 V.
VDS (a) = 5 V; VG2-S = 4 V; VDS (b) = 5 V; VG1-S (b) = 0 V; Tj = 25 C.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
Fig.8
Fig.7
Forward transfer admittance as a function
of drain current; typical values; amplifier a.
2003 Sep 30
8
Drain current as a function of internal G1
current (current in pin drain (b) if MOS-FET
(b) is switched off); typical values; amplifier a.
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX436
12
(1)
handbook,
I halfpage
D
(mA)
10
MGX437
120
handbook, halfpage
(2)
Vunw
(dBμV)
(3)
(4)
110
8
(5)
6
100
4
90
2
0
0
2
(1) VDS (b) = 5 V.
(2) VDS (b) = 4.5 V.
(3) VDS (b) = 4 V.
4
80
6
VGG = VDS (V)
0
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f w = 50 MHz;
f unw = 60 MHz; Tamb = 25 C; see Fig.13.
Drain current as a function of gate 2 and
drain supply voltage; typical values;
amplifier a.
2003 Sep 30
40
60
gain reduction (dB)
(4) VDS (b) = 3.5 V.
(5) VDS (b) = 3 V.
VDS (a) = 5 V; VG1-S (b) = 0 V; Gate 1 (a) = open; Tj = 25 C.
Fig.9
20
Fig.10 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier a.
9
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX438
0
MGX439
16
handbook, halfpage
handbook, halfpage
ID
(mA)
gain
reduction
(dB)
12
20
8
40
4
60
0
1
2
3
0
4
0
20
VAGC (V)
40
60
gain reduction (dB)
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; see Fig.13.
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; Tamb = 25 C;
see Fig.13.
Fig.11 Gain reduction as a function of AGC
voltage; typical values; amplifier a.
Fig.12 Drain current as a function of gain
reduction; typical values; amplifier a.
VDS(a)
5V
handbook, full pagewidth
VAGC
4.7 nF
L1
2.2 μH
10 kΩ
4.7 nF
RGEN
50 Ω
Vi
50 Ω
g1 (a)
4.7 nF
4.7 nF
g2
d (a)
BF1205
g1 (b)
4.7 nF
RL
50 Ω
s
d (b)
L2
2.2 μH
50 Ω
R G1
150 kΩ
4.7 nF
VGG
0V
VDS(b)
5V
MGX440
Fig.13 Cross-modulation test set-up for amplifier a.
2003 Sep 30
10
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX441
102
handbook, halfpage
MGX442
102
handbook, halfpage
yis
(mS)
ϕ fs
(deg)
| yfs |
(mS)
10
−102
| yfs |
b is
1
g is
10−1
10−2
10
102
ϕ fs
1
10
103
f (MHz)
−1
103
f (MHz)
Fig.15 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.14 Input admittance as a function of frequency;
typical values; amplifier a.
MGX443
103
handbook, halfpage
102
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
−103
MGX444
10
handbook, halfpage
ϕ rs
(deg)
| yrs|
(μS)
ϕrs
102
102
yos
(mS)
−102
| yrs|
10
1
10
−10
10
−10
f (MHz)
1
bos
10−1
gos
10−2
10
−1
103
102
f (MHz)
103
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.17 Output admittance as a function of
frequency; typical values; amplifier a.
2003 Sep 30
11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
Scattering parameters: amplifier a
VDS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 C
f
(MHz)
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.997
3.70
3.15
175.99
0.00067
86.39
0.992
1.38
100
0.995
7.37
3.15
171.92
0.00132
84.34
0.991
2.83
200
0.988
14.64
3.12
163.99
0.00262
79.71
0.990
5.62
300
0.976
21.85
3.09
156.06
0.00373
75.29
0.988
8.40
400
0.963
28.95
3.04
148.32
0.00471
71.43
0.985
11.15
500
0.944
35.98
2.99
140.52
0.00557
66.89
0.982
13.88
600
0.924
42.90
2.94
132.88
0.00624
63.52
0.978
16.65
700
0.900
49.77
2.87
125.30
0.00669
60.09
0.975
19.35
800
0.874
56.61
2.81
117.79
0.00701
59.58
0.972
22.08
900
0.846
63.18
2.73
110.29
0.00705
52.42
0.968
24.87
1000
0.817
69.84
2.65
102.91
0.00688
49.17
0.965
27.63
Noise data
VDS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 C
GAMMA OPT
f
(MHz)
F MIN
(dB)
Rn
()
(ratio)
(deg)
400
1.1
0.719
16.16
31.18
800
1.2
0.628
32.7
29.74
DYNAMIC CHARACTERISTICS AMPLIFIER b
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
Tj = 25 C
26
31
40
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz

2.0
2.5
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz

3.3

pF
Coss
output capacitance
f = 1 MHz

0.85

pF
Crss
reverse transfer capacitance
f = 1 MHz

20

fF
Gtr
power gain
f = 200 MHz; GS = 2 mS; BS = BS(opt);
GL = 0.5 mS; BL = BL(opt); note 1
30
34
38
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt);
GL = 1 mS; BL = BL(opt); note 1
27
31
35
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 22
GL = 1 mS; BL = BL(opt); note 1
26
30
dB
NF
noise figure
2003 Sep 30
f = 10.7 MHz; GS = 20 mS; BS = 0

4

dB
f = 400 MHz; YS = YS(opt)

1.3
1.9
dB
f = 800 MHz; YS = YS(opt)

1.4
2.1
dB
12
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
SYMBOL
PARAMETER
CONDITIONS
cross-modulation
Xmod
BF1205
MIN.
TYP.
MAX.
UNIT
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90


dBV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2

92

dBV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
100
105

dBV
Notes
1. For the MOS-FET not in use: VG1-S (a) = 0; VDS (a) = 0.
2. Measured in test circuit Fig.30.
GRAPHS FOR AMPLIFIER b
MGX445
20
handbook, halfpage
(3)
ID
(mA)
(2)
MGX446
24
(4)
handbook, halfpage
(5)
ID
(mA)
(1)
15
(1)
(2)
16
(3)
(6)
10
(4)
(5)
8
5
(6)
(7)
(7)
0
0
(1)
(2)
(3)
(4)
0.4
VG2-S = 4 V.
VG2-S = 3.5 V.
VG2-S = 3 V.
VG2-S = 2.5 V.
0.8
1.2
0
2
1.6
VG1-S (V)
0
(5) VG2-S = 2 V.
2
(1) VG1-S (b) = 1.4 V.
(2) VG1-S (b) = 1.3 V.
(3) VG1-S (b) = 1.2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
4
6
8
10
VDS (V)
(5) VG1-S (b) = 1 V.
(6) VG1-S (b) = 0.9 V.
(7) VG1-S (b) = 0.8 V.
(4) VG1-S (b) = 1.1 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
Fig.18 Transfer characteristics; typical values;
amplifier b.
Fig.19 Output characteristics; typical values;
amplifier b.
2003 Sep 30
13
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX447
60
handbook, halfpage
(2)
(1)
IG1
MGX448
40
handbook, halfpage
(3)
yfs
(mS)
(4)
(μA)
(1)
(2)
30
(3)
(5)
40
(4)
20
20
(6)
10
(5)
(7)
0
0
0
0.4
(1) VG2-S = 4 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
0.8
1.2
1.6
VG1-S (V)
0
2
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
4
8
12
16
20
ID (mA)
(4) VG2-S = 2.5 V.
(1) VG2-S = 4 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
Fig.20 Gate 1 current as a function of gate 1
voltage; typical values; amplifier b.
Fig.21 Forward transfer admittance as a function
of drain current; typical values; amplifier b.
2003 Sep 30
14
(4) VG2-S = 2.5 V.
(5) VG2-S = 2 V.
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX449
20
MGX450
16
handbook, halfpage
handbook, halfpage
ID
(mA)
ID
(mA)
16
12
12
8
8
4
4
0
0
10
20
30
0
40
50
IG1 (μA)
0
1
2
3
4
5
VGG (V)
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
Tj = 25 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.22 Drain current as a function of gate 1 current;
typical values; amplifier b.
Fig.23 Drain current as a function of gate 1 supply
voltage (VGG); typical values; amplifier b.
2003 Sep 30
15
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX451
20
MGX452
16
handbook, halfpage
(1)
handbook, halfpage
(mA)
(2)
ID
(mA)
ID
16
(1)
(3)
(2)
12
12
(4)
(3)
(5)
(4)
(5)
(6)
8
(7)
(8)
8
4
4
0
0
(1)
(2)
(3)
(4)
RG1 (b) = 68 k.
RG1 (b) = 82 k.
RG1 (b) = 100 k.
RG1 (b) = 120 k.
2
4
0
6
VGG = VDS (V)
0
4
6
VG2-S (V)
(5) RG1 (b) = 150 k.
(6) RG1 (b) = 180 k.
(7) RG1 (b) = 220 k.
(8) RG1 (b) = 270 k.
(1) VGG = 5.0 V.
(2) VGG = 4.5 V.
(3) VGG = 4.0 V.
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C;
RG1 (b) = 150 k (connected to VGG); see Fig.4.
(4) VGG = 3.5 V.
(5) VGG = 3.0 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C;
RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.24 Drain current as a function of gate 1 (VGG)
and drain supply voltage; typical values;
amplifier b.
2003 Sep 30
2
Fig.25 Drain current as a function of gate 2
voltage; typical values; amplifier b.
16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX453
30
MGX454
120
handbook, halfpage
handbook, halfpage
IG1
Vunw
(dBμV)
(1)
(μA)
110
(2)
20
(3)
(4)
100
(5)
10
90
80
0
0
(1) VGG = 5.0 V.
(2) VGG = 4.5 V.
(3) VGG = 4.0 V.
2
4
VG2-S (V)
0
6
(4) VGG = 3.5 V.
(5) VGG = 3.0 V.
40
60
gain reduction (dB)
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 k (connected to VGG); fw = 50 MHz;
funw = 60 MHz; Tamb = 25 C; see Fig.30.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C;
RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.27 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier b.
Fig.26 Gate 1 current as a function of gate 2
voltage; typical values; amplifier b.
2003 Sep 30
20
17
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX455
0
MGX456
16
handbook, halfpage
handbook, halfpage
ID
(mA)
gain
reduction
(dB)
12
20
8
40
4
60
0
0
1
2
3
4
0
VAGC (V)
20
40
60
gain reduction (dB)
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 k (connected to VGG); f = 50 MHz;
Tamb = 25 C; see Fig.30.
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 k (connected to VGG); f = 50 MHz;
Tamb = 25 C; see Fig.30.
Fig.28 Typical gain reduction as a function of AGC
voltage; amplifier b.
Fig.29 Drain current as a function of gain
reduction; typical values; amplifier b.
2003 Sep 30
18
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
VDS(a)
5V
handbook, full pagewidth
VAGC
4.7 nF
L1
2.2 μH
10 kΩ
4.7 nF
50 Ω
4.7 nF
4.7 nF
RGEN
50 Ω
g1 (a)
d (a)
g2
BF1205
g1 (b)
s
d (b)
R G1
150 kΩ
Vi
RL
50 Ω
L2
2.2 μH
50 Ω
4.7 nF
VGG
5V
VDS(b)
5V
MDB813
Fig.30 Cross-modulation test set-up for amplifier b.
MGX457
102
handbook, halfpage
MGX458
102
handbook, halfpage
yis
(mS)
ϕ fs
(deg)
| yfs |
(mS)
| yfs |
10
−10
10
b is
1
10−1
10
ϕ fs
g is
102
f (MHz)
1
10
103
102
f (MHz)
−1
103
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b)= 12 mA.
Fig.32 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
Fig.31 Input admittance as a function of frequency;
typical values; amplifier b.
2003 Sep 30
−102
19
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
MGX459
103
handbook, halfpage
−103
(μS)
ϕrs
102
102
yos
(mS)
−102
| yrs|
10
gos
10−1
10−2
10
−1
103
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
102
f (MHz)
103
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
Fig.33 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
2003 Sep 30
bos
1
−10
f (MHz)
MGX460
10
handbook, halfpage
ϕ rs
(deg)
| yrs|
1
10
BF1205
Fig.34 Output admittance as a function of
frequency; typical values; amplifier b.
20
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
Scattering parameters: amplifier b
VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 C
f
(MHz)
s21
s11
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.987
3.76
3.12
175.87
0.00071
85.43
0.991
1.56
100
0.985
7.38
3.11
171.77
0.00136
86.06
0.989
3.11
200
0.978
14.63
3.09
163.72
0.00272
84.25
0.988
6.16
300
0.968
21.82
3.06
155.67
0.00396
82.63
0.986
9.17
400
0.956
28.92
3.01
147.79
0.00509
81.35
0.983
12.17
500
0.941
35.99
2.95
139.86
0.00616
79.46
0.973
15.16
600
0.924
42.93
2.89
132.06
0.00710
78.57
0.975
18.15
700
0.905
49.89
2.83
124.31
0.00791
77.88
0.972
21.07
800
0.884
56.57
2.75
116.69
0.00848
76.72
0.968
24.08
900
0.861
63.36
2.67
108.97
0.00900
76.55
0.964
27.03
1000
0.837
70.05
2.59
101.39
0.00941
76.67
0.959
30.02
Noise data
VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 C
f
(MHz)
F MIN
(dB)
F MIN
(dB)
Rn
()
(ratio)
(deg)
400
1.3
0.662
16.76
31.55
800
1.4
0.578
33.97
30.53
2003 Sep 30
21
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
PACKAGE OUTLINE
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
2003 Sep 30
REFERENCES
IEC
JEDEC
JEITA
SC-88
22
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
Right to make changes  NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
DEFINITIONS
Product specification  The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
Suitability for use  NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
DISCLAIMERS
Limited warranty and liability  Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications  Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
2003 Sep 30
23
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
Export control  This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Quick reference data  The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products  Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
Terms and conditions of commercial sale  NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license  Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
2003 Sep 30
24
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/01/pp25
Date of release: 2003 Sep 30
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