Data Sheet

BF1207
Dual N-channel dual gate MOSFET
Rev. 2 — 7 September 2011
Product data sheet
1. Product profile
1.1 General description
The BF1207 is a combination of two dual gate MOSFET amplifiers with shared source
and gate2 leads and an integrated switch.
The source and substrate are interconnected. Internal bias circuits enable Direct Current
(DC) stabilization and a very good cross-modulation performance during Automatic Gain
Control (AGC). Integrated diodes between the gates and source protect against excessive
input voltage surges. The BF1207 has a SOT363 micro-miniature plastic package.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features and benefits
 Two low noise gain controlled amplifiers in a single package. One with a fully
integrated bias and one with partly integrated bias
 Internal switch to save external components
 Superior cross-modulation performance during AGC
 High forward transfer admittance
 High forward transfer admittance to input capacitance ratio
1.3 Applications
 Gain controlled low noise amplifiers for Very High Frequency (VHF) and Ultra High
Frequency (UHF) applications with 5 V supply voltage, such as digital and analog
television tuners and professional communication equipment
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
1.4 Quick reference data
Table 1.
Quick reference data
Per MOSFET unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
-
-
6
V
-
-
30
mA
-
-
180
mW
amplifier A; ID = 18 mA
25
30
40
mS
amplifier B; ID = 14 mA
26
31
41
mS
amplifier A
-
2.2
2.7
pF
amplifier B
-
1.9
2.4
pF
VDS
drain-source voltage
DC
ID
drain current
DC
Ptot
total power dissipation
Tsp  107 C
yfs
forward transfer admittance
f = 1 MHz
Ciss(G1)
input capacitance at gate1
[1]
f = 100 MHz
Crss
reverse transfer capacitance f = 100 MHz
-
20
-
fF
NF
noise figure
amplifier A; f = 400 MHz
-
1.3
-
dB
amplifier B; f = 800 MHz
-
1.4
-
dB
amplifier A
100
105
-
dBV
amplifier B
100
103
-
dBV
-
-
150
C
Xmod
input level for k = 1 % at
40 dB AGC
junction temperature
Tj
[1]
cross-modulation
Tsp is the temperature at the soldering point of the source lead.
2. Pinning information
Table 2.
Discrete pinning
Pin
Description
1
drain (AMP A)
2
source
3
drain (AMP B)
4
gate1 (AMP B)
5
gate2
6
gate1 (AMP A)
Simplified outline
6
5
Symbol
AMP B
4
G1B
1
2
3
DB
G2
S
DA
G1A
AMP A
sym108
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
2 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
3. Ordering information
Table 3.
Ordering information
Type number
BF1207
Package
Name
Description
Version
-
plastic surface mounted package; 6 leads
SOT363
4. Marking
Table 4.
Marking
Type number
Marking code[1]
BF1207
M2*
[1]
* = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Per MOSFET
VDS
drain-source voltage
DC
-
6
V
ID
drain current
DC
-
30
mA
IG1
gate1 current
-
10
mA
IG2
gate2 current
-
10
mA
-
180
mW
Ptot
total power dissipation
Tstg
storage temperature
65
+150
C
Tj
junction temperature
-
150
C
[1]
BF1207
Product data sheet
Tsp  107 C
[1]
Tsp is the temperature at the soldering point of the source lead.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
3 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac741
250
Ptot
(mW)
200
150
100
50
0
0
50
100
150
200
Tsp (°C)
Fig 1.
Power derating curve
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-sp)
thermal resistance from junction
to soldering point
Typ
Unit
240
K/W
7. Static characteristics
Table 7.
Static characteristics
Tj = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
amplifier A
6
-
-
V
amplifier B
6
-
-
V
Per MOSFET; unless otherwise specified
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0 V; ID = 10 A
V(BR)G1-SS
gate1-source breakdown voltage
VGS = VDS = 0 V; IG1-S = 10 mA
6
-
10
V
V(BR)G2-SS
gate2-source breakdown voltage
VGS = VDS = 0 V; IG2-S = 10 mA
6
-
10
V
VF(S-G1)
forward source-gate1 voltage
VG2-S = VDS = 0 V; IS-G1 = 10 mA
0.5
-
1.5
V
VF(S-G2)
forward source-gate2 voltage
VG1-S = VDS = 0 V; IS-G2 = 10 mA
0.5
-
1.5
V
VG1-S(th)
gate1-source threshold voltage
VDS = 5 V; VG2-S = 4 V; ID = 100 A
0.3
-
1.0
V
VG2-S(th)
gate2-source threshold voltage
VDS = 5 V; VG1-S = 5 V; ID = 100 A
0.4
-
1.0
V
IDSX
drain-source current
VG2-S = 4 V; VDS = 5 V; RG1 = 68 k
BF1207
Product data sheet
amplifier A
[1]
13
-
23
mA
amplifier B
[2]
9
-
19
mA
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
4 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
Table 7.
Static characteristics …continued
Tj = 25 C.
Symbol
Parameter
Conditions
IG1-S
gate1 cut-off current
VG2-S = VDS(A) = 0 V
gate2 cut-off current
IG2-S
Min
Typ
Max Unit
amplifier A; VG1-S(A) = 5 V; VDS(B) = 0 V
-
-
50
nA
amplifier B; VG1-S(A) = 0 V; ID(B) = 0 A
-
-
50
nA
VG2-S = 4 V; VG1-S = VDS(A) = VDS(B) = 0 V;
-
-
20
nA
[1]
RG1 connects gate1 (A) to VGG = 5 V (see Figure 3).
[2]
RG1 connects gate1 (B) to VGG = 0 V (see Figure 3).
001aac742
20
ID
(mA)
16
(1)
G1B
DB
(2)
12
G2
S
(3)
G1A
8
DA
RG1
(4)
VGG
4
(6)
001aac881
(5)
0
0
1
2
3
4
5
VGG (V)
(1) ID(A); RG1 = 47 k.
VGG = 5 V: amplifier A is on; amplifier B is off.
(2) ID(A); RG1 = 68 k.
VGG = 0 V: amplifier A is off; amplifier B is on.
(3) ID(A); RG1 = 100 k.
(4) ID(B); RG1 = 100 k.
(5) ID(B); RG1 = 68 k.
(6) ID(B); RG1 = 47 k.
VDS(A) = VDS(B) = 5 V; VG2-S = 4 V; Tj = 25 C.
Fig 2.
Drain currents of MOSFET A and B as function
of VGG
BF1207
Product data sheet
Fig 3.
Functional diagram
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
5 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8. Dynamic characteristics
8.1 Dynamic characteristics for amplifier A
Table 8.
Dynamic characteristics for amplifier A
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 18 mA.[1]
Symbol
Parameter
Conditions
Min
yfs
forward transfer admittance
Tj = 25 C
25
30
40
mS
Ciss(G1)
input capacitance at gate1
f = 100 MHz
-
2.2
2.7
pF
Ciss(G2)
input capacitance at gate2
f = 1 MHz
-
3.5
-
pF
Coss
output capacitance
f = 100 MHz
-
0.9
-
pF
Crss
reverse transfer capacitance
f = 100 MHz
-
20
-
fF
Gtr
power gain
BS = BS(opt); BL = BL(opt)
f = 200 MHz; GS = 2 mS; GL = 0.5 mS
30
34
38
dB
f = 400 MHz; GS = 2 mS; GL = 1 mS
26
30
34
dB
f = 800 MHz; GS = 3.3 mS; GL = 1 mS
NF
noise figure
cross-modulation
21
25
29
dB
3.0
-
dB
f = 400 MHz; YS = YS(opt)
-
1.3
-
dB
-
1.4
-
dB
at 0 dB AGC
90
-
-
dBV
at 10 dB AGC
-
90
-
dBV
input level for k = 1 %; fw = 50 MHz;
funw = 60 MHz
[2]
at 20 dB AGC
-
99
-
dBV
at 40 dB AGC
100
105
-
dBV
For the MOSFET not in use: VG1-S(B) = 0 V; VDS(B) = 0 V.
[2]
Measured in Figure 29 test circuit.
Product data sheet
Unit
-
[1]
BF1207
Max
f = 11 MHz; GS = 20 mS; BS = 0 S
f = 800 MHz; YS = YS(opt)
Xmod
Typ
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
6 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8.1.1 Graphs for amplifier A
001aac882
35
ID
(mA)
30
(1)
(2)
001aaa883
32
(1)
ID
(mA)
(2)
(3)
24
25
(3)
(4)
(4)
20
(5)
16
(5)
(6)
15
(7)
10
(8)
(6)
8
(9)
5
(7)
0
0
0.4
0.8
1.2
0
1.6
2.0
VG1-S (V)
0
2
6
VDS (V)
(1) VG2-S = 4 V.
(1) VG1-S(A) = 1.9 V.
(2) VG2-S = 3.5 V.
(2) VG1-S(A) = 1.8 V.
(3) VG2-S = 3 V.
(3) VG1-S(A) = 1.7 V.
(4) VG2-S = 2.5 V.
(4) VG1-S(A) = 1.6 V.
(5) VG2-S = 2 V.
(5) VG1-S(A) = 1.5 V.
(6) VG2-S = 1.5 V.
(6) VG1-S(A) = 1.4 V.
(7) VG2-S = 1 V.
(7) VG1-S(A) = 1.3 V.
VDS(A) = 5 V; Tj = 25 C.
4
(8) VG1-S(A) = 1.2 V.
(9) VG1-S(A) = 1.1 V.
VDS(A) = 5 V; VG2-S = 4 V; Tj = 25 C.
Fig 4.
Amplifier A: transfer characteristics; typical
values
BF1207
Product data sheet
Fig 5.
Amplifier A: output characteristics; typical
values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
7 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac884
40
001aac885
(1)
25
ID
(mA)
yfs
(mS)
(1)
(2)
20
30
(3)
(2)
(4)
15
(5)
20
(6)
(3)
(7)
10
10
(4)
5
(5)
(6)
(7)
0
0
8
0
16
24
32
0
2
(1) VG2-S = 4 V.
(1) RG1(A) = 39 k.
(2) VG2-S = 3.5 V.
(2) RG1(A) = 47 k
(3) VG2-S = 3 V.
(3) RG1(A) = 68 k.
(4) VG2-S = 2.5 V.
(4) RG1(A) = 82 k.
(5) VG2-S = 2 V.
(5) RG1(A) = 100 k
(6) VG2-S = 1.5 V.
(6) RG1(A) = 120 k.
(7) VG2-S = 1 V.
(7) RG1(A) = 150 k.
VDS(A) = 5 V; Tj = 25 C.
Fig 6.
4
6
VGG = VDS (V)
ID (mA)
VG2-S = 4 V; Tj = 25 C.
Amplifier A: forward transfer admittance as a
function of drain current; typical values
Fig 7.
Amplifier A: drain current as a function of VDS
and VGG; typical values
001aac886
20
ID
(mA)
16
12
8
4
0
0
1
2
3
4
5
Vsupply (V)
VG2-S = 4 V, Tj = 25 C, RG1(B) = 68 k (connected to ground); see Figure 3.
Fig 8.
Amplifier A: drain current of amplifier A as a function of supply voltage of A and B amplifier; typical
values
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
8 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac887
120
001aac888
0
gain
reduction
(dB)
10
Vunw
(dBμV)
110
20
100
30
90
40
80
50
0
10
20
30
40
50
gain reduction (dB)
0
2
3
4
VAGC (V)
VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; fw = 50 MHz;
funw = 60 MHz; Tamb = 25 C; see Figure 29.
Fig 9.
1
VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; see
Figure 29.
Amplifier A: unwanted voltage for 1 %
cross-modulation as a function of gain
reduction; typical values
Fig 10. Amplifier A: gain reduction as a function of
AGC voltage; typical values
001aac889
32
ID
(mA)
24
16
8
0
0
10
20
30
40
50
gain reduction (dB)
VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; Tamb = 25 C; see Figure 29.
Fig 11. Amplifier A: drain current as a function of gain reduction; typical values
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
9 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac890
102
001aac891
102
−102
bis, gis
(mS)
ϕfs
(deg)
|yfs|
|yfs|
(mS)
10
bis
1
−10
10
ϕfs
gis
10−1
10−2
10
102
1
103
10
−1
103
102
f (MHz)
f (MHz)
VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V;
ID(A) = 18 mA.
Fig 12. Amplifier A: input admittance as a function of
frequency; typical values
001aac892
103
−103
ϕrs
(deg)
|yrs|
(μS)
ϕrs
102
−102
VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V;
ID(A) = 18 mA.
Fig 13. Amplifier A: forward transfer admittance and
phase as a function of frequency; typical
values
001aac893
10
bos, gos
(mS)
bos
1
|yrs|
10
1
10
102
103
−10
10−1
−1
10−2
gos
10
VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V;
ID(A) = 18 mA.
Fig 14. Amplifier A: reverse transfer admittance and
phase as a function of frequency: typical
values
BF1207
Product data sheet
102
103
f (MHz)
f (MHz)
VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V;
ID(A) = 18 mA.
Fig 15. Amplifier A: output admittance as a function of
frequency; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
10 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8.1.2 Scattering parameters for amplifier A
Table 9.
Scattering parameters for amplifier A
VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 18 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 C; typical values.
f
s11
(MHz) Magnitude Angle
(ratio)
(deg)
BF1207
Product data sheet
s21
s12
s22
Magnitude
(ratio)
Angle
(deg)
Magnitude Angle
(ratio)
(deg)
Magnitude Angle
(ratio)
(deg)
50
0.987
4.169
2.87
175.5
0.0008
83.82
0.992
1.42
100
0.983
8.109
2.95
171.14 0.0015
82.08
0.992
2.86
200
0.976
15.97
2.93
162.44 0.0028
77.50
0.990
5.66
300
0.966
23.844 2.89
153.77 0.0041
73.45
0.989
8.49
400
0.952
31.575 2.84
145.23 0.0053
69.42
0.986
11.28
500
0.935
35.225 2.78
136.82 0.0063
65.72
0.984
14.03
600
0.917
46.678 2.72
128.50 0.0072
61.48
0.981
16.80
700
0.898
54.094 2.65
120.44 0.0079
58.05
0.977
19.55
800
0.876
61.205 2.57
112.33 0.0084
52.74
0.974
22.32
900
0.852
68.299 2.49
104.32 0.0089
48.61
0.970
25.10
1000
0.826
75.321 2.41
96.42
43.86
0.967
27.88
0.0091
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
11 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8.2 Dynamic characteristics for amplifier B
Table 10. Dynamic characteristics for amplifier B
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 14 mA.[1]
Symbol Parameter
Conditions
Min
Typ
Max Unit
yfs
forward transfer admittance
Tj = 25 C
26
31
41
mS
Ciss(G1)
input capacitance at gate1
f = 100 MHz
-
1.8
2.3
pF
Ciss(G2)
input capacitance at gate2
f = 1 MHz
-
3.5
-
pF
Coss
output capacitance
f = 100 MHz
-
0.8
-
pF
Crss
reverse transfer capacitance f = 100 MHz
-
20
-
fF
Gtr
power gain
f = 200 MHz; GS = 2 mS; GL = 0.5 mS
30
34
38
dB
f = 400 MHz; GS = 2 mS; GL = 1 mS
27
31
35
dB
f = 800 MHz; GS = 3.3 mS; GL = 1 mS
23
27
31
dB
f = 11 MHz; GS = 20 mS; BS = 0 S
-
5
-
dB
f = 400 MHz; YS = YS(opt)
-
1.3
-
dB
-
1.4
-
dB
NF
noise figure
BS = BS(opt); BL = BL(opt)
f = 800 MHz; YS = YS(opt)
Xmod
cross-modulation
input level for k = 1 %; fw = 50 MHz; funw = 60 MHz
at 0 dB AGC
90
-
-
dBV
at 10 dB AGC
-
88
-
dBV
at 20 dB AGC
-
94
-
dBV
at 40 dB AGC
100
103
-
dBV
[1]
For the MOSFET not in use: VG1-S(A) = 0 V; VDS(A) = 0 V.
[2]
Measured in Figure 30 test circuit.
BF1207
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
12 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8.2.1 Graphs for amplifier B
001aac894
30
(1)
(2)
ID
(mA)
(3)
(4)
001aac895
32
ID
(mA)
24
(1)
20
(2)
(3)
(5)
16
(4)
(5)
10
(6)
(6)
8
(7)
(7)
0
0
0
0.4
0.8
1.2
1.6
2
VG1-S (V)
0
2
(1) VG1-S(B) = 1.7 V.
(2) VG2-S = 3.5 V.
(2) VG1-S(B) = 1.6 V.
(3) VG2-S = 3 V.
(3) VG1-S(B) = 1.5 V.
(4) VG2-S = 2.5 V.
(4) VG1-S(B) = 1.4 V.
(5) VG2-S = 2 V.
(5) VG1-S(B) = 1.3 V.
(6) VG2-S = 1.5 V.
(6) VG1-S(B) = 1.2 V.
(7) VG2-S = 1 V.
(7) VG1-S(B) = 1.1 V.
VG2-S = 4 V; VG1-S(A) = 0 V; Tj = 25 C.
Fig 16. Amplifier B: transfer characteristics; typical
values
BF1207
Product data sheet
6
VDS (V)
(1) VG2-S = 4 V.
VDS(B) = 5 V; VG1-S(A) = 0 V; Tj = 25 C.
4
Fig 17. Amplifier B: output characteristics; typical
values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
13 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac896
40
001aac897
20
ID
(mA)
yfs
(mS)
(1)
16
30
(1)
(2)
(2)
12
(3)
(4)
20
(5)
8
(3)
10
4
(4)
(5)
(7)
0
0
(6)
0
8
16
24
32
0
1
2
3
4
5
VG2-S (V)
ID (mA)
(1) VG2-S = 4 V.
(1) VDS = 5 V.
(2) VG2-S = 3.5 V.
(2) VDS = 4.5 V.
(3) VG2-S = 3 V.
(3) VDS = 4 V.
(4) VG2-S = 2.5 V.
(4) VDS = 3.5 V.
(5) VG2-S = 2 V.
(5) VDS = 3 V.
VG1-S(A) = 0 V; Tj = 25 C.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
VDS(B) = 5 V; VG1-S(A) = 0 V; Tj = 25 C.
Fig 18. Amplifier B: forward transfer admittance as a
function of drain current; typical values
001aac898
20
ID(A)
(mA)
16
Fig 19. Amplifier B: drain current as function of gate2
voltage; typical values
001aac899
16
ID
(mA)
12
12
8
8
4
4
0
0
2
4
6
0
−40
−30
VDS (V)
VDS(B) = 5 V; VG1-S(A) = 0 V; Tj = 25 C.
Product data sheet
−10
0
IG1 (μA)
VDS(B) = 5 V; VG2-S = 4 V; VG1-S(A) = 0 V; Tj = 25 C.
Fig 20. Amplifier B: drain current as a function of
drain source voltage; typical values
BF1207
−20
Fig 21. Amplifier B: drain current as a function of
gate1 current; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
14 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac900
120
001aac901
0
gain
reduction
(dB)
10
Vunw
(dBμV)
110
20
100
30
90
40
80
50
0
20
40
60
gain reduction (dB)
0
1
2
3
4
VAGC (V)
VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V;
RG1(B) = 150 k (connected to VGG); fw = 50 MHz;
funw = 60 MHz; Tamb = 25 C; see Figure 30.
Fig 22. Amplifier B: unwanted voltage for 1 %
cross-modulation as a function of gain
reduction; typical values
VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V;
RG1(B) = 150 k (connected to VGG); f = 50 MHz;
Tamb = 25 C; see Figure 30.
Fig 23. Amplifier B: typical gain reduction as a
function of AGC voltage; typical values
001aac902
20
ID
(mA)
16
12
8
4
0
0
20
40
60
gain reduction (dB)
VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1(B) = 150 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Figure 30.
Fig 24. Amplifier B: drain current as a function of gain reduction; typical values
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
15 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
001aac903
102
001aac904
102
−102
bis, gis
(mS)
|yfs|
|yfs|
(mS)
10
ϕfs
(deg)
bis
1
−10
10
ϕfs
gis
10−1
10−2
10
102
1
103
10
−1
103
102
f (MHz)
f (MHz)
VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B)
= 14 mA.
Fig 25. Amplifier B: input admittance as a function of
frequency; typical values
001aac905
103
−103
ϕrs
(deg)
|yrs|
(μS)
ϕrs
102
−102
VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V;
ID(B) = 14 mA.
Fig 26. Amplifier B: forward transfer admittance and
phase as a function of frequency; typical
values
001aac906
10
bos, gos
(mS)
bos
1
|yrs|
gos
10
1
10
102
103
−10
10−1
−1
10−2
10
VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V;
ID(B) = 14 mA.
Fig 27. Amplifier B: reverse transfer admittance and
phase as a function of frequency; typical
values
BF1207
Product data sheet
102
103
f (MHz)
f (MHz)
VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V;
ID(B) = 14 mA.
Fig 28. Amplifier B: output admittance as a function of
frequency; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
16 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
8.2.2 Scattering parameters for amplifier B
Table 11. Scattering parameters for amplifier B
VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 14 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 C; typical values.
BF1207
Product data sheet
f
(MHz)
s11
s21
Magnitude
(ratio)
Angle
(deg)
50
0.993
3.018 3.07
100
0.992
200
300
Magnitude
(ratio)
s12
Angle
(deg)
Magnitude
(ratio)
s22
Angle
(deg)
Magnitude
(ratio)
Angle
(deg)
176.04 0.0004
95.97
0.991
1.39
6.186 3.07
172.05 0.0011
90.33
0.990
2.79
0.987
12.43 3.09
164.13 0.0024
85.03
0.988
5.49
0.979
18.60 3.02
156.28 0.0036
82.94
0.986
8.21
400
0.969
24.62 2.99
148.48 0.0046
81.97
0.983
10.91
500
0.957
30.72 2.95
140.69 0.0056
81.03
0.980
13.63
600
0.943
36.71 2.90
132.87 0.0065
79.77
0.977
16.40
700
0.927
42.77 2.86
125.21 0.0074
79.04
0.973
19.13
800
0.907
48.91 2.79
117.22 0.0082
79.42
0.969
21.93
900
0.885
54.77 2.736
109.29 0.0086
75.47
0.964
24.85
1000
0.858
61.01 2.675
101.18 0.0092
73.48
0.958
27.75
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
17 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
9. Test information
VDS(B)
VAGC
5V
4.7 nF
10 kΩ
4.7 nF
50 Ω
DB
G1B
4.7 nF
G2
4.7 nF
RGEN
50 Ω
L1
2.2 μH
BF1207
G1A
50 Ω
S
4.7 nF
DA
L2
2.2 μH
RG1
RL
50 Ω
4.7 nF
Vi
VDS(A)
VGG
5V
5V
001aac907
Fig 29. Cross-modulation test set-up for amplifier A
VDS(B)
VAGC
5V
4.7 nF
10 kΩ
4.7 nF
RGEN
50 Ω
50 Ω
4.7 nF
G2
G1A
50 Ω
4.7 nF
DB
G1B
4.7 nF
Vi
L1
2.2 μH
BF1207
RL
50 Ω
S
DA
RG1
L2
2.2 μH
4.7 nF
VGG
VDS(A)
0V
5V
001aac908
Fig 30. Cross-modulation test set-up for amplifier B
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
18 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
10. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
c
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
SOT363
JEDEC
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 31. Package outline SOT363
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
19 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
11. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BF1207 v.2
20110907
Product data sheet
-
BF1207 v.1
Modifications:
BF1207 v.1
(9397 750 14955)
BF1207
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Package outline drawings have been updated to the latest version.
20050728
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
-
© NXP B.V. 2011. All rights reserved.
20 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
21 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BF1207
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 September 2011
© NXP B.V. 2011. All rights reserved.
22 of 23
BF1207
NXP Semiconductors
Dual N-channel dual gate MOSFET
14. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
9
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics for amplifier A. . . . . . . 6
Graphs for amplifier A. . . . . . . . . . . . . . . . . . . . 7
Scattering parameters for amplifier A . . . . . . . 11
Dynamic characteristics for amplifier B. . . . . . 12
Graphs for amplifier B. . . . . . . . . . . . . . . . . . . 13
Scattering parameters for amplifier B . . . . . . . 17
Test information . . . . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses[email protected]
Date of release: 7 September 2011
Document identifier: BF1207