Data Sheet

BF904; BF904R
N-channel dual gate MOS-FETs
Rev. 06 — 13 November 2007
Product data sheet
IMPORTANT NOTICE
Dear customer,
As from October 1st, 2006 Philips Semiconductors has a new trade name
- NXP Semiconductors, which will be used in future data sheets together with new contact
details.
In data sheets where the previous Philips references remain, please use the new links as
shown below.
http://www.philips.semiconductors.com use http://www.nxp.com
http://www.semiconductors.philips.com use http://www.nxp.com (Internet)
[email protected] use [email protected]
(email)
The copyright notice at the bottom of each page (or elsewhere in the document,
depending on the version)
- © Koninklijke Philips Electronics N.V. (year). All rights reserved is replaced with:
- © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales
office via e-mail or phone (details via [email protected]). Thank you for your
cooperation and understanding,
NXP Semiconductors
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
FEATURES
• Specially designed for use at 5 V supply voltage
• Short channel transistor with high transfer admittance to
input capacitance ratio
• Low noise gain controlled amplifier up to 1 GHz
• Superior cross-modulation performance during AGC.
APPLICATIONS
• VHF and UHF applications with 3 to 7 V supply voltage
such as television tuners and professional
communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT143B and SOT143R package. The
transistor consists of an amplifier MOS-FET with source
4
This product is supplied in anti-static packing to
prevent damage caused by electrostatic discharge
during transport and handling. For further information,
refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A
and SNW-FQ-302B.
PINNING
PIN
SYMBOL
DESCRIPTION
1
s, b
2
d
drain
3
g2
gate 2
4
g1
gate 1
source
d
d
handbook, halfpage
CAUTION
handbook, halfpage
3
3
4
g2
g2
g1
g1
1
Top view
2
2
s,b
MAM124
1
Top view
s,b
MAM125 - 1
BF904R marking code: %MD.
BF904 marking code: %MC.
Fig.1 Simplified outline (SOT143B) and symbol.
Fig.2 Simplified outline (SOT143R) and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
drain-source voltage
−
−
7
V
ID
drain current
−
−
30
mA
Ptot
total power dissipation
−
−
200
mW
Tj
operating junction temperature
−
−
150
°C
yfs
forward transfer admittance
22
25
30
mS
Cig1-s
input capacitance at gate 1
−
2.2
2.6
pF
Crs
reverse transfer capacitance
f = 1 MHz
−
25
35
fF
F
noise figure
f = 800 MHz
−
2
−
dB
Rev. 06 - 13 November 2007
2 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
drain-source voltage
−
7
V
ID
drain current
−
30
mA
IG1
gate 1 current
−
±10
mA
IG2
gate 2 current
−
±10
mA
Ptot
total power dissipation
see Fig.3
BF904
Tamb ≤ 50 °C; note 1
−
200
mW
BF904R
Tamb ≤ 40 °C; note 1
−
200
mW
Tstg
storage temperature
−65
+150
°C
Tj
operating junction temperature
−
150
°C
Note
1. Device mounted on a printed-circuit board.
MRA770
250
handbook, halfpage
P
tot
(mW)
200
BF904
150
BF904R
100
50
0
0
50
100
150
200
Tamb (o C)
Fig.3 Power derating curves.
Rev. 06 - 13 November 2007
3 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
Rth j-s
PARAMETER
CONDITIONS
VALUE
UNIT
BF904
500
K/W
BF904R
550
K/W
thermal resistance from junction to ambient
note 1
thermal resistance from junction to soldering point
note 2
BF904
Ts = 92 °C
290
K/W
BF904R
Ts = 78 °C
360
K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V(BR)G1-SS
gate 1-source breakdown voltage
VG2-S = VDS = 0; IG1-S = 10 mA
6
15
V
V(BR)G2-SS
gate 2-source breakdown voltage
VG1-S = VDS = 0; IG2-S = 10 mA
6
15
V
V(F)S-G1
forward source-gate 1 voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate 2 voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate 1-source threshold voltage
VG2-S = 4 V; VDS = 5 V; ID = 20 µA
0.3
1
V
VG2-S(th)
gate 2-source threshold voltage
VG1-S = VDS = 5 V; ID = 20 µA
0.3
1.2
V
IDSX
drain-source current
VG2-S = 4 V; VDS = 5 V;
RG1 = 120 kΩ; note 1
8
13
mA
IG1-SS
gate 1 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V
−
50
nA
IG2-SS
gate 2 cut-off current
VG1-S = VDS = 0; VG2-S = 5 V
−
50
nA
Note
1. RG1 connects gate 1 to VGG = 5 V; see Fig.20.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
pulsed; Tj = 25 °C
22
25
30
mS
Cig1-s
input capacitance at gate 1
f = 1 MHz
−
2.2
2.6
pF
Cig2-s
input capacitance at gate 2
f = 1 MHz
1
1.5
2
pF
Cos
drain-source capacitance
f = 1 MHz
1
1.3
1.6
pF
Crs
reverse transfer capacitance f = 1 MHz
−
25
35
fF
F
noise figure
f = 200 MHz; GS = 2 mS; BS = BSopt
−
1
1.5
dB
f = 800 MHz; GS = GSopt; BS = BSopt
−
2
2.8
dB
Rev. 06 - 13 November 2007
4 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
MRA769
MLD268
40
0
handbook,
gain halfpage
reduction
(dB)
10
Y fs
(mS)
30
20
20
30
40
10
50
0
50
0
50
100
0
150
o
T j ( C)
1
2
3
4
VAGC (V)
f = 50 MHz.
Fig.4
Transfer admittance as a function of the
junction temperature; typical values.
Fig.5
Typical gain reduction as a function of
the AGC voltage.
MRA771
120
MLD270
20
handbook, halfpage
Vunw
V G2 S = 4 V
ID
(dB µV)
3V
2.5 V
(mA)
110
15
100
10
2V
1.5 V
90
5
1V
80
0
10
20
30
40
50
gain reduction (dB)
0
0
0.4
0.8
1.2
2.0
1.6
V G1 S (V)
VDS = 5 V; VGG = 5 V; fw = 50 MHz.
funw = 60 MHz; Tamb = 25 °C; RG1 = 120 kΩ.
Fig.6
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.20.
VDS = 5 V.
Tj = 25 °C.
Fig.7 Transfer characteristics; typical values.
Rev. 06 - 13 November 2007
5 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
MLD269
20
MLD271
150
handbook, halfpage
handbook, halfpage
V G1 S = 1.4 V
ID
(mA)
16
V G2 S = 4 V
3.5 V
I G1
(µA)
1.3 V
3V
100
1.2 V
12
1.1 V
8
2.5 V
1.0 V
50
2V
0.9 V
4
0
0
0
2
4
6
8
10
V DS (V)
0
0.5
1.0
1.5
2.0
2.5
V G1 S (V)
VDS = 5 V.
Tj = 25 °C.
VG2-S = 4 V.
Tj = 25 °C.
Fig.9
Fig.8 Output characteristics; typical values.
MLD272
40
Gate 1 current as a function of gate 1
voltage; typical values.
MLD273
16
handbook, halfpage
handbook, halfpage
y fs
(mS)
V G2 S = 4 V
30
ID
(mA)
12
3.5 V
3V
20
2.5 V
8
4
10
2V
0
0
0
4
8
12
16
20
I D (mA)
0
10
20
30
40
50
I G1 (µA)
VDS = 5 V.
VDS = 5 V.
Tj = 25 °C.
VG2-S = 4 V.
Tj = 25 °C.
Fig.10 Forward transfer admittance as a
function of drain current; typical values.
Fig.11 Drain current as a function of gate 1 current;
typical values.
Rev. 06 - 13 November 2007
6 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
MLD275
12
handbook, halfpage
BF904; BF904R
MLD274
20
handbook, halfpage
R G1 = 47 kΩ
ID
(mA)
ID
68 kΩ
82 kΩ
(mA)
15
100 kΩ
8
120 kΩ
150 kΩ
10
180 kΩ
220 kΩ
4
5
0
0
0
1
2
3
4
0
5
2
4
VGG (V)
VDS = 5 V; VG2-S = 4 V.
RG1 = 120 kΩ (connected to VGG); Tj = 25 °C.
6
V GG = V DS (V)
VG2-S = 4 V.
RG1 connected to VGG; Tj = 25 °C.
Fig.12 Drain current as a function of gate 1
supply voltage (= VGG); typical values;
see Fig.20.
Fig.13 Drain current as a function of gate 1
(= VGG) and drain supply voltage;
typical values; see Fig.20.
MLD276
12
MLB945
40
handbook, halfpage
handbook, halfpage
V GG = 5 V
4.5 V
ID
I G1
(µA)
4V
(mA)
V GG = 5 V
30
3.5 V
8
8
4.5 V
3V
4V
3.5 V
20
3V
4
10
0
0
2
4
V G2 S (V)
6
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG).
0
0
2
4
V G2 S (V)
6
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG).
Fig.14 Drain current as a function of gate 2 voltage;
typical values; see Fig.20.
Fig.15 Gate 1 current as a function of gate 2
voltage; typical values; see Fig.20.
Rev. 06 - 13 November 2007
7 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
MLD277
10 2
handbook, halfpage
MLD278
10 3
y is
(mS)
10 3
ϕ rs
(deg)
y rs
(µS)
10 2
10
ϕ rs
10 2
y rs
b is
1
10
10
g is
10 1
10
102
f (MHz)
1
1
10 3
10
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.16 Input admittance as a function of frequency;
typical values.
MLD279
10 2
y fs
ϕ fs
y fs
(mS)
10 2
Fig.17 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD280
10
handbook, halfpage
yos
(mS)
(deg)
bos
1
ϕ fs
10
10
gos
10 1
1
1
10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
10 2
10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.18 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.19 Output admittance as a function of
frequency; typical values.
Rev. 06 - 13 November 2007
8 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
VAGC
R1
10 k Ω
C1
4.7 nF
C2
R GEN
50 Ω
R2
50 Ω
C3
L1
DUT
4.7 nF
12 pF
≈ 450 nH
RL
50 Ω
C4
R G1
4.7 nF
VI
VGG
V DS
MLD171
Fig.20 Cross-modulation test set-up.
Rev. 06 - 13 November 2007
9 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
Table 1
f
(MHz)
BF904; BF904R
Scattering parameters: VDS =5 V; VG2-S = 4 V; ID = 10 mA
S11
MAGNITUDE
(ratio)
S21
ANGLE
(deg)
S12
S22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
−3.4
2.420
175.7
0.000
79.9
0.993
−1.6
40
0.989
100
0.985
−8.3
2.414
169.1
0.001
78.3
0.992
−3.9
200
0.976
−16.4
2.368
158.8
0.003
80.3
0.987
−7.8
300
0.958
−24.1
2.301
148.5
0.004
73.7
0.980
−11.4
400
0.942
−32.0
2.251
138.8
0.005
70.7
0.974
−15.2
500
0.918
−39.3
2.170
129.5
0.005
67.2
0.966
−18.7
600
0.899
−46.0
2.080
120.7
0.005
67.8
0.958
−22.2
700
0.876
−52.6
2.001
112.1
0.005
68.6
0.951
−25.5
800
0.852
−58.8
1.924
103.2
0.005
72.9
0.944
−28.9
900
0.823
−64.9
1.829
94.7
0.005
78.7
0.937
−32.1
1000
0.800
−70.9
1.747
86.5
0.005
88.3
0.933
−35.2
1200
0.750
−82.4
1.621
70.7
0.005
120.5
0.928
−41.7
1400
0.719
−92.7
1.535
54.6
0.008
139.8
0.930
−48.4
1600
0.682
−102.5
1.424
39.4
0.010
137.8
0.924
−54.9
1800
0.642
−109.8
1.349
22.5
0.013
156.8
0.928
−62.9
2000
0.602
−116.5
1.283
1.1
0.018
175.1
0.928
−73.1
2200
0.547
−124.9
1.130
−15.1
0.014
172.6
0.887
−81.0
2400
0.596
−128.7
1.018
−49.1
0.040
−163.9
0.837
−95.8
2600
0.682
−132.6
0.979
−79.4
0.077
−164.0
0.778
−109.6
2800
0.771
−142.5
0.804
−116.2
0.120
178.8
0.629
−119.5
3000
0.793
−157.5
0.541
−153.5
0.149
158.3
0.479
−119.9
Table 2
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA
Γopt
f
(MHz)
Fmin
(dB)
(ratio)
(deg)
800
2.00
0.686
49.6
Rev. 06 - 13 November 2007
rn
50.40
10 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
PACKAGE OUTLINES
Plastic surface mounted package; 4 leads
SOT143B
D
B
E
A
X
y
HE
v M A
e
bp
w M B
4
3
Q
A
A1
c
1
2
Lp
b1
e1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
b1
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.1
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
1.9
1.7
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
SOT143B
Rev. 06 - 13 November 2007
11 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
Plastic surface mounted package; reverse pinning; 4 leads
D
SOT143R
B
E
A
X
y
HE
v M A
e
bp
w M B
3
4
Q
A
A1
c
2
1
Lp
b1
e1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
b1
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.1
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
1.9
1.7
2.5
2.1
0.55
0.25
0.45
0.25
0.2
0.1
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-03-10
SOT143R
Rev. 06 - 13 November 2007
12 of 14
BF904; BF904R
NXP Semiconductors
N-channel dual gate MOS-FETs
Legal information
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
Rev. 06 - 13 November 2007
13 of 14
BF904; BF904R
NXP Semiconductors
N-channel dual gate MOS-FETs
Revision history
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BF904_904R_N_6
20071113
Product data sheet
-
BF904_904R_5
•
Modifications:
Fig. 1 and 2 on page 2; Figure note changed
BF904_904R_5
(9397 750 05898)
19990517
Product specification
-
BF904R_4
BF904R_4
(9397 750 02668)
19970905
Product specification
-
BF904R_3
BF904R_3
19950425
Product specification
-
BF904R_2
BF904R_2
-
-
-
BF904R_1
BF904R_1
-
-
-
-
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 November 2007
Document identifier: BF904_904R_N_6
Similar pages