Data Sheet

BF909; BF909R
N-channel dual gate MOS-FETs
Rev. 02 — 19 November 2007
Product data sheet
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NXP Semiconductors
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
transistor consists of an amplifier MOS-FET with source
and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
FEATURES
• Specially designed for use at 5 V supply voltage
• High forward transfer admittance
• Short channel transistor with high forward transfer
admittance to input capacitance ratio
CAUTION
• Low noise gain controlled amplifier up to 1 GHz
• Superior cross-modulation performance during AGC.
APPLICATIONS
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
PINNING
• VHF and UHF applications with 3 to 7 V supply voltage
such as television tuners and professional
communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT143 or SOT143R package. The
PIN
SYMBOL
DESCRIPTION
1
s, b
2
d
drain
3
g2
gate 2
4
g1
gate 1
source
d
d
handbook, halfpage
4
BF909; BF909R
handbook, halfpage
3
3
4
g2
g2
g1
g1
1
Top view
2
2
s,b
MAM124
BF909 marking code: %M3.
1
Top view
s,b
MAM125 - 1
BF909R marking code: %M4.
Fig.1 Simplified outline (SOT143) and symbol.
Fig.2 Simplified outline (SOT143R) and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
drain-source voltage
−
−
7
V
ID
drain current
−
−
40
mA
Ptot
total power dissipation
−
−
200
mW
Tj
operating junction temperature
−
−
150
°C
yfs
forward transfer admittance
36
43
50
mS
Cig1-s
input capacitance at gate 1
−
3.6
4.3
pF
Crs
reverse transfer capacitance
f = 1 MHz
−
35
50
fF
F
noise figure
f = 800 MHz
−
2
2.8
dB
Rev. 02 - 19 November 2007
2 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF909; BF909R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
drain-source voltage
−
7
V
ID
drain current
−
40
mA
IG1
gate 1 current
−
±10
mA
IG2
gate 2 current
−
±10
mA
Ptot
total power dissipation
see Fig.3
BF909
up to Tamb = 50 °C; note 1
−
200
mW
BF909R
up to Tamb = 40 °C; note 1
−
200
mW
Tstg
storage temperature
−65
+150
°C
Tj
operating junction temperature
−
150
°C
Note
1. Device mounted on a printed-circuit board.
MLB935
250
handbook, halfpage
Ptot
(mW)
200
150
BF909R
BF909
100
50
0
0
50
100
150
200
Tamb ( oC)
Fig.3 Power derating curves.
Rev. 02 - 19 November 2007
3 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF909; BF909R
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
Rth j-s
PARAMETER
CONDITIONS
VALUE
UNIT
BF909
500
K/W
BF909R
550
K/W
thermal resistance from junction to ambient
note 1
thermal resistance from junction to soldering point
note 2
BF909
Ts = 92 °C
290
K/W
BF909R
Ts = 78 °C
360
K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V(BR)G1-SS
gate 1-source breakdown voltage
VG2-S = VDS = 0; IG1-S = 10 mA
6
15
V
V(BR)G2-SS
gate 2-source breakdown voltage
VG1-S = VDS = 0; IG2-S = 10 mA
6
15
V
V(F)S-G1
forward source-gate 1 voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate 2 voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate 1-source threshold voltage
VG2-S = 4 V; VDS = 5 V;
ID = 20 µA
0.3
1
V
VG2-S(th)
gate 2-source threshold voltage
VG1-S = VDS = 5 V; ID = 20 µA
0.3
1.2
V
IDSX
drain-source current
VG2-S = 4 V; VDS = 5 V;
RG1 = 120 kΩ; note 1
12
20
mA
IG1-SS
gate 1 cut-off current
VG1-S = 5 V; VG2-S = VDS = 0
−
50
nA
IG2-SS
gate 2 cut-off current
VG2-S = 5 V; VG1-S = VDS = 0
−
50
nA
Note
1. RG1 connects gate 1 to VGG = 5 V; see Fig.18.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
pulsed; Tj = 25 °C
36
43
50
mS
Cig1-s
input capacitance at gate 1
f = 1 MHz
−
3.6
4.3
pF
Cig2-s
input capacitance at gate 2
f = 1 MHz
−
2.3
3
pF
Cos
drain-source capacitance
f = 1 MHz
−
2.3
3
pF
Crs
reverse transfer capacitance f = 1 MHz
−
35
50
fF
F
noise figure
−
2
2.8
dB
f = 800 MHz; GS = GSopt; BS = BSopt
Rev. 02 - 19 November 2007
4 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
MLB936
110
BF909; BF909R
MLB937
30
handbook, halfpage
handbook, halfpage
V G2 S = 4 V 3 V
Vunw
ID
(dBµV)
(mA)
2.5 V
2V
100
20
90
10
1.5 V
1V
80
0
10
20
30
40
50
gain reduction (dB)
0
0
0.4
0.8
1.2
1.6
2.0
V G1 S (V)
VDS = 5 V; VGG = 5 V; fw = 50 MHz.
funw = 60 MHz; Tamb = 25 °C; RG1 = 120 kΩ.
Fig.4
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.18.
MLB938
30
handbook, halfpage
MLB939
200
I G1
(µA)
ID
1.3 V
20
Fig.5 Transfer characteristics; typical values.
handbook, halfpage
V G1 S = 1.4 V
(mA)
VDS = 5 V.
Tj = 25 °C.
V G2 S = 4 V
150
3.5 V
1.2 V
3V
100
1.1 V
2.5 V
1.0 V
10
50
0.9 V
2V
0
0
0
2
4
6
8
10
V DS (V)
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 °C.
0
1
2
V G1 S (V)
3
VDS = 5 V.
Tj = 25 °C.
Fig.7
Fig.6 Output characteristics; typical values.
Rev. 02 - 19 November 2007
Gate 1 current as a function of gate 1
voltage; typical values.
5 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF909; BF909R
MLB941
MLB940
60
25
handbook, halfpage
handbook, halfpage
ID
(mA)
20
V G2 S = 4 V
y fs
(mS)
3.5 V
3V
40
15
2.5 V
10
20
5
2V
0
0
0
10
20
I D (mA)
30
VDS = 5 V.
Tj = 25 °C.
Fig.8
0
20
40
I G1 (µA)
60
VDS = 5 V; VG2-S = 4 V.
Tj = 25 °C.
Forward transfer admittance as a
function of drain current; typical values.
Fig.9
Drain current as a function of gate 1 current;
typical values.
MLB942
16
MLB943
30
handbook, halfpage
handbook, halfpage
ID
(mA)
R G1 = 47 kΩ
ID
(mA)
68 kΩ
82 kΩ
12
100 kΩ
20
120 kΩ
150 kΩ
8
180 kΩ
220 kΩ
10
4
0
0
0
2
4
V GG (V)
6
VDS = 5 V; VG2-S = 4 V.
RG1 = 120 kΩ (connected to VGG); Tj = 25 °C.
0
2
4
6
V GG = V DS (V)
8
VG2-S = 4 V.
RG1 connected to VGG; Tj = 25 °C.
Fig.10 Drain current as a function of gate 1
supply voltage (= VGG); typical values;
see Fig.18.
Fig.11 Drain current as a function of gate 1
(= VGG) and drain supply voltage;
typical values; see Fig.18.
Rev. 02 - 19 November 2007
6 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF909; BF909R
MLB944
20
MLB945
40
handbook, halfpage
handbook, halfpage
ID
(mA)
16
V GG = 5 V
I G1
(µA)
4.5 V
V GG = 5 V
30
4V
4.5 V
3.5 V
12
4V
3V
3.5 V
20
3V
8
10
4
0
0
0
2
4
V G2 S (V)
6
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG).
0
2
4
V G2 S (V)
6
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG).
Fig.12 Drain current as a function of gate 2 voltage;
typical values; see Fig.18.
MLB946
10 2
handbook, halfpage
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values; see Fig.18.
MLB947
10 3
ϕ rs
(deg)
y rs
(µS)
y is
(mS)
ϕ rs
10 2
10
10 3
10 2
b is
y rs
10
1
10
g is
10 1
10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
1
1
10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.14 Input admittance as a function of frequency;
typical values.
Fig.15 Reverse transfer admittance and phase as
a function of frequency; typical values.
Rev. 02 - 19 November 2007
7 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
MLB948
10 2
MLB949
10 2
y fs
y fs
BF909; BF909R
10
handbook, halfpage
yos
(mS)
ϕ fs
bos
(deg)
(mS)
1
ϕfs
10
gos
10
10 1
10 2
10
1
1
10
102
10 3
f (MHz)
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.16 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.17 Output admittance as a function of
frequency; typical values.
VAGC
R1
10 k Ω
C1
4.7 nF
R3
10 Ω
C2
R GEN
50 Ω
R2
50 Ω
C3
DUT
4.7 nF
R G1
C5
2.2
pF
12 pF
L1
≈ 350 nH
RL
50 Ω
C4
4.7 nF
VI
VGG
VDS
MLD151
Fig.18 Cross-modulation test set-up.
Rev. 02 - 19 November 2007
8 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
Table 1
f
(MHz)
BF909; BF909R
Scattering parameters: Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 15 mA
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.985
−6.4
4.064
172.3
0.001
86.9
0.985
−3.2
100
0.978
−12.6
3.997
164.9
0.002
82.7
0.982
−6.4
200
0.957
−25.0
3.886
150.8
0.005
74.3
0.973
−12.6
300
0.931
−36.5
3.682
137.3
0.006
68.9
0.960
−18.6
400
0.899
−47.6
3.484
123.8
0.007
59.6
0.947
−24.2
500
0.868
−57.4
3.260
111.7
0.007
57.9
0.936
−29.6
600
0.848
−66.6
3.053
101.0
0.006
58.5
0.927
−34.8
700
0.816
−74.6
2.829
90.3
0.005
65.5
0.919
−39.8
800
0.792
−82.2
2.652
79.9
0.005
83.3
0.913
−44.6
900
0.772
−89.3
2.470
69.5
0.005
114.9
0.910
−49.5
1000
0.754
−95.6
2.328
59.5
0.006
138.7
0.909
−54.6
Table 2
Noise data: Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 15 mA
Γopt
f
(MHz)
Fmin
(dB)
(ratio)
(deg)
800
2.00
0.603
67.71
Rev. 02 - 19 November 2007
rn
0.581
9 of 12
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF909; BF909R
PACKAGE OUTLINES
handbook, full pagewidth
3.0
2.8
0.150
0.090
0.75
0.60
B
1.9
4
3
0.1
max
o
10
max
0.2 M A B
A
2.5
max
1.4
1.2
o
10
max
1
1.1
max
o
30
max
2
0
0.1
0.88
0.48
0
0.1
0.1 M A B
MBC845
1.7
TOP VIEW
Dimensions in mm.
Fig.19 SOT143.
3.0
2.8
handbook, full pagewidth
0.150
0.090
0.40
0.25
B
1.9
3
4
0.1
max
o
10
max
0.2 M A
A
1.4
1.2
o
2.5
max
10
max
2
1.1
max
o
30
max
1
0.48
0.38
0.88
0.78
MBC844
1.7
0.1 M B
TOP VIEW
Dimensions in mm.
Fig.20 SOT143R.
Rev. 02 - 19 November 2007
10 of 12
BF909; BF909R
NXP Semiconductors
N-channel dual gate MOS-FETs
Legal information
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
Rev. 02 - 19 November 2007
11 of 12
BF909; BF909R
NXP Semiconductors
N-channel dual gate MOS-FETs
Revision history
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BF909_N_2
20071119
Product data sheet
-
BF909_1
-
-
Modifications:
BF909_1
•
Fig.1 and 2 on page 2; Figure note changed
19950425
Product specification
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 November 2007
Document identifier: BF909_N_2
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