DESIGN INFORMATION LTC1546 Multiprotocol Chip Simplifies NET1-, NET2- and TBR2-Compliant Serial Interfaces by Dan Eddleman ports the V.28 (RS232), V.35, V.36, X.21, RS449, EIA530 and EIA530-A protocols, including all of the necessary cable termination. With these two chips, the physical layer of a NET1-, NET2- and TBR2-compliant C3 1µF VCC 5V C1 1µF 3 28 1 27 26 CHARGE PUMP 2 4 25 C5 1µF LTC1546 5 DTE_TXD/DCE_RXD D1 6 DTE_SCTE/DCE_RXC T D2 T C2 1µF + The LTC1546 multiprotocol transceiver simplifies network interface design and frees up valuable PC board real estate. Operating from a single 5V supply, the LTC1546 and LTC1544 form a complete, software-selectable DTE or DCE interface port that sup- C4 3.3µF 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 DTE DCE TXD A RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B 7 D3 8 DTE_TXC/DCE_TXC 11 12 13 14 C9 1µF DTE_DTR/DCE_DSR T R3 M0 7 M1 M2 1 DCE/DTE VCC 1 VCC 2 VDD DTE_RTS/DCE_CTS T R2 10 DTE_RXD/DCE_TXD C10 1µF R1 9 DTE_RXC/DCE_SCTE T 3 VEE GND D1 4 D2 5 DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS DTE_LL/DCE_LL 6 7 R2 8 R3 10 11 12 M1 13 M2 14 DCE/DTE DB-25 CONNECTOR 28 C11 1µF 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B continued on page 35 Table 1. Mode-pin functions R1 R4 9 M0 SHIELD D3 LTC1544 DTE_DCD/DCE_DCD SG interface can be implemented in less than 3cm2. In a typical application (see Figure 1), the 3-driver/3-receiver LTC1546 multiprotocol serial transceiver/cable terminator handles the clock and data signals, and the 4-driver/4-receiver LTC1544 multiprotocol transceiver handles the control signals. The mode pins, M0, M1 and M2, select the active protocol and termination (see Table 1) and the DCE/DTE pin selects DTE or DCE mode. PC board layout consists of routing the pins of an LTC1546 and an LTC1544 to the connector and placing bypass and charge pump capacitors (see Figure 1). The LTC1546/ LTC1544 chipset is appropriate for most multiprotocol applications. Systems that additionally require LL (local loop-back), RL (remote loop-back), TM (test mode) or RI (ring indicate) signals should use the 5-driver/ 5-receiver LTC1545 multiprotocol transceiver in place of the LTC1544. The LTC1546 is pin compatible with the popular LTC1543 multiprotocol transceiver and has the added feature of on-chip cable termination. Most previous applications used an LTC1543 for the clock and data transceivers and an LTC1344A for the necessary cable termination. With the 22 8 21 10 20 6 19 22 18 5 17 13 16 18 DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B LL A LL A D4 M0 INVERT 15 DCD A NC M1 M2 DCE/DTE LTC1546/LTC1545 Mode Name M2 M1 M0 Not Used 0 0 0 EIA-530A 0 0 1 EIA-530 0 1 0 X. 21 0 1 1 V. 35 1 0 0 RS449/V.36 1 0 1 RS232/V.28 1 1 0 No Cable 1 1 1 Figure 1. LTC1544/LTC1546 software-selectable multiprotocol DCE/DTE port Linear Technology Magazine • February 2000 33 DESIGN INFORMATION The first source is caused by the settling of the internal sampling capacitor and is input referred; that is, it is multiplied by the closed loop gain of the op amp. This form of clock feedthrough is independent of input source resistance or gain setting resistors. Figure 4 shows the spectrum of the LTC2050 with a closed loop gain of –100 with R2 = 100k, and R1 = RS = 1k. There is a residue clock feedthrough of less than 1µVRMS (input-referred) at 7.5kHz. This very low clock feedthough is achieved in the LTC2050 by internal circuitry that improves settling of the internal autozero storage capacitors. Also in Figure 4, the clock feedthrough of the LTC2050 is compared with that of the very popular LTC1050. The second form of clock feedthrough appears when the input has a large source resistance or the gainsetting resistors are large. In this case, the charge injection caused by the internal MOS switches creates input-referred clock feedthrough currents that are multiplied by the impedance seen at the input terminals of the op amp. This form of clock feedthrough is not significant in the LTC2050 when RS and R1 in Figure 4 are below approximately 10k. Placing a capacitor across R2 reduces either form of clock feedthrough by lowering the bandwidth of the closed-loop response. 1mVRMS LTC2050 BW = 95Hz 100µVRMS/DIV 0mVRMS 1mVRMS LTC1050 BW = 95Hz 100µVRMS/DIV 0mVRMS 100Hz 1kHz/DIV 10.1kHz R2 R1 – RS + Figure 4. Output spectrum with a gain of 100; R2 = 100k; R1 = RS = 1k Conclusion The LTC2050 is the latest member of Linear Technology’s family of zerodrift operational amplifiers. It provides small packaging while still maintaining precision DC specifications. In addition, it operates at supplies as low as 2.7V and includes a power shutdown in the 6-lead SOT -23 package. For more information on parts featured in this issue, see http://www.linear-tech.com/go/ltmag LTC1546/LTC1545, continued from page 33 introduction of the LTC1546, the LTC1344A is no longer required. In fact, in most existing designs, the LTC1543 can be replaced by an LTC1546, and the LTC1344A can be removed without any changes to the PC board. In new designs, the LTC1546 will simplify PC board lay- out and reduce the required footprint compared to the LTC1543/LTC1544 solution. The LTC1546/LTC1544 chipset has been tested by TUV Telecom Services, Inc. and has been found to be compliant with the NET1, NET2 and TBR2 requirements. Test reports are available from LTC or TUV upon request (NET1 and NET2 report NET2/091301/99; TBR2 report CTR2/091301/99). http://www.linear-tech.com/ezone/zone.html Articles, Design Ideas, Tips from the Lab… Linear Technology Magazine • February 2000 35