® RT9088 DDR Termination Regulator General Description Features The RT9088 is a sink/source tracking termination regulator. It is specifically designed for low-cost and low-external component count systems. The RT9088 possesses a high speed operating amplifier that provides fast load transient response and only requires a minimum 30μF ceramic output capacitor. The RT9088 supports remote sensing functions and all features required to power the DDRIII and Low Power DDRIII / DDRIV VTT bus termination according to the JEDEC specification. In addition, the RT9088 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications. VIN Input Voltage Range: 1.1V to 3.5V VCNTL Input Voltage Range: 2.9V to 5.5V Support Ceramic Capacitors Power Good Indicator 10mA Source/Sink Reference Output Meet DDRI, DDRII JEDEC Spec Support DDRIII, Low Power DDRIII/DDRIV VTT Applications Soft-Start Function UVLO and OCP Protection Thermal Shutdown Applications The RT9088 is available in the thermal efficient package, WDFN-10L 3x3. Notebook/Desktop/Server Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV, Copier/Printer, Set-Top Box Marking Information 63= : Product Code 63=YM DNN YMDNN : Date Code Simplified Application Circuit RT9088 VIN VIN VCNTL R1 R3 REFIN C1 PGOOD C2 R2 VCNTL C4 Power Good Indicator VOUT SENSE REFOUT REFOUT C3 EN EN Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9088-03 August 2015 VOUT C5 PGND GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9088 Ordering Information Pin Configurations RT9088 Package Type QW : WDFN-10L 3x3 (W-Type) REFIN VIN VOUT PGND SENSE Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : 1 2 3 4 5 GND (TOP VIEW) 11 10 9 8 7 6 VCNTL PGOOD GND EN REFOUT WDFN-10L 3x3 RoHS compliant and compatible with the current require- Suitable for use in SnPb or Pb-free soldering processes. ments of IPC/JEDEC J-STD-020. Functional Pin Description Pin No. Pin Name Pin Function 1 REFIN Reference Input. 2 VIN Power Input of the Regulator. 3 VOUT Power Output of the Regulator. 4 PGND Power Ground of the Regulator. 5 SENSE Voltage Sense Input for the Regulator. Connect to positive terminal of the output capacitor or the load. 6 REFOUT Reference Output. Connect to GND through a 0.1F ceramic capacitor. 7 EN Enable Control Input. For DDR VTT application, connect EN to SLP_S3. For other applications, use EN as the ON/OFF function. 9 PGOOD Power Good Open-Drain Output. Connect a pull-up resistor between this pin and VCNTL pin. 10 VCNTL Control Voltage Input. Connect this pin to the 3.3V or 5V power supply. A ceramic decoupling capacitor with a value 4.7F is required. 8, GND 11 (Exposed Pad) Analog Ground. Connect to negative terminal of the output capacitor. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9088-03 August 2015 RT9088 Function Block Diagram EN VCNTL REFIN Control Logic Thermal Protection VIN + OCP - Buffer REFOUT VOUT SENSE OP + PGOOD Power Good Driver + OCP - GND PGND Operation The RT9088 is a linear sink/source DDR termination regulator with current capability up to 3A. The RT9088 builds in a high-side N-MOSFET which provides current sourcing and a low-side N-MOSFET which provides current sinking. All the control circuits are supplied by the power VCNTL. In normal operation, the error amplifier OP adjusts the gate driving voltage of the power MOSFET to achieve SENSE voltage well tracking the REFIN voltage. Both the source and sink currents are detected by the internal sensing resistor, and the OCP function will work to limit the current to a designed value when overload happens. Furthermore, the current will be folded back to be one half if VOUT is out of the power good window. Buffer This function provides REFOUT output equal to REFIN with 10mA source/sink current capability. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9088-03 August 2015 Power Good When the SENSE voltage is in the power good window and lasts for a certain delay time, then the PGOOD pin will be high impedance and the PGOOD voltage will be pulled high by the external resistor. Control Logic This block includes VCNTL UVLO, REFIN UVLO and Enable/Disable functions, and provides logic control to the whole chip. Thermal Protection Both the high-side and low-side power MOSFETs will be turned off when the junction temperature is higher than typically 160°C, and be released to normal operation when junction temperature falls below 120°C typically. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9088 Absolute Maximum Ratings (Note 1) Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------Input Voltage, EN, REFIN, SENSE ----------------------------------------------------------------------------------Output Voltage, VOUT, REFOUT, PGOOD -------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 6V −0.3V to 6V −0.3V to 6V 3.27W 30.5°C/W 7.5°C/W 260°C 150°C −65°C to 150°C 2kV (Note 4) Control Input Voltage, VCNTL -----------------------------------------------------------------------------------------Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------- 2.9V to 5.5V 1.1V to 3.5V −40°C to 125°C −40°C to 85°C Electrical Characteristics (VIN = 1.5V, VEN = VCNTL = 3.3V, VREFIN = VSENSE = 0.75V, COUT = 10μF x 3, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VEN = VCNTL, No Load -- 0.7 1 mA VEN = 0V, VREFIN = 0V, No Load -- 65 80 A VEN = 0V, VREFIN > 0.4V, No Load -- 200 400 A Supply Current VCNTL Supply Current IVCNTL VCNTL Shutdown Current ISHDN_VCNTL VIN Supply Current IVIN VEN = VCNTL, No Load -- 1 50 A VIN Shutdown Current ISHDN_VIN VEN = 0V, No Load -- 0.1 50 A VIN = 1.5V, VREFIN = 0.75V, IOUT = 0A -- 0.75 -- V VIN = 1.35V, VREFIN = 0.675V, IOUT = 0A -- 0.675 -- V VIN = 1.2V, VREFIN = 0.6V, IOUT = 0A -- 0.6 -- V IOUT = ±2A, VLDOIN = 1.5V, VREFOUT = 0.75V 25 -- 25 IOUT = ±2A, VLDOIN = 1.35V, VREFOUT = 0.675V 25 -- 25 IOUT = ±2A, VLDOIN = 1.2V, VREFOUT = 0.6V 25 -- 25 Output VTT Output Voltage REFIN, VTT Output Voltage Offset VOUT VOUT_OS Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 mV is a registered trademark of Richtek Technology Corporation. DS9088-03 August 2015 RT9088 Parameter Symbol Test Conditions Min Typ Max Unit VOUT Source Current Limit ILIM_VOUT_SR VOUT in PGOOD Window 3.5 -- 5.5 A VOUT Sink Current Limit ILIM_VOUT_SK VOUT in PGOOD Window 3.5 -- 5.5 A VOUT Discharge Resistance RDISCHARGE VREFIN = 0V, VOUT = 0.3V, VEN = 0V -- 18 25 VSENSE lower threshold with respect to REFOUT 25 20 15 VSENSE upper threshold with respect to REFOUT 15 20 25 PGOOD Hysteresis -- 5 -- Power Good Comparator PGOOD Threshold VTH_PGOOD % PGOOD Start-Up Delay TPGDELAY1 Start-up rising delay, VSENSE within PGOOD range -- 2 -- ms Output Low Voltage VLOW_PGOOD IPGOOD = 4mA -- -- 0.4 V PGOOD Falling Delay TPGDELAY2 Falling delay, VSENSE is out of PGOOD range -- 10 -- s Leakage Current VSENSE = VREFIN (PGOOD ILEAKAGE _PGOOD high impedance), VPGOOD = VIN + 0.3V -- -- 1 A REFIN Input Current IREFIN -- -- 1 A REFIN Voltage Range VREFIN 0.5 -- 1.8 V REFIN Under-Voltage Lockout VUVLO_REFIN 360 390 420 -- 20 -- 10mA < IREFOUT < 10mA, VREFIN = 0.75V 15 -- 15 10mA < IREFOUT < 10mA, VREFIN = 0.675V 15 -- 15 10mA < IREFOUT < 10mA, VREFIN = 0.6V 15 -- 15 ILIM_REFOUT_SR VREFOUT = 0V 10 40 -- mA ILIM_REFOUT_SK VREFOUT = REFIN + 1V 10 40 -- mA Rising 2.5 2.7 2.85 V -- 120 -- mV 1.7 -- -- -- -- 0.3 Shutdown Temperature -- 160 -- Hysteresis -- 15 -- REFIN and REFOUT REFOUT Voltage Tolerance to VREFIN REFOUT Source Current Limit REFOUT Sink Current Limit VTOL_REFOUT VEN = VCNTL REFIN Rising Hysteresis mV mV UVLO/EN UVLO Threshold EN Input Voltage VUVLO_VCNTL Hysteresis Logic-High VIN_H Logic-Low VIN_L V Thermal Shutdown Thermal Shutdown Threshold TSD Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9088-03 August 2015 °C is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9088 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9088-03 August 2015 RT9088 Typical Application Circuit RT9088 VIN 2 R1 10k C1 10µF x 2 REFOUT 1 EN 7 PGOOD REFOUT EN Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9088-03 August 2015 VCNTL 10 REFIN C2 1nF R2 10k 6 C3 0.1µF VIN 9 VOUT 3 SENSE 5 4 PGND GND R3 100k C4 4.7µF VCNTL 2.5V/3.3V/5V Power Good Indicator C5 10µF x 3 VOUT 8, 11 (Exposed Pad) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9088 Typical Operating Characteristics REFOUT Voltage vs. Temperature 1.0 0.9 0.9 Output Voltage(V) Output Voltage (V) Output Voltage vs. Temperature 1.0 0.8 0.7 0.6 0.8 0.7 0.6 VCNTL = 3.3V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V 0.5 -50 -25 0 25 50 75 100 VCNTL = 3.3V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V 0.5 125 -50 -25 0 Temperature (°C) 50 75 100 125 VCNTL Shutdown Current vs. Temperature VCNTL Supply Current vs. Temperature 500.0 350 480.0 460.0 440.0 VCNTL = 5V 420.0 400.0 380.0 360.0 VCNTL = 3.3V 340.0 320.0 VIN = VDDQSNS = 1.5V, VOUT = 0.75V 300.0 -50 -25 0 25 50 75 100 VCNTL Shutdown Current (μA)1 VCNTL Supply Current (μA)1 25 Temperature (°C) 300 250 VCNTL = 5V 200 VCNTL = 3.3V 150 100 VIN = VDDQSNS = 1.5V, VOUT = 0.75V 50 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) UVLO vs. Temperature Sourcing Current Limit vs. Temperature 3.0 4.0 2.9 3.5 2.8 UVLO (V) 2.7 Current Limit (A) Rising 2.6 2.5 Falling 2.4 2.3 2.2 VIN = VDDQSNS = 1.5V, VEN = 2V, VOUT = 0.75V 2.1 2.0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 125 3.0 2.5 2.0 1.5 VCNTL = 3.3V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V 1.0 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS9088-03 August 2015 RT9088 Power On from EN Sinking Current Limit vs. Temperature 4.0 Current Limit (A) 3.5 VEN (2V/Div) 3.0 VOUT (0.5V/Div) 2.5 2.0 IOUT (1A/Div) 1.5 VCNTL = 3.3V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V VREFOUT (1V/Div) VCNTL = 3.3V, VIN = 1.5V, VOUT = 0.75V, IOUT = 1.5A 1.0 -50 -25 0 25 50 75 100 Time (100μs/Div) 125 Temperature (°C) 0.75VOUT @ 1.5A Transient Response Power Off from EN VEN (2V/Div) VOUT (10mV/Div) VOUT (0.5V/Div) IOUT (1A/Div) VREFOUT (1V/Div) VCNTL = 3.3V, VIN = 1.5V, VOUT = 0.75V, IOUT = 1.5A IOUT (1A/Div) Source, VIN = 1.5V Time (500μs/Div) Time (10μs/Div) 0.75VOUT @ 1.5A Transient Response VOUT (10mV/Div) IOUT (1A/Div) Sink, VIN = 1.5V Time (500μs/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9088-03 August 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9088 Application Information Capacitor Selection Good bypassing is recommended from VLDOIN to GND to help improve AC performance. A 10μF or greater input capacitor located as close as possible to the IC is recommended. The input capacitor must be located at a distance of less than 0.5 inches from the VLDOIN pin of the IC. Adding a 1μF ceramic capacitor close to the VIN pin and it should be kept away from any parasitic impedance from the supply power. For stable operation, the total capacitance of the ceramic capacitor at the VTT output terminal must be larger than 30μF. The RT9088 is designed specifically to work with low ESR ceramic output capacitor in space saving and performance consideration. Larger output capacitance can reduce the noise and improve load transient response, stability and PSRR. The output capacitor should be located near the VTT output terminal pin as close as possible. WDFN-10L 3x3 package, the thermal resistance, θJA, is 30.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for WDFN-10L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 3.5 Maximum Power Dissipation (W)1 The RT9088 is a 3.5A sink/source tracking termination regulator. It is specifically designed for low-cost and lowexternal component count system such as notebook PC applications. The RT9088 possesses a high speed operating amplifier that provides fast load transient response and only requires two 10μF ceramic input capacitors and three 10μF ceramic output capacitors. Four-Layer PCB 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 1. Derating Curve of Maximum Power Dissipation Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS9088-03 August 2015 RT9088 Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9088-03 August 2015 www.richtek.com 11