82a850rv110.pdf

HT82A850R
Audio MCU
Features
· Operating voltage: fSYS= 6MHz/12MHz: 3.3V~5.5V
· Play/record interrupt
· Low voltage reset function (3.0V±0.3V)
· HALT function and wake-up feature reduce power
consumption
· Embedded high performance 16 bit PCM DAC
· 24 bidirectional I/O lines (max.)
· Built-in digital Programmable Gain Amplifier - PGA
· Two 16-bit programmable timer/event counter and
· High-performance 48kHz/8kHz sampling rate for au-
overflow interrupts
dio software playback
· Watchdog Timer
· 8kHz audio recording sampling rate
· 16-level subroutine nesting
· Embedded class AB power amplifier for speaker
· Bit manipulation instruction
driving
· Audio playback digital volume control
· 15-bit table read instruction
· 4096´15 program memory
· 63 powerful instructions
· 384´8 data memory RAM (Bank0,1)
· All instructions executed within one or two machine
cycles
· Programmable frequency divider - PFD
· 48-pin LQFP package
· Integrated SPI hardware circuit
General Description
and the 16-bit PCM ADC operates at a frequency of
8kHz for the Microphone input. The DAC in the
HT82A850R also has a digital programmable gain amplifier, whose gain ranges from -32dB to +6dB. For the
ADC input, the digital gain range is from 0dB to 19.5dB.
The HT82A850R is an 8-bit high performance RISC-like
microcontroller designed for USB Phone product applications. The HT82A850R integrates a 16-bit PCM ADC
and an 8-bit MCU into a single device. The DAC in the
HT82A850R operates at a sampling rate of 48/8kHz
Rev. 1.10
1
July 25, 2007
HT82A850R
Block Diagram
S T A C K 0
B P
S T A C K 1
S T A C K 2
P ro g ra m
C o u n te r
M
S T A C K 1 5
M
T M R 1 C
M
M P
U
X
/4
X
Y S
P C 1 /T M R 0
IN T C
T M R 1
In s tr u c tio n
R e g is te r
U
T M R 0
S T A C K 1 4
P ro g ra m
R O M
fS
T M R 0 C
In te rru p t
C ir c u it
fS
U
X
D a ta
M e m o ry
/4
Y S
P C 2 /T M R 1
E N /D IS
W D T S
M U X
In s tr u c tio n
D e c o d e r
P O R T A
S T A T U S
P B C
S h ifte r
P O R T B
O S C O
O S C I
A V S S 3
V A G R e f
V A G
T G
1 6 - B it A /D
C o n v e rte r
D ig ita l P G A
D ig ita l
V o lu m e
C o n tro l
A V D D 3
Rev. 1.10
M
M
U
X
P o w e r
A m p
/4
P C 4 ~ P C 7
(S D O , S D I,
S C S ,S C K )
U
X
P C 0 /B Z
P F D
1 6 - b it
D /A
Y S
W D T O S C
P C 3
S e r ia l In te r fa c e
T IT I+
P O R T C
P C
A C C
fS
X
P B 0 ~ P B 7
P B
P C C
U
P A 0 ~ P A 7
P A
A L U
T im in g
G e n e ra to r
P A C
M
W D T
W D T P r e s c a le r
L O U T
R O U T
M U S IC _ IN
2
July 25, 2007
HT82A850R
Pin Assignment
N
N
D V S S
P A
P A
P A
P A
P A
P A
P A
P A
A V D D
C
C
2
0
1
2
3
4
5
6
7
1
R O U T
L O U T
A V S S 2
A V S S 1
B IA S
M U S IC _ IN
A V D D 1
A V D D 3
V A G R e f
V A G
T I+
T I-
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
2
3 6
3 5
3
3 4
4
3 3
5
6
3 2
H T 8 2 A 8 5 0 R
4 8 L Q F P -A
7
8
3 1
3 0
2 9
9
2 8
1 0
2 7
1 1
2 6
1 2
2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
N C
D V D D
R E S E
O S C O
O S C I
P C 0 /B
P C 1 /T
P C 2 /T
P C 3
P C 4 /S
P C 5 /S
P C 6 /S
T
1
Z
M R 0
M R 1
D O
D I
C S
P C
P B
P B
P B
P B
D V
P B
P B
P B
P B
A V
T G
7 /S C K
0
1
2
3
S S 2
4
5
6
7
S S 3
Pin Description
Pin Name
I/O
Description
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or a Schmitt
trigger input. Pull-high resistor can be connected to the pins via configuration options - nibble option.
AVDD2
¾
Audio power amplifier positive power supply
ROUT
O
Right driver analog output
LOUT
O
Left driver analog output
AVSS2
¾
Audio power amplifier negative power supply, ground
AVSS1
¾
Audio DAC negative power supply, ground
BIAS
¾
A capacitor should be connected between this pin and ground for half-supply stability
MUSIC_IN
I
Power amplifier signal source if register bit SELW =²1². The analog signal input will be amplified by the power amp then output to pins ROUT and LOUT at the same time.
AVDD1
¾
Audio DAC positive power supply
AVDD3
¾
ADC positive power supply
VAGRef
O
ADC analog ground reference voltage - should be left open or connected via a bypass capacitor (Ex:100pF) to ground
VAG
O
ADC analog ground voltage - should be connected via a bypass capacitor (Ex:1mF) to
ground
TI+
I
OP AMP non-inverting input
TI-
I
OP AMP inverting input
TG
O
OP AMP gain setting output
AVSS3
¾
ADC negative power supply, ground
PB0~PB7
I/O
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS
output or a Schmitt trigger input. Pull-high resistor can be connected to the pins via configuration options - nibble option.
DVSS2
¾
Negative digital & I/O power supply, ground
PC7/SCK
I/O
Can be software optioned as a bidirectional input/output or serial interface clock signal.
Rev. 1.10
3
July 25, 2007
HT82A850R
Pin Name
PC6/SCS
I/O
Description
I/O
Can be software optioned as a bidirectional input/output or serial interface slave select signal.
PC5/SDI
I/O or O Can be software optioned as a bidirectional input/output or serial data input.
PC4/SDO
I/O or O Can be software optioned as a bidirectional input/output or serial data output.
PC3
I/O
Bidirectional I/O lines. Software instructions determine if the pin is a CMOS output or a
Schmitt trigger input. Pull-high resistor can be connected to the pins via configuration options.
PC2/TMR1,
PC1/TMR0
I/O
Software instructions determine if the pin is a CMOS output or a Schmitt trigger input.
Pull-high resistor can be connected to the pins via configuration options.TMR0, TMR1 are
pin shared with PC1, PC2 respectively.
PC0/BZ
I/O or O Can be software optioned as a bidirectional input/output or as a PFD output.
OSCI
OSCO
I
O
OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock
RESET
I
Schmitt trigger reset input, active low
NC
¾
No connection
DVDD1
¾
Positive digital power supply
DVSS1
¾
Negative digital power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
3.3
3.6
5.5
V
VDD
Operating Voltage
3.3V
IDD1
Operating Current
3.3V
No load, fSYS=12MHz
ADC on, DAC on
¾
9
¾
mA
IDD2
Operating Current
3.3V
No load, fSYS=12MHz
ADC off, DAC off
¾
5
¾
mA
ISTB
Standby Current
3.3V No load, system HALT
¾
155
¾
mA
V
VIL1
Input Low Voltage for I/O Ports
3.3V
¾
0
¾
0.3VDD
VIH1
Input High Voltage for I/O Ports
3.3V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RESET)
3.3V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RESET)
3.3V
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Sink Current
3.3V VOL=0.1VDD
¾
3
¾
mA
IOH
I/O Port Source Current
3.3V VOH=0.7VDD
¾
-2
¾
mA
RPH
Pull-high Resistance
3.3V
¾
110
80
40
kW
VLVR
Low Voltage Reset
3.3V
¾
2.7
3
3.3
V
Rev. 1.10
4
July 25, 2007
HT82A850R
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
DAC+Power Amp
Test condition: Measurement bandwidth 20Hz to 20kHz, fS= 48kHz. Line output series capacitor with 220mF.
THD+N
SNRDA
DR
POUT
THD+NNote
Signal to Noise RatioNote
Dynamic Range
Output Power
4W load
¾
-30
¾
8W load
¾
-35
¾
4W load
¾
81
¾
8W load
¾
82
¾
4W load
¾
87
¾
8W load
¾
88
¾
4W load, THD=10%
¾
400
¾
8W load, THD=10%
¾
200
¾
5V
5V
5V
5V
dB
dB
dB
mW/ch
PCM ADC
SNRAD
Signal to Noise Ratio
3.3V
¾
¾
77
¾
dB
VAG
Reference Voltage
3.3V
¾
¾
1.12
¾
V
VPEAK
Peak Single Frequency Tone
Amplitude without Clipping
3.3V
¾
¾
1.575
¾
VPK
Note: Sine wave input at 1kHz, -6dB
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock (Crystal OSC)
3.3V
¾
0.4
¾
12
MHz
tWDTOSC
Watchdog Oscillator Period
3.3V
¾
¾
100
¾
ms
tRES
RESET Input Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: tSYS=1/fSYS
Rev. 1.10
5
July 25, 2007
HT82A850R
Functional Description
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Execution Flow
The microcontroller system clock is sourced from a crystal oscillator. The system clock is internally divided into
four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, a conditional skip
execution, loading to the PCL register, performing a
subroutine call or returning from a subroutine, an initial
reset, an internal interrupt, external interrupt or return
from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the next instruction is executed.
The program counter, PC, controls the sequence in
which the instructions stored in the program memory are
executed. Its contents specify the full program memory
range.
The lower byte of the program counter, PCL, is a readable and writeable register. Moving data into the PCL
performs a short jump. The destination will be within the
current program memory page.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Play Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Serial Interface Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Record Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.10
@[email protected]: PCL bits
6
July 25, 2007
HT82A850R
· Location 014H
Program Memory
This location is reserved for when 8 bits of data have
been received or transmitted successful from the serial interface. If the related interrupts are enabled, and
the stack is not full, the program will jump to this location and begin execution.
The program memory is used to store the executable
program instructions. It also contains data, table, and interrupt entries, and is organized into 4096´15 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
· Location 018H
This location is reserved for the record interrupt service program. If the record data valid, the interrupt is
enabled and the stack is not full, the program will jump
to this location and begin execution.
· Location 000H
This location is reserved for program initialisation. After a device reset, the program always begins execution at location 000H.
· Table location
· Location 008H
Any location in the program memory can be used as a
look-up table. There are three method to read the program memory data. The first method uses the
TABRDC instruction to transfer the contents of the
current page lower-order byte to the specified data
memory, and the current page higher-order byte to the
TBLH register. The second method uses the TABRDL
instruction to transfer the contents of the last page
lower-order byte to the specified data memory, and
the last page higher-order byte to the TBLH register.
The third method uses the TABRDC instruction together with the TBLP and TBHP pointers to transfer
the contents of the lower order byte at the specified
address to the specified data memory, and the higher
order byte at the specified address to the TBLH register. Before accessing the table data, the address to be
read must be placed in the table pointer registers,
TBLP and TBHP. Note that if the configuration option
TBHP is disabled, then the value in TBHP has no effect. Only the destination of the lower-order byte in the
table is well-defined, the other bits of the table word
are transferred to the lower portion of TBLH, and the
remaining 1-bit word is read as ²0².The Table
Higher-order byte register, TBLH, is read only. The
TBLH register is read only and cannot be restored. If
the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
In such cases errors can occur. Therefore, using the
table read instruction in the main routine and the ISR
simultaneously should be avoided. However, if the table read instruction has to be used in both the main
routine and the ISR, the interrupt should be disabled
This location is reserved for the Timer/Event Counter
0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
will jump to this location and begin execution.
· Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
will jump to this location and begin execution.
· Location 010H
This location is reserved for the play interrupt service
program. If the play data is valid, and the interrupt is
enabled and the stack is not full, the program will jump
to this location and begin execution.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
R e s e rv e d
0 0 8 H
T im
In
T im
In
0 0 C H
0 1 0 H
0 1 4 H
v e
p t
v e
p t
n t
S u
n t
S u
C o
b r
C o
b r
u n
o u
u n
o u
te
tin
te
tin
r 0
e
r 1
e
P ro g ra m
M e m o ry
P la y In te r r u p t S u b r o u tin e
S e r ia l In te r fa c e In te r r u p t S u b r o u tin e
0 1 8 H
R e c o r d In te r r u p t S u b r o u tin e
0 1 B H
0 2 0 H
F F F H
e r/E
te rru
e r/E
te rru
1 5 B its
N o te : n ra n g e s fro m 0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
@[email protected]: Table pointer bits
Rev. 1.10
P11~P8: Current program counter bits when TBHP is disabled
TBHP register bit3~bit0 when TBHP is enabled
7
July 25, 2007
HT82A850R
0 0 H
prior to the table read instruction. It should not be
re-enabled until TBLH has been backed up.
All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending upon requirements.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organised into 16 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer, SP, which is neither readable nor
writeable. At a subroutine call or interrupt acknowledge
signal, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction, RET or RETI,
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, using RET or RETI, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more
easily. In a similar case, if the stack is full and a ²CALL²
is subsequently executed, a stack overflow will occur
and the first entry will be lost. Only the most recent 16 return addresses are stored.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
1 A H
1 B H
1 C H
U S V C
S p e c ia l P u r p o s e
D a ta M e m o ry
1 D H
1 E H
IN T C 1
1 F H
T B H P
2 0 H
2 1 H
2 2 H
U C C
2 3 H
Data Memory
2 7 H
The data memory is divided into two functional groups.
These are the special function registers and the general
purpose data memory in Bank0 and Bank1: 384´8 bits.
Most are read/write, but some are read only. The special
function registers are overlapped in all banks.
2 8 H
2 C H
2 D H
D A C _ L IM IT _ L
2 E H
D A C _ L IM IT _ H
Any unused space before 40H is reserved for future expanded usage and if read will return a value of ²00H².
The general purpose data memory, addressed from 40H
to FFH, is used for data and control information under instruction commands.
2 F H
D A C _ W R
3 0 H
P G A _ C T R L
All data memory areas can handle arithmetic, logical, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by ²SET [m].i² and ²CLR
[m].i². They are also indirectly accessible through the
memory pointer registers, MP0 or MP1.
3 5 H
S B C R
3 6 H
S B D R
3 1 H
P F D C
3 2 H
P F D D
3 3 H
3 4 H
M O D E _ C T R L
3 7 H
3 D H
3 E H
R E C O R D _ D A T A _ L
3 F H
4 0 H
R E C O R D _ D A T A _ H
F F H
G e n
D a
(1
B a
e ra
ta
9 2
n k
l P
M e
B y
0 /B
u rp o s e
m o ry
te s )
a n k 1
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.10
8
July 25, 2007
HT82A850R
Indirect Addressing Register
Status Register - STATUS
Locations 00H and 02H are the indirect addressing registers, however they are not physically implemented.
Any read/write operation to [00H] or [02H] will access
the data memory pointed to by MP0 and MP1. Reading
location 00H or 02H indirectly will return a result of 00H.
Writing indirectly results in no operation.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended.
Data transfer between two indirect addressing registers
is not supported. The memory pointer registers, MP0
and MP1, are 8-bit registers which are used to access
the Data Memory in combination with indirect addressing registers.
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a
system power-up.
Bank Pointer
The bank pointer is used to select the required Data
Memory bank. If Data Memory bank 0 is to be selected,
then a ²0² should be loaded into the BP register. Data
Memory locations before 40H in any bank are overlapped.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
The device provides an internal timer/event counter interrupt, play/record data valid interrupt and a serial interface interrupt. The Interrupt Control Register0, INTC0,
and the interrupt control register1, INTC1:1EH, both
contain the interrupt control bits that are used to set the
enable/disable status and interrupt request flags.
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
· Rotation - RL, RR, RLC, RRC
· Increment and Decrement - INC, DEC
Once an interrupt subroutine is serviced, other interrupts are all blocked, as the EMI bit is cleared automatically, preventing further interrupt nesting. Other interrupt
· Branch decision - SZ, SNZ, SIZ, SDZ ....
The ALU not only saves the results of a data operation
but also changes the status register.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.10
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July 25, 2007
HT82A850R
related interrupt request flag, T1F, will be reset and the
EMI bit cleared to disable further interrupts.
requests may take place during this interval, but only the
interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC0 or of INTC1
may be set in order to allow interrupt nesting. Once the
stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the
Stack Pointer is decremented. If immediate service is
desired, the stack should be prevented from becoming
full.
The play interrupt is initialised by setting the play interrupt request flag, bit 4 of INTC1, caused by a valid play
interrupt. When the interrupt is enabled, the stack is not
full and PLAYF is set, a subroutine call to location 10H
will occur. The related interrupt request flag, PLAYF, will
be reset and the EMI bit cleared to disable further interrupts. If PLAY_MODE, bit 3 of the MODE_CTRL register, is set to ²1², the play interrupt frequency will change
to 8kHz, otherwise the interrupt frequency is 48 kHz.
The firmware will write 16-bit unsigned data to the DAC
when a play interrupt occurs.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a
subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, the contents should
be saved in advance.
The serial interface interrupt is indicated by the interrupt
flag, SIF; bit 5 of INTC1, that is generated by the reception or transfer of a complete 8-bits of data between the
HT82A850R and the external device. The serial interface interrupt is controlled by setting the Serial interface
interrupt control bit, ESII; bit 1 of INTC1. After the interrupt is enabled, by setting SBEN; bit 4 of SBCR, and the
stack is not full and the SIF bit is set, a subroutine call to
location 14H occurs.
The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag, bit 5 of INTC0, caused by a timer 0 overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag, T0F, will be reset and the EMI bit cleared to disable further interrupts.
The record interrupt is initialised by setting the record interrupt request flag, bit 6 of INTC1, caused by a record
data valid. When the interrupt is enabled, the stack is not
full and RECF is set, a subroutine call to location 18H
will occur. The related interrupt request flag, RECF, will
be reset and the EMI bit cleared to disable further interrupts. If the ADC is powered down, AD_ENB =1, the record interrupt will be disabled.
The internal Timer/Even Counter 1 interrupt is initialised
by setting the Timer/Event Counter 1 interrupt request
flag, bit 6 of INTC0, caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and the T1F
is set, a subroutine call to location 0CH will occur. The
Bit No.
Label
0
EMI
Function
1, 4, 7
¾
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Controls the master (global) interrupt (1=enabled; 0=disabled)
Unused bit, read as ²0²
INTC 0 (0BH) Register
Bit No.
Label
0
EPLAYI
1
ESII
2
ERECI
3, 7
¾
4
PLAYF
5
SIF
6
RECF
Function
Play interrupt (1= enabled; 0= disabled)
Control Serial interface interrupt (1= enabled; 0= disabled)
Record interrupt (1= enabled; 0= disabled)
Unused bit, read as ²0²
Play interrupt request flag (1= active; 0= inactive)
Serial interface interrupt request flag (1= active; 0= inactive)
Record interrupt request flag (1= active; 0= inactive)
INTC 1 (1EH) Register
Rev. 1.10
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July 25, 2007
HT82A850R
A WDT oscillator is also contained within the device.
This is a free running fully integrated RC oscillator
requiring no external components. Even if the system
enters the power down mode, where the system clock is
stopped, the WDT oscillator continues to run. The WDT
oscillator can be disabled by a configuration option to
conserve power.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction should be executed. A RETI instruction will
set the EMI bit to enable an interrupt service, but a RET
instruction will not.
Watchdog Timer - WDT
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
Reserved
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Play Interrupt
4
10H
Serial Interface Interrupt
5
14H
Record Interrupt
6
18H
The WDT clock source is implemented by its own dedicated internal RC oscillator (WDT oscillator) or by using
the instruction clock, which is the system clock/4. The
WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location
with unpredictable results. The WDT can be disabled
using a configuration option. Note that if the WDT is disabled, all executions of instructions related to the WDT
will result in no operation.
When the WDT clock source is selected, it will be first divided by 256 (8-stage) to obtain a nominal time-out period. By using this WDT prescaler, longer time-out
periods can be implemented. This is achieved by writing
data to the the WS2, WS1, WS0 bits.
The WDT OSC period has a typical value of 65ms. This
time-out period may vary with temperature, VDD and
process variations. The WDT OSC keeps running in any
operational mode.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except
when the device is in the Power-down mode. Here the
WDT stops counting and loses its protecting function. In
this situation the device can only be re-started by external logic. The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to
indicate some specified status.
Oscillator Configuration
O S C I
The WDT overflow under normal operation initialises a
²chip reset² and sets the status bit ²TO². In the
Power-down mode, the overflow initialises a ²warm reset², where only the PC and SP are reset to zero. To
clear the contents of the WDT, there are three methods
that can be used, i.e., external reset (a low level on the
RESET pin), a software instruction, and a ²HALT² instruction. There are two types of software instructions;
²CLR WDT² and the other set ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
options ²CLR WDT² times selection option. If the ²CLR
WDT² is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears the WDT.
In the case that ²CLR WDT1² and ²CLR WDT2² are
chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out.
O S C O
C r y s ta l O s c illa to r
System Oscillator
An internal oscillator circuit is integrated within the
microcontroller to implement the system clock. When
the device enters the Power-down mode the system oscillator will stop running and external signals will be
ignored to conserve power.
A crystal across OSCI and OSCO is required to provide
the feedback and phase shift required for the oscillator.
No other external components are required. Instead of a
crystal, a resonator can also be connected between
OSCI and OSCO to obtain the correct frequency reference, however two external capacitors between the
OSCI, OSCO pins and ground are required.
Rev. 1.10
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July 25, 2007
HT82A850R
Bit No.
Label
0
1
2
WS0
WS1
WS2
3
¾
7~4
T3~T0
Function
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, division ratio = 1:1
Bit 2,1,0 = 001, division ratio = 1:2
Bit 2,1,0 = 010, division ratio = 1:4
Bit 2,1,0 = 011, division ratio = 1:8
Bit 2,1,0 = 100, division ratio = 1:16
Bit 2,1,0 = 101, division ratio = 1:32
Bit 2,1,0 = 110, division ratio = 1:64
Bit 2,1,0 = 111, division ratio = 1:128
Unused bit, read as ²0²
Test mode setting bits
(T3, T2, T1, T0)=(0, 1, 0, 1), enter DAC write mode. Otherwise normal operation.
WDTS (09H) Register
W D T O S C
S y s te m C lo c k /4
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
W S 0 ~ W S 2
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
A port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin in
port A can be independently selected to wake-up the device using configuration options. After awakening from
an I/O port stimulus, the program will resume execution
at the next instruction. If the device is awakened from an
interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack
is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not
full, the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock periods) to resume normal operation, i.e., a dummy period is inserted. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
Power Down Operation
The Power-down mode is entered by the execution of a
²HALT² instruction and results in the following:
· The system oscillator will be turned off but the WDT
oscillator keeps running if the internal WDT oscillator
is selected.
· The contents of the on-chip data memory and registers remain unchanged.
· The WDT and WDT prescaler will be cleared and will
start counting again if the WDT clock is sourced from
the internal WDT oscillator.
· All of the I/O ports remain in their original condition.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the cause for the device reset can be determined. The PDF flag is cleared by a system power-up
or by executing the ²CLR WDT² instruction and is set
when executing the ²HALT² instruction. The TO flag is
set if the WDT time-out occurs, and causes a wake-up
that only resets the program counter and SP; the others
remain in their original status.
Rev. 1.10
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
The ADC, DAC and PA will all be powered down when in
the HALT mode.
12
July 25, 2007
HT82A850R
V
Reset
D D
There are four ways in which a reset can occur:
· RES reset during normal operation
R E S E T
· RES reset when in the Power-down mode
· WDT time-out reset during normal operation
· USB reset
The WDT time-out when in the Power-down mode is different from other device reset conditions, since it can
perform a ²warm reset² that resets only the program
counter and stack pointer, leaving the other circuits in
their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to
their ²initial condition² when the reset conditions are
met. By examining the PDF and TO flags, the program
can distinguish between different ²device resets².
TO PDF
Reset Circuit
V D D
R E S
tS
S S T T im e - o u t
C h ip
R e s e t
RESET Conditions
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
1
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
S T
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
R E S E T
Note: ²u² stands for ²unchanged²
O S C I
To guarantee that the system oscillator is started and
stabilised, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
the system awakes from the Power-down mode.
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from the
Power-down mode will enable the SST delay.
The status of the device after a reset is shown below.
Program Counter
000H
Interrupt
Disabled
WDT
Cleared. After a master reset,
WDT begins counting
Timer/Event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
Rev. 1.10
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July 25, 2007
HT82A850R
The registers status are summarised in the following table.
Register
MP0
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT Time-Out
(HALT)*
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
TBLP
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
USVC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC1
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
DAC_LIMIT_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAC_LIMIT_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAC_WR
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PGA_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PFDC
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PFDD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MODE_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0uuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECOED_
DATA_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
RECOED_
DATA_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note: ²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
²_² stands for ²undefined²
Rev. 1.10
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July 25, 2007
HT82A850R
quest flag (T0F; bit 5 of INTC0, or T1F; bit 6 of INTC0).
In the pulse width measurement mode with the values of
the TON and TE bits equal to 1, after the TMR0 or TMR1
pin has received a transient from low to high, or high to
low if the TE bit is ²0², it will start counting until the TMR0
or TMR1 pin returns to its original level and resets the
TON bit. The measured result remains in the timer/event
counter even if the activated transient occurs again.
Therefore, only 1-cycle measurement is made. Not until
the TON bit is again set can the cycle measurement
re-function. In this operational mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the
other two modes, i.e., event and timer modes.
Timer/Event Counter
Two timer/event counters are implemented in the
microcontroller. Each timer contains a 16-bit programmable count-up counter whose clock may be sourced
from an external or internal clock source. The internal
clock source comes from fSYS/4. The external clock input allows external events to be counted, time intervals
or pulse widths to be measured, or to generate an accurate time base. There are three registers related to
Timer/Event Counter 0, TMR0H, TMR0L and TMR0C,
and another three related to Timer/Event Counter 1,
TMR1H, TMR1L and TMR1C. When writing data to the
TMR0L and TMR1L registers, note that the data will only
be written into a lower-order byte buffer. The data will
not be actually written into the TMR0L and TMR1L registers until a write operation to the TMR0H and TMR1H
registers is implemented. Reading the TMR0L and
TMR1L registers will read the contents of the lower-order byte buffer. The TMR0C and TMR1C registers are
the Timer/Event Counter control registers, which define
the operating mode, the count enable or disable and the
active edge.
To enable a count operation, the Timer ON bit (TON; bit
4 of TMR0C or TMR1C) should be set to 1. In the pulse
width measurement mode, TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON bit can only be reset by
instructions. A Timer/Event Counter overflow is one of
the wake-up sources. No matter what the operational
mode is, writing a 0 to ET0I or ET1I disables the related
interrupt service.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is sourced from the
external TMR0 or TMR1 pin. The timer mode functions
as a normal timer with the clock source coming from the
internal clock. Finally, the pulse width measurement
mode can be used to count the high level or low level duration of an external signal on pins TMR0 or TMR1,
whose counting is based on the internal clock source.
If the timer/event counter is turned OFF, writing data to
the timer/event counter preload register will also reload
the data into the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter keeps operating until an overflow occurs.
In the event count or timer mode, the timer/event counter starts counting from the current contents in the
timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
When the timer/event counter is read, the clock is
blocked to avoid errors, which may result in a counting
error. Blocking of the clock should be taken into account
by the programmer.
Bit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter
In Event counter mode (TM1, TM0)=(0, 1):
1=count on falling edge;
0=count on rising edge
In Pulse width measurement mode (TM1, TM0)=(1, 1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
Function
TMR0C (0EH), TMR1C (11H) Register
Rev. 1.10
15
July 25, 2007
HT82A850R
fS
f IN
Y S /4
D a ta B u s
T
T M 1
T M 0
T M R 0 /1
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 0 /1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
O v e r flo w
to In te rru p t
Timer/Event Counter 0/1
After a device reset, the input/output lines will default to
input high levels or a floating state, depending on the
pull-high configuration options. Each bit of these input/output latches can be set or cleared using the ²SET
[m].i² and ²CLR [m].i² (m=12H, 14H or 16H) instructions.
Input/Output Ports
There are 24 bidirectional input/output lines in the
microcontroller, labeled from PA to PC. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until
the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC or
PCC) to control the input/output configuration. With this
control register, either a CMOS output or Schmitt trigger
input with or without pull-high resistor structures can be
reconfigured dynamically under software control. To
function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is
²1² the input will read the pad state. If the control register
bit is ²0² the contents of the latches will move to the internal bus. The latter is possible in the
²Read-modify-write² instruction. For output function,
CMOS configurations can be selected.
Each line of port A has the capability of waking-up the
device.
Low Voltage Reset - LVR
The LVR function is enabled or disabled using a configuration option. The LVR voltage is 3.0V.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR such as when changing a battery, the LVR
will automatically reset the device internally.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
P A
P B
P C
P C
P C
P C
P C
P C
P C
P C
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
B
T M R
T M R
S D
S
S C
S C
(P A
Z fo
0 fo
1 fo
O
D I
S
K
fo
fo
fo
fo
r
r
r
r
r
r
r
o n
P
P
P
P
P
P
P
P
D D
C o n tr o l B it P u ll- h ig h
O p tio n
Q
D
U
0 ~ P
0 ~ P
0 /B
1 /T
2 /T
3
4 /S
5 /S
6 /S
7 /S
A 7
B 7
Z
M R 0
M R 1
D O
D I
C S
C K
X
ly )
C 0
C 1
C 2
C 3
C 4
C 5
C 6
C 7
C o n fig u r a tio n O p tio n
Input/Output Ports
Rev. 1.10
16
July 25, 2007
HT82A850R
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in this condition for a time greater than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and will not perform a reset function.
· The LVR uses an ²OR² function with the external RESET signal to perform a device reset.
System Clock Selection
This register consists of system clock selection (SYSCLK)
Bit No.
Label
R/W
Reset
0~2
¾
¾
0
Reserved
0
Defines the MCU system clock - sourced from the external OSC or
from the PLL output - 16MHz clock.
0: system clock sourced from OSC
1: system clock sourced from the PLL output - 16MHz
0
Used to specify the system clock oscillator frequency used by MCU.
If a 6MHz crystal oscillator or resonator is used, this bit should be set
to ²1².
If a 12MHz crystal oscillator or resonator is used. this bit should be
cleared to ²0².
fSYS16MHz
5
6
SYSCLK
R/W
R/W
Functions
UCC (22H) Register
The speaker output volume and speaker mute/un-mute are controlled by the Digital Volume Control register. The range
of volume is set from 6 dB to -32 dB using software.
· Speaker mute control:
MUTE= 0: Mute speaker output.
MUTE= 1: Normal.
Bit No.
Label
R/W
Power-on
0~6
USVC0~
USVC6
Functions
R/W
0
Volume Control Bit 0~Bit 6
7
MUTE
R/W
0
Mute control, low active
Digital Volume Control (1CH) Register
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
6
000_1100
-2
111_1100
-10
110_1100
-24
101_1100
5.5
000_1011
-2.5
111_1011
-10.5
110_1011
-25
101_1011
5
000_1010
-3
111_1010
-11
110_1010
-26
101_1010
4.5
000_1001
-3.5
111_1001
-11.5
110_1001
-27
101_1001
4
000_1000
-4
111_1000
-12
110_1000
-28
101_1000
3.5
000_0111
-4.5
111_0111
-13
110_0111
-29
101_0111
3
000_0110
-5
111_0110
-14
110_0110
-30
101_0110
2.5
000_0101
-5.5
111_0101
-15
110_0101
-31
101_0101
2
000_0100
-6
111_0100
-16
110_0100
-32
101_0100
1.5
000_0011
-6.5
111_0011
-17
110_0011
¾
¾
1
000_0010
-7
111_0010
-18
110_0010
¾
¾
0.5
000_0001
-7.5
111_0001
-19
110_0001
¾
¾
0
000_0000
-8
111_0000
-20
110_0000
¾
¾
-0.5
111_1111
-8.5
110_1111
-21
101_1111
¾
¾
-1
111_1110
-9
110_1110
-22
101_1110
¾
¾
-1.5
111_1101
-9.5
110_1101
-23
101_1101
¾
¾
Speaker Volume Control Table
Rev. 1.10
17
July 25, 2007
HT82A850R
The DAC_Limit_L and DAC_Limit_H registers are used to define the 16-bit DAC output limit. DAC_Limit_L and
DAC_Limit_H have unsigned values. If the 16-bit data from the Host exceeds the range defined by the DAC_Limit_L
and DAC_Limit_H, the output digital code to the DAC will be clamped.
DAC_Limit_L
DAC output limit low byte
DAC_Limit_H
DAC output limit high byte
Example to set the DAC output limit value:
;----------------------------------------------------------; Set DAC Limit Value=FF00H
;----------------------------------------------------------clr
[02DH]
; Set DAC Limit low byte=00H
set
[02EH]
; Set DAC Limit high byte=FFH
;----------------------------------------------------------In order to prevent speaker popping sounds, the power amplifier should be setup to output a value of VDD/2, implemented by sending 8000H to the DAC, during the initial power on state. A falling edge on the DAC_WR_TRIG bit (bit 3
of DAC_WR register), will write the values in the DAC_Limit_L and DAC_Limit_H registers into the DAC.
Bit No.
Label
R/W
Power-on
0~2, 4~7
¾
R
0
Undefined bit, read as ²0².
Functions
3
DAC_WR_TRIG
R/W
0
DAC write trigger bit
DAC_WR (2FH) Register
Example to avoid speaker popping noise:
System_Initial:
;----------------------------------------------------------; Avoid Pop Noise
;----------------------------------------------------------mov
a,WDTS
mov
FIFO_TEMP,a
;Save WDTS value
mov
a,01010000b
andm
a,WDTS
mov
a,01010000b
orm
a,WDTS
;Enter DAC Write Data mode, high nibble of WDTS=0101b
clr
[02DH]
;Set DAC data low byte=00H
mov
a,80H
mov
[02EH],a
;Set DAC data high byte=80H
nop
;Write 8000H to DAC
set
[02FH].3
nop
clr
[02FH].3
nop
;----------------------------------------------------------mov
a,FIFO_TEMP
;Restore WDTS value
mov
WDTS,a
;Quit DAC Write Data mode
;----------------------------------------------------------Note: When in the DAC write data mode(high nibble of WDTS register is 0101b), the DAC_Limit_L and DAC_Limit_H
registers will be used as the 16-bit DAC input data registers during the falling edge of the DAC_WR_TRIG. Otherwise, these two registers are used to define the 16-bit DAC output limits.
Rev. 1.10
18
July 25, 2007
HT82A850R
Digital PGA
Bit No.
Label
Functions
Digital PGA control bits with range 0~19.5 dB. The PGA is a digital amplifier used to
PGA0~PGA5 amplify the 16-bit data that comes from the PCM ADC. The PGA value versus gain
relationship is shown in the following table.
0~5
6
ADC_RESET=²1²: PCM ADC at reset condition
ADC_RESET=²0²: PCM ADC during normal operation - default=0
ADC_RESET The following conditions will reset the ADC:
- MCU Reset
- Set ADC_RESET to ²1² using the program
7
MUTE_MKB
Microphone mute Control:
MUTE_MKB =0: Mute microphone input.
MUTE_MKB =1: Normal.
PGA_CTRL Register
PGA_CRTL Value (PGA5~PGA0)
Gain (dB)
000000
»0
000001
» 0.5
:
:
:
:
100111
» 19.5
101000
» 19.5
:
:
:
:
111111
» 19.5
PFD Control
Label
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFDC
0
PRES1
PRES0
PFDEN
0
0
PFD_IO
SELW
PFDD
PFDD7
PFDD6
PFDD5
PFDD4
PFDD3
PFDD2
PFDD1
PFDD0
PFDC (31H), PFDD (32H) Register
A Programmable Frequency Divider, PFD, is implemented within the HT82A850R. It is composed of two sections, a
prescaler and a general counter.
The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general
counter is programmed by an 8-bit register known as PFDD.
The PFDD is write inhibited while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled. When
the generator is disabled, the PFDD is cleared by hardware.
PFD prescaler selection:
PRES1
PRES0
0
0
PFD frequency source ¸ 1
0
1
PFD frequency source ¸ 2
1
0
PFD frequency source ¸ 4
1
1
PFD frequency source ¸ 8
Rev. 1.10
Prescaler Output
19
July 25, 2007
HT82A850R
The bit PFD_IO is used to determine whether PC0 is a general purpose I/O pin or a PFD output.
PFD_IO=²1²
PC0 is PFD output
PFD_IO=²0²
PC0 is a general IO pin port - default=0
The SELW bit is used to control the power amplifier input source. The software should set SELW =²1² when the power
amplifier signal is sourced from MUSIC_IN, otherwise the speaker output is the USB Audio data.
SELW=²1²
The power amplifier signal is sourced from the MUSIC_IN pin
SELW=²0²
The power amplifier signal is sourced from the USB Audio data (Default=0)
fS
Y S
4 - S ta g e P r e s c a le r
(1 /1 6 )
/4
P F D
F re q u e n c y
P r e s c a le r
O u tp u t
P r e s c a le r
P F D
O u tp u t
P F D D
P F D E N
P R E S 1 , P R E S 0
N o te : P F D
O u tp u t F re q u e n c y =
P r e s c a le r O u tp u t
2 ´ (N + 1 )
, w h e re N
= th e v a lu e o f th e P F D
d a ta
SPI
The serial interface function is similar to the Motorola SPI, where four basic signals are included. These are the SDI
(Serial Data Input), SDO (Serial Data Output), SCK (serial clock) and SCS (slave select pin).
S C S
S C K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Timing
Label
SBCR
Default
SBDR
Default
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Serial Bus
Data Register
Note: ²U² unchanged
Rev. 1.10
20
July 25, 2007
HT82A850R
Two registers, SBCR and SBDR, are provided for serial interface control, status and data storage.
· SBCR: Serial bus control register
¨
¨
Bit7 (CKS): clock source selection: fSIO = fSYS/2, select as 0; fSIO = fSYS, select as 1
Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
-
M1, M0=
00: Master mode, baud rate = fSIO
01: Master mode, baud rate = fSIO/4
10: Master mode, baud rate = fSIO/16
11: Slave mode
¨
Bit4 (SBEN): Serial bus enable/disable (1/0)
-
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS =0 (SCK=²0²) and wait to write data to SBDR (TXRX buffer)
Master mode: write data to SBDR (TXRX buffer) ® start transmission/reception automatically
Master mode: when data has been transferred ® set TRF
Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in the TXRX buffer is shifted-out and
data on SDI is shifted-in.
-
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports.
Label
Functions
SBEN=1
PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1).
SBEN=0
PC4~PC7 are general purpose I/O Port pins - default
Note: 1. If SBEN=²1², the pull-high resistors on PC4~PC7 will be disabled. When this happens external pull-high
resistors should be added to the SPI related pins if necessary (EX: pin SCS).
2. If CSEN=²0², the SCS pin will enter a floating state.
¨
Bit3 (MLS): MSB or LSB (1/0) shift first control bit
¨
Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating
¨
Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when the data is transferring
® writing will be ignored if data is written to SBDR (TXRX buffer) when the data is transferring
WCOL will be set by hardware and cleared by software.
¨
Bit 0 (TRF): data transferred or data received ® used to generate an interrupt
Note: data reception is still operational when the MCU enters the Power-down mode
· SBDR: Serial bus data register
Data written to SBDR ® write data to the TXRX buffer only
Data read from SBDR ® read from SBDR only
¨
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing to SBDR
Master clock sending started by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
Rev. 1.10
21
July 25, 2007
HT82A850R
· Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Serial Interface Operation:
Label
Functions
· Select CKS and select M1,M0 = 00, 01, 10
· Select CSEN, MLS (same as slave)
· Set SBEN
· Writing data to SBDR ® data is stored in the TXRX buffer ® output CLK (and SCS) signals ® go
Master
·
·
·
·
·
to step 5 ® (SIO internal operation ® data stored in the TXRX buffer, and the SDI data is shifted
into the TXRX buffer ® data transferred, data in the TXRX buffer is latched into SBDR)
Check WCOL; WCOL = 1 ® clear WCOL and go to step 4; WCOL = 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
· CKS don¢t care and select M1, M0 = 11
· Select CSEN, MLS (same as master)
· Set SBEN
· Writing data to SBDR ® data is store in the TXRX buffer ® waiting for master clock signal (and
Slavehans
SCS): CLK ® go to step 5 ® (SIO internal operations ® CLK (SCS) received ® output data in
TXRX buffer and SDI data is shifted into the TXRX buffer ® data transferred, data in the TXRX
buffer is latched into SBDR)
· Check WCOL; WCOL = 1 ® clear WCOL, go to step 4; WCOL = 0 ® go to step 6
· Check TRF or waiting for SBI (serial bus interrupt)
· Read data from SBDR
· Clear TRF
· Go to step 4
· WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. The WCOL function can be enabled/disabled by a software option (SIO_WCOL bit of MODE_CTRL
register). WCOL is set by SIO and cleared by the user.
Data transmission and reception will continue to operated when the MCU enters the power-down mode.
CPOL is used to select the clock polarity of CLK and is a software option (SIO_CPOL bit of MODE_CTRL register).
· MLS: MSB or LSB first selection
· CSEN: chip select function enable/disable, CSEN = 1 ® SCS signal function is active. The master should output a
SCS signal before the CLK signal and slave data transferring should be disabled(enabled) before(after) SCS signal
received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
· CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled,
software CSEN function can be used.
· SBEN = 1 ® serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
· SBEN = 0 ® serial bus disable; SCS = SDI = SDO = CLK = floating
· TRF is set by SIO and cleared by the user. When the data is transferring (transmission and reception) is complete,
TRF is set to generate SBI (serial bus interrupt).
Rev. 1.10
22
July 25, 2007
HT82A850R
S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
S C S
C L K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
C L K
SIO Timing
Label
SBCR
Default
SBDR
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Serial Bus
Data Register
Default
D a ta B u s
S B D R
D 7
( R e c e iv e d D a ta R e g is te r )
D 6
D 5
D 4
D 3
D 2
D 1
D 0
M
U
S D O
X
M L S
A n d , S ta rt
E N
S C K
M
U
X
C 0
A n d , S ta rt
C 1
U
X
S D I
T R F
C 2
A N D
C lo c k
P o la r ity
M a s te r o r
S la v e
S B E N
S D O
S B E N
M
In te rn a l B a u d
R a te C lo c k
B u ffe r
W C O L F la g
In te r n a l B u s y F la g
W r ite S B D R
S B E N
W r ite S B D R E n a b le /D is a b le
W r ite S B D R
A n d , S ta rt
S C S
E N
M a s te r o r S la v e
S B E N
C S E N
Block Diagram of SIO
Rev. 1.10
23
July 25, 2007
HT82A850R
Label
Functions
WCOL
Set by SIO cleared by users
CESN
Enable or disable device selection function pin
Master mode: 1/0=with/without SCS output control
Slave mode: 1/0= with/without SCS input control
SBEN
Enable or disable serial bus (0= initialize all status flags)
When SBEN=0, all status flags should be initialized
When SBEN=0, all SIO related function pins should stay in a floating state
TRF
1= data transmitted or received
0= data is transmitting or still not received
If the clock polarity set to rising edge (SIO_CPOL=1), the serial clock timing will follow CLK, otherwise (SIO_CPOL=0)
CLK is the serial clock timing.
Mode Control
The MODE_CTRL register is used to control the DAC and ADC operational mode and the SPI function.
Bit No.
Label
0
DA_L_ENB
DAC enable/disable control (left channel)
1= DAC Left Channel disable
0= DAC Left Channel enable (default)
1
DA_R_ENB
DAC enable/disable control (right channel)
1= DAC Right Channel disable
0= DAC Right Channel enable (default)
2
AD_ENB
3
Functions
ADC enable/disable control
1= ADC power down
0= ADC power on (default)
DAC play mode control
PLAY_MODE 1= 8kHz/16-bit
0= 48kHz/16-bit (default)
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (default)
7
¾
Undefined bit, read as ²0²
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
UCC.@UCC_SYSCLK
set
SIO_CSEN
clr
SIO_CPOL
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;-------------clr
CKS
clr
TRF
clr
TRF_INT
set
MLS
set
CSEN
set
SBEN
Rev. 1.10
;12MHz SYSCLK
;SPI chip select function enable
;falling edge change data
;fSIO=fSYS/2
;clear TRF flag
;clear interrupt SPI flag
;MSB shift first
;Chip select enable
;SPI enable, SCS will go low
24
July 25, 2007
HT82A850R
if POLLING_MODE
clr
ESII
;SPI interrupt disable
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF
jmp
$0
clr
TRF
else
set
ESII
;SPI Interrupt Enable
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF_INT
;set at SPI Interrupt
jmp
$0
clr
TRF_INT
endif
Record Data
The record interrupt will be activated when the record data is valid in the RECORD_DATA registers. The RECORD_DATA registers will latch data until next interrupt occurs. The RECORD_DATA is 2¢s complement value
(8000H~7FFFH).
The update rate of the RECORD_DATA is 8kHz. All these registers (3EH~3FH) are read only.
Address
Label
Bit 7
Bit 6
Bit 5
Bit 4
3EH
RECORD_DATA_L
R_D7
R_D6
R_D5
R_D4
3FH
RECORD_DATA_H
R_D15
R_D14
R_D13
R_D12
Bit 3
Bit 2
Bit 1
Bit 0
R_D3
R_D2
R_D1
R_D0
R_D11
R_D10
R_D9
R_D8
Configuration Options
The following table shows the microcontroller configuration options . All of the OTP options must be defined to ensure
proper system functioning.
No.
Option
1
PA0~PA7 pull-high resistor enabled or disabled - bit option
2
LVR enable or disable
3
WDT enable or disable
4
WDT clock source: fSYS/4 or WDTOSC
5
CLRWDT instruction(s): 1 or 2
6
PA0~PA7 wake-up enabled or disabled - bit option
7
PB0~PB7 pull-high resistor enabled or disable - bit option
8
PC0~PC7 pull-high resistor enabled or disabled - nibble option
9
TBHP enable or disable - default disable
Rev. 1.10
25
July 25, 2007
HT82A850R
Application Circuits
V
J 4
P o w e r C O N
D D
1
D 2
5 0 W
S W 3
P A 1
V D D
L E D
2
B T 1
B a tte ry
2
1
S W 4
P A 2
P A 3
3
C 1 2
1 0 m F
2
S P K M u te
3 7
3 8
3 9
4 0
4 1
4 2
4 3
N C
N C
D V S S 1
P A 7
P A 6
P A 5
P A 4
H T 8 2 A 8 5 0 R
A V S S 2
1 2 M H z
3 2
+
1 0 m F
0 .1 m F
D V D D
S W 1
R e s e t
3 1
3 0
P C 1 /T M R 0
2 9
2 8
2 7
P C 4 /S D O
2 6
P C 5 /S D I
P B 0
P B 1
P B 2
P B 3
P B 4
D V S S 2
P B 5
P C 7 /S C K
T I-
1 0 0 k W
3 3
P C 3
P B 6
2 5
P C 6 /S C S
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 0 0 k W
1 0 W
3 4
P C 2 /T M R 1
1 4
B e a d F e r r ite
2
3 5
P C 0 /B Z
T I+
3 0 0 p F
P C 6
A V D D 4
5 0 k W
T G
3 0 0 p F
1 0 k W
A V S S 3
L 5
3 6
O S C I
1 3
2
O S C O
P B 7
L 4
A V S S 1
T G
1
R E S E T
V A G
1 2
T I-
0 .1 m F
D V D D 1
A V S S 2
A V S S 3
1
M ic r o p h o n e
L O U T
1 0 k W
A V S S 3
A V D D 1
V A G R e f
+
2
P A 3
9
1 0
3
4 4
V A G
1 0 0 k W
T I+
1
0 .1 m F
A V D D 3
1 1
0 .1 m F
1 0 m F
N C
A V D D 1
8
1 0 m F
A V S S 3
0 .1 m F
R O U T
M U S IC _ IN
7
3 .3 k W
1 0 m F
A V D D 1
B IA S
6
A V D D 3
1 0 m F
P A 2
5
+
1 0 m F
4 5
1 0 m F
4 6
0 .1 m F
4
P A 1
3
A V D D 3
P A 0
A V D D 2
2
B e a d F e r r ite
M K 1
2
B e a d F e r r ite
4 7
C 4 7
1 0 m F
2
L 3
A V D D 2
0 .1 m F
L O U T
3 W
1
1
2
B e a d F e r r ite
L 1
1
V D D
L 2
1
V D D
R O U T
R 1 3
C 1 3
1 0 m F
3 W
S T E R E O
A V D D
2 7 0 W
G L E D
S P K V o lu m e In c
4 8
C 1 1
1 0 m F
A V S S 2
C 4 6
1 0 m F
R 1 2
3 W
R 1 1
2
P H O N E J A C K
A C T IV E
D 1
P A 0
B e a d F e r r ite
C 1 0 R 1 0
1 0 m F 3 W
1
S W 5
1
A V S S 2
J 5
S P K V o lu m e D e c
V D D 1
1
L 1 0
2
A V D D 4
B e a d F e r r ite
1
0 .1 m F
L 1 1
2
1 0 m F
A V S S 4
A V S S 4
1
P C 3
3
P C 7
5
P C 5
7
G N D
V D D
C E
C S N
S C K
M O S I
M IS O
IR Q
H e a d e r 4 x 2
2
A V D D 4
4
P C 6
6
P C 4
8
P C 2
B e a d F e r r ite
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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HT82A850R
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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HT82A850R
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine
will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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Package Information
48-pin LQFP (7´7) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
A
Rev. 1.10
1 2
Dimensions in mm
Min.
Nom.
Max.
8.9
¾
9.1
B
6.9
¾
7.1
C
8.9
¾
9.1
D
6.9
¾
7.1
E
¾
0.5
¾
F
¾
0.2
¾
G
1.35
¾
1.45
H
¾
¾
1.6
I
¾
0.1
¾
J
0.45
¾
0.75
K
0.1
¾
0.2
a
0°
¾
7°
40
July 25, 2007
HT82A850R
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
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Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
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Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
41
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