DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Rev. 03 — 2 July 2012 Product data sheet 1. General description The DAC1003D160 is optimized to reduce architecture complexity and overall system cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier support because of its direct IF conversion capabilities. With an internal sampling rate up to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband wireless systems transmitters, as well as a wide range of applications. 2. Features Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz Input data rate up to 80 MHz 2 interpolation filter Output data rate up to 160 Mhz Single 3.3 V power supply Low noise capacitor free integrated Phase-Locked Loop (PLL) Low power dissipation HTQFP80 package Ambient temperature from 40 C to +85 C 3. Applications Broadband wireless systems Digital radio links Cellular base stations Instrumentation Cable modems Cable Modem Termination System (CMTS)/Data Over Cable Service Interface Specification (DOCSIS) ® DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 4. Ordering information Table 1. Ordering information Type number DAC1003D160HW Package Name Description Version HTQFP80 plastic thermal enhanced thin quad flat package; 80 leads; body 12 12 1 mm; exposed die pad SOT841-1 5. Block diagram VCCA DAC1003D160 I9 to I0 CLK CLKN Q9 to Q0 i.c. VCCD 11 to 16, 19 to 22 LATCH 10 10 FIR 10 U/I 60 73 72 DAC IVIRES IOUT IOUTN (CLK × 2) 5 CLOCK DRIVER 6 PLL (CLK × 2) INTERNAL BAND GAP (CLK × 2) 31 to 34, 37 to 42 LATCH 10 10 FIR 10 57 69 68 DAC U/I 2, 8 10, 51 58 59 GAPOUT GAPD QOUT QOUTN QVIRES VCCA (1) VCCA (2) (3) (4) AGND DGND DEC 014aaa532 (1) Pins 1, 3, 61, 65, 76 and 80. (2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79. (3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56. (4) Pins 18, 26, 36, 43, 63 and 78. Fig 1. Block diagram DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 2 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 6. Pinning information 61 VCCA 62 AGND 63 DEC 64 AGND 65 VCCA 66 AGND 67 AGND 68 QOUTN 69 QOUT 70 AGND 71 AGND 72 IOUTN 73 IOUT 74 AGND 75 AGND 76 VCCA 77 AGND 78 DEC 79 AGND 80 VCCA 6.1 Pinning VCCA 1 60 IVIRES i.c. 2 59 QVIRES VCCA 3 58 GAPOUT AGND 4 57 GAPD CLK 5 56 DGND CLKN 6 55 DGND AGND 7 54 DGND i.c. 8 53 DGND DGND 9 52 DGND VCCD 10 51 VCCD DAC1003D160 I9 11 50 DGND I8 12 49 DGND I7 13 48 n.c. I6 14 47 n.c. I5 15 46 n.c. DGND I4 16 45 n.c. DGND 17 44 DGND DEC 18 43 DEC Q2 40 Q3 39 Q4 38 Q5 37 DEC 36 DGND 35 Q6 34 Q7 33 Q8 32 Q9 31 DGND 30 DGND 29 n.c. 28 n.c. 27 DEC 26 DGND 25 n.c. 24 n.c. 23 41 Q1 I0 22 42 Q0 I2 20 I1 21 I3 19 014aaa533 Fig 2. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description VCCA 1 S analog supply voltage i.c. 2 I/O internally connected; leave open VCCA 3 S analog supply voltage AGND 4 G analog ground CLK 5 I clock input CLKN 6 I complementary clock input AGND 7 G analog ground i.c. 8 O internally connected; leave open DGND 9 G digital ground DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 3 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Table 2. Pin description …continued Symbol Pin Type[1] Description VCCD 10 S digital supply voltage I9 11 I I data input bit 9 (Most Significant Bit (MSB)) I8 12 I I data input bit 8 I7 13 I I data input bit 7 I6 14 I I data input bit 6 I5 15 I I data input bit 5 I4 16 I I data input bit 4 DGND 17 G digital ground DEC 18 O decoupling node I3 19 I I data input bit 3 I2 20 I I data input bit 2 I1 21 I I data input bit 1 I0 22 I I data input bit 0 (Least Significant Bit (LSB)) n.c. 23 I not connected n.c. 23 I not connected DGND 25 G digital ground DEC 26 O decoupling node n.c. 27 I not connected n.c. 28 I not connected DGND 29 G digital ground DGND 30 G digital ground Q9 31 I Q data input bit 9 (MSB) Q8 32 I Q data input bit 8 Q7 33 I Q data input bit 7 Q6 34 I Q data input bit 6 DGND 35 G digital ground DEC 36 O decoupling node Q5 37 I Q data input bit 5 Q4 38 I Q data input bit 4 Q3 39 I Q data input bit 3 Q2 40 I Q data input bit 2 Q1 41 I Q data input bit 1 Q0 42 I Q data input bit 0 (LSB) DEC 43 O decoupling node DGND 44 G digital ground n.c. 45 I not connected n.c. 46 I not connected n.c. 47 I not connected n.c. 48 I not connected DGND 49 G digital ground DGND 50 G digital ground DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 4 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Table 2. Pin description …continued Symbol Pin Type[1] Description VCCD 51 S digital supply voltage DGND 52 G digital ground DGND 53 G digital ground DGND 54 G digital ground DGND 55 G digital ground DGND 56 G digital ground GAPD 57 I internal band gap power disable input GAPOUT 58 I/O band gap output voltage QVIRES 59 I Q DAC biasing resistor IVIRES 60 I I DAC biasing resistor VCCA 61 S analog supply voltage AGND 62 G analog ground DEC 63 O decoupling node AGND 64 G analog ground VCCA 65 S analog supply voltage AGND 66 G analog ground AGND 67 G analog ground QOUTN 68 O complementary Q DAC output current QOUT 69 O Q DAC output current AGND 70 G analog ground AGND 71 G analog ground IOUTN 72 O complementary I DAC output current IOUT 73 O I DAC output current AGND 74 G analog ground AGND 75 G analog ground VCCA 76 S analog supply voltage AGND 77 G analog ground DEC 78 O decoupling node AGND 79 G analog ground VCCA 80 S analog supply voltage [1] Type description: S: Supply; G: Ground; I: Input; O: Output. DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 5 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 7. Functional description The DAC1003D160 is a segmented architecture composed of a 7-bit thermometer sub-DAC and the remaining 3-bit in a binary weighted sub-DAC. The device produces two complementary current outputs on both channels, respectively pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to the ground. Figure 3 shows the equivalent analog output circuit of one DAC, which consists of a parallel combination of PMOS current sources and associated switches for each segment. The cascade source configuration enables the increase of the output impedance of the source and the improvement of the dynamic performance of the DAC by introducing less distortion. Figure 4 shows the internal reference configuration. In this case the bias current is given by the output of the internal regulator connected to the inverting input of the internal operational amplifiers, while external resistors RI and RQ are connected respectively to pins IVIRES and QVIRES. Thus the output current of the two DACs is typically fixed to 20 mA with an appropriate choice of these resistors. This configuration is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. The relation between full-scale output current IO(fs) and the RI (RQ) is: 2048 V GAPOUT R I = ----------------------------------------- 82 I O FS The output current can also be adjusted by imposing an external reference voltage to the inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA. The input references at pins IVIRES and QVIRES may also be driven by separate reference voltages to adjust independently the two DAC currents. DAC1003D160 GAPD INTERNAL BAND GAP AGND GAPOUT DAC1003D160 IOUT/QOUT RL AGND RI IVIRES I DAC current sources array RQ QVIRES Q DAC current sources array IOUTN/QOUTN RL AGND 014aaa538 014aaa537 Fig 3. Equivalent analog output circuit Fig 4. Internal reference configuration DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 6 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit 0.3 +3.9 V 0.3 +3.9 V mV VCCD digital supply voltage [1] VCCA analog supply voltage [1] VCC supply voltage difference between the analog and digital supply voltages 150 +150 VI input voltage pins Qn and In referenced to DGND 0.3 VCCD + 0.3 V pins IVIRES, QVIRES, GAPD, CLK and CLKN referenced to AGND 0.3 VCCA + 0.3 V pins IOUT, IOUTN, QOUT and QOUTN referenced to DAGND 0.3 VCCA + 0.3 V VO output voltage Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature - 125 C [1] All supplies are connected together. 9. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 27.1 K/W Rth(c-a) thermal resistance from case to ambient in free air 11.8 K/W 10. Characteristics Table 5. Characteristics VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCD digital supply voltage 3.0 3.3 3.6 V VCCA analog supply voltage 3.0 3.3 3.6 V ICCD digital supply current - 55 65 mA DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 7 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Table 5. Characteristics …continued VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol Parameter ICCA analog supply current Ptot total power dissipation Conditions fclk = 80 MHz; fIOUT = fQOUT = 5 MHz Min Typ Max Unit - 73 85 mA - 422 540 mW Clock inputs (CLK and CLKN) VI(cm) common-mode input voltage - 1.65 - V Vi(dif)(p-p) peak-to-peak differential input voltage - 1.0 - V Analog outputs (IOUT, IOUTN, QOUT and QOUTN) IO(fs) Ro Co full-scale output current differential outputs 4 - 20 mA output resistance [1] - 150 - k output capacitance [1] - 3 - pF - 0.3 VCCD V Digital inputs (I0 to I9, Q0 to Q9 and GAPD) VIL LOW-level input voltage DGND VIH HIGH-level input voltage 0.7 VCCD - VCCD V IIL LOW-level input current VIL = 0.3 VCCD - 5 - A IIH HIGH-level input current VIH = 0.7 VCCD - 5 - A - 1.31 - V - 1 - A - 133 - ppm/C Reference voltage output (GAPOUT) VGAPOUT voltage on pin GAPOUT IGAPOUT current on pin GAPOUT VGAPOUT voltage variation on pin GAPOUT external voltage Clock timing inputs (CLK and CLKN) fclk clock frequency - 80 MHz tw(clk)H HIGH clock pulse width 5 - - ns tw(clk)L LOW clock pulse width 5 - - ns Input timing (I0 to I9 and Q0 to Q9); see Figure 5 th(i) input hold time 1.1 - 3.4 ns tsu(i) input set-up time 1.5 - +0.7 ns - 16 - ns - - 80 MHz Output timing (IOUT, IOUTN, QOUT, QOUTN) ts settling time to 0.5 LSB [1] Digital filter specification (FIR); order N = 42 see Figure 6 and 7 and Table 7 fdata data rate ripple(pb) pass-band ripple fdata/fclk; 0.005 dB attenuation - 0.405 - Bp power bandwidth fdata/fclk; 3 dB attenuation - 0.479 - stpb stop-band attenuation fdata/fclk = 0.6 dB to 1 dB - 69 - dB td(grp) group delay time - 11 Tclk - ns Analog signal processing INL integral non-linearity - 0.2 - LSB DNL differential non-linearity - 0.1 - LSB DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 8 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Table 5. Characteristics …continued VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol Parameter In(o) output noise current Min Typ Max Unit - 120 - pA/Hz Eoffset offset error relative to full-scale - 0.3 - % EG gain error relative to full-scale 5.4 - +5.4 % GIQ IQ gain mismatch between I and Q, relative to full-scale - 0.2 - % SFDR spurious free dynamic range fclk = 80 MHz; B = Nyquist fo = 2.5 MHz at 0 dBFS - 80 - dBc 2H Conditions second harmonic level 3H third harmonic level fo = 5 MHz at 0 dBFS - 72 - dBc fo = 13 MHz at 0 dBFS - 64 - dBc fo = 5 MHz - 73 - dBc fo = 13 MHz - 65 - dBc fo = 5 MHz - 88 - dBc fo = 13 MHz - 86 - dBc IMD2 second-order intermodulation distortion fclk = 80 MHZ; fo 1 = 10 MHz; fo 2 = 12 MHz; B = Nyquist - 65 - dBc IMD3 third-order intermodulation fclk = 80 MHz; fo 1 = 10 MHz; fo 2 = 12 MHz distortion - 84 - dBc THD total harmonic distortion NSD S/N signal-to-noise ratio ACPR [1] noise spectral density adjacent channel power ratio fclk = 80 MHz; B = Nyquist; Tamb = 25 C fo = 2.5 MHz - 75 - dBc fo = 5 MHz 68 71 - dBc fo = 2.5 MHz - 155 - dBm/Hz fo = 5 MHz - 155 - dBm/Hz fo = 19 MHz - 153 - dBm/Hz fo = 2.5 MHz - 80 - dBc fo = 5 MHz 70 80 - dBc fo = 19 MHz - 78 - dBc fclk = 80 MHz fclk = 80 Msample/s; B = Nyquist baseband; 5 MHz channel spacing; B = 3.84 MHz fo = 2.5 MHz - 60 - dBc fo = 20 MHz - 61 - dBc Guaranteed by design. Table 6. Band gap Band gap disable (GAPD) Band gap input/output (GAPOUT) LOW output (VGAPOUT = 1.2 V) enable HIGH input disable DAC1003D160_3 Product data sheet Internal band gap © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 9 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation tsu(i) I0 to I9, Q0 to Q9 CLKN 50 % CLK th(i) IOUT/IOUTN, QOUT/QOUTN 014aaa534 Fig 5. Input timing diagram DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 10 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 014aaa535 20 014aaa536 0.6 output (dB) normalized output −20 0.4 −60 0.2 −100 0 −140 −180 0 0.2 0.4 0.6 0.8 normalized frequency fo/fclk −0.2 1.0 20 30 40 Fig 7. FIR filter impulse response Interpolation FIR filter coefficient Coefficient Coefficient Value H(1) H(43) 10 H(2) H(42) 0 H(3) H(41) 31 H(4) H(40) 0 H(5) H(39) 69 H(6) H(38) 0 H(7) H(37) 138 H(8) H(36) 0 H(9) H(35) 248 H(10) H(34) 0 H(11) H(33) 419 H(12) H(32) 0 H(13) H(31) 678 H(14) H(30) 0 H(15) H(29) 1 083 H(16) H(28) 0 H(17) H(27) 1 776 H(18) H(26) 0 H(19) H(25) 3 282 H(20) H(24) 0 H(21) H(23) 10 364 H(22) - 16 384 DAC1003D160_3 Product data sheet 10 t (sample) Fig 6. FIR filter frequency response Table 7. 0 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 11 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 11. Application information AGND DAC1003D160 1 kΩ CLK 100 nF DAC1003D160 Rs 1 kΩ CLK VCCA VCCA 100 nF AGND 1 kΩ 1 kΩ CLKN Vth CLKN 100 nF 1 kΩ 100 nF 1 kΩ AGND AGND 014aaa539 Fig 8. Single-ended clock schematic Fig 9. Differential clock schematic DAC1003D160_3 Product data sheet 014aaa540 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 12 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 50 Ω 50 Ω (RLOAD) (RLOAD) 1:1 1:1 AGND AGND AGND AGND C AGND AGND DGND C DEC I3 DEC AGND VCCA AGND AGND AGND QOUTN QOUT AGND AGND IOUTN IOUT AGND AGND AGND VCCA DEC 9 52 10 51 DAC1003D160 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I1 I2 53 C DGND IVIRES 1.5 kΩ QVIRES 1.5 kΩ GAPOUT GAPD C AGND DGND DGND DGND DGND DGND DGND VCCD DGND 3.3 V C DGND DGND n.c. n.c. n.c. n.c. DGND DEC C DGND Q0 Q1 Q2 DGND 8 Q3 I4 54 Q4 I5 7 Q5 I6 55 DEC I7 6 DGND I8 56 Q6 I9 5 Q7 3.3 V VCCD 57 Q8 C 4 Q9 DGND 58 DGND DGND 3 DGND i.c. 59 n.c. AGND C 2 n.c. CLKN AGND C 60 DEC CLK C DGND AGND AGND 3.3 V 3.3 V 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 n.c. C C n.c. 3.3 V C 1 I0 i.c. VCCA AGND VCCA C C AGND AGND AGND AGND 3.3 V 3.3 V VCCA 50 Ω C AGND AGND AGND 3.3 V 50 Ω 50 Ω VCCA 50 Ω C DGND DGND 014aaa541 All resistors are 1 % precision resistors. C = 100 nF. Fig 10. Application diagram DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 13 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 11.1 Alternative parts The following alternative parts are also available: Table 8. Alternative parts Type number Description DAC1403D160 Dual 14 bits DAC, with 2 interpolating [1] 160 MHz DAC1203D160 Dual 12 bits DAC, with 2 interpolating [1] 160 MHz [1] Pin to pin compatible DAC1003D160_3 Product data sheet Sampling frequency © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 14 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 12. Package outline HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad SOT841-1 c y exposed die pad X Dh A 60 41 61 ZE 40 e Eh E w (A 3) A A2 HE M θ bp A1 Lp L detail X pin 1 index 80 21 1 20 w bp e ZD M D v M A v M B B HD 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 A3 bp c D (1) Dh E (1) Eh e mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 12.1 11.9 6.05 5.95 12.1 11.9 6.05 5.95 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.1 ZD(1) ZE(1) θ 1.45 1.05 7° 0° 1.45 1.05 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT841-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-01-15 MS-026 Fig 11. Package outline SOT841-1 (HTQFP80) DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 15 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 13. Abbreviations Table 9. Abbreviations Acronym Description FIR Finite Impulse Response IF Intermediate Frequency LSB Least Significant Bit MSB Most Significant Bit PLL Phase-Locked Loop PMOS Positive-Metal Oxide Semiconductor 14. Glossary 14.1 Static parameters DNL — Differential Non-Linearity. The difference between the ideal and the measured output value between successive DAC codes. INL — Integral Non-Linearity. The deviation of the transfer function from a best-fit straight line (linear regression computation). 14.2 Dynamic parameters IMD2 — Second-order intermodulation distortion. From a dual-tone digital input sine wave (these two frequencies are close together), the intermodulation distortion product IMD2 is the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order intermodulation product. IMD3 — Third-order intermodulation distortion. From a dual-tone digital input sine wave (these two frequencies are close together), the intermodulation distortion product IMD3 is the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order intermodulation product. SFDR — Spurious Free Dynamic Range. The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. S/N — Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise excluding the harmonics and the DC component. THD — Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the output frequency to the RMS value of the output sine wave. Usually, the calculation of THD is done on the first 5 harmonics. DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 16 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC1003D160_3 20120702 Product data sheet - DAC1003D160_2 DAC1003D160_2 20080813 Product data sheet - DAC1003D160_1 - - Modifications: DAC1003D160_1 • • Added condition to ts in Table 5. Correction to Figure 10. 20080612 Product data sheet 16. Contact information For more information or sales office addresses, please visit: http://www.idt.com DAC1003D160_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 17 of 18 DAC1003D160 Integrated Device Technology Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 General description . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Pinning information . . . . . . . . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . . 1 1 1 2 2 3 3 3 6 7 7 10 11 11.1 12 13 14 14.1 14.2 15 16 17 DAC1003D160_3 Product data sheet Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information . . . . . . . . . . . . . . . . . 12 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 16 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Static parameters . . . . . . . . . . . . . . . . . . . . . . 16 Dynamic parameters . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 18 of 18