A5988 Datasheet

A5988
Quad DMOS Full-Bridge PWM Motor Driver
FEATURES AND BENEFITS
DESCRIPTION
40 V output rating
4 full bridges
Dual stepper motor driver
High-current outputs
3.3 and 5 V compatible logic
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Overcurrent protection
Low-power sleep mode
Low-profile QFN package
The A5988 is a quad DMOS full-bridge driver capable of driving
up to two stepper motors or four DC motors. Each full-bridge
output is rated up to 1.6 A and 40 V. The A5988 includes fixed
off-time pulse-width modulation (PWM) current regulators,
along with 2- bit nonlinear DACs (digital-to-analog converters)
that allow stepper motors to be controlled in full, half, and
quarter steps, and DC motors in forward, reverse, and coast
modes. The PWM current regulator uses the Allegro™ patented
mixed decay mode for reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
PACKAGES
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover-current protection.
Special power-up sequencing is not required.
The A5988 is supplied in two packages, EV and JP, with exposed
power tabs for enhanced thermal performance. The EV is a
6 mm × 6 mm, 36-pin QFN package with a nominal overall
package height of 0.90 mm. The JP is a 7 mm × 7 mm 48-pin
LQFP. Both packages are lead (Pb) free, with 100% matte-tin
leadframe plating.
Package EV, 36-pin QFN
0.90 mm nominal height
with exposed thermal pad
Not to scale
0.1 µF
50 V
VCP
* JP package only
CP2
CP1
0.1 µF
50 V
FAULTn*
PHASE1
I01
OUT2A
I02
OUT2B
I12
OUT3A
PHASE3
I13
PHASE4
I04
I14
VREF1
VREF2
VREF3
VREF4
SLEEPn
A5988
Bipolar Stepper Motors
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
Figure 1: Typical Application Circuit
A5988-DS
0.22 µF
50 V
OUT1B
PHASE2
I03
VREF
100 µF
50 V
OUT1A
I11
Microprocessor
VMOTOR 32 V
VBB2
Package JP, 48-pin LQFP
with exposed thermal pad
VBB1
•
•
•
•
•
•
•
•
•
•
•
•
RS2
RS1
RS3
RS4
A5988
Quad DMOS Full-Bridge PWM Motor Driver
SELECTION GUIDE
Part Number
Package
Packing
Fixed Off-Time (µs)
36-pin QFN with exposed thermal pad
61 pieces per tube
30
A5988GEVTR-T
36-pin QFN with exposed thermal pad
1500 pieces per reel
30
A5988GJPTR-T
48-pin LQFP with exposed thermal pad
1500 pieces per reel
30
A5988GEV-T
A5988GEVTR-1-T
36-pin QFN with exposed thermal pad
1500 pieces per reel
8.1
A5988GJPTR-1-T
48-pin LQFP with exposed thermal pad
1500 pieces per reel
8.1
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
Units
–0.5 to 40
V
1.6
A
Load Supply Voltage
VBB
Output Current
IOUT
Logic Input Voltage Range
VIN
–0.3 to 7
V
VSENSEx
0.5
V
SENSEx Pin Voltage
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Pulsed tw < 1 µs
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
2.5
V
2.5
V
–40 to 105
ºC
TJ(max)
150
ºC
Tstg
–40 to 125
ºC
VREFx
TA
Range G
THERMAL CHARACTERISTICS (may require derating at maximum conditions)
Package Thermal Resistance
Symbol
RθJA
Test Conditions
Min.
Units
EV package, 4-layer PCB based on JEDEC standard
27
ºC/W
JP package, 4-layer PCB based on JEDEC standard
23
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
JP Package
4-layer PCB
(RθJA = 23 ºC/W)
4500
4000
Power Dissipation, PD (mW)
Characteristic
3500
3000
2500
2000
1500
EV Package
4-layer PCB
(RθJA = 27 ºC/W)
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A5988
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
0.1 µF
50 V
100 µF
50 V
VBB1
VCP
CP2
FAULTn*
0.22 µF
50 V
To
VBB2
DMOS
FULL-BRIDGE 1
OCP
VREG VCP
OSC
SLEEPn
CHARGE PUMP
OUT1A
PHASE1
OUT1B
I01
I11
CONTROL LOGIC
BRIDGES 1 AND 2
PHASE2
SENSE1
I02
GATE
DRIVE
VREF1
3
+
Sense1
DMOS
FULL-BRIDGE 2
-
I12
PWM LATCH
BLANKING
OUT2A
3
-
Sense2
+
VREF2
PWM LATCH
BLANKING
OUT2B
PHASE3
VREG VCP
I03
SENSE2
Sense2
I13
CONTROL LOGIC
BRIDGES 3 AND 4
PHASE4
VBB2
DMOS
FULL-BRIDGE 3
I04
OUT3A
OUT3B
I14
VREF3
3
VBB2
PWM LATCH
BLANKING
DMOS
FULL-BRIDGE 4
Sense4
OUT4A
OUT4B
SENSE4
PGND
-
Sense4
PWM LATCH
BLANKING
GND
3
+
VREF4
SENSE3
Sense3
-
Sense3
GATE
DRIVE
+
*JP
package
only
CP1
0.1 µF
50 V
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A5988
Quad DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1: Valid at TA = 25°C, VBB = 40 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Output On Resistance
Symbol
VBB
RDS(on)
Vf , Outputs
Output Leakage
VBB Supply Current
Output Driver Slew Rate
Test Conditions
Operating
IBB
SROUT
Typ.2
Max.
Units
8
–
40
V
Source driver, IOUT = –1.2 A, TJ = 25°C
–
500
600
mΩ
Sink driver, IOUT = 1.2 A, TJ = 25°C
–
500
600
mΩ
IOUT = 1.2 A
IDSS
Min.
–
–
1.2
V
–20
–
20
µA
–
–
23
mA
Outputs off
–
13.7
16
mA
Sleep mode
–10
<1
10
µA
10% to 90%
50
100
150
ns
2
–
–
V
Outputs, VOUT = 0 to VBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
CONTROL LOGIC
Logic Input Voltage
Logic Input Current
Logic Input Hysteresis
VIN(1)
VIN(0)
IIN
VIN = 0 to 5 V
Vhys
Sleep Rising Threshold
Sleep Falling Threshold
Sleep Hysteresis
Sleep Input Current
Crossover Delay
tCOD
–
–
0.8
V
–20
<1
20
µA
150
300
500
mV
2.5
2.7
2.95
V
–
2.4
–
V
250
325
450
mV
–
100
150
µA
250
425
1000
ns
0.7
1
1.3
µs
0.0
–
1.5
V
Blank Time
tBLANK
VREFx Pin Input Voltage Range
VREFx
Operating
IREF
VREF = 1.5
–
–
±1
μA
VREF = 1.5, phase current = 100%
–5
–
5
%
VREF = 1.5, phase current = 67%
–5
–
5
%
VREF = 1.5, phase current = 33%
–15
–
15
%
VREFx Pin Reference Input Current
Current Trip-Level Error3
VERR
PROTECTION CIRCUITS
VBB UVLO Threshold
VBB Hysteresis
VUV(VBB)
VBB rising
VUV(VBB)hys
Overcurrent Protection Threshold
IOUT = 1 mA
Fault Output Voltage
No fault, VOUT = 5 V
Thermal Shutdown Hysteresis
7.6
7.9
V
500
600
mV
1.6
–
–
A
–
–
0.5
V
–
–
1
µA
TJTSD
155
165
175
°C
TJTSDhys
–
15
–
°C
Fault Output Leakage Current
Thermal Shutdown Temperature
7.3
400
1 For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/3) – VSENSE] / (VREF/3).
2 Typical
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A5988
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation. The A5988 is designed to operate two
stepper motors, four DC motors, or one stepper and two DC
motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse-widthmodulated (PWM) control circuitry. Each full-bridge peak current is set by the value of an external current sense resistor, RSx ,
and a reference voltage, VREFx .
Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled, and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
RS and voltage at the VREF input with a transconductance function, approximated by:
ITripMax = VREF / (3 × RS )
Each current step is a percentage of the maximum current,
ITripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) × ITripMax
where % ITripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of
±500 mV on each SENSEx pin is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the time the drivers remain
off. For the A5988 variant, the off-time (toff) is 30 µs. For the
A5988-1 variant, toff is 8.1 µs.
Blanking. This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
Control Logic. Communication is implemented via the industry standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent VREF input, so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than VBB to drive the source-side
DMOS gates. A 0.1 μF ceramic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic
capacitor is required between VCP and VBBx to act as a reservoir
to operate the high-side DMOS devices.
Shutdown. In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A5988
Quad DMOS Full-Bridge PWM Motor Driver
Synchronous Rectification
Sleep Mode
When a PWM-off cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A5988 synchronous rectification feature will turn on the appropriate MOSFETs during the
current decay, and effectively short out the body diodes with the
low RDS(on) driver. This significantly lowers power dissipation.
When a zero current level is detected, synchronous rectification is
turned off to prevent reversal of the load current.
To minimize power consumption when not in use, the A5988 can
be put into Sleep Mode by bringing the SLEEPn pin low. Sleep
Mode disables much of the internal circuitry, including the charge
pump.
Mixed Decay Operation
The bridges operate in mixed decay mode. Referring to Figure
2, as the trip point is reached, the device goes into fast decay
mode for 30.1% of the fixed off-time period. After this fast decay
portion, tFD , the device switches to slow decay mode for the
remainder of the off-time. During transitions from fast decay to
slow decay, the drivers are forced off for approximately 600 ns.
This feature is added to prevent shoot-through in the bridge. As
shown in Figure 2, during this “dead time” portion, synchronous
rectification is not active, and the device operates in fast decay
and slow decay only.
Overcurrent Protection
An overcurrent monitor protects the A5988 from damage due to
output shorts. If a short is detected, the A5988 latches the fault
and disables the outputs. The latched fault can only be cleared
by cycling the power to VBB or by putting the device in Sleep
Mode. During OCP events, Absolute Maximum Ratings may be
exceeded for a short period of time before outputs are latched off.
Fault Output (FAULTn pin, available on JP package only)
The open-drain fault output is pulled low when an overcurrent
protection event occurs and the outputs are latched off.
VPHASE
+
IOUT
See Enlargement A
0
–
Fixed Off-Time 30 µs
9 µs
Fixed Off-Time 8.1 µs
21 µs
2.4 µs
ITrip
5.7 µs
ITrip
IOUT
SDSR
FDSR
FDDT
IOUT
SDDT
SDSR
FDSR
SDDT
FDDT
A5988
SDDT
SDDT
A5988-1
Enlargement A
Figure 2: Mixed Decay Mode Operation
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A5988
Quad DMOS Full-Bridge PWM Motor Driver
STEP SEQUENCING DIAGRAMS
Phase 1
(%)
100.0
100.0
66.7
66.7
Phase 1
(%)
0
–66.7
–66.7
–100.0
–100.0
100.0
100.0
66.7
Phase 2
(%)
0
66.7
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Full step 2 phase
Half step 2 phase
Modified full step 2 phase
Modified half step 2 phase
Figure 3: Step Sequencing for Full-Step Increments
Figure 4: Step Sequencing for Half-Step Increments
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A5988
Quad DMOS Full-Bridge PWM Motor Driver
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 5: Step Sequence for Quarter-Step Increments
Table 1: Step Sequencing Settings
Full
1/2
1
1/4
1
2
1
2
3
4
3
5
6
2
4
7
8
5
9
10
3
6
11
12
7
13
14
4
8
15
16
*Denotes modified step mode
Phase 1
(%ITripMax)
I0x
I1x
PHASE
Phase 2
(%ITripMax)
I0x
I1x
PHASE
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
H
L
L
L
L
L
H
H
H
L
L
L
L
L
H
X
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
L
L
0
0
0
0
X
1
1
1
1
1
1
1
X
0
0
0
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A5988
Quad DMOS Full-Bridge PWM Motor Driver
APPLICATIONS INFORMATION
Motor Configurations. For applications that require either a
stepper/DC motor driver or dual DC motor driver, Allegro offers
the A5989 and A5995. These devices are offered in the same
36-terminal QFN package as the A5988. The DC motor drivers
are capable of supplying 3.2 A at 40 V. Commutation is done
with a standard phase/enable logic interface. Please refer to the
Allegro website for further information and datasheets about
those devices.
DC Motor Control. Each of the 4 full bridges has independent
PWM current control circuitry that makes the A5988 capable of
driving up to four DC motors at currents up to 1.2 A. Control
of the DC motors is accomplished by tying the I0x and I1x pins
together, creating an equivalent ENABLE function with maximum current defined by the voltage on the corresponding VREF
pin. The DC motors can be driven via a PWM signal on this
enable signal, or on the corresponding PHASE pin. Motor control
includes forward, reverse, and coast.
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
Grounding. In order to minimize the effects of ground bounce
and offset issues, it is important to have a low-impedance singlepoint ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A5988, that area
becomes an ideal location for a star ground point.
A low-impedance ground will prevent ground bounce during
high-current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below illustrates how to create a star ground under
the device to serve both as low-impedance ground point and
thermal path.
Solder
A5988
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A5988 must be soldered directly onto the board. On the underside of the A5988 package is an exposed pad, which provides a
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
VBB
VBB
CVCP
CVCP
GND
CCP
OUT3B
OUT1A
RS1
CIN1
I11
I12
VCP
CP1
PGND
VBB2
OUT2B
OUT4B
SENSE2
SENSE4
OUT2A
OUT4A
CIN2
RS4
I14
PHASE2
PHASE4
PHASE3
RS2
VBB1
RS3
PHASE1
OUT4A
RS4
RS2
OUT3B
GND
OUT4B
SENSE3
PAD
VREF3
OUT2B
OUT2A
OUT1B
VREF4
CIN2
I13
OUT3A
A5988
SENSE1
VREF1
CIN1
I04
VREF2
OUT1B
I01
1
OUT3A
U1
CP2
RS3
I03
RS1
OUT1A
I02
CIN3
SLEEPn
GND
CIN3
CCP
GND
EV package layout shown
Figure 6: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A5988 (U1) is
soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the
ground plane on the other side of the PCB, so the two copper areas together form the star ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A5988
Quad DMOS Full-Bridge PWM Motor Driver
The two input capacitors should be placed in parallel and as
close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high-frequency current components.
As shown in the layout in Figure 6, the SENSEx pins have very
short traces to the RSx resistors and very thick, low-impedance
traces directly to the star ground beneath the device. If possible,
there should be no other components on the sense circuits.
Sense Pins. The sense resistors, RSx, should have a very low
impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by
the current sense comparators. Long ground traces will cause
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A5988
Quad DMOS Full-Bridge PWM Motor Driver
20 OUT4A
19 I14
22 OUT4B
21 SENSE4
24 OUT3B
23 VBB2
25 SENSE3
27 I13
26 OUT3A
28
18 PHASE1
I11 29
17 PHASE2
25 NC
27 OUT4A
26 NC
29 OUT4B
28 SENSE4
31 VBB2
30 NC
33 SENSE3
32 OUT3B
35 NC
34 OUT3A
Package JP
Package EV
I12
36 NC
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
I13 37
24 I14
I12 38
23 FAULTn
I11 39
22 PHASE1
PGND 40
21 PHASE2
20 GND
NC 41
PGND
30
16 GND
VCP
31
15 VREF4
CP1
32
CP2
33
13 VREF2
CP2 44
17 VREF2
I01
34
12 VREF1
I01 45
16 VREF1
I02
35
11 SLEEPn
I02 46
15 SLEEPn
I03
36
10 PHASE3
I03 47
14 PHASE3
I04 48
13 PHASE4
VCP 42
EV
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
–
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
–
–
Number
JP
3
4
5
6
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
31
32
33
34
37
38
39
40
42
43
44
45
46
47
48
1, 2, 7, 11,
12, 25, 26,
30, 35, 36,
41
–
Pin Description
OUT1A
SENSE1
OUT1B
VBB1
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
SLEEPn
VREF1
VREF2
VREF3
VREF4
GND*
PHASE2
PHASE1
FAULTn
I14
OUT4A
SENSE4
OUT4B
VBB2
OUT3B
SENSE3
OUT3A
I13
I12
I11
PGND*
VCP
CP1
CP2
I01
I02
I03
I04
DMOS Full-Bridge 1 Output A
Sense Resistor Terminal for Bridge 1
DMOS Full-Bridge 1 Output B
Load Supply Voltage
DMOS Full-Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full-Bridge 2 Output A
Control Input
Control Input
Active Low Sleep Mode Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog and Digital Ground
Control Input
Control Input
Open Drain Fault Output (JP package only)
Control Input
DMOS Full-Bridge 4 Output A
Sense Resistor Terminal for Bridge 4
DMOS Full-Bridge 4 Output B
Load Supply Voltage
DMOS Full-Bridge 3 Output B
Sense Resistor Terminal for Bridge 3
DMOS Full-Bridge 3 Output A
Control Input
Control Input
Control Input
Power Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
Control Input
NC
No Connect
PAD
Exposed pad for enhanced thermal performance. Should be soldered to the PCB.
NC 12
NC 11
8
9
OUT2B
SENSE2
Pin Name
OUT2A 10
6
7
NC
18 VREF3
VBB1
4
5
OUT1B
3
OUT1A
SENSE1
1
2
NC
CP1 43
Terminal List Table
19 VREF4
PAD
NC
8
9
OUT2A
PHASE4
6
7
OUT2B
14 VREF3
SENSE2
4
OUT1B
5
3
SENSE1
VBB1
1
2
I04
OUT1A
PAD
Packages are not to scale
* GND, PGND, and thermal pad must be connected together externally under the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A5988
Quad DMOS Full-Bridge PWM Motor Driver
EV PACKAGE, 36-PIN QFN WITH EXPOSED THERMAL PAD
1.15
6.00 ±0.15
1
2
0.30
0.50
36
36
1
2
A
6.00 ±0.15
D 37X
SEATING
PLANE
0.08 C
4.15
C
5.80
4.15
5.80
0.90 ±0.10
+0.05
0.25 –0.07
0.50
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.55 ±0.20
B
A Terminal #1 mark area
4.15
2
1
36
4.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A5988
Quad DMOS Full-Bridge PWM Motor Driver
JP PACKAGE, 48-PIN LQFP WITH EXPOSED THERMAL PAD
0.30
9.00 ±0.20
7.00 ±0.20
0.50
1.70
7º
4° ±4
0º
+0.05
0.15 –0.06
C
B
9.00 ±0.20 7.00 ±0.20
5.00
5.00±0.04
8.60
0.60 ±0.15
48
(1.00)
A
1
48
2
48X
0.22 ±0.05
SEATING PLANE
GAGE PLANE
SEATING
PLANE
0.08 C
0.50
1 2
0.25
5.00±0.04
C
1.60 MAX
1.40 ±0.05
0.10 ±0.05
5.00
8.60
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A5988
Quad DMOS Full-Bridge PWM Motor Driver
Revision History
Number
Date
Description
–
March 21, 2016
Initial release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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