Low Voltage, 2.5V and 3.3V LVCMOS PLL Clock Driver MPC9600 NRND NRND – Not Recommend for New Designs DATASHEET The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. Features • • • • • • • • • • • • • Multiplication of Input Frequency by 2, 3, 4, and 6 Distribution of Output Frequency to 21 Outputs Organized in Three Output Banks: QA0-QA6, QB0-QB6, QC0-QC6, Each Fully Selectable Fully Integrated PLL Selectable Output Frequency Range Is 50 to 100 MHz and 100 to 200 MHz Selectable Input Frequency Range Is 16.67 to 33 MHz and 25 to 50 MHz LVCMOS Outputs Outputs Disable to High Impedance (Except QFB) LVCMOS or LVPECL Reference Clock Options 48-Lead QFP Packaging, Pb-Free 50 ps Cycle-to-Cycle Jitter 150 ps Maximum Output-to-Output Skew 200 ps Maximum Static Phase Offset Window NRND – Not Recommend for New Designs 3.3 V OR 2.5 V LOW VOLTAGE CMOS PLL CLOCK DRIVER SCALE 2:1 AE SUFFIX 48-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 932-03 Functional Description The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN. Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4, and 6. The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to VTT = VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems. The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL. The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance. MPC9600 REVISION 6 JANUARY 7, 2013 1 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER VCCA VCC 7 CCLK PCLK (Pulldown) 0 0 (Pulldown) Ref 1 1 PCLK /2 PLL /4 FB REF_SEL (Pullup) FB_IN FSELA (Pullup) VCC/2 /8 200 – 400 MHz 0 Bank A QA0 D QA1 Q 1 QA2 /12 QA3 (Pulldown) QA4 QA5 0 D Q 7 1 FSELB QB0–6 (Pullup) 0 Bank C D QC0–6 Q 7 1 FSELC QA6 Bank B (Pullup) 0 Feedback D Q QFB 1 FSEL_FB OE (Pullup) (Pulldown) 8 GND Figure 1. MPC9600 Logic Diagram MPC9600 REVISION 6 JANUARY 7, 2013 2 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Table 1. Pin Configuration – 48 LQFP Pin I/O Type Description QAn Output LVCMOS Bank A outputs QBn Output LVCMOS Bank B outputs QCn Output LVCMOS Bank C outputs QFB Output LVCMOS Differential feedback output REF_SEL Input LVCMOS Reference clock input select FSELA Input LVCMOS Selection of bank A output frequency FSELB Input LVCMOS Selection of bank B output frequency FSELC Input LVCMOS Selection of bank C output frequency FSEL_FB Input LVCMOS Selection of feedback frequency OE Input LVCMOS Output enable VCCA Power supply Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA VCC Power supply Core power supply GND Ground Ground VCC PLL feedback clock input QB6 LVCMOS QB5 Input QB4 FB_IN GND Reference clock input QB3 LVCMOS QB2 Input VCC CCLK QB1 Differential reference clock frequency input QB0 PECL QFB Input GND PCLK, PCLK 36 35 34 33 32 31 30 29 28 27 26 25 VCC 37 24 GND QA6 38 23 QC0 QA5 39 22 QC1 QA4 40 21 QC2 GND 41 20 VCC QA3 42 19 QC3 QA2 43 18 QC4 VCC 44 17 GND QA1 45 16 QC5 QA0 46 15 QC6 FB_IN 47 14 OE GND 48 13 VCC 1 2 3 4 5 6 7 8 9 10 11 12 GND CCLK PCLK PCLK VCC REF_SEL FSEL_FB VCCA FSELA FSELB FSELC GND MPC9600 Figure 2. 48-Lead Package Pinout (Top View) MPC9600 REVISION 6 JANUARY 7, 2013 3 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Table 2. Function Table (Controls) Control Pin 0 1 REF_SEL CCLK PCLK VCCA PLL Bypass(1) PLL Power OE Outputs Enabled Outputs Disabled (except QFB) FSELA Output Bank A at VCO/2 Output Bank A at VCO/4 FSELB Output Bank B at VCO/2 Output Bank B at VCO/4 FSELC Output Bank C at VCO/2 Output Bank C at VCO/4 FSEL_FB Feedback Output at VCO/8 Feedback Output at VCO/12 1. VCCA = GND, PLL off and bypassed for static test and diagnosis. Table 3. Absolute Maximum Ratings(1) Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V DC Input Current 20 mA IOUT DC Output Current 50 mA TStor Storage Temperature Range 125 C VOUT IIN –65 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ VCC 2 Max Unit Condition VTT Output Termination Voltage MM ESD Protection (Machine Model) 400 V HBM ESD Protection (Human Body Model) 4000 V CDM ESD Protection (Charged Device Model) 1500 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance 4.0 pF Inputs MPC9600 REVISION 6 JANUARY 7, 2013 4 V ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = – 40°C to +85°C) Symbol Characteristics Min VIH Input High Voltage VIL Input Low Voltage VPP Peak-to-Peak Input Voltage (DC) PCLK, PCLK 250 Common Mode Range (DC) PCLK, PCLK 1.0 VCMR(1) 2.0 VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN Typ Max Unit VCC + 0.3 V LVCMOS 0.8 V LVCMOS mV LVPECL V LVPECL V IOH = –24 mA(2) V V IOL = 24 mA IOL = 12 mA VCC – 0.6 2.4 0.55 0.30 14 – 17 Input Leakage Current ICCA Maximum PLL Supply Current ICCQ Maximum Quiescent Supply Current 2.0 Condition W 150 A VIN = VCC or GND 5.0 mA VCCA Pin 1.0 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 6. DC Characteristics (VCC = 2.5 V ± 5%, TA = – 40°C to +85°C) Symbol Characteristics Min VIH Input High Voltage VIL Input Low Voltage VPP Peak-to-Peak input voltage (DC) PCLK, PCLK 250 Common Mode Range (DC) PCLK, PCLK 1.0 VCMR(1) VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN Typ 1.7 Maximum PLL Supply Current ICCQ Maximum Quiescent Supply Current Unit VCC + 0.3 V LVCMOS 0.7 V LVCMOS mV LVPECL V LVPECL V IOH = –15 mA(2) V IOL = 15 mA VCC – 0.6 1.8 0.6 17 – 20 Input Leakage Current ICCA Max 3.0 Condition W 150 A VIN = VCC or GND 5.0 mA VCCA Pin 1.0 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. MPC9600 REVISION 6 JANUARY 7, 2013 5 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Table 7. AC Characteristics – 48 LQFP (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1) Symbol fref Characteristics Typ Max Unit Condition Input Frequency 8 feedback (FSEL_FB = 0) 12 feedback (FSEL_FB = 1) 25 16.67 50 33 MHz MHz PLL locked PLL locked Static test mode (VCCA = GND) 0 500 MHz VCCA = GND 200 400 MHz 100 50 200 100 MHz MHz 25 75 % PCLK, PCLK 500 1000 mV LVPECL Common Mode Range PCLK, PCLK (VCC = 3.3 V 5%) PCLK, PCLK (VCC = 2.5 V 5%) 1.2 1.2 VCC –0.8 VCC –0.6 V V LVPECL LVPECL 1.0 ns see Figure 11 +40 +130 +140 +230 ps ps PLL locked PLL locked all outputs, single frequency all outputs, multiple frequency 70 70 150 150 ps ps Measured at coincident rising edge within QAx output bank within QBx outputs within QCx outputs 30 40 30 75 125 75 ps ps ps 50 55 % 1.0 ns fVCO VCO Frequency fMAX Maximum Output Frequency frefDC Reference Input Duty Cycle VPP Peak-to-Peak Input Voltage VCMR Min (2) 2 outputs (FSELx = 0) 4 outputs (FSELx = 1) tr, tf CCLK Input Rise/Fall Time t() Propagation Delay (static phase offset) tsk(o) Output-to-Output Skew CCLK to FB_IN PECL_CLK to FB_IN –60 +30 DC Output Duty Cycle 45 tr, tf Output Rise/Fall Time 0.1 tPLZ, HZ Output Disable Time 10 ns tPZL, ZH Output Enable Time 10 ns BW tJIT(CC) tJIT(PER) PLL Closed Loop Bandwidth 8 feedback (FSEL_FB=0) 12 feedback (FSEL_FB=1) 1.0 – 10 0.6 – 4.0 MHz MHz Cycle-to-Cycle Jitter(3) All outputs in 2 configuration All outputs in 4 configuration tJIT() I/O Phase Jitter (1 ) tLOCK Maximum PLL Lock Time VCC = 3.3 V VCC = 2.5 V see Figure 11 –3 dB point of PLL transfer characteristic Refer to application section for other configurations 40 40 130 180 ps ps 25 20 70 100 ps ps Refer to application section for other configurations 17(4) 15(3) ps ps RMS value at fVCO = 400 MHz 5.0 ms Period Jitter(3) All outputs in 2 configuration All outputs in 4 configuration PLL locked PLL locked 1. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 3. Cycle-to-cycle and period jitter depends on output divider configuration. 4. See Applications Information section for max I/O phase jitter versus frequency. MPC9600 REVISION 6 JANUARY 7, 2013 6 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER APPLICATIONS INFORMATION Programming the MPC9600 The MPC9600 clock driver outputs can be configured into several divider modes. Additionally the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The selectable feedback divider of the three output groups allows the user to configure the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency ratios. The use of even dividers ensure that the output duty cycle is always 50%. Table 8 illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The feedback divider division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 50 MHz to 200 MHz while the VCO frequency range is specified from 200 MHz to 400 MHz and should not be exceeded for stable operation. Table 8. Output Frequency Relationship(1) for QFB Connected to FB_IN Configuration Inputs FSEL_FB FSELA FSELB FSELC Input Frequency Range CLK [MHz] 0 0 0 0 25.0–50.0 0 0 0 0 0 0 Output Frequency Ratio and Range Ratio, QAx [MHz] Ratio, QBx [MHz] Ratio, QCx [MHz] 4•CLK (100–200) 4•CLK (100–200) 4•CLK (100–200) 1 4•CLK (100–200) 4•CLK (100–200) 2•CLK (50.0–100) 1 0 4•CLK (100–200) 2•CLK (50.0–100) 4•CLK (100–200) 0 1 1 4•CLK (100–200) 2•CLK (50.0–100) 2•CLK (50.0–100) 0 1 0 0 2•CLK (50.0–100) 4•CLK (100–200) 4•CLK (100–200) 0 1 0 1 2•CLK (50.0–100) 4•CLK (100–200) 2•CLK (50.0–100) 0 1 1 0 2•CLK (50.0–100) 2•CLK (50.0–100) 4•CLK (100–200) 0 1 1 1 2•CLK (50.0–100) 2•CLK (50.0–100) 2•CLK (50.0–100) 1 0 0 0 6•CLK (100–200) 6•CLK (100–200) 6•CLK (100–200) 1 0 0 1 6•CLK (100–200) 6•CLK (100–200) 3•CLK (50.0–100) 1 0 1 0 6•CLK (100–200) 3•CLK (50.0–100) 6•CLK (100–200) 1 0 1 1 6•CLK (100–200) 3•CLK (50.0–100) 3•CLK (50.0–100) 1 1 0 0 3•CLK (50.0–100) 6•CLK (100–200) 6•CLK (100–200) 1 1 0 1 3•CLK (50.0–100) 6•CLK (100–200) 3•CLK (50.0–100) 1 1 1 0 3•CLK (50.0–100) 3•CLK (50.0–100) 6•CLK (100–200) 1 1 1 1 3•CLK (50.0–100) 3•CLK (50.0–100) 3•CLK (50.0–100) 16.67–33.33 1. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400. MPC9600 REVISION 6 JANUARY 7, 2013 7 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Table 9. Typical and Maximum Period Jitter Specification QA0 to QA6 Device Configuration QB0 to QB6 QC0 to QC6 Typ Max Typ Max Typ Max All output banks in 2 or 4 divider configuration 2 (FSELA = 0 and FESLB = 0 and FSELC = 0) 4 (FSELA = 1 and FESLB = 1 and FSELC = 1) 25 20 50 70 50 50 70 100 25 20 50 70 Mixed 2/4 divider configurations(2) for output banks in 2 divider configurations for output banks in 4 divider configurations 80 25 130 70 100 60 150 100 80 25 130 70 (1) 1. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 3 for an example configuration. 2. Multiple frequency generation. Jitter data are specified for each output divider separately. See Figure 7 for an example. Table 10. Typical and Maximum Cycle-to-Cycle Jitter Specification QA0 to QA6 Device Configuration QB0 to QB6 QC0 to QC6 Typ Max Typ Max Typ Max All output banks in 2 or 4 divider configuration(1) 2 (FSELA = 0 and FESLB = 0 and FSELC = 0) 4 (FSELA = 1 and FESLB = 1 and FSELC = 1) 40 40 90 110 80 120 130 180 40 40 90 110 Mixed 2/ 4 divider configurations(2) for output banks in 2 divider configurations for output banks in 4 divider configurations 150 30 250 110 200 120 280 180 150 30 250 110 1. In this configuration, all MPC9600 outputs generate the same clock frequency. 2. Multiple frequency generation. Jitter data are specified for each output divider separately. fref = 20.833 MHz CCLK QA0–6 QB0–6 FB_IN 1 FSEL_FB 0 0 0 FSELA FSELB FSELC QC0–6 7 7 7 fref = 33.33 MHz 125 MHz CCLK QA0–6 125 MHz QB0–6 FB_IN 125 MHz QFB 0 FSEL_FB 0 1 1 FSELA FSELB FSELC QC0–6 MPC9600 20.833 MHz (Feedback) 33.33 MHz (Feedback) Min Max Frequency Range 7 7 133.3 MHz 66.67 MHz 66.67 MHz QFB MPC9600 Frequency Range 7 Min Max Input 16.67 MHz 33.33 MHz Input 25 MHz 50 MHz QA outputs 100 MHz 200 MHz QA outputs 100 MHz 200 MHz QB outputs 100 MHz 200 MHz QB outputs 100 MHz 200 MHz QC outputs 100 MHz 200 MHz QC outputs 100 MHz 200 MHz Figure 3. Configuration for 126 MHz Clocks MPC9600 REVISION 6 JANUARY 7, 2013 Figure 4. Configuration for 133.3/66.67 MHz Clocks 8 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Power Supply Filtering The MPC9600 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9600 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9600. Figure 5 illustrates a typical power supply filter scheme. The MPC9600 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 5, must have a resistance of 9–10 (VCC = 2.5 V) to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 5, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. Using the MPC9600 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9600. For these applications the MPC9600 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Freescale Semiconductor MC100ES6111 or MC100ES6226, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9600 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9600 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9600 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O)) relative to the feedback output. Calculation of Part-to-Part Skew The MPC9600 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (CCLK or PCLK) of two or more MPC9600 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: RF = 9–10 for VCC = 2.5 V or VCC = 3.3 V CF = 22 F for VCC = 2.5 V or VCC = 3.3 V RF VCCA VCC CF TCLKCommon tPD,LINE(FB) —t() 10 nF MPC9600 QFBDevice 1 VCC 33...100 nF tJIT() Any QDevice 1 +tSK(O) Figure 5. VCCA Power Supply Filter +t() As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9600 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. MPC9600 REVISION 6 JANUARY 7, 2013 QFBDevice2 Any QDevice 2 Max. skew tJIT() +tSK(O) tSK(PP) Figure 6. MPC9600 Maximum Device-to-Device Skew 9 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 11. or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9600 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9600 clock driver is effectively doubled due to its capability to drive multiple lines. Table 11. Confidence Factor CF CF Probability of Clock Edge Within the Distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of – 261 ps to 341 ps relative to CCLK (VCC = 3.3 V and fVCO = 200 MHz): MPC9600 Output Buffer IN tSK(PP) = [–60 ps...140 ps] + [–150 ps...150 ps] + [(17 ps @ –3)...(17 ps @ 3)] + tPD, LINE(FB) MPC9600 Output Buffer tSK(PP) = [–261 ps...341 ps] + tPD, LINE(FB) Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC = 3.3 V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9600). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 7 can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). IN tjit(ø) [ps] rms VCC = 2.5 V 260 280 300 320 340 360 380 400 VCO FREQUENCY (MHz) Figure 7. I/O Jitter versus VCO Frequency for VCC = 2.5 V and VCC = 3.3 V RS = 36 ZO = 50 RS = 36 ZO = 50 OutA OutB0 14 OutB1 VL = VS (Z0 (RS + R0 + Z0)) Z0 = 50 || 50 Driving Transmission Lines The MPC9600 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel MPC9600 REVISION 6 JANUARY 7, 2013 ZO = 50 The waveform plots in Figure 9 shows the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9600 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9600. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VCC = 3.3 V 220 240 RS = 36 Figure 8. Single versus Dual Transmission Lines Maximum I/O Jitter versus Frequency 18 16 14 12 10 8 6 4 2 0 200 14 RS = 36 || 36 R0 = 14 VL = 3.0 (25 (18 + 17 + 25) = 1.31 V 10 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER At the load end the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 MPC9600 Output Buffer Voltage (V) 2.0 In 1.5 RS = 22 ZO = 50 RS = 22 ZO = 50 14 1.0 0.5 14 + 22 || 22 = 50 || 50 25 = 25 0 2 4 6 8 Time (ns) 10 12 14 Figure 10. Optimized Dual Line Termination Figure 9. Single versus Dual Waveforms The following figures illustrate the measurement reference for the MPC9600 clock driver circuit. MPC9600 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 RT = 50 VTT VTT Figure 11. CCLK MPC9600 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 MPC9600 DUT ZO = 50 RT = 50 RT = 50 VTT VTT Figure 12. PCLK MPC9600 AC Test Reference MPC9600 REVISION 6 JANUARY 7, 2013 11 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER PCLK VCC VPP PCLK VCC 2 TCLK VCMR GND VCC VCC 2 FB_IN VCC VCC 2 FB_IN GND GND t() t() Figure 14. Propagation Delay (tØ, status phase offset) Test Reference Figure 15. Propagation Delay (tØ) Test Reference VCC VCC 2 VCC VCC 2 GND GND tP VCC VCC 2 T0 GND DC = tP/T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output Duty Cycle (DC) Figure 17. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN–TN+1| TJIT(P) = |TN–1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle-to-Cycle Jitter Figure 19. Period Jitter CCLK (PCLK) FB_IN TJIT() = |T0–T1mean| tF VCC = 3.3 V VCC = 2.5 V 2.4 1.8 0.55 0.6 tR The deviation in T0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 20. I/O Jitter MPC9600 REVISION 6 JANUARY 7, 2013 Figure 21. Transition Time Test Reference 12 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER PACKAGE DIMENSIONS 4X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5m, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLAN AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATAUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL AE NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 0.200 AB T-U Z 9 DETAIL Y A P A1 48 37 36 1 T U V B AE B1 12 25 13 V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0˚ 7˚ 12˚ REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF M˚ BASE METAL TOP & BOTTOM J 0.250 N C E GAUGE PLANE R F D 0.080 M AC T-U Z SECTION AE-AE W H L˚ K DETAIL AD AA CASE 932-03 ISSUE F 48-LEAD LQFP PACKAGE MPC9600 REVISION 6 JANUARY 7, 2013 13 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER Revision History Sheet Rev 6 Table Page 1 Description of Change Date NRND – Not Recommend for New Designs 1/7/13 MPC9600 REVISION 6 JANUARY 7, 2013 14 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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