ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The ICS853301 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8533-01 ideal for those applications demanding well defined performance and repeatability. • Four differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 30ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 1.4ns (maximum) • Additive phase jitter, RMS: 0.06ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free packages available • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VCC D CLK_EN Q LE CLK nCLK PCLK nPCLK CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8533-01 Q3 nQ3 8533AG-01 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View www.idt.com 1 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VEE Power Type 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input 6 PCLK Input Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. Pullup LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. 7 nPCLK Input 8, 9 nc Unused 10, 13, 18 VCC Power Positive supply pins. 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. No connect. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8533AG-01 www.idt.com 2 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK or PCLK Outputs nCLK or nPCLK Q0:Q3 nQ0:nQ3 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIG H LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8533AG-01 www.idt.com 3 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units 2 VEE + 0.3 V -0.3 TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical 0.8 V CLK_EN VIN = VCC = 3.465V 5 µA CLK_SEL VIN = VCC = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units nCLK VCC = VIN = 3.465V 5 µA CLK VCC = VIN = 3.465V 150 µA nCLK VCC = 3.465V, VIN = 0V -150 CLK VCC = 3.465V, VIN = 0V -5 VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8533AG-01 Maximum www.idt.com 4 µA µA 1.3 V VCC - 0.85 V REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions PCLK Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA nPCLK VCC = VIN = 3.465V PCLK VCC = 3.465V, VIN = 0V -5 µA nPCLK VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 5 0.3 µA 1 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 3 VCC - 2.0 VCC - 1.7 V 1.0 V Maximum Units 650 MHz 1.4 ns VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions ƒ≤ 650MHz Minimum Typical 1.0 t sk(o) Output Skew; NOTE 2, 4 30 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time 150 ps t jit tR / tF 0.06 20% to 80% @ 50MHz 300 odc Output Duty Cycle 47 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Driving only one input clock. 8533AG-01 www.idt.com 5 ps 700 ps 53 % REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Input/Output Additive Phase Jitter -20 at 156.25MHz = 0.06ps (typical) -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 8533AG-01 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.idt.com 6 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nPCLK, nCLK LVPECL V Cross Points PP nQx VEE V CMR PCLK, CLK V EE -1.3V ± 0.165 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx nPCLK, nCLK Qx PCLK, CLK nQ0:nQ3 nQy Q0:Q3 Qy tPD t sk(o) OUTPUT SKEW PROPAGATION DELAY nQ0:nQ3 80% 80% Q0:Q3 VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 8533AG-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.idt.com 7 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF - C1 0.1uF R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 8533AG-01 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.idt.com 8 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 4B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 4D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 8533AG-01 www.idt.com 9 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here 3.3V 3.3V R1 50 CML 3.3V 3.3V 3.3V Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK nPCLK PCLK R1 100 Zo = 50 Ohm nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 5A. PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 5B. PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 5C. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 5D. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 5E. PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 8533AG-01 HiPerClockS PCLK/nPCLK R2 125 FIGURE 5F. HiPerClockS PCL K/n PC LK R2 1K PCLK/nPCLK INPUT DRIVEN 3.3V LVDS DRIVER BY A www.idt.com 10 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8533-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8533-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120mW = 293.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8533AG-01 www.idt.com 11 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8533AG-01 www.idt.com 12 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 73.2°C/W 200 500 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8533-01 is: 404 8533AG-01 www.idt.com 13 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 8533AG-01 www.idt.com 14 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8533AG-01 ICS8533AG-01 20 lead TSSOP tube 0°C to 70°C 8533AG-01T ICS8533AG-01 20 lead TSSOP 2500 tape & reel 0°C to70°C 8533AG-01LN ICS8533A01LN 20 lead "Lead Free/Annealed" TSSOP tube 0°C to 70°C 8533AG-01LNT ICS8533A01LN 20 lead "Lead Free/Annealed" TSSOP 2500 tape & reel 0°C to70°C 8533AG-01LF ICS8533A01LF 20 lead "Lead Free" TSSOP tube 0°C to 70°C 8533AG-01LFT ICS8533A01LF 20 lead "Lead Free" TSSOP 2500 tape & reel 0°C to70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8533AG-01 www.idt.com 15 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER REVISION HISTORY SHEET Rev Table 4C Page 4 Description of Change VPP values changed from 0.1 Min. to 0.15 Min. VCMR values changed from 0.13 Min., 1.3 Max. to 1.5 Min, VCC Max. 4D 5 Deleted VIH and VIL rows. 5 5 5 5 tR values changed from 100 Min. to 300 Min, and added 700 Max. tF values changed from 100 Min., 600 Max. to 300 Min. to 700 Max. For tR and tF rows changed test conditions from 30% to 70% to 20% to 80%. tjit(cc) values changed 150 Max. to 0 Max. Deleted tS and tH rows. 5/22/01 B B Date 6/4/01 B 4D 5 VPP values changed from 0.15 Min., 1.3 Max. to 0.3 Min., 1 Max. VCMR values changed from 1.5 Min., to VEE + 1.5 Min. C 4B 5 4 5 VIH values changed from 3.765 Max. to VCC + 0.3 Max. Deleted tjit(cc) row. 10/15/01 6/28/01 C 6, 7 Revised Parameter Measurement diagrams. 10/18/01 C 3 Updated Figure 1, CLK_EN Timing Diagram. 11/1/01 C 8 Added Termination for LVPECL Outputs section. 5/28/02 C 6 T2 D D D T4D T5 T9 T9 T4D E F 8533AG-01 1 2 4 5 5 6 8 9 10 15 10 15 5 11 - 12 T9 15 T9 15 17 Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V ± 0.165V from VEE = -1.3V ± 0.135V. Added RMS Jitter to Features section. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Changed Outputs Absolute Maximum Rating. LVPECL Table - changed VSWING 0.85V max. to 1.0V max. AC Characteristics Table - added RMS jitter. Added Additive Phase Jitter Section. Updated LVPECL Output Termination diagrams. Added Differential Clock Input Interface. Added LVPECL Clock Input Interface. Updated format throughout data sheet. Added Lead Free Annealed part number to Ordering Information table. Updated LVPECL Clock Input Interface section. Ordering Information Table - added Lead Free part number. LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCC- 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. Ordering Information Table - added lead-free note. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. www.idt.com 16 10/03/02 10/12/03 2/9/04 6/17/04 4/12/07 8/4/10 REV. F AUGUST 4, 2010 ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 [email protected] © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8533AG-01 www.idt.com 17 REV. F AUGUST 4, 2010