IDT ADC1613S065HN-C1

ADC1613S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC1613S is a single channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1613S is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it outputs data in serial mode via a
single differential lane, which complies with the JESD204A standard. The integration of
Serial Peripheral Interface allows the user to easily configure the ADCs and the serial
output modes. The device also includes a programmable full-scale SPI to allow a flexible
input voltage range from 1 V (p-p) to 2 V (p-p).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1613S ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
 SNR, 72.3 dBFS; SFDR, 88 dBc
 Sample rates up to 125 Msps
 Single channel, 16-bit pipelined ADC
core
 3 V, 1.8 V power supplies
 Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
 Serial output
 Power-down mode and Sleep mode
 Pin compatible with ADC1413S series,
ADC1213S series, and ADC1113S125
 Input bandwidth, 600 MHz
 Power dissipation, 550 mW at 80 Msps
 SPI register programming
 Duty cycle stabilizer
 High Intermediate Frequency (IF)
capability
 Offset binary, two’s complement, gray
code
 Compliant with JESD204A serial
transmission standard
 HVQFN32 package
3. Applications
 Wireless and wired broadband
communications
 Spectral analysis
 Ultrasound equipment
 Portable instrumentation
 Imaging systems
®
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
ADC1613S125HN-C1
125
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7  7  0.8 mm
ADC1613S105HN-C1
105
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7  7  0.8 mm
ADC1613S080HN-C1
80
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7  7  0.8 mm
ADC1613S065HN-C1
65
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7  7  0.8 mm
Name
Description
ADC1613S_SER 3
Product data sheet
Version
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
2 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
5. Block diagram
SDIO
SCLK
CS
SPI
SYNCP
SYNCN
CLKP
DLL
PLL
CLKM
ADC CORE
16-BIT
PIPELINED
D15 to D0
INM
8-bit
8-bit
ENCODER 8-bit/10-bit A
OTR
T/H
INPUT
STAGE
SCRAMBLER A
INP
FRAME ASSEMBLY
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SERIALIZER A
CMLP
OUTPUT
BUFFER A
CMLN
10-bit
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1613S
OTR
SENSE
VDDD
AGND
DGND
VDDA
001aam779
Fig 1.
Block diagram
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
3 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
6. Pinning information
25 SYNCP
26 SYNCN
27 VDDD
28 DGND
29 VDDA
30 AGND
terminal 1
index area
31 SENSE
32 VREF
6.1 Pinning
CLKP
1
24 n.c.
CLKM
2
23 DGND
AGND
3
22 DGND
REFB
4
21 VDDD
ADC1613S
7
18 VDDD
INP
8
17 DGND
11
SCLK
VDDA
DGND 16
INM
VDDD 15
19 CMLP
OTR 14
6
CS 13
VCM
SDIO 12
20 CMLN
VDDA 10
5
9
REFT
001aam781
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type [1]
Description
CLKP
1
I
clock input
CLKM
2
I
complementary clock input
AGND
3
G
analog ground
REFB
4
O
ADC bottom reference
REFT
5
O
ADC top reference
VCM
6
O
ADC output common voltage
INM
7
I
ADC complementary analog input
INP
8
I
ADC analog input
VDDA
9
P
analog power supply 3 V
VDDA
10
P
analog power supply 3 V
SCLK
11
I
SPI clock
SDIO
12
I/O
SPI data input/output
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
4 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
CS
13
I
chip select
OTR
14
O
out-of-range information
VDDD
15
P
digital power supply 1.8 V
DGND
16
G
digital ground
DGND
17
G
digital ground
VDDD
18
P
digital power supply 1.8 V
CMLP
19
O
serial output
CMLN
20
O
serial complementary output
VDDD
21
P
digital power supply 1.8 V
DGND
22
G
digital ground
DGND
23
G
digital ground
n.c.
24
-
not connected
SYNCP
25
I
positive synchronization signal from the receiver
SYNCN
26
I
negative synchronization signal from the receiver
VDDD
27
P
digital power supply 1.8 V
DGND
28
G
digital ground
VDDA
29
P
analog power supply 3 V
AGND
30
G
analog ground
SENSE
31
I
reference programming pin
VREF
32
I/O
voltage reference input/output
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDDA
Conditions
Min
Max
Unit
analog supply voltage
0.4
+4.6
V
VDDD(1V8)
digital supply voltage (1.8 V)
0.4
+2.5
V
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
125
C
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
[1]
25.6
K/W
Rth(j-c)
thermal resistance from junction to case
[1]
8.6
K/W
[1]
Conditions
Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
5 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
9. Static characteristics
Table 5.
Static characteristics [1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA
analog supply voltage
2.85
3.0
3.4
V
VDDD(1V8)
digital supply voltage
(1.8 V)
1.65
1.8
1.95
V
IDDA
analog supply current
fclk = 125 Msps;
fi = 70 MHz
-
185
-
mA
IDDD(1V8)
digital supply current
(1.8 V)
fclk = 125 Msps;
fi = 70 MHz
-
75
-
mA
Ptot
total power dissipation
fclk = 125 Msps
-
690
-
mW
fclk = 105 Msps
-
625
-
mW
fclk = 80 Msps
-
550
-
mW
fclk = 65 Msps
-
495
-
mW
Power-down mode
-
30
-
mW
Standby mode
-
150
-
mW
P
power dissipation
Digital inputs
Clock inputs: pins CLKP and CLKM (AC-coupled)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif
differential clock input
voltage
peak-to-peak
-
1.6
-
V
differential clock input
voltage
peak
0.8
3.0
-
V
Sine
Vi(clk)dif
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL
LOW-level input voltage
-
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
-
V
SPI: pins CS, SDIO, and SCLK
VIL
LOW-level input voltage
0
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
VDDA
V
IIL
LOW-level input current
10
-
+10
A
IIH
HIGH-level input current
50
-
+50
A
CI
input capacitance
-
4
-
pF
track mode
5
-
+5
A
Analog inputs: pins INP and INM
II
input current
RI
input resistance
track mode
-
15
-

CI
input capacitance
track mode
-
5
-
pF
VI(cm)
common-mode input
voltage
track mode
1.1
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
peak-to-peak
1
-
2
V
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
6 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 5.
Symbol
Static characteristics …continued[1]
Parameter
Conditions
Min
Typ
Max
Unit
Voltage controlled regulator output: pin VCM
VO(cm)
common-mode output
voltage
-
0.5VDDA
-
V
IO(cm)
common-mode output
current
-
4
-
mA
output
0.5
-
1
V
input
0.5
-
1
V
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
Data outputs: CMLP, CMLN
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 000
VOL
VOH
LOW-level output
voltage
DC-coupled; output
-
1.5
-
V
AC-coupled
-
1.35
-
V
HIGH-level output
voltage
DC-coupled; output
-
1.8
-
V
AC-coupled
-
1.65
-
V
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 001
VOL
VOH
LOW-level output
voltage
DC-coupled; output
-
1.45
-
V
AC-coupled
-
1.275
-
V
HIGH-level output
voltage
DC-coupled; output
-
1.8
-
V
AC-coupled
-
1.625
-
V
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 010
VOL
VOH
LOW-level output
voltage
DC-coupled; output
-
1.4
-
V
AC-coupled
-
1.2
-
V
HIGH-level output
voltage
DC-coupled; output
-
1.8
-
V
AC-coupled
-
1.6
-
V
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 011
VOL
LOW-level output
voltage
DC-coupled; output
-
1.35
-
V
AC-coupled
-
1.125
-
V
VOH
HIGH-level output
voltage
DC-coupled; output
-
1.8
-
V
AC-coupled
-
1.575
-
V
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 100
VOL
VOH
LOW-level output
voltage
DC-coupled; output
-
1.3
-
V
AC-coupled
-
1.05
-
V
HIGH-level output
voltage
DC-coupled; output
-
1.8
-
V
AC-coupled
-
1.55
-
V
Serial configuration: SYNCP, SYNCN
VIL
LOW-level input voltage
differential; input
-
0.95
-
V
VIH
HIGH-level input voltage differential; input
-
1.47
-
V
Accuracy
INL
integral non-linearity
DNL
differential non-linearity
Eoffset
offset error
guaranteed no missing
codes
5
-
+5
LSB
0.95
0.5
+0.95
LSB
-
2
-
mV
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
7 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 5.
Static characteristics …continued[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EG
gain error
full-scale
-
 0.5
-
%
power supply rejection
ratio
200 mV (p-p) on
pin VDDA; fi = DC
-
54
-
dB
Supply
PSRR
[1]
Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature
range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP)  Vi(INM) = 1 dBFS; internal reference mode; 100  differential
applied to serial outputs; unless otherwise specified.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
8 of 37
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Integrated Device Technology
ADC1613S_SER 3
Product data sheet
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6.
Dynamic characteristics [1]
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
2H
second harmonic
level
fi = 3 MHz
-
89
-
-
89
-
-
88
-
-
90
-
dBc
fi = 30 MHz
-
88
-
-
88
-
-
88
-
-
89
-
dBc
fi = 70 MHz
-
87
-
-
87
-
-
86
-
-
87
-
dBc
fi = 170 MHz
-
84
-
-
84
-
-
83
-
-
85
-
dBc
fi = 3 MHz
-
88
-
-
88
-
-
87
-
-
89
-
dBc
fi = 30 MHz
-
87
-
-
87
-
-
87
-
-
88
-
dBc
fi = 70 MHz
-
86
-
-
86
-
-
85
-
-
86
-
dBc
fi = 170 MHz
-
83
-
-
83
-
-
82
-
-
84
-
dBc
fi = 3 MHz
-
85
-
-
85
-
-
84
-
-
86
-
dBc
fi = 30 MHz
-
84
-
-
84
-
-
84
-
-
85
-
dBc
fi = 70 MHz
-
83
-
-
83
-
-
82
-
-
83
-
dBc
fi = 170 MHz
-
80
-
-
80
-
-
79
-
-
81
-
dBc
fi = 3 MHz
-
11.7
-
-
11.7
-
-
11.7
-
-
11.6
-
bits
fi = 30 MHz
-
11.6
-
-
11.6
-
-
11.6
-
-
11.6
-
bits
fi = 70 MHz
-
11.5
-
-
11.5
-
-
11.5
-
-
11.5
-
bits
3H
Rev. 03 — 2 July 2012
THD
ENOB
SFDR
total harmonic
distortion
effective number of
bits
signal-to-noise ratio
spurious-free
dynamic range
ADC1613S080
ADC1613S105
ADC1613S125
Unit
9 of 37
© IDT 2012. All rights reserved.
fi = 170 MHz
-
11.4
-
-
11.4
-
-
11.4
-
-
11.4
-
bits
fi = 3 MHz
-
72.3
-
-
72.2
-
-
72.0
-
-
71.6
-
dBFS
fi = 30 MHz
-
71.5
-
-
71.4
-
-
71.4
-
-
71.3
-
dBFS
fi = 70 MHz
-
70.9
-
-
70.9
-
-
70.8
-
-
70.7
-
dBFS
fi = 170 MHz
-
70.4
-
-
70.3
-
-
70.2
-
-
70.1
-
dBFS
fi = 3 MHz
-
88
-
-
88
-
-
87
-
-
89
-
dBc
fi = 30 MHz
-
87
-
-
87
-
-
87
-
-
88
-
dBc
fi = 70 MHz
-
86
-
-
86
-
-
85
-
-
86
-
dBc
fi = 170 MHz
-
83
-
-
83
-
-
82
-
-
84
-
dBc
ADC1613S series
SNR
third harmonic level
ADC1613S065
Single 16-bit ADC; serial JESD204A interface
Symbol
Symbol
Dynamic characteristics …continued[1]
Parameter
Conditions
ADC1613S065
Min
IMD
ct(ch)
[1]
intermodulation
distortion
channel crosstalk
Typ
Max
ADC1613S080
Min
Typ
Max
ADC1613S105
Min
ADC1613S125
Typ
Max
Min
Typ
Max
Integrated Device Technology
ADC1613S_SER 3
Product data sheet
Table 6.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Unit
fi = 3 MHz
-
89
-
-
89
-
-
88
-
-
89
-
dBc
fi = 30 MHz
-
88
-
-
88
-
-
88
-
-
88
-
dBc
fi = 70 MHz
-
87
-
-
87
-
-
86
-
-
86
-
dBc
fi = 170 MHz
-
84
-
-
85
-
-
83
-
-
84
-
dBc
fi = 70 MHz
-
100
-
-
100
-
-
100
-
-
100
-
dBc
Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at
VDDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP)  Vi(INM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
Table 7.
Rev. 03 — 2 July 2012
Symbol
Clock and digital output characteristics [1]
Parameter
Conditions
ADC1613S065
Min
Typ
Max
ADC1613S080
Min
Typ
Max
ADC1613S105
Min
Typ
Max
ADC1613S125
Min
Typ
Max
Unit
pins CLKP and CLKM
clock frequency
45
-
65
60
-
80
75
-
105
100
-
125
Msps
tlat(data)
data latency time
clock cycles
307
-
850
250
-
283
190
-
226
160
-
170
ns
clk
clock duty cycle
DCS_EN = 1:
en
30
50
70
30
50
70
30
50
70
30
50
70
%
td(s)
sampling delay time
-
0.8
-
-
0.8
-
-
0.8
-
-
0.8
-
ns
twake
wake-up time
-
76
-
-
76
-
-
76
-
-
76
-
ns
Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at
VDDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP)  Vi(INM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs; unless otherwise specified.
10 of 37
© IDT 2012. All rights reserved.
ADC1613S series
[1]
Single 16-bit ADC; serial JESD204A interface
fclk
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC-coupling with two different receiver common-mode voltages
005aaa088
Fig 3.
Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4.
Eye diagram at 2 V receiver common-mode
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
11 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
10.4 SPI timing
Table 8.
SPI timing characteristics [1]
Symbol
Parameter
tw(SCLK)
Min
Typ
Max
Unit
SCLK pulse width
-
40
-
ns
tw(SCLKH)
SCLK HIGH pulse
width
-
16
-
ns
tw(SCLKL)
SCLK LOW pulse
width
-
16
-
ns
tsu
set-up time
data to
SCLK HIGH
-
5
-
ns
CS to
SCLK HIGH
-
5
-
ns
data to
SCLK HIGH
-
2
-
ns
CS to
SCLK HIGH
-
2
-
ns
-
25
-
MHz
hold time
th
fclk(max)
[1]
Conditions
maximum clock
frequency
Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values
are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD(1V8) = 1.8 V;
Vi(INP)  Vi(INM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs; unless
otherwise specified.
tsu
tsu
th
CS
tw(SCLKL)
th
tw(SCLKH)
tw(SCLK)
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 5.
SPI timing
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
12 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1613S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
package
ESD
parasitics
switch
INP
Ron = 15 Ω
8
Cs
internal
clock
switch
Ron = 15 Ω
INM
7
Cs
internal
clock
005aaa185
Fig 6.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
13 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
R
INP
C
R
INM
005aaa073
Fig 7.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Table 9.
RC coupling versus input frequency, typical values
Input frequency (MHz)
Resistance ()
Capacitance (pF)
3
25
12
70
12
8
170
12
8
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
ADT1-1WT
100 nF
analog
input
25 Ω
100 nF
INP
25 Ω
12 pF
100 nF
100 nF
25 Ω
25 Ω
INM
VCM
100 nF
100 nF
005aaa044
Fig 8.
Single transformer configuration
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
14 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
ADT1-1WT
analog
input
100 nF
ADT1-1WT
50 Ω
12 Ω
INP
50 Ω
8.2 pF
50 Ω
100 nF
50 Ω
12 Ω
INM
VCM
100 nF
100 nF
005aaa045
Fig 9.
Dual transformer configuration
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1613S has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an
SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent
reference circuit is shown in Figure 10. External reference is also possible by providing a
voltage on pin VREF as described in Figure 14.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
15 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
REFT
REFERENCE
AMP
REFB
VREF
EXT_ref
BUFFER
EXT_ref
BANDGAP
REFERENCE
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 10. Reference equivalent schematic
Table 10 shows how to choose between the different internal/external modes:
Table 10.
Reference modes
Mode
SPI bit, “Internal
reference”
SENSE pin
VREF pin
Full-scale,
(V (p-p))
Internal (Figure 11)
0
GND
330 pF capacitor 2
to GND
Internal (Figure 12)
0
VREF pin = SENSE pin and
330 pF capacitor to GND
1
Internal, SPI mode
(Figure 13)
1
VREF pin = SENSE pin and
330 pF capacitor to GND
1 to 2
External (Figure 14)
0
VDDA
External voltage 1 to 2
from 0.5 V to 1 V
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
16 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
V
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
0.1 μF
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
VDDA
005aaa118
Fig 13. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
005aaa119
Fig 14. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Table 11.
Reference modes
INTREF[2:0]
Level
Full-scale (V (p-p))
000
0 dB
2
001
1 dB
1.78
010
2 dB
1.59
011
3 dB
1.42
100
4 dB
1.26
101
5 dB
1.12
110
6 dB
1
111
not used
x
11.2.3 Common-mode output voltage (VO(cm))
An 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, these pins can be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
17 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
package
ESD
parasitics
COMMON-MODE
REFERENCE
1.5 V
VCM
0.1 μF
ADC core
005aaa051
Fig 15. Reference equivalent schematic
11.2.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to
0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
11.3 Clock input
11.3.1 Drive modes
The ADC1613S can be driven differentially (LVPECL). It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor).
LVCMOS
clock input
CLKP
CLKP
CLKM
LVCMOS
clock input
005aaa174
a. Rising edge LVCMOS
CLKM
005aaa053
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
18 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Sine
clock input
CLKP
Sine
clock input
CLKP
CLKM
CLKM
005aaa054
005aaa173
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
LVPECL
clock input
CLKM
005aaa172
c. LVPECL clock input
Fig 17. Differential clock input
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal 5 k resistors.
package
ESD
parasitics
CLKP
Vcm(clk)
SE_SEL
SE_SEL
5 kΩ
5 kΩ
CLKM
005aaa081
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
19 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12.
Duty cycle stabilizer
bit DCS_EN
Description
0
duty cycle stabilizer disable
1
duty cycle stabilizer enable
11.3.4 Clock input divider
The ADC1613S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
VDDD
VDDD
50 Ω
50 Ω
CMLP
100 Ω
RECEIVER
CMLN
+
12 mA to 26 mA
AGND
005aaa197
Fig 19. CML output connection to the receiver in DC-coupling
The output should be terminated when 100  (typical) is reached at the receiver side.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
20 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
VDDD
50 Ω
50 Ω
CMLP
10 nF
100 Ω
CMLN
RECEIVER
10 nF
-
+
12 mA to 26 mA
005aaa187
Fig 20. CML output connection to the receiver in AC-coupling
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functions of the JESD204A
standard. This ensures signal integrity and guarantees the clock and the data recovery at
the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
N bits from Cr0 +
CS bits for control
F octets
TX transport layer
FRAME
TO
OCTETS
SCRAMBLER
SYNC~
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
SER
LANE 0
TX CONTROLLER
N' = N + CS
S samples per frame cycle
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
M × (N' × S) bits
L × (F) octets
L octets
005aaa198
Fig 21. General overview of the JESD204A serializer
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
21 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
ADC_MODE[1:0]
PRBS
DUMMY
SCR_IN_MODE
11
16
10
16
N
AND
CS
LANE_MODE[1:0]
8
N + CS
PLL
AND
DLL
16
00
FRAME
ASSEMBLY
×1
frame CLK
×F
character CLK
× 10F
8-bit/
10-bit
SCR
PRBS
ADC_PD
ADC
00
01
FSM
(frame assembly,
character
replication,
ILA,
test mode)
10
00
'0'
01
'0/1'
10
PRBS
11
LANE_POL
SER
SWING_SEL[2:0]
bit CLK
001aam780
sync_request
Fig 22. Detailed view of the JESD204A serializer with debug functionality
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13.
Output codes versus input voltage
INP-INM (V)
Offset binary
Two’s complement
OTR
< 1
0000 0000 0000 0000
1000 0000 0000 0000
1
1
0000 0000 0000 0000
1000 0000 0000 0000
0
0.99996948
0000 0000 0000 0001
1000 0000 0000 0001
0
0.99993896
0000 0000 0000 0010
1000 0000 0000 0010
0
0.99990845
0000 0000 0000 0011
1000 0000 0000 0011
0
0.99987793
0000 0000 0000 0100
1000 0000 0000 0100
0
....
....
....
0
0.00006104
0111 1111 1111 1110
1111 1111 1111 1110
0
0.00003052
0111 1111 1111 1111
1111 1111 1111 1111
0
0
1000 0000 0000 0000
0000 0000 0000 0000
0
+0.00003052
1000 0000 0000 0001
0000 0000 0000 0001
0
+0.00006104
1000 0000 0000 0010
0000 0000 0000 0010
0
....
....
....
0
+0.99987793
1111 1111 1111 1011
0111 1111 1111 1011
0
+0.99990845
1111 1111 1111 1100
0111 1111 1111 1100
0
+0.99993896
1111 1111 1111 1101
0111 1111 1111 1101
0
+0.99996948
1111 1111 1111 1110
0111 1111 1111 1110
0
+1
1111 1111 1111 1111
0111 1111 1111 1111
0
> +1
1111 1111 1111 1111
0111 1111 1111 1111
1
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
22 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1613S serial interface is a synchronous serial communications port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK acts as the serial clock and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with N bytes, depending on the content of the instruction byte
(see Table 14).
Table 14.
Instruction bytes for the SPI
MSB
LSB
Bit
7
6
5
Description
R/W[1]
W1
A7
A6
[1]
4
3
2
1
0
W0
A12
A11
A10
A9
A8
A5
A4
A3
A2
A1
A0
R/W indicates whether a read or write transfer occurs after the instruction byte
Table 15.
Read or Write mode access description
R/W[1]
Description
0
Write mode operation
1
Read mode operation
[1]
Bits W1 and W0 indicate the number of bytes transferred.
Table 16.
Number of bytes to be transferred
W1
W0
Number of bytes transferred
0
0
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but is always
a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
23 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
CS
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
Instruction bytes
D4
D3
D2
Register N (data)
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
24 of 37
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17.
Integrated Device Technology
ADC1613S_SER 3
Product data sheet
11.6.2 Channel control
Register allocation map
Address Register name
(hex)
Access[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default[2]
(bin)
-
-
-
-
-
-
ENABLE
-
1111 1111
SW_RST
-
-
-
-
-
Bit definition
ADC control register
SPI control
R/W
0005
Reset and
R/W
Operating modes
0006
Clock
R/W
-
-
-
SE_SEL
DIFF_SE
0008
Vref
R/W
-
-
-
-
INTREF_EN
0013
Offset
R/W
-
-
0014
Test pattern 1
R/W
-
-
0015
Test pattern 2
R/W
TESTPAT_2[15:8]
0000
0000
0016
Test pattern 3
R/W
TESTPAT_3[7:0]
0000
0000
PD[1:0]
CLKDIV2_
SEL
0000
0000
DCS_EN
INTREF[2:0]
0000
0000
DIG_OFFSET[5:0]
-
-
-
0000
000*
0000
0000
TESTPAT_1[2:0]
0000
0000
JESD204A control
Ser_Status
R
RXSYNC
_ERROR
0802
Ser_Reset
R/W
SW_RST
0805
Ser_Control1
R/W
0
0808
Ser_Analog_Ctrl
R/W
0
0809
Ser_ScramblerA
R/W
0
RESERVED[2:0]
0
0
RESERVED SYNC_POL
0
0
0
0
POR_TST
RESERVED
0110
0000
0
FSM_SW_
RST
0
0
0
0000
0000
SYNC_
SINGLE_
ENDED
1
REV_
SCR
0
0
LSB_INIT[6:0]
REV_
REV_SERIAL 0100
ENCODER
1001
SWING_SEL[2:0]
0000
0011
25 of 37
© IDT 2012. All rights reserved.
0000
0000
ADC1613S series
0801
Single 16-bit ADC; serial JESD204A interface
Rev. 03 — 2 July 2012
0003
Register allocation map …continued
Access[1]
080A
Ser_ScramblerB
R/W
080B
Ser_PRBS_Ctrl
R/W
0820
Cfg_0_DID
R
0821
Cfg_1_BID
R/W*
0
0
0
0
0822
Cfg_3_SCR_L
R/W*
SCR
0
0
0
0
0823
Cfg_4_F
R/W*
0
0
0
0
0
0824
Cfg_5_K
R/W*
0
0
0
0825
Cfg_6_M
R/W*
0
0
0
0
0826
Cfg_7_CS_N
R/W*
0
CS[0]
0
0
0827
Cfg_8_Np
R/W*
0
0
0
0828
Cfg_9_S
R/W*
0
0
0
0
0
0
0829
Cfg_10_HD_CF
R/W*
HD
0
0
0
0
0
082D
Cfg_02_2_LID
R/W*
0
0
0
084D
Cfg02_13_FCHK R
0871
Lane_0_Ctrl
R/W
0
SCR_IN_
MODE
LANE_MODE[1:0]
0
LANE_
POL
0
LANE_PD
0000
0000
0891
ADC_0_Ctrl
R/W
0
0
ADC_MODE[1:0]
0
0
0
ADC_PD
0000
0000
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
MSB_INIT[7:0]
0
1111 1111
0
PRBS_TYPE[1:0]
DID[7:0]
0000
0000
1110
1101
BID[3:0]
0
0000
1010
0
L
F[2:0]
0000
0000
0000 0***
K[4:0]
0
Default[2]
(bin)
000* ****
0
0
M
N[3:0]
0000
000*
0100
0110
NP[4:0]
0000
1111
0
S
CF[1:0]
*000
0000
0001
1100
FCHK[7:0]
**** ****
26 of 37
© IDT 2012. All rights reserved.
[1]
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
[2]
an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler).
ADC1613S series
LID[4:0]
0000
0000
Single 16-bit ADC; serial JESD204A interface
Rev. 03 — 2 July 2012
Address Register name
(hex)
Integrated Device Technology
ADC1613S_SER 3
Product data sheet
Table 17.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register SPI control (address 0003h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2
-
-
111111
not used
1
ENABLE
R/W
0
-
-
ADC SPI control enable:
0
ADC does not get the next SPI command
1
ADC gets the next SPI command
1
not used
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit
Symbol
Access
7
SW_RST
R/W
6 to 2
-
-
1 to 0
PD[1:0]
R/W
Value
Description
reset digital part:
0
no reset
1
performs a reset of the digital part
00000
not used
power-down mode:
00
normal (power-up)
01
full power-down
10
sleep
11
normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4
SE_SEL
R/W
3
DIFF_SE
-
-
1
CLKDIV2_SEL
R/W
DCS_EN
select CLKM input
1
select CLKP input
R/W
2
0
select SE clock input pin:
0
differential/single ended clock input select:
0
fully differential
1
single-ended
0
not used
select clock input divider by 2:
0
disable
1
enable
R/W
duty cycle stabilizer enable:
0
disable
1
enable
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
27 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 21. Register Vref (address 0008h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
-
-
0000
not used
3
INTREF_EN
R/W
enable internal programmable VREF mode:
0
disable
1
2 to 0
INTREF[2:0]
R/W
enable
programmable internal reference:
000
0 dB (FS = 2 V)
001
1 dB (FS = 1.78 V)
010
2 dB (FS = 1.59 V)
011
3 dB (FS = 1.42 V)
100
4 dB (FS = 1.26 V)
101
5 dB (FS = 1.12 V)
110
6 dB (FS = 1 V)
111
not used
Table 22. Digital offset adjustment (address 0013h)
Default values are highlighted.
Register offset
Decimal
DIG_OFFSET[5:0]
+31
011111
+31 LSB
...
...
...
0
000000
0
...
...
...
32
100000
32 LSB
Table 23. Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
TESTPAT_1[2:0]
R/W
digital test pattern:
000
off
001
mid-scale
010
 FS
011
+ FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern, to be written in register 0015h and 0016h
110
‘010101...’
111
‘101010...’
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
28 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit
Symbol
Access
Value
7 to 0
TESTPAT_2[15:8]
R/W
00000000 custom digital test pattern (bit 15 to 8)
Description
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit
Symbol
Access
Value
7 to 0
TESTPAT_3[7:0]
R/W
00000000 custom digital test pattern (bit 7 to 0)
Description
11.6.4 JESD204A digital control registers
Table 26. SER_Status (address 0801h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
RXSYNC_ERROR
R/W
0
set to 1 when a synchronization error occurs
6 to 4
RESERVED[2:0]
R
110
reserved
3 to 2
-
-
00
not used
1
POR_TST
R
0
power-on-reset
0
RESERVED
-
0
reserved
Table 27. SER_Reset (address 0802h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
0
initiates a software reset of the JEDEC204A unit
6 to 4
-
-
000
not used
3
FSM_SW_RST
R/W
0
initiates a software reset of the internal state machine of
JEDEC204A unit
2 to 0
-
-
000
not used
Table 28. SER_Control1 (address 0805h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
RESERVED
-
0
reserved
5
SYNC_POL
R/W
defines the sync signal polarity:
0
1
4
SYNC_SINGLE_ENDED R/W
3
-
-
2
REV_SCR
-
synchronization signal is active LOW
synchronization signal is active HIGH
defines the input mode of the sync signal:
0
synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
1
not used
LSB are swapped to MSB at the scrambler input:
0
disable
1
enable
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
29 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 28. SER_Control1 (address 0805h) …continued
Default values are highlighted.
Bit
Symbol
Access
1
REV_ENCODER
-
0
REV_SERIAL
Value
Description
LSB are swapped to MSB at the 8-bit/10-bit encoder input:
0
disable
1
enable
-
LSB are swapped to MSB at the lane input:
0
disable
1
enable
Table 29. SER_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
SWING_SEL[2:0]
R/W
011
defines the swing output for the lane pads
Table 30. SER_ScramblerA (address 0809h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6 to 0
LSB_INIT[6:0]
R/W
0000000
defines the initialization vector for the scrambler polynomial
(lower)
Table 31. SER_ScramblerB (address 080Ah)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MSB_INIT[7:0]
R/W
11111111
defines the initialization vector for the scrambler polynomial
(upper)
Table 32. SER_PRBS_Ctrl (address 080Bh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2
1 to 0
-
-
000000
not used
PRBS_TYPE[1:0]
R/W
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
01
PRBS-7
10
PRBS-23
11
PRBS-31
Table 33. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
DID[7:0]
R
11101101 defines the device (= link) identification number
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
30 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 34. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
-
-
0000
not used
3 to 0
BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 35. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
SCR
R/W
0
scrambling enabled
6 to 1
-
-
000000
not used
0
L
R/W
0
defines the number of lanes per converter device, minus 1
Description
Table 36. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit
Symbol
Access
Value
7 to 3
-
-
00000
not used
2 to 0
F[2:0]
R/W
***
defines the number of octets per frame, minus 1
Table 37. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
K[4:0]
R/W
*****
defines the number of frames per multiframe, minus 1
Table 38. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 1
-
-
0000000
not used
0
M
R/W
*
defines the number of converters per device, minus 1
Table 39. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
CS[0]
R/W
1
defines the number of control bits per sample, minus 1
5 to 4
-
-
00
not used
3 to 0
N[3:0]
R/W
0110
defines the converter resolution
Table 40. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
NP[4:0]
R/W
01111
defines the total number of bits per sample, minus 1
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
31 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 41. Cfg_9_S (address 0828h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 1
-
-
0000000
not used
0
S
R/W
0
defines number of samples per converter per frame cycle
Table 42. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
HD
R/W
*
defines high density format
6 to 2
-
R
00000
not used
1 to 0
CF[1:0]
R/W
00
defines number of control words per frame clock cycle per link.
Value
Description
Table 43. Cfg02_2_LID (address 082Dh)
Default values are highlighted.
Bit
Symbol
Access
7 to 5
-
-
000
not used
4 to 0
LID[4:0]
R/W
11100
defines lane identification number
Table 44. Cfg01_13_FCHK (address 084Dh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
********
defines the checksum value for lane
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 45. Lane_0_ctrl (address 0871h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
SCR_IN_MODE
R/W
5 to 4
3
LANE_MODE[1:0]
-
defines the input type for scrambler and 8-bit/10-bit units:
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRSB
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
R/W
-
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
01
constant mode: lane output is set to a constant (0  0)
10
toggle mode: lane output is toggling between 0  0 and 0  1
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
0
not used
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
32 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
Table 45. Lane_0_ctrl (address 0871h) …continued
Default values are highlighted.
Bit
Symbol
Access
2
LANE_POL
R/W
1
RESERVED
R/W
0
Lane_PD
R/W
Value
Description
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
0
reserved
lane power-down control:
0
lane is operational
1
lane is in Power-down mode
Table 46. ADC_0_ctrl (address 0891h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
-
-
00
not used
5 to 4
ADC_MODE[1:0]
R/W
3 to 1
-
-
0
ADC_PD
R/W
defines input type of JESD204A unit
00 (reset)
ADC output is connected to the JESD204A input
01
not used
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_ctrl register)
000
not used
ADC power-down control:
0
ADC is operational
1
ADC is in Power-down mode
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
33 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
12. Package outline
HVQFN32R: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; resin based; body 7 x 7 x 0.8 mm
B
D
SOT1152-1
A
terminal 1
index area
A
E
detail X
e1
e
∅v
∅w
b
C A B
C
C
1/2 e
L1
9
y
y1 C
16
L
8
17
e
Eh
e2
1/2 e
1
24
terminal 1
index area
32
25
X
Dh
0
2.5
5 mm
scale
Dimensions
Unit
mm
A
b
max 0.90 0.28
nom 0.80 0.23
min 0.75 0.18
D
Dh
E
7.1
7.0
6.9
4.05
4.00
3.95
7.1
7.0
6.9
Eh
e
e1
e2
L
L1
4.05
0.55 0.10
4.00 0.65 4.55 4.55 0.50 0.05
3.95
0.45 0.00
v
0.1
w
y
0.05 0.08
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
References
Outline
version
IEC
JEDEC
JEITA
SOT1152-1
---
---
---
sot1152-1_po
European
projection
Issue date
09-10-13
09-11-16
Fig 24. Package outline SOT1152-1 (HVQFN32)
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
34 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
13. Abbreviations
Table 47.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
DCS
Duty Cycle Stabilizer
ESD
ElectroStatic Discharge
IF
Intermediate Frequency
IMD
InterModulation Distortion
LSB
Least Significant Bit
LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
MSB
Most Significant Bit
OTR
OuT-of-Range
PRBS
Pseudo-Random Binary Sequence
SFDR
Spurious-Free Dynamic Range
SNR
Signal-to-Noise Ratio
SPI
Serial Peripheral Interface
TX
Transmitter
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
35 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
14. Revision history
Table 48.
Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
ADC1613S_SER v.3
20120702
Product data sheet
-
ADC1613S_SERT v.2
ADC1613S_SER v.2
20110609
Product data sheet
-
ADC1613S_SERT v.1
Modifications:
ADC1613S_SER v.1
•
Section 10.2 “Clock and digital output timing” has been updated.
20110314
Product data sheet
-
-
15. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
ADC1613S_SER 3
Product data sheet
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
36 of 37
ADC1613S series
Integrated Device Technology
Single 16-bit ADC; serial JESD204A interface
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
10.4
11
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . . 10
Serial output timing . . . . . . . . . . . . . . . . . . . . . 11
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 13
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input stage description . . . . . . . . . . . . . . . . . . 13
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System reference and power management . . 15
Internal/external reference . . . . . . . . . . . . . . . 15
11.2.2
Programmable full-scale . . . . . . . . . . . . . . . .
11.2.3
Common-mode output voltage (VO(cm)) . . . . .
11.2.4
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1
Drive modes. . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2
Equivalent input circuit . . . . . . . . . . . . . . . . . .
11.3.3
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . .
11.3.4
Clock input divider . . . . . . . . . . . . . . . . . . . . .
11.4
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . .
11.4.1
Serial output equivalent circuit . . . . . . . . . . . .
11.5
JESD204A serializer . . . . . . . . . . . . . . . . . . .
11.5.1
Digital JESD204A formatter . . . . . . . . . . . . . .
11.5.2
ADC core output codes versus input voltage .
11.6
Serial Peripheral Interface (SPI) . . . . . . . . . .
11.6.1
Register description . . . . . . . . . . . . . . . . . . . .
11.6.2
Channel control . . . . . . . . . . . . . . . . . . . . . . .
11.6.3
Register description . . . . . . . . . . . . . . . . . . . .
11.6.3.1 ADC control registers. . . . . . . . . . . . . . . . . . .
11.6.4
JESD204A digital control registers . . . . . . . .
12
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
14
Revision history . . . . . . . . . . . . . . . . . . . . . . .
15
Contact information . . . . . . . . . . . . . . . . . . . .
16
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1613S_SER 3
Product data sheet
17
17
18
18
18
19
20
20
20
20
21
21
22
23
23
25
27
27
29
34
35
36
36
37
© IDT 2012. All rights reserved.
Rev. 03 — 2 July 2012
37 of 37