LTC4380 - Low Quiescent Current Surge Stopper

LTC4380
Low Quiescent Current
Surge Stopper
Features
Description
Low Quiescent Current: 8µA Operating, 6µA
Shutdown
n Withstands Surge Voltage Up to the MOSFET Limit
n Wide Operating Voltage Range: 4V to 72V
n Overcurrent Protection
n Selectable Internal 31.5V/50V or Adjustable Gate
Clamp Voltage (Table 1)
n Reverse Input Protection to –60V
n Adjustable Turn-On Threshold
n Adjustable Fault Timer with MOSFET Stress
Acceleration
n Controls N-Channel MOSFET
n Latchoff and Retry Options (Table 1)
n Low Retry Duty Cycle During Faults (Table 1)
n10-Pin DFN (3mm × 3mm) and MSOP Packages
The LTC®4380 low quiescent current surge stopper protects
loads from high voltage transients. Overvoltage protection
is provided by clamping the gate voltage of an external
N-channel MOSFET to limit the output voltage to a safe
value during overvoltage events such as load dump in
automobiles. Fixed gate clamp voltages are selectable for
12V and 24V/28V systems. For systems of any voltage up
to 72V, use the adjustable gate clamp versions. Overcurrent protection is also provided.
n
Applications
n
n
n
n
Automotive/Avionic/Industrial Surge Protection
Hot Swap/ Live Insertion
High Side Switch for Battery Powered Systems
Intrinsic Safety Applications
An internal multiplier generates a TMR pin current proportional to VDS and ID, so that operating time in both
overcurrent and overvoltage conditions is limited in accordance with MOSFET stress.
The GATE pin can drive back-to-back MOSFETs for reverse
input protection, eliminating the voltage drop and dissipation of a Schottky diode solution. A low 8µA operating
current permits use in always-on and battery powered
applications. An accurate ON pin comparator monitors
the input supply for undervoltage (UV) conditions and
also serves as a shutdown input, reducing the quiescent
current to 6µA.
L, LT, LTC, LTM, Linear Technology, the Linear logo and LTspice are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
12V, 1A with 250V Overvoltage Protection
20mΩ
FDB33N25
VIN
12V
(250VPK)
Surge Stopper Limits Output to 27V During Input Surge
22µF
10Ω
10k
249k
33Ω
GATE
VCC
SNS
OUT
LTC4380-2
ON
GND
68V
CMHZ5266B
CTMR = 8.2µF
ILOAD = 1A
100V INPUT SURGE
47nF
DRN
0.1µF
12V/1A
OUTPUT CLAMPED
AT 27V
TMR
FLT
VIN
20V/DIV
12V
VOUT
12V
20V/DIV
SEL
27V ADJUSTABLE CLAMP
8.2µF
4380 TA01a
100ms/DIV
4380 TA01b
4380f
For more information www.linear.com/LTC4380
1
LTC4380
Absolute Maximum Ratings
(Notes 1, 2)
VCC, ON, SEL................................................ –60V to 80V
DRN (Note 3), SNS, OUT
LTC4380-1/LTC4380-2........................... –0.3V to 53V
LTC4380-3/LTC4380-4........................... –0.3V to 80V
SNS to OUT...................................................... –5V to 5V
GATE (Note 4)
LTC4380-1/LTC4380-2........................... –0.3V to 53V
LTC4380-3/LTC4380-4........................... –0.3V to 86V
GATE to OUT, VCC (Note 4).......................... –0.3V to 10V
TMR.............................................................. –0.3V to 5V
FLT.............................................................. –0.3V to 80V
IDRN........................................................................2.5mA
Operating Ambient Temperature Range
LTC4380C................................................. 0°C to 70°C
LTC4380I..............................................–40°C to 85°C
LTC4380H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP................................................................ 300°C
Pin Configuration
TOP VIEW
DRN 1
10 TMR
VCC 2
9 ON
GATE 3
SNS 4
11
GND
TOP VIEW
DRN
VCC
GATE
SNS
OUT
8 GND
7 FLT
6 SEL
OUT 5
10
9
8
7
6
TMR
ON
GND
FLT
SEL
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 160°C/W
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 135°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, PCB CONNECTION OPTIONAL
Order Information
1
2
3
4
5
http://www.linear.com/product/LTC4380#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4380CDD-1#PBF
LTC4380CDD-1#TRPBF
LGHQ
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4380IDD-1#PBF
LTC4380IDD-1#TRPBF
LGHQ
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4380HDD-1#PBF
LTC4380HDD-1#TRPBF
LGHQ
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4380CMS-1#PBF
LTC4380CMS-1#TRPBF
LTGHR
10-Lead Plastic MSOP
0°C to 70°C
LTC4380IMS-1#PBF
LTC4380IMS-1#TRPBF
LTGHR
10-Lead Plastic MSOP
–40°C to 85°C
LTC4380HMS-1#PBF
LTC4380HMS-1#TRPBF
LTGHR
10-Lead Plastic MSOP
–40°C to 125°C
LTC4380CDD-2#PBF
LTC4380CDD-2#TRPBF
LGHS
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4380IDD-2#PBF
LTC4380IDD-2#TRPBF
LGHS
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4380HDD-2#PBF
LTC4380HDD-2#TRPBF
LGHS
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4380CMS-2#PBF
LTC4380CMS-2#TRPBF
LTGHT
10-Lead Plastic MSOP
0°C to 70°C
LTC4380IMS-2#PBF
LTC4380IMS-2#TRPBF
LTGHT
10-Lead Plastic MSOP
–40°C to 85°C
LTC4380HMS-2#PBF
LTC4380HMS-2#TRPBF
LTGHT
10-Lead Plastic MSOP
–40°C to 125°C
LTC4380CDD-3#PBF
LTC4380CDD-3#TRPBF
LGXZ
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4380IDD-3#PBF
LTC4380IDD-3#TRPBF
LGXZ
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4380HDD-3#PBF
LTC4380HDD-3#TRPBF
LGXZ
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4380CMS-3#PBF
LTC4380CMS-3#TRPBF
LTGYD
10-Lead Plastic MSOP
0°C to 70°C
LTC4380IMS-3#PBF
LTC4380IMS-3#TRPBF
LTGYD
10-Lead Plastic MSOP
–40°C to 85°C
2
4380f
For more information www.linear.com/LTC4380
LTC4380
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4380HMS-3#PBF
LTC4380HMS-3#TRPBF
LTGYD
10-Lead Plastic MSOP
–40°C to 125°C
LTC4380CDD-4#PBF
LTC4380CDD-4#TRPBF
LGYC
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4380IDD-4#PBF
LTC4380IDD-4#TRPBF
LGYC
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4380HDD-4#PBF
LTC4380HDD-4#TRPBF
LGYC
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4380CMS-4#PBF
LTC4380CMS-4#TRPBF
LTGYF
10-Lead Plastic MSOP
0°C to 70°C
LTC4380IMS-4#PBF
LTC4380IMS-4#TRPBF
LTGYF
10-Lead Plastic MSOP
–40°C to 85°C
LTC4380HMS-4#PBF
LTC4380HMS-4#TRPBF
LTGYF
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VCC
Operating Voltage Range
LTC4380-1/LTC4380-2
LTC4380-3/LTC4380-4 (Note 6)
VOUT
Operating Voltage Range
IQ
Total Supply Current, ON
(Note 5)
MIN
l
l
TYP
4
4
V
V
72
V
8
11
12
20
µA
µA
µA
22
28
35
µA
µA
6
10
µA
7
9
12
µA
µA
20
25
30
µA
µA
l
l
VCC = OUT = SNS = DRN = 4V
l
ICC
VCC Current, OFF
ON = OUT = SNS = 0V
VCC Current, ON
VCC = OUT = SNS = DRN = 12V
l
l
VCC = OUT = SNS = DRN = 4V
UNITS
80
72
l
VCC = OUT = SNS = DRN = 12V
C-Grade and I-Grade
H-Grade
MAX
l
ISNS
SNS Current, ON
VCC = OUT = SNS = DRN
l
0.5
1.4
µA
IOUT
OUT Current, ON
OUT Current, OFF
SNS = OUT = DRN = 12V
SNS = OUT = DRN = 12V,C-Grade and I-Grade
H-Grade
l
l
l
1.5
5
2
12
80
µA
µA
µA
IR
Reverse Input Current
VCC = –60V, ON Open, SEL = 0
VCC = ON = SEL = –60V
l
l
–0.4
–1.2
–2
–5
mA
mA
∆VGATE
GATE Drive (GATE – OUT)
SEL = SNS = OUT = VCC
8V ≤ VCC ≤ 30V; IGATE = –1µA, 0µA
VCC = 4V; IGATE = –1µA, 0µA
l
l
10
5
11.5
14
8
V
V
∆VCLAMP
GATE Clamp to VCC (GATE – VCC)
SNS = OUT = 20V, IGATE = 0µA
l
12
13.5
14.5
V
VGATE
GATE Clamp to GND
VCC = 30V, SEL = 0V
VCC = 60V, SEL = VCC
l
l
30
47.5
31.5
50
33
52.5
V
V
IGATE(UP)
GATE Pull-Up Current
VCC = GATE = OUT = 12V, SEL = 0V
VCC = GATE = OUT = 24V, SEL = VCC
l
l
–10
–12
–20
–25
–30
–35
µA
µA
IGATE(DN)
GATE Pull-Down Current
Overcurrent
Shutdown
Input UV
Fault Time Out
∆VSNS = 200mV, GATE = 12V, OUT = 0V
ON = 0V, GATE = 20V
VCC = 2V, GATE = 10V
TMR = 2V, GATE = 10V
l
l
l
l
50
0.3
2
1.5
100
5
5
3.5
mA
mA
mA
mA
4380f
For more information www.linear.com/LTC4380
3
LTC4380
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
∆VSNS
Current Limit Sense Voltage (SNS – OUT)
VCC = 12V, 24V, OUT = 6V, 12V
VCC = 12V, 24V, OUT = 0V
l
l
ISEL
SEL Input Current
SEL = 0V to 80V
l
VSEL
SEL Input Threshold
l
MIN
TYP
MAX
44
42
50
62
55
95
mV
mV
±0.1
µA
3
V
0.4
ION
ON Input Current
VON = 1V
l
–1
–2
VON
ON Input Threshold
ON Rising
l
0.99
1.05
VON(HYST)
ON Input Hysteresis
IFLT
FLT Leakage Current
FLT = 80V
l
VFLT(LOW)
FLT Output Low
ISINK = 0.1mA
ISINK = 3mA
l
l
∆VDRN
DRN Voltage (DRN – OUT)
IDRN = 0.1mA, OUT = SNS = 12V
l
VDS(MAX)
Overvoltage VDS Threshold (DRN – OUT)
TMR = 0.8V, IDRN = 2µA
SNS = OUT = 12V
TMR = 0.8V
UNITS
µA
1.1
45
V
mV
2
µA
0.1
1
0.5
4
V
V
0.7
1.5
2.5
V
0.7
l
0.6
0.3
0.8
1.0
V
V
l
1.25
2
2.75
µA
l
TMR = 2V
TMR = 0.8V, OUT = 11V, VDS = 1.1V, ∆VSNS = 0mV l
–1
–2
–3
µA
TMR Pull-Up Current, Overvoltage
–0.8
–1.6
–2.4
µA
Small OV, Light Load
High OV, Light Load
OUT = 28V, TMR = 0.8V
IDRN = 0.1mA, ∆VSNS = 10mV
IDRN = 1mA, ∆VSNS = 10mV
l
l
–3.5
–13
–6.7
–30
–11.6
–61
µA
µA
Small OV, Heavy Load
High OV, Heavy Load
IDRN = 0.1mA, ∆VSNS = 40mV
IDRN = 1mA, ∆VSNS = 40mV
l
l
–10
–60
–20
–120
–30
–180
µA
µA
TMR Pull-Up Current, Overcurrent
TMR = 0.8V
IDRN = 0mA, OUT = 11V
IDRN = 0mA, OUT = 0V
l
l
–4
–17
–6
–27
–9
–34
µA
µA
Small OV, Light Load
High OV, Light Load
IDRN = 0.1mA, OUT = 11V
IDRN = 1mA, OUT = 11V
l
l
–16
–80
–27
–142
–38
–200
µA
µA
Small OV, Heavy Load
High OV, Heavy Load
IDRN = 0.1mA, OUT = 0V
IDRN = 1mA, OUT = 0V
l
l
–35
–130
–50
–170
–60
–220
µA
µA
VTMR(F)
TMR Gate Off Threshold
TMR Rising
l
1.178
1.215
1.251
V
D
Retry Duty Cycle; Overvoltage,
LTC4380-2/LTC4380-4
∆VSNS = 40mV, IDRN = 5µA, OUT = 28V, VCC = 29V l
2.8
3.5
%
∆VSNS = 40mV, IDRN = 500µA, OUT = 28V, VCC =
80V
l
0.1
0.2
%
Retry Duty Cycle; Overcurrent,
LTC4380-2/LTC4380-4
IDRN = 500µA
OUT = 0V
OUT = 6V
l
l
0.1
0.35
0.2
0.7
%
%
tON(ON)
Turn-On Propagation Delay
ON Steps from 0V to 1.5V, OUT = SNS = 0V
l
5
25
ms
tOFF(ON)
Turn-Off Propagation Delay
ON Steps from 1.5V to 0V, OUT = SNS = VCC
l
1
5
µs
tOFF(OC)
Overcurrent Turn-Off Propagation Delay
∆VSNS Steps from 0V to 200mV, OUT = 6V
l
2
4
µs
∆VSNS Steps from 0V to 200mV, OUT = 0V
l
2
4
µs
ITMR(DN)
TMR Pull-Down Current
ITMR(UP,COOL) TMR Pull-Up Current, Cool Down
ITMR(UP)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: Internal clamps limit the DRN pin to a minimum of 10V above the
OUT and SNS pins.
4
Note 4: Internal clamps limit the GATE pin to a minimum of 10V above the
OUT pin or VCC pin, or 50V (SEL = VCC) or 31.5V (SEL = GND) above the
GND pin (LTC4380-1/LTC4380-2). Driving this pin to voltages beyond the
clamp may damage the device.
Note 5: Total supply current is the sum of the current into the VCC, OUT,
SNS and DRN pins.
Note 6: Operating voltage is limited by the maximum GATE voltage of 86V.
4380f
For more information www.linear.com/LTC4380
LTC4380
Typical Performance Characteristics
Total Supply Current (IQ) vs Input
Voltage
30
VCC = 12V, unless otherwise noted.
Total Supply Current (IQ) vs Gate
Leakage
Total Supply Current (IQ) vs
Temperature
100
SEL = VCC
100
IQ (µA)
IQ (µA)
IQ (µA)
20
10
10
10
0
IGATE = 0
OFF
0
10
20
VIN (V)
1
–0.001
30
–0.01
4380 G01
Supply Current (ICC) vs Supply
Voltage
–0.1
IGATE (µA)
–1
1
–50 –25
–10
100
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G03
10
SNS = OUT = VCC
SNS = OUT= SEL = VCC
0
4380 G02
Supply Current (ICC) vs
Temperature
30
IGATE = 0
IGATE = –1µA
OFF
ISNS vs Temperature
SNS = OUT = VCC
ISNS (µA)
ICC (µA)
ICC (µA)
20
10
1
10
0
0
10
20
VCC (V)
1
–50 –25
30
VCC = 4V
VCC = 12V
0
0.1
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G04
4380 G06
Reverse Current vs Reverse
Voltage
10
1k
Gate Drive vs Gate Current
14
SEL = ON = VCC
SNS = OUT = VCC
12
10
ON
OFF
∆VGATE (V)
IGND (mA)
IOUT (µA)
100
1
8
6
4
2
1
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G05
Output Pin Current vs
Temperature
10
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G07
0.1
–10
–20
–30
–40 –50
VCC (V)
–60
–70
–80
4380 G08
0
VCC = 12V
VCC = 4V
0
–5
–10
–15
IGATE (µA)
–20
–25
4380 G09
4380f
For more information www.linear.com/LTC4380
5
LTC4380
Typical Performance Characteristics
Gate Pull Up Current vs
Temperature
VCC = 12V, unless otherwise noted.
Gate Drive vs Temperature
–35
15
Gate Drive vs Supply Voltage
15
IGATE = –1µA
IGATE = –1µA
SEL = VCC
10
–25
∆VGATE (V)
10
∆VGATE (V)
IGATE(UP) (µA)
–30
5
5
–20
–15
–50 –25
GATE = 0V
GATE = 12V
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
VCC = 4V
VCC = 12V
0
4380 G10
–4.0
–60
OUT = 20V
–3.5
14
∆VCLAMP (V)
–1.5
–1.0
13
12
1
2
3
VON (V)
4
5
0
–40
–35
–20
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G13
Current Limit vs Output Voltage
–140
60
3.5
–120
50
30
20
–40
10
0
25 50 75 100 125 150
TEMPERATURE (°C)
4380 G16
3.0
40
–60
–20
–50 –25
∆VDRN = VDRN – VOUT
∆VDRN (V)
IDRN = 1mA
∆VSNS = 40mV
∆VSNS = 10mV
25 50 75 100 125 150
TEMPERATURE (°C)
DRN Voltage vs Current
4.0
–80
0
4380 G15
70
–100
OUT = 0V
OUT = 6V
4380 G14
∆VSNS (mV)
ITMR(OV) (µA)
–45
–30
11
–50 –25
TMR Pin Current vs Temperature
–160
6
IDRN = 0.1mA
–25
0
4380 G12
–50
–0.5
0
0
30
–55
ITMR(OC) (µA)
–3.0
20
TMR Pin Current vs Temperature
15
–2.0
10
VCC (V)
Gate Clamp to VCC vs
Temperature
–2.5
0
4380 G11
ON Pin Current vs Voltage
ION (µA)
0
25 50 75 100 125 150
TEMPERATURE (°C)
2.5
2.0
1.5
0
1
2
3
4
VOUT (V)
5
6
7
8
4380 G17
1.0
1
10
100
IDRN (µA)
1k
4380 G18
4380f
For more information www.linear.com/LTC4380
LTC4380
Pin Functions
DRN: External MOSFET Drain-Source Sense. The DRN
pin voltage tracks the OUT pin. The resulting DRN pin
current through external resistor RDRN is proportional to
the external MOSFET VDS. The DRN pin current and ΔVSNS
(SNS – OUT) are multiplied internally to produce a TMR
pin current approximately proportional to the MOSFET's
power dissipation. This reduces the SOA requirement of
the MOSFET by timing out faster during more severe faults.
Choose RDRN to limit the current to 1mA at the peak input
voltage. Connect to OUT if unused.
Exposed Pad: Exposed Pad. May be left open or connected
to device ground (GND).
FLT: Fault Output. This open drain logic output pin pulls
low after the voltage at the TMR pin has reached the fault
threshold of 1.215V. It indicates that the MOSFET is off
because either the supply voltage has stayed at an elevated
level for an extended period of time (voltage fault) or the
device is in an overcurrent condition (current fault). The
fault output is capable of sinking up to 3mA. Leave open
if unused.
GATE: Gate Drive for N-Channel MOSFET. The GATE pin is
pulled up by an internal 20µA charge pump that is regulated
to 11.5V above the OUT pin. An amplifier controls the GATE
pin to limit the current through the MOSFET. The GATE
pin is clamped during an overvoltage event, thus indirectly
limiting the output voltage. The clamp voltage is set to
31.5V with SEL = 0V or 50V when SEL = VCC for the fixed
voltage versions, LTC4380-1/LTC4380-2. The LTC4380-3
and LTC4380-4 are adjustable versions without the internal
gate clamp. The voltage at the GATE pin is limited to 13.5V
above VCC when not in regulation mode. A minimum of
47nF of capacitance and 33Ω series resistor at the pin is
necessary to compensate the current limit amplifier. To
avoid damaging the external MOSFET during an output
short, GATE is also clamped internally to 17V above OUT.
at the pin to no more than 1µA if no external pull-up is
used. The ON pin can be pulled up to 80V or below GND
by 60V without damage.
OUT: Output Voltage Sense. This pin senses the output
voltage at the output terminal of the current sense resistor.
An internal clamp limits the voltage in between the GATE
and OUT pins to 17V. Bypass the OUT pin with a minimum
of 22µF as close to the pin as possible.
SEL: Gate Clamp Voltage Select for LTC4380-1 and
LTC4380-2. Connect the SEL pin to GND to set the internal
gate clamp voltage to 31.5V. Connect it to VCC or OUT for
a 50V gate clamp voltage. The SEL pin can be pulled up
to 80V or below GND by 60V without damage. Connect
SEL to GND for LTC4380-3 and LTC4380-4.
SNS: Current Sense Input. Connect to the input terminal
of the current sense resistor. The current limit amplifier
controls the GATE pin to limit the current sense voltage
to 50mV. This voltage increases to 62mV in a severe fault
when OUT is below 1.5V. A fixed 7µA is added to the TMR
pin current during an overcurrent condition to shorten the
timer. In a severe short condition when output voltage is
below 1.5V, the extra current increases to 27µA to reduce
the power dissipation in the MOSFET. ∆VSNS (SNS – OUT)
must be limited to less than 5V. Connect to OUT if unused.
GND: Device Ground.
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the fault turn-off time and cool down
period. The charging current during fault conditions varies depending on the power dissipation of the MOSFET.
When TMR reaches 1.215V, the MOSFET turns off and
FLT pulls low. Upon gate off, the part immediately enters
a cool down period with a 2µA current pull up and pull
down on the TMR pin. After the cool down period has
concluded the LTC4380-2 and LTC4380-4 immediately
restart, while the LTC4380-1and LTC4380-3 remain off
until the ON pin is pulled low momentarily for more than
100µs or power is cycled.
ON: Turn-On Control Input. The LTC4380 can be turned
on by pulling this pin above 1.05V or by leaving it open to
allow an internal 1M resistor to turn the part on. Pulling the
pin below the threshold turns off the part and reduces the
supply current to 6µA. Limit the leakage current to ground
VCC: Positive Supply Voltage Input. The positive supply
input ranges from 4V to 80V for normal operation. It can
go below ground by up to 60V during a reverse battery
condition, without damaging the part. For applications
where the input voltage is expected to exceed 80V, the
4380f
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7
LTC4380
Pin Functions
VCC pin may be protected by a Zener diode clamp or, in
the case of short duration spikes, by a simple RC filter.
Clamping the VCC pin with a Zener diode can also be used
as a means of adjusting the GATE pin clamp voltage to
a value less than the internal 31.5V or 50V clamps for
the LTC4380-1/LTC4380-2. For the adjustable versions,
LTC4380-3/LTC4380-4, which have no internal gate clamp,
a Zener diode at the VCC pin is the only way to limit the
voltage at the GATE pin.
Block Diagram
VCC
GATE
OUTPUT
SNS
17V
OUT
13.5V
31.5V*
+
SEL
+
–
CHARGE PUMP
REGULATED TO
VOUT + 11.5V
20µA
(250kHz)
RDRN
RSNS
Q1
INPUT
IA
18.5V*
50mV/68mV
3.5V
–
1M
+
SNS
ON
VCC
+
IMULT
2.2V
UV
OUT
VCC
3.4V
7µA, 27µA
–
VMAX RST GOFF
+
OVERCURRENT
4µA
3.5µA
VCC
0.1V
+
FLT
–
OVERVOLTAGE
+
2µA
1.215V
–
TMR
GND
4380 BD
*ONLY IN LTC4380-1/LTC4380-2
8
1V
CONTROL
LOGIC
MULTIPLIER
COOL
DOWN
–
–
DRN
VCC
ON
4380f
For more information www.linear.com/LTC4380
LTC4380
Operation
The LTC4380 is a low quiescent current surge stopper
that drives an external N-channel MOSFET as the pass
device. In normal operation, a 20µA charge pump (see
Block Diagram) drives the MOSFET (Q1) high, turning it
fully on and providing a low impedance path from input
to the load. The MOSFET gate is clamped to ground by a
Zener stack. If the input voltage rises to the point where the
output approaches the gate clamp, the output is effectively
limited to one threshold voltage below the gate clamp and
the input surge is blocked from reaching the load.
For the LTC4380-1 and LTC4380-2 versions, two internal
gate clamping voltages to ground are available: 31.5V,
which limits the output to about 27V for use in 12V
systems, and 50V, which limits the output to about 45V
for use in 24V and 28V systems. The clamping voltage is
selectable using the SEL pin. Besides the gate to ground
clamp, the GATE pin is also limited to 13.5V above the
VCC pin voltage.
There is no internal gate clamp to ground for the LTC4380-3
and LTC4380-4 versions and the gate pin is only limited
to 13.5V above the voltage at the VCC pin. A Zener diode
clamp connected from the VCC pin to ground thus clamps
the voltages at both the VCC and GATE pins during overvoltage events.
Load current is limited by a current limit amplifier (IA),
using a sense resistor in series with the MOSFET source
to monitor the current. The current limit threshold is 50mV
rising to 62mV when the output is less than 3V.
MOSFET stress is monitored by a timer, whose current
is a function of Q1’s VDS as well as ID. VDS is monitored
by RDRN at the DRN pin, while ID is monitored by sensing the voltage drop across RSNS. The timer allows the
load to continue functioning during short transient events
while protecting the MOSFET from being damaged by a
sustained overvoltage, such as load dump in vehicles, or
an output overload or short circuit.
A multiplier sets the timer period depending on the power
dissipation in the MOSFET. Higher power dissipation corresponds to a shorter timer period, helping to keep the
MOSFET within its safe operating area (SOA).
The timer responds to stresses at start-up, during voltage
limiting, and during current limiting. TMR pin current is
integrated on timing capacitor CTMR and if TMR charges
to 1.215V, the MOSFET is turned off. At this point the
LTC4380-1 and LTC4380-3 latch off, and can be reset
by cycling power or by pulling the ON pin low for at least
100µs. For the LTC4380-2 and LTC4380-4, the TMR pin
enters a cool down phase, allowing time for the MOSFET
temperature to equalize with its surroundings before
automatically restarting. The TMR pin slowly charges up
and down in between 3.4V and 1.215V for 15 times and
discharges to ground at the last cycle. When the TMR pin
has reached the 100mV threshold, the MOSFET is turned
back on. The cool down interval can be curtailed by pulling
the ON pin low for at least 10ms/µF of CTMR.
In addition to resetting the timer, the ON pin is used for
on/off control and for undervoltage detection. The ON pin
threshold is 1.05V.
The open drain FLT pin pulls low whenever the timer is
faulted off, and goes high again when reset by a power
cycle, by pulling the ON pin low for at least 100µs or in
the case of the LTC4380-2 and LTC4380-4, when the TMR
pin discharges to 100mV.
Table 1. LTC4380 Options
LTC4380
GATE CLAMP
FAULT BEHAVIOR
-1
Internal 31.5V/50V to GND
Latchoff
-2
Internal 31.5V/50V to GND
Auto Retry
-3
Externally Adjustable
Latchoff
-4
Externally Adjustable
Auto Retry
4380f
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9
LTC4380
Applications Information
The LTC4380 limits the voltage and current delivered to
the load during supply transient or output overload events.
The N-channel MOSFET provides a low resistance path
from the input to the load during normal operation, while
in overvoltage conditions it limits the output to a threshold
voltage below the clamped gate voltage. The total fault timer
period is set to ride through short-duration faults, while
longer events cause the output to shut off and protect the
MOSFET from damage.
Startup
Figure 1 shows a 12V, 1A application which limits the
output to approximately 27V. When power is first applied with VCC ≥ 4V and ON ≥ 1.05V, there is a delay of
about 10ms before the GATE pin begins charging C2 and
Q1’s gate terminal with a fixed, 20µA current source. Q1,
operating as a source follower, ramps the output up at a
rate of IGATE(UP)/C2. Inrush current in the load capacitance
CL is given by
IINRUSH = IGATE(UP) •
CL
C2
where IGATE(UP) is typically 20µA.
Eventually the GATE pin charges to the point where VIN ≈
VOUT and stops only when ΔVGATE (VGATE – VOUT) reaches
its regulation point of 11.5V, fully enhancing Q1.
Overcurrent Fault Protection
The LTC4380 features an adjustable current limit that
protects against short circuits and excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the SNS and OUT
pins (ΔVSNS) to 50mV when out is above 3V. In the case
of a severe short at the output, where OUT is less than
1.5V, the current sense voltage is 62mV. Output current is
thereby limited to ΔVSNS/RSNS. Current limit may control
the startup ramp rate in extreme cases, such as if CL is
unusually large or if current limit is set to an unusually low
value, and artificially reduces CL’s inrush current below
the value previously calculated.
Overvoltage Fault Protection
The LTC4380 limits the voltage at the output during an
overvoltage at the input. For the LTC4380-1/LTC4380-2
illustrated in Figure 1, an internal clamp limits the GATE
pin to either 31.5V or 50V, depending on the state of the
SEL pin. With the SEL pin grounded as shown, the GATE
pin is clamped at 31.5V. Assuming a threshold voltage of
5V for Q1, this limits the output to approximately 26.5V.
Tying the SEL pin high causes the GATE pin to clamp at
50V, and limits the output to approximately 45V.
The GATE pin may also be limited by the compliance of
the internal 20µA current source, to VCC + 13.5V. In the
LTC4380-3/LTC4380-4 the GATE pin clamp is entirely
disconnected, leaving only the VCC + 13.5V compliance
limit. This arrangement allows the GATE pin to be effectively
clamped at any voltage from 18V to 86V, by clamping VCC
to between 4V and 72V.
VCC Pin
The VCC pin operating range extends from 4V to 80V. In the
presence of an input overvoltage exceeding 80V, the VCC
pin must be protected by filtering or clamping. For short
duration spikes and transients exceeding 80V, filtering is
the most sensible means of protecting the VCC pin. R1 and
C1 provide filtering in Figure 1. Owing to the LTC4380’s low
ICC, values up to 20k may be used for R1 without seriously
impairing the lower end of the operating voltage range.
For long duration surges such as automotive load dump,
C1 becomes prohibitively large and Zener D1 is the most
RSNS
20mΩ
Q1
FDB33N25
VIN = 12V
R1
10k
RDRN
249k
DRN
R3
10Ω
GATE
SNS
OUT
LTC4380-2
ON
D1
68V
CMHZ5266B
R2
33Ω
C2
47nF
VCC
C1
4.7µF
OUT
CL
22µF
GND
TMR
SEL
CTMR
8.2µF
4380 F01
Figure 1. 12V/1A, Output Limited to 27V
10
4380f
For more information www.linear.com/LTC4380
LTC4380
Applications Information
effective means of limiting the VCC voltage. Using a 68V
Zener assures that D1 will not override the internal GATE
pin clamp in the LTC4380-1 and LTC4380-2 devices. For
the LTC4380-3 and LTC4380-4, the VCC operating range
extends from 4V to 72V. Since the GATE pin is regulated to
VOUT + 11.5V, D1 is chosen to achieve the desired output
clamping effect while at the same time keeping the VCC
pin within its 4V to 72V range.
Fault Timer Overview
Overvoltage and overcurrent conditions, and high VDS conditions in Q1 are limited in duration by an adjustable fault
timer. A capacitor at the TMR pin CTMR sets the delay time
before a fault condition is reported at the FLT pin and Q1 is
turned off. CTMR also sets the cool down time before Q1 is
permitted to turn back on for the LTC4380-2 and LTC4380-4
auto retry versions. The LTC4380-1 and LTC4380-3 versions
simply latch off at the end of the timer delay.
Fault timing starts as soon as the input power is applied
with the part in the on condition, or when the part is turn
on after application of power. A 1.5µA current is generated to pull up the TMR pin when the voltage across the
MOSFET is higher than 0.7V. The timer speeds up with
an additional current that varies with the power dissipated
in the MOSFET, Q1. The power dissipation is the product
of the voltage across the MOSFET (VDS) and the current
flowing through it (ID). VDS is inferred from the voltage
drop across the drain pin resistor, RDRN, while ΔVSNS
represents ID.
At initial power-up, the 1.5µA pilot current charges the
TMR pin capacitor because the input supply is, at least
for a short time, more than 0.7V above the output voltage.
When the output rises to within 0.7V of the input supply
voltage, the pull-up current disappears and an internal
2µA current source discharges the TMR pin capacitor. The
capacitor must be sized to ride through the initial start-up
interval for successful power-up.
In the presence of a sustained fault, the timer current charges
the TMR pin to 1.215V. At this point the FLT pin pulls low
to indicate a fault condition and the GATE pin pulls low,
shutting off the MOSFET. After faulting off, the timer enters
the cool down phase. At the end of the cool down period
the LTC4380-1/LTC4380-3 remain off until manually reset,
while the LTC4380-2/LTC4380-4 automatically restart.
Fault Timer Operation in Overvoltage
During an overvoltage condition, where the MOSFET’s VDS
exceeds 0.7V, the TMR pin charges from 0V to 1.215V
with a current that varies principally as a function of VDS
and ID. VDS is inferred from the current flowing in the DRN
pin resistor, RDRN, while the voltage difference between
the SNS and OUT pins (∆VSNS) represents the MOSFET
current, ID.
The TMR pin current is given by
⎡ A⎤
ITMR = 1.5 • 10 –6A + 0.0917 ⎢
⎥ • ΔVSNS • IDRN
V ⎦
⎣
Where 1.5 • 10–6A is the minimum TMR current and
0.0917√A/V is the gain term of the multiplier.
Substituting for ∆VSNS and IDRN
⎡ A⎤
R
ITMR = 1.5 • 10 –6A + 0.0917 ⎢
⎥ •ID • VDS SNS
RDRN
⎣ V ⎦
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by:
t TMR = VTMR(F) •
CTMR
ITMR
Because ITMR is a function of VDS and ID, the exact time
spent in overvoltage before turning off depends upon the
input waveform and the load current.
Fault Timer Operation in Overcurrent
TMR pin behavior in overcurrent is substantially the same as
in overvoltage. In the presence of an overcurrent condition
when the LTC4380 regulates the output current, the TMR
pin charges from 0V to 1.215V with a current that varies
principally as a function of the power dissipated on the
MOSFET. In addition to the variable current, an additional
27µA hastens timeout in a low impedance short where the
output is less than 1.5V. This additional current is reduced
to 7µA when VOUT is above 3V.
4380f
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11
LTC4380
Applications Information
The TMR pin current with VOUT less than 1.5V is given by
⎡ A⎤
ITMR = (27 + 1.5) • 10 –6A + 0.0917 ⎢
⎥•
⎣ V ⎦
ID • VDS
RSNS
RDRN
Where 27 • 10–6A is the extra TMR current during overcurrent condition.
And with VOUT above 3V
⎡ A⎤
ITMR = (7 + 1.5) • 10 –6A + 0.0917 ⎢
⎥•
⎣ V ⎦
ID • VDS
RSNS
RDRN
Where 7 • 10–6A is the extra TMR current during overcurrent condition.
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by
t TMR = VTMR(F) •
CTMR
ITMR
Because ITMR is a function of VDS and ID, the exact time
spent in overcurrent before turning off depends upon the
input waveform, the output voltage and the time required
for the output current to come into regulation.
Cool Down Phase
Cool down behavior is the same whether initiated by
overvoltage or overcurrent. During the cool down phase,
the timer continues to charge from 1.215V to 3.4V with
2µA, and then discharge back down to 1.215V with 2µA.
This cycle repeats 14 times and at the 15th cycle the TMR
pin is pulled all the way to ground. The total cool down
time is given by:
tCOOL = CTMR
12
15 • 4.37V +(1.215V – 0.1V)
2µA
Up to this point the operation of the LTC4380-1/LTC4380-3
and LTC4380-2/LTC4380-4 is the same. Behavior at the
end of the cool down phase is entirely different.
At the end of the cool down phase, when TMR crosses the
100mV reset threshold, the LTC4380-1/LTC4380-3 remain
latched off and FLT remains low. They may be restarted by
pulling the ON pin low for at least 100µs or by cycling the
power supply. The cool down phase may be interrupted
at anytime by pulling the ON pin low for at least 10ms/µF
of CTMR; the LTC4380-1/LTC4380-3 will restart when ON
goes high. The LTC4380-2/LTC4380-4 will automatically
retry at the end of the cool down phase without cycling
the ON pin and the cool down phase may be interrupted
by pulling the ON pin low for at least 10ms/µF of CTMR.
For both versions, the FLT pin goes high in shutdown and
is cleared high when power is first applied to VCC. If FLT
is set low, it can be reset during the cool down phase by
pulling the ON pin low for at least 10ms/µF of CTMR.
Supply Transient Protection
The LTC4380 is tested to operate to 72V and guaranteed
to be safe from damage up to 80V. Nevertheless, voltage
transients above 80V may cause permanent damage.
During a short-circuit condition, the large change in current flowing through power supply traces and associated
wiring can cause inductive voltage transients which can
exceed 80V. To minimize the voltage transients, minimize
the power trace parasitic inductance by using short, wide
traces. An RC filter at the VCC pin is an effective measure
against voltage spikes.
Another way to limit transients to less than 80V at the VCC
pin is to use a small Zener diode and a resistor, D1 and R1
in Figure 1. The Zener diode limits the voltage at the pin
while the resistor limits the current through the diode to a
safe level during the surge. However, D1 can be omitted if
the filtered voltage at the VCC pin, due to R1 and C1, stays
below 80V. The inclusion of R1 in series with the VCC pin
modestly increases the minimum required voltage at VIN
due to the extra voltage drop across it from the small VCC
current of the LTC4380 and the leakage current of D1.
A total bulk capacitance of at least 22µF low ESR electrolytic or ceramic is required close to the source pin of
MOSFET Q1.
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LTC4380
Applications Information
MOSFET Selection
The LTC4380 drives an N-channel MOSFET to carry the
load current. The important features of the MOSFET are
on-resistance RDS(ON), the maximum drain-source voltage
V(BR)DSS, the threshold voltage, and the safe operating
area (SOA).
The maximum allowable drain-source voltage must be
higher than the peak supply voltage. If the output is off
or shorted to ground during an overvoltage event, the full
supply voltage will appear across the MOSFET.
The gate drive for the MOSFET is guaranteed to be more
than 10V and less than 14V above the OUT pin for those
applications with VCC higher than 8V. This allows the use
of a standard threshold voltage N-channel MOSFET. For
systems with steady state VCC less than 8V, a logic level
MOSFET is required since the gate drive can be as low as 5V.
The SOA of the MOSFET must encompass all fault conditions. In normal operation the MOSFET is fully on, dissipating very little power. But during overvoltage or overcurrent
faults, the GATE pin is either clamped to limit the output
voltage or controlled to regulate the current through the
MOSFET. Large current and high voltage drop across
the MOSFET can coexist and dissipate significant power
in these cases. The SOA curves of the MOSFET must be
considered carefully in conjunction with the selection of
the fault timer capacitor.
Transient Stress in the MOSFET
During an overvoltage event, the LTC4380 clamps the
gate of the pass MOSFET to limit the output voltage at an
acceptable level. The load circuitry may continue operating
throughout this interval, but only at the expense of dissipation in the MOSFET pass device. MOSFET dissipation or
stress is a function of the input voltage waveform, output
voltage and load current. The MOSFET must be sized to
survive this stress.
Most transient event specifications use the prototypical waveshape shown in Figure 2, comprising a linear
ramp of rise time tr, reaching a peak voltage of VPK and
exponentially decaying back to VIN with a time constant
of τ. A common automotive transient specification has
constants of tr = 10µs, VPK = 80V and τ = 1ms. A surge
VPK
τ
VIN
tr
4380 F02
Figure 2. Prototypical Transient Waveform
condition known as load dump commonly has constants
of tr = 5ms, VPK = 60V and τ = 200ms.
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer out of the
package; this is a matter of device packaging and mounting, and heat sink thermal mass. This is best analyzed by
simulation, using the MOSFET thermal model.
For short duration transients of less than 100ms, MOSFET
survival is a matter of safe operating area (SOA), an intrinsic
property of the MOSFET. SOA quantifies the time required
at any given condition of VDS and ID to raise the junction
temperature of the MOSFET to its rated maximum. MOSFET
SOA can be expressed in units of watt-squared-seconds
(P2t). This figure is essentially constant for intervals of
less than 100ms for any given device type, and rises
to infinity under DC operating conditions. Destruction
mechanisms other than bulk die temperature distort the
lines of an accurately drawn SOA graph so that P2t is not
the same for all combinations of ID and VDS. In particular
P2t tends to degrade as VDS approaches the maximum
rating, rendering some devices useless for absorbing
energy above a certain voltage.
Calculating Transient Stress
To select a MOSFET suitable for any given application, the
SOA stress must be calculated or simulated for each input
transient which shall not interrupt operation. It is then a
simple matter to choose a device which has adequate
SOA to survive the maximum calculated stress. P2t for a
prototypical transient waveform is calculated as follows
(Figure 3):
4380f
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13
LTC4380
Applications Information
For VIN = 15V, ∆VDS = 12V (VOUT = 3V), ∆VSNS = 50mV,
RSNS = 12mΩ, RDRN = 100kΩ and CTMR = 68nF, P2t is
24.5W2s – somewhat higher than the transient SOA calculated in the previous example.
VPK
τ
VREG
VIN
Limiting Inrush Current and GATE Pin Compensation
tr
4380 F03
Figure 3. Safe Operating Area Required to Survive Prototypical
Transient Waveform
Let
The LTC4380 limits the inrush current to any load capacitance by controlling the GATE pin voltage slew rate.
An external capacitor, C2, can be connected from GATE
to ground to reduce the inrush current at the expense of
slower turn-off time. The gate capacitor is set at:
a = VREG – VIN
C2 = IGATE(UP) •
CL
IINRUSH
b = VPK – VIN
(VIN = Nominal Input Voltage)
The LTC4380 needs a minimum of 47nF capacitance
(C2) and a 33Ω (R2) resistor in series at the GATE pin to
stabilize the current limit amplifier during an overcurrent
event. C2 also limits self enhancement of the MOSFET. A
10Ω resistor, R3, is connected to the gate of the MOSFET
to supress parasitic oscillations.
Then
P2 t = ILOAD 2 •
3
⎡
⎞⎤
b – a) 1 ⎛ 2 b
⎢ 1 tr (
+ τ ⎜2a ln + 3a2 + b2 – 4ab⎟⎥
⎠⎥⎦
2 ⎝
a
b
⎢3
⎣
For the transient conditions of VPK = 100V, VIN = 12V,
VREG = 27V, tr = 10µs, τ = 1ms, and a load current of 3A,
P2t is 18W2s which can be handled by a MOSFET in a
DPAK package. The P2t of other transient waveshapes is
evaluated by integrating the square of MOSFET power over
time. LTspice® can be used to simulate timer behavior for
more complex transients and cases where overvoltage and
overcurrent faults coexist, as well as the peak temperature
rise of the MOSFET.
Automobile Cold Crank Ride Through
During cold crank the battery potential drops from the 12V
nominal to as low as 3V for up to 40ms. The LTC4380
needs at least 4V at the VCC pin to function correctly. The
low quiescent current requirement of the part allows an
RC filter with reasonable values to be placed at the VCC pin
to ride through cold crank, as shown in Figure 4.
Calculating Short-Circuit Stress
RDRN
R1 249k
10k
SOA stress must also be calculated for a short-circuit
condition. Short-circuit P2t is given by:
2
⎛
ΔV ⎞
P2 t = ⎜ ΔVDS • SNS ⎟ • t TMR
RSNS ⎠
⎝
⎡W2s⎤
⎣
⎦
Where ∆VDS is the voltage across the MOSFET, ∆VSNS
is the current limit threshold and tTMR is the overcurrent
timer interval.
14
R3
10Ω
OUTPUT
R2
33Ω
C2
47nF
DRN
C1
4.7µF
RSNS
10mΩ
Q1
VIN = 12V, NOMINAL
3V AT COLD CRANK
GATE
VCC
SNS
OUT
LTC4380
ON
GND
TMR
FLT
SEL
CTMR
220nF
4380 F04
Figure 4. Automotive Cold Crank Ride Through
4380f
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LTC4380
Applications Information
Ignoring the supply current (ICC), the VCC potential at the
end of cold crank is given by:
VCC = (VIN(NOM) – VIN(LOW) ) • e
–t
R1•C1 + V
IN(LOW)
Where VIN(NOM) is the input voltage before the cold crank
starts, VIN(LOW) is the lowest input voltage during cold
crank, and t is the duration of the cold crank.
With the combination of R1 (10kΩ) and C1 (4.7µF), VCC
drops to 6.8V after the input voltage drops from 12V to 3V
for 40ms. During this time GATE stays high, keeping the
MOSFET on to continue providing current to the output.
Reverse Input Protection
A blocking diode is commonly employed to protect the
load where reverse input is possible, such as in automotive applications. This diode causes extra power loss,
generates heat, and reduces the available supply voltage
range. During cold crank, the extra voltage drop across
the diode is particularly undesirable.
The LTC4380 is designed to withstand reverse voltage
without damage to itself. The VCC, ON, and SEL pins can
withstand up to 60V of DC voltage below GND. Back-to-back
MOSFETs can be used to block the reverse current path
through Q1’s body diode to protect the load. See Figure 5.
Q2
VIN
12V
Q3
2N3904
R1
10k
D1
68V
CMHZ5266B
D4
1N4148
R5
10k
C1
100nF
GATE
VCC
SNS
OUT
LTC4380
ON
GND
TMR
The LTC4380 can be shut down to a lower current mode by
pulling the ON pin below the shutdown threshold of 1.05V.
The quiescent current drops down to 6µA. An external
Zener diode from the input supply to the ON pin can be
used to implement undervoltage lockout, as illustrated in
Figure 8. The UV threshold is the Zener voltage plus the
shutdown threshold voltage.
The ON pin can be pulled up to 80V or below GND by up
to 60V without damage. Leaving the pin open allows an
internal resistor to pull it up and turn on the part. The leakage current at the pin should be limited to no more than
1µA, if no pull up device is used to help turn on the part.
Layout Considerations
To achieve accurate current sensing, use Kelvin connections
to the current sense resistor (RSNS in Figure 5). The minimum
trace width for 1 oz copper foil is 0.02" per amp to ensure
the trace stays at a reasonable temperature. 0.03" per amp
or wider is recommended. Note that 1 oz copper exhibits a
sheet resistance of about 530µΩ/square. Small resistances
can cause large errors in high current applications.
Design Example
As a design example, take an application with the following specifications: VIN = 5V to 14VDC with a transient of
150V and decay time constant (τ) of 400ms, VOUT ≤ 27V,
current limit (ILIM) at 5A, and cold crank to 3V for 40ms.
The SEL pin is grounded for 27V output clamping in Figure
6. The selection of a 68V Zener diode for D1 limits the voltage at the VCC pin to less than 80V during a 150V surge.
The minimum required voltage at the VCC pin is 4V when
VIN is at 5V; the VCC pin input current is less than 40µA.
The maximum value for R1 to ensure proper operation is:
R2
33Ω
C2
47nF
RDRN
150k
DRN
OUT
R3
10Ω
R4
1M
R6
240k
D3
1N4148
RSNS
10mΩ
Q1
Shutdown
R1=
FLT
Minimum VIN – Minimum VCC 5V – 4V
=
= 25kΩ
Supply Current
40µA
Select 10kΩ for R1 to accommodate all conditions.
SEL
CTMR
220nF
4380 F05
Figure 5. Overvoltage Protector with N-Channel MOSFET
Reverse Input Protection
The maximum current through R1 into D1 during transients
is then calculated as:
I D1=
150V – 68V
= 8.2mA
10kΩ
For more information www.linear.com/LTC4380
4380f
15
LTC4380
Applications Information
RSNS
10mΩ
Q1
FDB33N25
VIN
OUT
22µF
R1
10k
RDRN
150k
DRN
R3
10Ω
R2
33Ω
GATE
SNS
GND
TMR
D1
CMHZ5266B
68V
OUT
4380 F06
CMHZ5266B can handle 500mW indefinitely and 1W for
1 second.
The VCC pin needs at least 4V to operate through cold
crank from 12V down to 3V for 40ms. The value of C1
can be calculated as:
–40ms
= 1.82µF
⎛ 1⎞
10kΩ • ln ⎜ ⎟
⎝9⎠
Next calculate the sense resistor (RSNS) value where the
current limit threshold is 50mV:
50mV 50mV
RSNS =
=
= 10mΩ
ILIM
5A
14V • 47nF
= 32.9ms
20µA
CTMR =
1.5µA • 32.9ms
≈ 123nF
0.4V
220nF is chosen to accommodate all conditions.
The pass transistor, Q1, should be chosen to withstand an
output short with VCC = 14V. In the case of a severe output
short where VOUT = 0V, the total overcurrent fault time is:
tOC =
220nF • 1.215V
= 8.76ms
30.5µA
14V • 68mV
= 95.2W
10mΩ
During an output overload or soft short, the voltage at the
OUT pin could stay at 3V or higher. The total overcurrent
fault time when VOUT = 3V is:
tOC =
220nF • 1.215V
= 27.4ms
9.75µA
The power dissipation in Q1 is:
150V – 27V
=123kΩ
1mA
P=
and P2t = 79.4W2S
RDRN is chosen to produce a current into the DRN pin of
1mA, during the maximum overvoltage transient event:
P=
(14V – 3V ) • 50mV = 55W
10mΩ
and P2t ≈ 83W2S
150kΩ is chosen to ensure enough margin.
Next CTMR is chosen to power up the output before the
TMR pin reaches the gateoff threshold of 1.215V:
16
CLOAD
IINRUSH
The power dissipation in Q1 is:
With C1 = 4.7µF and R1 = 10kΩ, high voltage transients up
to 200V with a pulse width of less than 10ms are filtered
out at the VCC pin. Longer surges are suppressed by D1.
IGATE(UP)
= VIN
ITMR(UP) ≈ 1.5µA. To limit the rise of VTMR to 0.4V
4.7µF is chosen to accommodate for the supply current
of the part and other conditions.
RDRN =
VIN • C2
=
SEL
CTMR
220nF
Figure 6. Design Example
C1=
VTMR
t INRUSH =
LTC4380
ON
ITMR(UP) • tINRUSH
Where
C2
47nF
VCC
C1
4.7µF
CTMR =
These conditions are well within the safe operating area
of the FDB33N25.
4380f
For more information www.linear.com/LTC4380
LTC4380
Applications Information
Q2
IRLR2908
12V
80VDC MAX
D3
Q3
1N4148
MMBE3904
R1
10k
R5
10k
DRN
D1
CMZ5933B
22V
C1
220nF
R2
150Ω
C2
0.1µF
RDRN
100k
D2
1N4148
OUTPUT
12V/2A
OUTPUT CLAMPED
CL
22µF AT 29.5V
R3
10Ω
R4
240k
R6
240k
RSNS
20mΩ
Q1
IRLR2908
GATE
VCC
SNS
OUT
LTC4380-2
ON
FLT
TMR
GND
SEL
CTMR
100nF
4380 TA02
Figure 7. 12V Overcurrent Protected High Side Switch
RSNS
10mΩ
Q1
IRL3714ZS
VIN
12V
20VDC MAX
VOUT
12V, 4A
OUTPUT CLAMPED
CL
100µF AT 29V
R3
10Ω
D2
DDZ9696T
9.1V
RDRN
100k
R1
10k
DRN
D1
CMZ5933B
22V
UV ≈ 10.2V
C1
220nF
R2
33Ω
C2
47nF
GATE
SNS
R4
51k
OUT
VCC
FLT
LTC4380-2
ON
R5
240k
GND
TMR
SEL
CTMR
220nF
4380 TA03
Figure 8. 12V Hot Swap Controller with Input UV Detection
4380f
For more information www.linear.com/LTC4380
17
LTC4380
Applications Information
R1
10k
RDRN
200k
R2
33Ω
C2
47nF
GATE
R4
51k
SNS
OUT
VCC
C1
220nF
VOUT
28V, 2A
OUTPUT CLAMPED
CL
22µF AT 38.5V
R3
10Ω
DRN
D1
CMZ5936B
30V
RSNS
20mΩ
Q1
FDB33N25
VIN
28V
250VDC MAX
FLT
LTC4380-4
ON
GND
SEL
TMR
CTMR
470nF
4380 TA04
Figure 9. 28V Surge Stopper with Output Clamped to Below 40V
20mΩ
FDB33N25
VIN
12V
22µF
10Ω
33Ω
10k
47nF
DRN
GATE
VCC
0.1µF
12V/1A
OUTPUT CLAMPED
AT ~ 27V
SNS
OUT
LTC4380-1
ON
GND
TMR
FLT
SEL
68V
CMHZ5266B
4380 TA06
Figure 10. 12V Surge Stopper with Fault Timer Disabled
18
4380f
For more information www.linear.com/LTC4380
LTC4380
Package Description
Please refer to http://www.linear.com/product/LTC4380#packaging for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
R = 0.125
TYP
6
0.40 ±0.10
10
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
5
0.75 ±0.05
0.200 REF
0.00 – 0.05
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF
(WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF
VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETER
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev F)
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.50
0.305 ±0.038
(.0197)
(.0120 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0.497 ±0.076
(.0196 ±.003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS) 0213 REV F
4380f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC4380
19
LTC4380
Typical Application
10nF
12Ω
175VDC MAX
250VPK MAX
INPUT
RSNS
40mΩ
FDB33N25
+
12V
CMPZ5242B
10Ω
1A OUTPUT
100µF
100V
200k
1W
10k
33Ω
250V
47nF
DRN
GATE
SNS
OUT
VCC
100V
100nF
33V
CMPZ5257B
ON
GND
TMR
100nF
100V
FLT
LTC4380-2
SEL
MBR160
3.3µF
16V
100k
43V
CMPZ5260B
4380 TA05
Figure 11. 48V Floating Surge Stopper
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT4356
Surge Stopper with Current Limit
4V to 80V Operation, 100V Protection, DFN-12, MSOP-10 and SO-16 Packages
LTC4359
Ideal Diode Controller
4V to 80V Operation, –40V Input Protection, DFN-8, MSOP-8 Packages
LTC4361
Overvoltage/Overcurrent Protection Controller
2.5V to 5.5V Operation, 80V Protection, TSOT-8 and DFN-8 Packages
LT4363
Surge Stopper with Current Limit
4V to 80V Operation, >100V Protection, DFN-12, MSOP-12 and SO-16 Packages
LTC4364
Surge Stopper with Ideal Diode
4V to 80V Operation, –40V to >100V Protection, DFN-14, MSOP-16 and
SO-16 Packages
LTC4365
OV, UV and Reverse Input Protection Controller
2.5V to 34V Operation, –40V to 60V Protection, DFN-8 and TSOT-8 Packages
LTC4366
High Voltage Surge Stopper
9V to >500V Operation, Floating Topology, TSOT-8 and DFN-8 Packages
LTC4367
OV, UV and Reverse Input Protection Controller
2.5V to 60V Operation, –40V to 100V Protection, DFN-8 and MSOP-8 Packages
LTC7860
Switching Surge Stopper
3.5V to 60V Operation, >100V Protection, MSOPE-12 Package
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4380
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC4380
4380f
LT 0416 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2016