Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer ICS841S104I DATA SHEET General Description Features The ICS841S104I is a PLL-based clock synthesizer specifically designed for PCI_Express™ Clock applications. This device generates a 100MHz differential HCSL clock from an input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.The ICS841S104I is available in a lead-free 24-Lead package. • • • • • • • • • • • Four 0.7V current mode differential HCSL output pairs Crystal oscillator interface: 25MHz Output frequency: 100MHz RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.145ps (typical) Cycle-to-cycle jitter: 20ps (maximum) I2C support with readback capabilities up to 400kHz Spread Spectrum for electromagnetic interference (EMI) reduction 3.3V operating supply mode -40°C to 85°C ambient operating temperature Available lead-free (RoHS 6) package PCI Express Gen 1, 2, 3 jitter compliant HiPerClockS™ Block Diagram XTAL_IN Pin Assignment 25MHz OSC PLL XTAL_OUT SDATA Pullup SCLK Pullup I2C Logic Divider Network 4 4 SRCT[1:4] SRCC[1:4] 4 IREF SRCT3 SRCC3 VSS VDD SRCT2 SRCC2 SRCT1 SRCC1 VSS VDD VSS IREF 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SRCC4 SRCT4 VDD SDATA SCLK XTAL_OUT XTAL_IN VDD VSS nc VDDA VSS ICS841S104I 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View ICS841S104EGI REVISION A JUNE 18, 2010 1 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Table 1. Pin Descriptions Number Name 1, 2 SRCT3, SRCC3 Output Type Description Differential output pair. HCSL interface levels. 3, 9, 11, 13, 16 VSS Power Power supply ground. 4, 10, 17, 22 VDD Power Positive supply pins. 5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels. 12 IREF Input An external fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode SRCCx, SRCTx clock outputs. Analog supply for PLL. 14 VDDA Power 15 nc Unused 18, 19 XTAL_IN, XTAL_OUT Input 20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain. LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output No connect. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Differential output pair. HCSL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 kΩ ICS841S104EGI REVISION A JUNE 18, 2010 Test Conditions 2 Minimum Typical Maximum Units ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default settings upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation 6:5 Chip select address, set to “00” to access device. 4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000” ICS841S104EGI REVISION A JUNE 18, 2010 3 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Table 3B. Block Read and Block Write Protocol Bit 1 2:8 Description = Block Write Start Slave address - 7 bits Bit Description = Block Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 20:27 28 29:36 37 38:45 46 Acknowledge from slave 19 Acknowledge from slave Byte Count - 8 bits 20 Repeat start Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop 21:27 Slave address - 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Byte Count from slave - 8 bits 38 Acknowledge 39:46 Data Byte 1 from slave - 8 bits 47 Acknowledge 48:55 Data Byte 2 from slave - 8 bits 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Table 3C. Byte Read and Byte Write Protocol Bit 1 2:8 Description = Byte Write Start Slave address - 7 bits Bit Description = Byte Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits Acknowledge from slave 19 Acknowledge from slave Data Byte- 8 bits 20 Repeat start 19 20:27 28 Acknowledge from slave 29 Stop ICS841S104EGI REVISION A JUNE 18, 2010 21:27 Slave address - 7 bits 28 Read 29 Acknowledge from slave 30:37 Data from slave - 8 bits 38 Not Acknowledge 39 Stop 4 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Control Registers Table 3D. Byte 0: Control Register 0 Bit @Pup Name 7 0 Reserved 6 1 5 1 Table 3G. Byte 3:Control Register 3 Description Bit @Pup Name Description Reserved 7 1 Reserved Reserved SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable 6 0 Reserved Reserved SRC[T/C]4 5 1 Reserved Reserved 4 0 Reserved Reserved SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Table 3H. Byte 4: Control Register 4 NOTE: Pup denotes Power-up. Table 3E. Byte 1: Control Register 1 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved Bit @Pup Name Description 0 Reserved Reserved Table 3I. Byte 5: Control Register 5 2 0 Reserved Reserved 7 1 0 Reserved Reserved 6 0 Reserved Reserved 0 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Table 3F. Byte 2: Control Register 2 Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 0 = -0.35%, 1 = - 0.5% 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On 2 0 SRC 1 1 Reserved Reserved 0 0 Reserved Reserved ICS841S104EGI REVISION A JUNE 18, 2010 5 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Table 3J. Byte 6: Control Register 6 Bit @Pup Name 7 0 TEST_SEL Table 3K. Byte 7: Control Register 7 Description Bit @Pup Name Description REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 6 0 TEST_MODE 3 0 Vendor ID Bit 3 5 0 Reserved Reserved 2 0 Vendor ID Bit 2 4 1 Reserved Reserved 1 0 Vendor ID Bit 1 3 0 Reserved Reserved 0 1 Vendor ID Bit 0 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved NOTE: Pup denotes Power-up. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 77.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.21 3.3 VDD V IDD Power Supply Current 80 mA IDDA Analog Supply Current 21 mA ICS841S104EGI REVISION A JUNE 18, 2010 Test Conditions 6 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V 10 µA -150 µA Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6A. PCI Express Jitter Specifications, VDD = 3.3V±5%, TA = -40°C to 85°C Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.8 21 86 ps tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2, 4 (PCIe Gen 2) ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 1.34 3.03 3.1 ps tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.18 0.3 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; NOTE 3, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.28 0.71 0.8 ps Parameter Symbol tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 Test Conditions Minimum NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. ICS841S104EGI REVISION A JUNE 18, 2010 7 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet AC Electrical Characteristics Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency fREF Reference frequency tjit(Ø) Phase Jitter, RMS (Random); NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tL PLL Lock Time FM SSC Modulation Frequency; NOTE 4 SSCRED Spectral Reduction; NOTE 4 VRB Ring-back Voltage Margin; NOTE 5, 6 VMAX Absolute Max. Output Voltage; NOTE 7, 8 VMIN Absolute Min. Output Voltage; NOTE 7, 9 -300 VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 250 ∆VCROSS Total Variation of VCROSS over all edges; NOTE 7, 10, 12 Rise/Fall Edge Rate; NOTE 7, 13 odc Test Conditions Minimum 25MHz crystal, ƒ = 100MHz, Integration Range: 12kHz – 20MHz Typical Maximum 100 MHz 25 MHz 1.145 ps 40 PLL Mode 25MHz Crystal 30 32 -7 -10 -100 Measured between 150mV to +150mV Output Duty Cycle Units ps 20 ps 50 ms 33.33 kHz dB 100 mV 1150 mV mV 550 mV 140 mV 0.6 4.0 V/ns 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz quartz crystal. NOTE 1: Refer to phase jitter plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: Measurement taken from differential waveform. NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. ICS841S104EGI REVISION A JUNE 18, 2010 8 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Noise Power dBc Hz Typical Phase Noise at 100MHz Offset Frequency (Hz) ICS841S104EGI REVISION A JUNE 18, 2010 9 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Parameter Measurement Information 3.3V±5% 3.3V±5% 3.3V±5% SCOPE 3.3V±5% 50Ω VDD VDD 50Ω 33Ω Measurement Point VDDA VDDA HCSL 49.9Ω 2pF HCSL 50Ω 33Ω IREF 50Ω IREF Measurement Point GND 475Ω GND 49.9Ω 2pF 475Ω 0V This load condition is used for IDD, tjit(cc), tjit(Ø), and tsk(o) measurements. 0V 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit SRCCx SRCC[1:4] SRCCx SRCT[1:4] ➤ tcycle n ➤ tcycle n+1 ➤ SRCTy ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles SRCTy tsk(o) Output Skew Cycle-to-Cycle Jitter VMAX = 1.15V SRCC SRCC VCROSS_MAX = 550mV VCROSS_DELTA = 140mV VCROSS_MIN = 250mV SRCT SRCT VMIN = -0.30V Single-ended Measurement Points for Absolute Cross Point and Swing ICS841S104EGI REVISION A JUNE 18, 2010 Single-ended Measurement Points for Delta Cross Point 10 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Parameter Measurement Information, continued TSTABLE Clock Period (Differential) VRB Positive Duty Cycle (Differential) +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Negative Duty Cycle (Differential) 0.0V SRCT SRCC SRCT SRCC VRB TSTABLE Differential Measurement Points for Ringback Differential Measurement Points for Duty Cycle/Period Phase Noise Plot Fall Edge Rate Noise Power Rise Edge Rate +150mV 0.0V -150mV SRCC SRCT f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Differential Measurement Points for Rise/Fall Edge Rate ICS841S104EGI REVISION A JUNE 18, 2010 RMS Phase Jitter 11 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841S104I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS841S104EGI REVISION A JUNE 18, 2010 12 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Crystal Input Interface The ICS841S104I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 15pF X1 18pF Parallel Crystal XTAL_OUT C2 22pF Figure 2. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm LVPECL 0.1uF XTAL_OUT Cry stal Input Interf ace R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS841S104EGI REVISION A JUNE 18, 2010 13 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Recommended Termination Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. Figure 4B. Recommended Termination ICS841S104EGI REVISION A JUNE 18, 2010 14 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht ( s ) = H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y ( s ) = X ( s ) × H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function PCIe Gen 3 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ICS841S104EGI REVISION A JUNE 18, 2010 For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 15 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Schematic Layout Figure 5 shows an example of ICS841S104I application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 =18pF and C2 = 33pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of HCSL termination are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. R5 SRCT1 R7 SRCC1 VDD 33 Zo = 50 + TL3 33 Zo = 50 VDD - TL5 R8 50 R9 50 Recommended for PCI Express Add-In Card 12 11 10 9 8 7 6 5 4 3 2 1 IREF U1 IR EF VSS VD D VSS SR C C 1 SR C T 1 SR C C 2 SR C T 2 VD D VSS SR C C 3 SR C T 3 R13 475 Ohm HCSL Termination 13 14 15 16 17 18 19 20 21 22 23 24 VSS VD D A nc VSS VD D XT AL_IN XT AL_OU T SC LK SD AT A VD D SR C T 4 SR C C 4 VDD=3.3V SRCT4 VDD VDDA C3 VDD C4 0.01u 10uF SRCC4 X1 J1 5 SDA 4 3 2 SCL 1 R8 R9 R7 SP - TL7 VDD C1 18pF R6 SP Zo = 50 R11 50 F p 8 1 VDD 25MHz C2 33pF + TL6 SC LK SD AT A R3 10 Zo = 50 0 Recommended for PCI Express Point-to-Point Connection VDD (U1-4) 0 R12 50 VDD C5 0.1uF (U1-10) C6 0.1uF (U1-17) C7 0.1uF (U1-22) C8 0.1uF Figure 5. ICS841S104I Application Schematic. ICS841S104EGI REVISION A JUNE 18, 2010 16 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Spread Spectrum Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used with 0.5% down-spread from the nominal 100MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 6A below. amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 6B. The ratio of this difference to the fundamental frequency is typically 0.5%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 2B. It is important to note the ICS841S104I 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. ➤ The ICS841S104I triangle modulation frequency deviation is 0.5% down-spread from the nominal clock frequency. An example of the Fnom (1 - δ) Fnom 0.5/fm ➤ 1/fm Figure 6A. Triangle Frequency Modulation ∆ – 7dBm A B ➔ ➔ δ = 0.25% Figure 6B. 100MHz Clock Output In Frequency Domain (A) Spread-Spectrum OFF (B) Spread-Spectrum ON ICS841S104EGI REVISION A JUNE 18, 2010 17 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS841S104I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841S104I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. The maximum current at 85°C is as follows: IDD_MAX = 77mA IDDA_MAX = 20mA • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(77mA + 20mA) = 336.105mW • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW Total Power_MAX = 336.105mW + 178mW = 514.105mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.514W * 77.5°C/W = 124.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS841S104EGI REVISION A JUNE 18, 2010 0 1 2.5 77.5°C/W 73.2°C/W 71.0°C/W 18 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 7. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841S104EGI REVISION A JUNE 18, 2010 19 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Reliability Information Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 77.5°C/W 73.2°C/W 71.0°C/W Transistor Count The transistor count for ICS841S104I is: 11,775 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS841S104EGI REVISION A JUNE 18, 2010 20 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet Ordering Information Table 10. Ordering Information Part/Order Number 841S104EGILF 841S104EGILFT Marking ICS841S104EIL ICS841S104EIL Package “Lead-Free” 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS841S104EGI REVISION A JUNE 18, 2010 21 ©2010 Integrated Device Technology, Inc. CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER ICS841S104I Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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