ADC1010S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1010S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 62 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 10-bit pipelined ADC core Clock input divided by 2 for less jitter Single 3 V supply Flexible input voltage range: 1 V (p-p) to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin compatible with the ADC1410S series and the ADC1210S series Input bandwidth, 600 MHz Power dissipation, 430 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT-of-Range (OTR) detection Offset binary, two’s complement, gray code Power-down and Sleep modes HVQFN40 package 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio ® ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1010S125HN-C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm SOT618-1 ADC1010S105HN-C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm SOT618-1 ADC1010S080HN-C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm SOT618-1 ADC1010S065HN-C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm SOT618-1 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1010S ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTR INP T/H INPUT STAGE ADC CORE 10-BIT PIPELINED OUTPUT DRIVERS INM OUTPUT DRIVERS CLOCK INPUT STAGE AND DUTY CYCLE CONTROL CLKP CLKM SYSTEM REFERENCE AND POWER MANAGEMENT CMOS: D9 to D0 or LVDS DDR: D8_D9_M to D0_D1_M D8_D9_P to D0_D1_P CMOS: DAV or LVDS DDR: DAVP DAVM PWD OE VCM SENSE REFT VREF REFB 005aaa134 Fig 1. Block diagram ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 2 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 6. Pinning information 5 AGND 6 INM 7 INP 8 23 D3 AGND 9 22 D4 VDDA 10 21 D5 26 D0 D6 20 D7 19 D8 18 D9 17 PWD 16 OE 15 DEC 14 CLKM 13 CLKP 12 VDDA 11 31 DAVM 32 DAVP 33 VDDO INM 7 24 D2_D3_P INP 8 23 D2_D3_M AGND 9 22 D4_D5_P VDDA 10 21 D4_D5_M 005aaa135 Transparent top view Fig 2. 34 OGND 6 25 D1 24 D2 35 OTR AGND 27 n.c. 26 D0_D1_P ADC1010S HVQFN40 25 D0_D1_M D6_D7_P 20 VDDA 36 SCLK/DFS 5 D6_D7_M 19 27 n.c. 37 SDIO/ODS VDDA D8_D9_P 18 4 38 CS 4 D8_D9_M 17 VCM 39 SENSE 28 n.c. VCM 28 n.c. ADC1010S HVQFN40 40 VREF 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 3 PWD 16 3 29 n.c. AGND OE 15 AGND 29 n.c. 30 n.c. 2 DEC 14 2 1 REFT CLKM 13 REFT 30 n.c. REFB CLKP 12 1 terminal 1 index area VDDA 11 REFB 38 CS terminal 1 index area 39 SENSE 40 VREF 6.1 Pinning 005aaa136 Transparent top view Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS DDR digital outputs selected 6.2 Pin description Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA 5 P analog power supply AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA 10 P analog power supply VDDA 11 P analog power supply CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 3 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 2. Symbol Pin description (CMOS digital outputs) …continued Pin Type [1] Description D9 17 O data output bit 9 (Most Significant Bit (MSB)) D8 18 O data output bit 8 D7 19 O data output bit 7 D6 20 O data output bit 6 D5 21 O data output bit 5 D4 22 O data output bit 4 D3 23 O data output bit 3 D2 24 O data output bit 2 D1 25 O data output bit 1 D0 26 O data output bit 0 (Least Significant Bit (LSB)) n.c. 27 - not connected n.c. 28 - not connected n.c. 29 - not connected n.c. 30 - not connected DAV 31 O data valid output clock n.c. 32 - not connected VDDO 33 P output power supply OGND 34 G output ground OTR 35 O out of range SCLK/DFS 36 I SPI clock SDIO/ODS 37 I/O SPI data IO CS 38 I SPI chip select SENSE 39 I reference programming pin VREF 40 I/O voltage reference input/output data format select output data standard [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Pin description (LVDS DDR) digital outputs) Symbol Pin [1] Type [2] Description D8_D9_M 17 O differential output data D8 and D9 multiplexed, complement D8_D9_P 18 O differential output data D8 and D9 multiplexed, true D6_D7_M 19 O differential output data D6 and D7 multiplexed, complement D6_D7_P 20 O differential output data D6 and D7 multiplexed, true D4_D5_M 21 O differential output data D4 and D5 multiplexed, complement D4_D5_P 22 O differential output data D4 and D5 multiplexed, true D2_D3_M 23 O differential output data D2 and D3 multiplexed, complement D2_D3_P 24 O differential output data D2 and D3 multiplexed, true D0_D1_M 25 O differential output data D0 and D1 multiplexed, complement D0_D1_P 26 O differential output data D0 and D1 multiplexed, true n.c. 27 - not connected n.c. 28 - not connected n.c. 29 - not connected ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 4 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 3. Pin description (LVDS DDR) digital outputs) …continued Symbol Pin [1] Type [2] n.c. 30 - not connected DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true Description [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit pins D9 to D0 or pins D8_D9_P to D0_D1_P and D8_D9_M to D0_D1_M 0.4 +3.9 V +3.9 V VO output voltage VDDA analog supply voltage 0.4 VDDO output supply voltage 0.4 +3.9 V Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C Tj junction temperature - 125 C 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Typ Unit Rth(j-a) thermal resistance from junction to ambient [1] 22.5 K/W Rth(j-c) thermal resistance from junction to case [1] 11.7 K/W [1] Conditions Value for six layers board in still air with a minimum of 25 thermal vias. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 5 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 9. Static characteristics Table 6. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V CMOS mode 1.65 1.8 3.6 V LVDS DDR mode 2.85 3.0 3.6 V Supplies VDDA analog supply voltage VDDO output supply voltage IDDA analog supply current fclk = 125 Msps; fi = 70 MHz - 210 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi = 70 MHz - 10 - mA LVDS DDR mode: fclk = 125 Msps; fi = 70 MHz - 35 - mA ADC1010S125; analog supply only - 630 - mW ADC1010S105; analog supply only - 550 - mW ADC1010S080; analog supply only - 430 - mW ADC1010S065; analog supply only - 380 - mW Power-down mode - 2 - mW Sleep mode - 40 - mW P power dissipation Clock inputs: pins CLKP and CLKM Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Vi(clk)dif differential clock input voltage peak-to-peak - 1.6 - V differential clock input voltage peak - 3.0 - V SINE wave Vi(clk)dif Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) VIL LOW-level input voltage - - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - - V Logic inputs: pins PWD and OE VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VDDA V IIL LOW-level input current - 55 - A IIH HIGH-level input current - 65 - A Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - VDDA V IIL LOW-level input current 10 - +10 A IIH HIGH-level input current 50 - +50 A CI input capacitance - 4 - pF ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 6 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Digital outputs, CMOS mode: pins D9 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage OGND - 0.2VDDO V VOH HIGH-level output voltage 0.8VDDO - VDDO V CO output capacitance - 3 - pF high impedance; OE = HIGH Output levels, VDDO = 1.8 V VOL LOW-level output voltage OGND - 0.2VDDO V VOH HIGH-level output voltage 0.8VDDO - VDDO V Digital outputs, LVDS mode: pins D8_D9_P to D0_D1_P, D8_D9_M to D0_D1_M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - 3 - pF Analog inputs: pins INP and INM II input current 5 - +5 A Ri(dif) differential input resistance - 19.8 - k Ci(dif) differential input capacitance VI(cm) common-mode input voltage Bi input bandwidth VI(dif) differential input voltage VINP = VINM peak-to-peak - 2.8 - pF 1.1 1.5 2.5 V - 650 - MHz 1 - 2 V Common mode output voltage: pin VCM VO(cm) common-mode output voltage - VDDA / 2 - V IO(cm) common-mode output current - 4 - mA output 0.5 - 1 V input 0.5 - 1 V - 0.07 - LSB 0.06 0.04 +0.06 LSB - 2 - mV I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity Eoffset offset error EG gain error full-scale power supply rejection ratio 200 mV (p-p) on VDDA; fi = DC guaranteed no missing codes 0.5 % Supply PSRR [1] - 54 - dB Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP VINM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 7 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology ADC1010S_SER 3 Product data sheet 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Dynamic characteristics[1] Symbol Parameter Conditions ADC1010S065 ADC1010S080 ADC1010S105 ADC1010S125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max fi = 3 MHz - 87 - - 87 - - 89 - - 91 - dBc fi = 30 MHz - 86 - - 86 - - 89 - - 90 - dBc Analog signal processing 2H 3H ENOB 8 of 37 © IDT 2012. All rights reserved. SFDR total harmonic distortion effective number of bits signal-to-noise ratio spurious-free dynamic range - 85 - - 85 - - 87 - - 88 - dBc fi = 170 MHz - 82 - - 82 - - 84 - - 86 - dBc fi = 3 MHz - 86 - - 86 - - 88 - - 90 - dBc fi = 30 MHz - 85 - - 85 - - 88 - - 89 - dBc fi = 70 MHz - 84 - - 84 - - 86 - - 87 - dBc fi = 170 MHz - 81 - - 81 - - 83 - - 85 - dBc fi = 3 MHz - 83 - - 83 - - 85 - - 87 - dBc fi = 30 MHz - 82 - - 82 - - 85 - - 86 - dBc fi = 70 MHz - 81 - - 81 - - 83 - - 84 - dBc fi = 170 MHz - 78 - - 78 - - 80 - - 82 - dBc fi = 3 MHz - 9.9 - - 9.9 - - 9.9 - - 9.9 - bits fi = 30 MHz - 9.9 - - 9.9 - - 9.9 - - 9.9 - bits fi = 70 MHz - 9.9 - - 9.9 - - 9.9 - - 9.9 - bits fi = 170 MHz - 9.9 - - 9.9 - - 9.9 - - 9.9 - bits fi = 3 MHz - 61.7 - - 61.7 - - 61.6 - - 61.6 - dBFS fi = 30 MHz - 61.6 - - 61.6 - - 61.6 - - 61.6 - dBFS fi = 70 MHz - 61.6 - - 61.6 - - 61.5 - - 61.5 - dBFS fi = 170 MHz - 61.5 - - 61.5 - - 61.5 - - 61.5 - dBFS fi = 3 MHz - 86 - - 86 - - 88 - - 90 - dBc fi = 30 MHz - 85 - - 85 - - 88 - - 89 - dBc fi = 70 MHz - 84 - - 84 - - 86 - - 87 - dBc fi = 170 MHz - 81 - - 81 - - 83 - - 85 - dBc ADC1010S series SNR third harmonic level fi = 70 MHz Single 10-bit ADC; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 THD second harmonic level Dynamic characteristics[1] …continued Symbol Parameter IMD [1] Conditions ADC1010S065 ADC1010S080 ADC1010S105 ADC1010S125 Integrated Device Technology ADC1010S_SER 3 Product data sheet Table 7. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Intermodulation fi = 3 MHz distortion fi = 30 MHz - 89 - - 89 - - 92 - - 93 - dBc - 88 - - 88 - - 92 - - 92 - dBc fi = 70 MHz - 87 - - 87 - - 90 - - 90 - dBc fi = 170 MHz - 84 - - 85 - - 87 - - 88 - dBc Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP VINM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. 10.2 Clock and digital output timing Table 8. Symbol Clock input and digital output timing characteristics[1] Parameter Conditions ADC1010S065 ADC1010S080 ADC1010S105 ADC1010S125 Unit Rev. 03 — 2 July 2012 Min Typ Max Min Typ Max Min Typ Max Min Typ Max 40 - 65 60 - 80 75 - 105 100 - 125 - 13.5 - - 13.5 - - 13.5 - - 13.5 - DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 % DCS_EN = logic 0 Clock timing input: pins CLKP and CLKM MHz tlat(data) data latency time clk clock duty cycle 45 50 55 45 50 55 45 50 55 45 50 55 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time - 76 - - 76 - - 76 - - 76 - s 13.6 14.9 16.4 11.9 12.9 14.4 8.0 10.8 12.4 8.2 9.7 - 4.2 - - 3.6 - - 3.3 - - 3.4 - ns clock cycles CMOS Mode timing output: pins D9 to D0 and DAV tPD propagation DATA delay DAV 11.3 ns 9 of 37 © IDT 2012. All rights reserved. tsu set-up time - 12.5 - - 9.8 - - 6.8 - - 5.6 - ns th hold time - 3.4 - - 3.3 - - 3.1 - - 2.8 - ns 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 ns 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 ns 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 ns tr rise time DATA [2] DAV tf fall time DATA [2] ADC1010S series clock frequency Single 10-bit ADC; CMOS or LVDS DDR digital outputs fclk Symbol Clock input and digital output timing characteristics[1] …continued Parameter Conditions ADC1010S065 Min Typ ADC1010S080 Max Min Typ ADC1010S105 Max Min ADC1010S125 Integrated Device Technology ADC1010S_SER 3 Product data sheet Table 8. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Unit Typ Max Min Typ Max LVDS DDR mode timing output: pins D8_D9_P to D0_D1_P, D8_D9_M to D0_D1_M, DAVP and DAVM tPD propagation DATA delay DAV tsu set-up time th hold time tr rise time DATA [3] DAV tf fall time DATA [3] 3.3 5.1 7.6 2.9 4.6 7.1 2.5 4.2 6.8 2.2 4.0 6.6 ns - 2.8 - - 2.5 - - 2.3 - - 2.2 - ns - 5.4 - - 4.1 - - 2.6 - - 1.9 - ns - 2.2 - - 2.0 - - 1.8 - - 1.7 - ns 0.5 - 5 0.5 - 5 0.5 - 5 0.5 - 5 ns 0.18 - 2.4 0.18 - 2.4 0.18 - 2.4 0.18 - 2.4 ns 0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 ns Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP VINM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. [3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV. ADC1010S series 10 of 37 © IDT 2012. All rights reserved. Single 10-bit ADC; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 [1] ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 4. CMOS mode and clock timing N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk Fig 5. LDVS DDR mode and clock timing ADC1010S_SER 3 Product data sheet 005aaa061 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 11 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. SPI timings characteristics[1] Symbol Parameter tw(SCLK) SCLK pulse width tw(SCLKH) SCLK HIGH pulse width - 16 - ns tw(SCLKL) SCLK LOW pulse width - 16 - ns tsu set-up time data to SCLK HIGH - 5 - ns CS to SCLK HIGH - 5 - ns data to SCLK HIGH - 2 - ns CS to SCLK HIGH - 2 - ns - 25 - MHz hold time th fclk(max) [1] Conditions maximum clock frequency Min Typ Max Unit - 40 - ns Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 12 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 001aam619 3.2 001aam614 16 C (pF) R (kΩ) 3.0 12 2.8 8 2.6 4 2.4 0 50 Fig 7. 150 250 350 450 550 f (MHz) Capacitance as a function of frequency 001aam616 100 SFDR (dBc) 50 Fig 8. 150 250 350 450 550 f (MHz) Resistance as a function of frequency 001aam615 80 (1) SNR (dBFS) (1) 80 60 60 (2) (2) 40 40 20 20 0 0 10 30 50 70 δ (%) 90 10 T = 25 C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off (2) DCS off SFDR as a function of duty cycle () 70 δ (%) 90 Fig 10. SNR as a function of duty cycle () ADC1010S_SER 3 Product data sheet 50 T = 25 C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on Fig 9. 30 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 13 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 001aam617 92 SFDR (dBc) 88 001aam618 80 (1) SNR (dBFS) (2) 60 (1) (2) (3) (3) 84 40 80 20 10 30 50 70 δ (%) 90 (1) Tamb = 40 C/typical supply voltages 10 30 50 70 δ (%) (1) Tamb = 40 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages Fig 11. SFDR as a function of duty cycle () Fig 12. SNR as a function of duty cycle () 001aam659 90 90 001aam660 75 SFDR (dBc) SNR (dBFS) 86 73 82 71 78 69 74 67 70 65 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 VI(cm) (V) Fig 13. SFDR as a function of common-mode input voltage (VI(cm)) 1.0 1.5 2.0 2.5 3.0 3.5 VI(cm) (V) Fig 14. SNR as a function of common-mode input voltage (VI(cm)) ADC1010S_SER 3 Product data sheet 0.5 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 14 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1010S can be controlled via SPI or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device remains in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 15. CS SCLK/DFS SDIO/ODS Pin control mode Data format two's complement SPI control mode Data format offset binary LVDS DDR CMOS R/W W1 W0 A12 005aaa039 Fig 15. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1010S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 20) or by using pins PWD and OE in Pin control mode, as described in Table 10. Table 10. Operating mode selection via pin PWD and OE Pin PWD Pin OE Operating mode Output high-Z LOW LOW Power-up no LOW HIGH Power-up yes HIGH LOW Sleep yes HIGH HIGH Power-down yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or by using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 15 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1010S supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 22). The equivalent circuit of the sample and hold input stage, including Electrostatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16. Package ESD Parasitics Switch INP Ron = 15 Ω 8 Internal clock 4 pF Sampling capacitor Switch INM Ron = 15 Ω 7 Internal clock 4 pF Sampling capacitor 005aaa043 Fig 16. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (R-C filter in Figure 17) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 16 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs R INP C R INM 005aaa073 Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency - typical values Input frequency R C 3 MHz 25 12 pF 70 MHz 12 8 pF 170 MHz 12 8 pF 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 18 would be suitable for a baseband application. ADT1-1WT 100 nF analog input 25 Ω 100 nF INP 25 Ω 12 pF 100 nF 100 nF 25 Ω 25 Ω INM VCM 100 nF 100 nF 005aaa044 Fig 18. Single transformer configuration suitable for baseband applications The configuration shown in Figure 19 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 17 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs ADT1-1WT analog input 100 nF ADT1-1WT 50 Ω 12 Ω INP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INM VCM 100 nF 100 nF 005aaa045 Fig 19. Dual transformer configuration suitable for a high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1010S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 22). See Figure 21 to Figure 24. The equivalent reference circuit is shown in Figure 20. An external reference is also possible by providing a voltage on pin VREF as described in Figure 23. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 18 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs REFT REFERENCE AMP REFB VREF EXT_ref EXT_ref BUFFER BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12. Reference selection Selection SPI bit INTREF_EN SENSE pin VREF pin Full-scale (p-p) internal (Figure 21) 0 AGND 330 pF capacitor to AGND 2V internal (Figure 22) 0 pin VREF connected to pin SENSE and via 1 V a 330 pF capacitor to AGND external (Figure 23) 0 VDDA internal via SPI (Figure 24) 1 pin VREF connected to pin SENSE and via 1 V to 2 V 330 pF capacitor to AGND [1] external voltage between 0.5 V and 1 V[1] 1 V to 2 V The voltage on pin VREF is doubled internally to generate the internal reference voltage. Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 19 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa119 005aaa118 Fig 23. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 24. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak) (see Table 13). Table 13. Reference SPI gain control INTREF[2:0] Gain (dB) Full-scale (V (p-p)) 000 0 2 001 1 1.78 010 2 1.59 011 3 1.42 100 4 1.26 101 5 1.12 110 6 1 111 reserved x ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 20 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. package ESD parasitics COMMON-MODE REFERENCE 1.5 V VCM 0.1 μF ADC core 005aaa051 Fig 25. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. 11.4 Clock input 11.4.1 Drive modes The ADC1010S can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input 005aaa174 a. Rising edge LVCMOS CLKM 005aaa053 b. Falling edge LVCMOS Fig 26. LVCMOS single-ended clock input ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 21 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa054 005aaa173 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode voltage of the differential input stage is set via internal 5 k resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage. Fig 28. Equivalent input circuit ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 22 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 21), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1010S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 21). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 29. The buffer is powered by a separate power supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO Parasitics ESD Package 50 Ω LOGIC DRIVER Dx OGND 005aaa057 Fig 29. CMOS digital output buffer ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 23 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs The output resistance is 50 and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 23). VDDO 3.5 mA typ − + DxP/Dx + 1P 100 Ω RECEIVER DxM/Dx + 1M − + OGND 005aaa058 Fig 30. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 resistor (typical) at the receiver side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and Table 32). VDDO 3.5 mA typ − + DxP/Dx + 1P 100 Ω RECEIVER DxM/Dx + 1M + − OGND 005aaa059 Fig 31. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATA[1:0]; see Table 31) in order to adjust the output logic voltage levels. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 24 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 14. LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value () 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1010S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in Figure 4 and Figure 5 respectively. 11.5.4 OuT-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0]. Table 15. Fast OTR register FASTOTR_DET[2:0] Detection level (dB) 000 20.56 001 16.12 010 11.02 011 7.82 100 5.49 101 3.66 110 2.14 111 0.86 11.5.5 Digital offset By default, the ADC1010S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25). 11.5.6 Test patterns For test purposes, the ADC1010S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER[9:0]; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the analog input. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 25 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 16. Output codes VINP VINM Offset binary Two’s complement OTR pin < 1 00 0000 0000 10 0000 0000 1 1.0000000 00 0000 0000 10 0000 0000 0 0.9980469 00 0000 0001 10 0000 0001 0 0.9960938 00 0000 0010 10 0000 0010 0 0.9941406 00 0000 0011 10 0000 0011 0 0.9921875 00 0000 0100 10 0000 0100 0 .... .... .... 0 0.0039063 01 1111 1110 11 1111 1110 0 0.0019531 01 111 1111 11 1111 1111 0 0.0000000 10 0000 0000 00 0000 0000 0 +0.0019531 10 0000 0001 00 0000 0001 0 +0.0039063 10 0000 0010 00 0000 0010 0 .... .... .... 0 +0.9921875 11 1111 1011 01 1111 1011 0 +0.9941406 11 1111 1100 01 1111 1100 0 +0.9960938 11 1111 1101 01 1111 1101 0 +0.9980469 11 1111 1110 01 1111 1110 0 +1.0000000 11 1111 1111 01 1111 1111 0 > +1 11 1111 1111 01 1111 1111 1 11.6 Serial peripheral interface 11.6.1 Register description The ADC1010S serial interface is a synchronous serial communications port that allows easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on pin CS. A minimum of three bytes is transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 18). Table 17. Instruction bytes for the SPI MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18). ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 26 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 18. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end of data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 Instruction bytes D4 D3 D2 Register N (data) D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N + 1 (data) 005aaa062 Fig 32. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS triggers a transition to SPI control mode. When the ADC1010S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 33). Once in SPI control mode, the output data standard can be changed via bit LVDS_CMOS in Table 23. When the ADC1010S enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23. ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 27 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 28 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. Integrated Device Technology ADC1010S_SER 3 Product data sheet 11.6.3 Register allocation map Register allocation map Register name R/W Bit definition 0005 Reset and operating mode R/W SW_RST 0006 Clock R/W - - - 0008 Internal reference R/W - - 0011 Output data standard R/W - 0012 Output clock R/W 0013 Offset 0014 Bit 7 Bit 6 Bit 5 Bit 4 Default Bit 3 Bit 2 - - SE_SEL DIFF_SE - - - INTREF_EN - - LVDS_ CMOS OUTBUF - - - - DAVINV R/W - - Test pattern 1 R/W - - 0015 Test pattern 2 R/W 0016 Test pattern 3 R/W 0017 Fast OTR R/W - - - - 0020 CMOS output R/W - - - - 0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN 0022 LVDS DDR O/P 2 R/W - - - RESERVED[2:0] Bit 1 Bit 0 OP_MODE[1:0] CLKDIV DCS_EN INTREF[2:0] OUTBUS_ SWAP - DATA_FORMAT[1:0] DAVPHASE[2:0] 0000 1110 TESTPAT_SEL[2:0] 0000 0000 TESTPAT_USER[9:2] 0000 0000 - - FASTOTR BIT_BYTE_WISE - FASTOTR_DET[2:0] DATAI_ x2_EN 0000 0000 0000 0000 DATA_DRV[1:0] 0000 1110 DATAI[1:0] 0000 0000 LVDS_INT_TER[2:0] 0000 0000 29 of 37 © IDT 2012. All rights reserved. ADC1010S series - - DAV_DRV[1:0] DAVI[1:0] 0000 0000 0000 0000 - TESTPAT_ USER[1:0] 0000 0001 0000 0000 DIG_OFFSET[5:0] - Bin 0000 0000 Single 10-bit ADC; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 Addr Hex ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 20. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset of the SPI registers 6 to 4 RESERVED[2:0] 000 reserved 3 to 2 - 00 not used 1 to 0 OP_MODE[1:0] R/W operating mode 00 normal (power-up) 01 power-down 10 sleep 11 normal (power-up) Table 21. Clock control register (address 0006h) bit description Default values are highlighted. Bit Symbol 7 to 5 - 4 SE_SEL 3 DIFF_SE Access Value Description 000 not used R/W single-ended clock input pin select 0 CLKM 1 CLKP R/W differential/single ended clock input select 0 1 2 - 1 CLKDIV 0 R/W 1 DCS_EN single-ended not used clock input divide by 2 0 0 fully differential R/W disabled enabled duty cycle stabilizer 0 disabled 1 enabled ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 30 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 22. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 INTREF_EN Access Value Description 0000 not used R/W programmable internal reference enable 0 disable 1 2 to 0 INTREF[2:0] active R/W programmable internal reference 000 FS = 2 V 001 FS = 1.78 V 010 FS = 1.59 V 011 FS = 1.42 V 100 FS = 1.26 V 101 FS = 1.12 V 110 FS = 1 V 111 reserved Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit Symbol 7 to 5 - 4 LVDS_CMOS Access Value Description 000 not used R/W output data standard: LVDS DDR or CMOS 0 1 3 2 1 to 0 OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] R/W CMOS LVDS DDR output buffers enable 0 output enabled 1 output disabled (high-Z) R/W output bus swapping 0 no swapping 1 output bus is swapping (MSB becomes LSB and vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 31 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 24. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 DAVINV Access Value Description 0000 not used R/W output clock data valid (DAV) polarity 0 normal 1 2 to 0 DAVPHASE[2:0] inverted R/W DAV phase select 000 output clock shifted (ahead) by 6/16 tclk 001 output clock shifted (ahead) by 5/16 tclk 010 output clock shifted (ahead) by 4/16 tclk 011 output clock shifted (ahead) by 3/16 tclk 100 output clock shifted (ahead) by 2/16 tclk 101 output clock shifted (ahead) by 1/16 tclk 110 default value as defined in timing section 111 output clock shifted (delayed) by 1/16 tclk Table 25. Offset register (address 0013h) bit description Default values are highlighted. Bit Symbol 7 to 6 - 5 to 0 DIG_OFFSET[5:0] Access Value Description 00 not used R/W digital offset adjustment 011111 +31 LSB ... ... 000000 0 ... ... 100000 32 LSB Table 26. Test pattern register 1 (address 0014h) bit description Default values are highlighted. Bit Symbol 7 to 3 - 2 to 0 TESTPAT_SEL[2:0] Access Value Description 00000 not used R/W digital test pattern select 000 off 001 mid scale 010 FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 32 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol Access Value 7 to 0 TESTPAT_USER[9:2] R/W 00000000 custom digital test pattern (bits 9 to 2) Description Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 6 TESTPAT_USER[1:0] R/W 00 custom digital test pattern (bits 1 to 0) 5 to 0 - 000000 not used Table 29. Fast OTR register (address 0017h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 FASTOTR 2 to 0 Access Value Description 0000 not used R/W FASTOTR_DET[2:0] fast OuT-of-Range (OTR) detection 0 disabled 1 enabled R/W set fast OTR detect level 000 20.56 dB 001 16.12 dB 010 11.02 dB 011 7.82 dB 100 5.49 dB 101 3.66 dB 110 2.14 dB 111 0.86 dB Table 30. CMOS output register (address 0020h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 to 2 DAV_DRV[1:0] 1 to 0 DATA_DRV[1:0] Access Value Description 0000 not used R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 33 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol 7 to 6 - 5 DAVI_x2_EN Access Value Description 00 not used R/W double LVDS current for DAV LVDS buffer 0 disabled 1 4 to 3 2 DAVI[1:0] DATAI_x2_EN enabled R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA R/W double LVDS current for DATA LVDS buffer 0 disabled 1 1 to 0 DATAI[1:0] enabled R/W LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 BIT_BYTE_WISE 2 to 0 LVDS_INT_TER[2:0] Access Value Description 0000 not used R/W DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge/odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge/LSB data bits output on DAV falling edge) R/W internal termination for LVDS buffer (DAV and DATA) 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60 ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 34 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A E A1 c detail X C e1 e 1/2 e 20 y y1 C v M C A B w M C b 11 L 21 10 e e2 Eh 1/2 1 e 30 terminal 1 index area 40 31 Dh X 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 5 mm c D(1) Dh E(1) Eh 0.2 6.1 5.9 4.25 3.95 6.1 5.9 4.25 3.95 e e1 4.5 0.5 e2 L v w y y1 4.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT618-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 35. Package outline SOT618-1 (HVQFN40) ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 35 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 13. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1010S_SER v.3 20120702 Product data sheet - ADC1010S_SER_2 ADC1010S_SER v.2 20101228 Product data sheet - ADC1010S_SER_1 Modifications: ADC1010S_SER_1 • • • Data sheet status changed from Preliminary to Product. • Section 10.4 “Typical characteristics” added to the data sheet. Text and drawings updated throughout entire data sheet. SOT618-6 changed to SOT618-1. See Table 1 “Ordering information” and Figure 35 “Package outline SOT618-1 (HVQFN40)”. 20100409 Preliminary data sheet - - 14. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1010S_SER 3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 36 of 37 ADC1010S series Integrated Device Technology Single 10-bit ADC; CMOS or LVDS DDR digital outputs 15. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Clock and digital output timing . . . . . . . . . . . . . 9 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical characteristics . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI and Pin control modes . . . . . . . . . . . . . . . 15 Operating mode selection. . . . . . . . . . . . . . . . 15 Selecting the output data standard . . . . . . . . . 15 Selecting the output data format. . . . . . . . . . . 16 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 12 13 14 15 ADC1010S_SER 3 Product data sheet System reference and power management . . Internal/external references . . . . . . . . . . . . . . Programmable full-scale . . . . . . . . . . . . . . . . Common-mode output voltage (VO(cm)) . . . . . Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent input circuit . . . . . . . . . . . . . . . . . . Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . Clock input divider . . . . . . . . . . . . . . . . . . . . . Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . Digital output buffers: CMOS mode . . . . . . . . Digital output buffers: LVDS DDR mode . . . . DAta Valid (DAV) output clock . . . . . . . . . . . . OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . Output codes versus input voltage. . . . . . . . . Serial peripheral interface . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 20 21 21 21 21 22 23 23 23 23 24 25 25 25 25 26 26 26 27 29 35 36 36 37 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 37 of 37