IDT 7203L25J

IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9
8,192 x 9, 16,384 x 9
32,768 x 9 and 65,536 x 9
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
2,048 x 9 organization (IDT7203)
4,096 x 9 organization (IDT7204)
8,192 x 9 organization (IDT7205)
16,384 x 9 organization (IDT7206)
32,768 x 9 organization (IDT7207)
65,636 x 9 organization (IDT7208)
High-speed: 12ns access time
Low power consumption
— Active: 660mW (max.)
— Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567
(IDT7203), and 5962-89568 (IDT7204) are listed on this function
•
Industrial temperature range (–40°C to +85°C) is available
(plastic packages only)
Green parts available, see ordering information
DESCRIPTION:
The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers
with internal pointers that load and empty data on a first-in/first-out basis. The
device uses Full and Empty flags to prevent data overflow and underflow and
expansion logic to allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of the Write (W) and
Read (R) pins.
The device's 9-bit width provides a bit for a control or parity at the user’s
option. It also features a Retransmit (RT) capability that allows the read pointer
to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is
available in the single device and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
are designed for applications requiring asynchronous and simultaneous read/
writes in multiprocessing, rate buffering and other applications.
Military grade product is manufactured in compliance with MIL-STD-883,
Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D0 -D8)
W
WRITE
CONTROL
RAM ARRAY
WRITE
POINTER
READ
POINTER
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
32,768 x 9
65,536 x 9
THREESTATE
BUFFERS
R
RS
DATA OUTPUTS
(Q 0-Q 8 )
READ
CONTROL
FLAG
LOGIC
XI
EF
FF
EXPANSION
LOGIC
XO/HF
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2012 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.
RESET
LOGIC
FL/RT
2661 drw01
JUNE 2012
DSC-2661/18
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
32
31
30
INDEX
Vcc
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
6
7
8
9
10
11
12
13
1
4
3
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
Q3
Q8
GND
NC
R
Q4
Q5
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
D3
D8
W
NC
Vcc
D4
D5
PIN CONFIGURATIONS
2661 drw02b
2661 drw02a
TOP VIEW
Package Type
PLASTIC DIP
PLASTIC THIN DIP
CERDIP
THIN CERDIP
SOIC
Reference
Identifier
P28-1
P28-2
D28-1
D28-3
SO28-3
Order
Code
P
TP
D
TD
SO
TOP VIEW
Device
Availability
All devices
All except IDT7207/7208
All except IDT7208
Only for IDT7203/7204/7205
Only for IDT7204
Reference
Identifier
Order
Code
PLCC
J32-1
J
All devices
LCC
L32-1
L
All except IDT7208
Package Type
(1)
Device
Availability
NOTE:
1. This package is only available in the military temperature range.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
ABSOLUTE MAXIMUM RATINGS
Symbol
V TERM
Rating
Terminal
Voltage with
Respect to GND
Com'l & Ind'l
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
Commercial/Industrial/Military
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
Input High Voltage
Commercial/Industrial
2.0
—
—
V
Input High Voltage Military
2.2
—
—
V
V
V
IH(1)
VIH(1)
IL(2)
TSTG
Storage
Temperature
–55 to + 125
–65 to +155
°C
V
Input Low Voltage
Commercial/Industrial/Military
—
—
0.8
V
I OUT
DC Output
+Current
–50 to +50
–50 to +50
mA
TA
Operating Temperature Commercial
0
—
70
°C
TA
Operating Temperature Industrial
–40
—
85
°C
TA
Operating Temperature Military
–55
—
125
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
For RT/RS/XI input, VIH = 2.6V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
2
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT7203(1)
IDT7204(1)
Commercial and Industrial
tA = 12, 15, 20, 25, 35, 50 ns
Symbol
Typ.
Max.
Min.
Max.
Unit
Input Leakage Current (Any Input)
–1
—
1
–1
—
1
μA
Output Leakage Current
–10
—
10
–10
—
10
μA
VOH
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(8,9,10)
Active Power Supply Current
—
—
120
—
—
150
mA
ICC2(8,10,11)
Standby Current (R=W=RS=FL/RT=VIH)
—
—
12
—
—
25
mA
Power Down Current
—
—
2
—
—
4
mA
ILI(6)
ILO
(7)
ICC3
(8,10,12)
Parameter
Min.
IDT7203
IDT7204
Military(3)
tA = 20, 30, 40 ns
Typ.
IDT7205
IDT7206(2,4)
IDT7207(2,4)
IDT7208(2,5)
Commercial and Industrial
tA = 12, 15, 20, 25, 35, 50 ns
IDT7205
IDT7206
IDT7207
(1)
Symbol
ILI
(6)
ILO
(7)
VOH
VOL
ICC1
(8,9,10)
ICC2(8,10,11)
ICC3
(8,10,12)
Parameter
Military
tA = 20, 30 ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Input Leakage Current (Any Input)
–1
—
1
–1
—
1
μA
Output Leakage Current
–10
—
10
–10
—
10
μA
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
Active Power Supply Current
—
—
120
—
—
150
mA
Standby Current (RS=FL/RT=VIH)
—
—
12
—
—
25
mA
Power Down Current
—
—
8
—
—
12
mA
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available
as a standard device.
2. Industrial temperature range product for 25ns speed grade only is available as a standard
device. All other speed grades are available by special order.
3. Military temperature range product for the 40ns is only available for 7203.
4. Commercial temperature range product for the 12ns not available.
5. Commercial temperature range product for the 12ns, 15ns and 50ns not available.
6. Measurements with 0.4 ≤ VIN ≤ VCC.
7. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
8. Tested with outputs open (IOUT = 0).
9. R and W toggle at 20 MHz and data inputs switch at 10 MHz.
10. ICC measurements are made with outputs open.
11. All Inputs = VCC - 0.2V or GND + 0.2V, except R and W, which toggle at 20MHz.
12. All Inputs = VCC - 0.2V or GND + 0.2V, except R and W = VCC -0.2V.
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
CAPACITANCE
(1)
Symbol
1.1KΩ
D.U.T.
680Ω
30pF*
(TA = +25°C, f = 1.0 MHz)
Parameter
Condition
Max.
Unit
(1)
CIN
Input Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output Capacitance
VOUT = 0V
10
pF
2661 drw03
or equivalent circuit
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
Figure 1. Output Load
*Includes jig and scope capacitances.
3
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
IDT7203L12
IDT7204L12
IDT7205L12
Symbol
fS
tRC
tA
tRR
tRPW
tRLZ
tWLZ
tDV
tRHZ
tWC
tWPW
tWR
tDS
tDH
tRSC
tRS
tRSS
tRTR
tRTC
tRT
tRTS
tRTR
tEFL
tHFH, tFFH
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
tXIR
tXIS
Parameters
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width(4)
Read LOW to Data Bus LOW(5)
Write HIGH to Data Bus Low-Z(5,6)
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z(5)
Write Cycle Time
Write Pulse Width(4)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width(4)
Reset Set-up Time(5)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width(4)
Retransmit Set-up Time(5)
Retransmit Recovery Time
Reset to EF LOW
Reset to HF and FF HIGH
Retransmit LOW to Flags Valid
Read LOW to EF LOW
Read HIGH to FF HIGH
Read Pulse Width after EF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF Flag LOW
Read HIGH to HF Flag HIGH
Write Pulse Width after FF HIGH
Read/Write LOW to XO LOW
Read/Write HIGH to XO HIGH
XI Pulse Width(4)
XI Recovery Time
XI Set-up Time
Min.
—
20
—
8
12
3
3
5
—
20
12
8
9
0
20
12
12
8
20
12
12
8
—
—
—
—
—
12
—
—
—
—
12
—
—
12
8
8
Max.
50
—
12
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
12
17
20
12
14
—
12
14
17
17
—
12
12
—
—
—
Com'l & Ind'l
IDT7203L15(2)
IDT7204L15(2)
IDT7205L15(2)
IDT7206L15
IDT7207L15
Min.
—
25
—
10
15
5
5
5
—
25
15
10
11
0
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
Max.
40
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
Com'l & Military
IDT7203L20
IDT7204L20
IDT7205L20
IDT7206L20
IDT7207L20
Min.
—
30
—
10
20
5
5
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
Max.
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
Commercial
IDT7208L20
Min.
—
30
—
10
20
5
5
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
Max.
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
Com'l & Ind'l
IDT7203L25(2)
IDT7204L25(2)
IDT7205L25(2)
IDT7206L25(3)
IDT7207L25(3)
IDT7208L25(3)
Min.
—
35
—
10
25
5
5
5
—
35
25
10
15
0
35
25
25
10
35
25
25
10
—
—
—
—
—
25
—
—
—
—
25
—
—
25
10
10
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.
3. Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order.
4. Pulse widths less than minimum are not allowed.
5. Values guaranteed by design, not currently tested.
6. Only applies to read data flow-through mode.
4
Max.
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
35
35
35
25
25
—
25
25
35
35
—
25
25
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (CONTINUED)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Military
IDT7203L30
IDT7204L30
IDT7205L30
IDT7206L30
IDT7207L30
Symbol
fS
tRC
tA
tRR
tRPW
tRLZ
tWLZ
tDV
tRHZ
tWC
tWPW
tWR
tDS
tDH
tRSC
tRS
tRSS
tRTR
tRTC
tRT
tRTS
tRTR
tEFL
tHFH, tFFH
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
tXIR
tXIS
Parameters
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width(2)
Read LOW to Data Bus LOW(3)
Write HIGH to Data Bus Low-Z(3,4)
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z(3)
Write Cycle Time
Write Pulse Width(2)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width(2)
Reset Set-up Time(3)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width(2)
Retransmit Set-up Time(3)
Retransmit Recovery Time
Reset to EF LOW
Reset to HF and FF HIGH
Retransmit LOW to Flags Valid
Read LOW to EF LOW
Read HIGH to FF HIGH
Read Pulse Width after EF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF Flag LOW
Read HIGH to HF Flag HIGH
Write Pulse Width after FF HIGH
Read/Write LOW to XO LOW
Read/Write HIGH to XO HIGH
XI Pulse Width(2)
XI Recovery Time
XI Set-up Time
Min.
—
40
—
10
30
5
5
5
—
40
30
10
18
0
40
30
30
10
40
30
30
10
—
—
—
—
—
30
—
—
—
—
30
—
—
30
10
10
Max.
25
—
30
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
30
30
—
30
30
40
40
—
30
30
—
—
—
Commercial
IDT7203L35
IDT7204L35
IDT7205L35
IDT7206L35
IDT7207L35
IDT7208L35
Min.
—
45
—
10
35
5
10
5
—
45
35
10
18
0
45
35
35
10
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
—
—
35
10
15
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5
Max.
22.22
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
45
45
45
30
30
—
30
30
45
45
—
35
35
—
—
—
Military
IDT7203L40
Min.
—
50
—
10
40
5
10
5
—
50
40
10
20
0
50
40
40
10
50
40
40
10
—
—
—
—
—
40
—
—
—
—
40
—
—
40
10
15
Max.
20
—
40
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
50
50
50
35
35
—
35
35
50
50
—
40
40
—
—
—
Commercial
IDT7203L50
IDT7204L50
IDT7205L50
IDT7206L50
IDT7207L50
Min.
—
65
—
15
50
10
15
5
—
65
50
15
30
5
65
50
50
15
65
50
50
15
—
—
—
—
—
50
—
—
—
—
50
—
—
50
10
15
Max.
15
—
50
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
65
65
65
45
45
—
45
45
65
65
—
50
50
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
SIGNAL DESCRIPTIONS
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
loaded (see Operating Modes). The Single Device Mode is initiated by grounding
the Expansion In (XI).
The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data
when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit
operation will set the internal read pointer to the first location and will not affect the
write pointer. The status of the Flags will change depending on the relative locations
of the read and write pointers. Read Enable (R) and Write Enable (W) must be
in the HIGH state during retransmit. This feature is useful when less than 2,048/
4,096/8,192/16,384/32,768/65,536 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion Mode.
INPUTS:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS ) — Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are set
to the first location. A reset is required after power-up before a write operation can
take place. Both the Read Enable (R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before
the rising edge of RS) and should not change until tRSR after the rising
edge of RS.
EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI)
is grounded to indicate an operation in the single device mode. Expansion In (XI)
is connected to Expansion Out (XO) of the previous device in the Depth Expansion
or Daisy-Chain Mode.
OUTPUTS:
WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this
input if the Full Flag (FF) is not set. Data set-up and hold times must be adheredto, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM
array sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference
between the write pointer and read pointer is less-than or equal to one-half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge
of the last write signal, which inhibits further write operations. Upon the completion
of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a
new valid write to begin. When the FIFO is full, the internal write pointer is blocked
from W, so external changes in W will not affect the FIFO when it is full.
FULL FLAG ( FF ) — The Full Flag (FF) will go LOW, inhibiting further write
operations, when the device is full. If the read pointer is not moved after Reset (RS),
the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536
writes.
EMPTY FLAG ( EF ) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer, indicating that
the device is empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF ) — This is a dual-purpose
output. In the single device mode, when Expansion In (XI) is grounded, this output
acts as an indication of a half-full memory.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse when the Write
pointer reaches the last location of memory, and an additional XO pulse when the
Read pointer reaches the last location of memory.
READ ENABLE ( R ) — A read cycle is initiated on the falling edge of the Read
Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on
a First-In/First-Out basis, independent of any ongoing write operations. After Read
Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a highimpedance condition until the next Read operation. When all the data has been
read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read
cycle but inhibiting further read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the
FIFO is empty, the internal read pointer is blocked from R so external changes will
not affect the FIFO when it is empty.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data.
These outputs are in a high-impedance condition whenever Read (R) is in a HIGH
state.
FIRST LOAD/RETRANSMIT ( FL/RT ) — This is a dual-purpose input. In
the Depth Expansion Mode, this pin is grounded to indicate that it is the first device
6
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
tRSC
tRS
RS
tRSS
tRSR
W
tRSS
R
tEFL
EF
tHFH, tFFH
HF, FF
2661 drw04
NOTE:
1. W and R = VIH around the rising edge of RS.
Figure 2. Reset
tRC
tRPW
tRR
tA
tA
R
tDV
tRLZ
Q0-Q8
tRHZ
DATA OUT VALID
DATA OUT VALID
tWC
W
tWR
tWPW
tDS
D0-D8
tDH
DATA IN VALID
DATA IN VALID
2661 drw05
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
R
W
tRFF
tWFF
FF
2661 drw06
Figure 4. Full Flag Timing From Last Write to First Read
7
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
LAST READ
W
IGNORED
READ
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
FIRST WRITE
R
tWEF
tREF
EF
tA
DATA OUT
VALID
2661 drw07
Figure 5. Empty Flag Timing From Last Read to First Write
RT
tRTC
tRT
tRTR
tRTS
W,R
tRTF
HF, EF, FF
FLAG VALID
2661 drw08
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
W
tWEF
EF
tRPE
R
2661 drw09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
tRFF
FF
tWPF
W
2661 drw10
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse.
8
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
W
R
tWHF
HF
tRHF
HALF-FULL OR LESS
HALF-FULL OR LESS
MORE THAN HALF-FULL
2661 drw11
Figure 9. Half-Full Flag Timing
W
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
R
tXOL
tXOL
tXOH
tXOH
XO
2661 drw12
Figure 10. Expansion Out
tXI
tXIR
XI
tXIS
W
WRITE TO
FIRST PHYSICAL
LOCATION
tXIS
READ FROM
FIRST PHYSICAL
LOCATION
R
2661 drw13
Figure 11. Expansion In
OPERATING MODES:
7204/7205/7206/7207/7208s. These devices operate in the Depth Expansion
mode when the following conditions are met:
Care must be taken to assure that the appropriate flag is monitored by
each system (i.e. FF is monitored on the device where W is used; EF is monitored
on the device where R is used). For additional information on the IDT7203/7204/
7205/7206/7207, refer to Tech Note 8: Operating FIFOs on Full and Empty
Boundary Conditions and Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7203/7204/7205/7206/7207/7208 may be used when the
application requirements are for 2,048/4,096/8,192/16,384/32,768/65,536 words
or less. These FIFOs are in a Single Device Configuration when the Expansion
In (XI) control input is grounded (see Figure 12).
Depth Expansion
These FIFOs can easily be adapted to applications when the requirements are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words.
Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/
7206/7207/7208s. Any depth can be attained by adding additional IDT7203/
1. The first device must be designated by grounding the First Load (FL) control
input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (FF) and Empty
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
the Depth Expansion Mode.
For additional information on the IDT7203/7204/7205/7206/7207, refer to
Tech Note 9: Cascading FIFOs or FIFO Modules.
9
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
USAGE MODES:
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing of
a single word of data immediately after reading one word of data from a full FIFO.
The R line causes the FF to be deasserted but the W line being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge of
W, the new word is loaded in the FIFO. The W line must be toggled when FF
is not asserted to write new data in the FIFO and to increment the write pointer.
Width Expansion
Word width may be increased simply by connecting the corresponding input
control signals of multiple devices. Status flags (EF, FF and HF) can be detected
from any one device. Figure 13 demonstrates an 18-bit word width by using
two IDT7203/7204/7205/7206/7207/7208s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Data Flow-Through
Two types of flow-through modes are permitted, a read flow-through and
write flow-through mode. For the read flow-through mode (Figure 17), the
(HALF-FULL FLAG)
WRITE (W)
(HF)
IDT
7203
7204
7205
7206
7207
7208
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
READ (R)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
2661 drw14
Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode
HF
18
HF
9
9
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
IDT
7203
7204
7205
7206
7207
7208
IDT
7203
7204
7205
7206
7207
7208
9
XI
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
9
XI
18
DATA
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
OUT (Q)
2661 drw15
Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode
10
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
TRUTH TABLES
TABLE 1 – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Mode
RS
Inputs
FL/RT
XI
0
1
1
X
0
1
0
0
0
Reset
Retransmit
Read/Write
Read Pointer
Internal Status
Write Pointer
Location Zero
Location Zero
Increment(1)
EF
Location Zero
Unchanged
Increment(1)
Outputs
FF
0
X
X
HF
1
X
X
1
X
X
NOTE:
1. Pointer will Increment if flag is HIGH.
TABLE 2 – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Mode
Reset First Device
Reset All Other Devices
Read/Write
RS
Inputs
FL/RT
XI
Read Pointer
0
0
1
0
1
X
(1)
(1)
(1)
Location Zero
Location Zero
X
Internal Status
Write Pointer
Outputs
Location Zero
Location Zero
X
EF
FF
0
0
X
1
1
X
NOTES:
1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XO
W
D
FF
9
9
IDT
7203
7204
7205
7206
7207
7208
R
EF
9
FL
Q
VCC
XI
XO
FF
FULL
9
IDT
7203
7204
7205
7206
7207
7208
EF
EMPTY
FL
XI
XO
FF
9
RS
IDT
7203
7204
7205
7206
7207
7208
EF
FL
XI
2661 drw16
Figure 14. Block Diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 FIFO Memory (Depth Expansion)
11
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Q0-Q8
Q9-Q17
Q(N-8)-QN
Q0-Q8
Q9-Q17
Q(N-8)-QN
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
R, W, RS
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
D0-D8
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
D9-D17
D(N-8)-DN
D0-DN
D9-DN
D18-DN
D(N-8)-DN
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13..
Figure 15. Compound FIFO Expansion
WA
FFA
IDT
7203
7204
IDT
7205
7201A
7206
7207
7208
RB
EFB
HFB
QB 0-8
DA 0-8
SYSTEM A
SYSTEM B
QA 0-8
RA
HFA
EFA
IDT
7203
7204
7205
7206
7207
7208
DB 0-8
WB
FFB
Figure 16. Bidirectional FIFO Operation
12
2661 drw18
2661 drw17
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
DATA IN
W
tRPE
R
EF
tWLZ
tWEF
tA
tREF
DATA OUT
DATA OUT VALID
2661 drw19
Figure 17. Read Data Flow-Through Mode
R
tWPF
W
tRFF
FF
tDH
tWFF
DATA
IN
DATA
tA
DATA
OUT
IN
VALID
tDS
DATA
OUT
VALID
Figure 18. Write Data Flow-Through Mode
13
2661 drw20
ORDERING INFORMATION
XXXX
X
Device Type Power
XX
X
Speed
Package
X
X
X
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (−40° to +85°C)
Military (−55°C to +125°C)
Compliant to MIL-STD-883, Class B
(4)
G
Green
P(5)
TP
D
TD
J
L(2)
SO
Plastic DIP
P28-1
Plastic Thin DIP
P28-2
CERDIP
D28-1
Thin CERDIP
D28-3
Plastic Leaded Chip Carrier PLCC J32-1
Leadless Chip Carrier
LCC
L32-1
Small Outline IC
SOIC SO28-3
12
15
20(3)
25(3)
30
35(3)
40
50
Commercial 7203/04/05 Only
Commercial and (Industrial only 7203/04/05)
Commercial and Military
Commercial and Industrial
Military Only
Commercial Only
Military 7203 Only
Commercial Only
L
Low Power
7203 ⎯
7204 ⎯
7205 ⎯
7206 ⎯
7207 ⎯
7208(3)
2,048 x9 FIFO
4,096 x 9 FIFO
8,192 x 9 FIFO
16,384 x 9 FIFO
32,768 x 9 FIFO
65,536 x 9 FIFO
(all except 7207/7208)
(all except 7208)
(only for 7203/7204/7205)
(all except 7208)
(only 7204)
Access Time (tA)
Speed in
Nanoseconds
2661 drw21
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device for IDT7203/7204/7205, and 25ns speed grade only is available
as a standard device for IDT7206/7207/7208. All other speed grades are available by special order.
2. The LCC is only available in the military temperature range.
3. The IDT7208 is only available in commercial speed grades of 20, 25 and 35 ns.
4. Green parts are available. For specific speeds and packages contact your local sales office.
5. For "P", Plastic Dip, when ordering green package, the suffix is "PDG".
DATA SHEET HISTORY
05/10/2001
05/30/2001
04/03/2006
10/22/2008
04/22/2010
06/29/2012
pgs.
pg.
pgs.
pg.
pgs.
pgs.
2, 3, 4, 5, 11 and 14.
2.
1 and 14.
14.
3, 4 and 14.
1 and 14.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
14
for Tech Support:
408-360-1753
email: FIFOhelp@idt.com