IDT 8305AGLF

ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
General Description
Features
The ICS8305 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™family of High
Performance Clock Solutions from IDT. The
ICS8305 has selectable clock inputs that accept
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
•
•
•
Four LVCMOS / LVTTL outputs, 7Ω output impedance
•
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
•
•
•
•
•
Maximum output frequency: 350MHz
•
•
0°C to 70°C ambient operating temperature
ICS
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
CLK_EN Pullup
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
D
Q
LE
LVCMOS_CLK Pulldown
00
CLK Pulldown
nCLK Pullup/
11
Q0
Pulldown
CLK_SEL Pullup
Q1
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
ICS8305
Q2
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
Q3
OE Pullup
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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2
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
2
OE
Input
3
VDD
Power
4
CLK_EN
Input
Pullup
5
CLK
Input
Pulldown
Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
7
CLK_SEL
Input
Pullup
8
LVCMOS_CLK
Input
Pulldown
10, 12, 14, 16
Q3, Q2, Q1, Q0
Output
Single-ended clock outputs. 7Ω output impedance.
LVCMOS/LVTTL interface levels.
11, 15
VDDO
Power
Output supply pins.
Power supply ground
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Power supply pin.
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
(per output)
11
pF
ROUT
Output Impedance
7
Ω
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Test Conditions
2
Minimum
Typical
Maximum
Units
ICS8305AG REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3. Control Input Function Table
Inputs
Outputs
OE
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
1
0
0
LVCMOS_CLK
Disabled; Low
1
0
1
CLK/nCLK
Disabled; Low
1
1
0
LVCMOS_CLK
Enabled
1
1
1
CLK/nCLK
Enabled
0
X
X
Hi-Z
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
Figure 1. CLK_EN Timing Diagram
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO+ 0.5V
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5% or 1.8V±0.5V or 1.5V±5%,
TA = 0°C to 70°C
Symbol
Parameter
VDD
Positive Supply Voltage
VDDO
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
1.65
1.8
1.95
V
1.425
1.5
1.575
V
Output Supply Voltage
IDD
Power Supply Current
21
mA
IDDO
Output Supply Current
5
mA
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4B. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High
Voltage
VIL
Input Low
Voltage
Input
High Current
CLK_EN, CLK_SEL, OE
IIH
LVCMOS_CLK
IIL
Input
Low Current
VOH
VOL
Test Conditions
Minimum
Typical
Maximum
Units
CLK_EN, CLK_SEL, OE
2
VDD + 0.3
V
LVCMOS_CLK
2
VDD + 0.3
V
CLK_EN, CLK_SEL, OE
-0.3
0.8
V
LVCMOS_CLK
-0.3
1.3
V
VDD = VIN = 3.465V
5
µA
VDD = VIN = 3.465V
150
µA
CLK_EN, CLK_SEL, OE
VDD = 3.465V, VIN = 0V
-150
µA
LVCMOS_CLK
VDD = 3.465V, VIN = 0V
-5
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 1.8V ± 0.15V
1.5
V
VDDO = 1.5V ± 5%
VDDO - 0.3
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOZL
Output Hi-Z Current Low
IOZH
Output Hi-Z Current High
VDDO = 3.3V ± 5%
0.5
V
VDDO = 2.5V ± 5%
0.5
V
VDDO = 1.8V ± 0.15V
0.4
V
VDDO = 1.5V ± 5%
0.35
V
-5
µA
5
µA
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Table 4C. Differential DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5
VDD – 0.85
V
nCLK
VDD = VIN = 3.465V
150
µA
CLK
VDD = VIN = 3.465V
150
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
CLK
VDD = 3.465V, VIN = 0V
-5
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Parameter
Symbol
Test Conditions
fMAX
Output Frequency
tpLH
Propagation
Delay,
Low to High
tsk(o)
Output Skew; NOTE 2, 6
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tR / tF
Output Rise/Fall Time; NOTE 4
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Minimum
Typical
1.75
Measured on the Rising Edge
Maximum
Units
350
MHz
2.75
ns
35
ps
700
ps
0.04
ps
20% to 80%
100
700
ps
Ref = CLK/nCLK
45
55
%
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
45
55
%
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
All parameters measured at ƒ ≤ 350MHz unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Parameter
Symbol
Test Conditions
fMAX
Output Frequency
tpLH
Propagation
Delay,
Low to High
tsk(o)
Output Skew; NOTE 2, 6
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
tDIS
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Minimum
Typical
1.8
Measured on the Rising Edge
Maximum
Units
350
MHz
2.9
ns
35
ps
800
ps
0.04
ps
20% to 80%
100
700
ps
Ref = CLK/nCLK
44
56
%
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
44
56
%
Output Enable Time; NOTE 4
5
ns
Output Disable Time; NOTE 4
5
ns
For NOTES, see Table 5A above.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C to 70°C
Parameter
Symbol
Test Conditions
fMAX
Output Frequency
tpLH
Propagation
Delay,
Low to High
tsk(o)
Output Skew; NOTE 2, 6
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tR / tF
Output Rise/Fall Time; NOTE 4
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Minimum
Typical
1.95
Measured on the Rising Edge
Maximum
Units
350
MHz
3.65
ns
35
ps
900
ps
0.04
ps
20% to 80%
100
700
ps
Ref = CLK/nCLK
44
56
%
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
44
56
%
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
All parameters measured at ƒ ≤ 350MHz unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V ± 5%, TA = 0°C to 70°C
Parameter
Symbol
Test Conditions
fMAX
Output Frequency
tpLH
Propagation
Delay,
Low to High
tsk(o)
Output Skew; NOTE 2, 6
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
tDIS
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Minimum
Typical
2
Measured on the Rising Edge
Maximum
Units
350
MHz
4
ns
35
ps
1
ns
0.04
ps
20% to 80%
200
900
ps
ƒ ≤ 166MHz
45
55
%
ƒ > 166MHz
42
58
%
Output Enable Time; NOTE 4
5
ns
Output Disable Time; NOTE 4
5
ns
For NOTES, see Table 5C above.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter at 155.52MHz
= 0.04ps (typical)
-10
-20
-30
-40
-50
-60
SSB Phase Noise dBc/Hz
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD
VDDO
Qx
LVCMOS
Qx
GND
LVCMOS
CL ≤ 25pF*
*For tR/tF measurement only
-1.65V±5%
-1.25V±5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.4V±0.09V
2.55V±5%
0.9V±0.075V
0.75V±5%
SCOPE
VDD
VDDO
SCOPE
VDD
VDDO
Qx
GND
Qx
GND
LVCMOS
LVCMOS
-0.9V±0.075V
-0.9V±0.75V
3.3V Core/1.5V LVCMOS Output Load AC Test Circuit
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
VDD
VCCO
2
Qx
nCLK
V
PP
Cross Points
V
CMR
VCCO
2
CLK
Qy
tsk(b)
GND
Differential Input Level
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Output Skew
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information, continued
V
Part 1
DDO
V
DDO
Qx
2
Q0:Q3
t PW
2
t
PERIOD
Part 2
V
DDO
Qy
2
tsk(pp)
t PW
odc =
x 100%
t PERIOD
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
LVCMOS_CLK
80%
80%
VDDO
2
nCLK
CLK
Clock
Outputs
20%
20%
tR
tF
VDDO
2
Q0:Q3
➤
Output Rise/Fall Time
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
tPD
➤
Propagation Delay
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS_CLK Input
LVCMOS Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK input to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Schematic Example
This application note provides general design guide using
ICS8305 LVCMOS buffer. Figure 4 shows a schematic example of
the ICS8305 LVCMOS clock buffer. In this example, the input is
driven by an LVCMOS driver. CLK_EN is set at logic low to select
LVCMOS_CLK input.
VDD
VDD
R4
1K
R5
1K
1
2
3
4
5
6
7
8
Zo = 50
R3
3,.3V LVCMOS
43
R6
1K
Zo = 50
43
U1
VDD
Ro ~ 7 Ohm
R1
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
ICS8305
16
15
14
13
12
11
10
9
LVCMOS Receiv er
R2
43
(U1,3)
VDD=3.3V
Zo = 50
(U1,11)
(U1,15)
C1
C2
C3
0.1u
0.1u
0.1u
VDD
LVCMOS Receiv er
Figure 4. ICS8305 LVCMOS Clock Output Buffer Schematic Example
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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Reliability Information
Table 6. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
118.2°C/W
106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0°C/W
81.8°C/W
78.1°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8305: 459
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 8. Ordering Information
Part/Order Number
8305AG
8305AGT
8305AGLF
8305AGLFT
Marking
8305AG
8305AG
8305AGLF
8305AGLF
Package
16 Lead TSSOP
16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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Revision History Sheet
Rev
A
B
B
C
C
Table
Page
T8
14
T5A - T5C
5&6
7
T1
T4A
T4B
T5D
Description of Change
Date
Ordering Information table - corrected Part/Order Number typo from
ICS88305AGT to ICS8305AGT.
1/20/04
Added Additive Phase Jitter to AC Characteristics Tables.
Added Additive Phase Jitter Section.
2/26/04
2
Pin Description Table - corrected CLK_EN description.
12/6/04
1
Features Section - added 1.5V output to Supply Mode bullet and
added Lead-Free buttlet.
Power Supply DC Characteristics Table - added VDDO 1.5V.
LVCMOS DC Characteristics Table - added VOH/VOL 1.5V.
Added 3.3V/1.5V AC Characteristics Table.
Added 3.3V/1.5V Output Load AC Test Circuit Drawing.
Added Recommendations for Unused Input and Output Pins.
Added Lead-Free part number.
11/17/05
Ordering Information Table - added lead-free marking.
Corrected non-lead free marking from ICS8305AG to 8305AG.
2/22/08
T8
4
4
7
10
11
16
T8
15
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