Si8902EDB www.vishay.com Vishay Siliconix Bi-Directional N-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VS1S2 (V) 20 IS1S2 (A) 0.045 at VGS = 4.5 V 5.0 • Ultra-low RSS(on) 0.048 at VGS = 3.7 V 4.8 • ESD protected: 4000 V 0.057 at VGS = 2.5 V 4.4 0.072 at VGS = 1.8 V 3.9 • MICRO FOOT® chipscale packaging reduces footprint area profile (0.62 mm) and on-resistance per footprint area • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 MICRO FOOT® 2.4 x 1.6 S 1 S2 4 2E 890 xx x 1. 6 m m 1 • TrenchFET® power MOSFET RS1S2(on) (Ω) 2.4 G1 3 2 APPLICATIONS 6 G2 mm • Battery protection circuit - 1-2 cell Li+/LiP battery pack for portable devices 1 S1 S1 5 S2 Bump Side View Backside View Marking Code: xxxx = 8902E G1 Ordering Information: Si8902EDB-T2-E1 (Lead (Pb)-free and halogen-free) 4 k 4 k G2 N-Channel S2 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL Source1- Source2 Voltage Gate-Source Voltage Continuous Source1- Source2 Current (TJ = 150 °C) a TA = 25 °C TA = 85 °C Pulsed Source1- Source2 Current Maximum Power Dissipation a STEADY STATE 20 VGS ± 12 IS1S2 TA = 25 °C TA = 85 °C PD TJ, Tstg UNIT V 5 3.9 3.4 2.8 ISM Operating Junction and Storage Temperature Range Package Reflow Conditions c 5s VS1S2 A 40 1.7 1 0.8 0.5 -55 to +150 IR/Convection W °C 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL Maximum Junction-to-Ambient a Maximum Junction-to-Foot b t≤5s Steady State Steady State RthJA RthJF TYPICAL MAXIMUM 60 75 95 120 18 22 UNIT °C/W Notes a. Surface mounted on 1" x 1" FR4 board. b. The foot is defined as the top surface of the package. c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering. S15-1171-Rev. J, 25-May-15 Document Number: 71862 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8902EDB www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Gate Threshold Voltage VGS(th) Gate-Body Leakage IGSS Zero Gate Voltage Source Current IS1S2 On-State Source Current a IS(on) Source1-Source2 On State Resistance a Forward Transconductance a RS1S2(on) gfs VSS = VGS, ID = 980 μA 0.45 - 1 V VSS = 0 V, VGS = ± 4.5 V - - ±4 μA VSS = 0 V, VGS = ± 12 V - - ± 10 mA VSS = 20 V, VGS = 0 V - - 1 VSS = 20 V, VGS = 0 V, TJ = 85 °C - - 5 VSS = 5 V, VGS = 4.5 V 5 - - VGS = 4.5 V, ISS = 1 A - 0.038 0.045 VGS = 3.7 V, ISS = 1 A - 0.041 0.048 VGS = 2.5 V, ISS = 1 A - 0.048 0.057 VGS = 1.8 V, ISS = 1 A - 0.060 0.072 VSS = 10 V, ISS = 1 A - 20 - - 1 1.5 VSS = 10 V, RL = 10 Ω ISS ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω - 3 4.5 - 17 26 - 10 15 μA A Ω S Dynamic b Turn-On Delay Time td(on) Rise Time tr Turn-Off Delay Time td(off) Fall Time tf μs Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 10 000 1000 I GSS - Gate Current (µA) I GSS - Gate Current (mA) IGSS at 25 °C (mA) 16 12 8 4 100 TJ = 150 °C 10 1 TJ = 25 °C 0.1 0 0.01 0 3 6 9 12 VGS - Gate-to-Source Voltage (V) Gate-Current vs. Gate-Source Voltage S15-1171-Rev. J, 25-May-15 15 0 3 6 9 12 15 VGS - Gate-to-Source Voltage (V) Gate Current vs. Gate-Source Voltage Document Number: 71862 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8902EDB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 10 VGS = 5 thru 1.5 V 8 I D - Drain Current (A) ID - Drain Current (A) 8 6 4 2 6 4 TC = 125 °C 2 1V 25 °C - 55 °C 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 0.4 0.6 0.8 1.0 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 1.2 1.4 125 150 1.6 RDS(on) - On-Resistance (Normalized) 0.10 RDS(on) - On-Resistance ( ) 0.2 VDS - Drain-to-Source Voltage (V) 0.08 VGS = 1.8 V 0.06 VGS = 2.5 V 0.04 VGS = 4.5 V VGS = 3.7 V 0.02 2 4 6 ID - Drain Current (A) 8 1.4 1.2 1.0 0.8 0.6 - 50 0.00 0 VGS = 4.5 V IS1S2 = 1 A 10 - 25 0 25 50 75 100 TJ - Junction Temperature (°C) On-Resistance vs. Drain Current On-Resistance vs. Junction Temperature 0.2 0.10 0.1 0.08 IS1S2 = 980 µA V GS(th) Variance (V) R DS(on) - On-Resistance ( ) IS1S2 = 5 A IS1S2 = 1 A 0.06 0.04 0.02 0.0 - 0.1 - 0.2 - 0.3 0.00 0 1 2 3 4 VGS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage S15-1171-Rev. J, 25-May-15 5 - 0.4 - 50 - 25 0 25 50 75 100 125 150 TJ - Temperature (°C) Threshold Voltage Document Number: 71862 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8902EDB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 30 IDM Limited Limited by R DS(on) * 25 0.0001 s I D - Drain Current (A) 10 Power (W) 20 15 10 0.001 s 1 0.01 s ID(on) Limited 0.1 s 0.1 5 1s 10 s DC TA = 25 °C Single Pulse BVDSS Limited 0 0.01 0.1 1 10 100 1000 0.01 0.1 Time (s) Single Pulse Power, Junction-to-Ambient 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum V GS at which RDS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 2. t1 t2 PER UNIT BASE = RTHJA = 95 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10- 4 10- 3 10- 2 10- 1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient S15-1171-Rev. J, 25-May-15 Document Number: 71862 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8902EDB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71862. S15-1171-Rev. J, 25-May-15 Document Number: 71862 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix MICRO FOOT®: 6-Bumps (1.6 mm x 2.4 mm, 0.8 mm Pitch, 0.290 mm Bump Height) E 6x Ø b1 Mark on backside of die e e S2 G1 S1 S2 G2 S1 D e XXXXXX XXX S S b1 Note 5 6x 0.30 to 0.31 (Note 3) Solder mask-0.4 Note 2 A1 A e A2 b K e b Diameter bump (Note 1) e Recommended land pattern Notes 1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2. Backside surface is coated with a Ti/Ni/Ag layer. 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back. 5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. 6. • is the location of pin 1 DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.550 0.575 0.600 0.0217 0.0226 0.0236 A1 0.260 0.275 0.290 0.0102 0.0108 0.0114 A2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.370 0.390 0.410 0.0146 0.0153 0.0161 b1 0.300 e 0.0118 0.800 0.0314 s 0.360 0.380 0.400 0.0141 0.0150 D 1.520 1.560 1.600 0.0598 0.0614 0.0157 0.0630 E 2.320 2.360 2.400 0.0913 0.0929 0.0945 K 0.155 0.185 0.215 0.0061 0.0072 0.0084 Note • Use millimeters as the primary measurement. ECN: T15-0143-Rev. A, 27-Apr-15 DWG: 6036 Revision: 27-Apr-15 1 Document Number: 69350 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 AN824 Vishay Siliconix PCB Design and Assembly Guidelines For MICRO FOOTr Products Johnson Zhao INTRODUCTION Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. For example, the 6−bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same performance as TSSOP−8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A MICRO FOOT analog switch, the 6−bump DG3000DB, offers low charge injection and 1.4 W on−resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). Vishay Siliconix MICRO FOOT products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable performance without underfill. The advantage of the device’s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, PDAs, cellular phones, and notebook computers. This application note discusses the mechanical design and reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework process. FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and Si8900EDB 3 2 1 0.18 ~ 0.25 A 1.08 0.5 B 0.285 0.285 0.5 1.58 FIGURE 2. Outline of MICRO FOOT CSP & Analog Switch DG3000DB Document Number: 71990 06-Jan-03 www.vishay.com 1 AN824 Vishay Siliconix TABLE 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Main Parameters of Solder Bumps in MICRO FOOT Designs MICRO FOOT CSP Bump Material MICRO FOOT CSP MOSFET Eutectic Solder: 63Sm/37Pb MICRO FOOT CSP Analog Switch MICRO FOOT UCSP Analog Switch Bump Pitch* Bump Diameter* Bump Height* 0.8 0.37-0.41 0.26-0.29 0.5 0.18-0.25 0.14-0.19 0.5 0.32-0.34 0.21-0.24 * All measurements in millimeters MICRO FOOT’S DESIGN AND RELIABILITY BOARD LAYOUT GUIDELINES As a mechanical, electrical, and thermal connection between the device and PCB, the solder bumps of MICRO FOOT products are mounted on the top active surface of the die. Table 1 shows the main parameters for solder bumps used in MICRO FOOT products. A silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. A green laser is used to mark the backside of the die without damaging it. Reliability results for MICRO FOOT products mounted on a FR-4 board without underfill are shown in Table 2. Board materials. Vishay Siliconix MICRO FOOT products are designed to be reliable on most board types, including organic boards such as FR-4 or polyamide boards. The package qualification information is based on the test on 0.5-oz. FR-4 and polyamide boards with NSMD pad design. TABLE 2 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ MICRO FOOT Reliability Results Test Condition C: −65_ to 150_C >500 Cycles Test condition B: −40_ to 125_C >1000 Cycles 121_C @ 15PSI 100% Humidity Test 96 Hours The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results shown in Table 2 demonstrate that a high level of reliability can be achieved with proper board design and assembly techniques. Land patterns. Two types of land patterns are used for surface-mount packages. Solder mask defined (SMD) pads have a solder mask opening smaller than the metal pad (Figure 3), whereas on-solder mask defined (NSMD) pads have a metal pad smaller than the solder-mask opening (Figure 4). NSMD is recommended for copper etch processes, since it provides a higher level of control compared to SMD etch processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the PCB. By contrast, SMD pad definition introduces a stress concentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. Copper pads should be finished with an organic solderability preservative (OSP) coating. For electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 mm to avoid solder joint embrittlement. Solder Mask Copper Copper FIGURE 3. SMD www.vishay.com 2 Solder Mask FIGURE 4. NSMD Document Number: 71990 06-Jan-03 AN824 Vishay Siliconix TABLE 3 Dimensions of Copper Pad and Solder Mask Opening in PCB and Stencil Aperture ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Pitch Copper Pad Solder Mask Opening Stencil Aperture 0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm 0.33 " 0.01 mm in ciircle aperture 0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm 0.30 " 0.01 mm in square aperture ASSEMBLY PROCESS MICRO FOOT products’ surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (Figure 5). Chip pick-and-placement. MICRO FOOT products can be picked and placed with standard pick-and-place equipment. The recommended pick-and-place force is 150 g. Though the part will self-center during solder reflow, the maximum placement offset is 0.02 mm. Reflow Process. MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other package, the thermal profile at specific board locations must be determined. Nitrogen purge is recommended during reflow operation. Figure 6 shows a typical reflow profile. Thermal Profile 250 200 Temperature (_C) Board pad design. The landing-pad size for MICRO FOOT products is determined by the bump pitch as shown in Table 3. The pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. 150 100 50 Stencil Design IIncoming Tape and Reel Inspection 0 0 Solder Paste Printing 100 200 300 400 Time (Seconds Chip Placement FIGURE 6. Reflow Profile Reflow Solder Joint Inspection Pack and Ship FIGURE 5. SMT Assembly Process Flow PCB REWORK To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 1. Stencil design. Stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). The stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. Remove the MICRO FOOT device using a convection nozzle to create localized heating similar to the original reflow profile. Preheat from the bottom. 2. Once the nozzle temperature is +190_C, use tweezers to remove the part to be replaced. 3. In MICRO FOOT products, the stencil is 0.125-mm (5-mils) thick. The recommended apertures are shown in Table 3 and are fabricated by laser cut. Resurface the pads using a temperature-controlled soldering iron. 4. Apply gel flux to the pad. 5. Use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 6. Reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile. Solder-paste printing. The solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. In MICRO FOOT products, the solder paste used is UP78 No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. Document Number: 71990 06-Jan-03 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000