PRELIMINARY ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION General Description Features The ICS889872 is a high speed Differential-toLVDS Buffer/Divider w/Internal Termination and is a HiPerClockS™ member of the HiPerClockS™family of high performance clock solutions from IDT. The ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. • • Three LVDS outputs • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML • • • • • • • • • Output frequency: >2GHz ICS Frequency divide select options: ÷4, ÷6: >2GHz, ÷8, ÷16: >1.6GHz Cycle-to-cycle jitter: 1ps (typical) Total jitter: 10ps (typical) Output skew: 7ps (typical), QA/nQA outputs Part-to-part skew: 250ps (typical) Propagation Delay: 750ps (typical), QA/nQA outputs Full 2.5V supply mode -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 16 15 14 13 12 IN 2 11 VT QB1 3 QA ÷2, ÷4, ÷8, ÷16 VT 50Ω nIN QA nQA 7 8 VDD 6 nQB0 ICS889872 QB1 VREF_AC 9 nIN 5 nRESET/ nDISABLE QB0 50Ω 10 VREF_AC nQB1 4 nQA IN VDD QB0 1 nQB0 Enable MUX GND S0 Enable FF nRESET/ nDISABLE S1 Pin Assignment Block Diagram 16-Lead VFQFN 3mm x 3mm x 0.95mm package body K Package Top View nQB1 S1 Decoder S0 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 1 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Table 1. Pin Descriptions Number Name Type 1, 2 QB0, nQB0 Output Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100W across the pin (QB0/nQB0). LVDS interface levels. 3, 4 QB1, nQB1 Output Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100W across the pin (QB1nQB1). LVDS interface levels. 5, 6 QA, nQA Output Differential undivided output pair. LVDS interface levels. 7, 14 VDD Power Power supply pins. 8 nRESET/ nDISABLE Input Output reset and enable/disable pin. When LOW, resets the divider select, and align Bank A and Bank B edges. In addition, when LOW, Bank A and Bank B will be disabled. Input threshold is VDD/2V. Includes a 37kΩ pullup resistor. LVTTL / LVCMOS interface levels. 9 nIN Input Pullup Description Inverting differential LVPECL clock input. RT = 50Ω termination to VT. Reference voltage for AC-coupled applications. Equal to VDD – 1.4V (approx.). Maximum sink/source current is 0.5mA. 10 VREF_AC Output 11 VT Input Termination input. Leave pin floating. 12 IN Input Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT. 13 GND Power Power supply ground. 15, 16 S1, S0 Input Pullup Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB. Input threshold is VDD/2. 37kW pullup resistor. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLUP Input Pullup Resistor Test Conditions IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Minimum Typical 37 2 Maximum Units kΩ ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Function Tables Table 3A. Control Input Function Table Input Outputs nRESET QA, QBx nQA, nQBx 0 Disabled; LOW Disabled; HIGH 1 Enabled Enabled NOTE: After nRESET switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. Figure 1. nRESET Timing Diagram VDD/2 nRESET tRR IN nIN VIN Swing tPD nQBx VOUT Swing QBx QA nQA Table 3B. Truth Table Inputs Outputs nRESET/nDISABLE S1 S0 Bank A Bank B 1 0 0 Input Clock Input Clock ÷2 1 0 1 Input Clock Input Clock ÷4 1 1 0 Input Clock Input Clock ÷8 1 1 1 Input Clock Input Clock ÷16 0 X X QA = LOW, nQA = HIGH; NOTE 1 QBx = LOW, nQBx = HIGH; NOTE 2 NOTE 1: On the next negative transition of the input signal. NOTE 2: Asynchronous reset/disable function.Absolute Maximum Ratings IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 3 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA, (Junction-to-Ambient) 51.5°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Positive Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 80 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 2.625V IIL Input Low Current VDD = 2.625V, VIN = 0V IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Minimum Maximum Units 2 VDD + 0.3 V 0 0.8 V 5 µA -150 4 Typical µA ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Table 4C. Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units RIN Differential Input Resistance (IN, nIN) VIH Input High Voltage (IN, nIN) 1.2 VDD V VIL Input Low Voltage (IN, nIN) 0 VDD – 0.15 V VIN Input Voltage Swing 0.15 2.8 V VDIFF_IN Differential Input Voltage Swing 0.3 IIN Input Current VREF_AC Bias Voltage Ω 100 V (IN, nIN) 45 VDD – 1.35 mA V Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VOUT Output Voltage Swing VOH Output High Voltage VOL Output Low Voltage VCCM Output Common Mode Voltage ∆VOCM Change in Common Mode Voltage Minimum Typical Maximum Units 350 mV 1.475 V 0.925 V 1.35 V 50 mV AC Electrical Characteristics Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Parameter fMAX tPD Symbol Test Conditions Minimum Typical Maximum Units Output Frequency ÷2, ÷4 >2 GHz Input Frequency ÷8, ÷16 >1.6 GHz Input Swing: <400mV 750 ps Input Swing: ≥400mV Propagation Delay; NOTE 1, 2 IN-to-Q 750 ps QB0-to-QB1 7 ps QA-to-QB 60 ps 250 ps tsk(o) Output Skew; NOTE 2, 3, 4 tsk(pp) Part-to-Part Skew; NOTE 2, 4, 5 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 6 1 ps tjit(j) Total Jitter; NOTE 2 10 ps tRR Reset Recovery Time; NOTE 2 tR / tF Output Rise/Fall Time; NOTE 2 600 ps 150 ps All parameters characterized at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Specs are design targets. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 5 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Parameter Measurement Information VDD , SCOPE 2.5V±5% POWER SUPPLY + Float GND – nIN Qx VDD V LVDS Cross Points IN V IH IN nQx V IL GND Differential Input Level LVDS Output Load AC Test Circuit nQx Par t 1 nQx Qx Qx nQy Qy Par t 1 Qy Qy tsk(o) tsk(pp) Output Skew Part-to-Part Skew nQA, nQB[0:1] nIN IN QA, QB[0:1] ➤ tcycle n ➤ tcycle n+1 nQA, nQB[0:1] ➤ ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles QA, QB[0:1] Cycle-to-Cycle Jitter IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION tPD Propagation Delay 6 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Parameter Measurement Information, continued 80% 80% VDIFF_IN, VDIFF_OUT VIN, VOUT VOD 1600mV (typical) Clock Outputs 800mV (typical) Single-Ended & Differential Input Voltage Swing 20% 20% tF tR Output Rise/Fall Time Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input IN V_REF nIN C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 7 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Differential Input with Built-in 50Ω Termination Interface The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V 3.3V or 2.5V Zo = 50Ω Zo = 50Ω IN IN VT Zo = 50Ω VT Zo = 50Ω nIN nIN Receiver LVDS Receiver LVPECL With With R1 18 Built-In Built-In 50Ω 50Ω Figure 3A. HiPerClockS IN/nIN Input with Built-In 50Ω Driven by an LVDS Driver 2.5V Figure 3B. HiPerClockS IN/nIN Input with Built-In 50Ω Driven by an LVPECL Driver 2.5V 2.5V 3.3V 3.3V LVPECL Zo = 50Ω Zo = 50Ω C1 IN IN 50Ω VT VT Zo = 50Ω Zo = 50Ω C2 50Ω nIN nIN Receiver REF_AC With CML - Built-in 50Ω Pull-up R5 100 - 200Ω Built-In R5 100 - 200Ω Receiver with Built-In 50Ω 50Ω Figure 3C. HiPerClockS IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Built-In 50Ω Pullup Figure 3D. HiPerClockS IN/nIN Input with Built-In 50Ω Driven by an SSTL Driver 2.5V 3.3V 3.3V CML with Built-In Pullup Zo = 50Ω C1 IN 50Ω VT Zo = 50Ω C2 50Ω nIN REF_AC Receiver with Built-In 50Ω Figure 3E. HiPerClockS IN/nIN Input with Built-In 50Ω Driven by a 3.3V CML Driver with Built-In Pullup IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 8 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Recommendations for Unused Input Pins Inputs: OUTputs: LVCMOS Select Pins LVDS Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. EPAD Thermal Release Path The EPAD provides heat transfer from the device to the P.C. board. The exposed metal pad on the PCB is connected to the ground plane through thermal vias. To guarantee the device’s electrical and thermal performance, EPAD must be soldered to the exposed PIN PIN PAD SOLDER metal pad on the PCB, as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. SOLDER EPAD GROUND PLANE PIN EXPOSED METAL PAD THERMAL VIA PIN PAD (GROUND PAD) Figure 4. P.C. Board for Exposed Pad Thermal Release Path Example IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 9 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY 2.5V LVDS Driver Termination Figure 5 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V 50Ω 2.5V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 10 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Power Considerations This section provides information on power dissipation and junction temperature for the ICS889872. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. • Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 80mA = 210mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.210W * 51.5°C/W = 95.8°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection θJA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 0 51.5°C/W 11 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Reliability Information Table 7. θJA vs. Air Flow Table for a 16 Lead VFQFN θJA by Velocity Linear Feet per Minute 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W Transistor Count The transistor count for ICS889872 is: 323 Pin compatible with SY89872U Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e N &N Odd 0. 08 C D2 2 Th er mal Ba se D2 C Table 8. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 12 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Ordering Information Table 9. Ordering Information Part/Order Number ICS889872AK ICS889872AKT ICS889872AKLF ICS889872AKLFT Marking 872A 872A TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 13 ICS889872AK REV. A AUGUST 22, 2007 ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 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